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[nrf fromlist] soc: nordic: add IRONside SE compatible UICR support
Upstream PR #: 91005 Add support for generating UICR and associated artifacts in a format compatible with IRONside SE, to be used for nRF SoCs in the Haltium family. The main feature added with this is the ability to configure certain global domain peripherals that are managed by the secure domain through setting UICR.PERIPHCONF. This register points at a blob of (register address, register value) pairs which are loaded into the peripherals by IRONside SE ahead of the application boot. The added helper macros in uicr.h can be used to add register configurations to the PERIPHCONF. Entries added through these macros are then extracted by a script, post-processed and placed in a blob located at specific part of MRAM. A default PERIPHCONF configuration has been added for the nrf54h20 soc to support the standard BLE use case. Signed-off-by: Jonathan Nilsen <[email protected]>
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‎boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map_iron.dtsi‎

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storage_partition: partition@1a8000 {
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reg = <0x1a8000 DT_SIZE_K(40)>;
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};
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periphconf_partition: partition@1b2000 {
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reg = <0x1b2000 DT_SIZE_K(8)>;
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};
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};
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};

‎boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts‎

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@@ -35,3 +35,5 @@ slot0_partition: &cpuapp_slot0_partition {
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slot1_partition: &cpuapp_slot1_partition {
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label = "image-1";
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};
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uicr: &cpuapp_uicr {};

‎soc/nordic/common/CMakeLists.txt‎

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@@ -3,6 +3,10 @@
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add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr)
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if(CONFIG_NRF_PERIPHCONF_SECTION OR CONFIG_NRF_HALTIUM_GENERATE_UICR)
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add_subdirectory(uicr)
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endif()
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# Let SystemInit() be called in place of soc_reset_hook() by default.
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zephyr_linker_symbol(SYMBOL soc_reset_hook EXPR "@SystemInit@")
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‎soc/nordic/common/Kconfig‎

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@@ -49,3 +49,4 @@ source "subsys/logging/Kconfig.template.log_config"
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endif # MRAM_LATENCY
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rsource "vpr/Kconfig"
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rsource "uicr/Kconfig"

‎soc/nordic/common/uicr/CMakeLists.txt‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if(CONFIG_NRF_PERIPHCONF_SECTION)
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zephyr_linker_sources(SECTIONS uicr.ld)
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endif()
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if(CONFIG_NRF_HALTIUM_GENERATE_UICR)
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set(uicr_hex_file ${PROJECT_BINARY_DIR}/uicr.hex)
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set(periphconf_hex_file ${PROJECT_BINARY_DIR}/periphconf.hex)
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if(CONFIG_NRF_HALTIUM_UICR_PERIPHCONF)
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set(in_periphconf_elf_arg
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--in-periphconf-elf $<TARGET_FILE:${ZEPHYR_LINK_STAGE_EXECUTABLE}>
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)
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endif()
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set(uicrgen_command
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${CMAKE_COMMAND} -E env PYTHONPATH=${ZEPHYR_BASE}/scripts/dts/python-devicetree/src
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${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_LIST_DIR}/uicrgen.py
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--in-config ${DOTCONFIG}
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--in-edt-pickle ${EDT_PICKLE}
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${in_periphconf_elf_arg}
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--out-uicr-hex ${uicr_hex_file}
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--out-periphconf-hex ${periphconf_hex_file}
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)
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set_property(
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GLOBAL APPEND
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PROPERTY extra_post_build_commands COMMAND ${uicrgen_command}
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)
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set_property(
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GLOBAL APPEND
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PROPERTY extra_post_build_byproducts ${uicr_hex_file} ${periphconf_hex_file}
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)
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endif()

‎soc/nordic/common/uicr/Kconfig‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config NRF_HALTIUM_GENERATE_UICR
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bool "Generate UICR file"
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depends on SOC_NRF54H20_CPUAPP
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depends on SOC_NRF54H20_IRON
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default y
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help
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Generate UICR HEX file.
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if NRF_HALTIUM_GENERATE_UICR
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config NRF_HALTIUM_UICR_PERIPHCONF
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bool "Initialize global domain peripherals"
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default y
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depends on NRF_PERIPHCONF_SECTION
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help
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Generates a blob containing static global domain peripheral initialization
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values extracted from the build artifacts, and configures UICR.PERIPHCONF
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to point at the blob. The initialization values are then loaded ahead of
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ahead of the application boot.
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endif
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config NRF_PERIPHCONF_SECTION
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bool "Populate global peripheral initialization section"
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default y if SOC_NRF54H20_CPUAPP
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depends on SOC_NRF54H20_IRON
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depends on LINKER_DEVNULL_SUPPORT
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imply LINKER_DEVNULL_MEMORY
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help
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Include static global domain peripheral initialization values from the
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build in a dedicated section in the devnull region.

‎soc/nordic/common/uicr/uicr.h‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SOC_NORDIC_COMMON_UICR_UICR_H_
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#define SOC_NORDIC_COMMON_UICR_UICR_H_
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#include <stdint.h>
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#include <nrfx.h>
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#include <zephyr/sys/iterable_sections.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/toolchain.h>
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/** Entry in the PERIPHCONF table. */
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struct uicr_periphconf_entry {
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/** Register pointer. */
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uint32_t regptr;
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/** Register value. */
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uint32_t value;
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} __packed;
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/** @brief Add an entry to the PERIPHCONF table section.
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*
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* This should typically not be used directly.
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* Prefer to use one of the higher level macros.
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*/
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#define UICR_PERIPHCONF_ADD(_regptr, _value) \
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static STRUCT_SECTION_ITERABLE(uicr_periphconf_entry, \
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_UICR_PERIPHCONF_ENTRY_NAME(__COUNTER__)) = { \
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.regptr = (_regptr), \
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.value = (_value), \
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}
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#define _UICR_PERIPHCONF_ENTRY_NAME(_id) __UICR_PERIPHCONF_ENTRY_NAME(_id)
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#define __UICR_PERIPHCONF_ENTRY_NAME(_id) _uicr_periphconf_entry_##_id
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/** @brief Add a PERIPHCONF entry for configuring a SPU PERIPH[n].PERM register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Register index.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _dmasec If true, set DMASEC to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_PERIPH_PERM_SET(_spu, _index, _secattr, _dmasec, _ownerid) \
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UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->PERIPH[(_index)].PERM, \
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(uint32_t)((((_ownerid) << SPU_PERIPH_PERM_OWNERID_Pos) & \
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SPU_PERIPH_PERM_OWNERID_Msk) | \
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(((_secattr) ? SPU_PERIPH_PERM_SECATTR_Secure \
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: SPU_PERIPH_PERM_SECATTR_NonSecure) \
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<< SPU_PERIPH_PERM_SECATTR_Pos) | \
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(((_dmasec) ? SPU_PERIPH_PERM_DMASEC_Secure \
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: SPU_PERIPH_PERM_DMASEC_NonSecure) \
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<< SPU_PERIPH_PERM_DMASEC_Pos) | \
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(SPU_PERIPH_PERM_LOCK_Locked << SPU_PERIPH_PERM_LOCK_Pos)))
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/** @brief Add a PERIPHCONF entry for a SPU FEATURE.IPCT.CH[n] register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Feature index.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_FEATURE_IPCT_CH_SET(_spu, _index, _secattr, _ownerid) \
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UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.IPCT.CH[_index], \
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_UICR_SPU_FEATURE_VAL(_secattr, _ownerid))
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/** @brief Add a PERIPHCONF entry for configuring a SPU FEATURE.IPCT.INTERRUPT[n] register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Feature index.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_FEATURE_IPCT_INTERRUPT_SET(_spu, _index, _secattr, _ownerid) \
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UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.IPCT.INTERRUPT[_index], \
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_UICR_SPU_FEATURE_VAL(_secattr, _ownerid))
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/** @brief Add a PERIPHCONF entry for configuring a SPU FEATURE.DPPIC.CH[n] register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Feature index.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_FEATURE_DPPIC_CH_SET(_spu, _index, _secattr, _ownerid) \
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UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.DPPIC.CH[_index], \
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_UICR_SPU_FEATURE_VAL(_secattr, _ownerid))
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/** @brief Add a PERIPHCONF entry for configuring a SPU FEATURE.DPPIC.CHG[n] register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Register index.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_FEATURE_DPPIC_CHG_SET(_spu, _index, _secattr, _ownerid) \
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UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.DPPIC.CHG[_index], \
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_UICR_SPU_FEATURE_VAL(_secattr, _ownerid))
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/** @brief Add a PERIPHCONF entry for configuring a SPU FEATURE.GPIOTE[n].CH[m] register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Feature index.
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* @param _subindex Feature subindex.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_FEATURE_GPIOTE_CH_SET(_spu, _index, _subindex, _secattr, _ownerid) \
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UICR_PERIPHCONF_ADD( \
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(uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.GPIOTE[_index].CH[_subindex], \
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_UICR_SPU_FEATURE_VAL(_secattr, _ownerid))
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/** @brief Add a PERIPHCONF entry for configuring a SPU FEATURE.GPIOTE.INTERRUPT[n] register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Feature index.
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* @param _subindex Feature subindex.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_FEATURE_GPIOTE_INTERRUPT_SET(_spu, _index, _subindex, _secattr, _ownerid) \
124+
UICR_PERIPHCONF_ADD( \
125+
(uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.GPIOTE[_index].INTERRUPT[_subindex], \
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_UICR_SPU_FEATURE_VAL(_secattr, _ownerid))
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/** @brief Add a PERIPHCONF entry for configuring a SPU FEATURE.GPIO[n].PIN[m] register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Feature index.
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* @param _subindex Feature subindex.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_FEATURE_GPIO_PIN_SET(_spu, _index, _subindex, _secattr, _ownerid) \
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UICR_PERIPHCONF_ADD( \
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(uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.GPIO[_index].PIN[_subindex], \
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_UICR_SPU_FEATURE_VAL(_secattr, _ownerid))
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/** @brief Add a PERIPHCONF entry for configuring a SPU FEATURE.GRTC.CC[n] register value.
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*
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* @param _spu Global domain SPU peripheral instance.
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* @param _index Feature index.
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* @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure.
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* @param _ownerid OWNERID field value.
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*/
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#define UICR_SPU_FEATURE_GRTC_CC_SET(_spu, _index, _secattr, _ownerid) \
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UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.GRTC.CC[_index], \
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_UICR_SPU_FEATURE_VAL(_secattr, _ownerid))
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/* Common macro for encoding a SPU FEATURE.* register value. */
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#define _UICR_SPU_FEATURE_VAL(_secattr, _ownerid) \
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(uint32_t)((((_ownerid) << SPU_FEATURE_IPCT_CH_OWNERID_Pos) & \
155+
SPU_FEATURE_IPCT_CH_OWNERID_Msk) | \
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(((_secattr) ? SPU_FEATURE_IPCT_CH_SECATTR_Secure \
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: SPU_FEATURE_IPCT_CH_SECATTR_NonSecure) \
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<< SPU_FEATURE_IPCT_CH_SECATTR_Pos) | \
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(SPU_FEATURE_IPCT_CH_LOCK_Locked << SPU_FEATURE_IPCT_CH_LOCK_Pos))
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/** @brief Add PERIPHCONF entries for configuring IPCMAP CHANNEL.SOURCE[n] and CHANNEL.SINK[n].
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*
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* @param _index Register index into CHANNEL.SOURCE[n]/CHANNEL.SINK[n].
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* @param _source_domain DOMAIN field value in CHANNEL[n].SOURCE.
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* @param _source_ch SOURCE field value in CHANNEL[n].SOURCE.
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* @param _sink_domain DOMAIN field value in CHANNEL[n].SINK.
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* @param _sink_ch SINK field value in CHANNEL[n].SINK.
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*/
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#define UICR_IPCMAP_CHANNEL_CFG(_index, _source_domain, _source_ch, _sink_domain, _sink_ch) \
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UICR_IPCMAP_CHANNEL_SOURCE_SET(_index, _source_domain, _source_ch, 1); \
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UICR_IPCMAP_CHANNEL_SINK_SET(_index, _sink_domain, _sink_ch)
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#define UICR_IPCMAP_CHANNEL_SOURCE_SET(_index, _domain, _ch, _enable) \
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UICR_PERIPHCONF_ADD((uint32_t)&NRF_IPCMAP->CHANNEL[(_index)].SOURCE, \
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(uint32_t)((((_domain) << IPCMAP_CHANNEL_SOURCE_DOMAIN_Pos) & \
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IPCMAP_CHANNEL_SOURCE_DOMAIN_Msk) | \
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(((_ch) << IPCMAP_CHANNEL_SOURCE_SOURCE_Pos) & \
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IPCMAP_CHANNEL_SOURCE_SOURCE_Msk) | \
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(((_enable) ? IPCMAP_CHANNEL_SOURCE_ENABLE_Enabled \
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: IPCMAP_CHANNEL_SOURCE_ENABLE_Disabled) \
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<< IPCMAP_CHANNEL_SOURCE_ENABLE_Pos)))
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#define UICR_IPCMAP_CHANNEL_SINK_SET(_index, _domain, _ch) \
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UICR_PERIPHCONF_ADD((uint32_t)&NRF_IPCMAP->CHANNEL[(_index)].SINK, \
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(uint32_t)((((_domain) << IPCMAP_CHANNEL_SINK_DOMAIN_Pos) & \
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IPCMAP_CHANNEL_SINK_DOMAIN_Msk) | \
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(((_ch) << IPCMAP_CHANNEL_SINK_SINK_Pos) & \
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IPCMAP_CHANNEL_SINK_SINK_Msk)))
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/** @brief Add a PERIPHCONF entry for configuring IRQMAP IRQ[n].SINK register value.
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*
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* @param _irqnum IRQ number - register index into IRQ[n].
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* @param _processor PROCESSORID field value.
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*/
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#define UICR_IRQMAP_IRQ_SINK_SET(_irqnum, _processor) \
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UICR_PERIPHCONF_ADD((uint32_t)&NRF_IRQMAP->IRQ[(_irqnum)].SINK, \
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(uint32_t)(((_processor) << IRQMAP_IRQ_SINK_PROCESSORID_Pos) & \
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IRQMAP_IRQ_SINK_PROCESSORID_Msk))
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/** @brief Add a PERIPHCONF entry for configuring a GPIO PIN_CNF[n] CTRLSEL field value.
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*
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* @param _gpio GPIO instance.
203+
* @param _pin Pin number.
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* @param _ctrlsel CTRLSEL field value.
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*/
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#define UICR_GPIO_PIN_CNF_CTRLSEL_SET(_gpio, _pin, _ctrlsel) \
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UICR_PERIPHCONF_ADD( \
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(uint32_t)&((NRF_GPIO_Type *)(_gpio))->PIN_CNF[(_pin)], \
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((GPIO_PIN_CNF_ResetValue) | \
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(uint32_t)(((_ctrlsel) << GPIO_PIN_CNF_CTRLSEL_Pos) & GPIO_PIN_CNF_CTRLSEL_Msk)))
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/** @brief Add a PERIPHCONF entry for configuring a PPIB SUBSCRIBE_SEND[n] register.
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*
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* @param _ppib Global domain PPIB instance.
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* @param _ppib_ch PPIB channel number.
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*/
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#define UICR_PPIB_SUBSCRIBE_SEND_ENABLE(_ppib, _ppib_ch) \
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UICR_PERIPHCONF_ADD((uint32_t)&((NRF_PPIB_Type *)(_ppib))->SUBSCRIBE_SEND[(_ppib_ch)], \
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(uint32_t)PPIB_SUBSCRIBE_SEND_EN_Msk)
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/** @brief Add a PERIPHCONF entry for configuring a PPIB PUBLISH_RECEIVE[n] register.
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*
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* @param _ppib Global domain PPIB instance.
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* @param _ppib_ch PPIB channel number.
225+
*/
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#define UICR_PPIB_PUBLISH_RECEIVE_ENABLE(_ppib, _ppib_ch) \
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UICR_PERIPHCONF_ADD((uint32_t)&((NRF_PPIB_Type *)(_ppib))->PUBLISH_RECEIVE[(_ppib_ch)], \
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(uint32_t)PPIB_PUBLISH_RECEIVE_EN_Msk)
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/* TODO: get everything below from the MDK */
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#ifndef IPCMAP_CHANNEL_SOURCE_SOURCE_Msk
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typedef struct {
234+
__IOM uint32_t SOURCE;
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__IOM uint32_t SINK;
236+
} NRF_IPCMAP_CHANNEL_Type;
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#define IPCMAP_CHANNEL_SOURCE_SOURCE_Pos (0UL)
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#define IPCMAP_CHANNEL_SOURCE_SOURCE_Msk (0xFUL << IPCMAP_CHANNEL_SOURCE_SOURCE_Pos)
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#define IPCMAP_CHANNEL_SOURCE_DOMAIN_Pos (8UL)
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#define IPCMAP_CHANNEL_SOURCE_DOMAIN_Msk (0xFUL << IPCMAP_CHANNEL_SOURCE_DOMAIN_Pos)
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#define IPCMAP_CHANNEL_SOURCE_ENABLE_Pos (31UL)
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#define IPCMAP_CHANNEL_SOURCE_ENABLE_Disabled (0x0UL)
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#define IPCMAP_CHANNEL_SOURCE_ENABLE_Enabled (0x1UL)
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#define IPCMAP_CHANNEL_SINK_SINK_Pos (0UL)
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#define IPCMAP_CHANNEL_SINK_SINK_Msk (0xFUL << IPCMAP_CHANNEL_SINK_SINK_Pos)
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#define IPCMAP_CHANNEL_SINK_DOMAIN_Pos (8UL)
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#define IPCMAP_CHANNEL_SINK_DOMAIN_Msk (0xFUL << IPCMAP_CHANNEL_SINK_DOMAIN_Pos)
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typedef struct {
251+
__IM uint32_t RESERVED[256];
252+
__IOM NRF_IPCMAP_CHANNEL_Type CHANNEL[16];
253+
} NRF_IPCMAP_Type;
254+
255+
#endif /* IPCMAP_CHANNEL_SOURCE_SOURCE_Msk */
256+
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#ifndef NRF_IPCMAP
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#define NRF_IPCMAP ((NRF_IPCMAP_Type *)0x5F923000UL)
259+
#endif
260+
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#ifndef IRQMAP_IRQ_SINK_PROCESSORID_Msk
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263+
typedef struct {
264+
__IOM uint32_t SINK;
265+
} NRF_IRQMAP_IRQ_Type;
266+
267+
#define IRQMAP_IRQ_SINK_PROCESSORID_Pos (8UL)
268+
#define IRQMAP_IRQ_SINK_PROCESSORID_Msk (0xFUL << IRQMAP_IRQ_SINK_PROCESSORID_Pos)
269+
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typedef struct {
271+
__IM uint32_t RESERVED[256];
272+
__IOM NRF_IRQMAP_IRQ_Type IRQ[480];
273+
} NRF_IRQMAP_Type;
274+
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#endif /* IRQMAP_IRQ_SINK_PROCESSORID_Msk */
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#ifndef NRF_IRQMAP
278+
#define NRF_IRQMAP ((NRF_IRQMAP_Type *)0x5F924000UL)
279+
#endif /* NRF_IRQMAP */
280+
281+
#ifndef NRF_GPIO_PIN_CNF_CTRLSEL_Pos
282+
283+
#define GPIO_PIN_CNF_CTRLSEL_Pos (28UL)
284+
#define GPIO_PIN_CNF_CTRLSEL_Msk (0x7UL << GPIO_PIN_CNF_CTRLSEL_Pos)
285+
286+
#endif /* NRF_GPIO_PIN_CNF_CTRLSEL_Pos */
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#endif /* SOC_NORDIC_COMMON_UICR_UICR_H_ */

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