@@ -117,6 +117,7 @@ DEFINE_MM_REG_RD(risr, 0x34)
117117DEFINE_MM_REG_RD_WR (dr , 0x60 )
118118DEFINE_MM_REG_WR (rx_sample_dly , 0xf0 )
119119DEFINE_MM_REG_WR (spi_ctrlr0 , 0xf4 )
120+ DEFINE_MM_REG_WR (txd_drive_edge , 0xf8 )
120121
121122#if defined(CONFIG_MSPI_XIP )
122123DEFINE_MM_REG_WR (xip_incr_inst , 0x100 )
@@ -691,8 +692,21 @@ static int _api_dev_config(const struct device *dev,
691692
692693 if (param_mask & MSPI_DEVICE_CONFIG_DATA_RATE ) {
693694 /* TODO: add support for DDR */
694- if (cfg -> data_rate != MSPI_DATA_RATE_SINGLE ) {
695- LOG_ERR ("Only single data rate is supported." );
695+ dev_data -> spi_ctrlr0 &= ~(SPI_CTRLR0_SPI_DDR_EN_BIT |
696+ SPI_CTRLR0_INST_DDR_EN_BIT );
697+ switch (cfg -> data_rate ) {
698+ case MSPI_DATA_RATE_SINGLE :
699+ break ;
700+ case MSPI_DATA_RATE_DUAL :
701+ dev_data -> spi_ctrlr0 |= SPI_CTRLR0_INST_DDR_EN_BIT ;
702+ /* Also need to set DDR_EN bit */
703+ __fallthrough ;
704+ case MSPI_DATA_RATE_S_D_D :
705+ dev_data -> spi_ctrlr0 |= SPI_CTRLR0_SPI_DDR_EN_BIT ;
706+ break ;
707+ default :
708+ LOG_ERR ("Data rate %d not supported" ,
709+ cfg -> data_rate );
696710 return - ENOTSUP ;
697711 }
698712 }
@@ -940,6 +954,12 @@ static int start_next_packet(const struct device *dev, k_timeout_t timeout)
940954 write_spi_ctrlr0 (dev , dev_data -> spi_ctrlr0 );
941955 write_baudr (dev , dev_data -> baudr );
942956 write_rx_sample_dly (dev , dev_data -> rx_sample_dly );
957+ if (dev_data -> spi_ctrlr0 & (SPI_CTRLR0_SPI_DDR_EN_BIT |
958+ SPI_CTRLR0_INST_DDR_EN_BIT )) {
959+ write_txd_drive_edge (dev , dev_data -> baudr / 4 );
960+ } else {
961+ write_txd_drive_edge (dev , 0 );
962+ }
943963
944964 if (xip_enabled ) {
945965 write_ssienr (dev , SSIENR_SSIC_EN_BIT );
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