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[nrf fromlist] soc: arm: nrf53: workaround pop lr after wfi crash
On nRF5340 net core it was observed that when `wfi` instruction was followed by `pop {r0, lr}` in the `arch_cpu_idle` function, the value of `lr` sometimes got read as 0 from memory despite having correct value stored in the memory. This commit inserts additional `nop` instruction after waking up to delay access to the memory. Upstream PR: zephyrproject-rtos/zephyr#60099 Signed-off-by: Andrzej Kuros <[email protected]>
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arch/arm/Kconfig

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@@ -53,6 +53,22 @@ config ARM_ON_ENTER_CPU_IDLE_HOOK
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If needed, this hook can be used to prevent the CPU from actually
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entering sleep by skipping the WFE/WFI instruction.
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config ARM_ON_EXIT_CPU_IDLE
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bool
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help
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Enables a possibility to inject SoC-specific code just after WFI/WFE
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instructions of the cpu idle implementation.
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Enabling this option requires that the SoC provides a soc_cpu_idle.h
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header file which defines SOC_ON_EXIT_CPU_IDLE macro guarded by
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_ASMLANGUAGE.
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The SOC_ON_EXIT_CPU_IDLE macro is expanded just after
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WFI/WFE instructions before any memory access is performed. The purpose
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of the SOC_ON_EXIT_CPU_IDLE is to perform an action that mitigate issues
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observed on some SoCs caused by a memory access following WFI/WFE
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instructions.
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rsource "core/aarch32/Kconfig"
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rsource "core/aarch32/Kconfig.vfp"
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arch/arm/core/aarch32/cpu_idle.S

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@@ -13,6 +13,10 @@
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
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#include <soc_cpu_idle.h>
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#endif
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_ASM_FILE_PROLOGUE
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GTEXT(z_arm_cpu_idle_init)
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dsb
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\wait_instruction
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#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
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/* Inline the macro provided by SoC-specific code */
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SOC_ON_EXIT_CPU_IDLE
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#endif /* CONFIG_ARM_ON_EXIT_CPU_IDLE */
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#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
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_skip_\@:
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)

soc/arm/nordic_nrf/nrf53/Kconfig.soc

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@@ -13,6 +13,7 @@ config SOC_NRF5340_CPUAPP
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config SOC_NRF5340_CPUNET
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bool
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select HAS_NO_PM
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select ARM_ON_EXIT_CPU_IDLE
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imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
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choice
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@@ -0,0 +1,20 @@
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/*
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC extensions of cpu_idle.S for the Nordic Semiconductor nRF53 processors family.
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*/
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#if defined(_ASMLANGUAGE)
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#define SOC_ON_EXIT_CPU_IDLE \
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nop; \
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nop; \
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nop; \
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nop;
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#endif /* _ASMLANGUAGE */

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