[nrf fromlist] drivers: clock_control: nrf: Apply fix for nRF54L anomaly 30.

Applied fix for nRF54L anomaly 30, which requires a periodic
calibration of high-frequency clock.

Upstream PR #: 88112

Signed-off-by: Michał Stasiak <[email protected]>

Author: mstasiaknordic

drivers/clock_control/Kconfig.nrf

@@ -128,6 +128,29 @@ config CLOCK_CONTROL_NRF_USES_TEMP_SENSOR
 endif # CLOCK_CONTROL_NRF_DRIVER_CALIBRATION
 endif # CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION
 
+config CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+	bool "HFINT clock calibration"
+	depends on SOC_NRF54L05 || SOC_NRF54L10 || SOC_NRF54L15
+	depends on DT_HAS_NORDIC_NRF_HFXO_ENABLED
+	depends on !TRUSTED_EXECUTION_NONSECURE
+	select EXPERIMENTAL
+	help
+	  Enables calibration of HFINT clock on every start of HFXO clock.
+
+if CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+
+config CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD
+	int "HFINT clock calibration period in milliseconds"
+	default 60000
+	help
+	  Periodically, HFINT clock calibration is performed.
+	  This includes requesting HFXO clock and starting actual calibration.
+	  Once the calibration is finished, the HFXO clock is released.
+	  Set to 0 to disable periodic calibration - in such case calibration
+	  will be done only when HFXO is started by the application itself.
+
+endif # CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+
 choice CLOCK_CONTROL_NRF_ACCURACY_PPM
 	prompt "32KHz clock accuracy"
 	default CLOCK_CONTROL_NRF_K32SRC_500PPM if CLOCK_CONTROL_NRF_K32SRC_RC && SOC_COMPATIBLE_NRF52X

drivers/clock_control/clock_control_nrf.c

@@ -14,6 +14,7 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/shell/shell.h>
 #include <zephyr/irq.h>
+#include <nrf_erratas.h>
 
 LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
 
@@ -84,6 +85,10 @@ static uint64_t hf_stop_tstamp;
 static struct onoff_client lfsynth_cli;
 #endif
 
+#if CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD
+static struct onoff_client hf_cal_cli;
+#endif
+
 static struct nrf_clock_control_sub_data *get_sub_data(const struct device *dev,
 						       enum clock_control_nrf_type type)
 {
@@ -172,9 +177,90 @@ static void set_on_state(uint32_t *flags)
 	irq_unlock(key);
 }
 
+#ifdef CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+
+static void nrf54l_errata_30_workaround(void)
+{
+	while (FIELD_GET(CLOCK_XO_STAT_STATE_Msk, NRF_CLOCK->XO.STAT) !=
+	       CLOCK_XO_STAT_STATE_Running) {
+	}
+	const uint32_t higher_bits = *((volatile uint32_t *)0x50120820UL) & 0xFFFFFFC0;
+	*((volatile uint32_t *)0x50120864UL) = 1 | BIT(31);
+	*((volatile uint32_t *)0x50120848UL) = 1;
+	uint32_t off_abs = 24;
+
+	while (off_abs >= 24) {
+		*((volatile uint32_t *)0x50120844UL) = 1;
+		while (((*((volatile uint32_t *)0x50120840UL)) & (1 << 16)) != 0) {
+		}
+		const uint32_t current_cal = *((volatile uint32_t *)0x50120820UL) & 0x3F;
+		const uint32_t cal_result = *((volatile uint32_t *)0x50120840UL) & 0x7FF;
+		int32_t off = 1024 - cal_result;
+
+		off_abs = (off < 0) ? -off : off;
+
+		if (off >= 24 && current_cal < 0x3F) {
+			*((volatile uint32_t *)0x50120820UL) = higher_bits | (current_cal + 1);
+		} else if (off <= -24 && current_cal > 0) {
+			*((volatile uint32_t *)0x50120820UL) = higher_bits | (current_cal - 1);
+		}
+	}
+
+	*((volatile uint32_t *)0x50120848UL) = 0;
+	*((volatile uint32_t *)0x50120864UL) = 0;
+}
+
+#if CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD
+
+static struct onoff_client hf_cal_cli;
+
+static void calibration_finished_callback(struct onoff_manager *mgr,
+					  struct onoff_client *cli,
+					  uint32_t state,
+					  int res)
+{
+	(void)onoff_cancel_or_release(mgr, cli);
+}
+
+static void calibration_handler(struct k_timer *timer)
+{
+	nrf_clock_hfclk_t clk_src;
+
+	bool ret = nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src);
+
+	if (ret && (clk_src == NRF_CLOCK_HFCLK_HIGH_ACCURACY)) {
+		return;
+	}
+
+	sys_notify_init_callback(&hf_cal_cli.notify, calibration_finished_callback);
+	(void)onoff_request(z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF),
+			    &hf_cal_cli);
+}
+
+static K_TIMER_DEFINE(calibration_timer, calibration_handler, NULL);
+
+static int calibration_init(void)
+{
+	k_timer_start(&calibration_timer,
+		      K_NO_WAIT,
+		      K_MSEC(CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD));
+
+	return 0;
+}
+
+SYS_INIT(calibration_init, APPLICATION, 0);
+
+#endif /* CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD */
+#endif /* CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION */
+
 static void clkstarted_handle(const struct device *dev,
 			      enum clock_control_nrf_type type)
 {
+#if CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+	if (nrf54l_errata_30() && (type == CLOCK_CONTROL_NRF_TYPE_HFCLK)) {
+		nrf54l_errata_30_workaround();
+	}
+#endif
 	struct nrf_clock_control_sub_data *sub_data = get_sub_data(dev, type);
 	clock_control_cb_t callback = sub_data->cb;
 	void *user_data = sub_data->user_data;