1313#include <zephyr/linker/devicetree_regions.h>
1414#include <zephyr/cache.h>
1515#include <zephyr/mem_mgmt/mem_attr.h>
16- #ifdef CONFIG_CLOCK_CONTROL
17- #include <zephyr/drivers/clock_control/nrf_clock_control.h>
18- #endif
1916#ifdef CONFIG_SOC_NRF54H20_GPD
2017#include <nrf/gpd.h>
2118#endif
@@ -38,26 +35,6 @@ LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
3835#define ANOMALY_109_EGU_IRQ_CONNECT (idx )
3936#endif
4037
41- #define PWM (dev_idx ) DT_NODELABEL(pwm##dev_idx)
42- #define PWM_PROP (dev_idx , prop ) DT_PROP(PWM(dev_idx), prop)
43- #define PWM_HAS_PROP (idx , prop ) DT_NODE_HAS_PROP(PWM(idx), prop)
44-
45- #define PWM_NRFX_IS_FAST (unused , prefix , idx , _ ) \
46- COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(PWM(idx)), \
47- (COND_CODE_1(PWM_HAS_PROP(idx, power_domains), \
48- (IS_EQ(DT_PHA(PWM(idx), power_domains, id), NRF_GPD_FAST_ACTIVE1)), \
49- (0))), (0))
50-
51- #if NRFX_FOREACH_PRESENT (PWM , PWM_NRFX_IS_FAST , (|| ), (0 ))
52- #if CONFIG_CLOCK_CONTROL
53- #define PWM_NRFX_USE_CLOCK_CONTROL 1
54- #endif
55- #define PWM_NRFX_INIT_PRIORITY 99
56- #else
57- #define PWM_NRFX_INIT_PRIORITY CONFIG_PWM_INIT_PRIORITY
58- #endif
59-
60-
6138#define PWM_NRFX_CH_POLARITY_MASK BIT(15)
6239#define PWM_NRFX_CH_COMPARE_MASK BIT_MASK(15)
6340#define PWM_NRFX_CH_VALUE (compare_value , inverted ) \
@@ -72,10 +49,6 @@ struct pwm_nrfx_config {
7249#ifdef CONFIG_DCACHE
7350 uint32_t mem_attr ;
7451#endif
75- #ifdef PWM_NRFX_USE_CLOCK_CONTROL
76- const struct device * clk_dev ;
77- struct nrf_clock_spec clk_spec ;
78- #endif
7952};
8053
8154struct pwm_nrfx_data {
@@ -84,9 +57,6 @@ struct pwm_nrfx_data {
8457 uint8_t pwm_needed ;
8558 uint8_t prescaler ;
8659 bool stop_requested ;
87- #ifdef PWM_NRFX_USE_CLOCK_CONTROL
88- bool clock_requested ;
89- #endif
9060};
9161/* Ensure the pwm_needed bit mask can accommodate all available channels. */
9262#if (NRF_PWM_CHANNEL_COUNT > 8 )
@@ -259,18 +229,6 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
259229 * ensure it is stopped before starting the next playback.
260230 */
261231 nrfx_pwm_stop (& config -> pwm , false);
262- #if PWM_NRFX_USE_CLOCK_CONTROL
263- if (data -> clock_requested ) {
264- int ret = nrf_clock_control_release (config -> clk_dev , & config -> clk_spec );
265-
266- if (ret < 0 ) {
267- LOG_ERR ("Global HSFLL release failed: %d" , ret );
268- return ret ;
269- }
270-
271- data -> clock_requested = false;
272- }
273- #endif
274232 data -> stop_requested = true;
275233 } else {
276234 if (data -> stop_requested ) {
@@ -290,18 +248,6 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
290248 * until another playback is requested (new values will be
291249 * loaded then) or the PWM peripheral is stopped.
292250 */
293- #if PWM_NRFX_USE_CLOCK_CONTROL
294-
295- int ret = nrf_clock_control_request_sync (config -> clk_dev , & config -> clk_spec ,
296- K_FOREVER );
297-
298- if (ret < 0 ) {
299- LOG_ERR ("Global HSFLL request failed: %d" , ret );
300- return ret ;
301- }
302-
303- data -> clock_requested = true;
304- #endif
305251 nrfx_pwm_simple_playback (& config -> pwm , & config -> seq , 1 ,
306252 NRFX_PWM_FLAG_NO_EVT_FINISHED );
307253 }
@@ -360,14 +306,6 @@ static void pwm_suspend(const struct device *dev)
360306 const struct pwm_nrfx_config * config = dev -> config ;
361307
362308 nrfx_pwm_stop (& config -> pwm , false);
363- #if PWM_NRFX_USE_CLOCK_CONTROL
364-
365- int ret = nrf_clock_control_release (config -> clk_dev , & config -> clk_spec );
366-
367- if (ret < 0 ) {
368- LOG_ERR ("Global HSFLL release failed: %d" , ret );
369- }
370- #endif
371309 while (!nrfx_pwm_stopped_check (& config -> pwm )) {
372310 }
373311
@@ -413,6 +351,9 @@ static int pwm_nrfx_init(const struct device *dev)
413351 return pm_device_driver_init (dev , pwm_nrfx_pm_action );
414352}
415353
354+ #define PWM (dev_idx ) DT_NODELABEL(pwm##dev_idx)
355+ #define PWM_PROP (dev_idx , prop ) DT_PROP(PWM(dev_idx), prop)
356+ #define PWM_HAS_PROP (idx , prop ) DT_NODE_HAS_PROP(PWM(idx), prop)
416357#define PWM_MEM_REGION (idx ) DT_PHANDLE(PWM(idx), memory_regions)
417358
418359#define PWM_MEMORY_SECTION (idx ) \
@@ -452,15 +393,6 @@ static int pwm_nrfx_init(const struct device *dev)
452393 (16ul * 1000ul * 1000ul)), \
453394 IF_ENABLED(CONFIG_DCACHE, \
454395 (.mem_attr = PWM_GET_MEM_ATTR(idx),)) \
455- IF_ENABLED(PWM_NRFX_USE_CLOCK_CONTROL, \
456- (.clk_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(PWM(idx))), \
457- .clk_spec = { \
458- .frequency = \
459- NRF_PERIPH_GET_FREQUENCY(PWM(idx)), \
460- .accuracy = 0, \
461- .precision = \
462- NRF_CLOCK_CONTROL_PRECISION_DEFAULT, \
463- },)) \
464396 }; \
465397 static int pwm_nrfx_init##idx(const struct device *dev) \
466398 { \
@@ -473,7 +405,7 @@ static int pwm_nrfx_init(const struct device *dev)
473405 pwm_nrfx_init##idx, PM_DEVICE_DT_GET(PWM(idx)), \
474406 &pwm_nrfx_##idx##_data, \
475407 &pwm_nrfx_##idx##_config, \
476- POST_KERNEL, PWM_NRFX_INIT_PRIORITY , \
408+ POST_KERNEL, CONFIG_PWM_INIT_PRIORITY , \
477409 &pwm_nrfx_drv_api_funcs)
478410
479411#define COND_PWM_NRFX_DEVICE (unused , prefix , i , _ ) \
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