1212 * for the Nordic Semiconductor nRF54L family processor.
1313 */
1414
15+ #ifdef __NRF_TFM__
16+ #include <autoconf.h>
17+ #endif
18+
1519#include <zephyr/kernel.h>
1620#include <zephyr/devicetree.h>
1721#include <zephyr/init.h>
1822#include <zephyr/logging/log.h>
23+
24+ #ifndef __NRF_TFM__
1925#include <zephyr/cache.h>
26+ #endif
2027
2128#if defined(NRF_APPLICATION )
2229#include <cmsis_core.h>
@@ -36,17 +43,9 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
3643#define HFXO_NODE DT_NODELABEL(hfxo)
3744#endif
3845
39- static int nordicsemi_nrf54l_init (void )
40- {
41- /* Update the SystemCoreClock global variable with current core clock
42- * retrieved from hardware state.
43- */
44- SystemCoreClockUpdate ();
45-
4646#if defined(NRF_APPLICATION )
47- /* Enable ICACHE */
48- sys_cache_instr_enable ();
49-
47+ static inline void power_and_clock_configuration (void )
48+ {
5049#if DT_ENUM_HAS_VALUE (LFXO_NODE , load_capacitors , internal )
5150 uint32_t xosc32ktrim = NRF_FICR -> XOSC32KTRIM ;
5251
@@ -73,16 +72,16 @@ static int nordicsemi_nrf54l_init(void)
7372 * NOTE: The desired capacitance value is used in encoded from in INTCAP calculation formula
7473 * That is different than in case of HFXO.
7574 */
76- uint32_t cap_val_encoded = ((( DT_PROP ( LFXO_NODE , load_capacitance_femtofarad ) - 4000UL )
77- * 2UL ) / 1000UL );
75+ uint32_t cap_val_encoded =
76+ ((( DT_PROP ( LFXO_NODE , load_capacitance_femtofarad ) - 4000UL ) * 2UL ) / 1000UL );
7877
7978 /* Calculation of INTCAP code before rounding. Min that calculations here are done on
8079 * values multiplied by 2^9, e.g. 0.765625 * 2^9 = 392.
8180 * offset_k should be divided by 2^6, but to add it to value shifted by 2^9 we have to
8281 * multiply it be 2^3.
8382 */
84- uint32_t mid_val = ( cap_val_encoded - 4UL ) * ( uint32_t )( slope_k + 392UL )
85- + (offset_k << 3UL );
83+ uint32_t mid_val =
84+ ( cap_val_encoded - 4UL ) * ( uint32_t )( slope_k + 392UL ) + (offset_k << 3UL );
8685
8786 /* Get integer part of the INTCAP code */
8887 uint32_t lfxo_intcap = mid_val >> 9UL ;
@@ -128,8 +127,9 @@ static int nordicsemi_nrf54l_init(void)
128127 */
129128 uint32_t cap_val_femto_f = DT_PROP (HFXO_NODE , load_capacitance_femtofarad );
130129
131- uint32_t mid_val_intcap = (((cap_val_femto_f - 5500UL ) * (uint32_t )(slope_m + 791UL ))
132- + (offset_m << 2UL ) * 1000UL ) >> 8UL ;
130+ uint32_t mid_val_intcap = (((cap_val_femto_f - 5500UL ) * (uint32_t )(slope_m + 791UL )) +
131+ (offset_m << 2UL ) * 1000UL ) >>
132+ 8UL ;
133133
134134 /* Convert the calculated value to piko Farads */
135135 uint32_t hfxo_intcap = mid_val_intcap / 1000 ;
@@ -160,8 +160,40 @@ static int nordicsemi_nrf54l_init(void)
160160#if defined(CONFIG_ELV_GRTC_LFXO_ALLOWED )
161161 nrf_regulators_elv_mode_allow_set (NRF_REGULATORS , NRF_REGULATORS_ELV_ELVGRTCLFXO_MASK );
162162#endif /* CONFIG_ELV_GRTC_LFXO_ALLOWED */
163+ }
163164#endif /* NRF_APPLICATION */
164165
166+ int nordicsemi_nrf54l_init (void )
167+ {
168+ /* Update the SystemCoreClock global variable with current core clock
169+ * retrieved from hardware state.
170+ */
171+ #if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE ) || defined(__NRF_TFM__ )
172+ /* Currently not supported for non-secure */
173+ SystemCoreClockUpdate ();
174+ #endif
175+
176+ #ifdef __NRF_TFM__
177+ /* TF-M enables the instruction cache from target_cfg.c, so we
178+ * don't need to enable it here.
179+ */
180+ #else
181+ /* Enable ICACHE */
182+ sys_cache_instr_enable ();
183+ #endif
184+
185+ /* NRF_REGULATORS and NRF_OSCILLATORS are configured to be secure
186+ * as NRF_REGULATORS.POFCON is needed by the secure domain to
187+ * prevent glitches when the power supply is attacked.
188+ *
189+ * NRF_OSCILLATORS is also configured as secure because of a HW limitation
190+ * that requires them to be configured with the same security property.
191+ */
192+ #if (defined(NRF_APPLICATION ) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE )) || \
193+ defined(__NRF_TFM__ )
194+ power_and_clock_configuration ();
195+ #endif
196+
165197 return 0 ;
166198}
167199
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