|
150 | 150 | fifo = <0x0008>; |
151 | 151 | interrupts = <0x08 0 0>; |
152 | 152 | interrupt-parent = <&ace_intc>; |
153 | | - power-domain = <&hub_ulp_domain>; |
| 153 | + power-domains = <&hub_ulp_domain>; |
154 | 154 | }; |
155 | 155 |
|
156 | 156 | dmic1: dmic1@10000 { |
|
160 | 160 | fifo = <0x0108>; |
161 | 161 | interrupts = <0x09 0 0>; |
162 | 162 | interrupt-parent = <&ace_intc>; |
163 | | - power-domain = <&hub_ulp_domain>; |
| 163 | + power-domains = <&hub_ulp_domain>; |
164 | 164 | }; |
165 | 165 |
|
166 | 166 | /* |
|
285 | 285 | dmas = <&lpgpdma0 2 |
286 | 286 | &lpgpdma0 3>; |
287 | 287 | dma-names = "tx", "rx"; |
288 | | - power-domain = <&io0_domain>; |
| 288 | + power-domains = <&io0_domain>; |
289 | 289 | ssp-index = <0>; |
290 | 290 | status = "okay"; |
291 | 291 |
|
|
307 | 307 | dmas = <&lpgpdma0 4 |
308 | 308 | &lpgpdma0 5>; |
309 | 309 | dma-names = "tx", "rx"; |
310 | | - power-domain = <&io0_domain>; |
| 310 | + power-domains = <&io0_domain>; |
311 | 311 | ssp-index = <1>; |
312 | 312 | status = "okay"; |
313 | 313 |
|
|
329 | 329 | dmas = <&lpgpdma0 6 |
330 | 330 | &lpgpdma0 7>; |
331 | 331 | dma-names = "tx", "rx"; |
332 | | - power-domain = <&io0_domain>; |
| 332 | + power-domains = <&io0_domain>; |
333 | 333 | ssp-index = <2>; |
334 | 334 | status = "okay"; |
335 | 335 |
|
|
387 | 387 | hub_ulp_domain: hub_ulp_domain { |
388 | 388 | compatible = "intel,adsp-power-domain"; |
389 | 389 | bit-position = <15>; |
| 390 | + #power-domain-cells = <0>; |
390 | 391 | }; |
391 | 392 | ml1_domain: ml1_domain { |
392 | 393 | compatible = "intel,adsp-power-domain"; |
393 | 394 | bit-position = <13>; |
| 395 | + #power-domain-cells = <0>; |
394 | 396 | }; |
395 | 397 | ml0_domain: ml0_domain { |
396 | 398 | compatible = "intel,adsp-power-domain"; |
397 | 399 | bit-position = <12>; |
| 400 | + #power-domain-cells = <0>; |
398 | 401 | }; |
399 | 402 | io3_domain: io3_domain { |
400 | 403 | compatible = "intel,adsp-power-domain"; |
401 | 404 | bit-position = <11>; |
| 405 | + #power-domain-cells = <0>; |
402 | 406 | }; |
403 | 407 | io2_domain: io2_domain { |
404 | 408 | compatible = "intel,adsp-power-domain"; |
405 | 409 | bit-position = <10>; |
| 410 | + #power-domain-cells = <0>; |
406 | 411 | }; |
407 | 412 | io1_domain: io1_domain { |
408 | 413 | compatible = "intel,adsp-power-domain"; |
409 | 414 | bit-position = <9>; |
| 415 | + #power-domain-cells = <0>; |
410 | 416 | }; |
411 | 417 | io0_domain: io0_domain { |
412 | 418 | compatible = "intel,adsp-power-domain"; |
413 | 419 | bit-position = <8>; |
| 420 | + #power-domain-cells = <0>; |
414 | 421 | }; |
415 | 422 | hub_hp_domain: hub_hp_domain { |
416 | 423 | compatible = "intel,adsp-power-domain"; |
417 | 424 | bit-position = <6>; |
| 425 | + #power-domain-cells = <0>; |
418 | 426 | }; |
419 | 427 | hst_domain: hst_domain { |
420 | 428 | compatible = "intel,adsp-power-domain"; |
421 | 429 | bit-position = <4>; |
| 430 | + #power-domain-cells = <0>; |
422 | 431 | }; |
423 | 432 | }; |
424 | 433 |
|
|
464 | 473 | dma-buf-addr-alignment = <128>; |
465 | 474 | dma-buf-size-alignment = <32>; |
466 | 475 | dma-copy-alignment = <16>; |
467 | | - power-domain = <&io0_domain>; |
| 476 | + power-domains = <&io0_domain>; |
468 | 477 | status = "okay"; |
469 | 478 | }; |
470 | 479 |
|
|
476 | 485 | dma-buf-addr-alignment = <128>; |
477 | 486 | dma-buf-size-alignment = <32>; |
478 | 487 | dma-copy-alignment = <16>; |
479 | | - power-domain = <&io0_domain>; |
| 488 | + power-domains = <&io0_domain>; |
480 | 489 | status = "okay"; |
481 | 490 | }; |
482 | 491 |
|
|
488 | 497 | dma-buf-addr-alignment = <128>; |
489 | 498 | dma-buf-size-alignment = <32>; |
490 | 499 | dma-copy-alignment = <16>; |
491 | | - power-domain = <&hst_domain>; |
| 500 | + power-domains = <&hst_domain>; |
492 | 501 | interrupts = <13 0 0>; |
493 | 502 | interrupt-parent = <&ace_intc>; |
494 | 503 | status = "okay"; |
|
502 | 511 | dma-buf-addr-alignment = <128>; |
503 | 512 | dma-buf-size-alignment = <32>; |
504 | 513 | dma-copy-alignment = <16>; |
505 | | - power-domain = <&hst_domain>; |
| 514 | + power-domains = <&hst_domain>; |
506 | 515 | interrupts = <12 0 0>; |
507 | 516 | interrupt-parent = <&ace_intc>; |
508 | 517 | status = "okay"; |
|
541 | 550 | dma-buf-size-alignment = <4>; |
542 | 551 | dma-copy-alignment = <4>; |
543 | 552 | status = "okay"; |
544 | | - power-domain = <&hub_ulp_domain>; |
| 553 | + power-domains = <&hub_ulp_domain>; |
545 | 554 | zephyr,pm-device-runtime-auto; |
546 | 555 | }; |
547 | 556 |
|
|
555 | 564 | dma-buf-size-alignment = <4>; |
556 | 565 | dma-copy-alignment = <4>; |
557 | 566 | status = "okay"; |
558 | | - power-domain = <&io0_domain>; |
| 567 | + power-domains = <&io0_domain>; |
559 | 568 | zephyr,pm-device-runtime-auto; |
560 | 569 | }; |
561 | 570 |
|
|
568 | 577 | interrupt-parent = <&core_intc>; |
569 | 578 | dma-buf-size-alignment = <4>; |
570 | 579 | dma-copy-alignment = <4>; |
571 | | - power-domain = <&io0_domain>; |
| 580 | + power-domains = <&io0_domain>; |
572 | 581 | status = "okay"; |
573 | 582 | zephyr,pm-device-runtime-auto; |
574 | 583 | }; |
|
0 commit comments