dwc2: support ISO transfer scheduling

Author: Victor Brzeski

drivers/usb/udc/udc_dwc2.c

@@ -62,6 +62,8 @@ enum dwc2_drv_event_type {
  */
 #define UDC_DWC2_FIFO0_DEPTH		(2 * 16U)
 
+#define UDC_DWC2_TARGET_FRAME_INITIAL UINT16_MAX
+
 /* Get Data FIFO access register */
 #define UDC_DWC2_EP_FIFO(base, idx)	((mem_addr_t)base + 0x1000 * (idx + 1))
 
@@ -138,6 +140,8 @@ struct udc_dwc2_data {
 	/* Number of OUT endpoints including control endpoint */
 	uint8_t outeps;
 	uint8_t setup[8];
+	/* Target frame numbers for isochronous endpoints */
+	uint16_t target_frames[32];
 };
 
 #if defined(CONFIG_PINCTRL)
@@ -381,6 +385,21 @@ static bool dwc2_ep_is_periodic(struct udc_ep_config *const cfg)
 	}
 }
 
+static void dwc2_ep_next_target_frame(const struct device *dev, struct udc_ep_config *const cfg) {
+	struct udc_dwc2_data *const priv = udc_get_private(dev);
+	uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr);
+	uint16_t limit = USB_DWC2_DSTS_SOFFN_LIMIT;
+
+	if ((priv->enumspd != USB_DWC2_DSTS_ENUMSPD_HS3060) {
+		limit >>= 3;
+	}
+
+	priv->target_frames[ep_idx] += cfg->interval;
+	if (priv->target_frames[ep_idx] > limit) {
+		priv->target_frames[ep_idx] &= limit;
+	}
+}
+
 static bool dwc2_ep_is_iso(struct udc_ep_config *const cfg)
 {
 	return (cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) == USB_EP_TYPE_ISO;
@@ -566,13 +585,12 @@ static int dwc2_tx_fifo_write(const struct device *dev,
 	}
 
 	if (is_iso) {
-		/* Queue transfer on next SOF. TODO: allow stack to explicitly
-		 * specify on which (micro-)frame the data should be sent.
-		 */
-		if (priv->sof_num & 1) {
-			diepctl |= USB_DWC2_DEPCTL_SETEVENFR;
-		} else {
-			diepctl |= USB_DWC2_DEPCTL_SETODDFR;
+		if (cfg->interval == 1) {
+			if (priv->target_frames[ep_idx] & 1) {
+				diepctl |= USB_DWC2_DEPCTL_SETODDFR;
+			} else {
+				diepctl |= USB_DWC2_DEPCTL_SETEVENFR;
+			}
 		}
 	}
 
@@ -706,10 +724,12 @@ static void dwc2_prep_rx(const struct device *dev, struct net_buf *buf,
 		}
 
 		/* Set the Even/Odd (micro-)frame appropriately */
-		if (priv->sof_num & 1) {
-			doepctl |= USB_DWC2_DEPCTL_SETEVENFR;
-		} else {
-			doepctl |= USB_DWC2_DEPCTL_SETODDFR;
+		if (cfg->interval == 1) {
+			if (priv->target_frames[ep_idx] & 1) {
+				diepctl |= USB_DWC2_DEPCTL_SETODDFR;
+			} else {
+				diepctl |= USB_DWC2_DEPCTL_SETEVENFR;
+			}
 		}
 	} else {
 		xfersize = net_buf_tailroom(buf);
@@ -1363,6 +1383,7 @@ static int dwc2_set_dedicated_fifo(const struct device *dev,
 static int dwc2_ep_control_enable(const struct device *dev,
 				  struct udc_ep_config *const cfg)
 {
+	struct udc_dwc2_data *const priv = udc_get_private(dev);
 	mem_addr_t dxepctl0_reg;
 	uint32_t dxepctl0;
 
@@ -1395,6 +1416,11 @@ static int dwc2_ep_control_enable(const struct device *dev,
 		dwc2_flush_tx_fifo(dev, 0);
 	}
 
+	if (dwc2_ep_is_iso(cfg)) {
+		const uint8_t ep_idx = USB_EP_GET_IDX(ep) + (USB_EP_DIR_IS_IN(ep) ? 0U : 16U);
+		priv->target_frames[ep_idx] = UDC_DWC2_TARGET_FRAME_INITIAL;
+	}
+
 	sys_write32(dxepctl0, dxepctl0_reg);
 	dwc2_set_epint(dev, cfg, true);
 
@@ -2417,6 +2443,7 @@ static void dwc2_on_bus_reset(const struct device *dev)
 	uint32_t doepmsk;
 
 	/* Set the NAK bit for all OUT endpoints */
+	sys_clear_bits((mem_addr_t)&base->diepmsk, USB_DWC2_DIEPINT_NAKINTRPT);
 	for (uint8_t i = 0U; i < priv->numdeveps; i++) {
 		uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(priv->ghwcfg1, i);
 		mem_addr_t doepctl_reg;
@@ -2435,7 +2462,7 @@ static void dwc2_on_bus_reset(const struct device *dev)
 	}
 
 	sys_write32(doepmsk, (mem_addr_t)&base->doepmsk);
-	sys_set_bits((mem_addr_t)&base->diepmsk, USB_DWC2_DIEPINT_XFERCOMPL);
+	sys_set_bits((mem_addr_t)&base->diepmsk, USB_DWC2_DIEPINT_XFERCOMPL | USB_DWC2_DIEPINT_NAKINTRPT);
 
 	/* Software has to handle RxFLvl interrupt only in Completer mode */
 	if (dwc2_in_completer_mode(dev)) {
@@ -2562,6 +2589,38 @@ static inline void dwc2_handle_in_xfercompl(const struct device *dev,
 	k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED));
 }
 
+static inline void dwc2_handle_in_nakintrpt(const struct device *dev,
+					    const uint8_t ep_idx)
+{
+	struct udc_dwc2_data *const priv = udc_get_private(dev);
+	/* TODO: use dwc2_get_dxepctl_reg() */
+	mem_addr_t diepctl_reg = (mem_addr_t)&base->in_ep[ep_idx].diepctl;
+	struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, ep_idx | USB_EP_DIR_IN);
+	uint32_t diepctl;
+
+	if (!dwc2_ep_is_iso(ep_cfg)) {
+		return;
+	}
+
+	if (priv->target_frames[ep_idx] == UDC_DWC2_TARGET_FRAME_INITIAL) {
+		priv->target_frames[ep_idx] = priv->sof_num;
+		if (cfg->interval > 1) {
+			diepctl = sys_read32(diepctl_reg);
+			if (priv->target_frames[ep_idx] & 1) {
+				diepctl |= USB_DWC2_DEPCTL_SETODDFR;
+			} else {
+				diepctl |= USB_DWC2_DEPCTL_SETEVENFR;
+			}
+
+			sys_write32(diepctl, diepctl_reg);
+		}
+	}
+
+	// TODO this holy fuck
+	diepctl = sys_read32(diepctl_reg);
+	if (diepctl )
+}
+
 static inline void dwc2_handle_iepint(const struct device *dev)
 {
 	struct usb_dwc2_reg *const base = dwc2_get_base(dev);
@@ -2590,6 +2649,9 @@ static inline void dwc2_handle_iepint(const struct device *dev)
 				dwc2_handle_in_xfercompl(dev, n);
 			}
 
+			if (status & USB_DWC2_DIEPINT_NAKINTRPT) {
+				dwc2_handle_in_nakintrpt(dev, n);
+			}
 		}
 	}