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[nrf fromlist] drivers: clock_control: nrf2: add support for global hfsll clock
Add device driver support for global hsfll clock. Upstream PR #: 81735 Signed-off-by: Bjarki Arge Andreasen <[email protected]>
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4 files changed

+306
-15
lines changed

4 files changed

+306
-15
lines changed

‎drivers/clock_control/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_cont
3535
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c)
3636
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c)
3737
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RPI_PICO clock_control_rpi_pico.c)
38+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL clock_control_nrf2_global_hsfll.c)
3839

3940
if(CONFIG_CLOCK_CONTROL_NRF2)
4041
zephyr_library_sources(clock_control_nrf2_common.c)

‎drivers/clock_control/Kconfig.nrf‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -193,4 +193,17 @@ config CLOCK_CONTROL_NRF2_NRFS_CLOCK_TIMEOUT_MS
193193
int "Timeout waiting for nrfs clock service callback in milliseconds"
194194
default 1000
195195

196+
config CLOCK_CONTROL_NRF2_GLOBAL_HSFLL
197+
bool "Clock control for global HSFLL"
198+
depends on NRFS_GDFS_SERVICE_ENABLED
199+
default y
200+
201+
if CLOCK_CONTROL_NRF2_GLOBAL_HSFLL
202+
203+
config CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_TIMEOUT_MS
204+
int "Frequency request timeout in milliseconds"
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default 10000
206+
207+
endif # CLOCK_CONTROL_NRF2_GLOBAL_HSFLL
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196209
endif # CLOCK_CONTROL_NRF2

‎drivers/clock_control/clock_control_nrf2_global_hsfll.c‎

Lines changed: 291 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,291 @@
1+
/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
3+
* SPDX-License-Identifier: Apache-2.0
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*/
5+
6+
#define DT_DRV_COMPAT nordic_nrf_hsfll_global
7+
8+
#include "clock_control_nrf2_common.h"
9+
#include <zephyr/devicetree.h>
10+
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
11+
#include <nrfs_gdfs.h>
12+
13+
#include <zephyr/logging/log.h>
14+
LOG_MODULE_DECLARE(clock_control_nrf2, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
15+
16+
#define GLOBAL_HSFLL_CLOCK_FREQUENCIES \
17+
DT_INST_PROP(0, supported_clock_frequencies)
18+
19+
#define GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(idx) \
20+
DT_INST_PROP_BY_IDX(0, supported_clock_frequencies, idx)
21+
22+
#define GLOBAL_HSFLL_CLOCK_FREQUENCIES_SIZE \
23+
DT_INST_PROP_LEN(0, supported_clock_frequencies)
24+
25+
#define GLOBAL_HSFLL_FREQ_REQ_TIMEOUT \
26+
K_MSEC(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_TIMEOUT_MS)
27+
28+
BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_SIZE == 4);
29+
BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(0) == 64000000);
30+
BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(1) == 128000000);
31+
BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(2) == 256000000);
32+
BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(3) == 320000000);
33+
BUILD_ASSERT(GDFS_FREQ_COUNT == 4);
34+
BUILD_ASSERT(GDFS_FREQ_HIGH == 0);
35+
BUILD_ASSERT(GDFS_FREQ_MEDHIGH == 1);
36+
BUILD_ASSERT(GDFS_FREQ_MEDLOW == 2);
37+
BUILD_ASSERT(GDFS_FREQ_LOW == 3);
38+
39+
struct global_hsfll_dev_config {
40+
uint32_t clock_frequencies[GLOBAL_HSFLL_CLOCK_FREQUENCIES_SIZE];
41+
};
42+
43+
struct global_hsfll_dev_data {
44+
STRUCT_CLOCK_CONFIG(global_hsfll, GLOBAL_HSFLL_CLOCK_FREQUENCIES_SIZE) clk_cfg;
45+
const struct device *dev;
46+
struct k_work evt_work;
47+
struct k_sem evt_sem;
48+
nrfs_gdfs_evt_type_t evt;
49+
struct k_work_delayable timeout_dwork;
50+
};
51+
52+
static uint32_t global_hsfll_get_max_clock_frequency(const struct device *dev)
53+
{
54+
const struct global_hsfll_dev_config *dev_config = dev->config;
55+
56+
return dev_config->clock_frequencies[ARRAY_SIZE(dev_config->clock_frequencies) - 1];
57+
}
58+
59+
static struct onoff_manager *global_hsfll_find_mgr(const struct device *dev,
60+
const struct nrf_clock_spec *spec)
61+
{
62+
struct global_hsfll_dev_data *dev_data = dev->data;
63+
const struct global_hsfll_dev_config *dev_config = dev->config;
64+
uint32_t frequency;
65+
66+
if (!spec) {
67+
return &dev_data->clk_cfg.onoff[0].mgr;
68+
}
69+
70+
if (spec->accuracy || spec->precision) {
71+
LOG_ERR("invalid specification of accuracy or precision");
72+
return NULL;
73+
}
74+
75+
frequency = spec->frequency == NRF_CLOCK_CONTROL_FREQUENCY_MAX
76+
? global_hsfll_get_max_clock_frequency(dev)
77+
: spec->frequency;
78+
79+
for (uint8_t i = 0; i < ARRAY_SIZE(dev_config->clock_frequencies); i++) {
80+
if (dev_config->clock_frequencies[i] < frequency) {
81+
continue;
82+
}
83+
84+
return &dev_data->clk_cfg.onoff[i].mgr;
85+
}
86+
87+
LOG_ERR("invalid frequency");
88+
return NULL;
89+
}
90+
91+
static int api_request_global_hsfll(const struct device *dev,
92+
const struct nrf_clock_spec *spec,
93+
struct onoff_client *cli)
94+
{
95+
struct onoff_manager *mgr = global_hsfll_find_mgr(dev, spec);
96+
97+
if (mgr) {
98+
return onoff_request(mgr, cli);
99+
}
100+
101+
return -EINVAL;
102+
}
103+
104+
static int api_release_global_hsfll(const struct device *dev,
105+
const struct nrf_clock_spec *spec)
106+
{
107+
struct onoff_manager *mgr = global_hsfll_find_mgr(dev, spec);
108+
109+
if (mgr) {
110+
return onoff_release(mgr);
111+
}
112+
113+
return -EINVAL;
114+
}
115+
116+
static int api_cancel_or_release_global_hsfll(const struct device *dev,
117+
const struct nrf_clock_spec *spec,
118+
struct onoff_client *cli)
119+
{
120+
struct onoff_manager *mgr = global_hsfll_find_mgr(dev, spec);
121+
122+
if (mgr) {
123+
return onoff_cancel_or_release(mgr, cli);
124+
}
125+
126+
return -EINVAL;
127+
}
128+
129+
static struct nrf_clock_control_driver_api driver_api = {
130+
.std_api = {
131+
.on = api_nosys_on_off,
132+
.off = api_nosys_on_off,
133+
},
134+
.request = api_request_global_hsfll,
135+
.release = api_release_global_hsfll,
136+
.cancel_or_release = api_cancel_or_release_global_hsfll,
137+
};
138+
139+
static enum gdfs_frequency_setting global_hsfll_freq_idx_to_nrfs_freq(const struct device *dev,
140+
uint8_t freq_idx)
141+
{
142+
const struct global_hsfll_dev_config *dev_config = dev->config;
143+
144+
return ARRAY_SIZE(dev_config->clock_frequencies) - 1 - freq_idx;
145+
}
146+
147+
static const char *global_hsfll_gdfs_freq_to_str(enum gdfs_frequency_setting freq)
148+
{
149+
switch (freq) {
150+
case GDFS_FREQ_HIGH:
151+
return "GDFS_FREQ_HIGH";
152+
case GDFS_FREQ_MEDHIGH:
153+
return "GDFS_FREQ_MEDHIGH";
154+
case GDFS_FREQ_MEDLOW:
155+
return "GDFS_FREQ_MEDLOW";
156+
case GDFS_FREQ_LOW:
157+
return "GDFS_FREQ_LOW";
158+
default:
159+
break;
160+
}
161+
162+
return "UNKNOWN";
163+
}
164+
165+
static void global_hsfll_work_handler(struct k_work *work)
166+
{
167+
struct global_hsfll_dev_data *dev_data =
168+
CONTAINER_OF(work, struct global_hsfll_dev_data, clk_cfg.work);
169+
const struct device *dev = dev_data->dev;
170+
uint8_t freq_idx;
171+
enum gdfs_frequency_setting target_freq;
172+
nrfs_err_t err;
173+
174+
freq_idx = clock_config_update_begin(work);
175+
target_freq = global_hsfll_freq_idx_to_nrfs_freq(dev, freq_idx);
176+
177+
LOG_DBG("requesting %s", global_hsfll_gdfs_freq_to_str(target_freq));
178+
err = nrfs_gdfs_request_freq(target_freq, dev_data);
179+
if (err != NRFS_SUCCESS) {
180+
clock_config_update_end(&dev_data->clk_cfg, -EIO);
181+
return;
182+
}
183+
184+
k_work_schedule(&dev_data->timeout_dwork, GLOBAL_HSFLL_FREQ_REQ_TIMEOUT);
185+
}
186+
187+
static void global_hsfll_evt_handler(struct k_work *work)
188+
{
189+
struct global_hsfll_dev_data *dev_data =
190+
CONTAINER_OF(work, struct global_hsfll_dev_data, evt_work);
191+
int rc;
192+
193+
k_work_cancel_delayable(&dev_data->timeout_dwork);
194+
rc = dev_data->evt == NRFS_GDFS_EVT_FREQ_CONFIRMED ? 0 : -EIO;
195+
clock_config_update_end(&dev_data->clk_cfg, rc);
196+
}
197+
198+
static void global_hfsll_nrfs_gdfs_init_evt_handler(nrfs_gdfs_evt_t const *p_evt, void *context)
199+
{
200+
struct global_hsfll_dev_data *dev_data = context;
201+
202+
dev_data->evt = p_evt->type;
203+
k_sem_give(&dev_data->evt_sem);
204+
}
205+
206+
static void global_hfsll_nrfs_gdfs_evt_handler(nrfs_gdfs_evt_t const *p_evt, void *context)
207+
{
208+
struct global_hsfll_dev_data *dev_data = context;
209+
210+
if (k_work_is_pending(&dev_data->evt_work)) {
211+
return;
212+
}
213+
214+
dev_data->evt = p_evt->type;
215+
k_work_submit(&dev_data->evt_work);
216+
}
217+
218+
static void global_hsfll_timeout_handler(struct k_work *work)
219+
{
220+
struct k_work_delayable *dwork = k_work_delayable_from_work(work);
221+
struct global_hsfll_dev_data *dev_data =
222+
CONTAINER_OF(dwork, struct global_hsfll_dev_data, timeout_dwork);
223+
224+
clock_config_update_end(&dev_data->clk_cfg, -ETIMEDOUT);
225+
}
226+
227+
static int global_hfsll_init(const struct device *dev)
228+
{
229+
struct global_hsfll_dev_data *dev_data = dev->data;
230+
nrfs_err_t err;
231+
int rc;
232+
233+
k_sem_init(&dev_data->evt_sem, 0, 1);
234+
k_work_init_delayable(&dev_data->timeout_dwork, global_hsfll_timeout_handler);
235+
k_work_init(&dev_data->evt_work, global_hsfll_evt_handler);
236+
237+
err = nrfs_gdfs_init(global_hfsll_nrfs_gdfs_init_evt_handler);
238+
if (err != NRFS_SUCCESS) {
239+
return -EIO;
240+
}
241+
242+
LOG_DBG("initial request %s", global_hsfll_gdfs_freq_to_str(GDFS_FREQ_LOW));
243+
err = nrfs_gdfs_request_freq(GDFS_FREQ_LOW, dev_data);
244+
if (err != NRFS_SUCCESS) {
245+
return -EIO;
246+
}
247+
248+
rc = k_sem_take(&dev_data->evt_sem, GLOBAL_HSFLL_FREQ_REQ_TIMEOUT);
249+
if (rc) {
250+
return -EIO;
251+
}
252+
253+
if (dev_data->evt != NRFS_GDFS_EVT_FREQ_CONFIRMED) {
254+
return -EIO;
255+
}
256+
257+
nrfs_gdfs_uninit();
258+
259+
rc = clock_config_init(&dev_data->clk_cfg,
260+
ARRAY_SIZE(dev_data->clk_cfg.onoff),
261+
global_hsfll_work_handler);
262+
if (rc < 0) {
263+
return rc;
264+
}
265+
266+
err = nrfs_gdfs_init(global_hfsll_nrfs_gdfs_evt_handler);
267+
if (err != NRFS_SUCCESS) {
268+
return -EIO;
269+
}
270+
271+
return 0;
272+
}
273+
274+
static struct global_hsfll_dev_data driver_data = {
275+
.dev = DEVICE_DT_INST_GET(0),
276+
};
277+
278+
static const struct global_hsfll_dev_config driver_config = {
279+
GLOBAL_HSFLL_CLOCK_FREQUENCIES
280+
};
281+
282+
DEVICE_DT_INST_DEFINE(
283+
0,
284+
global_hfsll_init,
285+
NULL,
286+
&driver_data,
287+
&driver_config,
288+
POST_KERNEL,
289+
99,
290+
&driver_api
291+
);

‎drivers/clock_control/clock_control_nrf2_hsfll.c‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@
88
#include "clock_control_nrf2_common.h"
99
#include <zephyr/devicetree.h>
1010
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
11-
#include <hal/nrf_hsfll.h>
1211

1312
#include <zephyr/logging/log.h>
1413
LOG_MODULE_DECLARE(clock_control_nrf2, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
@@ -48,7 +47,7 @@ static const struct clock_options {
4847
};
4948

5049
struct hsfll_dev_data {
51-
STRUCT_CLOCK_CONFIG(hsfll, ARRAY_SIZE(clock_options)) clk_cfg;
50+
STRUCT_CLOCK_CONFIG(global_hsfll, ARRAY_SIZE(clock_options)) clk_cfg;
5251
struct k_timer timer;
5352
};
5453

@@ -183,18 +182,6 @@ static int api_cancel_or_release_hsfll(const struct device *dev,
183182
#endif
184183
}
185184

186-
static int api_get_rate_hsfll(const struct device *dev,
187-
clock_control_subsys_t sys,
188-
uint32_t *rate)
189-
{
190-
ARG_UNUSED(dev);
191-
ARG_UNUSED(sys);
192-
193-
*rate = nrf_hsfll_clkctrl_mult_get(NRF_HSFLL) * MHZ(16);
194-
195-
return 0;
196-
}
197-
198185
static int hsfll_init(const struct device *dev)
199186
{
200187
#ifdef CONFIG_NRFS_DVFS_LOCAL_DOMAIN
@@ -221,7 +208,6 @@ static struct nrf_clock_control_driver_api hsfll_drv_api = {
221208
.std_api = {
222209
.on = api_nosys_on_off,
223210
.off = api_nosys_on_off,
224-
.get_rate = api_get_rate_hsfll,
225211
},
226212
.request = api_request_hsfll,
227213
.release = api_release_hsfll,

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