[nrf fromlist] drivers: serial: nrfx_uarte: enable cross domain pins for nRF54L15

UARTE20 and UARTE21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.

Upstream PR #: 90197

Signed-off-by: Michał Stasiak <[email protected]>

Author: mstasiaknordic

drivers/serial/uart_nrfx_uarte.c

@@ -148,6 +148,27 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_CLOCK_CONTROL));
  */
 #define UARTE_ANY_HIGH_SPEED (UARTE_FOR_EACH_INSTANCE(INSTANCE_IS_HIGH_SPEED, (||), (0)))
 
+#define UARTE_PINS_CROSS_DOMAIN(unused, prefix, idx, _)			\
+	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(UARTE(prefix##idx)),	\
+		   (UARTE_PROP(idx, cross_domain_pins_supported)),	\
+		   (0))
+
+#if UARTE_FOR_EACH_INSTANCE(UARTE_PINS_CROSS_DOMAIN, (||), (0))
+#include <hal/nrf_gpio.h>
+/* Certain UARTE instances support usage of cross domain pins in form of dedicated pins on
+ * a port different from the default one.
+ */
+#define UARTE_CROSS_DOMAIN_PINS_SUPPORTED 1
+#endif
+
+#if UARTE_CROSS_DOMAIN_PINS_SUPPORTED && defined(CONFIG_NRF_SYS_EVENT)
+#include <nrf_sys_event.h>
+/* To use cross domain pins, constant latency mode needs to be applied, which is
+ * handled via nrf_sys_event requests.
+ */
+#define UARTE_CROSS_DOMAIN_PINS_HANDLE 1
+#endif
+
 #ifdef UARTE_ANY_CACHE
 /* uart120 instance does not retain BAUDRATE register when ENABLE=0. When this instance
  * is used then baudrate must be set after enabling the peripheral and not before.
@@ -371,6 +392,10 @@ struct uarte_nrfx_config {
 #endif
 	uint8_t *poll_out_byte;
 	uint8_t *poll_in_byte;
+#if UARTE_CROSS_DOMAIN_PINS_SUPPORTED
+	bool cross_domain;
+	int8_t default_port;
+#endif
 };
 
 /* Using Macro instead of static inline function to handle NO_OPTIMIZATIONS case
@@ -444,6 +469,32 @@ static void uarte_disable_locked(const struct device *dev, uint32_t dis_mask)
 	nrf_uarte_disable(get_uarte_instance(dev));
 }
 
+#if UARTE_CROSS_DOMAIN_PINS_SUPPORTED
+static bool uarte_has_cross_domain_connection(const struct uarte_nrfx_config *config)
+{
+	const struct pinctrl_dev_config *pcfg = config->pcfg;
+	const struct pinctrl_state *state;
+	int ret;
+
+	ret = pinctrl_lookup_state(pcfg, PINCTRL_STATE_DEFAULT, &state);
+	if (ret < 0) {
+		LOG_ERR("Unable to read pin state");
+		return false;
+	}
+
+	for (uint8_t i = 0U; i < state->pin_cnt; i++) {
+		uint32_t pin = NRF_GET_PIN(state->pins[i]);
+
+		if ((pin != NRF_PIN_DISCONNECTED) &&
+		    (nrf_gpio_pin_port_number_extract(&pin) != config->default_port)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+#endif
+
 #if defined(UARTE_ANY_NONE_ASYNC) && !defined(CONFIG_UART_NRFX_UARTE_NO_IRQ)
 /**
  * @brief Interrupt service routine.
@@ -727,6 +778,19 @@ static void uarte_periph_enable(const struct device *dev)
 #ifdef CONFIG_SOC_NRF54H20_GPD
 	nrf_gpd_retain_pins_set(config->pcfg, false);
 #endif
+#if UARTE_CROSS_DOMAIN_PINS_SUPPORTED
+	if (config->cross_domain && uarte_has_cross_domain_connection(config)) {
+#if UARTE_CROSS_DOMAIN_PINS_HANDLE
+		int err;
+
+		err = nrf_sys_event_request_global_constlat();
+		(void)err;
+		__ASSERT_NO_MSG(err >= 0);
+#else
+		__ASSERT(false, "NRF_SYS_EVENT needs to be enabled to use cross domain pins.\n");
+#endif
+	}
+#endif
 #if UARTE_BAUDRATE_RETENTION_WORKAROUND
 	nrf_uarte_baudrate_set(uarte,
 		COND_CODE_1(CONFIG_UART_USE_RUNTIME_CONFIGURE,
@@ -2411,6 +2475,19 @@ static void uarte_pm_suspend(const struct device *dev)
 #ifdef CONFIG_SOC_NRF54H20_GPD
 	nrf_gpd_retain_pins_set(cfg->pcfg, true);
 #endif
+#if UARTE_CROSS_DOMAIN_PINS_SUPPORTED
+	if (cfg->cross_domain && uarte_has_cross_domain_connection(cfg)) {
+#if UARTE_CROSS_DOMAIN_PINS_HANDLE
+		int err;
+
+		err = nrf_sys_event_release_global_constlat();
+		(void)err;
+		__ASSERT_NO_MSG(err >= 0);
+#else
+		__ASSERT(false, "NRF_SYS_EVENT needs to be enabled to use cross domain pins.\n");
+#endif
+	}
+#endif
 
 	nrf_uarte_disable(uarte);
 
@@ -2698,6 +2775,11 @@ static int uarte_instance_init(const struct device *dev,
 				.accuracy = 0,				       \
 				.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,\
 				},))					       \
+		IF_ENABLED(UARTE_PINS_CROSS_DOMAIN(_, /*empty*/, idx, _),      \
+			(.cross_domain = true,				       \
+			 .default_port =				       \
+				DT_PROP_OR(DT_PHANDLE(UARTE(idx),	       \
+					default_gpio_port), port, -1),))       \
 	};								       \
 	UARTE_DIRECT_ISR_DECLARE(idx)					       \
 	static int uarte_##idx##_init(const struct device *dev)		       \

dts/bindings/serial/nordic,nrf-uarte.yaml

@@ -14,3 +14,13 @@ properties:
     type: boolean
     description: |
       UARTE has RX frame timeout HW feature.
+
+  default-gpio-port:
+    type: phandle
+    description: |
+      UARTE default GPIO port.
+
+  cross-domain-pins-supported:
+    type: boolean
+    description: |
+      UARTE allows usage of cross domain pins with constant latency mode required.

dts/vendor/nordic/nrf54l_05_10_15.dtsi

@@ -322,6 +322,8 @@
 				status = "disabled";
 				endtx-stoptx-supported;
 				frame-timeout-supported;
+				default-gpio-port = <&gpio1>;
+				cross-domain-pins-supported;
 			};
 
 			i2c21: i2c@c7000 {
@@ -361,6 +363,8 @@
 				status = "disabled";
 				endtx-stoptx-supported;
 				frame-timeout-supported;
+				default-gpio-port = <&gpio1>;
+				cross-domain-pins-supported;
 			};
 
 			i2c22: i2c@c8000 {

tests/drivers/uart/uart_elementary/boards/nrf54l15dk_nrf54l15_cpuapp_cross_domain.overlay

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>,
+				<NRF_PSEL(UART_RTS, 2, 10)>,
+				<NRF_PSEL(UART_CTS, 2, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>,
+				<NRF_PSEL(UART_RTS, 2, 10)>,
+				<NRF_PSEL(UART_CTS, 2, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};

tests/drivers/uart/uart_elementary/testcase.yaml

@@ -97,3 +97,12 @@ tests:
     extra_configs:
       - CONFIG_DUAL_UART_TEST=y
       - CONFIG_SETUP_MISMATCH_TEST=y
+  drivers.uart.uart_elementary_cross_domain:
+    filter: CONFIG_SERIAL_SUPPORT_INTERRUPT
+    harness_config:
+      fixture: uart_p1_p2_loopback
+    platform_allow:
+      - nrf54l15dk/nrf54l15/cpuapp
+    extra_args: DTC_OVERLAY_FILE="boards/nrf54l15dk_nrf54l15_cpuapp_cross_domain.overlay"
+    extra_configs:
+      - CONFIG_NRF_SYS_EVENT=y