dts: drivers: nordic: Don't manage hsfll120 from drivers

The hsfll120 is requested automatically by hardware which needs it,
CLOCK_CONTROL can be used to set to lower the frequency it runs at,
but this is a quirk which may be handled by the application if
desired. Disable the global clocks and remove references to the
hsfll120 from devices in the devicetree, and update samples which
specifically test the control of the clocks using CLOCK_CONTROL
to enable them.

Signed-off-by: Bjarki Arge Andreasen <[email protected]>

Author: bjarki-andreasen

drivers/can/can_nrf.c

@@ -139,6 +139,11 @@ static int configure_hsfll(const struct device *dev, bool on)
 	const struct can_nrf_config *config = mcan_config->custom;
 	struct nrf_clock_spec spec = { 0 };
 
+	if (config->hsfll == NULL) {
+		/* Frequency fixed at max */
+		return 0;
+	}
+
 	/* If CAN is on, HSFLL frequency >= AUXPLL frequency */
 	if (on) {
 		int ret;
@@ -158,7 +163,7 @@ static int can_nrf_init(const struct device *dev)
 	const struct can_nrf_config *config = mcan_config->custom;
 	int ret;
 
-	if (!device_is_ready(config->auxpll) || !device_is_ready(config->hsfll)) {
+	if (!device_is_ready(config->auxpll)) {
 		return -ENODEV;
 	}
 
@@ -215,7 +220,7 @@ static int can_nrf_init(const struct device *dev)
 		.mram = CAN_MCAN_DT_INST_MRAM_ADDR(n),                                             \
 		.auxpll = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, auxpll)),                   \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
-		.hsfll = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, hsfll)),                     \
+		.hsfll = DEVICE_DT_GET_OR_NULL(DT_INST_CLOCKS_CTLR_BY_NAME(n, hsfll)),             \
 		.irq = DT_INST_IRQN(n),                                                            \
 		.irq_configure = can_nrf_irq_configure##n,                                         \
 	};                                                                                         \

dts/arm/nordic/nrf54h20_cpuapp.dtsi

@@ -67,18 +67,6 @@ wdt011: &cpuapp_wdt011 {};
 	interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>;
 };
 
-&fll16m {
-	status = "okay";
-};
-
-&hsfll120 {
-	status = "okay";
-};
-
-&lfclk {
-	status = "okay";
-};
-
 &gdpwr {
 	status = "okay";
 };

dts/arm/nordic/nrf54h20_cpurad.dtsi

@@ -108,18 +108,6 @@ wdt011: &cpurad_wdt011 {};
 	status = "okay";
 };
 
-&fll16m {
-	status = "okay";
-};
-
-&hsfll120 {
-	status = "okay";
-};
-
-&lfclk {
-	status = "okay";
-};
-
 &gdpwr {
 	status = "okay";
 };

dts/vendor/nordic/nrf54h20.dtsi

@@ -734,7 +734,6 @@
 				cc-num = <6>;
 				interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
 				max-bit-width = <32>;
-				clocks = <&hsfll120>;
 				prescaler = <0>;
 			};
 
@@ -745,7 +744,6 @@
 				cc-num = <6>;
 				interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>;
 				max-bit-width = <32>;
-				clocks = <&hsfll120>;
 				prescaler = <0>;
 			};
 
@@ -754,7 +752,6 @@
 				reg = <0x8e4000 0x1000>;
 				status = "disabled";
 				interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>;
-				clocks = <&hsfll120>;
 				#pwm-cells = <3>;
 				idleout-supported;
 			};
@@ -765,7 +762,6 @@
 				status = "disabled";
 				easydma-maxcnt-bits = <15>;
 				interrupts = <229 NRF_DEFAULT_IRQ_PRIORITY>;
-				clocks = <&hsfll120>;
 				max-frequency = <DT_FREQ_M(32)>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -778,7 +774,6 @@
 				status = "disabled";
 				easydma-maxcnt-bits = <15>;
 				interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>;
-				clocks = <&hsfll120>;
 				max-frequency = <DT_FREQ_M(32)>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -792,7 +787,6 @@
 				reg = <0x8e6000 0x1000>;
 				status = "disabled";
 				interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>;
-				clocks = <&hsfll120>;
 				endtx-stoptx-supported;
 				frame-timeout-supported;
 				zephyr,pm-device-runtime-auto;
@@ -804,7 +798,6 @@
 				status = "disabled";
 				easydma-maxcnt-bits = <15>;
 				interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>;
-				clocks = <&hsfll120>;
 				max-frequency = <DT_FREQ_M(32)>;
 				#address-cells = <1>;
 				#size-cells = <0>;

samples/boards/nordic/clock_control/configs/cpuapp_hsfll.overlay

@@ -9,3 +9,7 @@
 		sample-clock = &cpuapp_hsfll;
 	};
 };
+
+&cpuapp_hsfll {
+	status = "okay";
+};

samples/boards/nordic/clock_control/configs/fll16m.overlay

@@ -9,3 +9,7 @@
 		sample-clock = &fll16m;
 	};
 };
+
+&fll16m {
+	status = "okay";
+};

samples/boards/nordic/clock_control/configs/global_hsfll.overlay

@@ -9,3 +9,7 @@
 		sample-clock = &hsfll120;
 	};
 };
+
+&hsfll120 {
+	status = "okay";
+};

samples/boards/nordic/clock_control/configs/lfclk.overlay

@@ -9,3 +9,7 @@
 		sample-clock = &lfclk;
 	};
 };
+
+&lfclk {
+	status = "okay";
+};

samples/boards/nordic/clock_control/configs/uart135.overlay

@@ -14,3 +14,7 @@
 	status = "okay";
 	memory-regions = <&cpuapp_dma_region>;
 };
+
+&fll16m {
+	status = "okay";
+};

tests/drivers/clock_control/nrf_clock_control/boards/nrf54h20dk_nrf54h20_cpuapp.overlay

@@ -0,0 +1,21 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&fll16m {
+	status = "okay";
+};
+
+&hsfll120 {
+	status = "okay";
+};
+
+&lfclk {
+	status = "okay";
+};
+
+&canpll {
+	status = "okay";
+};