[nrf fromlist] soc: nordic: dmm: Fix DMM_REG_ALIGN_SIZE macro when CONFIG_DCACHE=n

Upstream PR #: 80676

Make sure this expansion doesn't include `CONFIG_DCACHE_LINE_SIZE`,
which would be undefined and produce a build error.

Signed-off-by: Grzegorz Swiderski <[email protected]>
(cherry picked from commit a2988cae16afc4444d98f9fd9453271a250ac63c)

Author: 57300

soc/nordic/common/dmm.h

@@ -34,7 +34,9 @@ extern "C" {
  * Cache line alignment is required if region is cacheable and data cache is enabled.
  */
 #define DMM_REG_ALIGN_SIZE(node_id) \
-	(DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t))
+	COND_CODE_0(CONFIG_DCACHE,  \
+	   (sizeof(uint8_t)),       \
+	   (DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t)))
 
 /* Determine required alignment of the data buffers in memory region
  * associated with specified device node.