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[nrf fromlist] soc: nordic: dmm: Fix DMM_REG_ALIGN_SIZE macro when CONFIG_DCACHE=n
Upstream PR #: 80676 Make sure this expansion doesn't include `CONFIG_DCACHE_LINE_SIZE`, which would be undefined and produce a build error. Signed-off-by: Grzegorz Swiderski <[email protected]> (cherry picked from commit a2988cae16afc4444d98f9fd9453271a250ac63c)
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soc/nordic/common/dmm.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,9 @@ extern "C" {
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* Cache line alignment is required if region is cacheable and data cache is enabled.
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*/
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#define DMM_REG_ALIGN_SIZE(node_id) \
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(DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t))
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COND_CODE_0(CONFIG_DCACHE, \
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(sizeof(uint8_t)), \
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(DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t)))
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/* Determine required alignment of the data buffers in memory region
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* associated with specified device node.

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