[nrf fromtree] boards: arm: add support for MPS4 Corstone-320

Add initial support for the MPS4 Corstone-320 platform, including board
and SoC definitions. This platform features a Cortex-M85 CPU with an
Ethos-U85 NPU and runs in simulation using the FVP_Corstone_SSE-320
Fixed Virtual Platform.

Signed-off-by: Sudan Landge <[email protected]>
(cherry picked from commit d1e830f)

Author: wearyzen

boards/arm/mps4/Kconfig.defconfig

@@ -0,0 +1,23 @@
+# Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MPS4_CORSTONE320_FVP
+
+if SERIAL
+
+config UART_INTERRUPT_DRIVEN
+	default y
+
+endif # SERIAL
+
+if ROMSTART_RELOCATION_ROM && BOARD_MPS4_CORSTONE320_FVP
+
+config ROMSTART_REGION_ADDRESS
+	default $(dt_nodelabel_reg_addr_hex,itcm)
+
+config ROMSTART_REGION_SIZE
+	default $(dt_nodelabel_reg_size_hex,itcm,0,k)
+
+endif
+
+endif

boards/arm/mps4/Kconfig.mps4

@@ -0,0 +1,6 @@
+# Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MPS4
+	select SOC_SERIES_MPS4
+	select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS

boards/arm/mps4/board.cmake

@@ -0,0 +1,45 @@
+# Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# Default emulation:
+#     FVP  is used by default for corstone320/fvp.
+#
+
+
+if(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS)
+  set(SUPPORTED_EMU_PLATFORMS armfvp)
+  set(ARMFVP_BIN_NAME FVP_Corstone_SSE-320)
+  if(CONFIG_BOARD_MPS4_CORSTONE320_FVP)
+    set(ARMFVP_FLAGS
+      # default is '0x11000000' but should match cpu<i>.INITSVTOR which is 0.
+      -C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0
+      # default is 0x8, this change is needed since we split flash into itcm
+      # and sram and it reduces the number of available mpu regions causing a
+      # few MPU tests to fail.
+      -C mps4_board.subsystem.cpu0.MPU_S=16
+    )
+  endif()
+endif()
+
+if(CONFIG_BUILD_WITH_TFM)
+  set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex)
+endif()
+
+# FVP Parameters
+# -C indicate a config option in the form of:
+#   instance.parameter=value
+# Run the FVP with --list-params to list all options
+set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
+  -C mps4_board.uart0.out_file=-
+  -C mps4_board.uart0.unbuffered_output=1
+  -C mps4_board.uart1.out_file=-
+  -C mps4_board.uart1.unbuffered_output=1
+  -C mps4_board.uart2.out_file=-
+  -C mps4_board.uart2.unbuffered_output=1
+  -C mps4_board.visualisation.disable-visualisation=1
+  -C mps4_board.telnetterminal0.start_telnet=0
+  -C mps4_board.telnetterminal1.start_telnet=0
+  -C mps4_board.telnetterminal2.start_telnet=0
+  -C vis_hdlcd.disable_visualisation=1
+  )

boards/arm/mps4/board.yml

@@ -0,0 +1,10 @@
+board:
+  name: mps4
+  full_name: MPS4
+  vendor: arm
+  socs:
+  - name: 'corstone320'
+    variants:
+    - name: 'fvp'
+      variants:
+      - name: 'ns'

boards/arm/mps4/mps4_common.dtsi

@@ -0,0 +1,119 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* /dts-v1/; */
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <mem.h>
+
+/ {
+	aliases {
+		led0 = &led_0;
+		led1 = &led_1;
+		sw0 = &user_button_0;
+		sw1 = &user_button_1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_0: led_0 {
+			gpios = <&gpio_led0 0>;
+			label = "USERLED0";
+		};
+
+		led_1: led_1 {
+			gpios = <&gpio_led0 1>;
+			label = "USERLED1";
+		};
+
+		led_2: led_2 {
+			gpios = <&gpio_led0 2>;
+			label = "USERLED2";
+		};
+
+		led_3: led_3 {
+			gpios = <&gpio_led0 3>;
+			label = "USERLED3";
+		};
+
+		led_4: led_4 {
+			gpios = <&gpio_led0 4>;
+			label = "USERLED4";
+		};
+
+		led_5: led_5 {
+			gpios = <&gpio_led0 5>;
+			label = "USERLED5";
+		};
+
+		led_6: led_6 {
+			gpios = <&gpio_led0 6>;
+			label = "USERLED6";
+		};
+
+		led_7: led_7 {
+			gpios = <&gpio_led0 7>;
+			label = "USERLED7";
+		};
+
+		led_8: led_8 {
+			gpios = <&gpio_led0 8>;
+			label = "PB1LED";
+		};
+
+		led_9: led_9 {
+			gpios = <&gpio_led0 9>;
+			label = "PB2LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button_0: button_0 {
+			label = "USERPB0";
+			gpios = <&gpio_button 0>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		user_button_1: button_1 {
+			label = "USERPB1";
+			gpios = <&gpio_button 1>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	null_ptr_detect: null_ptr_detect@0 {
+		compatible = "zephyr,memory-region";
+		/* 0 - CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE> */
+		reg = <0x0 0x400>;
+		zephyr,memory-region = "NULL_PTR_DETECT";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>;
+	};
+
+	/* DDR4 - 2G, alternates non-secure/secure every 256M */
+	ddr4: memory@60000000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)
+		       0x70000000 DT_SIZE_M(256)
+		       0x80000000 DT_SIZE_M(256)
+		       0x90000000 DT_SIZE_M(256)
+		       0xa0000000 DT_SIZE_M(256)
+		       0xb0000000 DT_SIZE_M(256)
+		       0xc0000000 DT_SIZE_M(256)
+		       0xd0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};