[nrf toup] soc: add ironside boot report

Signed-off-by: Håkon Amundsen <[email protected]>

Author: hakonfam

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts

@@ -6,8 +6,17 @@
 
 #include "nrf54h20dk_nrf54h20_cpuapp.dts"
 
-/delete-node/&cpurad_rx_partitions;
+/* The code partitions are re-defined below, so delete the parent node. */
 /delete-node/&cpuapp_rx_partitions;
+
+/* No radio support for IRON variant, don't allocate MRAM. */
+/delete-node/&cpurad_rx_partitions;
+
+/* All of ram0x goes to cpuapp, delete these nodes to re-define below. */
+/delete-node/&cpuapp_ram0x_region;
+/delete-node/&cpurad_ram0x_region;
+
+/* IPC mechanism for IRON variant differs, delete the old node. */
 /delete-node/&cpusec_cpuapp_ipc;
 
 /* This is not yet an exhaustive memory map, and contain only a minimum required to boot
@@ -22,15 +31,40 @@
 		#size-cells = <1>;
 
 		cpuapp_slot0_partition: partition@2c000 {
-			reg = <0x2c000 DT_SIZE_K(480)>;
+			reg = <0x2c000 DT_SIZE_K(736)>;
+		};
+
+		cpuppr_code_partition: partition@e4000 {
+			reg = <0xe4000 DT_SIZE_K(64)>;
+		};
+
+		cpuflpr_code_partition: partition@f4000 {
+			reg = <0xf4000 DT_SIZE_K(48)>;
+		};
+	};
+};
+
+/ {
+	reserved-memory {
+		cpuapp_ram0x_region: memory@2f000000 {
+			compatible = "nordic,owned-memory", "fixed-partitions";
+			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
+			reg = <0x2f000000 DT_SIZE_K(768)>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x2f000000 0xc0000>;
+			cpuapp_data: memory@0{
+				reg = <0x0 DT_SIZE_K(768)>;
+			};
 		};
 
-		cpuppr_code_partition: partition@a4000 {
-			reg = <0xa4000 DT_SIZE_K(64)>;
+		sysctrl_rom_report: memory@2f88ff00 {
+			reg = <0x2f88ff00 0x100>;
 		};
 
-		cpuflpr_code_partition: partition@b4000 {
-			reg = <0xb4000 DT_SIZE_K(48)>;
+		cpuapp_ironside_boot_report: memory@2f88fd00 {
+			reg = <0x2f88fd00 0x200>;
 		};
 	};
 };

soc/nordic/nrf54h/CMakeLists.txt

@@ -18,3 +18,4 @@ zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld)
 
 add_subdirectory(bicr)
 add_subdirectory(gpd)
+add_subdirectory(ironside_boot_report)

soc/nordic/nrf54h/Kconfig

@@ -74,3 +74,4 @@ config SOC_NRF54H20_CPUFLPR
 
 rsource "bicr/Kconfig"
 rsource "gpd/Kconfig"
+rsource "ironside_boot_report/Kconfig"

soc/nordic/nrf54h/ironside_boot_report/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_SOC_NRF54H20_IRONSIDE_BOOT_REPORT ironside_boot_report.c)
+zephyr_include_directories(include)

soc/nordic/nrf54h/ironside_boot_report/Kconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_NRF54H20_IRONSIDE_BOOT_REPORT
+	bool "Nordic IRONside SE boot report"
+	default y if SOC_NRF54H20_CPUAPP
+	depends on SOC_NRF54H20_IRON
+	help
+	  This option enables parsing of the Boot Report populated by Nordic IRONside SE.
+
+config SOC_NRF54H_IRONSIDE_BOOT_REPORT_MAGIC
+	hex
+	default 0xe176928d
+	help
+	  Constant used to check if an Nordic IRONside SE boot report has been written.
+

soc/nordic/nrf54h/ironside_boot_report/include/nrf/ironside_boot_report.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_NORDIC_NRF54H_IRONSIDE_BOOT_REPORT_INCLUDE_NRF_IRONSIDE_BOOT_REPORT_H_
+#define ZEPHYR_SOC_NORDIC_NRF54H_IRONSIDE_BOOT_REPORT_INCLUDE_NRF_IRONSIDE_BOOT_REPORT_H_
+
+#include <stdint.h>
+#include <stddef.h>
+
+
+/** @brief UICR error description contained in the boot report. */
+struct ironside_boot_report_uicr_error {
+	/** The type of error. A value of 0 indicates no error */
+	uint32_t error_type;
+	/** Error descrpitions specific to each type of UICR error */
+	union {
+		/** MPCCONF error */
+		struct {
+			/** The MPC error type */
+			uint32_t err;
+			/** Address to the MPC instance that triggered the error */
+			uint32_t mpc_instance_address;
+			/** The index of the MPCCONF entry that triggered the error */
+			int32_t index;
+		} mpcconf;
+		/** PERIPHCONF error */
+		struct {
+			/** The SPU error type */
+			uint32_t err;
+			/** Address to the SPU instance that triggered the error */
+			uint32_t spu_instance_address;
+			/** Address to the peripheral index of the SPU that triggered the error */
+			uint32_t peripheral;
+			/** The index of the PERIPHCONF entry that triggered the error */
+			int32_t index;
+		} periphconf;
+		/** ITS error */
+		struct {
+			uint32_t err;
+		} its;
+	} description;
+};
+
+/** @brief IRONside boot report. */
+struct ironside_boot_report {
+	/** Magic value used to identify valid boot report */
+	uint32_t magic;
+	/** Firmware version of IRONside SE. 8bit MAJOR.MINOR.PATCH.TWEAK */
+	uint32_t ironside_version_int;
+	/** Human readable extraversion of IRONside SE */
+	char ironside_extraversion[12];
+	/** Firmware version of IRONside SE recovery firmware. 8bit MAJOR.MINOR.PATCH.TWEAK */
+	uint32_t ironside_recovery_version_int;
+	/** Human readable extraversion of IRONside SE */
+	char ironside_recovery_extraversion[12];
+	/** Copy of SICR.UROT.UPDATE.STATUS.*/
+	uint32_t ironside_update_status;
+	/** See @ref ironside_boot_report_uicr_error */
+	struct ironside_boot_report_uicr_error uicr_error_description;
+	/** Data passed from booting local domain to local domain being booted */
+	uint8_t local_domain_context[32];
+	/** CSPRNG data */
+	uint8_t random_data[32];
+	/** Reserved for Future Use */
+	uint32_t rfu[64];
+};
+
+/**
+ * @brief Get a pointer to the IRONside boot report.
+ *
+ * @param[out] report Will be set to point to the IRONside boot report.
+ *
+ * @return non-negative value if success, negative value otherwise.
+ * @retval -EFAULT if the magic field in the report is incorrect.
+ * @retval -EINVAL if @ref report is NULL.
+ */
+int ironside_boot_report_get(const struct ironside_boot_report **report);
+
+#endif /* ZEPHYR_SOC_NORDIC_NRF54H_IRONSIDE_BOOT_REPORT_INCLUDE_NRF_IRONSIDE_BOOT_REPORT_H_ */

soc/nordic/nrf54h/ironside_boot_report/ironside_boot_report.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr/devicetree.h>
+#include <nrf/ironside_boot_report.h>
+
+#define IRONSIDE_BOOT_REPORT_ADDR DT_REG_ADDR(DT_NODELABEL(cpuapp_ironside_boot_report))
+#define IRONSIDE_BOOT_REPORT_MAGIC CONFIG_SOC_NRF54H_IRONSIDE_BOOT_REPORT_MAGIC
+
+int ironside_boot_report_get(const struct ironside_boot_report **report)
+{
+	const struct ironside_boot_report *tmp_report =
+		(const struct ironside_boot_report *)IRONSIDE_BOOT_REPORT_ADDR;
+
+	if (tmp_report->magic != IRONSIDE_BOOT_REPORT_MAGIC) {
+		return -EINVAL;
+	}
+
+	*report = tmp_report;
+
+	return 0;
+}