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[nrf fromlist] soc: board: Add nRF54L20 SOC and board
Add necessary files to run nRF54L20 target Upstream PR: zephyrproject-rtos/zephyr#76332 Signed-off-by: Karol Lasończyk <[email protected]>
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‎boards/nordic/nrf54l20pdk/Kconfig‎

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# nRF54L20 PDK board configuration
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_NRF54L20PDK_NRF54L20_CPUAPP
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config BOARD_ENABLE_DCDC
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bool "DCDC mode"
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select SOC_NRF54L_VREG_MAIN_DCDC
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default y
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endif # BOARD_NRF54L20PDK_NRF54L20_CPUAPP

‎boards/nordic/nrf54l20pdk/Kconfig.defconfig‎

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_NRF54L20PDK_NRF54L20_CPUAPP
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config BT_CTLR
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default BT
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config ROM_START_OFFSET
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default 0x800 if BOOTLOADER_MCUBOOT
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config SOC_NRF54LX_SKIP_CLOCK_CONFIG
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default y
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config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE
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default y
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config SOC_NRF54LX_SKIP_TAMPC_SETUP
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default y
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endif # BOARD_NRF54L20PDK_NRF54L20_CPUAPP

‎boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk‎

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NRF54L20PDK
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select SOC_NRF54L20_ENGA_CPUAPP if BOARD_NRF54L20PDK_NRF54L20_CPUAPP

‎boards/nordic/nrf54l20pdk/board.cmake‎

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
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include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/nordic/nrf54l20pdk/board.yml‎

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board:
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name: nrf54l20pdk
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vendor: nordic
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socs:
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- name: nrf54l20
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revision:
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format: major.minor.patch
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default: "0.0.0"
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revisions:
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- name: "0.0.0"

‎boards/nordic/nrf54l20pdk/doc/index.rst‎

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.. _nrf54l20pdk_nrf54l20:
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nRF54L20 PDK
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############
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Overview
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********
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.. note::
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All software for the nRF54L20 SoC is experimental and hardware availability
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is restricted to the participants in the limited sampling program.
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The nRF54L20 Preview Development Kit hardware provides
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support for the Nordic Semiconductor nRF54L20 Arm Cortex-M33 CPU and
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the following devices:
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* CLOCK
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* RRAM
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* :abbr:`GPIO (General Purpose Input Output)`
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* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
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* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
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Hardware
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********
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nRF54L20 PDK has two crystal oscillators:
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* High-frequency 32 MHz crystal oscillator (HFXO)
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* Low-frequency 32.768 kHz crystal oscillator (LFXO)
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The crystal oscillators can be configured to use either
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internal or external capacitors.
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Supported Features
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==================
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The ``nrf54l20pdk/nrf54l20/cpuapp`` board configuration supports the following
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hardware features:
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+-----------+------------+----------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+======================+
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| CLOCK | on-chip | clock_control |
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+-----------+------------+----------------------+
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| RRAM | on-chip | flash |
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+-----------+------------+----------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+----------------------+
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| NVIC | on-chip | arch/arm |
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+-----------+------------+----------------------+
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| UARTE | on-chip | serial |
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+-----------+------------+----------------------+
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Other hardware features have not been enabled yet for this board.
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Programming and Debugging
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*************************
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Applications for the ``nrf54l20pdk/nrf54l20/cpuapp`` board can be
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built, flashed, and debugged in the usual way. See
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:ref:`build_an_application` and :ref:`application_run` for more details on
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building and running.
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Flashing
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========
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As an example, this section shows how to build and flash the :ref:`hello_world`
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application.
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Follow the instructions in the :ref:`nordic_segger` page to install
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and configure all the necessary software. Further information can be
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found in :ref:`nordic_segger_flashing`.
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To build and program the sample to the nRF54L20 PDK, complete the following steps:
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First, connect the nRF54L20 PDK to you computer using the IMCU USB port on the PDK.
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Next, build the sample by running the following command:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: nrf54l20pdk/nrf54l20/cpuapp
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:goals: build flash
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Testing the LEDs and buttons in the nRF54L20 PDK
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************************************************
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Test the nRF54L20 PDK with a :zephyr:code-sample:`blinky` sample.

‎boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* This file is common to the secure and non-secure domain */
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#include <nordic/nrf54l20_cpuapp.dtsi>
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#include "nrf54l20pdk_nrf54l20-common.dtsi"
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/ {
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chosen {
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zephyr,console = &uart20;
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zephyr,shell-uart = &uart20;
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zephyr,uart-mcumgr = &uart20;
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zephyr,bt-mon-uart = &uart20;
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zephyr,bt-c2h-uart = &uart20;
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zephyr,flash-controller = &rram_controller;
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zephyr,flash = &cpuapp_rram;
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};
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};
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&cpuapp_sram {
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status = "okay";
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};
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&lfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15500>;
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};
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&hfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15000>;
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};
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&grtc {
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owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
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/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
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child-owned-channels = <3 4 7 8 9 10 11>;
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status = "okay";
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};
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(449)>;
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};
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slot0_ns_partition: partition@80400 {
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label = "image-0-nonsecure";
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reg = <0x80400 DT_SIZE_K(449)>;
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};
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slot1_partition: partition@f0800 {
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label = "image-1";
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reg = <0xf0800 DT_SIZE_K(449)>;
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};
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slot1_ns_partition: partition@160c00 {
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label = "image-1-nonsecure";
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reg = <0x160c00 DT_SIZE_K(449)>;
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};
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};
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};
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&uart20 {
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status = "okay";
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hw-flow-control;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpiote20 {
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status = "okay";
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};
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&gpiote30 {
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status = "okay";
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};
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&radio {
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status = "okay";
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};
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&temp {
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status = "okay";
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};
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&clock {
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status = "okay";
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};
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&adc {
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status = "okay";
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};

‎boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "nrf54l20pdk_nrf54l20-pinctrl.dtsi"
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/ {
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leds {
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compatible = "gpio-leds";
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led0: led_0 {
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gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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label = "Green LED 0";
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};
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led1: led_1 {
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gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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label = "Green LED 1";
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};
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led2: led_2 {
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gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
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label = "Green LED 2";
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};
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led3: led_3 {
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gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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label = "Green LED 3";
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};
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};
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buttons {
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compatible = "gpio-keys";
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button0: button_0 {
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gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 0";
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zephyr,code = <INPUT_KEY_0>;
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};
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button1: button_1 {
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gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 1";
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zephyr,code = <INPUT_KEY_1>;
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};
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button2: button_2 {
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gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 2";
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zephyr,code = <INPUT_KEY_2>;
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};
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button3: button_3 {
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gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 3";
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zephyr,code = <INPUT_KEY_3>;
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};
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};
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aliases {
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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led3 = &led3;
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sw0 = &button0;
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sw1 = &button1;
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sw2 = &button2;
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sw3 = &button3;
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watchdog0 = &wdt31;
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};
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};
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&uart20 {
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current-speed = <115200>;
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pinctrl-0 = <&uart20_default>;
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pinctrl-1 = <&uart20_sleep>;
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pinctrl-names = "default", "sleep";
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};

‎boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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/omit-if-no-ref/ uart20_default: uart20_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 4)>;
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};
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group2 {
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psels = <NRF_PSEL(UART_RX, 1, 5)>;
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bias-pull-up;
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};
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};
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/omit-if-no-ref/ uart20_sleep: uart20_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 4)>,
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<NRF_PSEL(UART_RX, 1, 5)>;
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low-power-enable;
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};
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};
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};

‎boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include "nrf54l20_cpuapp_common.dtsi"
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/ {
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compatible = "nordic,nrf54l20pdk_nrf54l20-cpuapp";
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model = "Nordic nRF54L20 PDK nRF54L20 Application MCU";
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chosen {
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zephyr,code-partition = &slot0_partition;
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zephyr,sram = &cpuapp_sram;
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};
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};

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