[nrf fromtree] boards: nordic: Rearrange ram0x regions.

The ram0x partitions seem to be not compliant with nRF54H20
architecture and it causes that in the application dts overlay file
it is difficult to extend cpuapp_ram0x_region without modifying
whole layout.

It is better to place cpurad_ram0x_region at the beginning at
2f010000 address and then cpuapp_ram0x_region right after that.
Thanks to that, if the application needs to have more than 256 kB
of RAM, in the application dts overlay file, a user can increase
cpuapp_ram0x_region size up to 2f0be000.

Signed-off-by: Arkadiusz Balys <[email protected]>
(cherry picked from commit a53cb73)

Author: ArekBalysNordic

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi

@@ -7,44 +7,44 @@
 
 / {
 	reserved-memory {
-		cpuapp_ram0x_region: memory@2f010000 {
+		cpurad_ram0x_region: memory@2f010000 {
 			compatible = "nordic,owned-memory";
-			reg = <0x2f010000 DT_SIZE_K(260)>;
+			reg = <0x2f010000 DT_SIZE_K(4)>;
 			status = "disabled";
-			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
+			nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x0 0x2f010000 0x41000>;
+			ranges = <0x0 0x2f010000 0x1000>;
 
-			cpusec_cpuapp_ipc_shm: memory@0 {
+			cpusec_cpurad_ipc_shm: memory@0 {
 				reg = <0x0 DT_SIZE_K(2)>;
 			};
 
-			cpuapp_cpusec_ipc_shm: memory@800 {
+			cpurad_cpusec_ipc_shm: memory@800 {
 				reg = <0x800 DT_SIZE_K(2)>;
 			};
-
-			cpuapp_data: memory@1000 {
-				reg = <0x1000 DT_SIZE_K(256)>;
-			};
 		};
 
-		cpurad_ram0x_region: memory@2f051000 {
+		cpuapp_ram0x_region: memory@2f011000 {
 			compatible = "nordic,owned-memory";
-			reg = <0x2f051000 DT_SIZE_K(4)>;
+			reg = <0x2f010000 DT_SIZE_K(260)>;
 			status = "disabled";
-			nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>;
+			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x0 0x2f051000 0x1000>;
+			ranges = <0x0 0x2f011000 0x41000>;
 
-			cpusec_cpurad_ipc_shm: memory@0 {
+			cpusec_cpuapp_ipc_shm: memory@0 {
 				reg = <0x0 DT_SIZE_K(2)>;
 			};
 
-			cpurad_cpusec_ipc_shm: memory@800 {
+			cpuapp_cpusec_ipc_shm: memory@800 {
 				reg = <0x800 DT_SIZE_K(2)>;
 			};
+
+			cpuapp_data: memory@1000 {
+				reg = <0x1000 DT_SIZE_K(256)>;
+			};
 		};
 
 		etr_buf_ram0x_region: memory@2f0be000 {