[nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration

Configure SDP MSPI pins to switch their control to VPR core

Signed-off-by: Jakub Zymelka <[email protected]>
(cherry picked from commit 2540f7b)

Author: jaz1-nordic

drivers/pinctrl/pinctrl_nrf.c

@@ -108,6 +108,13 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
 #endif
 #endif
 
+#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || defined(CONFIG_MSPI_NRFE)
+#define NRF_PSEL_SDP_MSPI(psel)                                                                    \
+	nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR);
+#endif
+#endif
+
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			   uintptr_t reg)
 {
@@ -420,6 +427,28 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			input = NRF_GPIO_PIN_INPUT_CONNECT;
 			break;
 #endif /* defined(NRF_PSEL_TWIS) */
+#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller)
+		case NRF_FUN_SDP_MSPI_CS0:
+		case NRF_FUN_SDP_MSPI_CS1:
+		case NRF_FUN_SDP_MSPI_CS2:
+		case NRF_FUN_SDP_MSPI_CS3:
+		case NRF_FUN_SDP_MSPI_CS4:
+		case NRF_FUN_SDP_MSPI_SCK:
+		case NRF_FUN_SDP_MSPI_DQ0:
+		case NRF_FUN_SDP_MSPI_DQ1:
+		case NRF_FUN_SDP_MSPI_DQ2:
+		case NRF_FUN_SDP_MSPI_DQ3:
+		case NRF_FUN_SDP_MSPI_DQ4:
+		case NRF_FUN_SDP_MSPI_DQ5:
+		case NRF_FUN_SDP_MSPI_DQ6:
+		case NRF_FUN_SDP_MSPI_DQ7:
+			NRF_PSEL_SDP_MSPI(psel);
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_CONNECT;
+			break;
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) */
+#endif /* CONFIG_SOC_NRF54L15_CPUAPP */
 		default:
 			return -ENOTSUP;
 		}

include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h

@@ -172,6 +172,34 @@
 #define NRF_FUN_GRTC_CLKOUT_FAST 55U
 /** GRTC slow clock output */
 #define NRF_FUN_GRTC_CLKOUT_32K  56U
+/** SDP_MSPI CK */
+#define NRF_FUN_SDP_MSPI_SCK 57U
+/** SDP_MSPI DQ0 */
+#define NRF_FUN_SDP_MSPI_DQ0 58U
+/** SDP_MSPI DQ1 */
+#define NRF_FUN_SDP_MSPI_DQ1 59U
+/** SDP_MSPI DQ2 */
+#define NRF_FUN_SDP_MSPI_DQ2 60U
+/** SDP_MSPI DQ3 */
+#define NRF_FUN_SDP_MSPI_DQ3 61U
+/** SDP_MSPI DQ4 */
+#define NRF_FUN_SDP_MSPI_DQ4 62U
+/** SDP_MSPI DQ5 */
+#define NRF_FUN_SDP_MSPI_DQ5 63U
+/** SDP_MSPI DQ6 */
+#define NRF_FUN_SDP_MSPI_DQ6 64U
+/** SDP_MSPI DQ7 */
+#define NRF_FUN_SDP_MSPI_DQ7 65U
+/** SDP_MSPI CS0 */
+#define NRF_FUN_SDP_MSPI_CS0 66U
+/** SDP_MSPI CS1 */
+#define NRF_FUN_SDP_MSPI_CS1 67U
+/** SDP_MSPI CS2 */
+#define NRF_FUN_SDP_MSPI_CS2 68U
+/** SDP_MSPI CS3 */
+#define NRF_FUN_SDP_MSPI_CS3 69U
+/** SDP_MSPI CS4 */
+#define NRF_FUN_SDP_MSPI_CS4 70U
 
 /** @} */