1313#include <zephyr/linker/devicetree_regions.h>
1414#include <zephyr/cache.h>
1515#include <zephyr/mem_mgmt/mem_attr.h>
16- #include <zephyr/drivers/clock_control/nrf_clock_control.h>
1716
1817#include <zephyr/logging/log.h>
1918
@@ -36,20 +35,6 @@ LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
3635#define PWM (dev_idx ) DT_NODELABEL(pwm##dev_idx)
3736#define PWM_PROP (dev_idx , prop ) DT_PROP(PWM(dev_idx), prop)
3837#define PWM_HAS_PROP (idx , prop ) DT_NODE_HAS_PROP(PWM(idx), prop)
39- #define PWM_NRFX_IS_FAST (idx ) NRF_DT_IS_FAST(PWM(idx))
40-
41- #if NRF_DT_INST_ANY_IS_FAST
42- #define PWM_NRFX_FAST_PRESENT 1
43- /* If fast instances are used then system managed device PM cannot be used because
44- * it may call PM actions from locked context and fast PWM PM actions can only be
45- * called in a thread context.
46- */
47- BUILD_ASSERT (!IS_ENABLED (CONFIG_PM_DEVICE_SYSTEM_MANAGED ));
48- #endif
49-
50- #if defined(PWM_NRFX_FAST_PRESENT ) && CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL
51- #define PWM_NRFX_USE_CLOCK_CONTROL 1
52- #endif
5338
5439#define PWM_NRFX_CH_POLARITY_MASK BIT(15)
5540#define PWM_NRFX_CH_COMPARE_MASK BIT_MASK(15)
@@ -65,10 +50,6 @@ struct pwm_nrfx_config {
6550#ifdef CONFIG_DCACHE
6651 uint32_t mem_attr ;
6752#endif
68- #ifdef PWM_NRFX_USE_CLOCK_CONTROL
69- const struct device * clk_dev ;
70- struct nrf_clock_spec clk_spec ;
71- #endif
7253};
7354
7455struct pwm_nrfx_data {
@@ -77,27 +58,12 @@ struct pwm_nrfx_data {
7758 uint8_t pwm_needed ;
7859 uint8_t prescaler ;
7960 bool stop_requested ;
80- #ifdef PWM_NRFX_USE_CLOCK_CONTROL
81- bool clock_requested ;
82- #endif
8361};
8462/* Ensure the pwm_needed bit mask can accommodate all available channels. */
8563#if (NRF_PWM_CHANNEL_COUNT > 8 )
8664#error "Current implementation supports maximum 8 channels."
8765#endif
8866
89- #ifdef PWM_NRFX_FAST_PRESENT
90- static bool pwm_is_fast (const struct pwm_nrfx_config * config )
91- {
92- return config -> clock_freq > MHZ (16 );
93- }
94- #else
95- static bool pwm_is_fast (const struct pwm_nrfx_config * config )
96- {
97- return false;
98- }
99- #endif
100-
10167static uint16_t * seq_values_ptr_get (const struct device * dev )
10268{
10369 const struct pwm_nrfx_config * config = dev -> config ;
@@ -178,21 +144,6 @@ static int stop_pwm(const struct device *dev)
178144 */
179145 nrfx_pwm_stop (& config -> pwm , false);
180146
181- #if PWM_NRFX_USE_CLOCK_CONTROL
182- struct pwm_nrfx_data * data = dev -> data ;
183-
184- if (data -> clock_requested ) {
185- int ret = nrf_clock_control_release (config -> clk_dev , & config -> clk_spec );
186-
187- if (ret < 0 ) {
188- LOG_ERR ("Global HSFLL release failed: %d" , ret );
189- return ret ;
190- }
191-
192- data -> clock_requested = false;
193- }
194- #endif
195-
196147 return 0 ;
197148}
198149
@@ -232,9 +183,8 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
232183 /* Constantly active (duty 100%). */
233184 /* This value is always greater than or equal to COUNTERTOP. */
234185 compare_value = PWM_NRFX_CH_COMPARE_MASK ;
235- needs_pwm = pwm_is_fast (config ) ||
236- (IS_ENABLED (NRF_PWM_HAS_IDLEOUT ) &&
237- IS_ENABLED (CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100 ));
186+ needs_pwm = IS_ENABLED (NRF_PWM_HAS_IDLEOUT ) &&
187+ IS_ENABLED (CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100 );
238188 } else {
239189 /* PWM generation needed. Check if the requested period matches
240190 * the one that is currently set, or the PWM peripheral can be
@@ -290,22 +240,6 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
290240 * registers and drives its outputs accordingly.
291241 */
292242 if (data -> pwm_needed == 0 ) {
293- if (pwm_is_fast (config )) {
294- #if PWM_NRFX_USE_CLOCK_CONTROL
295- if (data -> clock_requested ) {
296- int ret = nrf_clock_control_release (config -> clk_dev ,
297- & config -> clk_spec );
298-
299- if (ret < 0 ) {
300- LOG_ERR ("Global HSFLL release failed: %d" , ret );
301- return ret ;
302- }
303-
304- data -> clock_requested = false;
305- }
306- #endif
307- return 0 ;
308- }
309243 int ret = stop_pwm (dev );
310244
311245 if (ret < 0 ) {
@@ -332,20 +266,6 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
332266 * until another playback is requested (new values will be
333267 * loaded then) or the PWM peripheral is stopped.
334268 */
335- #if PWM_NRFX_USE_CLOCK_CONTROL
336- if (config -> clk_dev && !data -> clock_requested ) {
337- int ret = nrf_clock_control_request_sync (config -> clk_dev ,
338- & config -> clk_spec ,
339- K_FOREVER );
340-
341- if (ret < 0 ) {
342- LOG_ERR ("Global HSFLL request failed: %d" , ret );
343- return ret ;
344- }
345-
346- data -> clock_requested = true;
347- }
348- #endif
349269 nrfx_pwm_simple_playback (& config -> pwm , & config -> seq , 1 ,
350270 NRFX_PWM_FLAG_NO_EVT_FINISHED );
351271 }
@@ -463,21 +383,6 @@ static int pwm_nrfx_init(const struct device *dev)
463383 COND_CODE_1(PWM_HAS_PROP(idx, memory_regions), \
464384 (DT_PROP_OR(PWM_MEM_REGION(idx), zephyr_memory_attr, 0)), (0))
465385
466- /* Fast instances depend on the global HSFLL clock controller (as they need
467- * to request the highest frequency from it to operate correctly), so they
468- * must be initialized after that controller driver, hence the default PWM
469- * initialization priority may be too early for them.
470- */
471- #if defined(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY ) && \
472- CONFIG_PWM_INIT_PRIORITY < CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY
473- #define PWM_INIT_PRIORITY (idx ) \
474- COND_CODE_1(PWM_NRFX_IS_FAST(idx), \
475- (UTIL_INC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY)), \
476- (CONFIG_PWM_INIT_PRIORITY))
477- #else
478- #define PWM_INIT_PRIORITY (idx ) CONFIG_PWM_INIT_PRIORITY
479- #endif
480-
481386#define PWM_NRFX_DEVICE (idx ) \
482387 NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(PWM(idx)); \
483388 NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(PWM(idx)); \
@@ -506,14 +411,6 @@ static int pwm_nrfx_init(const struct device *dev)
506411 (16ul * 1000ul * 1000ul)), \
507412 IF_ENABLED(CONFIG_DCACHE, \
508413 (.mem_attr = PWM_GET_MEM_ATTR(idx),)) \
509- IF_ENABLED(PWM_NRFX_USE_CLOCK_CONTROL, \
510- (.clk_dev = PWM_NRFX_IS_FAST(idx) \
511- ? DEVICE_DT_GET(DT_CLOCKS_CTLR(PWM(idx))) \
512- : NULL, \
513- .clk_spec = { \
514- .frequency = \
515- NRF_PERIPH_GET_FREQUENCY(PWM(idx)), \
516- },)) \
517414 }; \
518415 static int pwm_nrfx_init##idx(const struct device *dev) \
519416 { \
@@ -526,7 +423,7 @@ static int pwm_nrfx_init(const struct device *dev)
526423 pwm_nrfx_init##idx, PM_DEVICE_DT_GET(PWM(idx)), \
527424 &pwm_nrfx_##idx##_data, \
528425 &pwm_nrfx_##idx##_config, \
529- POST_KERNEL, PWM_INIT_PRIORITY(idx) , \
426+ POST_KERNEL, CONFIG_PWM_INIT_PRIORITY , \
530427 &pwm_nrfx_drv_api_funcs)
531428
532429#define COND_PWM_NRFX_DEVICE (unused , prefix , i , _ ) \
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