From 034a2eb1e83dcf6ab2d919757982635f342e8c77 Mon Sep 17 00:00:00 2001 From: Dominik Kilian Date: Wed, 23 Oct 2024 14:23:00 +0200 Subject: [PATCH] [nrf fromtree] boards: nordic: ipc: added dcache alignement The nRF54 and nRF92 chips has data cache, which means the ICMsg and ICBMsg must be configured to follow required cache alignment of the shared memory. The `dcache-alignement` needs to be defined for that. Signed-off-by: Dominik Kilian (cherry picked from commit cbaafe209c17f03feea3760be855dc76ef5612cc) (cherry picked from commit 6c435d6d9b1ffa8782d38ddb338edac2447a502e) --- .../nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi | 1 + .../nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi | 1 + .../ipc/ipc_service/backends/ipc_service_icbmsg.rst | 10 ++++++++++ .../ipc/ipc_service/backends/ipc_service_icmsg.rst | 10 ++++++++++ dts/bindings/ipc/zephyr,ipc-icmsg.yaml | 2 +- .../icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay | 1 + .../boards/nrf54l15dk_nrf54l15_cpuapp_icbmsg.overlay | 1 + .../remote/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay | 1 + .../boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay | 1 + subsys/ipc/ipc_service/backends/ipc_icbmsg.c | 4 ++-- 10 files changed, 29 insertions(+), 3 deletions(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi index a17889fe0b0..fdc93408dd3 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi @@ -22,6 +22,7 @@ cpuapp_cpurad_ipc: ipc-2-3 { compatible = "zephyr,ipc-icbmsg"; + dcache-alignment = <32>; status = "disabled"; mboxes = <&cpuapp_bellboard 18>, <&cpurad_bellboard 12>; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi index 944dd7fb6ab..906342f6f3d 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi @@ -22,6 +22,7 @@ cpuapp_cpurad_ipc: ipc-2-3 { compatible = "zephyr,ipc-icbmsg"; + dcache-alignment = <32>; status = "disabled"; mboxes = <&cpuapp_bellboard 18>, <&cpurad_bellboard 12>; diff --git a/doc/services/ipc/ipc_service/backends/ipc_service_icbmsg.rst b/doc/services/ipc/ipc_service/backends/ipc_service_icbmsg.rst index f570766b0bd..b1f13d7566a 100644 --- a/doc/services/ipc/ipc_service/backends/ipc_service_icbmsg.rst +++ b/doc/services/ipc/ipc_service/backends/ipc_service_icbmsg.rst @@ -40,12 +40,21 @@ Configuration The backend is configured using Kconfig and devicetree. When configuring the backend, do the following: +* If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value. + This must be the largest value of the invalidation or the write-back size for both sides of the communication. + You can skip it if none of the communication sides is using data cache on shared memory. * Define two memory regions and assign them to ``tx-region`` and ``rx-region`` of an instance. Ensure that the memory regions used for data exchange are unique (not overlapping any other region) and accessible by both domains (or CPUs). * Define the number of allocable blocks for each region with ``tx-blocks`` and ``rx-blocks``. * Define MBOX devices for sending a signal that informs the other domain (or CPU) of the written data. Ensure that the other domain (or CPU) can receive the signal. +.. caution:: + + Make sure that you set correct value of the ``dcache-alignment``. + At first, wrong value may not show any signs, which may give a false impression that everything works. + Unstable behavior will appear sooner or later. + See the following configuration example for one of the instances: .. code-block:: devicetree @@ -63,6 +72,7 @@ See the following configuration example for one of the instances: ipc { ipc0: ipc0 { compatible = "zephyr,ipc-icbmsg"; + dcache-alignment = <32>; tx-region = <&tx>; rx-region = <&rx>; tx-blocks = <16>; diff --git a/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst b/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst index 56f618b442d..251a332027a 100644 --- a/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst +++ b/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst @@ -24,6 +24,9 @@ Configuration The backend is configured via Kconfig and devicetree. When configuring the backend, do the following: +* If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value. + This must be the largest value of the invalidation or the write-back size for both sides of the communication. + You can skip it if none of the communication sides is using data cache on shared memory. * Define two memory regions and assign them to ``tx-region`` and ``rx-region`` of an instance. Ensure that the memory regions used for data exchange are unique (not overlapping any other region) and accessible by both domains @@ -32,6 +35,12 @@ When configuring the backend, do the following: domain (or CPU) that data has been written. Ensure that the other domain (or CPU) is able to receive the signal. +.. caution:: + + Make sure that you set correct value of the ``dcache-alignment``. + At first, wrong value may not show any signs, which may give a false impression that everything works. + Unstable behavior will appear sooner or later. + See the following configuration example for one of the instances: .. code-block:: devicetree @@ -49,6 +58,7 @@ See the following configuration example for one of the instances: ipc { ipc0: ipc0 { compatible = "zephyr,ipc-icmsg"; + dcache-alignment = <32>; tx-region = <&tx>; rx-region = <&rx>; mboxes = <&mbox 0>, <&mbox 1>; diff --git a/dts/bindings/ipc/zephyr,ipc-icmsg.yaml b/dts/bindings/ipc/zephyr,ipc-icmsg.yaml index 41793005373..13a9e2b84b6 100644 --- a/dts/bindings/ipc/zephyr,ipc-icmsg.yaml +++ b/dts/bindings/ipc/zephyr,ipc-icmsg.yaml @@ -32,7 +32,7 @@ properties: For example: Side A: no data cache Side B: 32 Bytes write-back size, 16 Bytes invalidation size - dcache-alignment = 32; for both + dcache-alignment = <32>; for both mboxes: description: phandle to the MBOX controller (TX and RX are required) diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay index b6f20acc42a..56b3ae097d8 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay @@ -23,6 +23,7 @@ ipc { ipc0: ipc0 { compatible = "zephyr,ipc-icmsg"; + dcache-alignment = <32>; tx-region = <&sram_tx>; rx-region = <&sram_rx>; mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>; diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp_icbmsg.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp_icbmsg.overlay index a3f853c6e3d..639ad5e844b 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp_icbmsg.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp_icbmsg.overlay @@ -23,6 +23,7 @@ ipc { ipc0: ipc0 { compatible = "zephyr,ipc-icbmsg"; + dcache-alignment = <32>; tx-region = <&sram_tx>; rx-region = <&sram_rx>; tx-blocks = <16>; diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay index c6e59f2b131..b3e86e96361 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay @@ -23,6 +23,7 @@ ipc { ipc0: ipc0 { compatible = "zephyr,ipc-icmsg"; + dcache-alignment = <32>; tx-region = <&sram_tx>; rx-region = <&sram_rx>; mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>; diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay index 0033e622107..7fe78a71653 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay +++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay @@ -23,6 +23,7 @@ ipc { ipc0: ipc0 { compatible = "zephyr,ipc-icbmsg"; + dcache-alignment = <32>; tx-region = <&sram_tx>; rx-region = <&sram_rx>; tx-blocks = <18>; diff --git a/subsys/ipc/ipc_service/backends/ipc_icbmsg.c b/subsys/ipc/ipc_service/backends/ipc_icbmsg.c index 9fd7752999f..927950dd50a 100644 --- a/subsys/ipc/ipc_service/backends/ipc_icbmsg.c +++ b/subsys/ipc/ipc_service/backends/ipc_icbmsg.c @@ -1434,11 +1434,11 @@ const static struct ipc_service_backend backend_ops = { }; \ BUILD_ASSERT(IS_POWER_OF_TWO(GET_CACHE_ALIGNMENT(i)), \ "This module supports only power of two cache alignment"); \ - BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, tx, rx) > GET_CACHE_ALIGNMENT(i)) && \ + BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, tx, rx) >= GET_CACHE_ALIGNMENT(i)) && \ (GET_BLOCK_SIZE_INST(i, tx, rx) < \ GET_MEM_SIZE_INST(i, tx)), \ "TX region is too small for provided number of blocks"); \ - BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, rx, tx) > GET_CACHE_ALIGNMENT(i)) && \ + BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, rx, tx) >= GET_CACHE_ALIGNMENT(i)) && \ (GET_BLOCK_SIZE_INST(i, rx, tx) < \ GET_MEM_SIZE_INST(i, rx)), \ "RX region is too small for provided number of blocks"); \