From 2aaf5f42972eaa6af1336f2d29f2ac4115278886 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 30 Sep 2024 13:22:27 +0300 Subject: [PATCH 01/20] [nrf fromtree] dts: bindings: power-domain: add binding for NXP's SCU-managed PDs Add DT binding for NXP's SCU-managed PDs. This binding describes exactly _one_ power domain. Signed-off-by: Laurentiu Mihalcea (cherry picked from commit fb84f4f53f34f33a90578c9e0855366814eab0b9) --- dts/bindings/power-domain/nxp,scu-pd.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 dts/bindings/power-domain/nxp,scu-pd.yaml diff --git a/dts/bindings/power-domain/nxp,scu-pd.yaml b/dts/bindings/power-domain/nxp,scu-pd.yaml new file mode 100644 index 00000000000..7e1d0855389 --- /dev/null +++ b/dts/bindings/power-domain/nxp,scu-pd.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP SCU-managed power domain + +compatible: "nxp,scu-pd" + +include: power-domain.yaml + +properties: + nxp,resource-id: + type: int + required: true + description: + Number used by the firmware running on the SCU to identify + the resource on which the PD-related operations are to be + performed. From 54f99d73d3e6db62a9c306ce0d75e9fc4eafc44e Mon Sep 17 00:00:00 2001 From: Grzegorz Bernat Date: Mon, 23 Sep 2024 13:14:55 +0200 Subject: [PATCH 02/20] [nrf fromtree] soc: intel: renamed soc from ace30_ptl to ace30 Renamed soc from ace30_ptl to ace30. We were previously using the wrong soc name. The correct name is ace30. There is only one ptl platform, but there can be several ace30 platforms. Signed-off-by: Grzegorz Bernat (cherry picked from commit a654bfbdfa002ac5ab32d8593d762f5ef3dc4868) --- boards/intel/adsp/Kconfig.intel_adsp | 4 +- boards/intel/adsp/board.yml | 6 +- boards/intel/adsp/intel_adsp_ace30_defconfig | 12 + boards/intel/adsp/intel_adsp_ace30_ptl.yaml | 2 +- .../intel/adsp/intel_adsp_ace30_ptl_sim.yaml | 2 +- drivers/dai/intel/dmic/dmic.c | 14 +- drivers/dai/intel/dmic/dmic.h | 2 +- drivers/dai/intel/dmic/dmic_nhlt.c | 4 +- drivers/dai/intel/ssp/dai-params-intel-ipc4.h | 2 +- drivers/dai/intel/ssp/ssp.c | 30 +- drivers/dai/intel/ssp/ssp.h | 4 +- drivers/dma/dma_intel_adsp_hda.c | 2 +- dts/xtensa/intel/intel_adsp_ace30.dtsi | 682 ++++++++++++++++++ soc/intel/intel_adsp/ace/CMakeLists.txt | 2 +- ...nfig.ace30_ptl => Kconfig.defconfig.ace30} | 2 +- soc/intel/intel_adsp/ace/Kconfig.soc | 6 +- .../include/{ace30_ptl => ace30}/adsp_boot.h | 0 .../{ace30_ptl => ace30}/adsp_interrupt.h | 0 .../{ace30_ptl => ace30}/adsp_ipc_regs.h | 0 .../include/{ace30_ptl => ace30}/adsp_power.h | 0 .../include/{ace30_ptl => ace30}/adsp_shim.h | 0 .../{ace30_ptl => ace30}/dmic_regs_ace3x.h | 0 soc/intel/intel_adsp/ace/include/dmic_regs.h | 4 +- soc/intel/intel_adsp/common/clk.c | 2 +- soc/intel/intel_adsp/soc.yml | 2 +- ...p_ace30_ptl.conf => intel_adsp_ace30.conf} | 0 ...p_ace30_ptl.conf => intel_adsp_ace30.conf} | 0 ...p_ace30_ptl.conf => intel_adsp_ace30.conf} | 0 ...p_ace30_ptl.conf => intel_adsp_ace30.conf} | 0 29 files changed, 740 insertions(+), 44 deletions(-) create mode 100644 boards/intel/adsp/intel_adsp_ace30_defconfig create mode 100644 dts/xtensa/intel/intel_adsp_ace30.dtsi rename soc/intel/intel_adsp/ace/{Kconfig.defconfig.ace30_ptl => Kconfig.defconfig.ace30} (96%) rename soc/intel/intel_adsp/ace/include/{ace30_ptl => ace30}/adsp_boot.h (100%) rename soc/intel/intel_adsp/ace/include/{ace30_ptl => ace30}/adsp_interrupt.h (100%) rename soc/intel/intel_adsp/ace/include/{ace30_ptl => ace30}/adsp_ipc_regs.h (100%) rename soc/intel/intel_adsp/ace/include/{ace30_ptl => ace30}/adsp_power.h (100%) rename soc/intel/intel_adsp/ace/include/{ace30_ptl => ace30}/adsp_shim.h (100%) rename soc/intel/intel_adsp/ace/include/{ace30_ptl => ace30}/dmic_regs_ace3x.h (100%) rename tests/kernel/mem_protect/sys_sem/boards/{intel_adsp_ace30_ptl.conf => intel_adsp_ace30.conf} (100%) rename tests/kernel/mutex/sys_mutex/boards/{intel_adsp_ace30_ptl.conf => intel_adsp_ace30.conf} (100%) rename tests/kernel/queue/boards/{intel_adsp_ace30_ptl.conf => intel_adsp_ace30.conf} (100%) rename tests/lib/c_lib/thrd/boards/{intel_adsp_ace30_ptl.conf => intel_adsp_ace30.conf} (100%) diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp index 67c3989fe32..225a2747ad5 100644 --- a/boards/intel/adsp/Kconfig.intel_adsp +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -8,5 +8,5 @@ config BOARD_INTEL_ADSP select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM - select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL - select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL_SIM + select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL + select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml index 5eadeb4fe1a..43004e8f2a4 100644 --- a/boards/intel/adsp/board.yml +++ b/boards/intel/adsp/board.yml @@ -11,6 +11,8 @@ boards: - name: ace20_lnl variants: - name: 'sim' - - name: ace30_ptl + - name: ace30 variants: - - name: 'sim' + - name: 'ptl' + variants: + - name: 'sim' diff --git a/boards/intel/adsp/intel_adsp_ace30_defconfig b/boards/intel/adsp/intel_adsp_ace30_defconfig new file mode 100644 index 00000000000..913d2a8c3e3 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl.yaml b/boards/intel/adsp/intel_adsp_ace30_ptl.yaml index bdfe837bd08..061ac9cd742 100644 --- a/boards/intel/adsp/intel_adsp_ace30_ptl.yaml +++ b/boards/intel/adsp/intel_adsp_ace30_ptl.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp/ace30_ptl +identifier: intel_adsp/ace30/ptl name: ACE 3.0 Panther Lake Audio DSP type: mcu arch: xtensa diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml b/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml index 3bf48d4c383..42b07e49ee3 100644 --- a/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml +++ b/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp/ace30_ptl/sim +identifier: intel_adsp/ace30/ptl/sim name: ACE 3.0 Panther Lake Audio DSP type: sim simulation: custom diff --git a/drivers/dai/intel/dmic/dmic.c b/drivers/dai/intel/dmic/dmic.c index b0d44d4da55..e528e96f38d 100644 --- a/drivers/dai/intel/dmic/dmic.c +++ b/drivers/dai/intel/dmic/dmic.c @@ -160,7 +160,7 @@ static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic) static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic) { -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) return dmic->hdamldmic_base; #else return dmic->shim_base; @@ -173,7 +173,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1; uint32_t base = dai_dmic_base(dmic); /* DMIC Change sync period */ -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), base + DMICSYNC_OFFSET); sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU, @@ -287,7 +287,7 @@ static void dai_dmic_irq_handler(const void *data) static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic) { /* Disable DMIC clock gating */ -#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL) +#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30) sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD), dmic->vshim_base + DMICLVSCTL_OFFSET); #else @@ -299,7 +299,7 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic) static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic) { /* Enable DMIC clock gating */ -#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL) +#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30) sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD), dmic->vshim_base + DMICLVSCTL_OFFSET); #else /* All other CAVS and ACE platforms */ @@ -313,7 +313,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi const struct dai_config *cfg, uint32_t index) { -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) uint16_t pcmsycm = cfg->link_config; uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index; @@ -322,7 +322,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi ARG_UNUSED(dmic); ARG_UNUSED(cfg); ARG_UNUSED(index); -#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) */ +#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) */ } static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic) @@ -332,7 +332,7 @@ static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic) sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA), base + DMICLCTL_OFFSET); -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) { k_sleep(K_USEC(100)); } diff --git a/drivers/dai/intel/dmic/dmic.h b/drivers/dai/intel/dmic/dmic.h index c507ec1c0ee..9b7d8c03ea8 100644 --- a/drivers/dai/intel/dmic/dmic.h +++ b/drivers/dai/intel/dmic/dmic.h @@ -173,7 +173,7 @@ struct dai_intel_dmic { /* hardware parameters */ uint32_t reg_base; uint32_t shim_base; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) uint32_t hdamldmic_base; uint32_t vshim_base; #endif diff --git a/drivers/dai/intel/dmic/dmic_nhlt.c b/drivers/dai/intel/dmic/dmic_nhlt.c index f71b0d47f2f..d041ef438ce 100644 --- a/drivers/dai/intel/dmic/dmic_nhlt.c +++ b/drivers/dai/intel/dmic/dmic_nhlt.c @@ -282,7 +282,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic, const int c static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, uint32_t source) { uint32_t val; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */ +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) /* ACE 2.0,3.0 */ val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET); val &= ~DMICLVSCTL_MLCS; val |= FIELD_PREP(DMICLVSCTL_MLCS, source); @@ -303,7 +303,7 @@ static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, static inline uint32_t dai_dmic_clock_select_get(const struct dai_intel_dmic *dmic) { uint32_t val; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */ +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) /* ACE 2.0,3.0 */ val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET); return FIELD_GET(DMICLVSCTL_MLCS, val); #else diff --git a/drivers/dai/intel/ssp/dai-params-intel-ipc4.h b/drivers/dai/intel/ssp/dai-params-intel-ipc4.h index 6d078cd0941..46acee049ce 100644 --- a/drivers/dai/intel/ssp/dai-params-intel-ipc4.h +++ b/drivers/dai/intel/ssp/dai-params-intel-ipc4.h @@ -269,7 +269,7 @@ struct dai_intel_ipc4_ssp_mclk_config_2 { } __packed; struct dai_intel_ipc4_ssp_driver_config { -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_config; #else struct dai_intel_ipc4_ssp_config i2s_config; diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c index 58ab0c10170..218f3c33162 100644 --- a/drivers/dai/intel/ssp/ssp.c +++ b/drivers/dai/intel/ssp/ssp.c @@ -800,7 +800,7 @@ static void dai_ssp_pm_runtime_en_ssp_power(struct dai_intel_ssp *dp, uint32_t s ret = dai_ssp_poll_for_register_delay(dai_ip_base(dp) + I2SLCTL_OFFSET, I2SLCTL_CPA(ssp_index), I2SLCTL_CPA(ssp_index), DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE); -#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL +#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) | I2SLCTL_SPA(ssp_index), dai_hdamlssp_base(dp) + I2SLCTL_OFFSET); @@ -835,7 +835,7 @@ static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t I2SLCTL_CPA(ssp_index), 0, DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE); -#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL +#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(ssp_index)), dai_hdamlssp_base(dp) + I2SLCTL_OFFSET); @@ -873,7 +873,7 @@ static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp, /* Program HDA input stream parameters */ sys_write16((pcmsycm & 0xffff), reg_add); } -#elif defined(CONFIG_SOC_INTEL_ACE30_PTL) +#elif defined(CONFIG_SOC_INTEL_ACE30) const struct dai_intel_ipc4_ssp_configuration_blob_ver_3_0 *blob30 = spec_config; const struct dai_intel_ipc4_ssp_configuration_blob *blob = spec_config; uint64_t time_slot_map = 0; @@ -930,7 +930,7 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp) * SSSR_TNF is cleared when TX FIFO is empty or full, * so wait for set TNF then for TFL zero - order matter. */ -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 ret = dai_ssp_poll_for_register_delay(dai_base(dp) + SSMODyCS(dp->tdm_slot_group), SSMODyCS_TNF, SSMODyCS_TNF, DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE); @@ -959,7 +959,7 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp) } } -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 static void ssp_empty_rx_fifo_on_start(struct dai_intel_ssp *dp) { uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX; @@ -1191,7 +1191,7 @@ static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp) mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate; #endif -#ifndef CONFIG_SOC_INTEL_ACE30_PTL +#ifndef CONFIG_SOC_INTEL_ACE30 if (need_ecs) { sscr0 |= SSCR0_ECS; } @@ -1724,7 +1724,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co sys_write32(sspsp2, dai_base(dp) + SSPSP2); sys_write32(ssioc, dai_base(dp) + SSIOC); sys_write32(ssto, dai_base(dp) + SSTO); -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) { sys_write64(sstsa, dai_base(dp) + SSMODyTSA(idx)); } @@ -1777,7 +1777,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co ssp_plat_data->clk_active |= SSP_CLK_BCLK_ES_REQ; if (enable_sse) { -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RSRE, SSMIDyCS_RSRE); dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), @@ -1806,7 +1806,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co LOG_INF("hw_free stage: releasing BCLK clocks for SSP%d...", dp->dai_index); if (ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE) { -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 for (uint32_t idx = 0; idx < I2SOPCMC; ++idx) { dai_ssp_update_bits(dp, SSMODyCS(idx), SSMODyCS_TSRE, 0); } @@ -1985,7 +1985,7 @@ static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, s ~I2CLCTL_MLCS(0x7)) | I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) + I2SLCTL_OFFSET); -#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL +#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) & ~I2CLCTL_MLCS(0x7)) | I2CLCTL_MLCS(link->clock_source), @@ -2065,7 +2065,7 @@ static int dai_ssp_set_clock_control_ver_1(struct dai_intel_ssp *dp, return 0; } -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_config *cfg, const void *spec_config) { @@ -2184,7 +2184,7 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp); int err; -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 dp->tdm_slot_group = cfg->tdm_slot_group; #endif @@ -2322,7 +2322,7 @@ static void dai_ssp_start(struct dai_intel_ssp *dp, int direction) /* enable DMA */ -#if CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_INTEL_ACE30 if (direction == DAI_DIR_PLAYBACK) { dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TSRE, SSMODyCS_TSRE); @@ -2392,7 +2392,7 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction) if (direction == DAI_DIR_CAPTURE && dp->state[DAI_DIR_CAPTURE] != DAI_STATE_PRE_RUNNING) { LOG_INF("SSP%d RX", dp->dai_index); -#if CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_INTEL_ACE30 dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RXEN, 0); dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RSRE, 0); #else @@ -2407,7 +2407,7 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction) if (direction == DAI_DIR_PLAYBACK && dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_PRE_RUNNING) { LOG_INF("SSP%d TX", dp->dai_index); -#if CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_INTEL_ACE30 dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TSRE, 0); dai_ssp_empty_tx_fifo(dp); dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TXEN, 0); diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h index 560b5d3df5f..5d1c2943724 100644 --- a/drivers/dai/intel/ssp/ssp.h +++ b/drivers/dai/intel/ssp/ssp.h @@ -52,7 +52,7 @@ #include "ssp_regs_v1.h" #elif defined(CONFIG_SOC_INTEL_ACE20_LNL) #include "ssp_regs_v2.h" -#elif defined(CONFIG_SOC_INTEL_ACE30_PTL) +#elif defined(CONFIG_SOC_INTEL_ACE30) #include "ssp_regs_v3.h" #else #error "Missing ssp definitions" @@ -116,7 +116,7 @@ struct dai_intel_ssp_plat_data { uint32_t base; uint32_t ip_base; uint32_t shim_base; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) uint32_t hdamlssp_base; uint32_t i2svss_base; #endif diff --git a/drivers/dma/dma_intel_adsp_hda.c b/drivers/dma/dma_intel_adsp_hda.c index 5a2dc1a1e0f..2f9b98ed74b 100644 --- a/drivers/dma/dma_intel_adsp_hda.c +++ b/drivers/dma/dma_intel_adsp_hda.c @@ -235,7 +235,7 @@ int intel_adsp_hda_dma_status(const struct device *dev, uint32_t channel, stat->pending_length = used; stat->free = unused; -#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 /* Linear Link Position via HDA-DMA is only supported on ACE2 or newer */ if (cfg->direction == MEMORY_TO_PERIPHERAL || cfg->direction == PERIPHERAL_TO_MEMORY) { uint32_t tmp; diff --git a/dts/xtensa/intel/intel_adsp_ace30.dtsi b/dts/xtensa/intel/intel_adsp_ace30.dtsi new file mode 100644 index 00000000000..97be77eb757 --- /dev/null +++ b/dts/xtensa/intel/intel_adsp_ace30.dtsi @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <0>; + cpu-power-states = <&d0i3 &d3>; + i-cache-line-size = <64>; + d-cache-line-size = <64>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <1>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <2>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <3>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <4>; + cpu-power-states = <&d0i3 &d3>; + }; + }; + + power-states { + d0i3: idle { + compatible = "zephyr,power-state"; + power-state-name = "runtime-idle"; + min-residency-us = <200>; + exit-latency-us = <100>; + }; + /* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force. + * The procedure is triggered by IPC from the HOST (SET_DX). + */ + d3: off { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + min-residency-us = <0>; + exit-latency-us = <0>; + status = "disabled"; + }; + }; + + sram0: memory@a0020000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0xa0020000 DT_SIZE_K(4608)>; + }; + + sram0virtual: virtualmemory@a0020000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0xa0020000 DT_SIZE_K(8192)>; + }; + + sram1: memory@a0000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0xa0000000 DT_SIZE_K(64)>; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + clkctl: clkctl { + compatible = "intel,adsp-shim-clkctl"; + adsp-clkctl-clk-wovcro = <0>; + adsp-clkctl-clk-ipll = <1>; + adsp-clkctl-freq-enc = <0xc 0x4>; + adsp-clkctl-freq-mask = <0x0 0x0>; + adsp-clkctl-freq-default = <1>; + adsp-clkctl-freq-lowest = <0>; + wovcro-supported; + }; + + audioclk: audio-clock { + compatible = "fixed-clock"; + clock-frequency = <24576000>; + #clock-cells = <0>; + }; + + pllclk: pll-clock { + compatible = "fixed-clock"; + clock-frequency = <96000000>; + #clock-cells = <0>; + }; + + IMR1: memory@A1000000 { + compatible = "intel,adsp-imr"; + reg = <0xA1000000 DT_SIZE_M(16)>; + block-size = <0x1000>; + zephyr,memory-region = "IMR1"; + }; + + soc { + l1ccap: l1ccap@3fe80080 { + compatible = "intel,adsp-l1ccap"; + reg = <0x3fe80080 0x4>; + }; + + l1ccfg: l1ccfg@3fe80084 { + compatible = "intel,adsp-l1ccfg"; + reg = <0x3fe80084 0x4>; + }; + + l1pcfg: l1pcfg@3fe80088 { + compatible = "intel,adsp-l1pcfg"; + reg = <0x3fe80088 0x4>; + }; + + lsbpm: lsbpm@71d80 { + compatible = "intel,adsp-lsbpm"; + reg = <0x71d80 0x0008>; + }; + + hsbpm: hsbpm@17a800 { + compatible = "intel,adsp-hsbpm"; + reg = <0x17a800 0x0008>; + }; + + core_intc: core_intc@0 { + compatible = "cdns,xtensa-core-intc"; + reg = <0x00 0x400>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + hdamlddmic: hdamlddmic@cc0 { + compatible = "intel,adsp-hda-dmic-cap"; + reg = <0xcc0 0x40>; + status = "okay"; + }; + + dmic0: dai-dmic0@10100 { + compatible = "intel,dai-dmic"; + reg = <0x10100 0x8000>; + shim = <0x10000>; + fifo = <0x0008>; + interrupts = <0x08 0 0>; + interrupt-parent = <&ace_intc>; + power-domain = <&hub_ulp_domain>; + }; + + dmic1: dai-dmic1@10100 { + compatible = "intel,dai-dmic"; + reg = <0x10100 0x8000>; + shim = <0x10000>; + fifo = <0x0108>; + interrupts = <0x08 0 0>; + interrupt-parent = <&ace_intc>; + power-domain = <&hub_ulp_domain>; + }; + + dmicvss: dmicvss@16000 { + compatible = "intel,adsp-dmic-vss"; + reg = <0x16000 0x2000>; + status = "okay"; + }; + + sspbase: ssp_base@28000 { + compatible = "intel,ssp-sspbase"; + reg = <0x28000 0x1000>; + }; + + hdamlssp: hdamlssp@d00 { + compatible = "intel,adsp-hda-ssp-cap"; + reg = <0xD00 0x40>; + status = "okay"; + }; + + ssp0: ssp@28100 { + compatible = "intel,ssp"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00028100 0x1000 + 0x00079C00 0x200>; + i2svss = <0x00028C00 0x1000>; + interrupts = <0x00 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 1 + &hda_link_in 1>; + dma-names = "tx", "rx"; + ssp-index = <0>; + power-domain = <&io0_domain>; + status = "okay"; + + ssp00: ssp@0 { + compatible = "intel,ssp-dai"; + reg = <0x0>; + status = "okay"; + }; + + ssp01: ssp@1 { + compatible = "intel,ssp-dai"; + reg = <0x1>; + status = "okay"; + }; + + ssp02: ssp@2 { + compatible = "intel,ssp-dai"; + reg = <0x2>; + status = "okay"; + }; + + ssp03: ssp@3 { + compatible = "intel,ssp-dai"; + reg = <0x3>; + status = "okay"; + }; + + ssp04: ssp@4 { + compatible = "intel,ssp-dai"; + reg = <0x4>; + status = "okay"; + }; + + ssp05: ssp@5 { + compatible = "intel,ssp-dai"; + reg = <0x5>; + status = "okay"; + }; + + ssp06: ssp@6 { + compatible = "intel,ssp-dai"; + reg = <0x6>; + status = "okay"; + }; + + ssp07: ssp@7 { + compatible = "intel,ssp-dai"; + reg = <0x7>; + status = "okay"; + }; + }; + + ssp1: ssp@29100 { + compatible = "intel,ssp"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00029100 0x1000 + 0x00079C00 0x200>; + i2svss = <0x00029C00 0x1000>; + interrupts = <0x01 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 2 + &hda_link_in 2>; + dma-names = "tx", "rx"; + ssp-index = <1>; + power-domain = <&io0_domain>; + status = "okay"; + + ssp10: ssp@10 { + compatible = "intel,ssp-dai"; + reg = <0x10>; + status = "okay"; + }; + + ssp11: ssp@11 { + compatible = "intel,ssp-dai"; + reg = <0x11>; + status = "okay"; + }; + + ssp12: ssp@12 { + compatible = "intel,ssp-dai"; + reg = <0x12>; + status = "okay"; + }; + + ssp13: ssp@13 { + compatible = "intel,ssp-dai"; + reg = <0x13>; + status = "okay"; + }; + + ssp14: ssp@14 { + compatible = "intel,ssp-dai"; + reg = <0x14>; + status = "okay"; + }; + + ssp15: ssp@15 { + compatible = "intel,ssp-dai"; + reg = <0x15>; + status = "okay"; + }; + + ssp16: ssp@16 { + compatible = "intel,ssp-dai"; + reg = <0x16>; + status = "okay"; + }; + + ssp17: ssp@17 { + compatible = "intel,ssp-dai"; + reg = <0x17>; + status = "okay"; + }; + }; + + ssp2: ssp@2a100 { + compatible = "intel,ssp"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0002a100 0x1000 + 0x00079C00 0x200>; + i2svss = <0x0002AC00 0x1000>; + interrupts = <0x02 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 3 + &hda_link_in 3>; + dma-names = "tx", "rx"; + ssp-index = <2>; + power-domain = <&io0_domain>; + status = "okay"; + + ssp20: ssp@20 { + compatible = "intel,ssp-dai"; + reg = <0x20>; + status = "okay"; + }; + + ssp21: ssp@21 { + compatible = "intel,ssp-dai"; + reg = <0x21>; + status = "okay"; + }; + + ssp22: ssp@22 { + compatible = "intel,ssp-dai"; + reg = <0x22>; + status = "okay"; + }; + + ssp23: ssp@23 { + compatible = "intel,ssp-dai"; + reg = <0x23>; + status = "okay"; + }; + + ssp24: ssp@24 { + compatible = "intel,ssp-dai"; + reg = <0x24>; + status = "okay"; + }; + + ssp25: ssp@25 { + compatible = "intel,ssp-dai"; + reg = <0x25>; + status = "okay"; + }; + + ssp26: ssp@26 { + compatible = "intel,ssp-dai"; + reg = <0x26>; + status = "okay"; + }; + + ssp27: ssp@27 { + compatible = "intel,ssp-dai"; + reg = <0x27>; + status = "okay"; + }; + }; + + mem_window0: mem_window@70200 { + compatible = "intel,adsp-mem-window"; + reg = <0x70200 0x8>; + offset = <0x4000>; + memory = <&sram0>; + initialize; + read-only; + }; + + mem_window1: mem_window@70208 { + compatible = "intel,adsp-mem-window"; + reg = <0x70208 0x8>; + memory = <&sram0>; + }; + + mem_window2: mem_window@70210 { + compatible = "intel,adsp-mem-window"; + reg = <0x70210 0x8>; + memory = <&sram0>; + }; + + mem_window3: mem_window@70218 { + compatible = "intel,adsp-mem-window"; + reg = <0x70218 0x8>; + memory = <&sram0>; + read-only; + }; + + adsp_idc: ace_idc@92000 { + compatible = "intel,adsp-idc"; + reg = <0x92000 0x0400>; + interrupts = <24 0 0>; + interrupt-parent = <&ace_intc>; + }; + + dfpmcch: dfpmcch@71ac0 { + compatible = "intel,adsp-dfpmcch"; + reg = <0x00071ac0 0x40>; + }; + + dfpmccu: dfpmccu@71b00 { + compatible = "intel,adsp-dfpmccu"; + reg = <0x71b00 0x100>; + + hub_ulp_domain: hub_ulp_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <15>; + }; + ml0_domain: ml0_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <12>; + }; + io1_domain: io1_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <9>; + }; + io0_domain: io0_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <8>; + }; + hub_hp_domain: hub_hpp_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <6>; + }; + hst_domain: hst_domain { + compatible = "intel,adsp-power-domain"; + bit-position = <5>; + }; + }; + + shim: shim@71f00 { + compatible = "intel,cavs-shim"; + reg = <0x71f00 0x100>; + }; + + tts: tts@72000 { + compatible = "intel,adsp-tts"; + reg = <0x72000 0x70>; + status = "okay"; + }; + + ace_rtc_counter: ace_rtc_counter@72008 { + compatible = "intel,ace-rtc-counter"; + reg = <0x72008 0x0064>; + }; + + ace_timestamp: ace_timestamp@72040 { + compatible = "intel,ace-timestamp"; + reg = <0x72040 0x0032>; + }; + + ace_art_counter: ace_art_counter@72058 { + compatible = "intel,ace-art-counter"; + reg = <0x72058 0x0064>; + }; + + hda_host_out: dma@72800 { + compatible = "intel,adsp-hda-host-out"; + #dma-cells = <1>; + reg = <0x00072800 0x40>; + dma-channels = <9>; + dma-buf-addr-alignment = <128>; + dma-buf-size-alignment = <32>; + dma-copy-alignment = <32>; + power-domain = <&hst_domain>; + interrupts = <13 0 0>; + interrupt-parent = <&ace_intc>; + status = "okay"; + }; + + hda_host_in: dma@72c00 { + compatible = "intel,adsp-hda-host-in"; + #dma-cells = <1>; + reg = <0x00072c00 0x40>; + dma-channels = <11>; + dma-buf-addr-alignment = <128>; + dma-buf-size-alignment = <32>; + dma-copy-alignment = <32>; + power-domain = <&hst_domain>; + interrupts = <12 0 0>; + interrupt-parent = <&ace_intc>; + status = "okay"; + }; + + adsp_host_ipc: ace_host_ipc@73000 { + compatible = "intel,adsp-host-ipc"; + status = "okay"; + reg = <0x73000 0x30>; + interrupts = <0 0 0>; + interrupt-parent = <&ace_intc>; + }; + + hda_link_out: dma@79400 { + compatible = "intel,adsp-hda-link-out"; + #dma-cells = <1>; + reg = <0x00079400 0x40>; + dma-channels = <9>; + dma-buf-addr-alignment = <128>; + dma-buf-size-alignment = <32>; + dma-copy-alignment = <32>; + power-domain = <&io0_domain>; + status = "okay"; + }; + + hda_link_in: dma@79800 { + compatible = "intel,adsp-hda-link-in"; + #dma-cells = <1>; + reg = <0x00079800 0x40>; + dma-channels = <11>; + dma-buf-addr-alignment = <128>; + dma-buf-size-alignment = <32>; + dma-copy-alignment = <32>; + power-domain = <&io0_domain>; + status = "okay"; + }; + + /* This is actually an array of per-core designware + * controllers, but the special setup and extra + * masking layer makes it easier for MTL to handle + * this internally. + */ + ace_intc: ace_intc@94000 { + compatible = "intel,ace-intc"; + reg = <0x94000 0xc00>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <4 0 0>; + num-irqs = <28>; + interrupt-parent = <&core_intc>; + }; + + tlb: tlb@17e000 { + compatible = "intel,adsp-mtl-tlb"; + reg = <0x17e000 0x1000>; + paddr-size = <12>; + exec-bit-idx = <14>; + write-bit-idx= <15>; + }; + + timer: timer { + compatible = "intel,adsp-timer"; + syscon = <&tts>; + }; + }; + + hdas { + #address-cells = <1>; + #size-cells = <0>; + + hda0: hda@0 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0>; + }; + hda1: hda@1 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <1>; + }; + hda2: hda@2 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <2>; + }; + hda3: hda@3 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <3>; + }; + hda4: hda@4 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <4>; + }; + hda5: hda@5 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <5>; + }; + hda6: hda@6 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <6>; + }; + hda7: hda@7 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <7>; + }; + hda8: hda@8 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <8>; + }; + hda9: hda@9 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <9>; + }; + hda10: hda@a { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0a>; + }; + hda11: hda@b { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0b>; + }; + hda12: hda@c { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0c>; + }; + hda13: hda@d { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0d>; + }; + hda14: hda@e { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0e>; + }; + hda15: hda@f { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x0f>; + }; + hda16: hda@10 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x10>; + }; + hda17: hda@11 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x11>; + }; + hda18: hda@12 { + compatible = "intel,hda-dai"; + status = "okay"; + reg = <0x12>; + }; + }; +}; diff --git a/soc/intel/intel_adsp/ace/CMakeLists.txt b/soc/intel/intel_adsp/ace/CMakeLists.txt index 0c9c43eb339..519275d9047 100644 --- a/soc/intel/intel_adsp/ace/CMakeLists.txt +++ b/soc/intel/intel_adsp/ace/CMakeLists.txt @@ -20,7 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c) zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c) if (CONFIG_XTENSA_MMU) - zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30_PTL mmu_ptl.c) + zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30 mmu_ace30.c) endif() set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30 similarity index 96% rename from soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl rename to soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30 index b5c67ea0f0b..a11e50a2af0 100644 --- a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30 @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 -if SOC_INTEL_ACE30_PTL +if SOC_INTEL_ACE30 config MP_MAX_NUM_CPUS default 5 diff --git a/soc/intel/intel_adsp/ace/Kconfig.soc b/soc/intel/intel_adsp/ace/Kconfig.soc index 89ef2eb30db..729cd1eb4ab 100644 --- a/soc/intel/intel_adsp/ace/Kconfig.soc +++ b/soc/intel/intel_adsp/ace/Kconfig.soc @@ -20,7 +20,7 @@ config SOC_INTEL_ACE20_LNL help ACE 2.0 Lunar Lake PCH -config SOC_INTEL_ACE30_PTL +config SOC_INTEL_ACE30 bool select SOC_SERIES_INTEL_ADSP_ACE help @@ -32,9 +32,9 @@ config SOC_SERIES config SOC_TOOLCHAIN_NAME default "intel_ace15_mtpm" if SOC_INTEL_ACE15_MTPM default "intel_ace15_mtpm" if SOC_INTEL_ACE20_LNL - default "intel_ace30_ptl" if SOC_INTEL_ACE30_PTL + default "intel_ace30_ptl" if SOC_INTEL_ACE30 config SOC default "ace15_mtpm" if SOC_INTEL_ACE15_MTPM default "ace20_lnl" if SOC_INTEL_ACE20_LNL - default "ace30_ptl" if SOC_INTEL_ACE30_PTL + default "ace30" if SOC_INTEL_ACE30 diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_boot.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h rename to soc/intel/intel_adsp/ace/include/ace30/adsp_boot.h diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h rename to soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_ipc_regs.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h rename to soc/intel/intel_adsp/ace/include/ace30/adsp_ipc_regs.h diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_power.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_power.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_power.h rename to soc/intel/intel_adsp/ace/include/ace30/adsp_power.h diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_shim.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h rename to soc/intel/intel_adsp/ace/include/ace30/adsp_shim.h diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/dmic_regs_ace3x.h b/soc/intel/intel_adsp/ace/include/ace30/dmic_regs_ace3x.h similarity index 100% rename from soc/intel/intel_adsp/ace/include/ace30_ptl/dmic_regs_ace3x.h rename to soc/intel/intel_adsp/ace/include/ace30/dmic_regs_ace3x.h diff --git a/soc/intel/intel_adsp/ace/include/dmic_regs.h b/soc/intel/intel_adsp/ace/include/dmic_regs.h index df69d3687f1..bff34b2dfc9 100644 --- a/soc/intel/intel_adsp/ace/include/dmic_regs.h +++ b/soc/intel/intel_adsp/ace/include/dmic_regs.h @@ -351,8 +351,8 @@ #include #elif CONFIG_SOC_INTEL_ACE15_MTPM #include -#elif CONFIG_SOC_INTEL_ACE30_PTL -#include +#elif CONFIG_SOC_INTEL_ACE30 +#include #else #error "Unknown SoC" #endif diff --git a/soc/intel/intel_adsp/common/clk.c b/soc/intel/intel_adsp/common/clk.c index ebcda7be1e7..66c86202198 100644 --- a/soc/intel/intel_adsp/common/clk.c +++ b/soc/intel/intel_adsp/common/clk.c @@ -96,7 +96,7 @@ void adsp_clock_init(void) } else { platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_IPLL; } -#if CONFIG_SOC_INTEL_ACE30_PTL +#if CONFIG_SOC_INTEL_ACE30 /* Set the Cardinal clock divider to 18 to get 24.576MHz */ ACE_DfPMCCU.dfcrodiv &= ACE_CRODIV_CARCDS_MASK; ACE_DfPMCCU.dfcrodiv |= ACE_CRODIV_CARCDS(0x12); diff --git a/soc/intel/intel_adsp/soc.yml b/soc/intel/intel_adsp/soc.yml index 0f889aea963..e797abd9de6 100644 --- a/soc/intel/intel_adsp/soc.yml +++ b/soc/intel/intel_adsp/soc.yml @@ -5,7 +5,7 @@ family: socs: - name: ace15_mtpm - name: ace20_lnl - - name: ace30_ptl + - name: ace30 - name: intel_adsp_cavs socs: - name: cavs25 diff --git a/tests/kernel/mem_protect/sys_sem/boards/intel_adsp_ace30_ptl.conf b/tests/kernel/mem_protect/sys_sem/boards/intel_adsp_ace30.conf similarity index 100% rename from tests/kernel/mem_protect/sys_sem/boards/intel_adsp_ace30_ptl.conf rename to tests/kernel/mem_protect/sys_sem/boards/intel_adsp_ace30.conf diff --git a/tests/kernel/mutex/sys_mutex/boards/intel_adsp_ace30_ptl.conf b/tests/kernel/mutex/sys_mutex/boards/intel_adsp_ace30.conf similarity index 100% rename from tests/kernel/mutex/sys_mutex/boards/intel_adsp_ace30_ptl.conf rename to tests/kernel/mutex/sys_mutex/boards/intel_adsp_ace30.conf diff --git a/tests/kernel/queue/boards/intel_adsp_ace30_ptl.conf b/tests/kernel/queue/boards/intel_adsp_ace30.conf similarity index 100% rename from tests/kernel/queue/boards/intel_adsp_ace30_ptl.conf rename to tests/kernel/queue/boards/intel_adsp_ace30.conf diff --git a/tests/lib/c_lib/thrd/boards/intel_adsp_ace30_ptl.conf b/tests/lib/c_lib/thrd/boards/intel_adsp_ace30.conf similarity index 100% rename from tests/lib/c_lib/thrd/boards/intel_adsp_ace30_ptl.conf rename to tests/lib/c_lib/thrd/boards/intel_adsp_ace30.conf From 9bdf25ebe1bd33065433bd8242323bdc56345102 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 30 Sep 2024 13:25:49 +0300 Subject: [PATCH 03/20] [nrf fromtree] dts: xtensa: nxp_imx8: add power domain for irqsteer Add power domain DT node for the irqsteer and a reference to it in irqsteer's DT node. Signed-off-by: Laurentiu Mihalcea (cherry picked from commit fdbf4d23df69f796fb73d8cfc90cf583634e3d57) --- dts/xtensa/nxp/nxp_imx8.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index 87713a71200..8dba2b7af08 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { cpus { @@ -34,6 +35,7 @@ irqsteer: interrupt-controller@510a0000 { compatible = "nxp,irqsteer-intc"; reg = <0x510a0000 DT_SIZE_K(64)>; + power-domain = <&irqstr_pd>; #size-cells = <0>; #address-cells = <1>; @@ -167,6 +169,17 @@ compatible = "nxp,imx8-pinctrl"; }; }; + + power-domains { + #address-cells = <1>; + #size-cells = <0>; + + irqstr_pd: pd@0 { + compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd"; + reg = <0>; + nxp,resource-id = ; + }; + }; }; lpuart2: serial@5a080000 { From 4e8040745edb332cf6daa0c891c67b044e0b4a6d Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 9 Oct 2024 15:53:56 +0300 Subject: [PATCH 04/20] [nrf fromtree] dts: xtensa: nxp_imx8: add bus clock for sai1 Add bus clock for `sai1` node. Signed-off-by: Laurentiu Mihalcea (cherry picked from commit 1174ea522ffa218cf4dc87d714f93742c508f3c2) --- dts/xtensa/nxp/nxp_imx8.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index 8dba2b7af08..21347b595fe 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -132,6 +132,8 @@ reg = <0x59050000 DT_SIZE_K(64)>; interrupt-parent = <&master5>; interrupts = <28>; + clocks = <&ccm IMX_CCM_SAI1_CLK 0x0 0x0>; + clock-names = "bus"; dai-index = <1>; dmas = <&edma0 15 0>, <&edma0 14 0>; dma-names = "tx", "rx"; From 58866f0bb3022924c8d8155e1eb557ce7169ce4f Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Wed, 18 Sep 2024 06:30:39 +0900 Subject: [PATCH 05/20] [nrf fromtree] tests: drivers: build_all: Add power_domain drivers test Add build_all test for power_domain drivers. Signed-off-by: TOKITA Hiroshi (cherry picked from commit 2c1274f6a9c1d62505783eb47f5817bf50877d39) --- .../build_all/power_domain/CMakeLists.txt | 8 +++++ .../build_all/power_domain/app.overlay | 31 +++++++++++++++++++ tests/drivers/build_all/power_domain/prj.conf | 4 +++ .../drivers/build_all/power_domain/src/main.c | 10 ++++++ .../build_all/power_domain/testcase.yaml | 14 +++++++++ 5 files changed, 67 insertions(+) create mode 100644 tests/drivers/build_all/power_domain/CMakeLists.txt create mode 100644 tests/drivers/build_all/power_domain/app.overlay create mode 100644 tests/drivers/build_all/power_domain/prj.conf create mode 100644 tests/drivers/build_all/power_domain/src/main.c create mode 100644 tests/drivers/build_all/power_domain/testcase.yaml diff --git a/tests/drivers/build_all/power_domain/CMakeLists.txt b/tests/drivers/build_all/power_domain/CMakeLists.txt new file mode 100644 index 00000000000..0ee1f839afd --- /dev/null +++ b/tests/drivers/build_all/power_domain/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(build_all_power_domain) + +FILE(GLOB app_sources src/*.c) +target_sources(app PRIVATE ${app_sources}) diff --git a/tests/drivers/build_all/power_domain/app.overlay b/tests/drivers/build_all/power_domain/app.overlay new file mode 100644 index 00000000000..0551d1b0289 --- /dev/null +++ b/tests/drivers/build_all/power_domain/app.overlay @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + test { + #address-cells = <1>; + #size-cells = <1>; + + test_gpio: gpio@deadbeef { + compatible = "vnd,gpio"; + gpio-controller; + reg = <0xdeadbeef 0x1000>; + #gpio-cells = <0x2>; + status = "okay"; + }; + + power_domain_gpio { + compatible = "power-domain-gpio"; + enable-gpios = <&test_gpio 0 0>; + zephyr,pm-device-runtime-auto; + }; + + power_domain_gpio_monitor { + compatible = "power-domain-gpio-monitor"; + status = "okay"; + gpios = <&test_gpio 0 0>; + }; + }; +}; diff --git a/tests/drivers/build_all/power_domain/prj.conf b/tests/drivers/build_all/power_domain/prj.conf new file mode 100644 index 00000000000..3a4d0d53f65 --- /dev/null +++ b/tests/drivers/build_all/power_domain/prj.conf @@ -0,0 +1,4 @@ +CONFIG_TEST=y +CONFIG_TEST_USERSPACE=y +CONFIG_GPIO=y +CONFIG_POWER_DOMAIN=y diff --git a/tests/drivers/build_all/power_domain/src/main.c b/tests/drivers/build_all/power_domain/src/main.c new file mode 100644 index 00000000000..19f5ee731af --- /dev/null +++ b/tests/drivers/build_all/power_domain/src/main.c @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +int main(void) +{ + return 0; +} diff --git a/tests/drivers/build_all/power_domain/testcase.yaml b/tests/drivers/build_all/power_domain/testcase.yaml new file mode 100644 index 00000000000..e1e10d2f8e2 --- /dev/null +++ b/tests/drivers/build_all/power_domain/testcase.yaml @@ -0,0 +1,14 @@ +common: + build_only: true + tags: + - drivers + - power_domain + platform_allow: + - native_sim + - native_sim/native/64 +tests: + drivers.power_domain.build: {} + drivers.power_domain.build.pm: + extra_configs: + - CONFIG_PM_DEVICE=y + - CONFIG_PM_DEVICE_RUNTIME=y From db9dedf82f00d6e2ce73ef4223881bb633aab791 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 16 Oct 2024 10:33:59 +0200 Subject: [PATCH 06/20] [nrf fromtree] pm: s/power-domain/power-domains and add power-domain-names Some devices may belong to >1 power domain, so with the current design this is something not possible to describe. It's worth to note that Linux also uses the `power-domains` naming scheme, not `power-domain`. This patch also introduces `power-domain-names` so that each entry in `power-domains` can be given a name if needed. `#power-domain-cells` is now required as well. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit f989711a60d434fc6a2023adda690ba21e586bb3) --- doc/services/pm/device_runtime.rst | 2 +- doc/services/pm/power_domain.rst | 4 +-- dts/bindings/base/base.yaml | 12 +++++++ dts/bindings/base/pm.yaml | 9 ----- .../power-domain/intel,adsp-power-domain.yaml | 3 ++ dts/bindings/power-domain/nxp,scu-pd.yaml | 3 ++ .../power-domain-gpio-monitor.yaml | 3 ++ .../power-domain/power-domain-gpio.yaml | 3 ++ dts/bindings/power-domain/power-domain.yaml | 4 +++ dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi | 33 ++++++++++++------- dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi | 12 +++++-- dts/xtensa/intel/intel_adsp_ace30.dtsi | 24 +++++++++----- dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi | 24 +++++++++----- dts/xtensa/nxp/nxp_imx8.dtsi | 3 +- include/zephyr/pm/device.h | 2 +- .../build_all/power_domain/app.overlay | 2 ++ tests/kernel/device/app.overlay | 7 ++-- .../device/boards/hifive_unmatched.overlay | 4 +-- .../subsys/pm/device_driver_init/app.overlay | 15 ++++++--- .../pm/device_power_domains/app.overlay | 7 ++-- tests/subsys/pm/power_domain/app.overlay | 8 +++-- 21 files changed, 124 insertions(+), 60 deletions(-) diff --git a/doc/services/pm/device_runtime.rst b/doc/services/pm/device_runtime.rst index c6173ef66f1..350874009b9 100644 --- a/doc/services/pm/device_runtime.rst +++ b/doc/services/pm/device_runtime.rst @@ -26,7 +26,7 @@ asynchronously, it will be put into the :c:enumerator:`PM_DEVICE_STATE_SUSPENDING` state first and then into the :c:enumerator:`PM_DEVICE_STATE_SUSPENDED` state when the action is run. -For devices on a power domain (via the devicetree 'power-domain' property), device runtime +For devices on a power domain (via the devicetree 'power-domains' property), device runtime power management automatically attempts to request and release the dependent domain in response to :c:func:`pm_device_runtime_get` and :c:func:`pm_device_runtime_put` calls on the child device. diff --git a/doc/services/pm/power_domain.rst b/doc/services/pm/power_domain.rst index faa677b796a..bdab54a54e7 100644 --- a/doc/services/pm/power_domain.rst +++ b/doc/services/pm/power_domain.rst @@ -131,13 +131,13 @@ Devices belonging to this device can be declared referring it in the &gpio0 { compatible = "zephyr,gpio-emul"; gpio-controller; - power-domain = <&gpio_domain>; + power-domains = <&gpio_domain>; }; &gpio1 { compatible = "zephyr,gpio-emul"; gpio-controller; - power-domain = <&gpio_domain>; + power-domains = <&gpio_domain>; }; All devices under a domain will be notified when the domain changes diff --git a/dts/bindings/base/base.yaml b/dts/bindings/base/base.yaml index b2e670fb5d8..676292a296a 100644 --- a/dts/bindings/base/base.yaml +++ b/dts/bindings/base/base.yaml @@ -93,6 +93,18 @@ properties: type: string-array description: Provided names of mailbox / IPM channel specifiers + power-domains: + type: phandle-array + description: Power domain specifiers + + power-domain-names: + type: string-array + description: Provided names of power domain specifiers + + "#power-domain-cells": + type: int + description: Number of cells in power-domains property + zephyr,deferred-init: type: boolean description: | diff --git a/dts/bindings/base/pm.yaml b/dts/bindings/base/pm.yaml index 50c016d07bd..6c0ffb1f637 100644 --- a/dts/bindings/base/pm.yaml +++ b/dts/bindings/base/pm.yaml @@ -16,15 +16,6 @@ properties: Wake up capable devices are disabled (interruptions will not wake up the system) by default but they can be enabled at runtime if necessary. - power-domain: - type: phandle - description: | - - Power domain the device belongs to. - - The device will be notified when the power domain it belongs to is either - suspended or resumed. - zephyr,pm-device-runtime-auto: type: boolean description: | diff --git a/dts/bindings/power-domain/intel,adsp-power-domain.yaml b/dts/bindings/power-domain/intel,adsp-power-domain.yaml index 70bf2a2c1ba..08533f9ea4c 100644 --- a/dts/bindings/power-domain/intel,adsp-power-domain.yaml +++ b/dts/bindings/power-domain/intel,adsp-power-domain.yaml @@ -17,3 +17,6 @@ properties: read_address (PWRSTS) to set power active or confirm power active for a desired domain. Same for write and read addresses + + "#power-domain-cells": + const: 0 diff --git a/dts/bindings/power-domain/nxp,scu-pd.yaml b/dts/bindings/power-domain/nxp,scu-pd.yaml index 7e1d0855389..30f7b2e6474 100644 --- a/dts/bindings/power-domain/nxp,scu-pd.yaml +++ b/dts/bindings/power-domain/nxp,scu-pd.yaml @@ -15,3 +15,6 @@ properties: Number used by the firmware running on the SCU to identify the resource on which the PD-related operations are to be performed. + + "#power-domain-cells": + const: 0 diff --git a/dts/bindings/power-domain/power-domain-gpio-monitor.yaml b/dts/bindings/power-domain/power-domain-gpio-monitor.yaml index 734aab8e6f7..45cee1387be 100644 --- a/dts/bindings/power-domain/power-domain-gpio-monitor.yaml +++ b/dts/bindings/power-domain/power-domain-gpio-monitor.yaml @@ -20,3 +20,6 @@ properties: required: true description: | GPIO to use to sense if rail is powered on. + + "#power-domain-cells": + const: 0 diff --git a/dts/bindings/power-domain/power-domain-gpio.yaml b/dts/bindings/power-domain/power-domain-gpio.yaml index 1ece08fb5e3..bba4c8602fe 100644 --- a/dts/bindings/power-domain/power-domain-gpio.yaml +++ b/dts/bindings/power-domain/power-domain-gpio.yaml @@ -28,3 +28,6 @@ properties: type: int default: 0 description: Off delay time, in microseconds + + "#power-domain-cells": + const: 0 diff --git a/dts/bindings/power-domain/power-domain.yaml b/dts/bindings/power-domain/power-domain.yaml index 429667fbb2e..1040f5c43b7 100644 --- a/dts/bindings/power-domain/power-domain.yaml +++ b/dts/bindings/power-domain/power-domain.yaml @@ -6,3 +6,7 @@ description: Properties for power domains compatible: "power-domain" include: base.yaml + +properties: + "#power-domain-cells": + const: 0 diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index 7c2050b109f..3500e51f761 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -150,7 +150,7 @@ fifo = <0x0008>; interrupts = <0x08 0 0>; interrupt-parent = <&ace_intc>; - power-domain = <&hub_ulp_domain>; + power-domains = <&hub_ulp_domain>; }; dmic1: dmic1@10000 { @@ -160,7 +160,7 @@ fifo = <0x0108>; interrupts = <0x09 0 0>; interrupt-parent = <&ace_intc>; - power-domain = <&hub_ulp_domain>; + power-domains = <&hub_ulp_domain>; }; /* @@ -285,7 +285,7 @@ dmas = <&lpgpdma0 2 &lpgpdma0 3>; dma-names = "tx", "rx"; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; ssp-index = <0>; status = "okay"; @@ -307,7 +307,7 @@ dmas = <&lpgpdma0 4 &lpgpdma0 5>; dma-names = "tx", "rx"; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; ssp-index = <1>; status = "okay"; @@ -329,7 +329,7 @@ dmas = <&lpgpdma0 6 &lpgpdma0 7>; dma-names = "tx", "rx"; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; ssp-index = <2>; status = "okay"; @@ -387,38 +387,47 @@ hub_ulp_domain: hub_ulp_domain { compatible = "intel,adsp-power-domain"; bit-position = <15>; + #power-domain-cells = <0>; }; ml1_domain: ml1_domain { compatible = "intel,adsp-power-domain"; bit-position = <13>; + #power-domain-cells = <0>; }; ml0_domain: ml0_domain { compatible = "intel,adsp-power-domain"; bit-position = <12>; + #power-domain-cells = <0>; }; io3_domain: io3_domain { compatible = "intel,adsp-power-domain"; bit-position = <11>; + #power-domain-cells = <0>; }; io2_domain: io2_domain { compatible = "intel,adsp-power-domain"; bit-position = <10>; + #power-domain-cells = <0>; }; io1_domain: io1_domain { compatible = "intel,adsp-power-domain"; bit-position = <9>; + #power-domain-cells = <0>; }; io0_domain: io0_domain { compatible = "intel,adsp-power-domain"; bit-position = <8>; + #power-domain-cells = <0>; }; hub_hp_domain: hub_hp_domain { compatible = "intel,adsp-power-domain"; bit-position = <6>; + #power-domain-cells = <0>; }; hst_domain: hst_domain { compatible = "intel,adsp-power-domain"; bit-position = <4>; + #power-domain-cells = <0>; }; }; @@ -464,7 +473,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <16>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; }; @@ -476,7 +485,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <16>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; }; @@ -488,7 +497,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <16>; - power-domain = <&hst_domain>; + power-domains = <&hst_domain>; interrupts = <13 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -502,7 +511,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <16>; - power-domain = <&hst_domain>; + power-domains = <&hst_domain>; interrupts = <12 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -541,7 +550,7 @@ dma-buf-size-alignment = <4>; dma-copy-alignment = <4>; status = "okay"; - power-domain = <&hub_ulp_domain>; + power-domains = <&hub_ulp_domain>; zephyr,pm-device-runtime-auto; }; @@ -555,7 +564,7 @@ dma-buf-size-alignment = <4>; dma-copy-alignment = <4>; status = "okay"; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; zephyr,pm-device-runtime-auto; }; @@ -568,7 +577,7 @@ interrupt-parent = <&core_intc>; dma-buf-size-alignment = <4>; dma-copy-alignment = <4>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; zephyr,pm-device-runtime-auto; }; diff --git a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi index c26d2b815fe..8dc4489d0ee 100644 --- a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi @@ -215,7 +215,7 @@ dmas = <&hda_link_out 1 &hda_link_in 1>; dma-names = "tx", "rx"; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; ssp-index = <0>; status = "okay"; @@ -238,7 +238,7 @@ dmas = <&hda_link_out 2 &hda_link_in 2>; dma-names = "tx", "rx"; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; ssp-index = <1>; status = "okay"; @@ -261,7 +261,7 @@ dmas = <&hda_link_out 3 &hda_link_in 3>; dma-names = "tx", "rx"; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; ssp-index = <2>; status = "okay"; @@ -319,26 +319,32 @@ hub_ulp_domain: hub_ulp_domain { compatible = "intel,adsp-power-domain"; bit-position = <15>; + #power-domain-cells = <0>; }; ml0_domain: ml0_domain { compatible = "intel,adsp-power-domain"; bit-position = <12>; + #power-domain-cells = <0>; }; io1_domain: io1_domain { compatible = "intel,adsp-power-domain"; bit-position = <9>; + #power-domain-cells = <0>; }; io0_domain: io0_domain { compatible = "intel,adsp-power-domain"; bit-position = <8>; + #power-domain-cells = <0>; }; hub_hp_domain: hub_hp_domain { compatible = "intel,adsp-power-domain"; bit-position = <6>; + #power-domain-cells = <0>; }; hst_domain: hst_domain { compatible = "intel,adsp-power-domain"; bit-position = <5>; + #power-domain-cells = <0>; }; }; diff --git a/dts/xtensa/intel/intel_adsp_ace30.dtsi b/dts/xtensa/intel/intel_adsp_ace30.dtsi index 97be77eb757..26ae1c47f56 100644 --- a/dts/xtensa/intel/intel_adsp_ace30.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace30.dtsi @@ -169,7 +169,7 @@ fifo = <0x0008>; interrupts = <0x08 0 0>; interrupt-parent = <&ace_intc>; - power-domain = <&hub_ulp_domain>; + power-domains = <&hub_ulp_domain>; }; dmic1: dai-dmic1@10100 { @@ -179,7 +179,7 @@ fifo = <0x0108>; interrupts = <0x08 0 0>; interrupt-parent = <&ace_intc>; - power-domain = <&hub_ulp_domain>; + power-domains = <&hub_ulp_domain>; }; dmicvss: dmicvss@16000 { @@ -212,7 +212,7 @@ &hda_link_in 1>; dma-names = "tx", "rx"; ssp-index = <0>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; ssp00: ssp@0 { @@ -277,7 +277,7 @@ &hda_link_in 2>; dma-names = "tx", "rx"; ssp-index = <1>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; ssp10: ssp@10 { @@ -342,7 +342,7 @@ &hda_link_in 3>; dma-names = "tx", "rx"; ssp-index = <2>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; ssp20: ssp@20 { @@ -441,26 +441,32 @@ hub_ulp_domain: hub_ulp_domain { compatible = "intel,adsp-power-domain"; bit-position = <15>; + #power-domain-cells = <0>; }; ml0_domain: ml0_domain { compatible = "intel,adsp-power-domain"; bit-position = <12>; + #power-domain-cells = <0>; }; io1_domain: io1_domain { compatible = "intel,adsp-power-domain"; bit-position = <9>; + #power-domain-cells = <0>; }; io0_domain: io0_domain { compatible = "intel,adsp-power-domain"; bit-position = <8>; + #power-domain-cells = <0>; }; hub_hp_domain: hub_hpp_domain { compatible = "intel,adsp-power-domain"; bit-position = <6>; + #power-domain-cells = <0>; }; hst_domain: hst_domain { compatible = "intel,adsp-power-domain"; bit-position = <5>; + #power-domain-cells = <0>; }; }; @@ -498,7 +504,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&hst_domain>; + power-domains = <&hst_domain>; interrupts = <13 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -512,7 +518,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&hst_domain>; + power-domains = <&hst_domain>; interrupts = <12 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -534,7 +540,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; }; @@ -546,7 +552,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; }; diff --git a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi index 97be77eb757..26ae1c47f56 100644 --- a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi @@ -169,7 +169,7 @@ fifo = <0x0008>; interrupts = <0x08 0 0>; interrupt-parent = <&ace_intc>; - power-domain = <&hub_ulp_domain>; + power-domains = <&hub_ulp_domain>; }; dmic1: dai-dmic1@10100 { @@ -179,7 +179,7 @@ fifo = <0x0108>; interrupts = <0x08 0 0>; interrupt-parent = <&ace_intc>; - power-domain = <&hub_ulp_domain>; + power-domains = <&hub_ulp_domain>; }; dmicvss: dmicvss@16000 { @@ -212,7 +212,7 @@ &hda_link_in 1>; dma-names = "tx", "rx"; ssp-index = <0>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; ssp00: ssp@0 { @@ -277,7 +277,7 @@ &hda_link_in 2>; dma-names = "tx", "rx"; ssp-index = <1>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; ssp10: ssp@10 { @@ -342,7 +342,7 @@ &hda_link_in 3>; dma-names = "tx", "rx"; ssp-index = <2>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; ssp20: ssp@20 { @@ -441,26 +441,32 @@ hub_ulp_domain: hub_ulp_domain { compatible = "intel,adsp-power-domain"; bit-position = <15>; + #power-domain-cells = <0>; }; ml0_domain: ml0_domain { compatible = "intel,adsp-power-domain"; bit-position = <12>; + #power-domain-cells = <0>; }; io1_domain: io1_domain { compatible = "intel,adsp-power-domain"; bit-position = <9>; + #power-domain-cells = <0>; }; io0_domain: io0_domain { compatible = "intel,adsp-power-domain"; bit-position = <8>; + #power-domain-cells = <0>; }; hub_hp_domain: hub_hpp_domain { compatible = "intel,adsp-power-domain"; bit-position = <6>; + #power-domain-cells = <0>; }; hst_domain: hst_domain { compatible = "intel,adsp-power-domain"; bit-position = <5>; + #power-domain-cells = <0>; }; }; @@ -498,7 +504,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&hst_domain>; + power-domains = <&hst_domain>; interrupts = <13 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -512,7 +518,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&hst_domain>; + power-domains = <&hst_domain>; interrupts = <12 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -534,7 +540,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; }; @@ -546,7 +552,7 @@ dma-buf-addr-alignment = <128>; dma-buf-size-alignment = <32>; dma-copy-alignment = <32>; - power-domain = <&io0_domain>; + power-domains = <&io0_domain>; status = "okay"; }; diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index 21347b595fe..701f2a1dc39 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -35,7 +35,7 @@ irqsteer: interrupt-controller@510a0000 { compatible = "nxp,irqsteer-intc"; reg = <0x510a0000 DT_SIZE_K(64)>; - power-domain = <&irqstr_pd>; + power-domains = <&irqstr_pd>; #size-cells = <0>; #address-cells = <1>; @@ -180,6 +180,7 @@ compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd"; reg = <0>; nxp,resource-id = ; + #power-domain-cells = <0>; }; }; }; diff --git a/include/zephyr/pm/device.h b/include/zephyr/pm/device.h index a6e2ef032c0..f7c008f3cf2 100644 --- a/include/zephyr/pm/device.h +++ b/include/zephyr/pm/device.h @@ -208,7 +208,7 @@ BUILD_ASSERT(offsetof(struct pm_device_isr, base) == 0); #ifdef CONFIG_PM_DEVICE_POWER_DOMAIN #define Z_PM_DEVICE_POWER_DOMAIN_INIT(_node_id) \ .domain = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(_node_id, \ - power_domain)), + power_domains)), #else #define Z_PM_DEVICE_POWER_DOMAIN_INIT(obj) #endif /* CONFIG_PM_DEVICE_POWER_DOMAIN */ diff --git a/tests/drivers/build_all/power_domain/app.overlay b/tests/drivers/build_all/power_domain/app.overlay index 0551d1b0289..79437b515f2 100644 --- a/tests/drivers/build_all/power_domain/app.overlay +++ b/tests/drivers/build_all/power_domain/app.overlay @@ -19,6 +19,7 @@ power_domain_gpio { compatible = "power-domain-gpio"; enable-gpios = <&test_gpio 0 0>; + #power-domain-cells = <0>; zephyr,pm-device-runtime-auto; }; @@ -26,6 +27,7 @@ compatible = "power-domain-gpio-monitor"; status = "okay"; gpios = <&test_gpio 0 0>; + #power-domain-cells = <0>; }; }; }; diff --git a/tests/kernel/device/app.overlay b/tests/kernel/device/app.overlay index 108f14bdb3e..ac77f271cc5 100644 --- a/tests/kernel/device/app.overlay +++ b/tests/kernel/device/app.overlay @@ -69,17 +69,20 @@ fakedomain_0: fakedomain_0 { compatible = "fakedomain"; status = "okay"; - power-domain = <&fakedomain_2>; + power-domains = <&fakedomain_2>; + #power-domain-cells = <0>; }; fakedomain_1: fakedomain_1 { compatible = "fakedomain"; status = "okay"; - power-domain = <&fakedomain_0>; + power-domains = <&fakedomain_0>; + #power-domain-cells = <0>; }; fakedomain_2: fakedomain_2 { compatible = "fakedomain"; status = "okay"; + #power-domain-cells = <0>; }; }; diff --git a/tests/kernel/device/boards/hifive_unmatched.overlay b/tests/kernel/device/boards/hifive_unmatched.overlay index 05f9992d889..6f16d2d9b7b 100644 --- a/tests/kernel/device/boards/hifive_unmatched.overlay +++ b/tests/kernel/device/boards/hifive_unmatched.overlay @@ -66,13 +66,13 @@ fakedomain_0: fakedomain_0 { compatible = "fakedomain"; status = "okay"; - power-domain = <&fakedomain_2>; + power-domains = <&fakedomain_2>; }; fakedomain_1: fakedomain_1 { compatible = "fakedomain"; status = "okay"; - power-domain = <&fakedomain_0>; + power-domains = <&fakedomain_0>; }; fakedomain_2: fakedomain_2 { diff --git a/tests/subsys/pm/device_driver_init/app.overlay b/tests/subsys/pm/device_driver_init/app.overlay index a5518b74be2..ea02a035ba8 100644 --- a/tests/subsys/pm/device_driver_init/app.overlay +++ b/tests/subsys/pm/device_driver_init/app.overlay @@ -2,43 +2,50 @@ test_reg: test_reg { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 0 0>; + #power-domain-cells = <0>; }; test_reg_chained: test_reg_chained { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 1 0>; - power-domain = <&test_reg>; + power-domains = <&test_reg>; + #power-domain-cells = <0>; }; test_reg_chained_auto: test_reg_chained_auto { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 2 0>; - power-domain = <&test_reg>; + power-domains = <&test_reg>; + #power-domain-cells = <0>; zephyr,pm-device-runtime-auto; }; test_reg_auto: test_reg_auto { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 3 0>; + #power-domain-cells = <0>; zephyr,pm-device-runtime-auto; }; test_reg_auto_chained: test_reg_auto_chained { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 4 0>; - power-domain = <&test_reg_auto>; + #power-domain-cells = <0>; + power-domains = <&test_reg_auto>; }; test_reg_auto_chained_auto: test_reg_auto_chained_auto { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 5 0>; - power-domain = <&test_reg_auto>; + power-domains = <&test_reg_auto>; + #power-domain-cells = <0>; zephyr,pm-device-runtime-auto; }; test_reg_disabled: test_reg_disabled { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 6 0>; + #power-domain-cells = <0>; status = "disabled"; }; }; diff --git a/tests/subsys/pm/device_power_domains/app.overlay b/tests/subsys/pm/device_power_domains/app.overlay index 0d6dfdfbbd0..e97f3827a2a 100644 --- a/tests/subsys/pm/device_power_domains/app.overlay +++ b/tests/subsys/pm/device_power_domains/app.overlay @@ -2,23 +2,26 @@ test_reg_0: test_reg_0 { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 0 0>; + #power-domain-cells = <0>; }; test_reg_1: test_reg_1 { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 1 0>; + #power-domain-cells = <0>; }; test_reg_chained: test_reg_chained { compatible = "power-domain-gpio"; enable-gpios = <&gpio0 2 0>; - power-domain = <&test_reg_0>; + power-domains = <&test_reg_0>; + #power-domain-cells = <0>; }; test_dev: test_dev { compatible = "test-device-pm"; status = "okay"; - power-domain = <&test_reg_1>; + power-domains = <&test_reg_1>; alternate-domain = <&test_reg_chained>; }; }; diff --git a/tests/subsys/pm/power_domain/app.overlay b/tests/subsys/pm/power_domain/app.overlay index b855ddbac89..2b8acd67b50 100644 --- a/tests/subsys/pm/power_domain/app.overlay +++ b/tests/subsys/pm/power_domain/app.overlay @@ -8,28 +8,30 @@ test_domain: test_domain { compatible = "power-domain"; status = "okay"; + #power-domain-cells = <0>; }; test_dev_a: test_dev_a { compatible = "test-device-pm"; status = "okay"; - power-domain = <&test_domain>; + power-domains = <&test_domain>; }; test_dev_b: test_dev_b { compatible = "test-device-pm"; status = "okay"; - power-domain = <&test_domain>; + power-domains = <&test_domain>; }; test_domain_balanced: test_domain_balanced { compatible = "power-domain"; status = "okay"; + #power-domain-cells = <0>; }; test_dev_balanced: test_dev_balanced { compatible = "test-device-pm"; status = "okay"; - power-domain = <&test_domain_balanced>; + power-domains = <&test_domain_balanced>; }; }; From 2cb95743fa12a54f1138c6bf06b9627aa4d2f2aa Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 10 Oct 2024 14:17:52 +0200 Subject: [PATCH 07/20] [nrf fromtree] dts: bindings: power: add nordic,nrf-global-pd Add binding for Global Power Domain found in nRF54Hx SoCs. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit f3d29d6fd29d04fdec441d5e1fbbdbeb4c3888c4) --- dts/bindings/power/nordic,nrf-gpd.yaml | 11 +++++++++++ .../zephyr/dt-bindings/power/nordic-nrf-gpd.h | 17 +++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 dts/bindings/power/nordic,nrf-gpd.yaml create mode 100644 include/zephyr/dt-bindings/power/nordic-nrf-gpd.h diff --git a/dts/bindings/power/nordic,nrf-gpd.yaml b/dts/bindings/power/nordic,nrf-gpd.yaml new file mode 100644 index 00000000000..feb5f2862e9 --- /dev/null +++ b/dts/bindings/power/nordic,nrf-gpd.yaml @@ -0,0 +1,11 @@ +# Copyright 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic nRF Global Power Domain + +compatible: "nordic,nrf-gpd" + +include: base.yaml + +power-domain-cells: + - id diff --git a/include/zephyr/dt-bindings/power/nordic-nrf-gpd.h b/include/zephyr/dt-bindings/power/nordic-nrf-gpd.h new file mode 100644 index 00000000000..7f6952f6f0b --- /dev/null +++ b/include/zephyr/dt-bindings/power/nordic-nrf-gpd.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD +#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD + +/* numbers aligned to nrfs service identifiers */ +#define NRF_GPD_SLOW_MAIN 2U +#define NRF_GPD_SLOW_ACTIVE 1U +#define NRF_GPD_FAST_MAIN 3U +#define NRF_GPD_FAST_ACTIVE1 0U +#define NRF_GPD_FAST_ACTIVE0 4U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD */ From ded8e40cfc54390a90e6a49394e184dbc1f328f0 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 16 Oct 2024 10:47:17 +0200 Subject: [PATCH 08/20] [nrf fromtree] dts: nordic: nrf54h20: define global power domain Add the global power domain entry. This domain is not memory-mapped but controlled using NRFS services. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit a56a170b7e4009d020969e17f3f82554c5f0b580) --- dts/common/nordic/nrf54h20.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi index 0c891161ab2..ef6c195629c 100644 --- a/dts/common/nordic/nrf54h20.dtsi +++ b/dts/common/nordic/nrf54h20.dtsi @@ -197,6 +197,11 @@ }; }; + gpd: global-power-domain { + compatible = "nordic,nrf-gpd"; + #power-domain-cells = <1>; + }; + soc { #address-cells = <1>; #size-cells = <1>; From f2bdcd06f97a1d46fdbf31fa95aa5f5c0af9f729 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 10 Oct 2024 14:18:51 +0200 Subject: [PATCH 09/20] [nrf fromtree] dts: nordic: nrf54h20: add power domain information So that it can be used to manually control certain power domains. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 01e285c1bad4e1f175502a0bc39b13815c9055c9) --- dts/common/nordic/nrf54h20.dtsi | 84 +++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi index ef6c195629c..3cc9bd5b459 100644 --- a/dts/common/nordic/nrf54h20.dtsi +++ b/dts/common/nordic/nrf54h20.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include /delete-node/ &sw_pwm; @@ -209,6 +210,7 @@ mram1x: mram@e000000 { compatible = "nordic,mram"; reg = <0xe000000 DT_SIZE_K(2048)>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; erase-block-size = <4096>; write-block-size = <16>; }; @@ -494,6 +496,7 @@ reg = <0x86000 0x1000>, <0x2f700000 0x40000>; reg-names = "wrapper", "core"; interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; num-in-eps = <8>; num-out-eps = <10>; ghwcfg1 = <0xaa555000>; @@ -509,6 +512,7 @@ reg = <0x95000 0x500 0x95500 0xb00>; reg-names = "wrapper", "core"; interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; clock-frequency = ; fifo-depth = <32>; max-xfer-size = <16>; @@ -518,18 +522,21 @@ cpusec_bellboard: mailbox@99000 { reg = <0x99000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; #mbox-cells = <1>; }; cpuapp_bellboard: mailbox@9a000 { reg = <0x9a000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; #mbox-cells = <1>; }; cpurad_bellboard: mailbox@9b000 { reg = <0x9b000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; #mbox-cells = <1>; }; @@ -570,6 +577,7 @@ compatible = "nordic,nrf-vpr-coprocessor"; reg = <0x8d4000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8d4000 0x1000>; @@ -590,6 +598,7 @@ reg-names = "wrapper", "m_can", "message_ram"; interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&canpll>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; status = "disabled"; }; @@ -598,6 +607,7 @@ compatible = "nordic,nrf-dppic-global"; reg = <0x8e1000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; }; timer120: timer@8e2000 { @@ -606,6 +616,7 @@ status = "disabled"; cc-num = <6>; interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; max-bit-width = <32>; max-frequency = ; prescaler = <0>; @@ -617,6 +628,7 @@ status = "disabled"; cc-num = <6>; interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; max-bit-width = <32>; max-frequency = ; prescaler = <0>; @@ -627,6 +639,7 @@ reg = <0x8e4000 0x1000>; status = "disabled"; interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; #pwm-cells = <3>; }; @@ -634,6 +647,7 @@ compatible = "nordic,nrf-spim"; reg = <0x8e6000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; easydma-maxcnt-bits = <15>; interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; max-frequency = ; @@ -651,6 +665,7 @@ status = "disabled"; interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&hsfll120>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; endtx-stoptx-supported; frame-timeout-supported; }; @@ -661,6 +676,7 @@ status = "disabled"; easydma-maxcnt-bits = <15>; interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -677,6 +693,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x908000 0x1000>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; cpuppr_vevif_tx: mailbox@0 { compatible = "nordic,nrf-vevif-task-tx"; @@ -692,6 +709,7 @@ compatible = "nordic,nrf-ipct-global"; reg = <0x921000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; channels = <8>; global-domain-id = <13>; }; @@ -700,6 +718,7 @@ compatible = "nordic,nrf-dppic-global"; reg = <0x922000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; }; rtc130: rtc@928000 { @@ -709,6 +728,7 @@ cc-num = <4>; clock-frequency = <32768>; interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; clocks = <&lfclk>; prescaler = <1>; }; @@ -720,6 +740,7 @@ cc-num = <4>; clock-frequency = <32768>; interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; clocks = <&lfclk>; prescaler = <1>; }; @@ -730,6 +751,7 @@ status = "disabled"; interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&lfclk>; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; }; wdt132: watchdog@92c000 { @@ -738,6 +760,7 @@ status = "disabled"; interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&lfclk>; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; }; egu130: egu@92d000 { @@ -745,12 +768,14 @@ reg = <0x92d000 0x1000>; status = "disabled"; interrupts = <301 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; }; gpiote130: gpiote@934000 { compatible = "nordic,nrf-gpiote"; reg = <0x934000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; instance = <130>; }; @@ -760,6 +785,7 @@ status = "disabled"; #gpio-cells = <2>; gpio-controller; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; gpiote-instance = <&gpiote130>; ngpios = <12>; port = <0>; @@ -771,6 +797,7 @@ status = "disabled"; #gpio-cells = <2>; gpio-controller; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; gpiote-instance = <&gpiote130>; ngpios = <12>; port = <1>; @@ -782,6 +809,7 @@ status = "disabled"; #gpio-cells = <2>; gpio-controller; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; gpiote-instance = <&gpiote130>; ngpios = <12>; port = <2>; @@ -793,6 +821,9 @@ status = "disabled"; #gpio-cells = <2>; gpio-controller; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>, + <&gpd NRF_GPD_FAST_ACTIVE1>; + power-domain-names = "peripheral", "pad"; ngpios = <14>; port = <6>; }; @@ -803,6 +834,9 @@ status = "disabled"; #gpio-cells = <2>; gpio-controller; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>, + <&gpd NRF_GPD_FAST_ACTIVE1>; + power-domain-names = "peripheral", "pad"; ngpios = <8>; port = <7>; }; @@ -813,6 +847,7 @@ status = "disabled"; #gpio-cells = <2>; gpio-controller; + power-domains = <&gpd NRF_GPD_SLOW_MAIN>; gpiote-instance = <&gpiote130>; ngpios = <6>; port = <9>; @@ -822,6 +857,7 @@ compatible = "nordic,nrf-dppic-global"; reg = <0x981000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; adc: adc@982000 { @@ -830,6 +866,7 @@ interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>; status = "disabled"; #io-channel-cells = <1>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; comp: comparator@983000 { @@ -841,6 +878,7 @@ reg = <0x983000 0x1000>; status = "disabled"; interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; temp: temperature-sensor@984000 { @@ -848,6 +886,7 @@ reg = <0x984000 0x1000>; interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; nfct: nfct@985000 { @@ -855,12 +894,14 @@ reg = <0x985000 0x1000>; status = "disabled"; interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; dppic132: dppic@991000 { compatible = "nordic,nrf-dppic-global"; reg = <0x991000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; qdec130: qdec@994000 { @@ -868,6 +909,7 @@ reg = <0x994000 0x1000>; status = "disabled"; interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; qdec131: qdec@995000 { @@ -875,6 +917,7 @@ reg = <0x995000 0x1000>; status = "disabled"; interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; grtc: grtc@99c000 { @@ -887,12 +930,14 @@ * one is linked here. */ clocks = <&lfclk>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; dppic133: dppic@9a1000 { compatible = "nordic,nrf-dppic-global"; reg = <0x9a1000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; timer130: timer@9a2000 { @@ -902,6 +947,7 @@ cc-num = <6>; interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-bit-width = <32>; prescaler = <0>; }; @@ -913,6 +959,7 @@ cc-num = <6>; interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-bit-width = <32>; prescaler = <0>; }; @@ -923,6 +970,7 @@ status = "disabled"; interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; #pwm-cells = <3>; }; @@ -932,6 +980,7 @@ status = "disabled"; interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; easydma-maxcnt-bits = <15>; #address-cells = <1>; #size-cells = <0>; @@ -946,6 +995,7 @@ easydma-maxcnt-bits = <15>; interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -963,6 +1013,7 @@ status = "disabled"; interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; nordic,clockpin-enable = ; endtx-stoptx-supported; frame-timeout-supported; @@ -974,6 +1025,7 @@ status = "disabled"; interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; easydma-maxcnt-bits = <15>; #address-cells = <1>; #size-cells = <0>; @@ -988,6 +1040,7 @@ easydma-maxcnt-bits = <15>; interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -1005,6 +1058,7 @@ status = "disabled"; interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; nordic,clockpin-enable = ; endtx-stoptx-supported; frame-timeout-supported; @@ -1014,6 +1068,7 @@ compatible = "nordic,nrf-dppic-global"; reg = <0x9b1000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; timer132: timer@9b2000 { @@ -1023,6 +1078,7 @@ cc-num = <6>; interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-bit-width = <32>; prescaler = <0>; }; @@ -1034,6 +1090,7 @@ cc-num = <6>; interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-bit-width = <32>; prescaler = <0>; }; @@ -1044,6 +1101,7 @@ status = "disabled"; interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; #pwm-cells = <3>; }; @@ -1053,6 +1111,7 @@ status = "disabled"; interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; easydma-maxcnt-bits = <15>; #address-cells = <1>; #size-cells = <0>; @@ -1067,6 +1126,7 @@ easydma-maxcnt-bits = <15>; interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -1084,6 +1144,7 @@ status = "disabled"; interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; nordic,clockpin-enable = ; endtx-stoptx-supported; frame-timeout-supported; @@ -1095,6 +1156,7 @@ status = "disabled"; interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; easydma-maxcnt-bits = <15>; #address-cells = <1>; #size-cells = <0>; @@ -1109,6 +1171,7 @@ easydma-maxcnt-bits = <15>; interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -1126,6 +1189,7 @@ status = "disabled"; interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; nordic,clockpin-enable = ; endtx-stoptx-supported; frame-timeout-supported; @@ -1135,6 +1199,7 @@ compatible = "nordic,nrf-dppic-global"; reg = <0x9c1000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; timer134: timer@9c2000 { @@ -1144,6 +1209,7 @@ cc-num = <6>; interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-bit-width = <32>; prescaler = <0>; }; @@ -1155,6 +1221,7 @@ cc-num = <6>; interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-bit-width = <32>; prescaler = <0>; }; @@ -1166,6 +1233,7 @@ interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; #pwm-cells = <3>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; i2c134: i2c@9c5000 { @@ -1174,6 +1242,7 @@ status = "disabled"; interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; easydma-maxcnt-bits = <15>; #address-cells = <1>; #size-cells = <0>; @@ -1188,6 +1257,7 @@ easydma-maxcnt-bits = <15>; interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -1205,6 +1275,7 @@ status = "disabled"; interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; nordic,clockpin-enable = ; endtx-stoptx-supported; frame-timeout-supported; @@ -1216,6 +1287,7 @@ status = "disabled"; interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; easydma-maxcnt-bits = <15>; #address-cells = <1>; #size-cells = <0>; @@ -1230,6 +1302,7 @@ easydma-maxcnt-bits = <15>; interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -1247,6 +1320,7 @@ status = "disabled"; interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; nordic,clockpin-enable = ; endtx-stoptx-supported; frame-timeout-supported; @@ -1256,6 +1330,7 @@ compatible = "nordic,nrf-dppic-global"; reg = <0x9d1000 0x1000>; status = "disabled"; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; timer136: timer@9d2000 { @@ -1265,6 +1340,7 @@ cc-num = <6>; interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-bit-width = <32>; prescaler = <0>; }; @@ -1276,6 +1352,7 @@ cc-num = <6>; interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-bit-width = <32>; prescaler = <0>; }; @@ -1287,6 +1364,7 @@ interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; #pwm-cells = <3>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; }; i2c136: i2c@9d5000 { @@ -1295,6 +1373,7 @@ status = "disabled"; interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; easydma-maxcnt-bits = <15>; #address-cells = <1>; #size-cells = <0>; @@ -1309,6 +1388,7 @@ easydma-maxcnt-bits = <15>; interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -1326,6 +1406,7 @@ status = "disabled"; interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; nordic,clockpin-enable = ; endtx-stoptx-supported; frame-timeout-supported; @@ -1337,6 +1418,7 @@ status = "disabled"; interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; easydma-maxcnt-bits = <15>; #address-cells = <1>; #size-cells = <0>; @@ -1351,6 +1433,7 @@ easydma-maxcnt-bits = <15>; interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; max-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -1368,6 +1451,7 @@ status = "disabled"; interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; clocks = <&fll16m>; + power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; nordic,clockpin-enable = ; endtx-stoptx-supported; frame-timeout-supported; From b44e8217ee6f6baa2857573c402bca1f14dfe26c Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 10 Oct 2024 15:57:52 +0200 Subject: [PATCH 10/20] [nrf fromtree] drivers: pinctrl: nrf: add flag to signal the FAST_ACTIVE1 peripherals This patch introduces a new flag to indicate if a peripheral belongs to FAST_ACTIVE1 domain. This way, pinctrl knows when to request the SLOW_ACTIVE domain (where CTRLSEL multiplexer resides). Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 9925ec99fddfe26bfd34a8cd4fce1642964573cb) --- drivers/pinctrl/pinctrl_nrf.c | 32 +++++++++++++++++++ .../zephyr/dt-bindings/pinctrl/nrf-pinctrl.h | 12 +++++-- soc/nordic/common/pinctrl_soc.h | 22 ++++++++++++- 3 files changed, 62 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index 7c6d83020bf..1e80de8fe67 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -7,6 +7,9 @@ #include #include +#ifdef CONFIG_SOC_NRF54H20_GPD +#include +#endif BUILD_ASSERT(((NRF_PULL_NONE == NRF_GPIO_PIN_NOPULL) && (NRF_PULL_DOWN == NRF_GPIO_PIN_PULLDOWN) && @@ -352,6 +355,21 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, if (psel != PSEL_DISCONNECTED) { uint32_t pin = psel; +#ifdef CONFIG_SOC_NRF54H20_GPD + if (NRF_GET_GPD_FAST_ACTIVE1(pins[i]) == 1U) { + int ret; + uint32_t d_pin = pin; + NRF_GPIO_Type *port = nrf_gpio_pin_port_decode(&d_pin); + + ret = nrf_gpd_request(NRF_GPD_SLOW_ACTIVE); + if (ret < 0) { + return ret; + } + + port->RETAINCLR = BIT(d_pin); + } +#endif /* CONFIG_SOC_NRF54H20_GPD */ + if (write != NO_WRITE) { nrf_gpio_pin_write(pin, write); } @@ -367,6 +385,20 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, #if NRF_GPIO_HAS_CLOCKPIN nrf_gpio_pin_clock_set(pin, NRF_GET_CLOCKPIN_ENABLE(pins[i])); #endif +#ifdef CONFIG_SOC_NRF54H20_GPD + if (NRF_GET_GPD_FAST_ACTIVE1(pins[i]) == 1U) { + int ret; + uint32_t d_pin = pin; + NRF_GPIO_Type *port = nrf_gpio_pin_port_decode(&d_pin); + + port->RETAINSET = BIT(d_pin); + + ret = nrf_gpd_release(NRF_GPD_SLOW_ACTIVE); + if (ret < 0) { + return ret; + } + } +#endif /* CONFIG_SOC_NRF54H20_GPD */ } } diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h index 7afa6783814..4611baef95c 100644 --- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h @@ -10,7 +10,9 @@ * The whole nRF pin configuration information is encoded in a 32-bit bitfield * organized as follows: * - * - 31..18: Pin function. + * - 31..24: Pin function. + * - 19-23: Reserved. + * - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only) * - 17: Clockpin enable. * - 16: Pin inversion mode. * - 15: Pin low power mode. @@ -25,9 +27,13 @@ */ /** Position of the function field. */ -#define NRF_FUN_POS 18U +#define NRF_FUN_POS 24U /** Mask for the function field. */ -#define NRF_FUN_MSK 0x3FFFU +#define NRF_FUN_MSK 0xFFU +/** Position of the GPD FAST ACTIVE1 */ +#define NRF_GPD_FAST_ACTIVE1_POS 18U +/** Mask for the GPD FAST ACTIVE1 */ +#define NRF_GPD_FAST_ACTIVE1_MSK 0x1U /** Position of the clockpin enable field. */ #define NRF_CLOCKPIN_ENABLE_POS 17U /** Mask for the clockpin enable field. */ diff --git a/soc/nordic/common/pinctrl_soc.h b/soc/nordic/common/pinctrl_soc.h index ea0f0196e2b..f1d3b6357f9 100644 --- a/soc/nordic/common/pinctrl_soc.h +++ b/soc/nordic/common/pinctrl_soc.h @@ -14,6 +14,7 @@ #include #include +#include #include #ifdef __cplusplus @@ -55,6 +56,16 @@ typedef uint32_t pinctrl_soc_pin_t; (), NRF_GET_FUN(DT_PROP_BY_IDX(node_id, prop, idx))) \ 0)), (0)) +/** + * @brief Utility macro to get the GPD_FAST_ACTIVE1 flag + * + * @param p_node_id Parent node identifier. + */ +#define Z_GET_GPD_FAST_ACTIVE1(p_node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(p_node_id, power_domains), \ + ((DT_PHA(p_node_id, power_domains, id) == \ + NRF_GPD_FAST_ACTIVE1) << NRF_GPD_FAST_ACTIVE1_POS), (0)) + /** * @brief Utility macro to initialize each pin. * @@ -70,7 +81,8 @@ typedef uint32_t pinctrl_soc_pin_t; (DT_PROP(node_id, nordic_drive_mode) << NRF_DRIVE_POS) | \ ((NRF_LP_ENABLE * DT_PROP(node_id, low_power_enable)) << NRF_LP_POS) |\ (DT_PROP(node_id, nordic_invert) << NRF_INVERT_POS) | \ - Z_GET_CLOCKPIN_ENABLE(node_id, prop, idx, p_node_id) \ + Z_GET_CLOCKPIN_ENABLE(node_id, prop, idx, p_node_id) | \ + Z_GET_GPD_FAST_ACTIVE1(p_node_id) \ ), /** @@ -99,6 +111,14 @@ typedef uint32_t pinctrl_soc_pin_t; #define NRF_GET_CLOCKPIN_ENABLE(pincfg) \ (((pincfg) >> NRF_CLOCKPIN_ENABLE_POS) & NRF_CLOCKPIN_ENABLE_MSK) +/** + * @brief Utility macro to obtain GPD_FAST_ACTIVE1 flag + * + * @param pincfg Pin configuration bit field. + */ +#define NRF_GET_GPD_FAST_ACTIVE1(pincfg) \ + (((pincfg) >> NRF_GPD_FAST_ACTIVE1_POS) & NRF_GPD_FAST_ACTIVE1_MSK) + /** * @brief Utility macro to obtain pin inversion flag. * From b0b698dd8291425bc134c48181c05d78334d04d1 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 10 Oct 2024 14:19:26 +0200 Subject: [PATCH 11/20] [nrf fromtree] soc: nordic: nrf54h: add SoC level API to request/release GPD Add a new soc-level API that allows to manually request/release global power domains. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 87a42a89cb60a0f725b6ef0e0d4e84dff5f461ba) --- soc/nordic/nrf54h/CMakeLists.txt | 2 + soc/nordic/nrf54h/Kconfig | 2 + soc/nordic/nrf54h/gpd/CMakeLists.txt | 5 + soc/nordic/nrf54h/gpd/Kconfig | 12 ++ soc/nordic/nrf54h/gpd/gpd.c | 276 ++++++++++++++++++++++++ soc/nordic/nrf54h/gpd/include/nrf/gpd.h | 33 +++ 6 files changed, 330 insertions(+) create mode 100644 soc/nordic/nrf54h/gpd/CMakeLists.txt create mode 100644 soc/nordic/nrf54h/gpd/Kconfig create mode 100644 soc/nordic/nrf54h/gpd/gpd.c create mode 100644 soc/nordic/nrf54h/gpd/include/nrf/gpd.h diff --git a/soc/nordic/nrf54h/CMakeLists.txt b/soc/nordic/nrf54h/CMakeLists.txt index 0496841ffe7..7edc4d43ea1 100644 --- a/soc/nordic/nrf54h/CMakeLists.txt +++ b/soc/nordic/nrf54h/CMakeLists.txt @@ -15,3 +15,5 @@ zephyr_include_directories(.) # Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes # for the image correctly zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) + +add_subdirectory(gpd) diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig index 9132ca8458b..1b667e25985 100644 --- a/soc/nordic/nrf54h/Kconfig +++ b/soc/nordic/nrf54h/Kconfig @@ -75,3 +75,5 @@ config SOC_NRF54H20_CPUFLPR config SOC_NRF54H20_ENGB_CPUFLPR depends on RISCV_CORE_NORDIC_VPR + +rsource "gpd/Kconfig" diff --git a/soc/nordic/nrf54h/gpd/CMakeLists.txt b/soc/nordic/nrf54h/gpd/CMakeLists.txt new file mode 100644 index 00000000000..7d029d2c8fc --- /dev/null +++ b/soc/nordic/nrf54h/gpd/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_SOC_NRF54H20_GPD gpd.c) +zephyr_include_directories(include) diff --git a/soc/nordic/nrf54h/gpd/Kconfig b/soc/nordic/nrf54h/gpd/Kconfig new file mode 100644 index 00000000000..b9bd568cda6 --- /dev/null +++ b/soc/nordic/nrf54h/gpd/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NRF54H20_GPD + bool "Global Power Domain service" + imply NRFS + imply NRFS_GDPWR_SERVICE_ENABLED + select ONOFF + default y if SOC_NRF54H20_CPUAPP || SOC_NRF54H20_ENGB_CPUAPP || \ + SOC_NRF54H20_CPURAD || SOC_NRF54H20_ENGB_CPURAD + help + This option enables the Global Power Domain service. diff --git a/soc/nordic/nrf54h/gpd/gpd.c b/soc/nordic/nrf54h/gpd/gpd.c new file mode 100644 index 00000000000..33cdb876e16 --- /dev/null +++ b/soc/nordic/nrf54h/gpd/gpd.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +LOG_MODULE_REGISTER(gpd, CONFIG_SOC_LOG_LEVEL); + +/* enforce alignment between DT<->nrfs */ +BUILD_ASSERT(GDPWR_POWER_DOMAIN_ACTIVE_FAST == NRF_GPD_FAST_ACTIVE1); +BUILD_ASSERT(GDPWR_POWER_DOMAIN_ACTIVE_SLOW == NRF_GPD_SLOW_ACTIVE); +BUILD_ASSERT(GDPWR_POWER_DOMAIN_MAIN_SLOW == NRF_GPD_SLOW_MAIN); + +struct gpd_onoff_manager { + struct onoff_manager mgr; + onoff_notify_fn notify; + uint8_t id; +}; + +static void start(struct onoff_manager *mgr, onoff_notify_fn notify); +static void stop(struct onoff_manager *mgr, onoff_notify_fn notify); + +#define GPD_READY_TIMEOUT_MS 1000 + +#define GPD_SERVICE_READY BIT(0) +#define GPD_SERVICE_ERROR BIT(1) +#define GPD_SERVICE_REQ_OK BIT(2) +#define GPD_SERVICE_REQ_ERR BIT(3) +static atomic_t gpd_service_status = ATOMIC_INIT(0); + +static struct gpd_onoff_manager fast_active1 = {.id = NRF_GPD_FAST_ACTIVE1}; +static struct gpd_onoff_manager slow_active = {.id = NRF_GPD_SLOW_ACTIVE}; +static struct gpd_onoff_manager slow_main = {.id = NRF_GPD_SLOW_MAIN}; + +static const struct onoff_transitions transitions = + ONOFF_TRANSITIONS_INITIALIZER(start, stop, NULL); + +static struct gpd_onoff_manager *get_mgr(uint8_t id) +{ + switch (id) { + case NRF_GPD_FAST_ACTIVE1: + return &fast_active1; + case NRF_GPD_SLOW_ACTIVE: + return &slow_active; + case NRF_GPD_SLOW_MAIN: + return &slow_main; + default: + return NULL; + } +} + +static int nrf_gpd_sync(struct gpd_onoff_manager *gpd_mgr) +{ + int64_t start; + nrfs_err_t err; + gdpwr_request_type_t request; + + K_SPINLOCK(&gpd_mgr->mgr.lock) { + if (gpd_mgr->mgr.refs == 0) { + request = GDPWR_POWER_REQUEST_CLEAR; + } else { + request = GDPWR_POWER_REQUEST_SET; + } + } + + atomic_clear_bit(&gpd_service_status, GPD_SERVICE_REQ_ERR); + atomic_clear_bit(&gpd_service_status, GPD_SERVICE_REQ_OK); + + err = nrfs_gdpwr_power_request(gpd_mgr->id, request, gpd_mgr); + if (err != NRFS_SUCCESS) { + return -EIO; + } + + start = k_uptime_get(); + while (k_uptime_get() - start < GPD_READY_TIMEOUT_MS) { + if (atomic_test_bit(&gpd_service_status, GPD_SERVICE_REQ_ERR)) { + return -EIO; + } + + if (atomic_test_bit(&gpd_service_status, GPD_SERVICE_REQ_OK)) { + return 0; + } + } + + LOG_ERR("nRFs GDPWR request timed out"); + + return -ETIMEDOUT; +} + +static void evt_handler(nrfs_gdpwr_evt_t const *p_evt, void *context) +{ + if (atomic_test_bit(&gpd_service_status, GPD_SERVICE_READY)) { + struct gpd_onoff_manager *gpd_mgr = context; + + switch (p_evt->type) { + case NRFS_GDPWR_REQ_APPLIED: + gpd_mgr->notify(&gpd_mgr->mgr, 0); + break; + default: + LOG_ERR("nRFs GDPWR request not applied"); + gpd_mgr->notify(&gpd_mgr->mgr, -EIO); + break; + } + } else { + switch (p_evt->type) { + case NRFS_GDPWR_REQ_APPLIED: + atomic_set_bit(&gpd_service_status, GPD_SERVICE_REQ_OK); + break; + default: + LOG_ERR("nRFs GDPWR request not applied"); + atomic_set_bit(&gpd_service_status, GPD_SERVICE_REQ_ERR); + break; + } + } +} + +static void start(struct onoff_manager *mgr, onoff_notify_fn notify) +{ + struct gpd_onoff_manager *gpd_mgr = CONTAINER_OF(mgr, struct gpd_onoff_manager, mgr); + + gpd_mgr->notify = notify; + + if (!atomic_test_bit(&gpd_service_status, GPD_SERVICE_READY)) { + notify(mgr, 0); + } else { + nrfs_err_t err; + + err = nrfs_gdpwr_power_request(gpd_mgr->id, GDPWR_POWER_REQUEST_SET, gpd_mgr); + if (err != NRFS_SUCCESS) { + LOG_ERR("nRFs GDPWR request failed (%d)", err); + notify(mgr, -EIO); + } + } +} + +static void stop(struct onoff_manager *mgr, onoff_notify_fn notify) +{ + struct gpd_onoff_manager *gpd_mgr = CONTAINER_OF(mgr, struct gpd_onoff_manager, mgr); + + gpd_mgr->notify = notify; + + if (!atomic_test_bit(&gpd_service_status, GPD_SERVICE_READY)) { + notify(mgr, 0); + } else { + nrfs_err_t err; + + err = nrfs_gdpwr_power_request(gpd_mgr->id, GDPWR_POWER_REQUEST_CLEAR, gpd_mgr); + if (err != NRFS_SUCCESS) { + LOG_ERR("nRFs GDPWR request failed (%d)", err); + notify(mgr, -EIO); + } + } +} + +int nrf_gpd_request(uint8_t id) +{ + int ret; + struct onoff_client client; + struct gpd_onoff_manager *gpd_mgr; + + gpd_mgr = get_mgr(id); + if (gpd_mgr == NULL) { + return -EINVAL; + } + + if (atomic_test_bit(&gpd_service_status, GPD_SERVICE_ERROR)) { + LOG_ERR("GPD service did not initialize properly"); + return -EIO; + } + + sys_notify_init_spinwait(&client.notify); + + onoff_request(&gpd_mgr->mgr, &client); + + while (sys_notify_fetch_result(&client.notify, &ret) == -EAGAIN) { + } + + return ret; +} + +int nrf_gpd_release(uint8_t id) +{ + struct gpd_onoff_manager *gpd_mgr; + + gpd_mgr = get_mgr(id); + if (gpd_mgr == NULL) { + return -EINVAL; + } + + if (atomic_test_bit(&gpd_service_status, GPD_SERVICE_ERROR)) { + LOG_ERR("GPD service did not initialize properly"); + return -EIO; + } + + return onoff_release(&gpd_mgr->mgr); +} + +static int nrf_gpd_pre_init(void) +{ + int ret; + + ret = onoff_manager_init(&fast_active1.mgr, &transitions); + if (ret < 0) { + return ret; + } + + ret = onoff_manager_init(&slow_active.mgr, &transitions); + if (ret < 0) { + return ret; + } + + ret = onoff_manager_init(&slow_main.mgr, &transitions); + if (ret < 0) { + return ret; + } + + return 0; +} + +static int nrf_gpd_post_init(void) +{ + nrfs_err_t err; + int ret; + + err = nrfs_backend_wait_for_connection(K_FOREVER); + if (err != NRFS_SUCCESS) { + ret = -EIO; + goto err; + } + + err = nrfs_gdpwr_init(evt_handler); + if (err != NRFS_SUCCESS) { + ret = -EIO; + goto err; + } + + /* submit GD requests now to align collected statuses */ + ret = nrf_gpd_sync(&fast_active1); + if (ret < 0) { + goto err; + } + + ret = nrf_gpd_sync(&slow_active); + if (ret < 0) { + goto err; + } + + ret = nrf_gpd_sync(&slow_main); + if (ret < 0) { + goto err; + } + + atomic_set_bit(&gpd_service_status, GPD_SERVICE_READY); + + return 0; + +err: + atomic_set_bit(&gpd_service_status, GPD_SERVICE_ERROR); + + return ret; +} + +SYS_INIT(nrf_gpd_pre_init, PRE_KERNEL_1, 0); +SYS_INIT(nrf_gpd_post_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY); diff --git a/soc/nordic/nrf54h/gpd/include/nrf/gpd.h b/soc/nordic/nrf54h/gpd/include/nrf/gpd.h new file mode 100644 index 00000000000..0504f94e858 --- /dev/null +++ b/soc/nordic/nrf54h/gpd/include/nrf/gpd.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_NORDIC_NRF54H_GPD_INCLUDE_NRF_GPD_H_ +#define ZEPHYR_SOC_NORDIC_NRF54H_GPD_INCLUDE_NRF_GPD_H_ + +#include + +#include + +/** + * @brief Request a global power domain. + * + * @param id Domain ID. + * + * @retval 0 If the request was successful. + * @retval -errno If the request was not successful. + */ +int nrf_gpd_request(uint8_t id); + +/** + * @brief Release a global power domain. + * + * @param id Domain ID. + * + * @retval 0 If the request was successful. + * @retval -errno If the request was not successful. + */ +int nrf_gpd_release(uint8_t id); + +#endif /* ZEPHYR_SOC_NORDIC_NRF54H_GPD_INCLUDE_NRF_GPD_H_ */ From 2c862e8963ad207ac7e8ae125ee654c40c067453 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 30 Oct 2024 11:20:41 +0100 Subject: [PATCH 12/20] [nrf fromtree] modules: hal_nordic: bump regtool to 8.0.0 It is required for some pinctrl changes. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 0b18f31246cd5d0bcdd10a3ad6e3bd108bf3f95d) --- modules/hal_nordic/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hal_nordic/CMakeLists.txt b/modules/hal_nordic/CMakeLists.txt index 3bed5a033b5..4e3f388b266 100644 --- a/modules/hal_nordic/CMakeLists.txt +++ b/modules/hal_nordic/CMakeLists.txt @@ -15,7 +15,7 @@ if(CONFIG_NRF_REGTOOL_GENERATE_BICR) list(APPEND nrf_regtool_components GENERATE:BICR) endif() if(DEFINED nrf_regtool_components) - find_package(nrf-regtool 7.0.0 REQUIRED + find_package(nrf-regtool 8.0.0 COMPONENTS ${nrf_regtool_components} PATHS ${CMAKE_CURRENT_LIST_DIR}/nrf-regtool NO_CMAKE_PATH From c85b86db9cfcbff6ab00575ed16a7b638039f1a7 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Thu, 10 Oct 2024 15:58:41 +0200 Subject: [PATCH 13/20] [nrf fromtree] drivers: gpio: nrfx: add support for ports with pad on FAST_ACTIVE1 This patch allows to _safely_ configure GPIO ports that have their pad on FAST_ACTIVE1 domain. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 56c5b1e2da11318844f6bb19414efac32e77613d) --- drivers/gpio/gpio_nrfx.c | 116 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 108 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio_nrfx.c b/drivers/gpio/gpio_nrfx.c index 151cf1a830c..d9eb9129937 100644 --- a/drivers/gpio/gpio_nrfx.c +++ b/drivers/gpio/gpio_nrfx.c @@ -14,6 +14,10 @@ #include +#ifdef CONFIG_SOC_NRF54H20_GPD +#include +#endif + struct gpio_nrfx_data { /* gpio_driver_data needs to be first */ struct gpio_driver_data common; @@ -27,6 +31,9 @@ struct gpio_nrfx_cfg { uint32_t edge_sense; uint8_t port_num; nrfx_gpiote_t gpiote; +#ifdef CONFIG_SOC_NRF54H20_GPD + uint8_t pad_pd; +#endif }; static inline struct gpio_nrfx_data *get_port_data(const struct device *port) @@ -55,9 +62,59 @@ static nrf_gpio_pin_pull_t get_pull(gpio_flags_t flags) return NRF_GPIO_PIN_NOPULL; } +static int gpio_nrfx_gpd_retain_set(const struct device *port, uint32_t mask, gpio_flags_t flags) +{ +#ifdef CONFIG_SOC_NRF54H20_GPD + const struct gpio_nrfx_cfg *cfg = get_port_cfg(port); + + if (cfg->pad_pd == NRF_GPD_FAST_ACTIVE1) { + int ret; + + if (flags & GPIO_OUTPUT) { + cfg->port->RETAINSET = mask; + } + + ret = nrf_gpd_release(NRF_GPD_FAST_ACTIVE1); + if (ret < 0) { + return ret; + } + } +#else + ARG_UNUSED(port); + ARG_UNUSED(mask); + ARG_UNUSED(flags); +#endif + + return 0; +} + +static int gpio_nrfx_gpd_retain_clear(const struct device *port, uint32_t mask) +{ +#ifdef CONFIG_SOC_NRF54H20_GPD + const struct gpio_nrfx_cfg *cfg = get_port_cfg(port); + + if (cfg->pad_pd == NRF_GPD_FAST_ACTIVE1) { + int ret; + + ret = nrf_gpd_request(NRF_GPD_FAST_ACTIVE1); + if (ret < 0) { + return ret; + } + + cfg->port->RETAINCLR = mask; + } +#else + ARG_UNUSED(port); + ARG_UNUSED(mask); +#endif + + return 0; +} + static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags) { + int ret = 0; nrfx_err_t err = NRFX_SUCCESS; uint8_t ch; bool free_ch = false; @@ -95,6 +152,11 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, return -EINVAL; } + ret = gpio_nrfx_gpd_retain_clear(port, BIT(pin)); + if (ret < 0) { + return ret; + } + if (flags & GPIO_OUTPUT_INIT_HIGH) { nrf_gpio_port_out_set(cfg->port, BIT(pin)); } else if (flags & GPIO_OUTPUT_INIT_LOW) { @@ -110,7 +172,8 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, : NRF_GPIO_PIN_INPUT_DISCONNECT; nrf_gpio_reconfigure(abs_pin, &dir, &input, &pull, &drive, NULL); - return 0; + + goto end; } /* Get the GPIOTE channel associated with this pin, if any. It needs @@ -137,7 +200,8 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, err = nrfx_gpiote_input_configure(&cfg->gpiote, abs_pin, &input_pin_config); if (err != NRFX_SUCCESS) { - return -EINVAL; + ret = -EINVAL; + goto end; } } @@ -162,7 +226,8 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, } if (err != NRFX_SUCCESS) { - return -EINVAL; + ret = -EINVAL; + goto end; } } @@ -171,7 +236,9 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, __ASSERT_NO_MSG(err == NRFX_SUCCESS); } - return 0; +end: + (void)gpio_nrfx_gpd_retain_set(port, BIT(pin), flags); + return ret; } static int gpio_nrfx_port_get_raw(const struct device *port, @@ -189,34 +256,52 @@ static int gpio_nrfx_port_set_masked_raw(const struct device *port, gpio_port_value_t value) { NRF_GPIO_Type *reg = get_port_cfg(port)->port; + int ret; const uint32_t set_mask = value & mask; const uint32_t clear_mask = (~set_mask) & mask; + ret = gpio_nrfx_gpd_retain_clear(port, mask); + if (ret < 0) { + return ret; + } + nrf_gpio_port_out_set(reg, set_mask); nrf_gpio_port_out_clear(reg, clear_mask); - return 0; + return gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); } static int gpio_nrfx_port_set_bits_raw(const struct device *port, gpio_port_pins_t mask) { NRF_GPIO_Type *reg = get_port_cfg(port)->port; + int ret; + + ret = gpio_nrfx_gpd_retain_clear(port, mask); + if (ret < 0) { + return ret; + } nrf_gpio_port_out_set(reg, mask); - return 0; + return gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); } static int gpio_nrfx_port_clear_bits_raw(const struct device *port, gpio_port_pins_t mask) { NRF_GPIO_Type *reg = get_port_cfg(port)->port; + int ret; + + ret = gpio_nrfx_gpd_retain_clear(port, mask); + if (ret < 0) { + return ret; + } nrf_gpio_port_out_clear(reg, mask); - return 0; + return gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); } static int gpio_nrfx_port_toggle_bits(const struct device *port, @@ -226,11 +311,17 @@ static int gpio_nrfx_port_toggle_bits(const struct device *port, const uint32_t value = nrf_gpio_port_out_read(reg) ^ mask; const uint32_t set_mask = value & mask; const uint32_t clear_mask = (~value) & mask; + int ret; + + ret = gpio_nrfx_gpd_retain_clear(port, mask); + if (ret < 0) { + return ret; + } nrf_gpio_port_out_set(reg, set_mask); nrf_gpio_port_out_clear(reg, clear_mask); - return 0; + return gpio_nrfx_gpd_retain_set(port, mask, GPIO_OUTPUT); } #ifdef CONFIG_GPIO_NRFX_INTERRUPT @@ -450,6 +541,14 @@ static const struct gpio_driver_api gpio_nrfx_drv_api_funcs = { "Please enable GPIOTE instance for used GPIO port!")), \ ()) +#ifdef CONFIG_SOC_NRF54H20_GPD +#define PAD_PD(inst) \ + .pad_pd = DT_INST_PHA_BY_NAME_OR(inst, power_domains, pad, id, \ + NRF_GPD_SLOW_MAIN), +#else +#define PAD_PD(inst) +#endif + #define GPIO_NRF_DEVICE(id) \ GPIOTE_CHECK(id); \ static const struct gpio_nrfx_cfg gpio_nrfx_p##id##_cfg = { \ @@ -461,6 +560,7 @@ static const struct gpio_driver_api gpio_nrfx_drv_api_funcs = { .port_num = DT_INST_PROP(id, port), \ .edge_sense = DT_INST_PROP_OR(id, sense_edge_mask, 0), \ .gpiote = GPIOTE_INSTANCE(id), \ + PAD_PD(id) \ }; \ \ static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \ From 777576bd5a1e183320237e276b39cd4d51720218 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 30 Oct 2024 11:42:28 +0100 Subject: [PATCH 14/20] [nrf fromtree] scripts: checkpatch: add NRF_GPIO_Type to typedefs file So that we do not get false warnings about consistent spacing around '*'. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 5e8905bb9483b33b4412e7c0a30e0e4dfa7f80b3) --- scripts/checkpatch/typedefsfile | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/checkpatch/typedefsfile b/scripts/checkpatch/typedefsfile index 62febe44e1b..0fc22b9779b 100644 --- a/scripts/checkpatch/typedefsfile +++ b/scripts/checkpatch/typedefsfile @@ -8,3 +8,4 @@ io_rw_32 \b[a-zA-Z_][a-zA-Z0-9_]*TypeDef Pwm FILE +NRF_GPIO_Type From 7fee7794da102328449571e2c7e99a4debc008d5 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 29 Oct 2024 10:25:25 +0100 Subject: [PATCH 15/20] [nrf fromtree] soc: nordic: nrf54h: gpd: add API to set/clear pin retention This API needs to be called by FAST peripherals before/after disabling/enabling them. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 77fc18327aa965625c60c958b5303cb14e456c00) --- soc/nordic/nrf54h/gpd/gpd.c | 29 +++++++++++++++++++++++++ soc/nordic/nrf54h/gpd/include/nrf/gpd.h | 12 ++++++++++ 2 files changed, 41 insertions(+) diff --git a/soc/nordic/nrf54h/gpd/gpd.c b/soc/nordic/nrf54h/gpd/gpd.c index 33cdb876e16..ea439a54460 100644 --- a/soc/nordic/nrf54h/gpd/gpd.c +++ b/soc/nordic/nrf54h/gpd/gpd.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -207,6 +208,34 @@ int nrf_gpd_release(uint8_t id) return onoff_release(&gpd_mgr->mgr); } +int nrf_gpd_retain_pins_set(const struct pinctrl_dev_config *pcfg, bool retain) +{ + const struct pinctrl_state *state; + int ret; + + ret = pinctrl_lookup_state(pcfg, PINCTRL_STATE_DEFAULT, &state); + if (ret < 0) { + return ret; + } + + for (uint8_t i = 0U; i < state->pin_cnt; i++) { + uint32_t pin = NRF_GET_PIN(state->pins[i]); + NRF_GPIO_Type *reg = nrf_gpio_pin_port_decode(&pin); + + if (pin == NRF_PIN_DISCONNECTED) { + continue; + } + + if (retain) { + reg->RETAINSET = BIT(pin); + } else { + reg->RETAINCLR = BIT(pin); + } + } + + return 0; +} + static int nrf_gpd_pre_init(void) { int ret; diff --git a/soc/nordic/nrf54h/gpd/include/nrf/gpd.h b/soc/nordic/nrf54h/gpd/include/nrf/gpd.h index 0504f94e858..b8aab94accb 100644 --- a/soc/nordic/nrf54h/gpd/include/nrf/gpd.h +++ b/soc/nordic/nrf54h/gpd/include/nrf/gpd.h @@ -9,6 +9,7 @@ #include #include +#include /** * @brief Request a global power domain. @@ -30,4 +31,15 @@ int nrf_gpd_request(uint8_t id); */ int nrf_gpd_release(uint8_t id); +/** + * @brief Retain set/clear a set of pins. + * + * @param pcfg Device pin configuration. + * @param retain Retain or not. + * + * @retval 0 If the request was successful. + * @retval -errno If the request was not successful. + */ +int nrf_gpd_retain_pins_set(const struct pinctrl_dev_config *pcfg, bool retain); + #endif /* ZEPHYR_SOC_NORDIC_NRF54H_GPD_INCLUDE_NRF_GPD_H_ */ From 9583f335d71f752dbb9a421a63bd8d49d1d58779 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 29 Oct 2024 10:26:39 +0100 Subject: [PATCH 16/20] [nrf fromtree] drivers: serial: nrfx_uarte: set/clear pins retention When GPD is managed by pinctrl, pins retention needs to be controlled by the driver to avoid glitches. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit b6d45423c60b950d02c389262745c2fdcd27b4f0) --- drivers/serial/uart_nrfx_uarte.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/serial/uart_nrfx_uarte.c b/drivers/serial/uart_nrfx_uarte.c index 2fb2ab3537e..452307acaa8 100644 --- a/drivers/serial/uart_nrfx_uarte.c +++ b/drivers/serial/uart_nrfx_uarte.c @@ -23,6 +23,11 @@ #include #include #include + +#ifdef CONFIG_SOC_NRF54H20_GPD +#include +#endif + LOG_MODULE_REGISTER(uart_nrfx_uarte, CONFIG_UART_LOG_LEVEL); #if !defined(CONFIG_ARCH_POSIX) @@ -2098,6 +2103,9 @@ static void uarte_pm_resume(const struct device *dev) if (IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME) || !LOW_POWER_ENABLED(cfg)) { uarte_periph_enable(dev); +#ifdef CONFIG_SOC_NRF54H20_GPD + nrf_gpd_retain_pins_set(cfg->pcfg, false); +#endif } } @@ -2160,6 +2168,10 @@ static void uarte_pm_suspend(const struct device *dev) wait_for_tx_stopped(dev); } +#ifdef CONFIG_SOC_NRF54H20_GPD + nrf_gpd_retain_pins_set(cfg->pcfg, true); +#endif + nrf_uarte_disable(uarte); (void)pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP); From 1839fec3e353cd7ec0d284e47b613b036cdb3963 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 29 Oct 2024 15:17:27 +0100 Subject: [PATCH 17/20] [nrf fromtree] soc: nordic: nrf54h: disable PM_DEVICE_POWER_DOMAIN It is enabled by default if we enable device PM, but we do not want this, otherwise we get linker errors (PM subsys, fun guaranteed!). Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 969326bfff2d90dfc1481fecb636d39a66a9581e) --- soc/nordic/nrf54h/Kconfig.defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/soc/nordic/nrf54h/Kconfig.defconfig b/soc/nordic/nrf54h/Kconfig.defconfig index b09b24e5e70..65023fc18ca 100644 --- a/soc/nordic/nrf54h/Kconfig.defconfig +++ b/soc/nordic/nrf54h/Kconfig.defconfig @@ -39,4 +39,7 @@ config SPI_DW_HSSI config SPI_DW_ACCESS_WORD_ONLY default y if SPI_DW +config PM_DEVICE_POWER_DOMAIN + default n if PM_DEVICE + endif # SOC_SERIES_NRF54HX From e0e211d828af31140d50c325f737097d27ac4cb2 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 30 Oct 2024 16:37:13 +0100 Subject: [PATCH 18/20] [nrf noup] moduled: hal_nordic: require nrf-regtool Upstream not ready yet, revert once applied there. Signed-off-by: Gerard Marull-Paretas --- modules/hal_nordic/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/hal_nordic/CMakeLists.txt b/modules/hal_nordic/CMakeLists.txt index 4e3f388b266..0dd750d457e 100644 --- a/modules/hal_nordic/CMakeLists.txt +++ b/modules/hal_nordic/CMakeLists.txt @@ -15,7 +15,7 @@ if(CONFIG_NRF_REGTOOL_GENERATE_BICR) list(APPEND nrf_regtool_components GENERATE:BICR) endif() if(DEFINED nrf_regtool_components) - find_package(nrf-regtool 8.0.0 + find_package(nrf-regtool 8.0.0 REQUIRED COMPONENTS ${nrf_regtool_components} PATHS ${CMAKE_CURRENT_LIST_DIR}/nrf-regtool NO_CMAKE_PATH From 7037a6f18b83d9ce8af48deb1012658afca8d820 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 4 Nov 2024 10:14:36 +0100 Subject: [PATCH 19/20] [nrf fromlist] soc: nrf54h: gpd: use callback to fetch nrfs async result Busy-waiting for the result of the nrfs service calls can stall, so let's use a callback that flags a semaphore instead. Since the API is supposed to be callable in the context of pre-kernel, fallback to busy-wait on that scenario. Upstream PR #: 80819 Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 714d82d232977309e0bdc8dadd2d7a71ee914a4b) --- soc/nordic/nrf54h/gpd/gpd.c | 55 +++++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 6 deletions(-) diff --git a/soc/nordic/nrf54h/gpd/gpd.c b/soc/nordic/nrf54h/gpd/gpd.c index ea439a54460..994b2c02b96 100644 --- a/soc/nordic/nrf54h/gpd/gpd.c +++ b/soc/nordic/nrf54h/gpd/gpd.c @@ -28,6 +28,9 @@ struct gpd_onoff_manager { struct onoff_manager mgr; onoff_notify_fn notify; uint8_t id; + struct k_mutex lock; + struct k_sem sem; + int res; }; static void start(struct onoff_manager *mgr, onoff_notify_fn notify); @@ -41,9 +44,21 @@ static void stop(struct onoff_manager *mgr, onoff_notify_fn notify); #define GPD_SERVICE_REQ_ERR BIT(3) static atomic_t gpd_service_status = ATOMIC_INIT(0); -static struct gpd_onoff_manager fast_active1 = {.id = NRF_GPD_FAST_ACTIVE1}; -static struct gpd_onoff_manager slow_active = {.id = NRF_GPD_SLOW_ACTIVE}; -static struct gpd_onoff_manager slow_main = {.id = NRF_GPD_SLOW_MAIN}; +static struct gpd_onoff_manager fast_active1 = { + .id = NRF_GPD_FAST_ACTIVE1, + .lock = Z_MUTEX_INITIALIZER(fast_active1.lock), + .sem = Z_SEM_INITIALIZER(fast_active1.sem, 0, 1), +}; +static struct gpd_onoff_manager slow_active = { + .id = NRF_GPD_SLOW_ACTIVE, + .lock = Z_MUTEX_INITIALIZER(slow_active.lock), + .sem = Z_SEM_INITIALIZER(slow_active.sem, 0, 1), +}; +static struct gpd_onoff_manager slow_main = { + .id = NRF_GPD_SLOW_MAIN, + .lock = Z_MUTEX_INITIALIZER(slow_main.lock), + .sem = Z_SEM_INITIALIZER(slow_main.sem, 0, 1), +}; static const struct onoff_transitions transitions = ONOFF_TRANSITIONS_INITIALIZER(start, stop, NULL); @@ -62,6 +77,18 @@ static struct gpd_onoff_manager *get_mgr(uint8_t id) } } +static void request_cb(struct onoff_manager *mgr_, struct onoff_client *cli, uint32_t state, + int res) +{ + ARG_UNUSED(cli); + ARG_UNUSED(state); + + struct gpd_onoff_manager *gpd_mgr = CONTAINER_OF(mgr_, struct gpd_onoff_manager, mgr); + + gpd_mgr->res = res; + k_sem_give(&gpd_mgr->sem); +} + static int nrf_gpd_sync(struct gpd_onoff_manager *gpd_mgr) { int64_t start; @@ -181,11 +208,27 @@ int nrf_gpd_request(uint8_t id) return -EIO; } - sys_notify_init_spinwait(&client.notify); + if (k_is_pre_kernel()) { + sys_notify_init_spinwait(&client.notify); + + ret = onoff_request(&gpd_mgr->mgr, &client); + if (ret < 0) { + return ret; + } - onoff_request(&gpd_mgr->mgr, &client); + while (sys_notify_fetch_result(&client.notify, &ret) == -EAGAIN) { + } + } else { + sys_notify_init_callback(&client.notify, request_cb); + k_mutex_lock(&gpd_mgr->lock, K_FOREVER); + + ret = onoff_request(&gpd_mgr->mgr, &client); + if (ret >= 0) { + (void)k_sem_take(&gpd_mgr->sem, K_FOREVER); + ret = gpd_mgr->res; + } - while (sys_notify_fetch_result(&client.notify, &ret) == -EAGAIN) { + k_mutex_unlock(&gpd_mgr->lock); } return ret; From 14fbad3a010e0092701893c8c014a6a72eaee7fd Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 5 Nov 2024 12:53:36 +0100 Subject: [PATCH 20/20] [nrf fromtree] soc: nordic: nrf54h: gpd: fix compile warning when CONFIG_DEBUG=y Usage of K_SPINLOCK with CONFIG_DEBUG=y seems to trigger a compiler warning about request not always being initialized. Fallback to k_spin_lock/unlock calls to fix this issue. Signed-off-by: Gerard Marull-Paretas (cherry picked from commit 5249619f6a19a3265852ae8a7ceba1b703be4c58) --- soc/nordic/nrf54h/gpd/gpd.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/soc/nordic/nrf54h/gpd/gpd.c b/soc/nordic/nrf54h/gpd/gpd.c index 994b2c02b96..a4d1889e53f 100644 --- a/soc/nordic/nrf54h/gpd/gpd.c +++ b/soc/nordic/nrf54h/gpd/gpd.c @@ -93,16 +93,19 @@ static int nrf_gpd_sync(struct gpd_onoff_manager *gpd_mgr) { int64_t start; nrfs_err_t err; + k_spinlock_key_t key; gdpwr_request_type_t request; - K_SPINLOCK(&gpd_mgr->mgr.lock) { - if (gpd_mgr->mgr.refs == 0) { - request = GDPWR_POWER_REQUEST_CLEAR; - } else { - request = GDPWR_POWER_REQUEST_SET; - } + key = k_spin_lock(&gpd_mgr->mgr.lock); + + if (gpd_mgr->mgr.refs == 0) { + request = GDPWR_POWER_REQUEST_CLEAR; + } else { + request = GDPWR_POWER_REQUEST_SET; } + k_spin_unlock(&gpd_mgr->mgr.lock, key); + atomic_clear_bit(&gpd_service_status, GPD_SERVICE_REQ_ERR); atomic_clear_bit(&gpd_service_status, GPD_SERVICE_REQ_OK);