diff --git a/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk b/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk index 09809ff7374..3ac84ee1ea3 100644 --- a/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk +++ b/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk @@ -3,3 +3,4 @@ config BOARD_NRF54L20PDK select SOC_NRF54L20_ENGA_CPUAPP if BOARD_NRF54L20PDK_NRF54L20_CPUAPP + select SOC_NRF54L20_ENGA_CPUFLPR if BOARD_NRF54L20PDK_NRF54L20_CPUFLPR diff --git a/boards/nordic/nrf54l20pdk/board.cmake b/boards/nordic/nrf54l20pdk/board.cmake index 5d36ac00a3e..3bb4e520198 100644 --- a/boards/nordic/nrf54l20pdk/board.cmake +++ b/boards/nordic/nrf54l20pdk/board.cmake @@ -1,7 +1,11 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=cortex-m33" "--speed=4000") +if(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUAPP) + board_runner_args(jlink "--device=cortex-m33" "--speed=4000") +elseif(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUFLPR) + board_runner_args(jlink "--speed=4000") +endif() include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l20pdk/board.yml b/boards/nordic/nrf54l20pdk/board.yml index 4eaa66669fc..de39dcb4a3f 100644 --- a/boards/nordic/nrf54l20pdk/board.yml +++ b/boards/nordic/nrf54l20pdk/board.yml @@ -4,3 +4,6 @@ board: vendor: nordic socs: - name: nrf54l20 + variants: + - name: xip + cpucluster: cpuflpr diff --git a/boards/nordic/nrf54l20pdk/doc/index.rst b/boards/nordic/nrf54l20pdk/doc/index.rst index aaed616ecce..7805d2ea9f9 100644 --- a/boards/nordic/nrf54l20pdk/doc/index.rst +++ b/boards/nordic/nrf54l20pdk/doc/index.rst @@ -65,6 +65,12 @@ built, flashed, and debugged in the usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on building and running. +Applications for the ``nrf54l20pdk/nrf54l20/cpuflpr`` board target need +to be built using sysbuild to include the ``vpr_launcher`` image for the application core. + +Enter the following command to compile ``hello_world`` for the FLPR core:: + west build -p -b nrf54l20pdk/nrf54l20/cpuflpr --sysbuild + Flashing ======== diff --git a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi index ec6f2740648..ed9d76a6b19 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi @@ -27,11 +27,6 @@ status = "okay"; }; -&hfpll { - /* For now use 64 MHz clock for CPU and fast peripherals. */ - clock-frequency = ; -}; - &lfxo { load-capacitors = "internal"; load-capacitance-femtofarad = <15500>; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi index 35a434cda4b..6eb67fe1bb3 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi @@ -91,3 +91,15 @@ pinctrl-1 = <&pwm20_sleep>; pinctrl-names = "default", "sleep"; }; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&hfpll { + /* For now use 64 MHz clock for CPU and fast peripherals. */ + clock-frequency = ; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi index 7dc2b77ae83..b70be2bfa5e 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi @@ -34,4 +34,27 @@ low-power-enable; }; }; + + /omit-if-no-ref/ uart30_default: uart30_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart30_sleep: uart30_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; }; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts new file mode 100644 index 00000000000..ea3c5d6ff6a --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf54l20pdk_nrf54l20-common.dtsi" + +/ { + model = "Nordic nRF54L20 PDK nRF54L20 FLPR MCU"; + compatible = "nordic,nrf54l20pdk_nrf54l20-cpuflpr"; + + chosen { + zephyr,console = &uart30; + zephyr,shell-uart = &uart30; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_rram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&cpuflpr_sram { + status = "okay"; +}; + +&cpuflpr_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(64)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&uart30 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml new file mode 100644 index 00000000000..8a9524bfbe4 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l20pdk/nrf54l20/cpuflpr +name: nRF54L20-PDK-nRF54L20-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 64 +flash: 64 +supported: + - counter + - gpio diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig new file mode 100644 index 00000000000..75f7c4386e3 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n + +CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL=y diff --git a/dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi index 1444be3b57b..5c7e5db3001 100644 --- a/dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi @@ -10,6 +10,11 @@ cpu: &cpuapp {}; systick: &cpuapp_systick {}; nvic: &cpuapp_nvic {}; +/delete-node/ &cpuflpr; +/delete-node/ &cpuflpr_rram; +/delete-node/ &cpuflpr_sram; +/delete-node/ &cpuflpr_clic; + / { chosen { zephyr,entropy = &prng; @@ -32,6 +37,27 @@ nvic: &cpuapp_nvic {}; }; }; +&cpuflpr_vpr { + cpuapp_vevif_rx: mailbox@1 { + compatible = "nordic,nrf-vevif-event-rx"; + reg = <0x0 0x1000>; + status = "disabled"; + interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>; + #mbox-cells = <1>; + nordic,events = <1>; + nordic,events-mask = <0x00100000>; + }; + + cpuapp_vevif_tx: mailbox@0 { + compatible = "nordic,nrf-vevif-task-tx"; + reg = <0x0 0x1000>; + #mbox-cells = <1>; + nordic,tasks = <7>; + nordic,tasks-mask = <0x007f0000>; + status = "disabled"; + }; +}; + &cpuapp_ppb { compatible = "simple-bus"; ranges; diff --git a/dts/common/nordic/nrf54l20.dtsi b/dts/common/nordic/nrf54l20.dtsi index 5e3ba49e7cf..d95ea80da26 100644 --- a/dts/common/nordic/nrf54l20.dtsi +++ b/dts/common/nordic/nrf54l20.dtsi @@ -11,6 +11,10 @@ /delete-node/ &sw_pwm; +/* Domain IDs. Can be used to specify channel links in IPCT nodes. */ +#define NRF_DOMAIN_ID_APPLICATION 0 +#define NRF_DOMAIN_ID_FLPR 1 + / { #address-cells = <1>; #size-cells = <1>; @@ -32,6 +36,14 @@ swo-ref-frequency = ; }; }; + + cpuflpr: cpu@1 { + compatible = "nordic,vpr"; + reg = <1>; + device_type = "cpu"; + riscv,isa = "rv32emc"; + nordic,bus-width = <64>; + }; }; clocks { @@ -77,10 +89,18 @@ cpuapp_sram: memory@20000000 { compatible = "mmio-sram"; - reg = <0x20000000 DT_SIZE_K(511)>; + reg = <0x20000000 DT_SIZE_K(447)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000000 0x6fc00>; + }; + + cpuflpr_sram: memory@2006fc00 { + compatible = "mmio-sram"; + reg = <0x2006fc00 DT_SIZE_K(64)>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x20000000 0x7fc00>; + ranges = <0x0 0x2006fc00 0x10000>; }; global_peripherals: peripheral@50000000 { @@ -106,6 +126,24 @@ status = "disabled"; }; + cpuflpr_vpr: vpr@4c000 { + compatible = "nordic,nrf-vpr-coprocessor"; + reg = <0x4c000 0x1000>; + ranges = <0x0 0x4c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + cpuflpr_clic: interrupt-controller@f0000000 { + compatible = "nordic,nrf-clic"; + reg = <0xf0000000 0x143c>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + status = "disabled"; + }; + }; + spi00: spi@4d000 { /* * This spi node can be either SPIM or SPIS, @@ -737,7 +775,14 @@ cpuapp_rram: rram@0 { compatible = "soc-nv-flash"; - reg = <0x0 DT_SIZE_K(2028)>; + reg = <0x0 DT_SIZE_K(1972)>; + erase-block-size = <4096>; + write-block-size = <16>; + }; + + cpuflpr_rram: rram@1ed000 { + compatible = "soc-nv-flash"; + reg = <0x1ed000 DT_SIZE_K(64)>; erase-block-size = <4096>; write-block-size = <16>; }; diff --git a/dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi b/dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi new file mode 100644 index 00000000000..4bd1a179fbc --- /dev/null +++ b/dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpuflpr {}; +clic: &cpuflpr_clic {}; + +/delete-node/ &cpuapp; +/delete-node/ &cpuapp_rram; +/delete-node/ &cpuapp_ppb; +/delete-node/ &cpuapp_sram; + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuflpr_clic>; + ranges; + }; +}; + +&cpuflpr { + cpuflpr_vevif_rx: mailbox { + compatible = "nordic,nrf-vevif-task-rx"; + status = "disabled"; + interrupt-parent = <&cpuflpr_clic>; + interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>, + <17 NRF_DEFAULT_IRQ_PRIORITY>, + <18 NRF_DEFAULT_IRQ_PRIORITY>, + <19 NRF_DEFAULT_IRQ_PRIORITY>, + <20 NRF_DEFAULT_IRQ_PRIORITY>, + <21 NRF_DEFAULT_IRQ_PRIORITY>, + <22 NRF_DEFAULT_IRQ_PRIORITY>; + #mbox-cells = <1>; + nordic,tasks = <7>; + nordic,tasks-mask = <0x007f0000>; + }; +}; + +&cpuflpr_vpr { + cpuflpr_vevif_tx: mailbox { + compatible = "nordic,nrf-vevif-event-tx"; + #mbox-cells = <1>; + nordic,events = <1>; + nordic,events-mask = <0x00100000>; + status = "disabled"; + }; +}; + +&cpuflpr_clic { + status = "okay"; +}; + +&grtc { + interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&gpiote20 { + interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&gpiote30 { + interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>; +}; diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 62262d31e87..686fdeabb69 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -61,6 +61,7 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54L15 NRF54L15_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54L15_CPUAPP NRF_APPLICATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L20_ENGA NRF54L20_ENGA_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUAPP NRF_APPLICATION) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUFLPR NRF_FLPR) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160 NRF9160_XXAA) @@ -241,6 +242,7 @@ mdk_svd_ifdef(CONFIG_SOC_NRF54L10_CPUFLPR nrf54l10_flpr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUAPP nrf54l15_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR nrf54l15_flpr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUAPP nrf54l20_enga_application.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUFLPR nrf54l20_enga_flpr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9120 nrf9120.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9160 nrf9160.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUAPP nrf9230_engb_application.svd) diff --git a/snippets/nordic-flpr/snippet.yml b/snippets/nordic-flpr/snippet.yml index f7578eccaac..dbeaf313df0 100644 --- a/snippets/nordic-flpr/snippet.yml +++ b/snippets/nordic-flpr/snippet.yml @@ -9,3 +9,6 @@ boards: /.*/nrf54h20/cpuapp/: append: EXTRA_DTC_OVERLAY_FILE: soc/nrf54h20_cpuapp.overlay + /.*/nrf54l20/cpuapp/: + append: + EXTRA_DTC_OVERLAY_FILE: soc/nrf54l20_cpuapp.overlay diff --git a/snippets/nordic-flpr/soc/nrf54l20_cpuapp.overlay b/snippets/nordic-flpr/soc/nrf54l20_cpuapp.overlay new file mode 100644 index 00000000000..1d36ba5ac48 --- /dev/null +++ b/snippets/nordic-flpr/soc/nrf54l20_cpuapp.overlay @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: image@1ed000 { + /* FLPR core code partition */ + reg = <0x1ed000 DT_SIZE_K(64)>; + }; + }; + + cpuflpr_sram_code_data: memory@2006fc00 { + compatible = "mmio-sram"; + reg = <0x2006fc00 DT_SIZE_K(64)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2006fc00 0x10000>; + }; + }; +}; + +&uart30 { + status = "reserved"; +}; + +&cpuflpr_vpr { + execution-memory = <&cpuflpr_sram_code_data>; + source-memory = <&cpuflpr_code_partition>; +}; + +&cpuapp_vevif_tx { + status = "okay"; +}; diff --git a/soc/nordic/common/vpr/Kconfig.sysbuild b/soc/nordic/common/vpr/Kconfig.sysbuild index cfbd619f623..eb62e3708bf 100644 --- a/soc/nordic/common/vpr/Kconfig.sysbuild +++ b/soc/nordic/common/vpr/Kconfig.sysbuild @@ -4,7 +4,7 @@ config VPR_LAUNCHER bool "VPR launcher" default y - depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_CPUFLPR || SOC_NRF9280_CPUPPR) + depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_CPUFLPR || SOC_NRF54L20_ENGA_CPUFLPR || SOC_NRF9280_CPUPPR) help Include VPR launcher in build. VPR launcher is a minimal sample built for an ARM core that starts given VPR core. diff --git a/soc/nordic/nrf54l/Kconfig b/soc/nordic/nrf54l/Kconfig index b8b4d015e37..fe7afd55b16 100644 --- a/soc/nordic/nrf54l/Kconfig +++ b/soc/nordic/nrf54l/Kconfig @@ -46,6 +46,9 @@ config SOC_NRF54L15_CPUFLPR config SOC_NRF54L20_ENGA_CPUAPP select SOC_NRF54L_CPUAPP_COMMON +config SOC_NRF54L20_ENGA_CPUFLPR + select RISCV_CORE_NORDIC_VPR + if SOC_SERIES_NRF54LX config SOC_NRF54LX_SKIP_CLOCK_CONFIG diff --git a/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuflpr b/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuflpr new file mode 100644 index 00000000000..4da2c703660 --- /dev/null +++ b/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuflpr @@ -0,0 +1,11 @@ +# Nordic Semiconductor nRF54L20 MCU + +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54L20_ENGA_CPUFLPR + +config NUM_IRQS + default 287 + +endif # SOC_NRF54L20_ENGA_CPUFLPR diff --git a/soc/nordic/nrf54l/Kconfig.soc b/soc/nordic/nrf54l/Kconfig.soc index e1feb7cdef1..f86b7bd4858 100644 --- a/soc/nordic/nrf54l/Kconfig.soc +++ b/soc/nordic/nrf54l/Kconfig.soc @@ -93,6 +93,12 @@ config SOC_NRF54L20_ENGA_CPUAPP help NRF54L20 ENGA CPUAPP +config SOC_NRF54L20_ENGA_CPUFLPR + bool + select SOC_NRF54L20_ENGA + help + NRF54L20 ENGA CPUFLPR + config SOC default "nrf54l05" if SOC_NRF54L05 default "nrf54l09" if SOC_NRF54L09 diff --git a/soc/nordic/soc.yml b/soc/nordic/soc.yml index b4c8ef5a034..1e9ecac5f28 100644 --- a/soc/nordic/soc.yml +++ b/soc/nordic/soc.yml @@ -39,6 +39,7 @@ family: - name: nrf54l20 cpuclusters: - name: cpuapp + - name: cpuflpr - name: nrf54h socs: - name: nrf54h20 diff --git a/soc/nordic/validate_base_addresses.c b/soc/nordic/validate_base_addresses.c index ef1dd194578..ac800f1cf00 100644 --- a/soc/nordic/validate_base_addresses.c +++ b/soc/nordic/validate_base_addresses.c @@ -339,7 +339,7 @@ CHECK_DT_REG(usbreg, NRF_USBREGULATOR); CHECK_DT_REG(vmc, NRF_VMC); CHECK_DT_REG(cpuflpr_clic, NRF_FLPR_VPRCLIC); CHECK_DT_REG(cpuppr_clic, NRF_PPR_VPRCLIC); -#if defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15) +#if defined(CONFIG_SOC_SERIES_NRF54LX) CHECK_DT_REG(cpuflpr_vpr, NRF_VPR00); #elif defined(CONFIG_NRF_PLATFORM_HALTIUM) CHECK_DT_REG(cpuflpr_vpr, NRF_VPR121);