diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index f5e76e43935..5eed35c70da 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3931,6 +3931,19 @@ OpenTitan Platforms: description: >- OpenTitan boards, SOCs, dts files and related drivers. +Realtek EC Platforms: + status: maintained + maintainers: + - JasonLin-RealTek + files: + - boards/realtek/ + - drivers/*/*rts5912* + - dts/bindings/*/*rts5912* + - dts/arm/realtek/ec/ + - soc/realtek/ec/ + labels: + - "platform: Realtek EC" + Renesas SmartBond Platforms: status: maintained maintainers: diff --git a/boards/realtek/index.rst b/boards/realtek/index.rst new file mode 100644 index 00000000000..b15a0a3d34c --- /dev/null +++ b/boards/realtek/index.rst @@ -0,0 +1,10 @@ +.. _boards-realtek: + +Realtek +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/realtek/rts5912_evb/Kconfig.defconfig b/boards/realtek/rts5912_evb/Kconfig.defconfig new file mode 100644 index 00000000000..21c1e3c6514 --- /dev/null +++ b/boards/realtek/rts5912_evb/Kconfig.defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# diff --git a/boards/realtek/rts5912_evb/Kconfig.rts5912_evb b/boards/realtek/rts5912_evb/Kconfig.rts5912_evb new file mode 100644 index 00000000000..d9e479f42b9 --- /dev/null +++ b/boards/realtek/rts5912_evb/Kconfig.rts5912_evb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config BOARD_RTS5912_EVB + select SOC_RTS5912 diff --git a/boards/realtek/rts5912_evb/board.cmake b/boards/realtek/rts5912_evb/board.cmake new file mode 100644 index 00000000000..46c6d4bd1ff --- /dev/null +++ b/boards/realtek/rts5912_evb/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/realtek/rts5912_evb/board.yml b/boards/realtek/rts5912_evb/board.yml new file mode 100644 index 00000000000..2be9b8d1746 --- /dev/null +++ b/boards/realtek/rts5912_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: rts5912_evb + vendor: realtek + socs: + - name: rts5912 diff --git a/boards/realtek/rts5912_evb/doc/rts5912_evb.rst b/boards/realtek/rts5912_evb/doc/rts5912_evb.rst new file mode 100644 index 00000000000..cb77ad613cc --- /dev/null +++ b/boards/realtek/rts5912_evb/doc/rts5912_evb.rst @@ -0,0 +1,93 @@ +.. _rts5912_evb: + +Realtek RTS5912 Evaluation Board +################################ + +Overview +******** + +The RTS5912 EVB is a development platform to evaluate the Realtek RTS5912 embedded controller. + +.. figure:: rts5912evb.webp + :width: 800px + :align: center + :alt: RTS5912-GR EVB + +Hardware +******** + +- Realtek-M300 Processor (compatible to Cortex-M33) +- Memory: + + - 384 KB SRAM + - 64 KB ROM + - 512 KB Flash(MCM) + - 256 B Battery SRAM +- PECI interface 3.1 +- FAN, PWM and TACHO pins +- 6x I2C instances +- eSPI header +- 1x PS/2 ports +- Keyboard interface headers + +For more information about the evb board please see `RTS5912_EVB_Schematics`_ and `RTS5912_DATASHEET`_ + +The board is powered through the +5V USB Type-C connector or adaptor. + +Supported Features +================== + +The ``rts5912_evb`` supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| SCCON | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| RTMR | on-chip | timer | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +Programming and Debugging +************************* + +Building +======== + +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. + +#. The file ``zephyr.rts5912.bin`` will be created if the build system can build successfully. + This binary image can be found under file "build/zephyr/". + +Flashing +======== + +#. Connect Dediprog into header ``J81`` and ``J82``. +#. Use Dediprog SF600 programmer to write the binary into the external flash ``U10`` at the address 0x0. +#. Power off the board. +#. Set the strap pin ``GPIO108`` to high and power on the board. + +Debugging +========= + +Using SWD or JTAG with ULINPRO. + +References +********** + +.. target-notes:: + +.. _RTS5912_EVB_Schematics: + https://github.com/JasonLin-RealTek/Realtek_EC/blob/main/RTS5912_EVB_Schematic_Ver%201.1_20240701_1407.pdf + +.. _RTS5912_DATASHEET: + https://github.com/JasonLin-RealTek/Realtek_EC/blob/main/RTS5912_datasheet_brief.pdf diff --git a/boards/realtek/rts5912_evb/doc/rts5912evb.webp b/boards/realtek/rts5912_evb/doc/rts5912evb.webp new file mode 100644 index 00000000000..e8a7d96420a Binary files /dev/null and b/boards/realtek/rts5912_evb/doc/rts5912evb.webp differ diff --git a/boards/realtek/rts5912_evb/rts5912_evb.dts b/boards/realtek/rts5912_evb/rts5912_evb.dts new file mode 100644 index 00000000000..1e22d6c4ace --- /dev/null +++ b/boards/realtek/rts5912_evb/rts5912_evb.dts @@ -0,0 +1,36 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * + */ + +/dts-v1/; +#include +#include +#include +/ { + model = "Realtek RTS5912 Evaluation Board"; + compatible = "realtek,rts5912-evb"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,flash = &flash0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; + +&uart0_wrapper { + status = "okay"; + pinctrl-0 = <&uart_rx_gpio113 &uart_tx_gpio114>; + pinctrl-names = "default"; +}; + +&swj_port { + status = "okay"; +}; diff --git a/boards/realtek/rts5912_evb/rts5912_evb.yaml b/boards/realtek/rts5912_evb/rts5912_evb.yaml new file mode 100644 index 00000000000..199a6e1027a --- /dev/null +++ b/boards/realtek/rts5912_evb/rts5912_evb.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +identifier: rts5912_evb +name: RTS5912-EVB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 64 +flash: 320 +supported: + - gpio + - pinmux +vendor: realtek diff --git a/boards/realtek/rts5912_evb/rts5912_evb_defconfig b/boards/realtek/rts5912_evb/rts5912_evb_defconfig new file mode 100644 index 00000000000..64454c374d5 --- /dev/null +++ b/boards/realtek/rts5912_evb/rts5912_evb_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +# Enable RTS5912 image tool +CONFIG_REALTEK_RTS5912_BOOTROM_HEADER=y + +# Serial Driver +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 057f4463247..33ad557742a 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -38,6 +38,8 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RPI_PICO clock_control_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL clock_control_nrf2_global_hsfll.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RTS5912_SCCON clock_control_rts5912_sccon.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL clock_control_nrf2_audiopll.c) if(CONFIG_CLOCK_CONTROL_NRF2) zephyr_library_sources(clock_control_nrf2_common.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index 040dab163c2..eec9b11c188 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -56,6 +56,8 @@ source "drivers/clock_control/Kconfig.npcx" source "drivers/clock_control/Kconfig.rv32m1" +source "drivers/clock_control/Kconfig.rts5912" + source "drivers/clock_control/Kconfig.esp32" source "drivers/clock_control/Kconfig.litex" diff --git a/drivers/clock_control/Kconfig.nrf b/drivers/clock_control/Kconfig.nrf index b5b066ac48e..da330f7b08e 100644 --- a/drivers/clock_control/Kconfig.nrf +++ b/drivers/clock_control/Kconfig.nrf @@ -226,4 +226,10 @@ config CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY endif # CLOCK_CONTROL_NRF2_GLOBAL_HSFLL +config CLOCK_CONTROL_NRF2_AUDIOPLL + bool "NRFS AudioPLL driver support" + depends on DT_HAS_NORDIC_NRFS_AUDIOPLL_ENABLED + depends on NRFS_AUDIOPLL_SERVICE_ENABLED + default y + endif # CLOCK_CONTROL_NRF2 diff --git a/drivers/clock_control/Kconfig.rts5912 b/drivers/clock_control/Kconfig.rts5912 new file mode 100644 index 00000000000..ec5547cb91d --- /dev/null +++ b/drivers/clock_control/Kconfig.rts5912 @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config CLOCK_CONTROL_RTS5912_SCCON + bool "Realtek RTS5912 system clock controller driver" + default y if DT_HAS_REALTEK_RTS5912_SCCON_ENABLED + help + Enable support for RTS5912 system clock controller driver diff --git a/drivers/clock_control/clock_control_nrf2_audiopll.c b/drivers/clock_control/clock_control_nrf2_audiopll.c new file mode 100644 index 00000000000..c4df962144a --- /dev/null +++ b/drivers/clock_control/clock_control_nrf2_audiopll.c @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nordic_nrfs_audiopll + +#include "clock_control_nrf2_common.h" +#include +#include +#include +#include +#include + +#include +LOG_MODULE_DECLARE(clock_control_nrf2, CONFIG_CLOCK_CONTROL_LOG_LEVEL); + +#define SHIM_DEFAULT_PRESCALER AUDIOPLL_DIV_12 + +BUILD_ASSERT( + DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, + "multiple instances not supported" +); + +BUILD_ASSERT(DT_INST_PROP(0, frequency) >= NRFS_AUDIOPLL_FREQ_MIN); +BUILD_ASSERT(DT_INST_PROP(0, frequency) <= NRFS_AUDIOPLL_FREQ_MAX); + +struct shim_data { + struct onoff_manager mgr; + onoff_notify_fn mgr_notify; + const struct device *dev; + struct k_sem evt_sem; + nrfs_audiopll_evt_type_t evt; +}; + +static int shim_nrfs_request_enable(const struct device *dev) +{ + struct shim_data *dev_data = dev->data; + nrfs_err_t err; + + LOG_DBG("send enable request"); + + dev_data->evt = NRFS_AUDIOPLL_EVT_ENABLED; + err = nrfs_audiopll_enable_request(dev_data); + if (err != NRFS_SUCCESS) { + return -EIO; + } + + return 0; +} + +static int shim_nrfs_request_disable(const struct device *dev) +{ + struct shim_data *dev_data = dev->data; + nrfs_err_t err; + + LOG_DBG("send disable request"); + + dev_data->evt = NRFS_AUDIOPLL_EVT_DISABLED; + err = nrfs_audiopll_disable_request(dev_data); + if (err != NRFS_SUCCESS) { + return -EIO; + } + + return 0; +} + +static void onoff_start_option(struct onoff_manager *mgr, onoff_notify_fn notify) +{ + struct shim_data *dev_data = CONTAINER_OF(mgr, struct shim_data, mgr); + const struct device *dev = dev_data->dev; + int ret; + + dev_data->mgr_notify = notify; + + ret = shim_nrfs_request_enable(dev); + if (ret) { + dev_data->mgr_notify = NULL; + notify(mgr, -EIO); + } +} + +static void onoff_stop_option(struct onoff_manager *mgr, onoff_notify_fn notify) +{ + struct shim_data *dev_data = CONTAINER_OF(mgr, struct shim_data, mgr); + const struct device *dev = dev_data->dev; + int ret; + + dev_data->mgr_notify = notify; + + ret = shim_nrfs_request_disable(dev); + if (ret) { + dev_data->mgr_notify = NULL; + notify(mgr, -EIO); + } +} + +static const struct onoff_transitions shim_mgr_transitions = { + .start = onoff_start_option, + .stop = onoff_stop_option +}; + +/* + * Formula: + * + * frequency = ((4 + (freq_fraction * 2^-16)) * 32000000) / 12 + * + * Simplified linear approximation: + * + * frequency = 10666666 + (((13333292 - 10666666) / 65535) * freq_fraction) + * frequency = 10666666 + ((2666626 / 65535) * freq_fraction) + * frequency = ((10666666 * 65535) + (2666626 * freq_fraction)) / 65535 + * frequency = (699039956310 + (2666626 * freq_fraction)) / 65535 + * + * Isolate freq_fraction: + * + * frequency = (699039956310 + (2666626 * freq_fraction)) / 65535 + * frequency * 65535 = 699039956310 + (2666626 * freq_fraction) + * (frequency * 65535) - 699039956310 = 2666626 * freq_fraction + * freq_fraction = ((frequency * 65535) - 699039956310) / 2666626 + */ +static uint16_t shim_frequency_to_freq_fraction(uint32_t frequency) +{ + uint64_t freq_fraction; + + freq_fraction = frequency; + freq_fraction *= 65535; + freq_fraction -= 699039956310; + freq_fraction = DIV_ROUND_CLOSEST(freq_fraction, 2666626); + + return (uint16_t)freq_fraction; +} + +static int shim_nrfs_request_freq_sync(const struct device *dev, uint16_t freq_fraction) +{ + struct shim_data *dev_data = dev->data; + nrfs_err_t err; + + LOG_DBG("send freq request"); + + err = nrfs_audiopll_request_freq(freq_fraction, dev_data); + if (err != NRFS_SUCCESS) { + return -EIO; + } + + k_sem_take(&dev_data->evt_sem, K_FOREVER); + return dev_data->evt == NRFS_AUDIOPLL_EVT_FREQ_CONFIRMED ? 0 : -EIO; +} + +static int shim_nrfs_request_prescaler_sync(const struct device *dev, + enum audiopll_prescaler_div div) +{ + struct shim_data *dev_data = dev->data; + nrfs_err_t err; + + LOG_DBG("send prescaler request"); + + err = nrfs_audiopll_request_prescaler(div, dev_data); + if (err != NRFS_SUCCESS) { + return -EIO; + } + + k_sem_take(&dev_data->evt_sem, K_FOREVER); + return dev_data->evt == NRFS_AUDIOPLL_EVT_PRESCALER_CONFIRMED ? 0 : -EIO; +} + +static void shim_nrfs_audiopll_init_evt_handler(nrfs_audiopll_evt_t const *evt, void *context) +{ + struct shim_data *dev_data = context; + + LOG_DBG("init resp evt %u", (uint32_t)evt->type); + + dev_data->evt = evt->type; + k_sem_give(&dev_data->evt_sem); +} + +static void shim_nrfs_audiopll_evt_handler(nrfs_audiopll_evt_t const *evt, void *context) +{ + struct shim_data *dev_data = context; + int ret; + + LOG_DBG("resp evt %u", (uint32_t)evt->type); + + if (dev_data->mgr_notify == NULL) { + return; + } + + ret = evt->type == dev_data->evt ? 0 : -EIO; + dev_data->mgr_notify(&dev_data->mgr, ret); +} + +static int api_request_audiopll(const struct device *dev, + const struct nrf_clock_spec *spec, + struct onoff_client *cli) +{ + struct shim_data *dev_data = dev->data; + struct onoff_manager *mgr = &dev_data->mgr; + + ARG_UNUSED(spec); + + return onoff_request(mgr, cli); +} + +static int api_release_audiopll(const struct device *dev, + const struct nrf_clock_spec *spec) +{ + struct shim_data *dev_data = dev->data; + struct onoff_manager *mgr = &dev_data->mgr; + + ARG_UNUSED(spec); + + return onoff_release(mgr); +} + +static int api_cancel_or_release_audiopll(const struct device *dev, + const struct nrf_clock_spec *spec, + struct onoff_client *cli) +{ + struct shim_data *dev_data = dev->data; + struct onoff_manager *mgr = &dev_data->mgr; + + ARG_UNUSED(spec); + + return onoff_cancel_or_release(mgr, cli); +} + +static DEVICE_API(nrf_clock_control, shim_driver_api) = { + .std_api = { + .on = api_nosys_on_off, + .off = api_nosys_on_off, + }, + .request = api_request_audiopll, + .release = api_release_audiopll, + .cancel_or_release = api_cancel_or_release_audiopll, +}; + +static int shim_init(const struct device *dev) +{ + struct shim_data *dev_data = dev->data; + nrfs_err_t err; + int ret; + uint16_t freq_fraction; + + LOG_DBG("waiting for nrfs backend connected"); + err = nrfs_backend_wait_for_connection(K_FOREVER); + if (err != NRFS_SUCCESS) { + LOG_ERR("nrfs backend not connected"); + return -ENODEV; + } + + k_sem_init(&dev_data->evt_sem, 0, 1); + + err = nrfs_audiopll_init(shim_nrfs_audiopll_init_evt_handler); + if (err != NRFS_SUCCESS) { + LOG_ERR("failed to init audiopll service"); + return -ENODEV; + } + + ret = shim_nrfs_request_prescaler_sync(dev, SHIM_DEFAULT_PRESCALER); + if (ret) { + LOG_ERR("failed to set prescaler divider"); + return ret; + } + + freq_fraction = shim_frequency_to_freq_fraction(DT_INST_PROP(0, frequency)); + + LOG_DBG("requesting freq_fraction %u for frequency %uHz", + freq_fraction, + DT_INST_PROP(0, frequency)); + + ret = shim_nrfs_request_freq_sync(dev, freq_fraction); + if (ret) { + LOG_ERR("failed to set freq_fraction"); + return ret; + } + + nrfs_audiopll_uninit(); + + ret = onoff_manager_init(&dev_data->mgr, &shim_mgr_transitions); + if (ret < 0) { + LOG_ERR("failed to init onoff manager"); + return ret; + } + + err = nrfs_audiopll_init(shim_nrfs_audiopll_evt_handler); + if (err != NRFS_SUCCESS) { + LOG_ERR("failed to init audiopll service"); + return -ENODEV; + } + + return 0; +} + +static struct shim_data shim_data = { + .dev = DEVICE_DT_INST_GET(0), +}; + +DEVICE_DT_INST_DEFINE( + 0, + shim_init, + NULL, + &shim_data, + NULL, + POST_KERNEL, + UTIL_INC(CONFIG_NRFS_BACKEND_IPC_SERVICE_INIT_PRIO), + &shim_driver_api, +); diff --git a/drivers/clock_control/clock_control_rts5912_sccon.c b/drivers/clock_control/clock_control_rts5912_sccon.c new file mode 100644 index 00000000000..686c47a4904 --- /dev/null +++ b/drivers/clock_control/clock_control_rts5912_sccon.c @@ -0,0 +1,247 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#define DT_DRV_COMPAT realtek_rts5912_sccon + +#include +#include +#include +#include + +#include + +LOG_MODULE_REGISTER(sccon, CONFIG_CLOCK_CONTROL_LOG_LEVEL); + +#define RC25M_FREQ DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rc25m), clock_frequency) +#define PLL_FREQ DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), clock_frequency) + +struct rts5912_sccon_config { + uint32_t reg_base; + uint8_t sysclk_src; + uint8_t sysclk_div; +}; + +static int rts5912_periph_clock_control(const struct device *dev, clock_control_subsys_t sub_system, + bool on_off) +{ + const struct rts5912_sccon_config *const config = dev->config; + struct rts5912_sccon_subsys *subsys = (struct rts5912_sccon_subsys *)sub_system; + + SYSTEM_Type *sys_reg = (SYSTEM_Type *)config->reg_base; + + uint32_t clk_grp = subsys->clk_grp; + uint32_t clk_idx = subsys->clk_idx; + + uint32_t module_idx; + + switch (clk_grp) { + case RTS5912_SCCON_I2C: + module_idx = (clk_idx - I2C0_CLKPWR) >> 2; + + if (on_off) { + sys_reg->I2CCLK |= BIT(clk_idx); + } else { + sys_reg->I2CCLK &= ~BIT(clk_idx); + } + + LOG_DBG("Turn I2C%d clock <%s>", module_idx, on_off ? "ON" : "OFF"); + break; + case RTS5912_SCCON_UART: + if (on_off) { + sys_reg->UARTCLK = BIT(clk_idx); + } else { + sys_reg->UARTCLK &= ~BIT(clk_idx); + } + + LOG_DBG("Turn UART0 clock <%s>", on_off ? "ON" : "OFF"); + break; + case RTS5912_SCCON_ADC: + if (on_off) { + sys_reg->ADCCLK = BIT(clk_idx); + } else { + sys_reg->ADCCLK &= ~BIT(clk_idx); + } + + LOG_DBG("Turn ADC clock <%s>", on_off ? "ON" : "OFF"); + break; + case RTS5912_SCCON_PERIPH_GRP0: + if (on_off) { + sys_reg->PERICLKPWR0 |= BIT(clk_idx); + } else { + sys_reg->PERICLKPWR0 &= ~BIT(clk_idx); + } + + LOG_DBG("Turn GRP0-%d clock <%s>", clk_idx, on_off ? "ON" : "OFF"); + break; + case RTS5912_SCCON_PERIPH_GRP1: + if (on_off) { + sys_reg->PERICLKPWR1 |= BIT(clk_idx); + } else { + sys_reg->PERICLKPWR1 &= ~BIT(clk_idx); + } + + LOG_DBG("Turn GRP1-%d clock <%s>", clk_idx, on_off ? "ON" : "OFF"); + break; + case RTS5912_SCCON_PERIPH_GRP2: + if (on_off) { + sys_reg->PERICLKPWR2 |= BIT(clk_idx); + } else { + sys_reg->PERICLKPWR2 &= ~BIT(clk_idx); + } + + LOG_DBG("Turn GRP2-%d clock <%s>", clk_idx, on_off ? "ON" : "OFF"); + break; + case RTS5912_SCCON_SYS: + LOG_ERR("Not support peripheral group #%d-%d", clk_grp, clk_idx); + return -ENOTSUP; + default: + LOG_ERR("Unknown peripheral group #%d", clk_grp); + return -EINVAL; + } + + return 0; +} + +static int rts5912_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) +{ + return rts5912_periph_clock_control(dev, sub_system, true); +} + +static int rts5912_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system) +{ + return rts5912_periph_clock_control(dev, sub_system, false); +} + +static int rts5912_clock_control_get_rate(const struct device *dev, + clock_control_subsys_t sub_system, uint32_t *rate) +{ + const struct rts5912_sccon_config *const config = dev->config; + struct rts5912_sccon_subsys *subsys = (struct rts5912_sccon_subsys *)sub_system; + + SYSTEM_Type *sys_reg = (SYSTEM_Type *)config->reg_base; + + uint32_t clk_grp = subsys->clk_grp; + uint32_t clk_idx = subsys->clk_idx; + uint32_t module_idx; + + uint32_t offset; + uint32_t src, divide, freq = 0; + + switch (clk_grp) { + case RTS5912_SCCON_I2C: + module_idx = (clk_idx - I2C0_CLKPWR) >> 2; + + offset = (SYSTEM_I2CCLK_I2C1CLKSRC_Pos - SYSTEM_I2CCLK_I2C0CLKSRC_Pos) * module_idx; + src = ((sys_reg->I2CCLK >> offset) & SYSTEM_I2CCLK_I2C0CLKSRC_Msk) ? PLL_FREQ + : RC25M_FREQ; + + offset = SYSTEM_I2CCLK_I2C0CLKDIV_Pos; + offset += (SYSTEM_I2CCLK_I2C1CLKDIV_Pos - SYSTEM_I2CCLK_I2C0CLKDIV_Pos) * + module_idx; + divide = (sys_reg->I2CCLK >> offset) & SYSTEM_I2CCLK_I2C0CLKDIV_Msk; + + freq = src >> divide; + + LOG_DBG("I2C%d: src<%s> divide<%ld> freq<%d>", module_idx, + (src == PLL_FREQ) ? "PLL" : "RC25M", BIT(divide), freq); + break; + case RTS5912_SCCON_UART: + src = (sys_reg->UARTCLK & SYSTEM_UARTCLK_SRC_Msk) ? PLL_FREQ : RC25M_FREQ; + divide = (sys_reg->UARTCLK & SYSTEM_UARTCLK_DIV_Msk) >> SYSTEM_UARTCLK_DIV_Pos; + freq = src >> divide; + + LOG_DBG("UART0: src<%s> divide<%ld> freq<%d>", (src == PLL_FREQ) ? "PLL" : "RC25M", + BIT(divide), freq); + break; + case RTS5912_SCCON_ADC: + src = (sys_reg->ADCCLK & SYSTEM_ADCCLK_SRC_Msk) ? RC25M_FREQ : PLL_FREQ; + divide = (sys_reg->ADCCLK & SYSTEM_ADCCLK_DIV_Msk) >> SYSTEM_ADCCLK_DIV_Pos; + + switch (divide) { + case 0: + __fallthrough; + case 1: + __fallthrough; + case 2: + __fallthrough; + case 3: + divide += 1; + freq = src / divide; + break; + case 4: + freq = src / 6; + divide = 6; + break; + case 5: + freq = src / 8; + divide = 8; + break; + case 6: + freq = src / 12; + divide = 12; + break; + case 7: + freq = src / 16; + divide = 16; + break; + default: + return -EINVAL; + } + + LOG_DBG("ADC0: src<%s> divide<%d> freq<%d>", (src == PLL_FREQ) ? "PLL" : "RC25M", + divide, freq); + break; + case RTS5912_SCCON_SYS: + src = (sys_reg->SYSCLK & SYSTEM_SYSCLK_SRC_Msk) ? PLL_FREQ : RC25M_FREQ; + divide = (sys_reg->SYSCLK & SYSTEM_SYSCLK_DIV_Msk) ? 0x01ul : 0x00ul; + freq = src >> divide; + + LOG_DBG("System Clock: src<%s> divide<%d> freq<%d>", + (src == PLL_FREQ) ? "PLL" : "RC25M", divide, freq); + break; + case RTS5912_SCCON_PERIPH_GRP0: + __fallthrough; + case RTS5912_SCCON_PERIPH_GRP1: + __fallthrough; + case RTS5912_SCCON_PERIPH_GRP2: + LOG_ERR("Not support peripheral group #%d-%d", clk_grp, clk_idx); + return -ENOTSUP; + default: + LOG_ERR("Unknown peripheral group #%d", clk_grp); + return -EINVAL; + } + + *rate = freq; + return 0; +} + +static DEVICE_API(clock_control, rts5912_clock_control_api) = { + .on = rts5912_clock_control_on, + .off = rts5912_clock_control_off, + .get_rate = rts5912_clock_control_get_rate, +}; + +static int rts5912_clock_control_init(const struct device *dev) +{ + const struct rts5912_sccon_config *const config = dev->config; + SYSTEM_Type *sys_reg = (SYSTEM_Type *)config->reg_base; + + /* Setup system clock */ + sys_reg->SYSCLK = (config->sysclk_src << SYSTEM_SYSCLK_SRC_Pos) | + (config->sysclk_div << SYSTEM_SYSCLK_DIV_Pos); + + return 0; +} + +const struct rts5912_sccon_config rts5912_sccon_config = { + .reg_base = DT_INST_REG_ADDR_BY_IDX(0, 0), + .sysclk_src = 1, + .sysclk_div = 0, +}; + +DEVICE_DT_INST_DEFINE(0, &rts5912_clock_control_init, NULL, NULL, &rts5912_sccon_config, + PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &rts5912_clock_control_api); diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index dcc4b96a54f..d88cb2b87a9 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -82,6 +82,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_RP1 gpio_rp1.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RPI_PICO gpio_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RT1718S gpio_rt1718s.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RT1718S gpio_rt1718s_port.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_RTS5912 gpio_rts5912.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RV32M1 gpio_rv32m1.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RZT2M gpio_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_GPIO_SAM gpio_sam.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ba1ed8a3f64..6ca6216a046 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -167,6 +167,7 @@ source "drivers/gpio/Kconfig.renesas_rz" source "drivers/gpio/Kconfig.rp1" source "drivers/gpio/Kconfig.rpi_pico" source "drivers/gpio/Kconfig.rt1718s" +source "drivers/gpio/Kconfig.rts5912" source "drivers/gpio/Kconfig.rv32m1" source "drivers/gpio/Kconfig.rzt2m" source "drivers/gpio/Kconfig.sam" diff --git a/drivers/gpio/Kconfig.rts5912 b/drivers/gpio/Kconfig.rts5912 new file mode 100644 index 00000000000..a0d845a8b3e --- /dev/null +++ b/drivers/gpio/Kconfig.rts5912 @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config GPIO_RTS5912 + bool "Realtek embedded controller (EC) gpio driver" + default y if DT_HAS_REALTEK_RTS5912_GPIO_ENABLED + help + Enable support for Realtek GPIO controller. diff --git a/drivers/gpio/gpio_rts5912.c b/drivers/gpio/gpio_rts5912.c new file mode 100644 index 00000000000..bda68ae39a5 --- /dev/null +++ b/drivers/gpio/gpio_rts5912.c @@ -0,0 +1,457 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#define DT_DRV_COMPAT realtek_rts5912_gpio + +#include +#include +#include +#include +#include +#include "zephyr/drivers/gpio/gpio_utils.h" +#include +#include + +#include + +LOG_MODULE_REGISTER(gpio_rts5912, CONFIG_GPIO_LOG_LEVEL); + +#define RTS5912_GPIOA_REG_BASE ((GPIO_Type *)(DT_REG_ADDR(DT_NODELABEL(gpioa)))) + +struct gpio_rts5912_config { + struct gpio_driver_config common; + volatile uint32_t *reg_base; + uint8_t num_pins; +}; + +struct gpio_rts5912_data { + struct gpio_driver_data common; + sys_slist_t callbacks; +}; + +static int pin_is_valid(const struct gpio_rts5912_config *config, gpio_pin_t pin) +{ + if (pin >= config->num_pins) { + return -EINVAL; + } + + return 0; +} + +static int pin_output_high(const struct device *port, gpio_pin_t pin) +{ + const struct gpio_rts5912_config *config = port->config; + volatile uint32_t *gcr = &config->reg_base[pin]; + + int err = pin_is_valid(config, pin); + + if (err) { + return err; + } + + if (*gcr & GPIO_GCR_OUTMD_Msk) { + /* Switch I/O mode to input mode when configuration is open-drain with output high + */ + *gcr = (*gcr & ~GPIO_GCR_DIR_Msk) | GPIO_GCR_OUTCTRL_Msk; + } else { + *gcr |= GPIO_GCR_OUTCTRL_Msk | GPIO_GCR_DIR_Msk; + } + + return 0; +} + +static int pin_output_low(const struct device *port, gpio_pin_t pin) +{ + const struct gpio_rts5912_config *config = port->config; + volatile uint32_t *gcr = &config->reg_base[pin]; + + int err = pin_is_valid(config, pin); + + if (err) { + return err; + } + + *gcr = (*gcr & ~GPIO_GCR_OUTCTRL_Msk) | GPIO_GCR_DIR_Msk; + + return 0; +} + +static int gpio_rts5912_configuration(const struct device *port, gpio_pin_t pin, gpio_flags_t flags) +{ + const struct gpio_rts5912_config *config = port->config; + volatile uint32_t *gcr = &config->reg_base[pin]; + uint32_t cfg_val = *gcr; + + int err = pin_is_valid(config, pin); + + if (err) { + return err; + } + + if (flags & GPIO_INPUT) { + cfg_val &= ~GPIO_GCR_DIR_Msk; + cfg_val &= ~GPIO_GCR_OUTCTRL_Msk; + cfg_val |= GPIO_GCR_INDETEN_Msk; + } + + if (flags & GPIO_OPEN_DRAIN) { + cfg_val |= GPIO_GCR_OUTMD_Msk; + } else { + cfg_val &= ~GPIO_GCR_OUTMD_Msk; + } + + switch (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) { + case GPIO_PULL_UP: + cfg_val &= ~GPIO_GCR_PULLDWEN_Msk; + cfg_val |= GPIO_GCR_PULLUPEN_Msk; + break; + case GPIO_PULL_DOWN: + cfg_val &= ~GPIO_GCR_PULLUPEN_Msk; + cfg_val |= GPIO_GCR_PULLDWEN_Msk; + break; + default: + break; + } + + switch (flags & RTS5912_GPIO_VOLTAGE_MASK) { + case RTS5912_GPIO_VOLTAGE_1V8: + cfg_val |= GPIO_GCR_INVOLMD_Msk; + break; + case RTS5912_GPIO_VOLTAGE_DEFAULT: + case RTS5912_GPIO_VOLTAGE_3V3: + cfg_val &= ~GPIO_GCR_INVOLMD_Msk; + break; + case RTS5912_GPIO_VOLTAGE_5V0: + return -ENOTSUP; + default: + break; + } + + *gcr = cfg_val; + + if (flags & GPIO_OUTPUT) { + if (flags & GPIO_OUTPUT_INIT_HIGH) { + pin_output_high(port, pin); + } else { + pin_output_low(port, pin); + } + } + + return 0; +} + +#ifdef CONFIG_GPIO_GET_CONFIG +static int gpio_rts5912_get_configuration(const struct device *port, gpio_pin_t pin, + gpio_flags_t *flags) +{ + const struct gpio_rts5912_config *config = port->config; + volatile uint32_t *gcr = &config->reg_base[pin]; + gpio_flags_t cfg_flag = 0x0UL; + + int err = pin_is_valid(config, pin); + + if (err) { + return err; + } + + if (*gcr & GPIO_GCR_OUTCTRL_Msk) { + cfg_flag |= GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH; + } else { + if (*gcr & GPIO_GCR_DIR_Msk) { + cfg_flag |= GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW; + } else { + cfg_flag |= GPIO_INPUT; + if (*gcr & GPIO_GCR_INVOLMD_Msk) { + cfg_flag |= RTS5912_GPIO_VOLTAGE_1V8; + } else { + cfg_flag |= RTS5912_GPIO_VOLTAGE_3V3; + } + } + } + + if (*gcr & GPIO_GCR_OUTMD_Msk) { + cfg_flag |= GPIO_OPEN_DRAIN; + } + + if (*gcr & GPIO_GCR_PULLUPEN_Msk) { + cfg_flag |= GPIO_PULL_UP; + } else if (*gcr & GPIO_GCR_PULLDWEN_Msk) { + cfg_flag |= GPIO_PULL_DOWN; + } + + *flags = cfg_flag; + + return 0; +} +#endif + +static int gpio_rts5912_port_get_raw(const struct device *port, gpio_port_value_t *value) +{ + const struct gpio_rts5912_config *config = port->config; + gpio_port_value_t ret_val = 0; + uint16_t mask = 0x1U; + + for (gpio_pin_t i = 0; i < config->num_pins; i++) { + if (config->reg_base[i] & GPIO_GCR_PINSTS_Msk) { + ret_val |= (gpio_port_value_t)mask; + } + mask <<= 1; + } + + *value = ret_val; + + return 0; +} + +static int gpio_rts5912_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct gpio_rts5912_config *config = port->config; + uint32_t pin; + + mask &= 0x0000FFFF; + for (; mask; mask &= ~BIT(pin)) { + pin = find_lsb_set(mask) - 1; + if (pin >= config->num_pins) { + break; + } + + if (value & BIT(pin)) { + pin_output_high(port, pin); + } else { + pin_output_low(port, pin); + } + } + + return 0; +} + +static int gpio_rts5912_port_set_bits_raw(const struct device *port, gpio_port_pins_t pins) +{ + const struct gpio_rts5912_config *config = port->config; + volatile uint32_t *gcr = config->reg_base; + uint32_t pin = 0; + + pins &= 0x0000FFFF; + gpio_port_pins_t sel_pin = 1; + + for (; pins;) { + if (pins & sel_pin) { + pin_output_high(port, pin); + } + pins &= ~sel_pin; + sel_pin <<= 1; + gcr++; + pin++; + } + + return 0; +} + +static int gpio_rts5912_port_clear_bits_raw(const struct device *port, gpio_port_pins_t pins) +{ + const struct gpio_rts5912_config *config = port->config; + volatile uint32_t *gcr = config->reg_base; + uint32_t pin = 0; + + pins &= 0x0000FFFF; + gpio_port_pins_t sel_pin = 1; + + for (; pins;) { + if (pins & sel_pin) { + pin_output_low(port, pin); + } + pins &= ~sel_pin; + sel_pin <<= 1; + gcr++; + pin++; + } + + return 0; +} + +static int gpio_rts5912_port_toggle_bits(const struct device *port, gpio_port_pins_t pins) +{ + const struct gpio_rts5912_config *config = port->config; + volatile uint32_t *gcr = config->reg_base; + uint32_t pin = 0; + + pins &= 0x0000FFFF; + gpio_port_pins_t sel_pin = 0x1UL; + + for (; pins;) { + if (pins & sel_pin) { + if (*gcr & GPIO_GCR_OUTCTRL_Msk) { + pin_output_low(port, pin); + } else { + pin_output_high(port, pin); + } + } + + pins &= ~sel_pin; + sel_pin <<= 1; + gcr++; + pin++; + } + + return 0; +} + +static gpio_pin_t gpio_rts5912_get_intr_pin(volatile uint32_t *reg_base) +{ + gpio_pin_t pin = 0U; + + for (; pin < 16; pin++) { + if (reg_base[pin] & GPIO_GCR_INTSTS_Msk) { + break; + } + } + + return pin; +} + +static void gpio_rts5912_isr(const void *arg) +{ + const struct device *port = arg; + const struct gpio_rts5912_config *config = port->config; + struct gpio_rts5912_data *data = port->data; + volatile uint32_t *gcr = config->reg_base; + unsigned int key = irq_lock(); + gpio_pin_t pin = gpio_rts5912_get_intr_pin(gcr); + + if (gcr[pin] & GPIO_GCR_INTSTS_Msk) { + gcr[pin] |= GPIO_GCR_INTSTS_Msk; + + gpio_fire_callbacks(&data->callbacks, port, BIT(pin)); + } + irq_unlock(key); +} + +static int gpio_rts5912_intr_config(const struct device *port, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) +{ + const struct gpio_rts5912_config *config = port->config; + volatile uint32_t *gcr = &config->reg_base[pin]; + uint32_t cfg_val = *gcr; + uint32_t pin_index = + DT_IRQ_BY_IDX(DT_NODELABEL(gpioa), 0, irq) + + ((uint32_t)(&config->reg_base[pin]) - (uint32_t)(RTS5912_GPIOA_REG_BASE)) / 4; + + int err = pin_is_valid(config, pin); + + if (err) { + return err; + } + + switch (mode) { + case GPIO_INT_MODE_DISABLED: + cfg_val &= ~GPIO_GCR_INTEN_Msk; + irq_disable(pin_index); + *gcr = cfg_val; + return 0; + case GPIO_INT_MODE_LEVEL: + switch (trig) { + case GPIO_INT_TRIG_LOW: + cfg_val &= ~GPIO_GCR_INTCTRL_Msk; + cfg_val |= 0x03UL << GPIO_GCR_INTCTRL_Pos; + break; + case GPIO_INT_TRIG_HIGH: + cfg_val &= ~GPIO_GCR_INTCTRL_Msk; + cfg_val |= 0x04UL << GPIO_GCR_INTCTRL_Pos; + break; + default: + return -EINVAL; + } + break; + case GPIO_INT_MODE_EDGE: + switch (trig) { + case GPIO_INT_TRIG_LOW: + cfg_val &= ~GPIO_GCR_INTCTRL_Msk; + cfg_val |= 0x01UL << GPIO_GCR_INTCTRL_Pos; + break; + case GPIO_INT_TRIG_HIGH: + cfg_val &= ~GPIO_GCR_INTCTRL_Msk; + cfg_val |= 0x00UL << GPIO_GCR_INTCTRL_Pos; + break; + case GPIO_INT_TRIG_BOTH: + cfg_val &= ~GPIO_GCR_INTCTRL_Msk; + cfg_val |= 0x2UL << GPIO_GCR_INTCTRL_Pos; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + cfg_val |= GPIO_GCR_INTEN_Msk; + *gcr = cfg_val; + + irq_enable(pin_index); + + return 0; +} + +static int gpio_rts5912_manage_cb(const struct device *port, struct gpio_callback *cb, bool set) +{ + struct gpio_rts5912_data *data = port->data; + + return gpio_manage_callback(&data->callbacks, cb, set); +} + +static DEVICE_API(gpio, gpio_rts5912_driver_api) = { + .pin_configure = gpio_rts5912_configuration, +#ifdef CONFIG_GPIO_GET_CONFIG + .pin_get_config = gpio_rts5912_get_configuration, +#endif + .port_get_raw = gpio_rts5912_port_get_raw, + .port_set_masked_raw = gpio_rts5912_port_set_masked_raw, + .port_set_bits_raw = gpio_rts5912_port_set_bits_raw, + .port_clear_bits_raw = gpio_rts5912_port_clear_bits_raw, + .port_toggle_bits = gpio_rts5912_port_toggle_bits, + .pin_interrupt_configure = gpio_rts5912_intr_config, + .manage_callback = gpio_rts5912_manage_cb, +}; + +#ifdef CONFIG_GEN_ISR_TABLES +#define RTS5912_GPIO_DTNAMIC_IRQ(id) \ + for (int i = 0; i < 16 && (DT_INST_IRQ_BY_IDX(id, 0, irq) + i) < 132; i++) { \ + irq_connect_dynamic((DT_INST_IRQ_BY_IDX(id, 0, irq) + i), \ + DT_INST_IRQ(id, priority), gpio_rts5912_isr, \ + DEVICE_DT_INST_GET(id), 0U); \ + } +#else +#define RTS5912_GPIO_DTNAMIC_IRQ(id) \ + IRQ_CONNECT(DT_INST_IRQN(id), DT_INST_IRQ(id, priority), gpio_rts5912_isr, \ + DEVICE_DT_INST_GET(id), 0U); +#endif + +#define GPIO_RTS5912_INIT(id) \ + static int gpio_rts5912_init_##id(const struct device *dev) \ + { \ + if (!(DT_INST_IRQ_HAS_CELL(id, irq))) { \ + return 0; \ + } \ + \ + RTS5912_GPIO_DTNAMIC_IRQ(id) \ + \ + return 0; \ + } \ + \ + static struct gpio_rts5912_data gpio_rts5912_data_##id; \ + \ + static const struct gpio_rts5912_config gpio_rts5912_config_##id = { \ + .common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id)}, \ + .reg_base = (volatile uint32_t *)DT_INST_REG_ADDR(id), \ + .num_pins = DT_INST_PROP(id, ngpios), \ + }; \ + DEVICE_DT_INST_DEFINE(id, gpio_rts5912_init_##id, NULL, &gpio_rts5912_data_##id, \ + &gpio_rts5912_config_##id, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \ + &gpio_rts5912_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(GPIO_RTS5912_INIT) diff --git a/drivers/i2s/Kconfig.nrfx b/drivers/i2s/Kconfig.nrfx index 4b7a9f6177a..6c92cda3993 100644 --- a/drivers/i2s/Kconfig.nrfx +++ b/drivers/i2s/Kconfig.nrfx @@ -28,6 +28,7 @@ menuconfig TDM_NRFX default y depends on DT_HAS_NORDIC_NRF_TDM_ENABLED select NRFX_TDM130 if HAS_HW_NRF_TDM130 + select CLOCK_CONTROL select PINCTRL help Enable support for nrfx TDM driver for nRF MCU series. diff --git a/drivers/i2s/i2s_nrfx_tdm.c b/drivers/i2s/i2s_nrfx_tdm.c index 0482fa732f6..4ca14ccd48f 100644 --- a/drivers/i2s/i2s_nrfx_tdm.c +++ b/drivers/i2s/i2s_nrfx_tdm.c @@ -15,6 +15,7 @@ #include #include #include + LOG_MODULE_REGISTER(tdm_nrfx, CONFIG_I2S_LOG_LEVEL); /* The application must provide buffers that are to be used in the next @@ -27,6 +28,17 @@ LOG_MODULE_REGISTER(tdm_nrfx, CONFIG_I2S_LOG_LEVEL); */ #define NRFX_TDM_STATUS_TRANSFER_STOPPED BIT(1) +#define NODE_AUDIOPLL DT_NODELABEL(audiopll) + +#if DT_NODE_HAS_STATUS_OKAY(NODE_AUDIOPLL) +static const struct device *audiopll = DEVICE_DT_GET(NODE_AUDIOPLL); +const struct nrf_clock_spec aclk_spec = { + .frequency = DT_PROP_OR(NODE_AUDIOPLL, frequency, 0), + .accuracy = 0, + .precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT, +}; +#endif + typedef struct { uint32_t *p_rx_buffer; uint32_t const *p_tx_buffer; @@ -75,7 +87,6 @@ struct tdm_drv_cfg { }; struct tdm_drv_data { - struct onoff_manager *clk_mgr; struct onoff_client clk_cli; struct stream_cfg tx; struct k_msgq tx_queue; @@ -94,6 +105,26 @@ struct tdm_drv_data { bool request_clock: 1; }; +static int audio_clock_request(struct tdm_drv_data *drv_data) +{ +#if DT_NODE_HAS_STATUS_OKAY(NODE_AUDIOPLL) + return nrf_clock_control_request(audiopll, &aclk_spec, &drv_data->clk_cli); +#else + (void)drv_data; + + return -ENOTSUP; +#endif +} + +static int audio_clock_release(void) +{ +#if DT_NODE_HAS_STATUS_OKAY(NODE_AUDIOPLL) + return nrf_clock_control_release(audiopll, &aclk_spec); +#else + return -ENOTSUP; +#endif +} + void tdm_irq_handler(const struct device *dev) { const struct tdm_drv_cfg *drv_cfg = dev->config; @@ -479,10 +510,9 @@ static int tdm_nrfx_configure(const struct device *dev, enum i2s_dir dir, nrfx_cfg.mck_setup = 0; if (nrfx_cfg.mode == NRF_TDM_MODE_MASTER) { uint32_t sck = tdm_cfg->word_size * tdm_cfg->frame_clk_freq * tdm_cfg->channels; - const uint32_t src_freq = - (drv_cfg->clk_src == ACLK) - ? DT_PROP_OR(DT_NODELABEL(clock), hfclkaudio_frequency, 0) - : drv_cfg->pclk_frequency; + const uint32_t src_freq = (drv_cfg->clk_src == ACLK) + ? DT_PROP_OR(NODE_AUDIOPLL, frequency, 0) + : drv_cfg->pclk_frequency; /* Unless the PCLK source is used, * it is required to request the proper clock to be running @@ -653,7 +683,7 @@ static int start_transfer(struct tdm_drv_data *drv_data) if (ret < 0) { tdm_uninit(drv_data); if (drv_data->request_clock) { - (void)onoff_release(drv_data->clk_mgr); + (void)audio_clock_release(); } if (initial_buffers.p_tx_buffer) { @@ -704,7 +734,7 @@ static void clock_started_callback(struct onoff_manager *mgr, struct onoff_clien */ if (drv_data->state == I2S_STATE_READY) { tdm_uninit(drv_data); - (void)onoff_release(drv_data->clk_mgr); + (void)audio_clock_release(); } else { (void)start_transfer(drv_data); } @@ -735,7 +765,7 @@ static int trigger_start(const struct device *dev) */ if (drv_data->request_clock) { sys_notify_init_callback(&drv_data->clk_cli.notify, clock_started_callback); - ret = onoff_request(drv_data->clk_mgr, &drv_data->clk_cli); + ret = audio_clock_request(drv_data); if (ret < 0) { tdm_uninit(drv_data); drv_data->state = I2S_STATE_READY; @@ -861,29 +891,6 @@ static int tdm_nrfx_trigger(const struct device *dev, enum i2s_dir dir, enum i2s } } -#if CONFIG_CLOCK_CONTROL_NRF -static void init_clock_manager(const struct device *dev) -{ - struct tdm_drv_data *drv_data = dev->data; - clock_control_subsys_t subsys; - -#if NRF_CLOCK_HAS_HFCLKAUDIO - const struct tdm_drv_cfg *drv_cfg = dev->config; - - if (drv_cfg->clk_src == ACLK) { - subsys = CLOCK_CONTROL_NRF_SUBSYS_HFAUDIO; - } else { - subsys = CLOCK_CONTROL_NRF_SUBSYS_HF; - } -#else - subsys = CLOCK_CONTROL_NRF_SUBSYS_HF; -#endif - - drv_data->clk_mgr = z_nrf_clock_control_get_onoff(subsys); - __ASSERT_NO_MSG(drv_data->clk_mgr != NULL); -} -#endif /* CONFIG_CLOCK_CONTROL_NRF */ - static void data_handler(const struct device *dev, const tdm_buffers_t *released, uint32_t status) { struct tdm_drv_data *drv_data = dev->data; @@ -922,7 +929,7 @@ static void data_handler(const struct device *dev, const tdm_buffers_t *released } tdm_uninit(drv_data); if (drv_data->request_clock) { - (void)onoff_release(drv_data->clk_mgr); + (void)audio_clock_release(); } } @@ -1039,7 +1046,6 @@ static int data_init(const struct device *dev) return err; } drv_data->drv_cfg = drv_cfg; - IF_ENABLED(CONFIG_CLOCK_CONTROL_NRF, (init_clock_manager(dev);)) return err; } @@ -1094,7 +1100,8 @@ static const struct i2s_driver_api tdm_nrf_drv_api = { sizeof(struct tdm_buf), ARRAY_SIZE(rx_msgs##idx)); \ return 0; \ } \ - BUILD_ASSERT(TDM_CLK_SRC(idx) != ACLK, "Clock source ACLK is currently not supported. "); \ + BUILD_ASSERT(TDM_CLK_SRC(idx) != ACLK || DT_NODE_HAS_STATUS_OKAY(NODE_AUDIOPLL), \ + "Clock source ACLK requires the audiopll node."); \ DEVICE_DT_DEFINE(TDM(idx), tdm_nrfx_init##idx, NULL, &tdm_nrfx_data##idx, \ &tdm_nrfx_cfg##idx, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, \ &tdm_nrf_drv_api); diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index d2834504eb2..e56922d083e 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -42,5 +42,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MAX32 pinctrl_max32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCMI pinctrl_imx_scmi.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_MEC5 pinctrl_mchp_mec5.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_AFIO pinctrl_wch_afio.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_SY1XX pinctrl_sy1xx.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_REALTEK_RTS5912 pinctrl_realtek_rts5912.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index d8621e7ad9e..299372eea7f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -69,6 +69,8 @@ source "drivers/pinctrl/Kconfig.zynqmp" source "drivers/pinctrl/Kconfig.max32" source "drivers/pinctrl/Kconfig.mec5" source "drivers/pinctrl/Kconfig.wch_afio" +source "drivers/pinctrl/Kconfig.sy1xx" +source "drivers/pinctrl/Kconfig.realtek_rts5912" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.realtek_rts5912 b/drivers/pinctrl/Kconfig.realtek_rts5912 new file mode 100644 index 00000000000..12b926b3f52 --- /dev/null +++ b/drivers/pinctrl/Kconfig.realtek_rts5912 @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config PINCTRL_REALTEK_RTS5912 + bool "Pin controller driver for REALTEK RTS MCUs" + default y if DT_HAS_REALTEK_RTS5912_PINCTRL_ENABLED + help + Enable pin controller driver for REALTEK RTS MCUs diff --git a/drivers/pinctrl/Kconfig.sy1xx b/drivers/pinctrl/Kconfig.sy1xx new file mode 100644 index 00000000000..857920bf9d8 --- /dev/null +++ b/drivers/pinctrl/Kconfig.sy1xx @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +config PINCTRL_SY1XX + bool "Sensry sy1xx pin controller driver" + default y + depends on DT_HAS_SENSRY_SY1XX_PINCTRL_ENABLED + help + Sensry pin controller driver is used on sy1xx SoC series diff --git a/drivers/pinctrl/pinctrl_realtek_rts5912.c b/drivers/pinctrl/pinctrl_realtek_rts5912.c new file mode 100644 index 00000000000..5764a73f086 --- /dev/null +++ b/drivers/pinctrl/pinctrl_realtek_rts5912.c @@ -0,0 +1,38 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#define DT_DRV_COMPAT realtek_rts5912_pinctrl + +#include +#include + +#include + +#define REALTEK_RTS5912_PINMUX_GET_GPIO_PIN(n) \ + (((((n) >> REALTEK_RTS5912_GPIO_LOW_POS) & REALTEK_RTS5912_GPIO_LOW_MSK)) | \ + (((((n) >> REALTEK_RTS5912_GPIO_HIGH_POS) & REALTEK_RTS5912_GPIO_HIGH_MSK)) << 5)) + +#define PURE_PINMUX_MASK (GENMASK(31, 24) | GENMASK(17, 8) | GENMASK(2, 0)) +#define REALTEK_RTS5912_GET_PURE_PINMUX(n) (n & PURE_PINMUX_MASK) + +static volatile GPIO_Type *pinctrl_base = + (volatile GPIO_Type *)(DT_REG_ADDR(DT_NODELABEL(pinctrl))); + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + uint32_t pin, pinmux, func; + + for (uint8_t i = 0U; i < pin_cnt; i++) { + pinmux = (uint32_t)pins[i]; + pin = REALTEK_RTS5912_PINMUX_GET_GPIO_PIN(pinmux); + func = REALTEK_RTS5912_GET_PURE_PINMUX(pinmux); + pinctrl_base->GCR[pin] = func; + } + + return 0; +} diff --git a/drivers/pinctrl/pinctrl_sy1xx.c b/drivers/pinctrl/pinctrl_sy1xx.c new file mode 100644 index 00000000000..1343ba2c987 --- /dev/null +++ b/drivers/pinctrl/pinctrl_sy1xx.c @@ -0,0 +1,59 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#define DT_DRV_COMPAT sensry_sy1xx_pinctrl + +#include +#include +#include + +#include + +static uint32_t pinctrl0_base_addr = DT_REG_ADDR(DT_NODELABEL(pinctrl)); +static uint32_t pinctrl0_base_mask = DT_REG_SIZE(DT_NODELABEL(pinctrl)) - 1; + +/** + * @brief Configure a pin. + * + * @param pin The pin to configure. + */ +static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) +{ + uint32_t addr = (pin->addr & pinctrl0_base_mask) | pinctrl0_base_addr; + + switch (pin->iro) { + case 0: + case 8: + case 16: + case 24: + /* fall through */ + break; + default: + /* invalid inter address offset */ + return -EINVAL; + } + + uint32_t reg = ~(0xFFUL << pin->iro) & sys_read32(addr); + + reg |= FIELD_PREP((0xFFUL << pin->iro), pin->cfg); + sys_write32(reg, addr); + + return 0; +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + + for (uint8_t i = 0U; i < pin_cnt; i++) { + int ret = pinctrl_configure_pin(pins++); + + if (ret < 0) { + return ret; + } + } + + return 0; +} diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index dcae664944d..c29700ac858 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -61,6 +61,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_RCAR uart_rcar.c) zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RA uart_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCIF uart_renesas_rz_scif.c) zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO_PIO uart_rpi_pico_pio.c) +zephyr_library_sources_ifdef(CONFIG_UART_RTS5912 uart_realtek_rts5912.c) zephyr_library_sources_ifdef(CONFIG_UART_RTT_DRIVER uart_rtt.c) zephyr_library_sources_ifdef(CONFIG_UART_RV32M1_LPUART uart_rv32m1_lpuart.c) zephyr_library_sources_ifdef(CONFIG_UART_RZT2M uart_rzt2m.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5c84620990f..baf3f7e4121 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -230,4 +230,6 @@ source "drivers/serial/Kconfig.si32" source "drivers/serial/Kconfig.wch_usart" +source "drivers/serial/Kconfig.realtek_rts5912" + endif # SERIAL diff --git a/drivers/serial/Kconfig.realtek_rts5912 b/drivers/serial/Kconfig.realtek_rts5912 new file mode 100644 index 00000000000..bafb518aa43 --- /dev/null +++ b/drivers/serial/Kconfig.realtek_rts5912 @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config UART_RTS5912 + bool "UART driver for Realtek RTS5912 EC" + default y if DT_HAS_REALTEK_RTS5912_UART_ENABLED + select PINCTRL + select CLOCK_CONTROL + help + This option enables the RTS5912 UART wrapper driver. + +config UART_RTS5912_INIT_PRIORITY + int "RTS5912 UART wrapper init priority" + default 49 + depends on UART_RTS5912 + help + Initialization priority for Realtek RTS5912 UART wrapper driver. diff --git a/drivers/serial/uart_realtek_rts5912.c b/drivers/serial/uart_realtek_rts5912.c new file mode 100644 index 00000000000..c57c3774514 --- /dev/null +++ b/drivers/serial/uart_realtek_rts5912.c @@ -0,0 +1,75 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#define DT_DRV_COMPAT realtek_rts5912_uart + +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(uart_rts5912, CONFIG_UART_LOG_LEVEL); + +BUILD_ASSERT(CONFIG_UART_RTS5912_INIT_PRIORITY < CONFIG_SERIAL_INIT_PRIORITY, + "The uart_realtek_rts5912 driver must be initialized before the uart_ns16550 driver"); + +/* device config */ +struct uart_rts5912_device_config { + const struct pinctrl_dev_config *pcfg; + const struct device *clk_dev; + struct rts5912_sccon_subsys sccon_cfg; +}; + +/** Device data structure */ +struct uart_rts5912_dev_data { +}; + +static int rts5912_uart_init(const struct device *dev) +{ + const struct uart_rts5912_device_config *const dev_cfg = dev->config; + int rc; + + if (!device_is_ready(dev_cfg->clk_dev)) { + return -ENODEV; + } + + rc = clock_control_on(dev_cfg->clk_dev, (clock_control_subsys_t)&dev_cfg->sccon_cfg); + if (rc != 0) { + return rc; + } + + rc = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (rc != 0) { + return rc; + } + + return 0; +} + +#define UART_RTS5912_DEVICE_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ + \ + static const struct uart_rts5912_device_config uart_rts5912_dev_cfg_##n = { \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .sccon_cfg = \ + { \ + .clk_grp = DT_INST_CLOCKS_CELL_BY_NAME(n, uart##n, clk_grp), \ + .clk_idx = DT_INST_CLOCKS_CELL_BY_NAME(n, uart##n, clk_idx), \ + }, \ + }; \ + \ + static struct uart_rts5912_dev_data uart_rts5912_dev_data_##n; \ + \ + DEVICE_DT_INST_DEFINE(n, &rts5912_uart_init, NULL, &uart_rts5912_dev_data_##n, \ + &uart_rts5912_dev_cfg_##n, PRE_KERNEL_1, \ + CONFIG_UART_RTS5912_INIT_PRIORITY, NULL); + +DT_INST_FOREACH_STATUS_OKAY(UART_RTS5912_DEVICE_INIT) diff --git a/drivers/timer/CMakeLists.txt b/drivers/timer/CMakeLists.txt index 2b837fba480..51b0e552f4a 100644 --- a/drivers/timer/CMakeLists.txt +++ b/drivers/timer/CMakeLists.txt @@ -33,6 +33,7 @@ zephyr_library_sources_ifdef(CONFIG_NRF_RTC_TIMER nrf_rtc_timer.c) zephyr_library_sources_ifdef(CONFIG_RCAR_CMT_TIMER rcar_cmt_timer.c) zephyr_library_sources_ifdef(CONFIG_RISCV_MACHINE_TIMER riscv_machine_timer.c) zephyr_library_sources_ifdef(CONFIG_RV32M1_LPTMR_TIMER rv32m1_lptmr_timer.c) +zephyr_library_sources_ifdef(CONFIG_REALTEK_RTS5912_RTMR realtek_rts5912_rtmr.c) zephyr_library_sources_ifdef(CONFIG_SAM0_RTC_TIMER sam0_rtc_timer.c) zephyr_library_sources_ifdef(CONFIG_SILABS_SLEEPTIMER_TIMER silabs_sleeptimer_timer.c) zephyr_library_sources_ifdef(CONFIG_STM32_LPTIM_TIMER stm32_lptim_timer.c) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index a43e666349c..f017589a60e 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -91,6 +91,7 @@ source "drivers/timer/Kconfig.nrf_xrtc" source "drivers/timer/Kconfig.rcar_cmt" source "drivers/timer/Kconfig.riscv_machine" source "drivers/timer/Kconfig.rv32m1_lptmr" +source "drivers/timer/Kconfig.realtek_rts5912_rtmr" source "drivers/timer/Kconfig.sam0_rtc" source "drivers/timer/Kconfig.silabs" source "drivers/timer/Kconfig.smartbond" diff --git a/drivers/timer/Kconfig.realtek_rts5912_rtmr b/drivers/timer/Kconfig.realtek_rts5912_rtmr new file mode 100644 index 00000000000..560ea7a7059 --- /dev/null +++ b/drivers/timer/Kconfig.realtek_rts5912_rtmr @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config REALTEK_RTS5912_RTMR + bool "Realtek RTS5912 RTOS Timer" + default y if DT_HAS_REALTEK_RTS5912_RTMR_ENABLED + select TICKLESS_CAPABLE + select SYSTEM_TIMER_HAS_DISABLE_SUPPORT + help + This module implements a kernel device driver for the Realtek + RTS5912 series RTOS timer. diff --git a/drivers/timer/realtek_rts5912_rtmr.c b/drivers/timer/realtek_rts5912_rtmr.c new file mode 100644 index 00000000000..3476e730999 --- /dev/null +++ b/drivers/timer/realtek_rts5912_rtmr.c @@ -0,0 +1,251 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#define DT_DRV_COMPAT realtek_rts5912_rtmr + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define RTS5912_SCCON_REG_BASE ((SYSTEM_Type *)(DT_REG_ADDR(DT_NODELABEL(sccon)))) + +#define CYCLES_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) + +BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, + "Realtek RTOS timer is not supported multiple instances"); + +#define RTMR_REG ((RTOSTMR_Type *)DT_INST_REG_ADDR(0)) + +#define SLWTMR_REG \ + ((RTOSTMR_Type *)(DT_REG_ADDR(DT_COMPAT_GET_ANY_STATUS_OKAY(realtek_rts5912_slwtimer)))) + +#define SSCON_REG ((SYSTEM_Type *)(DT_REG_ADDR(DT_NODELABEL(sccon)))) + +#define RTMR_COUNTER_MAX 0x0ffffffful +#define RTMR_COUNTER_MSK 0x0ffffffful +#define RTMR_TIMER_STOPPED 0xf0000000ul + +#define MAX_TICKS ((k_ticks_t)(RTMR_COUNTER_MAX / CYCLES_PER_TICK) - 1) + +#define RTMR_ADJUST_LIMIT 2 +#define RTMR_ADJUST_CYCLES 1 + +static struct k_spinlock lock; +static uint32_t accumulated_cycles; +static uint32_t previous_cnt; /* Record the counter set into RTMR */ +static uint32_t last_announcement; /* Record the last tick announced to system */ + +static void rtmr_restart(uint32_t counter) +{ + RTMR_REG->CTRL = 0ul; + RTMR_REG->LDCNT = counter; + RTMR_REG->CTRL = RTOSTMR_CTRL_INTEN_Msk | RTOSTMR_CTRL_EN_Msk; +} + +static uint32_t rtmr_get_counter(void) +{ + uint32_t counter = RTMR_REG->CNT; + + if ((counter == 0) && (RTMR_REG->CTRL & RTOSTMR_CTRL_EN_Msk)) { + counter = previous_cnt; + } + + return counter; +} + +static void rtmr_isr(const void *arg) +{ + ARG_UNUSED(arg); + + uint32_t cycles; + int32_t ticks; + + k_spinlock_key_t key = k_spin_lock(&lock); + + rtmr_restart(RTMR_COUNTER_MAX * CYCLES_PER_TICK); + + cycles = previous_cnt; + previous_cnt = RTMR_COUNTER_MAX * CYCLES_PER_TICK; + + accumulated_cycles += cycles; + + if (accumulated_cycles > RTMR_COUNTER_MSK) { + accumulated_cycles &= RTMR_COUNTER_MSK; + } + + ticks = accumulated_cycles - last_announcement; + ticks &= RTMR_COUNTER_MSK; + ticks /= CYCLES_PER_TICK; + + last_announcement = accumulated_cycles; + + k_spin_unlock(&lock, key); + + sys_clock_announce(ticks); +} + +void sys_clock_set_timeout(int32_t ticks, bool idle) +{ + ARG_UNUSED(idle); + + uint32_t cur_cnt, temp; + int full_ticks; + uint32_t full_cycles; + uint32_t partial_cycles; + + if (idle && (ticks == K_TICKS_FOREVER)) { + RTMR_REG->CTRL = 0U; + previous_cnt = RTMR_TIMER_STOPPED; + return; + } + + if (ticks < 1) { + full_ticks = 0; + } else if ((ticks == K_TICKS_FOREVER) || (ticks > MAX_TICKS)) { + full_ticks = MAX_TICKS - 1; + } else { + full_ticks = ticks - 1; + } + + full_cycles = full_ticks * CYCLES_PER_TICK; + + k_spinlock_key_t key = k_spin_lock(&lock); + + cur_cnt = rtmr_get_counter(); + + RTMR_REG->CTRL = 0U; + + temp = accumulated_cycles; + temp += previous_cnt - cur_cnt; + temp &= RTMR_COUNTER_MSK; + accumulated_cycles = temp; + + partial_cycles = CYCLES_PER_TICK - (accumulated_cycles % CYCLES_PER_TICK); + previous_cnt = full_cycles + partial_cycles; + + temp = previous_cnt; + if (temp > RTMR_ADJUST_LIMIT) { + temp -= RTMR_ADJUST_CYCLES; + } + rtmr_restart(temp); + + k_spin_unlock(&lock, key); +} + +uint32_t sys_clock_elapsed(void) +{ + uint32_t cur_cnt; + uint32_t ticks; + int32_t elapsed; + + k_spinlock_key_t key = k_spin_lock(&lock); + + cur_cnt = rtmr_get_counter(); + + elapsed = (int32_t)accumulated_cycles - (int32_t)last_announcement; + if (elapsed < 0) { + elapsed = -1 * elapsed; + } + ticks = (uint32_t)elapsed; + ticks += previous_cnt - cur_cnt; + ticks /= CYCLES_PER_TICK; + ticks &= RTMR_COUNTER_MSK; + + k_spin_unlock(&lock, key); + + return ticks; +} + +void sys_clock_idle_exit(void) +{ + if (previous_cnt == RTMR_TIMER_STOPPED) { + previous_cnt = CYCLES_PER_TICK; + rtmr_restart(previous_cnt); + } +} + +void sys_clock_disable(void) +{ + /* Disable RTMR. */ + RTMR_REG->CTRL = 0ul; +} + +uint32_t sys_clock_cycle_get_32(void) +{ + uint32_t ret; + uint32_t cur_cnt; + + k_spinlock_key_t key = k_spin_lock(&lock); + + cur_cnt = rtmr_get_counter(); + ret = (accumulated_cycles + (previous_cnt - cur_cnt)) & RTMR_COUNTER_MSK; + + k_spin_unlock(&lock, key); + + return ret; +} + +#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT + +void arch_busy_wait(uint32_t n_usec) +{ + if (n_usec == 0) { + return; + } + + uint32_t start = SLWTMR_REG->CNT; + + for (;;) { + uint32_t curr = SLWTMR_REG->CNT; + + if ((start - curr) >= n_usec) { + break; + } + } +} +#endif + +static int sys_clock_driver_init(void) +{ + /* Enable RTMR clock power */ + + SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE; + + sys_reg->PERICLKPWR1 |= SYSTEM_PERICLKPWR1_RTMRCLKPWR_Msk; + + /* Enable RTMR interrupt. */ + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), rtmr_isr, 0, 0); + irq_enable(DT_INST_IRQN(0)); + + /* Trigger RTMR and wait it start to counting */ + previous_cnt = RTMR_COUNTER_MAX; + + rtmr_restart(previous_cnt); + while (RTMR_REG->CNT == 0) { + }; + +#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT + /* Enable SLWTMR0 clock power */ + SSCON_REG->PERICLKPWR1 |= BIT(SYSTEM_PERICLKPWR1_SLWTMR0CLKPWR_Pos); + + /* Enable SLWTMR0 */ + SLWTMR_REG->LDCNT = UINT32_MAX; + SLWTMR_REG->CTRL = RTOSTMR_CTRL_MDSEL_Msk | RTOSTMR_CTRL_EN_Msk; +#endif + + return 0; +} + +SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY); diff --git a/dts/arm/realtek/ec/rts5912-pinctrl.dtsi b/dts/arm/realtek/ec/rts5912-pinctrl.dtsi new file mode 100644 index 00000000000..3ac81a34862 --- /dev/null +++ b/dts/arm/realtek/ec/rts5912-pinctrl.dtsi @@ -0,0 +1,645 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * + */ + +#include + +&pinctrl +{ + /* ADC PINCTRL SETTING START */ + /omit-if-no-ref/ adc0_gpio074: adc0_gpio074 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc1_gpio075: adc1_gpio075 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc2_gpio076: adc2_gpio076 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc3_gpio077: adc3_gpio077 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ adc4_gpio078: adc4_gpio078 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc5_gpio079: adc5_gpio079 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc6_gpio080: adc6_gpio080 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc7_gpio081: adc7_gpio081 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ adc8_gpio082: adc8_gpio082 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc9_gpio054: adc9_gpio054 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc10_gpio098: adc10_gpio098 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ adc11_gpio024: adc11_gpio024 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* ADC PINCTRL SETTING END */ + /* ESPI PINCTRL SETTING START */ + /omit-if-no-ref/ espi_alert_gpio003: espi_alert_gpio003 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ espi_cs_gpio004: espi_cs_gpio004 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ espi_io3_gpio005: espi_io3_gpio005 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ espi_io2_gpio006: espi_io2_gpio006 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ espi_io1_gpio007: espi_io1_gpio007 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ espi_io0_gpio008: espi_io0_gpio008 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ espi_clk_gpio009: espi_clk_gpio009 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ espi_reset_gpio020: espi_reset_gpio020 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* ESPI PINCTRL SETTING END */ + /* I2C PINCTRL SETTING START */ + /omit-if-no-ref/ i2c00_clk_gpio094: i2c00_clk_gpio094 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c00_data_gpio095: i2c00_data_gpio095 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c00_clk_gpio115: i2c00_clk_gpio115 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c00_data_gpio131: i2c00_data_gpio131 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c01_clk_gpio118: i2c01_clk_gpio118 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c01_data_gpio119: i2c01_data_gpio119 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c02_clk_gpio014: i2c02_clk_gpio014 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c02_data_gpio121: i2c02_data_gpio121 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c03_clk_gpio100: i2c03_clk_gpio100 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c03_data_gpio101: i2c03_data_gpio101 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c04_clk_gpio017: i2c04_clk_gpio017 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c04_data_gpio018: i2c04_data_gpio018 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c05_clk_gpio027: i2c05_clk_gpio027 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c05_data_gpio028: i2c05_data_gpio028 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c05_clk_gpio128: i2c05_clk_gpio128 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c05_data_gpio130: i2c05_data_gpio130 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c06_clk_gpio036: i2c06_clk_gpio036 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c06_data_gpio037: i2c06_data_gpio037 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ i2c07_clk_gpio038: i2c07_clk_gpio038 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ i2c07_data_gpio039: i2c07_data_gpio039 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* I2C PINCTRL SETTING END */ + /* JTAG PINCTRL SETTING START */ + /omit-if-no-ref/ jtag_tdi_gpio87: jtag_tdi_gpio87 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ jtag_tdo_gpio88: jtag_tdo_gpio88 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ jtag_rst_gpio89: jtag_rst_gpio89 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ jtag_clk_gpio90: jtag_clk_gpio90 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ jtag_tms_gpio91: jtag_tms_gpio91 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* JTAG PINCTRL SETTING END */ + /* KSM PINCTRL SETTING START */ + /* KSO PINCTRL SETTING START */ + /omit-if-no-ref/ kso0_gpio041: kso0_gpio041 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso1_gpio042: kso1_gpio042 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso2_gpio043: kso2_gpio043 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso3_gpio044: kso3_gpio044 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ kso4_gpio045: kso4_gpio045 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso5_gpio046: kso5_gpio046 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso6_gpio047: kso6_gpio047 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso7_gpio048: kso7_gpio048 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ kso8_gpio049: kso8_gpio049 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso9_gpio050: kso9_gpio050 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso10_gpio051: kso10_gpio051 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso11_gpio055: kso11_gpio055 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ kso12_gpio056: kso12_gpio056 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso13_gpio057: kso13_gpio057 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso14_gpio058: kso14_gpio058 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso15_gpio059: kso15_gpio059 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ kso16_gpio060: kso16_gpio060 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso17_gpio061: kso17_gpio061 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso18_gpio092: kso18_gpio092 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ kso19_gpio093: kso19_gpio093 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* KSO PINCTRL SETTING END */ + /* KSI PINCTRL SETTING START */ + /omit-if-no-ref/ ksi0_gpio064: ksi0_gpio064 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ksi1_gpio065: ksi1_gpio065 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ksi2_gpio066: ksi2_gpio066 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ksi3_gpio067: ksi3_gpio067 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ ksi4_gpio068: ksi4_gpio068 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ksi5_gpio069: ksi5_gpio069 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ksi6_gpio070: ksi6_gpio070 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ksi7_gpio071: ksi7_gpio071 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ ksi8_gpio054: ksi8_gpio054 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ksi9_gpio098: ksi9_gpio098 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* KSO PINCTRL SETTING END */ + /* KSM PINCTRL SETTING END */ + /* PS2 PINCTRL SETTING START */ + /omit-if-no-ref/ ps2clk0_gpio092: ps2clk0_gpio092 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ps2data0_gpio093: ps2data0_gpio093 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ps2clk0_gpio096: ps2clk0_gpio096 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ ps2data0_gpio097: ps2data0_gpio097 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* PS2 PINCTRL SETTING END */ + /* PWM PINCTRL SETTING START */ + /omit-if-no-ref/ pwm0_gpio022: pwm0_gpio022 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm1_gpio023: pwm1_gpio023 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm2_gpio025: pwm2_gpio025 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm3_gpio026: pwm3_gpio026 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ pwm4_gpio027: pwm4_gpio027 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm5_gpio028: pwm5_gpio028 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm6_gpio029: pwm6_gpio029 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm7_gpio031: pwm7_gpio031 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ pwm8_gpio032: pwm8_gpio032 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm9_gpio033: pwm9_gpio033 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm10_gpio034: pwm10_gpio034 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ pwm11_gpio035: pwm11_gpio035 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* PWM PINCTRL SETTING END */ + /* SPIC PINCTRL SETTING START */ + /omit-if-no-ref/ spic_cs_gpio107: spic_cs_gpio107 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ spic_si_gpio108: spic_si_gpio108 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ spic_so_gpio109: spic_so_gpio109 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ spic_clk_gpio111: spic_clk_gpio111 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ spic_io2_gpio124: spic_io2_gpio124 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ spic_io3_gpio122: spic_io3_gpio122 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* SPIC PINCTRL SETTING END */ + /* TACHO PINCTRL SETTING START */ + /omit-if-no-ref/ tacho0_gpio052: tacho0_gpio052 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ tacho1_gpio053: tacho1_gpio053 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ tacho1_gpio086: tacho1_gpio086 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ tacho2_gpio085: tacho2_gpio085 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ tacho3_gpio083: tacho3_gpio083 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ tacho3_gpio084: tacho3_gpio084 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* TACHO PINCTRL SETTING END */ + /* UART PINCTRL SETTING START */ + /omit-if-no-ref/ uart_rx_gpio113: uart0_rx_gpio113 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_tx_gpio114: uart0_tx_gpio114 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ uart_rx_gpio014: uart1_rx_gpio014 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_tx_gpio015: uart1_tx_gpio015 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ uart_rx_gpio100: uart_rx_gpio100 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_tx_gpio101: uart_tx_gpio101 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ uart_dtr_gpio039: uart_dtr_gpio039 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_rts_gpio040: uart_rts_gpio040 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_dcd_gpio079: uart_dcd_gpio079 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_dsr_gpio080: uart_dsr_gpio080 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_cts_gpio081: uart_cts_gpio081 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_ri_gpio088: uart_ri_gpio088 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /omit-if-no-ref/ uart_dtr_gpio124: uart_dtr_gpio124 { + pinmux = ; + input-enable; + input-schmitt-enable; + }; + /* UART PINCTRL SETTING END */ +}; diff --git a/dts/arm/realtek/ec/rts5912.dtsi b/dts/arm/realtek/ec/rts5912.dtsi new file mode 100644 index 00000000000..aa994898109 --- /dev/null +++ b/dts/arm/realtek/ec/rts5912.dtsi @@ -0,0 +1,252 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + cpu-power-states = <&idle &suspend_to_ram>; + }; + + power-states { + idle: idle { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <100000>; + }; + + suspend_to_ram: suspend_to_ram { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-ram"; + min-residency-us = <250000>; + }; + }; + }; + + flash0: flash@20000400 { + reg = <0x20000400 0x4FC00>; + }; + + sram0: memory@20050000 { + compatible = "mmio-sram"; + reg = <0x20050000 0x8000>; + }; + + clocks { + rc25m: rc25m { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + + pll: pll { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&nvic>; + ranges; + + sccon: clock-controller@40020000 { + compatible = "realtek,rts5912-sccon"; + reg = <0x40020000 0xf0>; + #clock-cells = <2>; + clocks = <&rc25m>, <&pll>; + clock-names = "rc25m", "pll"; + }; + + slwtmr0: slwtmr0@4000c200 { + compatible = "realtek,rts5912-slwtimer"; + reg = <0x4000c200 0x10>; + interrupts = <202 0>; + clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_SLWTMR0_CLKPWR>; + clock-names = "slwtmr"; + max-value = <0xFFFFFFFF>; + clock-frequency = <1000000>; + prescaler = <0>; + status = "okay"; + }; + + rtmr: rtmr@4000c500 { + compatible = "realtek,rts5912-rtmr"; + reg = <0x4000c500 0x10>; + interrupts = <204 0>; + status = "okay"; + }; + + uart0: uart@40010100 { + compatible = "ns16550"; + reg = <0x40010100 0x100>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupts = <191 0>; + status = "disabled"; + }; + + uart0_wrapper: uart_wrapper@40010200 { + compatible = "realtek,rts5912-uart"; + reg = <0x40010200 0x0020>; + port = <0>; + clocks = <&sccon RTS5912_SCCON_UART UART0_CLKPWR>; + clock-names = "uart0"; + status = "disabled"; + }; + + pinctrl: pin-controller@40090000 { + compatible = "realtek,rts5912-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40090000 0x300>; + + /* GPIO0-GPIO15 */ + gpioa: gpio@40090000 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40090000 0x40>; + ngpios = <16>; + interrupts = <0 0 1 0 2 0 3 0 + 4 0 5 0 6 0 7 0 + 8 0 9 0 10 0 11 0 + 12 0 13 0 14 0 15 0>; + }; + + /* GPIO16-GPIO31 */ + gpiob: gpio@40090040 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40090040 0x40>; + ngpios = <16>; + interrupts = <16 0 17 0 18 0 19 0 + 20 0 21 0 22 0 23 0 + 24 0 25 0 26 0 27 0 + 28 0 29 0 30 0 31 0>; + }; + + /* GPIO32-GPIO47 */ + gpioc: gpio@40090080 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40090080 0x40>; + ngpios = <16>; + interrupts = <32 0 33 0 34 0 35 0 + 36 0 37 0 38 0 39 0 + 40 0 41 0 42 0 43 0 + 44 0 45 0 46 0 47 0>; + }; + + /* GPIO48-GPIO63 */ + gpiod: gpio@400900c0 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x400900c0 0x40>; + ngpios = <16>; + interrupts = <48 0 49 0 50 0 51 0 + 52 0 53 0 54 0 55 0 + 56 0 57 0 58 0 59 0 + 60 0 61 0 62 0 63 0>; + }; + + /* GPIO64-GPIO79 */ + gpioe: gpio@40090100 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40090100 0x40>; + ngpios = <16>; + interrupts = <64 0 65 0 66 0 67 0 + 68 0 69 0 70 0 71 0 + 72 0 73 0 74 0 75 0 + 76 0 77 0 78 0 79 0>; + }; + + /* GPIO80-GPIO95 */ + gpiof: gpio@40090140 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40090140 0x40>; + ngpios = <16>; + interrupts = <80 0 81 0 82 0 83 0 + 84 0 85 0 86 0 87 0 + 88 0 89 0 90 0 91 0 + 92 0 93 0 94 0 95 0>; + }; + + /* GPIO96-GPIO111 */ + gpiog: gpio@40090180 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40090180 0x40>; + ngpios = <16>; + interrupts = <96 0 97 0 98 0 99 0 + 100 0 101 0 102 0 103 0 + 104 0 105 0 106 0 107 0 + 108 0 109 0 110 0 111 0>; + }; + + /* GPIO112-GPIO127 */ + gpioh: gpio@400901c0 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x400901c0 0x40>; + ngpios = <16>; + interrupts = <112 0 113 0 114 0 115 0 + 116 0 117 0 118 0 119 0 + 120 0 121 0 122 0 123 0 + 124 0 125 0 126 0 127 0>; + }; + + /* GPIO128-GPIO131 */ + gpioi: gpio@40090200 { + compatible = "realtek,rts5912-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40090200 0x10>; + ngpios = <4>; + interrupts = <128 0 129 0 130 0 131 0 + 132 0 133 0 134 0 135 0 + 136 0 137 0 138 0 139 0 + 140 0 141 0 142 0 143 0>; + }; + }; + }; + + swj_port: swj-port { + compatible = "swj-connector"; + pinctrl-0 = <&jtag_tdi_gpio87 &jtag_tdo_gpio88 &jtag_rst_gpio89 + &jtag_clk_gpio90 &jtag_tms_gpio91>; + pinctrl-names = "default"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; + +&systick { + status = "disabled"; +}; diff --git a/dts/bindings/clock/nordic,nrfs-audiopll.yaml b/dts/bindings/clock/nordic,nrfs-audiopll.yaml new file mode 100644 index 00000000000..a305b1c8088 --- /dev/null +++ b/dts/bindings/clock/nordic,nrfs-audiopll.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic NRFS AudioPLL clock + +compatible: "nordic,nrfs-audiopll" + +include: base.yaml + +properties: + frequency: + type: int + required: true + description: | + Initial frequency in Hertz. + + See zephyr/include/zephyr/dt-bindings/nrfs_audiopll.h for + predefined frequencies. diff --git a/dts/bindings/clock/realtek,rts5912-sccon.yaml b/dts/bindings/clock/realtek,rts5912-sccon.yaml new file mode 100644 index 00000000000..594c0095235 --- /dev/null +++ b/dts/bindings/clock/realtek,rts5912-sccon.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +description: Realtek RTS5912 System Clock Controller (SCCON) + +compatible: "realtek,rts5912-sccon" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 2 + +clock-cells: + - clk-grp + - clk-idx diff --git a/dts/bindings/gpio/realtek,rts5912-gpio.yaml b/dts/bindings/gpio/realtek,rts5912-gpio.yaml new file mode 100644 index 00000000000..4bf4d44e42f --- /dev/null +++ b/dts/bindings/gpio/realtek,rts5912-gpio.yaml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +description: Realtek RTS5912 GPIO + +compatible: "realtek,rts5912-gpio" + +include: [gpio-controller.yaml, base.yaml] + +properties: + reg: + required: true + +gpio-cells: + - pin + - flags diff --git a/dts/bindings/pinctrl/realtek,rts5912-pinctrl.yaml b/dts/bindings/pinctrl/realtek,rts5912-pinctrl.yaml new file mode 100644 index 00000000000..c5b00ae822a --- /dev/null +++ b/dts/bindings/pinctrl/realtek,rts5912-pinctrl.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +description: | + This binding gives a base representation of the pins configuration + +compatible: "realtek,rts5912-pinctrl" + +include: [base.yaml, pinctrl-device.yaml, pincfg-node.yaml] + +properties: + reg: + required: true + +child-binding: + description: | + This binding gives a base representation of the pins configuration + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-pull-down + - bias-pull-up + - drive-push-pull + - drive-open-drain + - input-enable + - output-enable + - output-high + - output-low + - input-schmitt-enable + + properties: + pinmux: + type: int + required: true + description: Pinmux selection + drive-strength: + type: string + enum: + - "low" + - "high" + description: | + "low" — 4mA/8mA drive strength + "high" — 8mA/12mA drive strength + slew-rate: + type: string + enum: + - "fast" + - "low" + description: | + "fast" — Fast Frequency Slew Rate + "slow" — Slow Frequency Slew Rate diff --git a/dts/bindings/pinctrl/sensry,sy1xx-pinctrl.yaml b/dts/bindings/pinctrl/sensry,sy1xx-pinctrl.yaml new file mode 100644 index 00000000000..776f561f4c4 --- /dev/null +++ b/dts/bindings/pinctrl/sensry,sy1xx-pinctrl.yaml @@ -0,0 +1,74 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +description: | + The sensry SY1xx pin controller is a single node responsible for controlling + pin configuration, such as pull-up, pull-down, tri-state, ... + + The node has the 'pinctrl0' node label set in your SoC's devicetree, + so you can modify it like this: + + &pinctrl0 { + /* your modifications go here */ + }; + + For example: + &pinctrl0 { + + /* UART0 */ + uart0_tx: uart0_tx { + pinmux = ; + }; + + uart0_rx: uart0_rx { + pinmux = ; + input-enable; + }; + } + + Then define the uart: + &uart0 { + pinctrl-0 = <&uart0_tx &uart0_rx>; + pinctrl-names = "default"; + }; + + Every pin configuration will be configured in a 32bit register. The configuration + itself is 8bit wide. So we have a number of 4 pin configurations per 32bit register. + + The pinmux describes the registers address and the offset [0, 8, 16, 24] for + the individual configuration. + + Allowed modifiers for each pin are: + - bias-high-impedance + - bias-pull-down + - bias-pull-up + - input-enable + - input-schmitt-enable + +compatible: "sensry,sy1xx-pinctrl" + +include: base.yaml + +properties: + reg: + required: true + +child-binding: + description: Each child node defines the configuration of a particular state. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-high-impedance + - bias-pull-down + - bias-pull-up + - input-enable + - input-schmitt-enable + + properties: + pinmux: + required: true + type: array + description: | + Pin mux selection. See the SOC level pinctrl header + for a defined list of these options. diff --git a/dts/bindings/serial/realtek,rts5912-uart.yaml b/dts/bindings/serial/realtek,rts5912-uart.yaml new file mode 100644 index 00000000000..b1464900490 --- /dev/null +++ b/dts/bindings/serial/realtek,rts5912-uart.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +description: Realtek RTS5912 UART + +compatible: "realtek,rts5912-uart" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + port: + type: int + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/timer/realtek,rts5912-rtmr.yaml b/dts/bindings/timer/realtek,rts5912-rtmr.yaml new file mode 100644 index 00000000000..6e6c0d3a0a6 --- /dev/null +++ b/dts/bindings/timer/realtek,rts5912-rtmr.yaml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +description: RTOS Timer on Realtek RTS5912 EC + +compatible: "realtek,rts5912-rtmr" + +include: base.yaml + +properties: + reg: + required: true + + interrupts: + required: true diff --git a/dts/bindings/timer/realtek,rts5912-slwtimer.yaml b/dts/bindings/timer/realtek,rts5912-slwtimer.yaml new file mode 100644 index 00000000000..aa8a3f40510 --- /dev/null +++ b/dts/bindings/timer/realtek,rts5912-slwtimer.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +description: Realtek RTS5912 32-bit slow timer + +compatible: "realtek,rts5912-slwtimer" + +include: rtc.yaml + +properties: + reg: + required: true + + interrupts: + required: true + + max-value: + type: int + required: true + description: Maximum counter value the instance can handle + + clock-frequency: + required: true + + prescaler: + type: int + required: true + description: Timer frequency equals clock-frequency divided by the prescaler value diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi index 1fe345e33f2..2211a4b6643 100644 --- a/dts/common/nordic/nrf54h20.dtsi +++ b/dts/common/nordic/nrf54h20.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -201,6 +202,12 @@ clocks = <&hfxo>, <&lfxo>; clock-names = "hfxo", "lfxo"; }; + + audiopll: audiopll { + compatible = "nordic,nrfs-audiopll"; + frequency = ; + status = "disabled"; + }; }; gpd: global-power-domain { diff --git a/dts/riscv/sensry/ganymed-sy1xx.dtsi b/dts/riscv/sensry/ganymed-sy1xx.dtsi index ad2df617b28..5e652c56a15 100644 --- a/dts/riscv/sensry/ganymed-sy1xx.dtsi +++ b/dts/riscv/sensry/ganymed-sy1xx.dtsi @@ -38,18 +38,18 @@ soc { #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; event0: interrupt-controller@1000 { compatible = "sensry,sy1xx-event-unit"; - reg = <0x1000>; + reg = <0x1000 0x40>; interrupt-controller; #interrupt-cells = <1>; }; systick: timer@1a10b040 { compatible = "sensry,sy1xx-sys-timer"; - reg = <0x1a10b040>; + reg = <0x1a10b040 0x04>; interrupt-parent = <&event0>; interrupts = <10 0>; ticks_us = <1000>; @@ -57,7 +57,7 @@ timer1: timer@1a10b044 { compatible = "sensry,sy1xx-sys-timer"; - reg = <0x1a10b044>; + reg = <0x1a10b044 0x04>; interrupt-parent = <&event0>; interrupts = <11 0>; ticks_us = <1000>; @@ -65,7 +65,7 @@ uart0: uart@1a102000 { compatible = "sensry,sy1xx-uart"; - reg = <0x1a102000>; + reg = <0x1a102000 0x80>; instance = <0>; current-speed = <1000000>; status = "okay"; @@ -73,7 +73,7 @@ uart1: uart@1a102080 { compatible = "sensry,sy1xx-uart"; - reg = <0x1a102080>; + reg = <0x1a102080 0x80>; instance = <1>; current-speed = <1000000>; status = "okay"; @@ -81,11 +81,17 @@ uart2: uart@1a102100 { compatible = "sensry,sy1xx-uart"; - reg = <0x1a102100>; + reg = <0x1a102100 0x80>; instance = <2>; current-speed = <1000000>; status = "okay"; }; + pinctrl: pinctrl@1a104000 { + compatible = "sensry,sy1xx-pinctrl"; + reg = <0x1a104000 0x1000>; + status = "okay"; + }; + }; }; diff --git a/include/zephyr/drivers/clock_control/clock_control_rts5912.h b/include/zephyr/drivers/clock_control/clock_control_rts5912.h new file mode 100644 index 00000000000..381502bf7c1 --- /dev/null +++ b/include/zephyr/drivers/clock_control/clock_control_rts5912.h @@ -0,0 +1,20 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#include + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RTS5912_H_ +#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RTS5912_H_ + +struct rts5912_sccon_subsys { + uint32_t clk_grp; + uint32_t clk_idx; + uint32_t clk_src; + uint32_t clk_div; +}; + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RTS591X_H_ */ diff --git a/include/zephyr/dt-bindings/clock/nrfs-audiopll.h b/include/zephyr/dt-bindings/clock/nrfs-audiopll.h new file mode 100644 index 00000000000..b4c3975b5e1 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/nrfs-audiopll.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRFS_AUDIOPLL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRFS_AUDIOPLL_H_ + +#define NRFS_AUDIOPLL_FREQ_MIN 10666707 +#define NRFS_AUDIOPLL_FREQ_AUDIO_44K1 11289591 +#define NRFS_AUDIOPLL_FREQ_AUDIO_48K 12287963 +#define NRFS_AUDIOPLL_FREQ_MAX 13333292 + +#endif /* #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRFS_AUDIOPLL_H_ */ diff --git a/include/zephyr/dt-bindings/clock/rts5912_clock.h b/include/zephyr/dt-bindings/clock/rts5912_clock.h new file mode 100644 index 00000000000..ef754602dd6 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/rts5912_clock.h @@ -0,0 +1,343 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RTS5912_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RTS5912_CLOCK_H_ + +/* ====================================================================================== */ +/* ===================================== I2CCLK ======================================= */ +#define I2CCLK_I2C0CLKPWR_Pos (0) /*!< I2C0CLKPWR (Bit 0) */ +#define I2CCLK_I2C0CLKPWR_Msk (0x1) /*!< I2C0CLKPWR (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C0CLKSRC_Pos (1) /*!< I2C0CLKSRC (Bit 1) */ +#define I2CCLK_I2C0CLKSRC_Msk (0x2) /*!< I2C0CLKSRC (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C0CLKDIV_Pos (2) /*!< I2C0CLKDIV (Bit 2) */ +#define I2CCLK_I2C0CLKDIV_Msk (0xc) /*!< I2C0CLKDIV (Bitfield-Mask: 0x03) */ +#define I2CCLK_I2C1CLKPWR_Pos (4) /*!< I2C1CLKPWR (Bit 4) */ +#define I2CCLK_I2C1CLKPWR_Msk (0x10) /*!< I2C1CLKPWR (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C1CLKSRC_Pos (5) /*!< I2C1CLKSRC (Bit 5) */ +#define I2CCLK_I2C1CLKSRC_Msk (0x20) /*!< I2C1CLKSRC (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C1CLKDIV_Pos (6) /*!< I2C1CLKDIV (Bit 6) */ +#define I2CCLK_I2C1CLKDIV_Msk (0xc0) /*!< I2C1CLKDIV (Bitfield-Mask: 0x03) */ +#define I2CCLK_I2C2CLKPWR_Pos (8) /*!< I2C2CLKPWR (Bit 8) */ +#define I2CCLK_I2C2CLKPWR_Msk (0x100) /*!< I2C2CLKPWR (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C2CLKSRC_Pos (9) /*!< I2C2CLKSRC (Bit 9) */ +#define I2CCLK_I2C2CLKSRC_Msk (0x200) /*!< I2C2CLKSRC (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C2CLKDIV_Pos (10) /*!< I2C2CLKDIV (Bit 10) */ +#define I2CCLK_I2C2CLKDIV_Msk (0xc00) /*!< I2C2CLKDIV (Bitfield-Mask: 0x03) */ +#define I2CCLK_I2C3CLKPWR_Pos (12) /*!< I2C3CLKPWR (Bit 12) */ +#define I2CCLK_I2C3CLKPWR_Msk (0x1000) /*!< I2C3CLKPWR (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C3CLKSRC_Pos (13) /*!< I2C3CLKSRC (Bit 13) */ +#define I2CCLK_I2C3CLKSRC_Msk (0x2000) /*!< I2C3CLKSRC (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C3CLKDIV_Pos (14) /*!< I2C3CLKDIV (Bit 14) */ +#define I2CCLK_I2C3CLKDIV_Msk (0xc000) /*!< I2C3CLKDIV (Bitfield-Mask: 0x03) */ +#define I2CCLK_I2C4CLKPWR_Pos (16) /*!< I2C4CLKPWR (Bit 16) */ +#define I2CCLK_I2C4CLKPWR_Msk (0x10000) /*!< I2C4CLKPWR (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C4CLKSRC_Pos (17) /*!< I2C4CLKSRC (Bit 17) */ +#define I2CCLK_I2C4CLKSRC_Msk (0x20000) /*!< I2C4CLKSRC (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C4CLKDIV_Pos (18) /*!< I2C4CLKDIV (Bit 18) */ +#define I2CCLK_I2C4CLKDIV_Msk (0xc0000) /*!< I2C4CLKDIV (Bitfield-Mask: 0x03) */ +#define I2CCLK_I2C5CLKPWR_Pos (20) /*!< I2C5CLKPWR (Bit 20) */ +#define I2CCLK_I2C5CLKPWR_Msk (0x100000) /*!< I2C5CLKPWR (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C5CLKSRC_Pos (21) /*!< I2C5CLKSRC (Bit 21) */ +#define I2CCLK_I2C5CLKSRC_Msk (0x200000) /*!< I2C5CLKSRC (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C5CLKDIV_Pos (22) /*!< I2C5CLKDIV (Bit 22) */ +#define I2CCLK_I2C5CLKDIV_Msk (0xc00000) /*!< I2C5CLKDIV (Bitfield-Mask: 0x03) */ +#define I2CCLK_I2C6CLKPWR_Pos (24) /*!< I2C6CLKPWR (Bit 24) */ +#define I2CCLK_I2C6CLKPWR_Msk (0x1000000) /*!< I2C6CLKPWR (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C6CLKSRC_Pos (25) /*!< I2C6CLKSRC (Bit 25) */ +#define I2CCLK_I2C6CLKSRC_Msk (0x2000000) /*!< I2C6CLKSRC (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C6CLKDIV_Pos (26) /*!< I2C6CLKDIV (Bit 26) */ +#define I2CCLK_I2C6CLKDIV_Msk (0xc000000) /*!< I2C6CLKDIV (Bitfield-Mask: 0x03) */ +#define I2CCLK_I2C7CLKPWR_Pos (28) /*!< I2C7CLKPWR (Bit 28) */ +#define I2CCLK_I2C7CLKPWR_Msk (0x10000000) /*!< I2C7CLKPWR (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C7CLKSRC_Pos (29) /*!< I2C7CLKSRC (Bit 29) */ +#define I2CCLK_I2C7CLKSRC_Msk (0x20000000) /*!< I2C7CLKSRC (Bitfield-Mask: 0x01) */ +#define I2CCLK_I2C7CLKDIV_Pos (30) /*!< I2C7CLKDIV (Bit 30) */ +#define I2CCLK_I2C7CLKDIV_Msk (0xc0000000) /*!< I2C7CLKDIV (Bitfield-Mask: 0x03) */ +/* =================================== PERICLKPWR0 ==================================== */ +#define PERICLKPWR0_GPIOCLKPWR_Pos (0) /*!< GPIOCLKPWR (Bit 0) */ +#define PERICLKPWR0_GPIOCLKPWR_Msk (0x1) /*!< GPIOCLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_TACHO0CLKPWR_Pos (1) /*!< TACHO0CLKPWR (Bit 1) */ +#define PERICLKPWR0_TACHO0CLKPWR_Msk (0x2) /*!< TACHO0CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_TACHO1CLKPWR_Pos (2) /*!< TACHO1CLKPWR (Bit 2) */ +#define PERICLKPWR0_TACHO1CLKPWR_Msk (0x4) /*!< TACHO1CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_TACHO2CLKPWR_Pos (3) /*!< TACHO2CLKPWR (Bit 3) */ +#define PERICLKPWR0_TACHO2CLKPWR_Msk (0x8) /*!< TACHO2CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_TACHO3CLKPWR_Pos (4) /*!< TACHO3CLKPWR (Bit 4) */ +#define PERICLKPWR0_TACHO3CLKPWR_Msk (0x10) /*!< TACHO3CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PS2CLKPWR_Pos (5) /*!< PS2CLKPWR (Bit 5) */ +#define PERICLKPWR0_PS2CLKPWR_Msk (0x20) /*!< PS2CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_KBMCLKPWR_Pos (6) /*!< KBMCLKPWR (Bit 6) */ +#define PERICLKPWR0_KBMCLKPWR_Msk (0x40) /*!< KBMCLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PECICLKPWR_Pos (7) /*!< PECICLKPWR (Bit 7) */ +#define PERICLKPWR0_PECICLKPWR_Msk (0x80) /*!< PECICLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PL0CLKPWR_Pos (8) /*!< PL0CLKPWR (Bit 8) */ +#define PERICLKPWR0_PL0CLKPWR_Msk (0x100) /*!< PL0CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PL1CLKPWR_Pos (9) /*!< PL1CLKPWR (Bit 9) */ +#define PERICLKPWR0_PL1CLKPWR_Msk (0x200) /*!< PL1CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM0CLKPWR_Pos (10) /*!< PWM0CLKPWR (Bit 10) */ +#define PERICLKPWR0_PWM0CLKPWR_Msk (0x400) /*!< PWM0CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM1CLKPWR_Pos (11) /*!< PWM1CLKPWR (Bit 11) */ +#define PERICLKPWR0_PWM1CLKPWR_Msk (0x800) /*!< PWM1CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM2CLKPWR_Pos (12) /*!< PWM2CLKPWR (Bit 12) */ +#define PERICLKPWR0_PWM2CLKPWR_Msk (0x1000) /*!< PWM2CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM3CLKPWR_Pos (13) /*!< PWM3CLKPWR (Bit 13) */ +#define PERICLKPWR0_PWM3CLKPWR_Msk (0x2000) /*!< PWM3CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM4CLKPWR_Pos (14) /*!< PWM4CLKPWR (Bit 14) */ +#define PERICLKPWR0_PWM4CLKPWR_Msk (0x4000) /*!< PWM4CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM5CLKPWR_Pos (15) /*!< PWM5CLKPWR (Bit 15) */ +#define PERICLKPWR0_PWM5CLKPWR_Msk (0x8000) /*!< PWM5CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM6CLKPWR_Pos (16) /*!< PWM6CLKPWR (Bit 16) */ +#define PERICLKPWR0_PWM6CLKPWR_Msk (0x10000) /*!< PWM6CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM7CLKPWR_Pos (17) /*!< PWM7CLKPWR (Bit 17) */ +#define PERICLKPWR0_PWM7CLKPWR_Msk (0x20000) /*!< PWM7CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM8CLKPWR_Pos (18) /*!< PWM8CLKPWR (Bit 18) */ +#define PERICLKPWR0_PWM8CLKPWR_Msk (0x40000) /*!< PWM8CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM9CLKPWR_Pos (19) /*!< PWM9CLKPWR (Bit 19) */ +#define PERICLKPWR0_PWM9CLKPWR_Msk (0x80000) /*!< PWM9CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM10CLKPWR_Pos (20) /*!< PWM10CLKPWR (Bit 20) */ +#define PERICLKPWR0_PWM10CLKPWR_Msk (0x100000) /*!< PWM10CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PWM11CLKPWR_Pos (21) /*!< PWM11CLKPWR (Bit 21) */ +#define PERICLKPWR0_PWM11CLKPWR_Msk (0x200000) /*!< PWM11CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_ESPICLKPWR_Pos (22) /*!< ESPICLKPWR (Bit 22) */ +#define PERICLKPWR0_ESPICLKPWR_Msk (0x400000) /*!< ESPICLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_KBCCLKPWR_Pos (23) /*!< KBCCLKPWR (Bit 23) */ +#define PERICLKPWR0_KBCCLKPWR_Msk (0x800000) /*!< KBCCLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_ACPICLKPWR_Pos (24) /*!< ACPICLKPWR (Bit 24) */ +#define PERICLKPWR0_ACPICLKPWR_Msk (0x1000000) /*!< ACPICLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_PMPORT0CLKPWR_Pos (25) /*!< PMPORT0CLKPWR (Bit 25) */ +#define PERICLKPWR0_PMPORT0CLKPWR_Msk (0x2000000) /*!< PMPORT0CLKPWR (Bitfield-Mask: 0x01)*/ +#define PERICLKPWR0_PMPORT1CLKPWR_Pos (26) /*!< PMPORT1CLKPWR (Bit 26) */ +#define PERICLKPWR0_PMPORT1CLKPWR_Msk (0x4000000) /*!< PMPORT1CLKPWR (Bitfield-Mask: 0x01)*/ +#define PERICLKPWR0_PMPORT2CLKPWR_Pos (27) /*!< PMPORT2CLKPWR (Bit 27) */ +#define PERICLKPWR0_PMPORT2CLKPWR_Msk (0x8000000) /*!< PMPORT2CLKPWR (Bitfield-Mask: 0x01)*/ +#define PERICLKPWR0_PMPORT3CLKPWR_Pos (28) /*!< PMPORT3CLKPWR (Bit 28) */ +#define PERICLKPWR0_PMPORT3CLKPWR_Msk (0x10000000) /*!< PMPORT3CLKPWR (Bitfield-Mask: 0x01)*/ +#define PERICLKPWR0_P80CLKPWR_Pos (29) /*!< P80CLKPWR (Bit 29) */ +#define PERICLKPWR0_P80CLKPWR_Msk (0x20000000) /*!< P80CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_EMI0CLKPWR_Pos (30) /*!< EMI0CLKPWR (Bit 30) */ +#define PERICLKPWR0_EMI0CLKPWR_Msk (0x40000000) /*!< EMI0CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR0_EMI1CLKPWR_Pos (31) /*!< EMI1CLKPWR (Bit 31) */ +#define PERICLKPWR0_EMI1CLKPWR_Msk (0x80000000) /*!< EMI1CLKPWR (Bitfield-Mask: 0x01) */ +/* ===================================== UARTCLK ====================================== */ +#define UARTCLK_PWR_Pos (0) /*!< PWR (Bit 0) */ +#define UARTCLK_PWR_Msk (0x1) /*!< PWR (Bitfield-Mask: 0x01) */ +#define UARTCLK_SRC_Pos (1) /*!< SRC (Bit 1) */ +#define UARTCLK_SRC_Msk (0x2) /*!< SRC (Bitfield-Mask: 0x01) */ +#define UARTCLK_DIV_Pos (2) /*!< DIV (Bit 2) */ +#define UARTCLK_DIV_Msk (0xc) /*!< DIV (Bitfield-Mask: 0x03) */ +/* ===================================== ADCCLK ======================================= */ +#define ADCCLK_PWR_Pos (0) /*!< PWR (Bit 0) */ +#define ADCCLK_PWR_Msk (0x1) /*!< PWR (Bitfield-Mask: 0x01) */ +#define ADCCLK_SRC_Pos (1) /*!< SRC (Bit 1) */ +#define ADCCLK_SRC_Msk (0x2) /*!< SRC (Bitfield-Mask: 0x01) */ +#define ADCCLK_DIV_Pos (2) /*!< DIV (Bit 2) */ +#define ADCCLK_DIV_Msk (0x1c) /*!< DIV (Bitfield-Mask: 0x07) */ +/* =================================== PERICLKPWR1 ==================================== */ +#define PERICLKPWR1_EMI2CLKPWR_Pos (0) /*!< EMI2CLKPWR (Bit 0) */ +#define PERICLKPWR1_EMI2CLKPWR_Msk (0x1) /*!< EMI2CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_EMI3CLKPWR_Pos (1) /*!< EMI3CLKPWR (Bit 1) */ +#define PERICLKPWR1_EMI3CLKPWR_Msk (0x2) /*!< EMI3CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_EMI4CLKPWR_Pos (2) /*!< EMI4CLKPWR (Bit 2) */ +#define PERICLKPWR1_EMI4CLKPWR_Msk (0x4) /*!< EMI4CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_EMI5CLKPWR_Pos (3) /*!< EMI5CLKPWR (Bit 3) */ +#define PERICLKPWR1_EMI5CLKPWR_Msk (0x8) /*!< EMI5CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_EMI6CLKPWR_Pos (4) /*!< EMI6CLKPWR (Bit 4) */ +#define PERICLKPWR1_EMI6CLKPWR_Msk (0x10) /*!< EMI6CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_EMI7CLKPWR_Pos (5) /*!< EMI7CLKPWR (Bit 5) */ +#define PERICLKPWR1_EMI7CLKPWR_Msk (0x20) /*!< EMI7CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_I3C0CLKPWR_Pos (9) /*!< I3C0CLKPWR (Bit 9) */ +#define PERICLKPWR1_I3C0CLKPWR_Msk (0x200) /*!< I3C0CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_I3C1CLKPWR_Pos (10) /*!< I3C1CLKPWR (Bit 10) */ +#define PERICLKPWR1_I3C1CLKPWR_Msk (0x400) /*!< I3C1CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_I2CAUTOCLKPWR_Pos (11) /*!< I2CAUTOCLKPWR (Bit 11) */ +#define PERICLKPWR1_I2CAUTOCLKPWR_Msk (0x800) /*!< I2CAUTOCLKPWR (Bitfield-Mask: 0x01)*/ +#define PERICLKPWR1_MCCLKPWR_Pos (12) /*!< MCCLKPWR (Bit 12) */ +#define PERICLKPWR1_MCCLKPWR_Msk (0x1000) /*!< MCCLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_TMR0CLKPWR_Pos (13) /*!< TMR0CLKPWR (Bit 13) */ +#define PERICLKPWR1_TMR0CLKPWR_Msk (0x2000) /*!< TMR0CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_TMR1CLKPWR_Pos (14) /*!< TMR1CLKPWR (Bit 14) */ +#define PERICLKPWR1_TMR1CLKPWR_Msk (0x4000) /*!< TMR1CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_TMR2CLKPWR_Pos (15) /*!< TMR2CLKPWR (Bit 15) */ +#define PERICLKPWR1_TMR2CLKPWR_Msk (0x8000) /*!< TMR2CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_TMR3CLKPWR_Pos (16) /*!< TMR3CLKPWR (Bit 16) */ +#define PERICLKPWR1_TMR3CLKPWR_Msk (0x10000) /*!< TMR3CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_TMR4CLKPWR_Pos (17) /*!< TMR4CLKPWR (Bit 17) */ +#define PERICLKPWR1_TMR4CLKPWR_Msk (0x20000) /*!< TMR4CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_TMR5CLKPWR_Pos (18) /*!< TMR5CLKPWR (Bit 18) */ +#define PERICLKPWR1_TMR5CLKPWR_Msk (0x40000) /*!< TMR5CLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_RTMRCLKPWR_Pos (19) /*!< RTMRCLKPWR (Bit 19) */ +#define PERICLKPWR1_RTMRCLKPWR_Msk (0x80000) /*!< RTMRCLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR1_SLWTMR0CLKPWR_Pos (20) /*!< SLWTMR0CLKPWR (Bit 20) */ +#define PERICLKPWR1_SLWTMR0CLKPWR_Msk (0x100000) /*!< SLWTMR0CLKPWR (Bitfield-Mask: 0x01)*/ +#define PERICLKPWR1_SLWTMR1CLKPWR_Pos (21) /*!< SLWTMR1CLKPWR (Bit 21) */ +#define PERICLKPWR1_SLWTMR1CLKPWR_Msk (0x200000) /*!< SLWTMR1CLKPWR (Bitfield-Mask: 0x01)*/ +/* =================================== PERICLKPWR2 ==================================== */ +#define PERICLKPWR2_RTCCLKPWR_Pos (0) /*!< RTCCLKPWR (Bit 0) */ +#define PERICLKPWR2_RTCCLKPWR_Msk (0x1) /*!< RTCCLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR2_WDTCLKPWR_Pos (1) /*!< WDTCLKPWR (Bit 1) */ +#define PERICLKPWR2_WDTCLKPWR_Msk (0x2) /*!< WDTCLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR2_PWRBTNCLKPWR_Pos (2) /*!< PWRBTNCLKPWR (Bit 2) */ +#define PERICLKPWR2_PWRBTNCLKPWR_Msk (0x4) /*!< PWRBTNCLKPWR (Bitfield-Mask: 0x01) */ +#define PERICLKPWR2_RC32KSRC_Pos (30) /*!< RC32KSRC (Bit 30) */ +#define PERICLKPWR2_RC32KSRC_Msk (0xc0000000) /*!< RC32KSRC (Bitfield-Mask: 0x03) */ +/* ====================================================================================== */ + +#define RTS5912_SCCON_SYS (0) +#define RTS5912_SCCON_I2C (2) +#define RTS5912_SCCON_UART (3) +#define RTS5912_SCCON_ADC (4) +#define RTS5912_SCCON_PERIPH_GRP0 (5) +#define RTS5912_SCCON_PERIPH_GRP1 (6) +#define RTS5912_SCCON_PERIPH_GRP2 (7) + +#define I2C0_CLKPWR (I2CCLK_I2C0CLKPWR_Pos) +#define I2C1_CLKPWR (I2CCLK_I2C1CLKPWR_Pos) +#define I2C2_CLKPWR (I2CCLK_I2C2CLKPWR_Pos) +#define I2C3_CLKPWR (I2CCLK_I2C3CLKPWR_Pos) +#define I2C4_CLKPWR (I2CCLK_I2C4CLKPWR_Pos) +#define I2C5_CLKPWR (I2CCLK_I2C5CLKPWR_Pos) +#define I2C6_CLKPWR (I2CCLK_I2C6CLKPWR_Pos) +#define I2C7_CLKPWR (I2CCLK_I2C7CLKPWR_Pos) + +#define I2C0_PLL (0x0 << I2CCLK_I2C0CLKSRC_Pos) +#define I2C0_RC25M (0x1 << I2CCLK_I2C0CLKSRC_Pos) +#define I2C1_PLL (0x0 << I2CCLK_I2C1CLKSRC_Pos) +#define I2C1_RC25M (0x1 << I2CCLK_I2C1CLKSRC_Pos) +#define I2C2_PLL (0x0 << I2CCLK_I2C2CLKSRC_Pos) +#define I2C2_RC25M (0x1 << I2CCLK_I2C2CLKSRC_Pos) +#define I2C3_PLL (0x0 << I2CCLK_I2C3CLKSRC_Pos) +#define I2C3_RC25M (0x1 << I2CCLK_I2C3CLKSRC_Pos) +#define I2C4_PLL (0x0 << I2CCLK_I2C4CLKSRC_Pos) +#define I2C4_RC25M (0x1 << I2CCLK_I2C4CLKSRC_Pos) +#define I2C5_PLL (0x0 << I2CCLK_I2C5CLKSRC_Pos) +#define I2C5_RC25M (0x1 << I2CCLK_I2C5CLKSRC_Pos) +#define I2C6_PLL (0x0 << I2CCLK_I2C6CLKSRC_Pos) +#define I2C6_RC25M (0x1 << I2CCLK_I2C6CLKSRC_Pos) +#define I2C7_PLL (0x0 << I2CCLK_I2C7CLKSRC_Pos) +#define I2C7_RC25M (0x1 << I2CCLK_I2C7CLKSRC_Pos) + +#define I2C0_CLKDIV1 (0 << I2CCLK_I2C0CLKDIV_Pos) +#define I2C0_CLKDIV2 (1 << I2CCLK_I2C0CLKDIV_Pos) +#define I2C0_CLKDIV4 (2 << I2CCLK_I2C0CLKDIV_Pos) +#define I2C0_CLKDIV8 (3 << I2CCLK_I2C0CLKDIV_Pos) + +#define I2C1_CLKDIV1 (0 << I2CCLK_I2C1CLKDIV_Pos) +#define I2C1_CLKDIV2 (1 << I2CCLK_I2C1CLKDIV_Pos) +#define I2C1_CLKDIV4 (2 << I2CCLK_I2C1CLKDIV_Pos) +#define I2C1_CLKDIV8 (3 << I2CCLK_I2C1CLKDIV_Pos) + +#define I2C2_CLKDIV1 (0 << I2CCLK_I2C2CLKDIV_Pos) +#define I2C2_CLKDIV2 (1 << I2CCLK_I2C2CLKDIV_Pos) +#define I2C2_CLKDIV4 (2 << I2CCLK_I2C2CLKDIV_Pos) +#define I2C2_CLKDIV8 (3 << I2CCLK_I2C2CLKDIV_Pos) + +#define I2C3_CLKDIV1 (0 << I2CCLK_I2C3CLKDIV_Pos) +#define I2C3_CLKDIV2 (1 << I2CCLK_I2C3CLKDIV_Pos) +#define I2C3_CLKDIV4 (2 << I2CCLK_I2C3CLKDIV_Pos) +#define I2C3_CLKDIV8 (3 << I2CCLK_I2C3CLKDIV_Pos) + +#define I2C4_CLKDIV1 (0 << I2CCLK_I2C4CLKDIV_Pos) +#define I2C4_CLKDIV2 (1 << I2CCLK_I2C4CLKDIV_Pos) +#define I2C4_CLKDIV4 (2 << I2CCLK_I2C4CLKDIV_Pos) +#define I2C4_CLKDIV8 (3 << I2CCLK_I2C4CLKDIV_Pos) + +#define I2C5_CLKDIV1 (0 << I2CCLK_I2C5CLKDIV_Pos) +#define I2C5_CLKDIV2 (1 << I2CCLK_I2C5CLKDIV_Pos) +#define I2C5_CLKDIV4 (2 << I2CCLK_I2C5CLKDIV_Pos) +#define I2C5_CLKDIV8 (3 << I2CCLK_I2C5CLKDIV_Pos) + +#define I2C6_CLKDIV1 (0 << I2CCLK_I2C6CLKDIV_Pos) +#define I2C6_CLKDIV2 (1 << I2CCLK_I2C6CLKDIV_Pos) +#define I2C6_CLKDIV4 (2 << I2CCLK_I2C6CLKDIV_Pos) +#define I2C6_CLKDIV8 (3 << I2CCLK_I2C6CLKDIV_Pos) + +#define I2C7_CLKDIV1 (0 << I2CCLK_I2C7CLKDIV_Pos) +#define I2C7_CLKDIV2 (1 << I2CCLK_I2C7CLKDIV_Pos) +#define I2C7_CLKDIV4 (2 << I2CCLK_I2C7CLKDIV_Pos) +#define I2C7_CLKDIV8 (3 << I2CCLK_I2C7CLKDIV_Pos) + +#define UART0_CLKPWR (UARTCLK_PWR_Pos) + +#define UART0_RC25M (0x0 << UARTCLK_SRC_Pos) +#define UART0_PLL (0x1 << UARTCLK_SRC_Pos) + +#define UART0_CLKDIV1 (0 << UARTCLK_DIV_Pos) +#define UART0_CLKDIV2 (1 << UARTCLK_DIV_Pos) +#define UART0_CLKDIV4 (2 << UARTCLK_DIV_Pos) +#define UART0_CLKDIV8 (3 << UARTCLK_DIV_Pos) + +#define ADC0_CLKPWR (ADCCLK_PWR_Pos) + +#define ADC0_RC25M (0x0 << ADCCLK_SRC_Pos) +#define ADC0_PLL (0x1 << ADCCLK_SRC_Pos) + +#define ADC0_CLKDIV1 (0 << ADCCLK_DIV_Pos) +#define ADC0_CLKDIV2 (1 << ADCCLK_DIV_Pos) +#define ADC0_CLKDIV3 (2 << ADCCLK_DIV_Pos) +#define ADC0_CLKDIV4 (3 << ADCCLK_DIV_Pos) +#define ADC0_CLKDIV6 (4 << ADCCLK_DIV_Pos) +#define ADC0_CLKDIV8 (5 << ADCCLK_DIV_Pos) + +#define PERIPH_GRP0_GPIO_CLKPWR (PERICLKPWR0_GPIOCLKPWR_Pos) +#define PERIPH_GRP0_TACH0_CLKPWR (PERICLKPWR0_TACHO0CLKPWR_Pos) +#define PERIPH_GRP0_TACH1_CLKPWR (PERICLKPWR0_TACHO1CLKPWR_Pos) +#define PERIPH_GRP0_TACH2_CLKPWR (PERICLKPWR0_TACHO2CLKPWR_Pos) +#define PERIPH_GRP0_TACH3_CLKPWR (PERICLKPWR0_TACHO3CLKPWR_Pos) +#define PERIPH_GRP0_PS2_CLKPWR (PERICLKPWR0_PS2CLKPWR_Pos) +#define PERIPH_GRP0_KBM_CLKPWR (PERICLKPWR0_KBMCLKPWR_Pos) +#define PERIPH_GRP0_PECI_CLKPWR (PERICLKPWR0_PECICLKPWR_Pos) +#define PERIPH_GRP0_LEDPWM0_CLKPWR (PERICLKPWR0_PL0CLKPWR_Pos) +#define PERIPH_GRP0_LEDPWM1_CLKPWR (PERICLKPWR0_PL1CLKPWR_Pos) +#define PERIPH_GRP0_PWM0_CLKPWR (PERICLKPWR0_PWM0CLKPWR_Pos) +#define PERIPH_GRP0_PWM1_CLKPWR (PERICLKPWR0_PWM1CLKPWR_Pos) +#define PERIPH_GRP0_PWM2_CLKPWR (PERICLKPWR0_PWM2CLKPWR_Pos) +#define PERIPH_GRP0_PWM3_CLKPWR (PERICLKPWR0_PWM3CLKPWR_Pos) +#define PERIPH_GRP0_PWM4_CLKPWR (PERICLKPWR0_PWM4CLKPWR_Pos) +#define PERIPH_GRP0_PWM5_CLKPWR (PERICLKPWR0_PWM5CLKPWR_Pos) +#define PERIPH_GRP0_PWM6_CLKPWR (PERICLKPWR0_PWM6CLKPWR_Pos) +#define PERIPH_GRP0_PWM7_CLKPWR (PERICLKPWR0_PWM7CLKPWR_Pos) +#define PERIPH_GRP0_PWM8_CLKPWR (PERICLKPWR0_PWM8CLKPWR_Pos) +#define PERIPH_GRP0_PWM9_CLKPWR (PERICLKPWR0_PWM9CLKPWR_Pos) +#define PERIPH_GRP0_PWM10_CLKPWR (PERICLKPWR0_PWM10CLKPWR_Pos) +#define PERIPH_GRP0_PWM11_CLKPWR (PERICLKPWR0_PWM11CLKPWR_Pos) +#define PERIPH_GRP0_ESPI_CLKPWR (PERICLKPWR0_ESPICLKPWR_Pos) +#define PERIPH_GRP0_KBC_CLKPWR (PERICLKPWR0_KBCCLKPWR_Pos) +#define PERIPH_GRP0_ACPI_CLKPWR (PERICLKPWR0_ACPICLKPWR_Pos) +#define PERIPH_GRP0_PMPORT0_CLKPWR (PERICLKPWR0_PMPORT0CLKPWR_Pos) +#define PERIPH_GRP0_PMPORT1_CLKPWR (PERICLKPWR0_PMPORT1CLKPWR_Pos) +#define PERIPH_GRP0_PMPORT2_CLKPWR (PERICLKPWR0_PMPORT2CLKPWR_Pos) +#define PERIPH_GRP0_PMPORT3_CLKPWR (PERICLKPWR0_PMPORT3CLKPWR_Pos) +#define PERIPH_GRP0_P80_CLKPWR (PERICLKPWR0_P80CLKPWR_Pos) +#define PERIPH_GRP0_EMI0_CLKPWR (PERICLKPWR0_EMI0CLKPWR_Pos) +#define PERIPH_GRP0_EMI1_CLKPWR (PERICLKPWR0_EMI1CLKPWR_Pos) + +#define PERIPH_GRP1_EMI2_CLKPWR (PERICLKPWR1_EMI2CLKPWR_Pos) +#define PERIPH_GRP1_EMI3_CLKPWR (PERICLKPWR1_EMI3CLKPWR_Pos) +#define PERIPH_GRP1_EMI4_CLKPWR (PERICLKPWR1_EMI4CLKPWR_Pos) +#define PERIPH_GRP1_EMI5_CLKPWR (PERICLKPWR1_EMI5CLKPWR_Pos) +#define PERIPH_GRP1_EMI6_CLKPWR (PERICLKPWR1_EMI6CLKPWR_Pos) +#define PERIPH_GRP1_EMI7_CLKPWR (PERICLKPWR1_EMI7CLKPWR_Pos) +#define PERIPH_GRP1_I3C0_CLKPWR (PERICLKPWR1_I3C0CLKPWR_Pos) +#define PERIPH_GRP1_I3C1_CLKPWR (PERICLKPWR1_I3C1CLKPWR_Pos) +#define PERIPH_GRP1_I2CAUTO_CLKPWR (PERICLKPWR1_I2CAUTOCLKPWR_Pos) +#define PERIPH_GRP1_MC_CLKPWR (PERICLKPWR1_MCCLKPWR_Pos) +#define PERIPH_GRP1_TMR0_CLKPWR (PERICLKPWR1_TMR0CLKPWR_Pos) +#define PERIPH_GRP1_TMR1_CLKPWR (PERICLKPWR1_TMR1CLKPWR_Pos) +#define PERIPH_GRP1_TMR2_CLKPWR (PERICLKPWR1_TMR2CLKPWR_Pos) +#define PERIPH_GRP1_TMR3_CLKPWR (PERICLKPWR1_TMR3CLKPWR_Pos) +#define PERIPH_GRP1_TMR4_CLKPWR (PERICLKPWR1_TMR4CLKPWR_Pos) +#define PERIPH_GRP1_TMR5_CLKPWR (PERICLKPWR1_TMR5CLKPWR_Pos) +#define PERIPH_GRP1_RTMR_CLKPWR (PERICLKPWR1_RTMRCLKPWR_Pos) +#define PERIPH_GRP1_SLWTMR0_CLKPWR (PERICLKPWR1_SLWTMR0CLKPWR_Pos) +#define PERIPH_GRP1_SLWTMR1_CLKPWR (PERICLKPWR1_SLWTMR1CLKPWR_Pos) + +#define PERIPH_GRP2_RTC_CLKPWR (PERICLKPWR2_RTCCLKPWR_Pos) +#define PERIPH_GRP2_WDT_CLKPWR (PERICLKPWR2_WDTCLKPWR_Pos) +#define PERIPH_GRP2_WDTPWRBTN_CLKPWR (PERICLKPWR2_PWRBTNCLKPWR_Pos) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RTS5912_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/gpio/realtek-gpio.h b/include/zephyr/dt-bindings/gpio/realtek-gpio.h new file mode 100644 index 00000000000..9b346f4301b --- /dev/null +++ b/include/zephyr/dt-bindings/gpio/realtek-gpio.h @@ -0,0 +1,23 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_ + +#define RTS5912_GPIO_VOLTAGE_POS 11 +#define RTS5912_GPIO_VOLTAGE_MASK (3U << RTS5912_GPIO_VOLTAGE_POS) + +/** Set pin at the default voltage level */ +#define RTS5912_GPIO_VOLTAGE_DEFAULT (0U << RTS5912_GPIO_VOLTAGE_POS) +/** Set pin voltage level at 1.8 V */ +#define RTS5912_GPIO_VOLTAGE_1V8 (1U << RTS5912_GPIO_VOLTAGE_POS) +/** Set pin voltage level at 3.3 V */ +#define RTS5912_GPIO_VOLTAGE_3V3 (2U << RTS5912_GPIO_VOLTAGE_POS) +/** Set pin voltage level at 5.0 V */ +#define RTS5912_GPIO_VOLTAGE_5V0 (3U << RTS5912_GPIO_VOLTAGE_POS) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/realtek-rts5912-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/realtek-rts5912-pinctrl.h new file mode 100644 index 00000000000..9954f4105d7 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/realtek-rts5912-pinctrl.h @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_REALTEK_RTS5912_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_REALTEK_RTS5912_PINCTRL_H_ + +#include + +#define REALTEK_RTS5912_GPIO_INOUT BIT(0) /* IN/OUT : 0 input 1 output */ +#define REALTEK_RTS5912_GPIO_PINON BIT(1) /* Input_detect : 1 enable 0 disable */ +#define REALTEK_RTS5912_GPIO_VOLT BIT(2) /* Pin Volt : 1 1.8V 0 3.3V */ +#define REALTEK_RTS5912_FUNC0 0 /* GPIO mode */ +#define REALTEK_RTS5912_FUNC1 BIT(8) /* Function mode use BIT0~2 */ +#define REALTEK_RTS5912_FUNC2 BIT(9) +#define REALTEK_RTS5912_FUNC3 ((BIT(8)) | (BIT(9))) +#define REALTEK_RTS5912_FUNC4 BIT(10) + +#define REALTEK_RTS5912_INPUT_OUTPUT_POS 0 +#define REALTEK_RTS5912_INPUT_DETECTION_POS 1 +#define REALTEK_RTS5912_VOLTAGE_POS 2 +#define REALTEK_RTS5912_DRV_STR_POS 11 +#define REALTEK_RTS5912_SLEW_RATE_POS 12 +#define REALTEK_RTS5912_PD_POS 13 +#define REALTEK_RTS5912_PU_POS 14 +#define REALTEK_RTS5912_SCHMITTER_POS 15 +#define REALTEK_RTS5912_TYPE_POS 16 +#define REALTEK_RTS5912_HIGH_LOW_POS 17 + +#define REALTEK_RTS5912_GPIO_HIGH_POS 18 +#define REALTEK_RTS5912_GPIO_HIGH_MSK 0x3f +#define REALTEK_RTS5912_GPIO_LOW_POS 3 +#define REALTEK_RTS5912_GPIO_LOW_MSK 0x1f + +#define FUNC0 REALTEK_RTS5912_FUNC0 +#define FUNC1 REALTEK_RTS5912_FUNC1 +#define FUNC2 REALTEK_RTS5912_FUNC2 +#define FUNC3 REALTEK_RTS5912_FUNC3 +#define FUNC4 REALTEK_RTS5912_FUNC4 + +#define REALTEK_RTS5912_PINMUX(n, f) \ + (((((n) >> 5) & REALTEK_RTS5912_GPIO_HIGH_MSK) << REALTEK_RTS5912_GPIO_HIGH_POS) | \ + (((n) & REALTEK_RTS5912_GPIO_LOW_MSK) << REALTEK_RTS5912_GPIO_LOW_POS) | (f)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_REALTEK_RTS5912_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/sy1xx-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/sy1xx-pinctrl.h new file mode 100644 index 00000000000..deee135bd60 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/sy1xx-pinctrl.h @@ -0,0 +1,70 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#ifndef _ZEPHYR_DT_BINDINGS_PINCTRL_SY1XX_PINCTRL_ +#define _ZEPHYR_DT_BINDINGS_PINCTRL_SY1XX_PINCTRL_ + +#define SY1XX_PAD(pad) (pad * 8) + +#define SY1XX_UART0_PAD_CFG0 0x0020 +#define SY1XX_UART1_PAD_CFG0 0x0024 +#define SY1XX_UART2_PAD_CFG0 0x0028 + +#define SY1XX_SPI0_PAD_CFG0 0x002c +#define SY1XX_SPI0_PAD_CFG1 0x0030 + +#define SY1XX_SPI1_PAD_CFG0 0x0034 +#define SY1XX_SPI1_PAD_CFG1 0x0038 + +#define SY1XX_SPI2_PAD_CFG0 0x003c +#define SY1XX_SPI2_PAD_CFG1 0x0040 + +#define SY1XX_SPI3_PAD_CFG0 0x0044 +#define SY1XX_SPI3_PAD_CFG1 0x0048 + +#define SY1XX_SPI4_PAD_CFG0 0x004c +#define SY1XX_SPI4_PAD_CFG1 0x0050 + +#define SY1XX_SPI5_PAD_CFG0 0x0054 +#define SY1XX_SPI5_PAD_CFG1 0x0058 + +#define SY1XX_SPI6_PAD_CFG0 0x005c +#define SY1XX_SPI6_PAD_CFG1 0x0060 + +#define SY1XX_I2C0_PAD_CFG0 0x0100 +#define SY1XX_I2C1_PAD_CFG0 0x0104 +#define SY1XX_I2C2_PAD_CFG0 0x0108 +#define SY1XX_I2C3_PAD_CFG0 0x010c + +#define SY1XX_GPIO0_PAD_CFG0 0x0110 +#define SY1XX_GPIO0_PAD_CFG1 0x0114 +#define SY1XX_GPIO0_PAD_CFG2 0x0118 +#define SY1XX_GPIO0_PAD_CFG3 0x011c +#define SY1XX_GPIO0_PAD_CFG4 0x0120 +#define SY1XX_GPIO0_PAD_CFG5 0x0124 +#define SY1XX_GPIO0_PAD_CFG6 0x0128 +#define SY1XX_GPIO0_PAD_CFG7 0x012c + +#define SY1XX_RGMII0_PAD_CFG0 0x0130 +#define SY1XX_RGMII0_PAD_CFG1 0x0134 +#define SY1XX_RGMII0_PAD_CFG2 0x0138 +#define SY1XX_RGMII0_PAD_CFG3 0x013c + +#define SY1XX_CAN0_PAD_CFG0 0x0140 + +#define SY1XX_I2S0_PAD_CFG0 0x0144 +#define SY1XX_I2S1_PAD_CFG0 0x0148 +#define SY1XX_I2S2_PAD_CFG0 0x014c +#define SY1XX_I2S3_PAD_CFG0 0x0150 + +#define SY1XX_HBUS0_PAD_CFG0 0x0154 +#define SY1XX_HBUS0_PAD_CFG1 0x0158 +#define SY1XX_HBUS0_PAD_CFG2 0x015c +#define SY1XX_HBUS0_PAD_CFG3 0x0160 + +#define SY1XX_QSPI0_PAD_CFG0 0x0164 +#define SY1XX_QSPI0_PAD_CFG1 0x0168 + +#endif /* _ZEPHYR_DT_BINDINGS_PINCTRL_SY1XX_PINCTRL_ */ diff --git a/samples/boards/nordic/clock_control/configs/audiopll.conf b/samples/boards/nordic/clock_control/configs/audiopll.conf new file mode 100644 index 00000000000..c06f206ab86 --- /dev/null +++ b/samples/boards/nordic/clock_control/configs/audiopll.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y diff --git a/samples/boards/nordic/clock_control/configs/audiopll.overlay b/samples/boards/nordic/clock_control/configs/audiopll.overlay new file mode 100644 index 00000000000..3e99bbdbeb8 --- /dev/null +++ b/samples/boards/nordic/clock_control/configs/audiopll.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/{ + aliases { + sample-clock = &audiopll; + }; +}; + +&audiopll { + status = "okay"; +}; diff --git a/samples/boards/nordic/clock_control/sample.yaml b/samples/boards/nordic/clock_control/sample.yaml index 820ad0de75f..ee63e7c518e 100644 --- a/samples/boards/nordic/clock_control/sample.yaml +++ b/samples/boards/nordic/clock_control/sample.yaml @@ -41,3 +41,8 @@ tests: extra_args: - CONF_FILE="configs/global_hsfll.conf" - DTC_OVERLAY_FILE="configs/global_hsfll.overlay" + sample.boards.nrf.clock_control.audiopll: + filter: dt_nodelabel_enabled("audiopll") + extra_args: + - CONF_FILE="configs/audiopll.conf" + - DTC_OVERLAY_FILE="configs/audiopll.overlay" diff --git a/soc/realtek/ec/CMakeLists.txt b/soc/realtek/ec/CMakeLists.txt new file mode 100644 index 00000000000..9953afd14f4 --- /dev/null +++ b/soc/realtek/ec/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +add_subdirectory(${SOC_SERIES}) +add_subdirectory(common) diff --git a/soc/realtek/ec/Kconfig b/soc/realtek/ec/Kconfig new file mode 100644 index 00000000000..a759cb44c37 --- /dev/null +++ b/soc/realtek/ec/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +if SOC_FAMILY_REALTEK_EC + +menuconfig REALTEK_RTS5912_BOOTROM_HEADER + bool "Create BOOTROM header for RTS5912" + help + The RTS5912 BOOTROM needs the information about boot up progress. + Invoke the 'rts5912_imgtool' to generates the RTS5912 bootrom header. + +if REALTEK_RTS5912_BOOTROM_HEADER + +config REALTEK_HEADER_CHIP + string + default "RTS5912" if SOC_RTS5912 + +DT_CHOSEN_Z_FLASH := zephyr,flash +FLASH_BASE := $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config REALTEK_RTS5912_BOOTROM_HEADER_LOAD_ADDRESS + string "Set the address for BOOTROM" + default "$(FLASH_BASE) - 0x20" + help + This address will be used by the RTS5912 BOOTROM to decide where firmware image start. + +endif # REALTEK_RTS5912_BOOTROM_HEADER + +# Select SoC Part No. and configuration options +rsource "*/Kconfig" + +endif # SOC_FAMILY_REALTEK_EC diff --git a/soc/realtek/ec/Kconfig.defconfig b/soc/realtek/ec/Kconfig.defconfig new file mode 100644 index 00000000000..effe686675a --- /dev/null +++ b/soc/realtek/ec/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +if SOC_FAMILY_REALTEK_EC + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_REALTEK_EC diff --git a/soc/realtek/ec/Kconfig.soc b/soc/realtek/ec/Kconfig.soc new file mode 100644 index 00000000000..fd19689cb07 --- /dev/null +++ b/soc/realtek/ec/Kconfig.soc @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config SOC_FAMILY_REALTEK_EC + bool + +config SOC_FAMILY + string + default "realtek_ec" if SOC_FAMILY_REALTEK_EC + +rsource "*/Kconfig.soc" diff --git a/soc/realtek/ec/common/CMakeLists.txt b/soc/realtek/ec/common/CMakeLists.txt new file mode 100644 index 00000000000..de4a266ee39 --- /dev/null +++ b/soc/realtek/ec/common/CMakeLists.txt @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +zephyr_include_directories(.) + +if (DEFINED CONFIG_REALTEK_RTS5912_BOOTROM_HEADER) + math(EXPR adjustment "${CONFIG_REALTEK_RTS5912_BOOTROM_HEADER_LOAD_ADDRESS}" OUTPUT_FORMAT DECIMAL) + set(RTS5912_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.rts5912.bin) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/realtek/ec/common/rts5912_imgtool/img_gen.py + -L ${adjustment} + -I ${KERNEL_BIN_NAME} + -O ${RTS5912_BIN_NAME} + -V + ) +endif() diff --git a/soc/realtek/ec/common/pinctrl_soc.h b/soc/realtek/ec/common/pinctrl_soc.h new file mode 100644 index 00000000000..5ca47e1e8a5 --- /dev/null +++ b/soc/realtek/ec/common/pinctrl_soc.h @@ -0,0 +1,63 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +/** + * @file + * realtek SoC specific helpers for pinctrl driver + */ + +#ifndef ZEPHYR_SOC_ARM_REALTEK_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_REALTEK_COMMON_PINCTRL_SOC_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +typedef uint32_t pinctrl_soc_pin_t; + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_REALTEK_RTS5912_PINMUX_INIT(node_id) (uint32_t)(DT_PROP(node_id, pinmux)) + +#define Z_PINCTRL_STATE_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, bias_pull_down) << REALTEK_RTS5912_PD_POS) | \ + (DT_PROP(node_id, bias_pull_up) << REALTEK_RTS5912_PU_POS) | \ + (DT_PROP(node_id, drive_open_drain) << REALTEK_RTS5912_TYPE_POS) | \ + (DT_PROP(node_id, output_high) << REALTEK_RTS5912_HIGH_LOW_POS) | \ + (DT_PROP(node_id, output_enable) << REALTEK_RTS5912_INPUT_OUTPUT_POS) | \ + (DT_PROP(node_id, input_schmitt_enable) << REALTEK_RTS5912_SCHMITTER_POS) | \ + (DT_PROP(node_id, input_enable) << REALTEK_RTS5912_INPUT_DETECTION_POS) | \ + (DT_ENUM_IDX_OR(node_id, slew_rate, 0x0) << REALTEK_RTS5912_SLEW_RATE_POS) | \ + (DT_ENUM_IDX_OR(node_id, drive_strength, 0x0) << REALTEK_RTS5912_DRV_STR_POS)) + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + (Z_PINCTRL_REALTEK_RTS5912_PINMUX_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx)) | \ + Z_PINCTRL_STATE_PINCFG_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))), + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { \ + DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) \ + } + +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_REALTEK_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/realtek/ec/common/rts5912_imgtool/img_gen.py b/soc/realtek/ec/common/rts5912_imgtool/img_gen.py new file mode 100644 index 00000000000..53fcefb916e --- /dev/null +++ b/soc/realtek/ec/common/rts5912_imgtool/img_gen.py @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# Author: Dylan Hsieh + +""" +The RTS5912 specific image header shows the bootROM how to +load the image from flash to internal SRAM, this script obtains +the header to original BIN and output a new BIN file. +""" + +import argparse +import os +import struct + +IMAGE_MAGIC = 0x524C544B # ASCII 'RLTK' +IMAGE_HDR_SIZE = 32 +RAM_LOAD = 0x0000020 +FREQ_50M = 0 +FREQ_25M = 1 +FREQ_12P5M = 2 +FREQ_6P25M = 3 +NORMAL_read = "0x03" +DUAL_read = "0x3B" +QUAD_read = "0x6B" + + +def parse_args(): + """ + Parsing the arguments + """ + parser = argparse.ArgumentParser(allow_abbrev=False) + + parser.add_argument( + "-L", + "--load-addr", + type=int, + dest="load_addr", + help="Load address for image when it should run from RAM.", + ) + + parser.add_argument( + "-I", + "--input", + type=str, + dest="original_bin", + default="zephyr.bin", + help="Input bin file path", + ) + + parser.add_argument( + "-O", + "--output", + type=str, + dest="signed_bin", + default="zephyr.rts5912.bin", + help="Output bin file path", + ) + + parser.add_argument( + "-F", + "--spi-freq", + type=int, + dest="spi_freq", + choices=[FREQ_50M, FREQ_25M, FREQ_12P5M, FREQ_6P25M], + default=FREQ_6P25M, + help="Specify the frequency of SPI I/F.", + ) + + parser.add_argument( + "-R", + "--spi-rdcmd", + type=str, + dest="spi_rdcmd", + choices=[NORMAL_read, DUAL_read, QUAD_read], + default=NORMAL_read, + help="Specify the command for flash read.", + ) + + parser.add_argument("-V", "--verbose", action="count", default=0, help="Verbose Output") + + ret_args = parser.parse_args() + return ret_args + + +def img_gen(load_addr, spi_freq, spi_rdcmd, original_bin, signed_bin): + """ + To obtain the RTS5912 image header and output a new BIN file + """ + img_size = os.path.getsize(original_bin) + payload = bytearray(0) + img_size = os.path.getsize(original_bin) + + fmt = ( + "<" + + + # type ImageHdr struct { + "I" # Magic uint32 + + "I" # LoadAddr uint32 + + "H" # HdrSz uint16 + + "H" # reserved uint16 + + "I" # ImgSz uint32 + + "I" # Flags uint32 + + "I" # reserved uint32 + + "I" # reserved uint32 + + "B" # SpiFmt uint8 + + "B" # SpiRdCmd uint8 + + "H" # reserved uint16 + ) # } + + header = struct.pack( + fmt, + IMAGE_MAGIC, + load_addr, + IMAGE_HDR_SIZE, + 0, + img_size, + RAM_LOAD, + 0, + 0, + 0 + (int(spi_freq) << 2), + int(spi_rdcmd, 0), + 0, + ) + + payload[: len(header)] = header + + with open(signed_bin, "wb") as signed: + signed.write(payload) + signed.flush() + signed.close() + + with open(signed_bin, "ab") as signed, open(original_bin, "rb") as original: + signed.write(original.read()) + signed.flush() + signed.close() + original.close() + + +def main(): + """ + Image generateor tool entry point + """ + args = parse_args() + if args.verbose: + print(f" Input = {args.original_bin}") + print(f" Output = {args.signed_bin}") + print(f" Load Address = {hex(args.load_addr)}") + print(f" SPI Frequency = {args.spi_freq}") + print(f" SPI Read Command = {args.spi_rdcmd}") + img_gen( + args.load_addr, + args.spi_freq, + args.spi_rdcmd, + args.original_bin, + args.signed_bin, + ) + + +if __name__ == "__main__": + main() diff --git a/soc/realtek/ec/rts5912/CMakeLists.txt b/soc/realtek/ec/rts5912/CMakeLists.txt new file mode 100644 index 00000000000..219c68e5a8d --- /dev/null +++ b/soc/realtek/ec/rts5912/CMakeLists.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources(soc.c) +zephyr_include_directories(.) + +zephyr_sources_ifdef(CONFIG_PM + device_power.c + power.c + ) + +zephyr_sources_ifdef(CONFIG_DT_HAS_SWJ_CONNECTOR_ENABLED debug_swj.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/realtek/ec/rts5912/Kconfig b/soc/realtek/ec/rts5912/Kconfig new file mode 100644 index 00000000000..aebac7b3d00 --- /dev/null +++ b/soc/realtek/ec/rts5912/Kconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config SOC_SERIES_RTS5912 + select ARM + select CPU_CORTEX_M33 + select SYS_CLOCK_EXISTS + select DYNAMIC_INTERRUPTS + select SOC_EARLY_INIT_HOOK + +if SOC_SERIES_RTS5912 + +config RTS5912_ON_ENTER_CPU_IDLE_HOOK + bool "CPU idle hook enable" + default y + imply ARM_ON_ENTER_CPU_IDLE_HOOK + help + Enables a hook (z_arm_on_enter_cpu_idle()) that is called when + the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()). + If needed, this hook can be used to prevent the CPU from actually + entering sleep by skipping the WFE/WFI instruction. + +endif # SOC_SERIES_RTS5912 diff --git a/soc/realtek/ec/rts5912/Kconfig.defconfig.rts5912 b/soc/realtek/ec/rts5912/Kconfig.defconfig.rts5912 new file mode 100644 index 00000000000..5ff22637497 --- /dev/null +++ b/soc/realtek/ec/rts5912/Kconfig.defconfig.rts5912 @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +if SOC_RTS5912 + +if REALTEK_RTS5912_RTMR + +config PM + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y + +endif # REALTEK_RTS5912_RTMR + +endif # SOC_RTS5912 diff --git a/soc/realtek/ec/rts5912/Kconfig.defconfig.series b/soc/realtek/ec/rts5912/Kconfig.defconfig.series new file mode 100644 index 00000000000..429dbd9c788 --- /dev/null +++ b/soc/realtek/ec/rts5912/Kconfig.defconfig.series @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +if SOC_SERIES_RTS5912 + +config NUM_IRQS + default 240 + +rsource "Kconfig.defconfig.rts5912" + +endif # SOC_SERIES_RTS5912 diff --git a/soc/realtek/ec/rts5912/Kconfig.soc b/soc/realtek/ec/rts5912/Kconfig.soc new file mode 100644 index 00000000000..cf86fe3bcb7 --- /dev/null +++ b/soc/realtek/ec/rts5912/Kconfig.soc @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 +# + +config SOC_SERIES_RTS5912 + bool + select SOC_FAMILY_REALTEK_EC + help + Enable support for REALTEK EC MCU series + +config SOC_SERIES + default "rts5912" if SOC_SERIES_RTS5912 + +config SOC_RTS5912 + bool + select SOC_SERIES_RTS5912 + +config SOC + default "rts5912" if SOC_RTS5912 diff --git a/soc/realtek/ec/rts5912/debug_swj.c b/soc/realtek/ec/rts5912/debug_swj.c new file mode 100644 index 00000000000..c04c9d8c106 --- /dev/null +++ b/soc/realtek/ec/rts5912/debug_swj.c @@ -0,0 +1,27 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Titan Chen + */ + +#include +#include + +#define SWJ_NODE DT_NODELABEL(swj_port) + +PINCTRL_DT_DEFINE(SWJ_NODE); + +const struct pinctrl_dev_config *swj_pcfg = PINCTRL_DT_DEV_CONFIG_GET(SWJ_NODE); + +int swj_connector_init(void) +{ + int err; + + err = pinctrl_apply_state(swj_pcfg, PINCTRL_STATE_DEFAULT); + if (err < 0) { + return err; + } + + return 0; +} diff --git a/soc/realtek/ec/rts5912/debug_swj.h b/soc/realtek/ec/rts5912/debug_swj.h new file mode 100644 index 00000000000..0f610b7285f --- /dev/null +++ b/soc/realtek/ec/rts5912/debug_swj.h @@ -0,0 +1,8 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +int swj_connector_init(void); diff --git a/soc/realtek/ec/rts5912/device_power.c b/soc/realtek/ec/rts5912/device_power.c new file mode 100644 index 00000000000..b346cafd156 --- /dev/null +++ b/soc/realtek/ec/rts5912/device_power.c @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#include +#include + +#include +#include "device_power.h" + +void before_rts5912_sleep(void) +{ + __disable_irq(); + __set_BASEPRI(0); + __ISB(); +} + +void after_rts5912_sleep(void) +{ + __enable_irq(); + __ISB(); +} diff --git a/soc/realtek/ec/rts5912/device_power.h b/soc/realtek/ec/rts5912/device_power.h new file mode 100644 index 00000000000..6a2817fa79f --- /dev/null +++ b/soc/realtek/ec/rts5912/device_power.h @@ -0,0 +1,14 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#ifndef ZEPHYR_SOC_REALTEK_RTS5912_DEVICE_POWER_H +#define ZEPHYR_SOC_REALTEK_RTS5912_DEVICE_POWER_H + +void before_rts5912_sleep(void); +void after_rts5912_sleep(void); + +#endif /* ZEPHYR_SOC_REALTEK_RTS5912_DEVICE_POWER_H */ diff --git a/soc/realtek/ec/rts5912/power.c b/soc/realtek/ec/rts5912/power.c new file mode 100644 index 00000000000..d0702bc4ada --- /dev/null +++ b/soc/realtek/ec/rts5912/power.c @@ -0,0 +1,88 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#include +#include + +#include +#include "device_power.h" + +#define RTS5912_SCCON_REG_BASE ((SYSTEM_Type *)(DT_REG_ADDR(DT_NODELABEL(sccon)))) + +static void realtek_WFI(void) +{ + __DSB(); + __WFI(); +} + +static void rts5912_light_sleep(void) +{ + SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE; + + before_rts5912_sleep(); + + sys_reg->SLPCTRL &= ~SYSTEM_SLPCTRL_SLPMDSEL_Msk; + + realtek_WFI(); + + after_rts5912_sleep(); +} + +static void rts5912_heavy_sleep(void) +{ + SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE; + int main_clk_src_record = sys_reg->SYSCLK; + int PLL_en_record = sys_reg->PLLCTRL; + + before_rts5912_sleep(); + + if ((main_clk_src_record & SYSTEM_SYSCLK_SRC_Msk) == 0x0) { + if ((PLL_en_record & SYSTEM_PLLCTRL_EN_Msk) == 0x0) { + sys_reg->PLLCTRL |= SYSTEM_PLLCTRL_EN_Msk; /* Force to enable PLL */ + while ((sys_reg->PLLCTRL & SYSTEM_PLLCTRL_RDY_Msk) == 0x00) { + ; /* Wait until PLL is ready */ + } + } + sys_reg->SYSCLK |= SYSTEM_SYSCLK_SRC_Msk; /* Switch system clock to PLL */ + } + + sys_reg->SLPCTRL |= SYSTEM_SLPCTRL_SLPMDSEL_Msk; /* Heavy Sleep mode */ + + realtek_WFI(); + + if ((main_clk_src_record & SYSTEM_SYSCLK_SRC_Msk) == 0) { + sys_reg->SYSCLK &= ~SYSTEM_SYSCLK_SRC_Msk; /* Return system clock to 25M */ + if ((PLL_en_record & SYSTEM_PLLCTRL_EN_Msk) == 0x0) { + sys_reg->PLLCTRL &= ~SYSTEM_PLLCTRL_EN_Msk; /* Disable PLL */ + } + } + + after_rts5912_sleep(); +} + +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + + switch (state) { + case PM_STATE_SUSPEND_TO_IDLE: + rts5912_light_sleep(); + break; + case PM_STATE_SUSPEND_TO_RAM: + rts5912_heavy_sleep(); + break; + default: + break; + } +} + +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(state); + ARG_UNUSED(substate_id); + + irq_unlock(0); +} diff --git a/soc/realtek/ec/rts5912/reg/reg_gpio.h b/soc/realtek/ec/rts5912/reg/reg_gpio.h new file mode 100644 index 00000000000..818408c6914 --- /dev/null +++ b/soc/realtek/ec/rts5912/reg/reg_gpio.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Realtek, SIBG-SD7 + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_GPIO_H +#define ZEPHYR_SOC_REALTEK_RTS5912_REG_GPIO_H + +/* + * @brief GPIO Controller (GPIO) + */ + +typedef struct { + volatile uint32_t GCR[132]; +} GPIO_Type; + +/* GCR */ +#define GPIO_GCR_DIR_Pos (0UL) +#define GPIO_GCR_DIR_Msk BIT(GPIO_GCR_DIR_Pos) +#define GPIO_GCR_INDETEN_Pos (1UL) +#define GPIO_GCR_INDETEN_Msk BIT(GPIO_GCR_INDETEN_Pos) +#define GPIO_GCR_INVOLMD_Pos (2UL) +#define GPIO_GCR_INVOLMD_Msk BIT(GPIO_GCR_INVOLMD_Pos) +#define GPIO_GCR_PINSTS_Pos (3UL) +#define GPIO_GCR_PINSTS_Msk BIT(GPIO_GCR_PINSTS_Pos) +#define GPIO_GCR_MFCTRL_Pos (8UL) +#define GPIO_GCR_MFCTRL_Msk GENMASK(10, 8) +#define GPIO_GCR_OUTDRV_Pos (11UL) +#define GPIO_GCR_OUTDRV_Msk BIT(GPIO_GCR_OUTDRV_Pos) +#define GPIO_GCR_SLEWRATE_Pos (12UL) +#define GPIO_GCR_SLEWRATE_Msk BIT(GPIO_GCR_SLEWRATE_Pos) +#define GPIO_GCR_PULLDWEN_Pos (13UL) +#define GPIO_GCR_PULLDWEN_Msk BIT(GPIO_GCR_PULLDWEN_Pos) +#define GPIO_GCR_PULLUPEN_Pos (14UL) +#define GPIO_GCR_PULLUPEN_Msk BIT(GPIO_GCR_PULLUPEN_Pos) +#define GPIO_GCR_SCHEN_Pos (15UL) +#define GPIO_GCR_SCHEN_Msk BIT(GPIO_GCR_SCHEN_Pos) +#define GPIO_GCR_OUTMD_Pos (16UL) +#define GPIO_GCR_OUTMD_Msk BIT(GPIO_GCR_OUTMD_Pos) +#define GPIO_GCR_OUTCTRL_Pos (17UL) +#define GPIO_GCR_OUTCTRL_Msk BIT(GPIO_GCR_OUTCTRL_Pos) +#define GPIO_GCR_INTCTRL_Pos (24UL) +#define GPIO_GCR_INTCTRL_Msk GENMASK(26, 24) +#define GPIO_GCR_INTEN_Pos (28UL) +#define GPIO_GCR_INTEN_Msk BIT(GPIO_GCR_INTEN_Pos) +#define GPIO_GCR_INTSTS_Pos (31UL) +#define GPIO_GCR_INTSTS_Msk BIT(GPIO_GCR_INTSTS_Pos) + +#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_GPIO_H */ diff --git a/soc/realtek/ec/rts5912/reg/reg_rtmr.h b/soc/realtek/ec/rts5912/reg/reg_rtmr.h new file mode 100644 index 00000000000..63957494728 --- /dev/null +++ b/soc/realtek/ec/rts5912/reg/reg_rtmr.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2023 Realtek, SIBG-SD7 + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_RTMR_H +#define ZEPHYR_SOC_REALTEK_RTS5912_REG_RTMR_H + +/* + * @brief RTOS Timer Controller (RTMR) + */ + +typedef struct { + volatile uint32_t LDCNT; + volatile uint32_t CNT; + volatile uint32_t CTRL; + volatile uint32_t INTSTS; +} RTOSTMR_Type; +/* CTRL */ +#define RTOSTMR_CTRL_EN_Pos (0UL) +#define RTOSTMR_CTRL_EN_Msk BIT(RTOSTMR_CTRL_EN_Pos) +#define RTOSTMR_CTRL_MDSEL_Pos (1UL) +#define RTOSTMR_CTRL_MDSEL_Msk BIT(RTOSTMR_CTRL_MDSEL_Pos) +#define RTOSTMR_CTRL_INTEN_Pos (2UL) +#define RTOSTMR_CTRL_INTEN_Msk BIT(RTOSTMR_CTRL_INTEN_Pos) +/* INTSTS */ +#define RTOSTMR_INTSTS_STS_Pos (0UL) +#define RTOSTMR_INTSTS_STS_Msk BIT(RTOSTMR_INTSTS_STS_Pos) + +#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_RTMR_H */ diff --git a/soc/realtek/ec/rts5912/reg/reg_system.h b/soc/realtek/ec/rts5912/reg/reg_system.h new file mode 100644 index 00000000000..673baf4ac35 --- /dev/null +++ b/soc/realtek/ec/rts5912/reg/reg_system.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2023 Realtek, SIBG-SD7 + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_SYSTEM_H +#define ZEPHYR_SOC_REALTEK_RTS5912_REG_SYSTEM_H + +/* + * @brief System Controller (SYSTEM) + */ +typedef struct { + union { + volatile uint32_t I3CCLK; + volatile uint32_t TMRRST; + }; + volatile uint32_t I2CCLK; + volatile uint32_t TMRCLK; + volatile uint32_t PERICLKPWR0; + volatile uint32_t UARTCLK; + volatile uint32_t SYSCLK; + volatile uint32_t ADCCLK; + volatile uint32_t PERICLKPWR1; + volatile const uint32_t RESERVED[24]; + volatile uint32_t SLPCTRL; + volatile const uint32_t RESERVED1[7]; + volatile uint32_t VIVOCTRL; + volatile uint32_t LDOCTRL; + volatile uint32_t RC25MCTRL; + volatile uint32_t PLLCTRL; + volatile const uint32_t RESERVED2[12]; + volatile uint32_t RC32KCTRL; + volatile const uint32_t RESERVED3; + volatile uint32_t PERICLKPWR2; +} SYSTEM_Type; + +/* I3CCLK */ +#define SYSTEM_I3CCLK_I3C0DIV_Pos (0UL) +#define SYSTEM_I3CCLK_I3C0DIV_Msk GENMASK(1, 0) +#define SYSTEM_I3CCLK_I3C1DIV_Pos (2UL) +#define SYSTEM_I3CCLK_I3C1DIV_Msk GENMASK(3, 2) +/* TMRRST */ +#define SYSTEM_TMRRST_TMR0RST_Pos (4UL) +#define SYSTEM_TMRRST_TMR0RST_Msk BIT(SYSTEM_TMRRST_TMR0RST_Pos) +#define SYSTEM_TMRRST_TMR1RST_Pos (5UL) +#define SYSTEM_TMRRST_TMR1RST_Msk BIT(SYSTEM_TMRRST_TMR1RST_Pos) +#define SYSTEM_TMRRST_TMR2RST_Pos (6UL) +#define SYSTEM_TMRRST_TMR2RST_Msk BIT(SYSTEM_TMRRST_TMR2RST_Pos) +#define SYSTEM_TMRRST_TMR3RST_Pos (7UL) +#define SYSTEM_TMRRST_TMR3RST_Msk BIT(SYSTEM_TMRRST_TMR3RST_Pos) +#define SYSTEM_TMRRST_TMR4RST_Pos (8UL) +#define SYSTEM_TMRRST_TMR4RST_Msk BIT(SYSTEM_TMRRST_TMR4RST_Pos) +#define SYSTEM_TMRRST_TMR5RST_Pos (9UL) +#define SYSTEM_TMRRST_TMR5RST_Msk BIT(SYSTEM_TMRRST_TMR5RST_Pos) +/* I2CCLK */ +#define SYSTEM_I2CCLK_I2C0CLKPWR_Pos (0UL) +#define SYSTEM_I2CCLK_I2C0CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C0CLKPWR_Pos) +#define SYSTEM_I2CCLK_I2C0CLKSRC_Pos (1UL) +#define SYSTEM_I2CCLK_I2C0CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C0CLKSRC_Pos) +#define SYSTEM_I2CCLK_I2C0CLKDIV_Pos (2UL) +#define SYSTEM_I2CCLK_I2C0CLKDIV_Msk GENMASK(3, 2) +#define SYSTEM_I2CCLK_I2C1CLKPWR_Pos (4UL) +#define SYSTEM_I2CCLK_I2C1CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C1CLKPWR_Pos) +#define SYSTEM_I2CCLK_I2C1CLKSRC_Pos (5UL) +#define SYSTEM_I2CCLK_I2C1CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C1CLKSRC_Pos) +#define SYSTEM_I2CCLK_I2C1CLKDIV_Pos (6UL) +#define SYSTEM_I2CCLK_I2C1CLKDIV_Msk GENMASK(7, 6) +#define SYSTEM_I2CCLK_I2C2CLKPWR_Pos (8UL) +#define SYSTEM_I2CCLK_I2C2CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C2CLKPWR_Pos) +#define SYSTEM_I2CCLK_I2C2CLKSRC_Pos (9UL) +#define SYSTEM_I2CCLK_I2C2CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C2CLKSRC_Pos) +#define SYSTEM_I2CCLK_I2C2CLKDIV_Pos (10UL) +#define SYSTEM_I2CCLK_I2C2CLKDIV_Msk GENMASK(11, 10) +#define SYSTEM_I2CCLK_I2C3CLKPWR_Pos (12UL) +#define SYSTEM_I2CCLK_I2C3CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C3CLKPWR_Pos) +#define SYSTEM_I2CCLK_I2C3CLKSRC_Pos (13UL) +#define SYSTEM_I2CCLK_I2C3CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C3CLKSRC_Pos) +#define SYSTEM_I2CCLK_I2C3CLKDIV_Pos (14UL) +#define SYSTEM_I2CCLK_I2C3CLKDIV_Msk GENMASK(15, 14) +#define SYSTEM_I2CCLK_I2C4CLKPWR_Pos (16UL) +#define SYSTEM_I2CCLK_I2C4CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C4CLKPWR_Pos) +#define SYSTEM_I2CCLK_I2C4CLKSRC_Pos (17UL) +#define SYSTEM_I2CCLK_I2C4CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C4CLKSRC_Pos) +#define SYSTEM_I2CCLK_I2C4CLKDIV_Pos (18UL) +#define SYSTEM_I2CCLK_I2C4CLKDIV_Msk GENMASK(19, 18) +#define SYSTEM_I2CCLK_I2C5CLKPWR_Pos (20UL) +#define SYSTEM_I2CCLK_I2C5CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C5CLKPWR_Pos) +#define SYSTEM_I2CCLK_I2C5CLKSRC_Pos (21UL) +#define SYSTEM_I2CCLK_I2C5CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C5CLKSRC_Pos) +#define SYSTEM_I2CCLK_I2C5CLKDIV_Pos (22UL) +#define SYSTEM_I2CCLK_I2C5CLKDIV_Msk GENMASK(23, 22) +#define SYSTEM_I2CCLK_I2C6CLKPWR_Pos (24UL) +#define SYSTEM_I2CCLK_I2C6CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C6CLKPWR_Pos) +#define SYSTEM_I2CCLK_I2C6CLKSRC_Pos (25UL) +#define SYSTEM_I2CCLK_I2C6CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C6CLKSRC_Pos) +#define SYSTEM_I2CCLK_I2C6CLKDIV_Pos (26UL) +#define SYSTEM_I2CCLK_I2C6CLKDIV_Msk GENMASK(27, 26) +#define SYSTEM_I2CCLK_I2C7CLKPWR_Pos (28UL) +#define SYSTEM_I2CCLK_I2C7CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C7CLKPWR_Pos) +#define SYSTEM_I2CCLK_I2C7CLKSRC_Pos (29UL) +#define SYSTEM_I2CCLK_I2C7CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C7CLKSRC_Pos) +#define SYSTEM_I2CCLK_I2C7CLKDIV_Pos (30UL) +#define SYSTEM_I2CCLK_I2C7CLKDIV_Msk GENMASK(31, 30) +/* TMRCLK */ +#define SYSTEM_TMRCLK_TMR0DIV_Pos (0UL) +#define SYSTEM_TMRCLK_TMR0DIV_Msk GENMASK(3, 0) +#define SYSTEM_TMRCLK_TMR1DIV_Pos (4UL) +#define SYSTEM_TMRCLK_TMR1DIV_Msk GENMASK(7, 4) +#define SYSTEM_TMRCLK_TMR2DIV_Pos (8UL) +#define SYSTEM_TMRCLK_TMR2DIV_Msk GENMASK(11, 8) +#define SYSTEM_TMRCLK_TMR3DIV_Pos (12UL) +#define SYSTEM_TMRCLK_TMR3DIV_Msk GENMASK(15, 12) +#define SYSTEM_TMRCLK_TMR4DIV_Pos (16UL) +#define SYSTEM_TMRCLK_TMR4DIV_Msk GENMASK(19, 16) +#define SYSTEM_TMRCLK_TMR5DIV_Pos (20UL) +#define SYSTEM_TMRCLK_TMR5DIV_Msk GENMASK(23, 20) +#define SYSTEM_TMRCLK_TMR0PAUSE_Pos (24UL) +#define SYSTEM_TMRCLK_TMR0PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR0PAUSE_Pos) +#define SYSTEM_TMRCLK_TMR1PAUSE_Pos (25UL) +#define SYSTEM_TMRCLK_TMR1PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR1PAUSE_Pos) +#define SYSTEM_TMRCLK_TMR2PAUSE_Pos (26UL) +#define SYSTEM_TMRCLK_TMR2PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR2PAUSE_Pos) +#define SYSTEM_TMRCLK_TMR3PAUSE_Pos (27UL) +#define SYSTEM_TMRCLK_TMR3PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR3PAUSE_Pos) +#define SYSTEM_TMRCLK_TMR4PAUSE_Pos (28UL) +#define SYSTEM_TMRCLK_TMR4PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR4PAUSE_Pos) +#define SYSTEM_TMRCLK_TMR5PAUSE_Pos (29UL) +#define SYSTEM_TMRCLK_TMR5PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR5PAUSE_Pos) +/* PERICLKPWR0 */ +#define SYSTEM_PERICLKPWR0_GPIOCLKPWR_Pos (0UL) +#define SYSTEM_PERICLKPWR0_GPIOCLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_GPIOCLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_TACHO0CLKPWR_Pos (1UL) +#define SYSTEM_PERICLKPWR0_TACHO0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_TACHO0CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_TACHO1CLKPWR_Pos (2UL) +#define SYSTEM_PERICLKPWR0_TACHO1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_TACHO1CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_TACHO2CLKPWR_Pos (3UL) +#define SYSTEM_PERICLKPWR0_TACHO2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_TACHO2CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_TACHO3CLKPWR_Pos (4UL) +#define SYSTEM_PERICLKPWR0_TACHO3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_TACHO3CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PS2CLKPWR_Pos (5UL) +#define SYSTEM_PERICLKPWR0_PS2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PS2CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_KBMCLKPWR_Pos (6UL) +#define SYSTEM_PERICLKPWR0_KBMCLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_KBMCLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PECICLKPWR_Pos (7UL) +#define SYSTEM_PERICLKPWR0_PECICLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PECICLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PL0CLKPWR_Pos (8UL) +#define SYSTEM_PERICLKPWR0_PL0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PL0CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PL1CLKPWR_Pos (9UL) +#define SYSTEM_PERICLKPWR0_PL1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PL1CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM0CLKPWR_Pos (10UL) +#define SYSTEM_PERICLKPWR0_PWM0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM0CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM1CLKPWR_Pos (11UL) +#define SYSTEM_PERICLKPWR0_PWM1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM1CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM2CLKPWR_Pos (12UL) +#define SYSTEM_PERICLKPWR0_PWM2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM2CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM3CLKPWR_Pos (13UL) +#define SYSTEM_PERICLKPWR0_PWM3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM3CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM4CLKPWR_Pos (14UL) +#define SYSTEM_PERICLKPWR0_PWM4CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM4CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM5CLKPWR_Pos (15UL) +#define SYSTEM_PERICLKPWR0_PWM5CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM5CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM6CLKPWR_Pos (16UL) +#define SYSTEM_PERICLKPWR0_PWM6CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM6CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM7CLKPWR_Pos (17UL) +#define SYSTEM_PERICLKPWR0_PWM7CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM7CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM8CLKPWR_Pos (18UL) +#define SYSTEM_PERICLKPWR0_PWM8CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM8CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM9CLKPWR_Pos (19UL) +#define SYSTEM_PERICLKPWR0_PWM9CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM9CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM10CLKPWR_Pos (20UL) +#define SYSTEM_PERICLKPWR0_PWM10CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM10CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PWM11CLKPWR_Pos (21UL) +#define SYSTEM_PERICLKPWR0_PWM11CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM11CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_ESPICLKPWR_Pos (22UL) +#define SYSTEM_PERICLKPWR0_ESPICLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_ESPICLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_KBCCLKPWR_Pos (23UL) +#define SYSTEM_PERICLKPWR0_KBCCLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_KBCCLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_ACPICLKPWR_Pos (24UL) +#define SYSTEM_PERICLKPWR0_ACPICLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_ACPICLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PMPORT0CLKPWR_Pos (25UL) +#define SYSTEM_PERICLKPWR0_PMPORT0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PMPORT0CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PMPORT1CLKPWR_Pos (26UL) +#define SYSTEM_PERICLKPWR0_PMPORT1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PMPORT1CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PMPORT2CLKPWR_Pos (27UL) +#define SYSTEM_PERICLKPWR0_PMPORT2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PMPORT2CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_PMPORT3CLKPWR_Pos (28UL) +#define SYSTEM_PERICLKPWR0_PMPORT3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PMPORT3CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_P80CLKPWR_Pos (29UL) +#define SYSTEM_PERICLKPWR0_P80CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_P80CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_EMI0CLKPWR_Pos (30UL) +#define SYSTEM_PERICLKPWR0_EMI0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_EMI0CLKPWR_Pos) +#define SYSTEM_PERICLKPWR0_EMI1CLKPWR_Pos (31UL) +#define SYSTEM_PERICLKPWR0_EMI1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_EMI1CLKPWR_Pos) +/* UARTCLK */ +#define SYSTEM_UARTCLK_PWR_Pos (0UL) +#define SYSTEM_UARTCLK_PWR_Msk BIT(SYSTEM_UARTCLK_PWR_Pos) +#define SYSTEM_UARTCLK_SRC_Pos (1UL) +#define SYSTEM_UARTCLK_SRC_Msk BIT(SYSTEM_UARTCLK_SRC_Pos) +#define SYSTEM_UARTCLK_DIV_Pos (2UL) +#define SYSTEM_UARTCLK_DIV_Msk GENMASK(3, 2) +/* SYSCLK */ +#define SYSTEM_SYSCLK_SRC_Pos (1UL) +#define SYSTEM_SYSCLK_SRC_Msk BIT(SYSTEM_SYSCLK_SRC_Pos) +#define SYSTEM_SYSCLK_DIV_Pos (2UL) +#define SYSTEM_SYSCLK_DIV_Msk BIT(SYSTEM_SYSCLK_DIV_Pos) +/* ADCCLK */ +#define SYSTEM_ADCCLK_PWR_Pos (0UL) +#define SYSTEM_ADCCLK_PWR_Msk BIT(SYSTEM_ADCCLK_PWR_Pos) +#define SYSTEM_ADCCLK_SRC_Pos (1UL) +#define SYSTEM_ADCCLK_SRC_Msk BIT(SYSTEM_ADCCLK_SRC_Pos) +#define SYSTEM_ADCCLK_DIV_Pos (2UL) +#define SYSTEM_ADCCLK_DIV_Msk GENMASK(4, 2) +/* PERICLKPWR1 */ +#define SYSTEM_PERICLKPWR1_EMI2CLKPWR_Pos (0UL) +#define SYSTEM_PERICLKPWR1_EMI2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI2CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_EMI3CLKPWR_Pos (1UL) +#define SYSTEM_PERICLKPWR1_EMI3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI3CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_EMI4CLKPWR_Pos (2UL) +#define SYSTEM_PERICLKPWR1_EMI4CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI4CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_EMI5CLKPWR_Pos (3UL) +#define SYSTEM_PERICLKPWR1_EMI5CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI5CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_EMI6CLKPWR_Pos (4UL) +#define SYSTEM_PERICLKPWR1_EMI6CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI6CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_EMI7CLKPWR_Pos (5UL) +#define SYSTEM_PERICLKPWR1_EMI7CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI7CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_I3C0CLKPWR_Pos (9UL) +#define SYSTEM_PERICLKPWR1_I3C0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_I3C0CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_I3C1CLKPWR_Pos (10UL) +#define SYSTEM_PERICLKPWR1_I3C1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_I3C1CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_I2CAUTOCLKPWR_Pos (11UL) +#define SYSTEM_PERICLKPWR1_I2CAUTOCLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_I2CAUTOCLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_MCCLKPWR_Pos (12UL) +#define SYSTEM_PERICLKPWR1_MCCLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_MCCLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_TMR0CLKPWR_Pos (13UL) +#define SYSTEM_PERICLKPWR1_TMR0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR0CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_TMR1CLKPWR_Pos (14UL) +#define SYSTEM_PERICLKPWR1_TMR1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR1CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_TMR2CLKPWR_Pos (15UL) +#define SYSTEM_PERICLKPWR1_TMR2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR2CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_TMR3CLKPWR_Pos (16UL) +#define SYSTEM_PERICLKPWR1_TMR3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR3CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_TMR4CLKPWR_Pos (17UL) +#define SYSTEM_PERICLKPWR1_TMR4CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR4CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_TMR5CLKPWR_Pos (18UL) +#define SYSTEM_PERICLKPWR1_TMR5CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR5CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_RTMRCLKPWR_Pos (19UL) +#define SYSTEM_PERICLKPWR1_RTMRCLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_RTMRCLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_SLWTMR0CLKPWR_Pos (20UL) +#define SYSTEM_PERICLKPWR1_SLWTMR0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_SLWTMR0CLKPWR_Pos) +#define SYSTEM_PERICLKPWR1_SLWTMR1CLKPWR_Pos (21UL) +#define SYSTEM_PERICLKPWR1_SLWTMR1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_SLWTMR1CLKPWR_Pos) +/* SLPCTRL */ +#define SYSTEM_SLPCTRL_SLPMDSEL_Pos (1UL) +#define SYSTEM_SLPCTRL_SLPMDSEL_Msk BIT(SYSTEM_SLPCTRL_SLPMDSEL_Pos) +#define SYSTEM_SLPCTRL_ESPIWKEN_Pos (2UL) +#define SYSTEM_SLPCTRL_ESPIWKEN_Msk BIT(SYSTEM_SLPCTRL_ESPIWKEN_Pos) +#define SYSTEM_SLPCTRL_PS2WKEN_Pos (3UL) +#define SYSTEM_SLPCTRL_PS2WKEN_Msk BIT(SYSTEM_SLPCTRL_PS2WKEN_Pos) +#define SYSTEM_SLPCTRL_I2CWKEN_Pos (4UL) +#define SYSTEM_SLPCTRL_I2CWKEN_Msk BIT(SYSTEM_SLPCTRL_I2CWKEN_Pos) +#define SYSTEM_SLPCTRL_GPIOWKEN_Pos (5UL) +#define SYSTEM_SLPCTRL_GPIOWKEN_Msk BIT(SYSTEM_SLPCTRL_GPIOWKEN_Pos) +/* VIVOCTRL */ +#define SYSTEM_VIVOCTRL_VIN0MD_Pos (0UL) +#define SYSTEM_VIVOCTRL_VIN0MD_Msk BIT(SYSTEM_VIVOCTRL_VIN0MD_Pos) +#define SYSTEM_VIVOCTRL_VIN1MD_Pos (1UL) +#define SYSTEM_VIVOCTRL_VIN1MD_Msk BIT(SYSTEM_VIVOCTRL_VIN1MD_Pos) +#define SYSTEM_VIVOCTRL_VIN2MD_Pos (2UL) +#define SYSTEM_VIVOCTRL_VIN2MD_Msk BIT(SYSTEM_VIVOCTRL_VIN2MD_Pos) +#define SYSTEM_VIVOCTRL_VIN3MD_Pos (3UL) +#define SYSTEM_VIVOCTRL_VIN3MD_Msk BIT(SYSTEM_VIVOCTRL_VIN3MD_Pos) +#define SYSTEM_VIVOCTRL_VIN4MD_Pos (4UL) +#define SYSTEM_VIVOCTRL_VIN4MD_Msk BIT(SYSTEM_VIVOCTRL_VIN4MD_Pos) +#define SYSTEM_VIVOCTRL_VIN5MD_Pos (5UL) +#define SYSTEM_VIVOCTRL_VIN5MD_Msk BIT(SYSTEM_VIVOCTRL_VIN5MD_Pos) +#define SYSTEM_VIVOCTRL_VIN0STS_Pos (6UL) +#define SYSTEM_VIVOCTRL_VIN0STS_Msk BIT(SYSTEM_VIVOCTRL_VIN0STS_Pos) +#define SYSTEM_VIVOCTRL_VIN1STS_Pos (7UL) +#define SYSTEM_VIVOCTRL_VIN1STS_Msk BIT(SYSTEM_VIVOCTRL_VIN1STS_Pos) +#define SYSTEM_VIVOCTRL_VIN2STS_Pos (8UL) +#define SYSTEM_VIVOCTRL_VIN2STS_Msk BIT(SYSTEM_VIVOCTRL_VIN2STS_Pos) +#define SYSTEM_VIVOCTRL_VIN3STS_Pos (9UL) +#define SYSTEM_VIVOCTRL_VIN3STS_Msk BIT(SYSTEM_VIVOCTRL_VIN3STS_Pos) +#define SYSTEM_VIVOCTRL_VIN4STS_Pos (10UL) +#define SYSTEM_VIVOCTRL_VIN4STS_Msk BIT(SYSTEM_VIVOCTRL_VIN4STS_Pos) +#define SYSTEM_VIVOCTRL_VIN5STS_Pos (11UL) +#define SYSTEM_VIVOCTRL_VIN5STS_Msk BIT(SYSTEM_VIVOCTRL_VIN5STS_Pos) +#define SYSTEM_VIVOCTRL_VIN0POL_Pos (12UL) +#define SYSTEM_VIVOCTRL_VIN0POL_Msk BIT(SYSTEM_VIVOCTRL_VIN0POL_Pos) +#define SYSTEM_VIVOCTRL_VIN1POL_Pos (13UL) +#define SYSTEM_VIVOCTRL_VIN1POL_Msk BIT(SYSTEM_VIVOCTRL_VIN1POL_Pos) +#define SYSTEM_VIVOCTRL_VIN2POL_Pos (14UL) +#define SYSTEM_VIVOCTRL_VIN2POL_Msk BIT(SYSTEM_VIVOCTRL_VIN2POL_Pos) +#define SYSTEM_VIVOCTRL_VIN3POL_Pos (15UL) +#define SYSTEM_VIVOCTRL_VIN3POL_Msk BIT(SYSTEM_VIVOCTRL_VIN3POL_Pos) +#define SYSTEM_VIVOCTRL_VIN4POL_Pos (16UL) +#define SYSTEM_VIVOCTRL_VIN4POL_Msk BIT(SYSTEM_VIVOCTRL_VIN4POL_Pos) +#define SYSTEM_VIVOCTRL_VIN5POL_Pos (17UL) +#define SYSTEM_VIVOCTRL_VIN5POL_Msk BIT(SYSTEM_VIVOCTRL_VIN5POL_Pos) +#define SYSTEM_VIVOCTRL_REGWREN_Pos (30UL) +#define SYSTEM_VIVOCTRL_REGWREN_Msk BIT(SYSTEM_VIVOCTRL_REGWREN_Pos) +#define SYSTEM_VIVOCTRL_VOUTMD_Pos (31UL) +#define SYSTEM_VIVOCTRL_VOUTMD_Msk BIT(SYSTEM_VIVOCTRL_VOUTMD_Pos) +/* LDOCTRL */ +#define SYSTEM_LDOCTRL_LDO2EN_Pos (3UL) +#define SYSTEM_LDOCTRL_LDO2EN_Msk BIT(SYSTEM_LDOCTRL_LDO2EN_Pos) +#define SYSTEM_LDOCTRL_LDO3EN_Pos (7UL) +#define SYSTEM_LDOCTRL_LDO3EN_Msk BIT(SYSTEM_LDOCTRL_LDO3EN_Pos) +/* RC25MCTRL */ +#define SYSTEM_RC25MCTRL_EN_Pos (0UL) +#define SYSTEM_RC25MCTRL_EN_Msk BIT(SYSTEM_RC25MCTRL_EN_Pos) +#define SYSTEM_RC25MCTRL_CALCURR_Pos (1UL) +#define SYSTEM_RC25MCTRL_CALCURR_Msk GENMASK(7, 1) +/* PLLCTRL */ +#define SYSTEM_PLLCTRL_EN_Pos (0UL) +#define SYSTEM_PLLCTRL_EN_Msk BIT(SYSTEM_PLLCTRL_EN_Pos) +#define SYSTEM_PLLCTRL_RDY_Pos (19UL) +#define SYSTEM_PLLCTRL_RDY_Msk BIT(SYSTEM_PLLCTRL_RDY_Pos) +/* RC32KCTRL */ +#define SYSTEM_RC32KCTRL_EN_Pos (0UL) +#define SYSTEM_RC32KCTRL_EN_Msk BIT(SYSTEM_RC32KCTRL_EN_Pos) +#define SYSTEM_RC32KCTRL_CAL_Pos (1UL) +#define SYSTEM_RC32KCTRL_CAL_Msk GENMASK(7, 1) +/* PERICLKPWR2 */ +#define SYSTEM_PERICLKPWR2_RTCCLKPWR_Pos (0UL) +#define SYSTEM_PERICLKPWR2_RTCCLKPWR_Msk BIT(SYSTEM_PERICLKPWR2_RTCCLKPWR_Pos) +#define SYSTEM_PERICLKPWR2_WDTCLKPWR_Pos (1UL) +#define SYSTEM_PERICLKPWR2_WDTCLKPWR_Msk BIT(SYSTEM_PERICLKPWR2_WDTCLKPWR_Pos) +#define SYSTEM_PERICLKPWR2_PWRBTNCLKPWR_Pos (2UL) +#define SYSTEM_PERICLKPWR2_PWRBTNCLKPWR_Msk BIT(SYSTEM_PERICLKPWR2_PWRBTNCLKPWR_Pos) +#define SYSTEM_PERICLKPWR2_RC32KSRC_Pos (30UL) +#define SYSTEM_PERICLKPWR2_RC32KSRC_Msk GENMASK(31, 30) + +#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_SYSTEM_H */ diff --git a/soc/realtek/ec/rts5912/soc.c b/soc/realtek/ec/rts5912/soc.c new file mode 100644 index 00000000000..ce1e254e051 --- /dev/null +++ b/soc/realtek/ec/rts5912/soc.c @@ -0,0 +1,38 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng / Titan Chen + */ + +#include +#include +#include +#include +#include "debug_swj.h" + +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#if defined(CONFIG_RTS5912_ON_ENTER_CPU_IDLE_HOOK) +bool z_arm_on_enter_cpu_idle(void) +{ + /* Returning false prevent device goes to sleep mode */ + return false; +} +#endif + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + */ +void soc_early_init_hook(void) +{ + int ret; + + /* Apply device related preinit configuration */ + ret = swj_connector_init(); + if (ret < 0) { + LOG_ERR("SWJ init failed"); + } +} diff --git a/soc/realtek/ec/rts5912/soc.h b/soc/realtek/ec/rts5912/soc.h new file mode 100644 index 00000000000..3824ae900fb --- /dev/null +++ b/soc/realtek/ec/rts5912/soc.h @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7 + * Author: Lin Yu-Cheng + */ + +#ifndef SOC_REALTEK_RTS5912_H_ +#define SOC_REALTEK_RTS5912_H_ + +#include + +#endif /* SOC_REALTEK_RTS5912_H_ */ diff --git a/soc/realtek/ec/soc.yml b/soc/realtek/ec/soc.yml new file mode 100644 index 00000000000..928ceedb635 --- /dev/null +++ b/soc/realtek/ec/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: rts5912 diff --git a/soc/sensry/ganymed/sy1xx/common/pinctrl_soc.h b/soc/sensry/ganymed/sy1xx/common/pinctrl_soc.h new file mode 100644 index 00000000000..5a124fa0783 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/pinctrl_soc.h @@ -0,0 +1,72 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#ifndef GANYMED_SY1XX_PINCTRL_SOC_H +#define GANYMED_SY1XX_PINCTRL_SOC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SY1XX_SCHMITT_ENABLE 1U +#define SY1XX_PULL_UP_ENABLE 1U +#define SY1XX_PULL_DOWN_ENABLE 1U +#define SY1XX_TRISTATE_ENABLE 1U +#define SY1XX_OUTPUT_ENABLE 1U + +#define SY1XX_PAD_SCHMITT_OFFS 7 +#define SY1XX_PAD_PULL_UP_OFFS 5 +#define SY1XX_PAD_PULL_DOWN_OFFS 4 +#define SY1XX_PAD_DRIVE_OFFS 2 +#define SY1XX_PAD_TRISTATE_OFFS 1 +#define SY1XX_PAD_DIR_OFFS 0 + +/** Type for SY1XX pin. */ +typedef struct { + /** address of pin config register */ + uint32_t addr; + /** intra register offset (8bit cfg per pin) */ + uint32_t iro; + /** config for pin (8bit), describes pull-up/down, ... */ + uint32_t cfg; +} pinctrl_soc_pin_t; + +#define Z_PINCTRL_CFG(node) \ + ( \ + \ + (SY1XX_SCHMITT_ENABLE * DT_PROP(node, input_schmitt_enable)) \ + << SY1XX_PAD_SCHMITT_OFFS | \ + (SY1XX_PULL_UP_ENABLE * DT_PROP(node, bias_pull_up)) << SY1XX_PAD_PULL_UP_OFFS | \ + (SY1XX_PULL_DOWN_ENABLE * DT_PROP(node, bias_pull_down)) \ + << SY1XX_PAD_PULL_DOWN_OFFS | \ + (SY1XX_TRISTATE_ENABLE * DT_PROP(node, bias_high_impedance)) \ + << SY1XX_PAD_TRISTATE_OFFS | \ + (SY1XX_OUTPUT_ENABLE & (1 - DT_PROP(node, input_enable))) << SY1XX_PAD_DIR_OFFS \ + \ + ) + +#define Z_PINCTRL_STATE_PIN_INIT(node, pr, idx) \ + { \ + \ + .addr = DT_PROP_BY_IDX(DT_PHANDLE_BY_IDX(node, pr, idx), pinmux, 0), \ + .iro = DT_PROP_BY_IDX(DT_PHANDLE_BY_IDX(node, pr, idx), pinmux, 1), \ + .cfg = Z_PINCTRL_CFG(DT_PHANDLE_BY_IDX(node, pr, idx)) \ + \ + }, + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { \ + DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* GANYMED_SY1XX_PINCTRL_SOC_H */