diff --git a/drivers/misc/nordic_vpr_launcher/Kconfig b/drivers/misc/nordic_vpr_launcher/Kconfig index 6aeabcd251c..d00bcc583f9 100644 --- a/drivers/misc/nordic_vpr_launcher/Kconfig +++ b/drivers/misc/nordic_vpr_launcher/Kconfig @@ -4,7 +4,8 @@ config NORDIC_VPR_LAUNCHER bool "Nordic VPR coprocessor launcher" default y - depends on DT_HAS_NORDIC_NRF_VPR_COPROCESSOR_ENABLED + depends on DT_HAS_NORDIC_NRF_VPR_COPROCESSOR_ENABLED && \ + $(dt_compat_any_has_prop,$(DT_COMPAT_NORDIC_NRF_VPR_COPROCESSOR),execution-memory) help When enabled, the VPR coprocessors will be automatically launched during system initialization. diff --git a/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c b/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c index 5bd43f87fb9..b28ebec6b5c 100644 --- a/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c +++ b/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c @@ -34,6 +34,11 @@ static int nordic_vpr_launcher_init(const struct device *dev) { const struct nordic_vpr_launcher_config *config = dev->config; + /* Do nothing if execution memory is not specified for a given VPR. */ + if (config->exec_addr == 0) { + return 0; + } + #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory) if (config->size > 0U) { LOG_DBG("Loading VPR (%p) from %p to %p (%zu bytes)", config->vpr, @@ -63,16 +68,20 @@ static int nordic_vpr_launcher_init(const struct device *dev) (DT_REG_ADDR(node_id) + \ COND_CODE_0(DT_FIXED_PARTITION_EXISTS(node_id), (0), (DT_REG_ADDR(DT_GPARENT(node_id))))) +#define NEEDS_COPYING(inst) UTIL_AND(DT_INST_NODE_HAS_PROP(inst, execution_memory), \ + DT_INST_NODE_HAS_PROP(inst, source_memory)) + #define NORDIC_VPR_LAUNCHER_DEFINE(inst) \ - IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \ + IF_ENABLED(NEEDS_COPYING(inst), \ (BUILD_ASSERT((DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)) <= \ DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory))), \ "Execution memory exceeds source memory size");)) \ \ static const struct nordic_vpr_launcher_config config##inst = { \ .vpr = (NRF_VPR_Type *)DT_INST_REG_ADDR(inst), \ - .exec_addr = VPR_ADDR(DT_INST_PHANDLE(inst, execution_memory)), \ - IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, execution_memory), \ + (.exec_addr = VPR_ADDR(DT_INST_PHANDLE(inst, execution_memory)),)) \ + IF_ENABLED(NEEDS_COPYING(inst), \ (.src_addr = VPR_ADDR(DT_INST_PHANDLE(inst, source_memory)), \ .size = DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)),))}; \ \ diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index 3f909b3e990..5e4cd6fb549 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -112,12 +112,17 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = { #define NRF_PSEL_TDM(reg, line) ((NRF_TDM_Type *)reg)->PSEL.line #endif -#if defined(CONFIG_SOC_NRF54L15_CPUAPP) -#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || defined(CONFIG_MSPI_NRFE) -#define NRF_PSEL_SDP_MSPI(psel) \ +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || \ + defined(CONFIG_MSPI_NRFE) || \ + DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(nordic_nrf_vpr_coprocessor, pinctrl_0) +#if defined(CONFIG_SOC_SERIES_NRF54LX) +#define NRF_PSEL_SDP_MSPI(psel) \ nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR); +#elif defined(CONFIG_SOC_SERIES_NRF54HX) +/* On nRF54H, pin routing is controlled by secure domain, via UICR. */ +#define NRF_PSEL_SDP_MSPI(psel) #endif -#endif +#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || ... */ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) @@ -472,8 +477,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, input = NRF_GPIO_PIN_INPUT_CONNECT; break; #endif /* defined(NRF_PSEL_TWIS) */ -#if defined(CONFIG_SOC_NRF54L15_CPUAPP) -#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) +#if defined(NRF_PSEL_SDP_MSPI) case NRF_FUN_SDP_MSPI_CS0: case NRF_FUN_SDP_MSPI_CS1: case NRF_FUN_SDP_MSPI_CS2: @@ -492,8 +496,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, dir = NRF_GPIO_PIN_DIR_OUTPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; break; -#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) */ -#endif /* CONFIG_SOC_NRF54L15_CPUAPP */ +#endif /* defined(NRF_PSEL_SDP_MSPI) */ default: return -ENOTSUP; } diff --git a/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml b/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml index 43deaeb6d3b..8760e828880 100644 --- a/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml +++ b/dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml @@ -9,14 +9,17 @@ description: | VPR is a RISC-V CPU implementation. VPR instances are exposed to other CPUs as peripherals. -include: base.yaml +include: [base.yaml, pinctrl-device.yaml] properties: execution-memory: type: phandle - required: true description: | - Memory area from which the VPR core will execute. + Memory area from which the VPR code will execute. + If not specified, the VPR coprocessor will not be launched automatically + by the nordic_vpr_launcher driver when the node is enabled. In such case, + the launching is supposed to be done explicitly by the user code, in some + custom way presumably. source-memory: type: phandle diff --git a/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c b/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c index b76fac86bcd..a9e8b3de7a9 100644 --- a/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c +++ b/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c @@ -18,6 +18,9 @@ #define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \ DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can) +#define SOFTPERIPH_BASE DT_REG_ADDR(DT_NODELABEL(softperiph_ram)) +#define SOFTPERIPH_SIZE DT_REG_SIZE(DT_NODELABEL(softperiph_ram)) + static struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS, @@ -40,6 +43,10 @@ static struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("CAN121_MCAN", CAN121_BASE, REGION_RAM_NOCACHE_ATTR(CAN121_BASE, CAN121_SIZE)), #endif +#if DT_NODE_EXISTS(DT_NODELABEL(softperiph_ram)) + MPU_REGION_ENTRY("SOFTPERIPH_RAM", SOFTPERIPH_BASE, + REGION_RAM_NOCACHE_ATTR(SOFTPERIPH_BASE, SOFTPERIPH_SIZE)), +#endif }; const struct arm_mpu_config mpu_config = {