diff --git a/boards/nordic/nrf54h20dk/Kconfig.defconfig b/boards/nordic/nrf54h20dk/Kconfig.defconfig index f55de22275c..d2ac190fd17 100644 --- a/boards/nordic/nrf54h20dk/Kconfig.defconfig +++ b/boards/nordic/nrf54h20dk/Kconfig.defconfig @@ -9,28 +9,33 @@ config BT_HCI_IPC config MAX_THREAD_BYTES default 3 if USERSPACE -endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT -if BOARD_NRF54H20DK_NRF54H20_CPURAD +if !USE_DT_CODE_PARTITION -config MAX_THREAD_BYTES - default 3 if USERSPACE +# Application core firmware must start at this offset when not using MCUboot. +# However, the default 'zephyr,code-partition' in DT is set for MCUboot. +config FLASH_LOAD_OFFSET + default $(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition) -endif # BOARD_NRF54H20DK_NRF54H20_CPURAD +# This is meant to span 'cpuapp_boot_partition' and 'cpuapp_slot0_partition' +# in the default memory map. +config FLASH_LOAD_SIZE + default $(add_hex, $(dt_nodelabel_reg_addr_hex,cpuapp_slot0_partition), \ + $(dt_nodelabel_reg_size_hex,cpuapp_slot0_partition), \ + -$(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition)) -if BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON +endif # !USE_DT_CODE_PARTITION -config ROM_START_OFFSET - default 0x800 if BOOTLOADER_MCUBOOT - -config FLASH_LOAD_OFFSET - default 0x30000 if !USE_DT_CODE_PARTITION +endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP -endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON +if BOARD_NRF54H20DK_NRF54H20_CPURAD -if BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON +config MAX_THREAD_BYTES + default 3 if USERSPACE config ROM_START_OFFSET default 0x800 if BOOTLOADER_MCUBOOT -endif # BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON +endif # BOARD_NRF54H20DK_NRF54H20_CPURAD diff --git a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk index c509f968db6..62ad7a0d21c 100644 --- a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk +++ b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk @@ -2,13 +2,9 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_NRF54H20DK - select SOC_NRF54H20_CPUAPP if (BOARD_NRF54H20DK_NRF54H20_CPUAPP || \ - BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON) - select SOC_NRF54H20_CPURAD if (BOARD_NRF54H20DK_NRF54H20_CPURAD || \ - BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON) + select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP + select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD select SOC_NRF54H20_CPUPPR if (BOARD_NRF54H20DK_NRF54H20_CPUPPR || \ BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP) select SOC_NRF54H20_CPUFLPR if (BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \ BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP) - select SOC_NRF54H20_IRON if (BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON || \ - BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON) diff --git a/boards/nordic/nrf54h20dk/Kconfig.sysbuild b/boards/nordic/nrf54h20dk/Kconfig.sysbuild new file mode 100644 index 00000000000..29bd62b4992 --- /dev/null +++ b/boards/nordic/nrf54h20dk/Kconfig.sysbuild @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54H20DK_NRF54H20_CPURAD + +config NRF_DEFAULT_EMPTY + default y + +endif # BOARD_NRF54H20DK_NRF54H20_CPURAD diff --git a/boards/nordic/nrf54h20dk/board.cmake b/boards/nordic/nrf54h20dk/board.cmake index 093155e9322..b9383042b0c 100644 --- a/boards/nordic/nrf54h20dk/board.cmake +++ b/boards/nordic/nrf54h20dk/board.cmake @@ -2,10 +2,7 @@ include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR - CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR - CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON OR - CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON) +if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD) if(CONFIG_SOC_NRF54H20_CPUAPP) set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuapp.JLinkScript) else() @@ -17,7 +14,7 @@ if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR endif() if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUFLPR) - if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR) + if(CONFIG_SOC_NRF54H20_CPUPPR) set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuppr.JLinkScript) else() set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuflpr.JLinkScript) diff --git a/boards/nordic/nrf54h20dk/board.yml b/boards/nordic/nrf54h20dk/board.yml index a54cf1ae549..2d3d40c20e0 100644 --- a/boards/nordic/nrf54h20dk/board.yml +++ b/boards/nordic/nrf54h20dk/board.yml @@ -9,10 +9,6 @@ board: cpucluster: cpuppr - name: xip cpucluster: cpuflpr - - name: iron - cpucluster: cpuapp - - name: iron - cpucluster: cpurad revision: format: major.minor.patch default: "0.9.0" diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi index 94cda5e8ee2..f31d909b6f9 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi @@ -7,17 +7,17 @@ / { ipc { cpusec_cpuapp_ipc: ipc-1-2 { - compatible = "zephyr,ipc-icmsg"; + compatible = "nordic,ironside-call"; status = "disabled"; - dcache-alignment = <32>; + memory-region = <&cpusec_cpuapp_ipc_shm>; mboxes = <&cpusec_bellboard 12>, <&cpuapp_bellboard 0>; }; cpusec_cpurad_ipc: ipc-1-3 { - compatible = "zephyr,ipc-icmsg"; + compatible = "nordic,ironside-call"; status = "disabled"; - dcache-alignment = <32>; + memory-region = <&cpusec_cpurad_ipc_shm>; mboxes = <&cpusec_bellboard 18>, <&cpurad_bellboard 0>; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi deleted file mode 100644 index a44db40538d..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* This file is to be merged with the original ipc_conf.dtsi in the future. */ - -/ { - ipc { - /delete-node/ ipc-1-2; - /delete-node/ ipc-1-3; - - cpusec_cpuapp_ipc: ipc-1-2 { - compatible = "nordic,ironside-call"; - memory-region = <&cpusec_cpuapp_ipc_shm>; - mboxes = <&cpusec_bellboard 12>, - <&cpuapp_bellboard 0>; - status = "disabled"; - }; - - cpusec_cpurad_ipc: ipc-1-3 { - compatible = "nordic,ironside-call"; - memory-region = <&cpusec_cpurad_ipc_shm>; - mboxes = <&cpusec_bellboard 18>, - <&cpurad_bellboard 0>; - status = "disabled"; - }; - }; -}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index f2937402554..b6a53955c60 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -7,170 +7,109 @@ / { reserved-memory { - cpuapp_ram0x_region: memory@2f010000 { - compatible = "nordic,owned-memory"; - reg = <0x2f010000 DT_SIZE_K(260)>; - status = "disabled"; - nordic,access = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f010000 0x41000>; - - cpusec_cpuapp_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; - - cpuapp_cpusec_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; - - cpuapp_data: memory@1000 { - reg = <0x1000 DT_SIZE_K(256)>; - }; + cpuapp_data: memory@2f000000 { + reg = <0x2f000000 DT_SIZE_K(760)>; }; - cpurad_ram0x_region: memory@2f051000 { - compatible = "nordic,owned-memory"; - reg = <0x2f051000 DT_SIZE_K(4)>; - status = "disabled"; - nordic,access = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f051000 0x1000>; - - cpusec_cpurad_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; + etr_buffer: memory@2f0be000 { + reg = <0x2f0be000 DT_SIZE_K(4)>; + }; - cpurad_cpusec_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; + cpuapp_cpurad_ipc_shm: memory@2f0bf000 { + reg = <0x2f0bf000 DT_SIZE_K(2)>; }; - etr_buf_ram0x_region: memory@2f0be000 { - compatible = "nordic,owned-memory"; - reg = <0x2f0be000 DT_SIZE_K(4)>; - status = "disabled"; - nordic,access = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f0be000 0x1000>; + cpurad_cpuapp_ipc_shm: memory@2f0bf800 { + reg = <0x2f0bf800 DT_SIZE_K(2)>; + }; - /* TODO In future move this region to cpuapp_ram0x_region. */ - etr_buffer: memory@0 { - reg = <0x0 DT_SIZE_K(4)>; - }; + cpuapp_cpusys_ipc_shm: memory@2f88f600 { + reg = <0x2f88f600 0x80>; }; - cpuapp_cpurad_ram0x_region: memory@2f0bf000 { - compatible = "nordic,owned-memory"; - reg = <0x2f0bf000 DT_SIZE_K(4)>; - status = "disabled"; - nordic,access = , - ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f0bf000 0x1000>; + cpusys_cpuapp_ipc_shm: memory@2f88f680 { + reg = <0x2f88f680 0x80>; + }; - cpuapp_cpurad_ipc_shm: memory@0 { - reg = <0x0 DT_SIZE_K(2)>; - }; + cpurad_cpusys_ipc_shm: memory@2f88f700 { + reg = <0x2f88f700 0x80>; + }; - cpurad_cpuapp_ipc_shm: memory@800 { - reg = <0x800 DT_SIZE_K(2)>; - }; + cpusys_cpurad_ipc_shm: memory@2f88f780 { + reg = <0x2f88f780 0x80>; }; - cpuapp_cpusys_ipc_shm: memory@2f88fce0 { - reg = <0x2f88fce0 0x80>; + cpusec_cpurad_ipc_shm: memory@2f88f800 { + reg = <0x2f88f800 0x80>; }; - cpusys_cpuapp_ipc_shm: memory@2f88fd60 { - reg = <0x2f88fd60 0x80>; + cpurad_ironside_se_event_report: memory@2f88f880 { + reg = <0x2f88f880 0x100>; }; - cpurad_cpusys_ipc_shm: memory@2f88fe00 { - reg = <0x2f88fe00 0x80>; + cpurad_ironside_se_boot_report: memory@2f88f980 { + reg = <0x2f88f980 0x200>; }; - cpusys_cpurad_ipc_shm: memory@2f88fe80 { - reg = <0x2f88fe80 0x80>; + cpusec_cpuapp_ipc_shm: memory@2f88fb80 { + reg = <0x2f88fb80 0x80>; }; - /* - * NOTE: FLPR has a direct bridge with RAM21 that bypasses MPC. - * This means that when this region is marked as non-executable, - * only FLPR can execute code from it. - */ - ram21_region: memory@2f890000 { - compatible = "nordic,owned-memory"; - status = "disabled"; - reg = <0x2f890000 DT_SIZE_K(64)>; - nordic,access = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f890000 0x10000>; + cpuapp_ironside_se_event_report: memory@2f88fc00 { + reg = <0x2f88fc00 0x100>; + }; - cpuflpr_code_data: memory@0 { - reg = <0x0 DT_SIZE_K(46)>; - }; + cpuapp_ironside_se_boot_report: memory@2f88fd00 { + reg = <0x2f88fd00 0x200>; + }; - cpuapp_cpuflpr_ipc_shm: memory@b800 { - reg = <0xb800 DT_SIZE_K(1)>; - }; + cpuflpr_code_data: memory@2f890000 { + reg = <0x2f890000 DT_SIZE_K(46)>; + }; - cpuflpr_cpuapp_ipc_shm: memory@bc00 { - reg = <0xbc00 DT_SIZE_K(1)>; - }; + cpuapp_cpuflpr_ipc_shm: memory@2f89b800 { + reg = <0x2f89b800 DT_SIZE_K(1)>; + }; - dma_fast_region: memory@c000 { - compatible = "zephyr,memory-region"; - reg = <0xc000 DT_SIZE_K(16)>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM21"; - zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>; - }; + cpuflpr_cpuapp_ipc_shm: memory@2f89bc00 { + reg = <0x2f89bc00 DT_SIZE_K(1)>; }; - cpuppr_ram3x_region: memory@2fc00000 { - compatible = "nordic,owned-memory"; - reg = <0x2fc00000 DT_SIZE_K(64)>; + dma_fast_region: memory@2f89c000 { + compatible = "zephyr,memory-region"; + reg = <0x2f89c000 DT_SIZE_K(16)>; status = "disabled"; - nordic,access = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2fc00000 0x10000>; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM21"; + zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>; + }; - cpuppr_code_data: memory@0 { - reg = <0x0 DT_SIZE_K(62)>; - }; + cpuppr_code_data: memory@2fc00000 { + reg = <0x2fc00000 DT_SIZE_K(62)>; + }; - cpuapp_cpuppr_ipc_shm: memory@f800 { - reg = <0xf800 DT_SIZE_K(1)>; - }; + cpuapp_cpuppr_ipc_shm: memory@2fc0f800 { + reg = <0x2fc0f800 DT_SIZE_K(1)>; + }; - cpuppr_cpuapp_ipc_shm: memory@fc00 { - reg = <0xfc00 DT_SIZE_K(1)>; - }; + cpuppr_cpuapp_ipc_shm: memory@2fc0fc00 { + reg = <0x2fc0fc00 DT_SIZE_K(1)>; }; cpuapp_dma_region: memory@2fc12000 { - compatible = "nordic,owned-memory", "zephyr,memory-region"; + compatible = "zephyr,memory-region"; reg = <0x2fc12000 DT_SIZE_K(4)>; status = "disabled"; #memory-region-cells = <0>; - nordic,access = ; zephyr,memory-region = "DMA_RAM3x_APP"; zephyr,memory-attr = <( DT_MEM_DMA )>; }; cpurad_dma_region: memory@2fc13000 { - compatible = "nordic,owned-memory", "zephyr,memory-region"; + compatible = "zephyr,memory-region"; reg = <0x2fc13000 DT_SIZE_K(1)>; status = "disabled"; #memory-region-cells = <0>; - nordic,access = ; zephyr,memory-region = "DMA_RAM3x_RAD"; zephyr,memory-attr = <( DT_MEM_DMA )>; }; @@ -187,27 +126,21 @@ }; &mram1x { - cpurad_rx_partitions: cpurad-rx-partitions { - compatible = "nordic,owned-partitions", "fixed-partitions"; - status = "disabled"; - nordic,access = ; + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - cpurad_slot0_partition: partition@54000 { - reg = <0x54000 DT_SIZE_K(256)>; + cpuapp_boot_partition: partition@30000 { + reg = <0x30000 DT_SIZE_K(64)>; }; - }; - cpuapp_rx_partitions: cpuapp-rx-partitions { - compatible = "nordic,owned-partitions", "fixed-partitions"; - status = "disabled"; - nordic,access = ; - #address-cells = <1>; - #size-cells = <1>; + cpuapp_slot0_partition: partition@40000 { + reg = <0x40000 DT_SIZE_K(328)>; + }; - cpuapp_slot0_partition: partition@94000 { - reg = <0x94000 DT_SIZE_K(320)>; + cpurad_slot0_partition: partition@92000 { + reg = <0x92000 DT_SIZE_K(328)>; }; cpuppr_code_partition: partition@e4000 { @@ -217,21 +150,21 @@ cpuflpr_code_partition: partition@f4000 { reg = <0xf4000 DT_SIZE_K(48)>; }; - }; - cpuapp_rw_partitions: cpuapp-rw-partitions { - compatible = "nordic,owned-partitions", "fixed-partitions"; - status = "disabled"; - nordic,access = ; - #address-cells = <1>; - #size-cells = <1>; + cpuapp_slot1_partition: partition@100000 { + reg = <0x100000 DT_SIZE_K(328)>; + }; + + cpurad_slot1_partition: partition@152000 { + reg = <0x152000 DT_SIZE_K(328)>; + }; - dfu_partition: partition@100000 { - reg = < 0x100000 DT_SIZE_K(908) >; + storage_partition: partition@1a4000 { + reg = <0x1a4000 DT_SIZE_K(40)>; }; - storage_partition: partition@1e3000 { - reg = < 0x1e3000 DT_SIZE_K(40) >; + periphconf_partition: partition@1ae000 { + reg = <0x1ae000 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map_iron.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map_iron.dtsi deleted file mode 100644 index 2ecec360694..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map_iron.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* This file is to be merged with the original memory_map.dtsi in the future. - * The following nodes will be replaced: - */ -/delete-node/ &cpuapp_cpusec_ipc_shm; -/delete-node/ &cpuapp_cpusys_ipc_shm; -/delete-node/ &cpurad_cpusec_ipc_shm; -/delete-node/ &cpurad_cpusys_ipc_shm; -/delete-node/ &cpusec_cpuapp_ipc_shm; -/delete-node/ &cpusec_cpurad_ipc_shm; -/delete-node/ &cpusys_cpuapp_ipc_shm; -/delete-node/ &cpusys_cpurad_ipc_shm; -/delete-node/ &cpuapp_rw_partitions; -/delete-node/ &cpuapp_rx_partitions; -/delete-node/ &cpurad_rx_partitions; - -/ { - reserved-memory { - cpuapp_cpusys_ipc_shm: memory@2f88f600 { - reg = <0x2f88f600 0x80>; - }; - - cpusys_cpuapp_ipc_shm: memory@2f88f680 { - reg = <0x2f88f680 0x80>; - }; - - cpurad_cpusys_ipc_shm: memory@2f88f700 { - reg = <0x2f88f700 0x80>; - }; - - cpusys_cpurad_ipc_shm: memory@2f88f780 { - reg = <0x2f88f780 0x80>; - }; - - cpusec_cpurad_ipc_shm: memory@2f88f800 { - reg = <0x2f88f800 0x80>; - }; - - cpurad_ironside_se_event_report: memory@2f88f880 { - reg = <0x2f88f880 0x100>; - }; - - cpurad_ironside_se_boot_report: memory@2f88f980 { - reg = <0x2f88f980 0x200>; - }; - - cpusec_cpuapp_ipc_shm: memory@2f88fb80 { - reg = <0x2f88fb80 0x80>; - }; - - cpuapp_ironside_se_event_report: memory@2f88fc00 { - reg = <0x2f88fc00 0x100>; - }; - - cpuapp_ironside_se_boot_report: memory@2f88fd00 { - reg = <0x2f88fd00 0x200>; - }; - }; -}; - -&mram1x { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - cpuapp_boot_partition: partition@30000 { - reg = <0x30000 DT_SIZE_K(64)>; - }; - - cpuapp_slot0_partition: partition@40000 { - reg = <0x40000 DT_SIZE_K(328)>; - }; - - cpurad_slot0_partition: partition@92000 { - reg = <0x92000 DT_SIZE_K(328)>; - }; - - cpuppr_code_partition: partition@e4000 { - reg = <0xe4000 DT_SIZE_K(64)>; - }; - - cpuflpr_code_partition: partition@f4000 { - reg = <0xf4000 DT_SIZE_K(48)>; - }; - - cpuapp_slot1_partition: partition@100000 { - reg = <0x100000 DT_SIZE_K(328)>; - }; - - cpurad_slot1_partition: partition@152000 { - reg = <0x152000 DT_SIZE_K(328)>; - }; - - storage_partition: partition@1a4000 { - reg = <0x1a4000 DT_SIZE_K(40)>; - }; - }; -}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 49ecb821aa0..85a2539c3ff 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -18,10 +18,11 @@ chosen { zephyr,console = &uart136; - zephyr,code-partition = &cpuapp_slot0_partition; + zephyr,code-partition = &slot0_partition; zephyr,flash = &mram1x; zephyr,sram = &cpuapp_data; zephyr,shell-uart = &uart136; + zephyr,uart-mcumgr = &uart136; zephyr,ieee802154 = &cpuapp_ieee802154; zephyr,bt-hci = &bt_hci_ipc0; nordic,802154-spinel-ipc = &ipc0; @@ -114,18 +115,6 @@ }; }; -&cpuapp_ram0x_region { - status = "okay"; -}; - -&etr_buf_ram0x_region { - status = "okay"; -}; - -&ram21_region { - status = "okay"; -}; - &cpuapp_bellboard { status = "okay"; interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; @@ -151,8 +140,6 @@ &cpusec_cpuapp_ipc { status = "okay"; mbox-names = "tx", "rx"; - tx-region = <&cpuapp_cpusec_ipc_shm>; - rx-region = <&cpusec_cpuapp_ipc_shm>; }; &cpusec_bellboard { @@ -196,12 +183,26 @@ ipc0: &cpuapp_cpurad_ipc { status = "okay"; }; -&cpuapp_rx_partitions { - status = "okay"; +ironside_se_boot_report: &cpuapp_ironside_se_boot_report {}; + +boot_partition: &cpuapp_boot_partition { + label = "mcuboot"; }; -&cpuapp_rw_partitions { - status = "okay"; +slot0_partition: &cpuapp_slot0_partition { + label = "image-0"; +}; + +slot1_partition: &cpuapp_slot1_partition { + label = "image-1"; +}; + +slot2_partition: &cpurad_slot0_partition { + label = "image-2"; +}; + +slot3_partition: &cpurad_slot1_partition { + label = "image-3"; }; &cpuppr_vpr { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml index 1884ce0a4d0..4e82987d28e 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml @@ -9,8 +9,8 @@ toolchain: - gnuarmemb - zephyr sysbuild: true -ram: 256 -flash: 296 +ram: 760 +flash: 392 supported: - adc - can diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig index e1ba596d135..70bb6a24c9c 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_defconfig @@ -8,8 +8,6 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -CONFIG_USE_DT_CODE_PARTITION=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts deleted file mode 100644 index e822cf2c911..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "nrf54h20dk_nrf54h20_cpuapp.dts" -#include "nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi" -#include "nrf54h20dk_nrf54h20-memory_map_iron.dtsi" - -/delete-node/ &cpusec_cpurad_ipc; - -/ { - chosen { - zephyr,code-partition = &slot0_partition; - zephyr,uart-mcumgr = &uart136; - }; -}; - -&cpusec_cpuapp_ipc { - mbox-names = "tx", "rx"; - status = "okay"; -}; - -ironside_se_boot_report: &cpuapp_ironside_se_boot_report {}; - -boot_partition: &cpuapp_boot_partition { - label = "mcuboot"; -}; - -slot0_partition: &cpuapp_slot0_partition { - label = "image-0"; -}; - -slot1_partition: &cpuapp_slot1_partition { - label = "image-1"; -}; - -slot2_partition: &cpurad_slot0_partition { - label = "image-2"; -}; - -slot3_partition: &cpurad_slot1_partition { - label = "image-3"; -}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_0_9_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_0_9_0.yaml deleted file mode 100644 index fa64abbd3a4..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_0_9_0.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20dk/nrf54h20/cpuapp/iron -name: nRF54H20-DK-nRF54H20-Application (IRONside compatible) (revision 0.9.0) -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -sysbuild: true -ram: 256 -flash: 392 -supported: - - adc - - can - - counter - - gpio - - i2c - - pwm - - retained_mem - - spi - - watchdog - - usbd diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_defconfig deleted file mode 100644 index 01f3bec3932..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Enable GPIO -CONFIG_GPIO=y - -# UICR generation is not supported, and when reintroduced will not use nrf-regtool. -CONFIG_NRF_REGTOOL_GENERATE_UICR=n diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index f6eccadc852..7e1a1c8e9e0 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -24,6 +24,7 @@ zephyr,flash = &mram1x; zephyr,sram = &cpurad_ram0; zephyr,shell-uart = &uart135; + zephyr,uart-mcumgr = &uart135; zephyr,ieee802154 = &cpurad_ieee802154; zephyr,bt-hci-ipc = &ipc0; nordic,802154-spinel-ipc = &ipc0; @@ -40,14 +41,6 @@ }; }; -&cpuapp_cpurad_ram0x_region { - status = "okay"; -}; - -&cpurad_ram0x_region { - status = "okay"; -}; - &cpurad_bellboard { status = "okay"; interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; @@ -67,8 +60,6 @@ &cpusec_cpurad_ipc { status = "okay"; mbox-names = "tx", "rx"; - tx-region = <&cpurad_cpusec_ipc_shm>; - rx-region = <&cpusec_cpurad_ipc_shm>; }; &cpusec_bellboard { @@ -95,8 +86,12 @@ ipc0: &cpuapp_cpurad_ipc { status = "okay"; }; -&cpurad_rx_partitions { - status = "okay"; +slot0_partition: &cpurad_slot0_partition { + label = "image-0"; +}; + +slot1_partition: &cpurad_slot1_partition { + label = "image-1"; }; &grtc { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml index de557fcc2cd..8567494d1e3 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml @@ -10,7 +10,7 @@ toolchain: - zephyr sysbuild: true ram: 192 -flash: 256 +flash: 328 supported: - counter - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron.dts deleted file mode 100644 index 16b599f554e..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "nrf54h20dk_nrf54h20_cpurad.dts" -#include "nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi" -#include "nrf54h20dk_nrf54h20-memory_map_iron.dtsi" - -/ { - chosen { - zephyr,code-partition = &cpurad_slot0_partition; - zephyr,uart-mcumgr = &uart135; - }; -}; - -&cpusec_cpurad_ipc { - mbox-names = "tx", "rx"; - status = "okay"; -}; - -slot0_partition: &cpurad_slot0_partition { - label = "image-0"; -}; - -slot1_partition: &cpurad_slot1_partition { - label = "image-1"; -}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron_0_9_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron_0_9_0.yaml deleted file mode 100644 index eae5f08a090..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron_0_9_0.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54h20dk/nrf54h20/cpurad/iron -name: nRF54H20-DK-nRF54H20-Radio (IRONside SE compatible) (revision 0.9.0) -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -sysbuild: true -ram: 192 -flash: 328 -supported: - - counter - - gpio - - pwm - - retained_mem - - spi diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron_defconfig b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron_defconfig deleted file mode 100644 index 0ee0a96f99d..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_iron_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# UICR generation is not supported, and when reintroduced will not use nrf-regtool. -CONFIG_NRF_REGTOOL_GENERATE_UICR=n diff --git a/doc/build/kconfig/preprocessor-functions.rst b/doc/build/kconfig/preprocessor-functions.rst index 9de5110bfdb..e3ed5f40636 100644 --- a/doc/build/kconfig/preprocessor-functions.rst +++ b/doc/build/kconfig/preprocessor-functions.rst @@ -81,18 +81,29 @@ Integer functions The functions listed below can be used to do arithmetic operations on integer variables, such as addition, subtraction and more. +Functions with and without the ``_hex`` suffix in their names +return hexadecimal and decimal values respectively. .. code-block:: none $(add,[,value]...) + $(add_hex,[,value]...) $(dec,[,value]...) + $(dec_hex,[,value]...) $(div,[,value]...) + $(div_hex,[,value]...) $(inc,[,value]...) + $(inc_hex,[,value]...) $(max,[,value]...) + $(max_hex,[,value]...) $(min,[,value]...) + $(min_hex,[,value]...) $(mod,[,value]...) + $(mod_hex,[,value]...) $(mul,[,value]...) + $(mul_hex,[,value]...) $(sub,[,value]...) + $(sub_hex,[,value]...) String functions diff --git a/drivers/firmware/nrf_ironside/Kconfig b/drivers/firmware/nrf_ironside/Kconfig index 4c313618638..a9e68bba0b2 100644 --- a/drivers/firmware/nrf_ironside/Kconfig +++ b/drivers/firmware/nrf_ironside/Kconfig @@ -3,9 +3,9 @@ config NRF_IRONSIDE bool - depends on SOC_NRF54H20_IRON || SOC_NRF9280_IRON + depends on SOC_NRF54H20 || SOC_NRF9280_IRON help - This is selected by drivers interacting with Nordic IRONside firmware. + This is selected by drivers interacting with Nordic IronSide firmware. config NRF_IRONSIDE_CALL bool @@ -14,44 +14,44 @@ config NRF_IRONSIDE_CALL select EVENTS select MBOX help - This is selected by features that require support for IRONside calls. + This is selected by features that require support for IronSide calls. if NRF_IRONSIDE_CALL config NRF_IRONSIDE_CALL_INIT_PRIORITY - int "IRONside calls' initialization priority" + int "IronSide calls' initialization priority" default 41 help - Initialization priority of IRONside calls. It must be below MBOX_INIT_PRIORITY, + Initialization priority of IronSide calls. It must be below MBOX_INIT_PRIORITY, but higher than the priority of any feature that selects NRF_IRONSIDE_CALL. endif # NRF_IRONSIDE_CALL -menu "Nordic IRONside services" - depends on SOC_NRF54H20_IRON || SOC_NRF9280_IRON +menu "Nordic IronSide services" + depends on SOC_NRF54H20 || SOC_NRF9280_IRON config NRF_IRONSIDE_CPUCONF_SERVICE - bool "IRONside CPUCONF service" + bool "IronSide CPUCONF service" depends on SOC_NRF54H20_CPUAPP || SOC_NRF9280_CPUAPP select NRF_IRONSIDE_CALL help Service used to boot local domain cores. config NRF_IRONSIDE_UPDATE_SERVICE - bool "IRONside update service" + bool "IronSide update service" select NRF_IRONSIDE_CALL help - Service used to update the IRONside SE firmware. + Service used to update the IronSide SE firmware. config NRF_IRONSIDE_BOOT_REPORT - bool "IRONside boot report" + bool "IronSide boot report" depends on $(dt_nodelabel_exists,ironside_se_boot_report) select NRF_IRONSIDE help - Support for parsing the Boot Report populated by Nordic IRONside firmware. + Support for parsing the Boot Report populated by Nordic IronSide firmware. config NRF_IRONSIDE_DVFS_SERVICE - bool "IRONside DVFS service" + bool "IronSide DVFS service" depends on SOC_NRF54H20_CPUAPP select NRF_IRONSIDE_CALL help diff --git a/drivers/firmware/nrf_ironside/dvfs.c b/drivers/firmware/nrf_ironside/dvfs.c index 89208f71fb7..ba95a6a1481 100644 --- a/drivers/firmware/nrf_ironside/dvfs.c +++ b/drivers/firmware/nrf_ironside/dvfs.c @@ -122,8 +122,8 @@ static inline bool ironside_dvfs_is_abb_locked(NRF_ABB_Type *abb) } /** - * @brief Request DVFS oppoint change from IRONside secure domain. - * This function will send a request over IPC to the IRONside secure domain + * @brief Request DVFS oppoint change from IronSide secure domain. + * This function will send a request over IPC to the IronSide secure domain * This function is synchronous and will return when the request is completed. * * @param oppoint @ref enum ironside_dvfs_oppoint diff --git a/dts/bindings/firmware/nordic,ironside-call.yaml b/dts/bindings/firmware/nordic,ironside-call.yaml index 14f39cb0b74..a2605ff2294 100644 --- a/dts/bindings/firmware/nordic,ironside-call.yaml +++ b/dts/bindings/firmware/nordic,ironside-call.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2025 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -description: IPC configuration for Nordic IRONside calls +description: IPC configuration for Nordic IronSide calls compatible: "nordic,ironside-call" diff --git a/dts/vendor/nordic/nrf54h20.dtsi b/dts/vendor/nordic/nrf54h20.dtsi index 1ff7fae23cd..df9e46a7220 100644 --- a/dts/vendor/nordic/nrf54h20.dtsi +++ b/dts/vendor/nordic/nrf54h20.dtsi @@ -13,7 +13,6 @@ #include #include #include -#include #include /delete-node/ &sw_pwm; @@ -151,10 +150,6 @@ reserved-memory { #address-cells = <1>; #size-cells = <1>; - - suit_storage_partition: memory@e1ed000 { - reg = <0xe1ed000 DT_SIZE_K(20)>; - }; }; clocks { @@ -230,13 +225,12 @@ write-block-size = <16>; }; - cpuapp_uicr: uicr@fff8000 { - compatible = "nordic,nrf-uicr-v2"; + uicr: uicr@fff8000 { + compatible = "nordic,nrf-uicr"; reg = <0xfff8000 DT_SIZE_K(2)>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xfff8000 DT_SIZE_K(2)>; - domain = <2>; bicr: bicr@7b0 { compatible = "nordic,nrf-bicr"; @@ -244,12 +238,6 @@ }; }; - cpurad_uicr: uicr@fffa000 { - compatible = "nordic,nrf-uicr-v2"; - reg = <0xfffa000 DT_SIZE_K(2)>; - domain = <3>; - }; - ficr: ficr@fffe000 { compatible = "nordic,nrf-ficr"; reg = <0xfffe000 DT_SIZE_K(2)>; diff --git a/include/zephyr/drivers/firmware/nrf_ironside/boot_report.h b/include/zephyr/drivers/firmware/nrf_ironside/boot_report.h index 8a209b8788d..509c05babcb 100644 --- a/include/zephyr/drivers/firmware/nrf_ironside/boot_report.h +++ b/include/zephyr/drivers/firmware/nrf_ironside/boot_report.h @@ -9,14 +9,14 @@ #include #include -/** Constant used to check if an Nordic IRONside SE boot report has been written. */ +/** Constant used to check if an Nordic IronSide SE boot report has been written. */ #define IRONSIDE_BOOT_REPORT_MAGIC (0x4d69546fUL) /** Length of the local domain context buffer in bytes. */ #define IRONSIDE_BOOT_REPORT_LOCAL_DOMAIN_CONTEXT_SIZE (16UL) /** Length of the random data buffer in bytes. */ #define IRONSIDE_BOOT_REPORT_RANDOM_DATA_SIZE (32UL) -/** @brief IRONside version structure. */ +/** @brief IronSide version structure. */ struct ironside_version { /** Wrapping sequence number ranging from 1-126, incremented for each release. */ uint8_t seqnum; @@ -43,13 +43,13 @@ struct ironside_boot_report_uicr_error { } description; }; -/** @brief IRONside boot report. */ +/** @brief IronSide boot report. */ struct ironside_boot_report { /** Magic value used to identify valid boot report */ uint32_t magic; - /** Firmware version of IRONside SE. */ + /** Firmware version of IronSide SE. */ struct ironside_version ironside_se_version; - /** Firmware version of IRONside SE recovery firmware. */ + /** Firmware version of IronSide SE recovery firmware. */ struct ironside_version ironside_se_recovery_version; /** Copy of SICR.UROT.UPDATE.STATUS.*/ uint32_t ironside_update_status; @@ -64,9 +64,9 @@ struct ironside_boot_report { }; /** - * @brief Get a pointer to the IRONside boot report. + * @brief Get a pointer to the IronSide boot report. * - * @param[out] report Will be set to point to the IRONside boot report. + * @param[out] report Will be set to point to the IronSide boot report. * * @retval 0 if successful. * @retval -EFAULT if the magic field in the report is incorrect. diff --git a/include/zephyr/drivers/firmware/nrf_ironside/call.h b/include/zephyr/drivers/firmware/nrf_ironside/call.h index 178b9371cdb..d67e9762202 100644 --- a/include/zephyr/drivers/firmware/nrf_ironside/call.h +++ b/include/zephyr/drivers/firmware/nrf_ironside/call.h @@ -8,7 +8,7 @@ #include -/** @brief Maximum number of arguments to an IRONside call. +/** @brief Maximum number of arguments to an IronSide call. * * This is chosen so that the containing message buffer size is minimal but * cache line aligned. @@ -50,7 +50,7 @@ struct ironside_call_buf { */ /** - * @brief Allocate memory for an IRONside call. + * @brief Allocate memory for an IronSide call. * * This function will block when no buffers are available, until one is * released by another thread on the client side. @@ -60,7 +60,7 @@ struct ironside_call_buf { struct ironside_call_buf *ironside_call_alloc(void); /** - * @brief Dispatch an IRONside call. + * @brief Dispatch an IronSide call. * * This function will block until a response is received from the server. * @@ -71,7 +71,7 @@ struct ironside_call_buf *ironside_call_alloc(void); void ironside_call_dispatch(struct ironside_call_buf *buf); /** - * @brief Release an IRONside call buffer. + * @brief Release an IronSide call buffer. * * This function must be called after processing the response. * diff --git a/include/zephyr/drivers/firmware/nrf_ironside/cpuconf.h b/include/zephyr/drivers/firmware/nrf_ironside/cpuconf.h index d769a319def..bed8932868f 100644 --- a/include/zephyr/drivers/firmware/nrf_ironside/cpuconf.h +++ b/include/zephyr/drivers/firmware/nrf_ironside/cpuconf.h @@ -63,7 +63,7 @@ BUILD_ASSERT(IRONSIDE_CPUCONF_NUM_ARGS <= NRF_IRONSIDE_CALL_NUM_ARGS); * If the given msg_size is less than that, the remaining bytes are set to zero. * * @retval 0 on success or if the CPU has already booted. - * @retval Positive non-0 error status if reported by IRONside call. + * @retval Positive non-0 error status if reported by IronSide call. * @retval -IRONSIDE_CPUCONF_ERROR_WRONG_CPU if cpu is unrecognized * @retval -IRONSIDE_CPUCONF_ERROR_MESSAGE_TOO_LARGE if msg_size is greater than * IRONSIDE_CPUCONF_SERVICE_MSG_MAX_SIZE. diff --git a/include/zephyr/drivers/firmware/nrf_ironside/dvfs.h b/include/zephyr/drivers/firmware/nrf_ironside/dvfs.h index 7d6587bb3c0..5a80f062bd7 100644 --- a/include/zephyr/drivers/firmware/nrf_ironside/dvfs.h +++ b/include/zephyr/drivers/firmware/nrf_ironside/dvfs.h @@ -18,15 +18,15 @@ enum ironside_dvfs_oppoint { }; /** - * @brief Number of DVFS oppoints supported by IRONside. + * @brief Number of DVFS oppoints supported by IronSide. * - * This is the number of different DVFS oppoints that can be set on IRONside. + * This is the number of different DVFS oppoints that can be set on IronSide. * The oppoints are defined in the `ironside_dvfs_oppoint` enum. */ #define IRONSIDE_DVFS_OPPOINT_COUNT (3) /** - * @name IRONside DVFS service error codes. + * @name IronSide DVFS service error codes. * @{ */ @@ -49,10 +49,10 @@ enum ironside_dvfs_oppoint { * @} */ -/* IRONside call identifiers with implicit versions. +/* IronSide call identifiers with implicit versions. * * With the initial "version 0", the service ABI is allowed to break until the - * first production release of IRONside SE. + * first production release of IronSide SE. */ #define IRONSIDE_CALL_ID_DVFS_SERVICE_V0 3 diff --git a/include/zephyr/drivers/firmware/nrf_ironside/update.h b/include/zephyr/drivers/firmware/nrf_ironside/update.h index 62191b3285b..5da02c97e6d 100644 --- a/include/zephyr/drivers/firmware/nrf_ironside/update.h +++ b/include/zephyr/drivers/firmware/nrf_ironside/update.h @@ -30,10 +30,10 @@ /** Length of the update signature in bytes. */ #define IRONSIDE_UPDATE_SIGNATURE_LENGTH (64) -/* IRONside call identifiers with implicit versions. +/* IronSide call identifiers with implicit versions. * * With the initial "version 0", the service ABI is allowed to break until the - * first production release of IRONside SE. + * first production release of IronSide SE. */ #define IRONSIDE_CALL_ID_UPDATE_SERVICE_V0 1 @@ -43,7 +43,7 @@ #define IRONSIDE_UPDATE_SERVICE_RETCODE_IDX (0) /** - * @brief IRONside update blob. + * @brief IronSide update blob. */ struct ironside_update_blob { uint8_t manifest[IRONSIDE_UPDATE_MANIFEST_LENGTH]; @@ -53,9 +53,9 @@ struct ironside_update_blob { }; /** - * @brief Request a firmware upgrade of the IRONside SE. + * @brief Request a firmware upgrade of the IronSide SE. * - * This invokes the IRONside SE update service. The device must be restarted for the update + * This invokes the IronSide SE update service. The device must be restarted for the update * to be installed. Check the update status in the application boot report to see if the update * was successfully installed. * @@ -63,7 +63,7 @@ struct ironside_update_blob { * * @retval -IRONSIDE_UPDATE_ERROR_NOT_PERMITTED if missing access to the update candidate. * @retval -IRONSIDE_UPDATE_ERROR_SICR_WRITE_FAILED if writing update parameters to SICR failed. - * @returns Positive non-0 error status if reported by IRONside call. + * @returns Positive non-0 error status if reported by IronSide call. * @returns 0 on a successful request (although the update itself may still fail). * */ diff --git a/modules/hal_nordic/Kconfig.nrf_regtool b/modules/hal_nordic/Kconfig.nrf_regtool index 396ec2050a0..12f7a53f471 100644 --- a/modules/hal_nordic/Kconfig.nrf_regtool +++ b/modules/hal_nordic/Kconfig.nrf_regtool @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 menu "nrf-regtool options" - depends on SOC_SERIES_NRF54HX || SOC_SERIES_NRF92X + depends on SOC_SERIES_NRF92X config NRF_REGTOOL_GENERATE_UICR bool "Generate UICR" diff --git a/samples/application_development/code_relocation_nocopy/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/application_development/code_relocation_nocopy/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index ab53f12725d..98d67e2ad08 100644 --- a/samples/application_development/code_relocation_nocopy/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/samples/application_development/code_relocation_nocopy/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -1,10 +1,5 @@ -&cpuapp_ram0x_region { - nordic,access = ; -}; - &xip_region { status = "okay"; - nordic,access = ; }; &mx25uw63 { diff --git a/samples/boards/nordic/coresight_stm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/boards/nordic/coresight_stm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index bf5ba18d204..970377c4d89 100644 --- a/samples/boards/nordic/coresight_stm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/samples/boards/nordic/coresight_stm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -7,10 +7,6 @@ status = "okay"; }; -&cpuppr_ram3x_region { - status = "okay"; -}; - &cpuflpr_vpr { status = "okay"; }; diff --git a/samples/boards/nordic/nrf_ironside/update/Kconfig b/samples/boards/nordic/nrf_ironside/update/Kconfig index 702b943ff60..12d3350ef79 100644 --- a/samples/boards/nordic/nrf_ironside/update/Kconfig +++ b/samples/boards/nordic/nrf_ironside/update/Kconfig @@ -6,6 +6,6 @@ config UPDATE_BLOB_ADDRESS default 0xe100000 help Address of the update blob. The default value matches the placement of the - update blobs delivered with the IRONside SE firmware. + update blobs delivered with the IronSide SE firmware. source "Kconfig.zephyr" diff --git a/samples/boards/nordic/nrf_ironside/update/README.rst b/samples/boards/nordic/nrf_ironside/update/README.rst index 2f44feedf06..484d97d0add 100644 --- a/samples/boards/nordic/nrf_ironside/update/README.rst +++ b/samples/boards/nordic/nrf_ironside/update/README.rst @@ -1,37 +1,37 @@ .. zephyr:code-sample:: nrf_ironside_update - :name: Nordic IRONside SE firmware update + :name: Nordic IronSide SE firmware update - Update the Nordic IRONside SE firmware. + Update the Nordic IronSide SE firmware. Overview ******** -The Nordic IRONside SE Update sample updates the IRONside SE firmware on a SoC that already has IRONside SE installed. -It can update both the main image and the recovery image of IRONside SE using the IRONside SE firmware release ZIP file. +The Nordic IronSide SE Update sample updates the IronSide SE firmware on a SoC that already has IronSide SE installed. +It can update both the main image and the recovery image of IronSide SE using the IronSide SE firmware release ZIP file. Update procedure **************** The update procedure works as follows: -1. The application invokes the IRONside SE update service and passes the parameters that correspond to the location of the HEX file of the IRONside SE firmware update. +1. The application invokes the IronSide SE update service and passes the parameters that correspond to the location of the HEX file of the IronSide SE firmware update. #. The application prints the return value of the service call and outputs information from the update HEX file. -#. After the service call completes, the IRONside SE firmware updates the internal state of the device. +#. After the service call completes, the IronSide SE firmware updates the internal state of the device. #. The firmware installs the update during the next device boot. This operation can take several seconds. Once the operation has completed, you can read the boot report to verify that the update has taken place. -Building and running the application for nrf54h20dk/nrf54h20/cpuapp/iron -************************************************************************ +Building and running the application for nrf54h20dk/nrf54h20/cpuapp +******************************************************************* .. note:: - You can use this application only when there is already a version of IRONside SE installed on the device. + You can use this application only when there is already a version of IronSide SE installed on the device. -1. Unzip the IRONside SE release ZIP to get the update hex file: +1. Unzip the IronSide SE release ZIP to get the update hex file: .. code-block:: console @@ -39,13 +39,13 @@ Building and running the application for nrf54h20dk/nrf54h20/cpuapp/iron #. Program the appropriate update hex file from the release ZIP using one (not both) of the following commands: - a) To update IRONside SE firmware: + a) To update IronSide SE firmware: .. code-block:: console nrfutil device program --traits jlink --firmware update/ironside_se_update.hex - b) To update IRONside SE recovery firmware: + b) To update IronSide SE recovery firmware: .. code-block:: console @@ -55,7 +55,7 @@ Building and running the application for nrf54h20dk/nrf54h20/cpuapp/iron .. zephyr-app-commands:: :zephyr-app: samples/boards/nordic/nrf_ironside/update - :board: nrf54h20dk/nrf54h20/cpuapp/iron + :board: nrf54h20dk/nrf54h20/cpuapp :goals: flash #. Trigger a reset: diff --git a/samples/boards/nordic/nrf_ironside/update/sample.yaml b/samples/boards/nordic/nrf_ironside/update/sample.yaml index af3c24624b8..3a5d9477da2 100644 --- a/samples/boards/nordic/nrf_ironside/update/sample.yaml +++ b/samples/boards/nordic/nrf_ironside/update/sample.yaml @@ -1,12 +1,12 @@ sample: - name: Nordic IRONside SE update service - description: Demonstrates how to update the Nordic IRONside SE firmware + name: Nordic IronSide SE update service + description: Demonstrates how to update the Nordic IronSide SE firmware common: build_only: true tags: nrf_ironside integration_platforms: - - nrf54h20dk/nrf54h20/cpuapp/iron + - nrf54h20dk/nrf54h20/cpuapp tests: sample.boards.nordic.nrf_ironside.update: - platform_allow: nrf54h20dk/nrf54h20/cpuapp/iron + platform_allow: nrf54h20dk/nrf54h20/cpuapp diff --git a/samples/boards/nordic/nrf_ironside/update/src/main.c b/samples/boards/nordic/nrf_ironside/update/src/main.c index a06603ca9b2..17098d93d3b 100644 --- a/samples/boards/nordic/nrf_ironside/update/src/main.c +++ b/samples/boards/nordic/nrf_ironside/update/src/main.c @@ -28,7 +28,7 @@ int main(void) LOG_HEXDUMP_INF((void *)report->random_data, sizeof(report->random_data), "random data"); err = ironside_update(update); - LOG_INF("IRONside update retval: 0x%x", err); + LOG_INF("IronSide update retval: 0x%x", err); if (err == 0) { LOG_HEXDUMP_INF(update->manifest, sizeof(update->manifest), "Update manifest:"); diff --git a/samples/drivers/counter/alarm/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay b/samples/drivers/counter/alarm/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay deleted file mode 100644 index f65b4dd3b0b..00000000000 --- a/samples/drivers/counter/alarm/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include "nrf54h20dk_nrf54h20_common.dtsi" diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index 3b154d9afca..e2ea0f6687e 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -24,7 +24,6 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR CONFIG_BOARD_ESP32_DEVKITC_ESP32_PROCPU OR CONFIG_BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR - CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR CONFIG_BOARD_NRF54L09PDK_NRF54L09_CPUAPP OR CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP OR CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUAPP OR diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index 1c0d77b7ded..96f1ba8c7f4 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -18,7 +18,6 @@ config REMOTE_BOARD default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947" default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk" - default "nrf54h20dk/nrf54h20/cpuapp" if "$(BOARD)${BOARD_QUALIFIERS}" = "nrf54h20dk/nrf54h20/cpurad" default "nrf54l09pdk/nrf54l09/cpuflpr" if $(BOARD) = "nrf54l09pdk" default "nrf54l15dk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15dk" default "nrf54l20pdk/nrf54l20/cpuflpr" if $(BOARD) = "nrf54l20pdk" diff --git a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp.overlay similarity index 100% rename from samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay rename to samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp.overlay diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index baa0e22ff35..2866503e448 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -23,7 +23,7 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET OR CONFIG_BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUFLPR OR - CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR + CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR CONFIG_BOARD_NRF54L09PDK_NRF54L09_CPUFLPR OR CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUFLPR OR CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUFLPR OR diff --git a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay similarity index 100% rename from samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpurad.overlay rename to samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index f1a1e56e771..e1f90d1d590 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -59,19 +59,22 @@ tests: - "Ping \\(on channel 16\\)" - "Pong \\(on channel 14\\)" - sample.drivers.mbox.nrf54h20_rad_app: + sample.drivers.mbox.nrf54h20_app_rad: platform_allow: - - nrf54h20dk/nrf54h20/cpurad + - nrf54h20dk/nrf54h20/cpuapp integration_platforms: - - nrf54h20dk/nrf54h20/cpurad + - nrf54h20dk/nrf54h20/cpuapp + extra_args: + - mbox_CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y + - SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad.conf sysbuild: true harness: console harness_config: type: multi_line ordered: false regex: - - "Ping \\(on channel 18\\)" - - "Pong \\(on channel 12\\)" + - "Ping \\(on channel 12\\)" + - "Pong \\(on channel 18\\)" sample.drivers.mbox.nrf54l: platform_allow: diff --git a/samples/drivers/mbox/sysbuild/nrf54h20dk_nrf54h20_cpurad.conf b/samples/drivers/mbox/sysbuild/nrf54h20dk_nrf54h20_cpurad.conf new file mode 100644 index 00000000000..dd863e78d99 --- /dev/null +++ b/samples/drivers/mbox/sysbuild/nrf54h20dk_nrf54h20_cpurad.conf @@ -0,0 +1 @@ +SB_CONFIG_REMOTE_BOARD="nrf54h20dk/nrf54h20/cpurad" diff --git a/samples/drivers/watchdog/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay b/samples/drivers/watchdog/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay deleted file mode 100644 index 102abfc8ef2..00000000000 --- a/samples/drivers/watchdog/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright 2025 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -&wdt010 { - status = "okay"; -}; diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index dcdd8cfc76f..aef16825a75 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -91,7 +91,7 @@ tests: - mimxrt685_evk/mimxrt685s/cm33 - rd_rw612_bga - nrf52840dk/nrf52840 - - nrf54h20dk/nrf54h20/cpuapp/iron + - nrf54h20dk/nrf54h20/cpuapp - pinnacle_100_dvk - mg100 integration_platforms: diff --git a/samples/sysbuild/hello_world/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf b/samples/sysbuild/hello_world/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf deleted file mode 100644 index ca2bc07e4f2..00000000000 --- a/samples/sysbuild/hello_world/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y diff --git a/samples/sysbuild/hello_world/sample.yaml b/samples/sysbuild/hello_world/sample.yaml index c8ca9cbe4c0..e638594c634 100644 --- a/samples/sysbuild/hello_world/sample.yaml +++ b/samples/sysbuild/hello_world/sample.yaml @@ -25,13 +25,9 @@ tests: - nrf54h20dk/nrf54h20/cpuapp integration_platforms: - nrf54h20dk/nrf54h20/cpuapp - extra_args: SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad.conf - - sample.sysbuild.hello_world.nrf54h20dk_cpuapp_cpurad.iron: - platform_allow: - - nrf54h20dk/nrf54h20/cpuapp/iron - extra_args: SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad_iron.conf - + extra_args: + - SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad.conf + - hello_world_CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y sample.sysbuild.hello_world.nrf54h20dk_cpuapp_cpuppr: platform_allow: - nrf54h20dk/nrf54h20/cpuapp diff --git a/samples/sysbuild/hello_world/sysbuild/nrf54h20dk_nrf54h20_cpurad_iron.conf b/samples/sysbuild/hello_world/sysbuild/nrf54h20dk_nrf54h20_cpurad_iron.conf deleted file mode 100644 index 8d4a230adbe..00000000000 --- a/samples/sysbuild/hello_world/sysbuild/nrf54h20dk_nrf54h20_cpurad_iron.conf +++ /dev/null @@ -1 +0,0 @@ -SB_CONFIG_REMOTE_BOARD="nrf54h20dk/nrf54h20/cpurad/iron" diff --git a/scripts/kconfig/kconfigfunctions.py b/scripts/kconfig/kconfigfunctions.py index ce4ce2aa6c2..4b42ce30cef 100644 --- a/scripts/kconfig/kconfigfunctions.py +++ b/scripts/kconfig/kconfigfunctions.py @@ -983,8 +983,8 @@ def arith(kconf, name, *args): the operation on the first two arguments and operates the same operation as the result and the following argument. For interoperability with inc and dec, - if there is only one argument, it will be split with a comma and processed - as a sequence of numbers. + each argument can be a single number or a comma-separated list of numbers, + but all numbers are processed as if they were individual arguments. Examples in Kconfig: @@ -1008,22 +1008,36 @@ def arith(kconf, name, *args): $(div, $(dec, 1, 1)) # Error (0 div 0) """ - intarray = map(int, args if len(args) > 1 else args[0].split(",")) + intarray = (int(val, base=0) for arg in args for val in arg.split(",")) if name == "add": return str(int(functools.reduce(operator.add, intarray))) + elif name == "add_hex": + return hex(int(functools.reduce(operator.add, intarray))) elif name == "sub": return str(int(functools.reduce(operator.sub, intarray))) + elif name == "sub_hex": + return hex(int(functools.reduce(operator.sub, intarray))) elif name == "mul": return str(int(functools.reduce(operator.mul, intarray))) + elif name == "mul_hex": + return hex(int(functools.reduce(operator.mul, intarray))) elif name == "div": return str(int(functools.reduce(operator.truediv, intarray))) + elif name == "div_hex": + return hex(int(functools.reduce(operator.truediv, intarray))) elif name == "mod": return str(int(functools.reduce(operator.mod, intarray))) + elif name == "mod_hex": + return hex(int(functools.reduce(operator.mod, intarray))) elif name == "max": return str(int(functools.reduce(max, intarray))) + elif name == "max_hex": + return hex(int(functools.reduce(max, intarray))) elif name == "min": return str(int(functools.reduce(min, intarray))) + elif name == "min_hex": + return hex(int(functools.reduce(min, intarray))) else: assert False @@ -1034,12 +1048,16 @@ def inc_dec(kconf, name, *args): Returns a string that concatenates numbers with a comma as a separator. """ - intarray = map(int, args if len(args) > 1 else args[0].split(",")) + intarray = (int(val, base=0) for arg in args for val in arg.split(",")) if name == "inc": return ",".join(map(lambda a: str(a + 1), intarray)) + if name == "inc_hex": + return ",".join(map(lambda a: hex(a + 1), intarray)) elif name == "dec": return ",".join(map(lambda a: str(a - 1), intarray)) + elif name == "dec_hex": + return ",".join(map(lambda a: hex(a - 1), intarray)) else: assert False @@ -1106,12 +1124,21 @@ def inc_dec(kconf, name, *args): "shields_list_contains": (shields_list_contains, 1, 1), "substring": (substring, 2, 3), "add": (arith, 1, 255), + "add_hex": (arith, 1, 255), "sub": (arith, 1, 255), + "sub_hex": (arith, 1, 255), "mul": (arith, 1, 255), + "mul_hex": (arith, 1, 255), "div": (arith, 1, 255), + "div_hex": (arith, 1, 255), "mod": (arith, 1, 255), + "mod_hex": (arith, 1, 255), "max": (arith, 1, 255), + "max_hex": (arith, 1, 255), "min": (arith, 1, 255), + "min_hex": (arith, 1, 255), "inc": (inc_dec, 1, 255), + "inc_hex": (inc_dec, 1, 255), "dec": (inc_dec, 1, 255), + "dec_hex": (inc_dec, 1, 255), } diff --git a/scripts/west_commands/runners/nrf_common.py b/scripts/west_commands/runners/nrf_common.py index a6af477c61a..a7401084ef3 100644 --- a/scripts/west_commands/runners/nrf_common.py +++ b/scripts/west_commands/runners/nrf_common.py @@ -320,8 +320,7 @@ def recover_target(self): # recover operation unlocks the core and then flashes a small image that # keeps the debug access port open, recovering the network core last # would result in that small image being deleted from the app core. - # In the case of the 54H, the order is indifferent. - if self.family in ('nrf53', 'nrf54h', 'nrf92'): + if self.family in ('nrf53', 'nrf92'): self.exec_op('recover', core='Network') self.exec_op('recover') @@ -369,9 +368,9 @@ def program_hex(self): if self.family in ('nrf54h', 'nrf92'): erase_arg = 'ERASE_NONE' - generated_uicr = self.build_conf.getboolean('CONFIG_NRF_REGTOOL_GENERATE_UICR') + regtool_generated_uicr = self.build_conf.getboolean('CONFIG_NRF_REGTOOL_GENERATE_UICR') - if generated_uicr and not self.hex_get_uicrs().get(core): + if regtool_generated_uicr and not self.hex_get_uicrs().get(core): raise RuntimeError( f"Expected a UICR to be contained in: {self.hex_}\n" "Please ensure that the correct version of nrf-regtool is " @@ -379,7 +378,7 @@ def program_hex(self): ) if self.erase: - if self.build_conf.get('CONFIG_SOC_NRF54H20_IRON'): + if self.family == 'nrf54h': self.exec_op('erase', kind='all') else: self.exec_op('erase', core='Application', kind='all') @@ -434,7 +433,27 @@ def program_hex(self): core='Application', ) - if not self.erase and generated_uicr: + if self.build_conf.getboolean("CONFIG_NRF_HALTIUM_GENERATE_UICR"): + zephyr_build_dir = Path(self.cfg.build_dir) / 'zephyr' + + self.op_program( + str(zephyr_build_dir / 'uicr.hex'), + 'ERASE_NONE', + None, + defer=True, + core='Application', + ) + + if self.build_conf.getboolean("CONFIG_NRF_HALTIUM_UICR_PERIPHCONF"): + self.op_program( + str(zephyr_build_dir / 'periphconf.hex'), + 'ERASE_NONE', + None, + defer=True, + core='Application', + ) + + if not self.erase and regtool_generated_uicr: self.exec_op('erase', core=core, kind='uicr') else: if self.erase: @@ -464,8 +483,8 @@ def program_hex(self): self.logger.debug(f'Erase modes: chip:{erase_arg} ext_mem:' f'{ext_mem_erase_opt}') - # Temp hack while waiting for NRF54H20_IRON support for Network in nrfutil - if self.build_conf.get('CONFIG_SOC_NRF54H20_IRON') and core == "Network": + # Temp hack while waiting for nrfutil Network support for NRF54H20 with IronSide + if self.family == 'nrf54h' and core == 'Network': core = "Application" self.op_program(self.hex_, erase_arg, ext_mem_erase_opt, defer=True, core=core) diff --git a/snippets/nordic-ppr-xip/soc/nrf54h20_cpuapp.overlay b/snippets/nordic-ppr-xip/soc/nrf54h20_cpuapp.overlay index 4d02921660b..2d884a3455a 100644 --- a/snippets/nordic-ppr-xip/soc/nrf54h20_cpuapp.overlay +++ b/snippets/nordic-ppr-xip/soc/nrf54h20_cpuapp.overlay @@ -3,10 +3,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -&cpuppr_ram3x_region { - status = "okay"; -}; - &cpuppr_vpr { execution-memory = <&cpuppr_code_partition>; /delete-property/ source-memory; diff --git a/snippets/nordic-ppr/soc/nrf54h20_cpuapp.overlay b/snippets/nordic-ppr/soc/nrf54h20_cpuapp.overlay index 75128f42a13..ae635c9ca9b 100644 --- a/snippets/nordic-ppr/soc/nrf54h20_cpuapp.overlay +++ b/snippets/nordic-ppr/soc/nrf54h20_cpuapp.overlay @@ -3,10 +3,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -&cpuppr_ram3x_region { - status = "okay"; -}; - &uart135 { status = "reserved"; }; diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt index ac75d083869..825be4842fb 100644 --- a/soc/nordic/common/CMakeLists.txt +++ b/soc/nordic/common/CMakeLists.txt @@ -3,6 +3,10 @@ add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr) +if(CONFIG_NRF_PERIPHCONF_SECTION OR CONFIG_NRF_HALTIUM_GENERATE_UICR) + add_subdirectory(uicr) +endif() + # Let SystemInit() be called in place of soc_reset_hook() by default. zephyr_linker_symbol(SYMBOL soc_reset_hook EXPR "@SystemInit@") diff --git a/soc/nordic/common/Kconfig b/soc/nordic/common/Kconfig index 059274fd299..782d9452b67 100644 --- a/soc/nordic/common/Kconfig +++ b/soc/nordic/common/Kconfig @@ -49,3 +49,4 @@ source "subsys/logging/Kconfig.template.log_config" endif # MRAM_LATENCY rsource "vpr/Kconfig" +rsource "uicr/Kconfig" diff --git a/soc/nordic/common/uicr/CMakeLists.txt b/soc/nordic/common/uicr/CMakeLists.txt new file mode 100644 index 00000000000..0bde6b47f57 --- /dev/null +++ b/soc/nordic/common/uicr/CMakeLists.txt @@ -0,0 +1,36 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_NRF_PERIPHCONF_SECTION) + zephyr_linker_sources(SECTIONS uicr.ld) +endif() + +if(CONFIG_NRF_HALTIUM_GENERATE_UICR) + if(CONFIG_NRF_PERIPHCONF_SECTION) + set(in_periphconf_elf_arg + --in-periphconf-elf $ + ) + endif() + + if(CONFIG_NRF_HALTIUM_UICR_PERIPHCONF) + set(periphconf_hex_file ${PROJECT_BINARY_DIR}/periphconf.hex) + set(out_periphconf_hex_arg + --out-periphconf-hex ${periphconf_hex_file} + ) + list(APPEND optional_byproducts ${periphconf_hex_file}) + endif() + + set(uicr_hex_file ${PROJECT_BINARY_DIR}/uicr.hex) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${CMAKE_COMMAND} -E env PYTHONPATH=${ZEPHYR_BASE}/scripts/dts/python-devicetree/src + ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_LIST_DIR}/gen_uicr.py + --in-config ${DOTCONFIG} + --in-edt-pickle ${EDT_PICKLE} + ${in_periphconf_elf_arg} + ${out_periphconf_hex_arg} + --out-uicr-hex ${uicr_hex_file} + ) + set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts + ${uicr_hex_file} ${optional_byproducts} + ) +endif() diff --git a/soc/nordic/common/uicr/Kconfig b/soc/nordic/common/uicr/Kconfig new file mode 100644 index 00000000000..f132510a7a5 --- /dev/null +++ b/soc/nordic/common/uicr/Kconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config NRF_HALTIUM_GENERATE_UICR + bool "Generate UICR file" + depends on SOC_NRF54H20_CPUAPP + default y + help + Generate UICR HEX file. + +if NRF_HALTIUM_GENERATE_UICR + +config NRF_HALTIUM_UICR_PERIPHCONF + bool "Initialize global domain peripherals" + default y + help + Generates a blob containing static global domain peripheral initialization + values extracted from the build artifacts, and configures UICR.PERIPHCONF + to point at the blob. The initialization values are then loaded ahead of + ahead of the application boot. + +endif + +config NRF_PERIPHCONF_SECTION + bool "Populate global peripheral initialization section" + default y if SOC_NRF54H20_CPUAPP + depends on LINKER_DEVNULL_SUPPORT + imply LINKER_DEVNULL_MEMORY + help + Include static global domain peripheral initialization values from the + build in a dedicated section in the devnull region. diff --git a/soc/nordic/common/uicr/gen_uicr.py b/soc/nordic/common/uicr/gen_uicr.py new file mode 100644 index 00000000000..50f96eab566 --- /dev/null +++ b/soc/nordic/common/uicr/gen_uicr.py @@ -0,0 +1,270 @@ +""" +Copyright (c) 2025 Nordic Semiconductor ASA +SPDX-License-Identifier: Apache-2.0 +""" + +from __future__ import annotations + +import argparse +import ctypes as c +import math +import pickle +import re +import sys +from collections import defaultdict +from itertools import groupby + +from elftools.elf.elffile import ELFFile +from intelhex import IntelHex + +# Name of the ELF section containing PERIPHCONF entries. +# Must match the name used in the linker script. +PERIPHCONF_SECTION = "uicr_periphconf_entry" + +# Expected nodelabel of the UICR devicetree node, used to extract its location from the devicetree. +UICR_NODELABEL = "uicr" +# Nodelabel of the PERIPHCONF devicetree node, used to extract its location from the devicetree. +PERIPHCONF_NODELABEL = "periphconf_partition" + +# Common values for representing enabled/disabled in the UICR format. +ENABLED_VALUE = 0xFFFF_FFFF +DISABLED_VALUE = 0xBD23_28A8 + + +class ScriptError(RuntimeError): ... + + +class PeriphconfEntry(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("regptr", c.c_uint32), + ("value", c.c_uint32), + ] + + +PERIPHCONF_ENTRY_SIZE = c.sizeof(PeriphconfEntry) + + +class Approtect(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("APPLICATION", c.c_uint32), + ("RADIOCORE", c.c_uint32), + ("RESERVED", c.c_uint32), + ("CORESIGHT", c.c_uint32), + ] + + +class Protectedmem(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("SIZE4KB", c.c_uint32), + ] + + +class Recovery(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("PROCESSOR", c.c_uint32), + ("INITSVTOR", c.c_uint32), + ("SIZE4KB", c.c_uint32), + ] + + +class Its(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("ADDRESS", c.c_uint32), + ("APPLICATIONSIZE", c.c_uint32), + ("RADIOCORESIZE", c.c_uint32), + ] + + +class Periphconf(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("ADDRESS", c.c_uint32), + ("MAXCOUNT", c.c_uint32), + ] + + +class Mpcconf(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("ENABLE", c.c_uint32), + ("ADDRESS", c.c_uint32), + ("MAXCOUNT", c.c_uint32), + ] + + +class Uicr(c.LittleEndianStructure): + _pack_ = 1 + _fields_ = [ + ("VERSION", c.c_uint32), + ("RESERVED", c.c_uint32), + ("LOCK", c.c_uint32), + ("RESERVED1", c.c_uint32), + ("APPROTECT", Approtect), + ("ERASEPROTECT", c.c_uint32), + ("PROTECTEDMEM", Protectedmem), + ("RECOVERY", Recovery), + ("ITS", Its), + ("RESERVED2", c.c_uint32 * 7), + ("PERIPHCONF", Periphconf), + ("MPCCONF", Mpcconf), + ] + + +def main() -> None: + parser = argparse.ArgumentParser( + allow_abbrev=False, + description=( + "Generate artifacts for the UICR and associated configuration blobs from application " + "build outputs. User Information Configuration Registers (UICR), in the context of " + "certain Nordic SoCs, are used to configure system resources, like memory and " + "peripherals, and to protect the device in various ways." + ), + ) + parser.add_argument( + "--in-config", + required=True, + type=argparse.FileType("r"), + help="Path to the .config file from the application build", + ) + parser.add_argument( + "--in-edt-pickle", + required=True, + type=argparse.FileType("rb"), + help="Path to the edt.pickle file from the application build", + ) + parser.add_argument( + "--in-periphconf-elf", + dest="in_periphconf_elfs", + default=[], + action="append", + type=argparse.FileType("rb"), + help=( + "Path to an ELF file to extract PERIPHCONF data from. Can be provided multiple times. " + "The PERIPHCONF data from each ELF file is combined in a single list which is sorted " + "by ascending address and cleared of duplicate entries." + ), + ) + parser.add_argument( + "--out-uicr-hex", + required=True, + type=argparse.FileType("w", encoding="utf-8"), + help="Path to write the generated UICR HEX file to", + ) + parser.add_argument( + "--out-periphconf-hex", + default=None, + type=argparse.FileType("w", encoding="utf-8"), + help="Path to write the generated PERIPHCONF HEX file to", + ) + args = parser.parse_args() + + try: + init_values = DISABLED_VALUE.to_bytes(4, "little") * (c.sizeof(Uicr) // 4) + uicr = Uicr.from_buffer_copy(init_values) + + kconfig_str = args.in_config.read() + kconfig = parse_kconfig(kconfig_str) + + edt = pickle.load(args.in_edt_pickle) + + try: + periphconf_partition = edt.label2node[PERIPHCONF_NODELABEL] + except LookupError as e: + raise ScriptError( + "Failed to find a PERIPHCONF partition in the devicetree. " + f"Expected a DT node with label '{PERIPHCONF_NODELABEL}'." + ) from e + + flash_base_address = periphconf_partition.flash_controller.regs[0].addr + periphconf_address = flash_base_address + periphconf_partition.regs[0].addr + periphconf_size = periphconf_partition.regs[0].size + + periphconf_combined = extract_and_combine_periphconfs(args.in_periphconf_elfs) + padding_len = periphconf_size - len(periphconf_combined) + periphconf_final = periphconf_combined + bytes([0xFF for _ in range(padding_len)]) + + if kconfig.get("CONFIG_NRF_HALTIUM_UICR_PERIPHCONF") == "y": + uicr.PERIPHCONF.ENABLE = ENABLED_VALUE + uicr.PERIPHCONF.ADDRESS = periphconf_address + uicr.PERIPHCONF.MAXCOUNT = math.floor(periphconf_size / 8) + + try: + uicr_node = edt.label2node[UICR_NODELABEL] + except LookupError as e: + raise ScriptError( + "Failed to find UICR node in the devicetree. " + f"Expected a DT node with label '{UICR_NODELABEL}'." + ) from e + + uicr_hex = IntelHex() + uicr_hex.frombytes(bytes(uicr), offset=uicr_node.regs[0].addr) + + uicr_hex.write_hex_file(args.out_uicr_hex) + + if args.out_periphconf_hex is not None: + periphconf_hex = IntelHex() + periphconf_hex.frombytes(periphconf_final, offset=periphconf_address) + periphconf_hex.write_hex_file(args.out_periphconf_hex) + + except ScriptError as e: + print(f"Error: {e!s}") + sys.exit(1) + + +def extract_and_combine_periphconfs(elf_files: list[argparse.FileType]) -> bytes: + combined_periphconf = [] + + for in_file in elf_files: + elf = ELFFile(in_file) + conf_section = elf.get_section_by_name(PERIPHCONF_SECTION) + if conf_section is None: + continue + + conf_section_data = conf_section.data() + num_entries = len(conf_section_data) // PERIPHCONF_ENTRY_SIZE + periphconf = (PeriphconfEntry * num_entries).from_buffer_copy(conf_section_data) + combined_periphconf.extend(periphconf) + + combined_periphconf.sort(key=lambda e: e.regptr) + deduplicated_periphconf = [] + + for regptr, regptr_entries in groupby(combined_periphconf, key=lambda e: e.regptr): + entries = list(regptr_entries) + if len(entries) > 1: + unique_values = {e.value for e in entries} + if len(unique_values) > 1: + raise ScriptError( + f"PERIPHCONF has conflicting values for register 0x{regptr:09_x}: " + + ", ".join([f"0x{val:09_x}" for val in unique_values]) + ) + deduplicated_periphconf.append(entries[0]) + + final_periphconf = (PeriphconfEntry * len(deduplicated_periphconf))() + for i, entry in enumerate(deduplicated_periphconf): + final_periphconf[i] = entry + + return bytes(final_periphconf) + + +def parse_kconfig(content: str) -> dict[str, str | None]: + result = defaultdict(None) + match_iter = re.finditer( + r"^(?P(SB_)?CONFIG_[^=\s]+)=(?P[^\s#])+$", content, re.MULTILINE + ) + for match in match_iter: + result[match["config"]] = match["value"] + + return result + + +if __name__ == "__main__": + main() diff --git a/soc/nordic/common/uicr/uicr.h b/soc/nordic/common/uicr/uicr.h new file mode 100644 index 00000000000..7ceb12429e2 --- /dev/null +++ b/soc/nordic/common/uicr/uicr.h @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SOC_NORDIC_COMMON_UICR_UICR_H_ +#define SOC_NORDIC_COMMON_UICR_UICR_H_ + +#include +#include +#include +#include +#include + +/** Entry in the PERIPHCONF table. */ +struct uicr_periphconf_entry { + /** Register pointer. */ + uint32_t regptr; + /** Register value. */ + uint32_t value; +} __packed; + +/** @brief Add an entry to the PERIPHCONF table section. + * + * This should typically not be used directly. + * Prefer to use one of the higher level macros. + */ +#define UICR_PERIPHCONF_ADD(_regptr, _value) \ + static STRUCT_SECTION_ITERABLE(uicr_periphconf_entry, \ + _UICR_PERIPHCONF_ENTRY_NAME(__COUNTER__)) = { \ + .regptr = (_regptr), \ + .value = (_value), \ + } + +#define _UICR_PERIPHCONF_ENTRY_NAME(_id) __UICR_PERIPHCONF_ENTRY_NAME(_id) +#define __UICR_PERIPHCONF_ENTRY_NAME(_id) _uicr_periphconf_entry_##_id + +/** @brief Add a PERIPHCONF entry for a SPU PERIPH[n].PERM register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Peripheral slave index on the bus (PERIPH[n] register index). + * @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure. + * @param _dmasec If true, set DMASEC to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_PERIPH_PERM_SET(_spu, _index, _secattr, _dmasec, _ownerid) \ + UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->PERIPH[(_index)].PERM, \ + (uint32_t)((((_ownerid) << SPU_PERIPH_PERM_OWNERID_Pos) & \ + SPU_PERIPH_PERM_OWNERID_Msk) | \ + (((_secattr) ? SPU_PERIPH_PERM_SECATTR_Secure \ + : SPU_PERIPH_PERM_SECATTR_NonSecure) \ + << SPU_PERIPH_PERM_SECATTR_Pos) | \ + (((_dmasec) ? SPU_PERIPH_PERM_DMASEC_Secure \ + : SPU_PERIPH_PERM_DMASEC_NonSecure) \ + << SPU_PERIPH_PERM_DMASEC_Pos) | \ + (SPU_PERIPH_PERM_LOCK_Locked << SPU_PERIPH_PERM_LOCK_Pos))) + +/** @brief Add a PERIPHCONF entry for a SPU FEATURE.IPCT.CH[n] register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Feature index. + * @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_FEATURE_IPCT_CH_SET(_spu, _index, _secattr, _ownerid) \ + UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.IPCT.CH[_index], \ + _UICR_SPU_FEATURE_VAL(_secattr, _ownerid)) + +/** @brief Add a PERIPHCONF entry for a SPU FEATURE.IPCT.INTERRUPT[n] register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Feature index. + * @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_FEATURE_IPCT_INTERRUPT_SET(_spu, _index, _secattr, _ownerid) \ + UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.IPCT.INTERRUPT[_index], \ + _UICR_SPU_FEATURE_VAL(_secattr, _ownerid)) + +/** @brief Add a PERIPHCONF entry for a SPU FEATURE.DPPIC.CH[n] register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Feature index. + * @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_FEATURE_DPPIC_CH_SET(_spu, _index, _secattr, _ownerid) \ + UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.DPPIC.CH[_index], \ + _UICR_SPU_FEATURE_VAL(_secattr, _ownerid)) + +/** @brief Add a PERIPHCONF entry for a SPU FEATURE.DPPIC.CHG[n] register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Register index. + * @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_FEATURE_DPPIC_CHG_SET(_spu, _index, _secattr, _ownerid) \ + UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.DPPIC.CHG[_index], \ + _UICR_SPU_FEATURE_VAL(_secattr, _ownerid)) + +/** @brief Add a PERIPHCONF entry for a SPU FEATURE.GPIOTE[n].CH[m] register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Feature index (GPIOTE[n] register index). + * @param _subindex Feature subindex (CH[m] register index). + * @param _secattr If true, set the SECATTR to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_FEATURE_GPIOTE_CH_SET(_spu, _index, _subindex, _secattr, _ownerid) \ + UICR_PERIPHCONF_ADD( \ + (uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.GPIOTE[_index].CH[_subindex], \ + _UICR_SPU_FEATURE_VAL(_secattr, _ownerid)) + +/** @brief Add a PERIPHCONF entry for a SPU FEATURE.GPIOTE.INTERRUPT[n] register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Feature index. + * @param _subindex Feature subindex. + * @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_FEATURE_GPIOTE_INTERRUPT_SET(_spu, _index, _subindex, _secattr, _ownerid) \ + UICR_PERIPHCONF_ADD( \ + (uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.GPIOTE[_index].INTERRUPT[_subindex], \ + _UICR_SPU_FEATURE_VAL(_secattr, _ownerid)) + +/** @brief Add a PERIPHCONF entry for a SPU FEATURE.GPIO[n].PIN[m] register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Feature index. + * @param _subindex Feature subindex. + * @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_FEATURE_GPIO_PIN_SET(_spu, _index, _subindex, _secattr, _ownerid) \ + UICR_PERIPHCONF_ADD( \ + (uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.GPIO[_index].PIN[_subindex], \ + _UICR_SPU_FEATURE_VAL(_secattr, _ownerid)) + +/** @brief Add a PERIPHCONF entry for a SPU FEATURE.GRTC.CC[n] register value. + * + * @param _spu Global domain SPU instance address. + * @param _index Feature index. + * @param _secattr If true, set SECATTR to secure, otherwise set it to non-secure. + * @param _ownerid OWNERID field value. + */ +#define UICR_SPU_FEATURE_GRTC_CC_SET(_spu, _index, _secattr, _ownerid) \ + UICR_PERIPHCONF_ADD((uint32_t)&((NRF_SPU_Type *)(_spu))->FEATURE.GRTC.CC[_index], \ + _UICR_SPU_FEATURE_VAL(_secattr, _ownerid)) + +/* Common macro for encoding a SPU FEATURE.* register value. + * Note that the MDK SPU_FEATURE_IPCT_CH_ macros are used for all since all the FEATURE registers + * have the same layout with different naming. + */ +#define _UICR_SPU_FEATURE_VAL(_secattr, _ownerid) \ + (uint32_t)((((_ownerid) << SPU_FEATURE_IPCT_CH_OWNERID_Pos) & \ + SPU_FEATURE_IPCT_CH_OWNERID_Msk) | \ + (((_secattr) ? SPU_FEATURE_IPCT_CH_SECATTR_Secure \ + : SPU_FEATURE_IPCT_CH_SECATTR_NonSecure) \ + << SPU_FEATURE_IPCT_CH_SECATTR_Pos) | \ + (SPU_FEATURE_IPCT_CH_LOCK_Locked << SPU_FEATURE_IPCT_CH_LOCK_Pos)) + +/** @brief Add PERIPHCONF entries for configuring IPCMAP CHANNEL.SOURCE[n] and CHANNEL.SINK[n]. + * + * @param _index CHANNEL.SOURCE[n]/CHANNEL.SINK[n] register index. + * @param _source_domain DOMAIN field value in CHANNEL[n].SOURCE. + * @param _source_ch SOURCE field value in CHANNEL[n].SOURCE. + * @param _sink_domain DOMAIN field value in CHANNEL[n].SINK. + * @param _sink_ch SINK field value in CHANNEL[n].SINK. + */ +#define UICR_IPCMAP_CHANNEL_CFG(_index, _source_domain, _source_ch, _sink_domain, _sink_ch) \ + UICR_IPCMAP_CHANNEL_SOURCE_SET(_index, _source_domain, _source_ch, 1); \ + UICR_IPCMAP_CHANNEL_SINK_SET(_index, _sink_domain, _sink_ch) + +#define UICR_IPCMAP_CHANNEL_SOURCE_SET(_index, _domain, _ch, _enable) \ + UICR_PERIPHCONF_ADD((uint32_t)&NRF_IPCMAP->CHANNEL[(_index)].SOURCE, \ + (uint32_t)((((_domain) << IPCMAP_CHANNEL_SOURCE_DOMAIN_Pos) & \ + IPCMAP_CHANNEL_SOURCE_DOMAIN_Msk) | \ + (((_ch) << IPCMAP_CHANNEL_SOURCE_SOURCE_Pos) & \ + IPCMAP_CHANNEL_SOURCE_SOURCE_Msk) | \ + (((_enable) ? IPCMAP_CHANNEL_SOURCE_ENABLE_Enabled \ + : IPCMAP_CHANNEL_SOURCE_ENABLE_Disabled) \ + << IPCMAP_CHANNEL_SOURCE_ENABLE_Pos))) + +#define UICR_IPCMAP_CHANNEL_SINK_SET(_index, _domain, _ch) \ + UICR_PERIPHCONF_ADD((uint32_t)&NRF_IPCMAP->CHANNEL[(_index)].SINK, \ + (uint32_t)((((_domain) << IPCMAP_CHANNEL_SINK_DOMAIN_Pos) & \ + IPCMAP_CHANNEL_SINK_DOMAIN_Msk) | \ + (((_ch) << IPCMAP_CHANNEL_SINK_SINK_Pos) & \ + IPCMAP_CHANNEL_SINK_SINK_Msk))) + +/** @brief Add a PERIPHCONF entry for an IRQMAP IRQ[n].SINK register value. + * + * @param _irqnum IRQ number (IRQ[n] register index). + * @param _processor Processor to route the interrupt to (PROCESSORID field value). + */ +#define UICR_IRQMAP_IRQ_SINK_SET(_irqnum, _processor) \ + UICR_PERIPHCONF_ADD((uint32_t)&NRF_IRQMAP->IRQ[(_irqnum)].SINK, \ + (uint32_t)(((_processor) << IRQMAP_IRQ_SINK_PROCESSORID_Pos) & \ + IRQMAP_IRQ_SINK_PROCESSORID_Msk)) + +/** @brief Add a PERIPHCONF entry for configuring a GPIO PIN_CNF[n] CTRLSEL field value. + * + * @param _gpio GPIO instance address. + * @param _pin Pin number (PIN_CNF[n] register index). + * @param _ctrlsel CTRLSEL field value. + */ +#define UICR_GPIO_PIN_CNF_CTRLSEL_SET(_gpio, _pin, _ctrlsel) \ + UICR_PERIPHCONF_ADD( \ + (uint32_t)&((NRF_GPIO_Type *)(_gpio))->PIN_CNF[(_pin)], \ + ((GPIO_PIN_CNF_ResetValue) | \ + (uint32_t)(((_ctrlsel) << GPIO_PIN_CNF_CTRLSEL_Pos) & GPIO_PIN_CNF_CTRLSEL_Msk))) + +/** @brief Add a PERIPHCONF entry for a PPIB SUBSCRIBE_SEND[n] register. + * + * @param _ppib Global domain PPIB instance address. + * @param _ppib_ch PPIB channel number. + */ +#define UICR_PPIB_SUBSCRIBE_SEND_ENABLE(_ppib, _ppib_ch) \ + UICR_PERIPHCONF_ADD((uint32_t)&((NRF_PPIB_Type *)(_ppib))->SUBSCRIBE_SEND[(_ppib_ch)], \ + (uint32_t)PPIB_SUBSCRIBE_SEND_EN_Msk) + +/** @brief Add a PERIPHCONF entry for a PPIB PUBLISH_RECEIVE[n] register. + * + * @param _ppib Global domain PPIB instance address. + * @param _ppib_ch PPIB channel number. + */ +#define UICR_PPIB_PUBLISH_RECEIVE_ENABLE(_ppib, _ppib_ch) \ + UICR_PERIPHCONF_ADD((uint32_t)&((NRF_PPIB_Type *)(_ppib))->PUBLISH_RECEIVE[(_ppib_ch)], \ + (uint32_t)PPIB_PUBLISH_RECEIVE_EN_Msk) + +/* The definitions below are not currently available in the MDK but are needed for the macros + * above. When they are, this can be deleted. + */ +#ifndef IPCMAP_CHANNEL_SOURCE_SOURCE_Msk + +typedef struct { + __IOM uint32_t SOURCE; + __IOM uint32_t SINK; +} NRF_IPCMAP_CHANNEL_Type; + +#define IPCMAP_CHANNEL_SOURCE_SOURCE_Pos (0UL) +#define IPCMAP_CHANNEL_SOURCE_SOURCE_Msk (0xFUL << IPCMAP_CHANNEL_SOURCE_SOURCE_Pos) +#define IPCMAP_CHANNEL_SOURCE_DOMAIN_Pos (8UL) +#define IPCMAP_CHANNEL_SOURCE_DOMAIN_Msk (0xFUL << IPCMAP_CHANNEL_SOURCE_DOMAIN_Pos) +#define IPCMAP_CHANNEL_SOURCE_ENABLE_Pos (31UL) +#define IPCMAP_CHANNEL_SOURCE_ENABLE_Disabled (0x0UL) +#define IPCMAP_CHANNEL_SOURCE_ENABLE_Enabled (0x1UL) +#define IPCMAP_CHANNEL_SINK_SINK_Pos (0UL) +#define IPCMAP_CHANNEL_SINK_SINK_Msk (0xFUL << IPCMAP_CHANNEL_SINK_SINK_Pos) +#define IPCMAP_CHANNEL_SINK_DOMAIN_Pos (8UL) +#define IPCMAP_CHANNEL_SINK_DOMAIN_Msk (0xFUL << IPCMAP_CHANNEL_SINK_DOMAIN_Pos) + +typedef struct { + __IM uint32_t RESERVED[256]; + __IOM NRF_IPCMAP_CHANNEL_Type CHANNEL[16]; +} NRF_IPCMAP_Type; + +#endif /* IPCMAP_CHANNEL_SOURCE_SOURCE_Msk */ + +#ifndef NRF_IPCMAP +#define NRF_IPCMAP ((NRF_IPCMAP_Type *)0x5F923000UL) +#endif + +#ifndef IRQMAP_IRQ_SINK_PROCESSORID_Msk + +typedef struct { + __IOM uint32_t SINK; +} NRF_IRQMAP_IRQ_Type; + +#define IRQMAP_IRQ_SINK_PROCESSORID_Pos (8UL) +#define IRQMAP_IRQ_SINK_PROCESSORID_Msk (0xFUL << IRQMAP_IRQ_SINK_PROCESSORID_Pos) + +typedef struct { + __IM uint32_t RESERVED[256]; + __IOM NRF_IRQMAP_IRQ_Type IRQ[480]; +} NRF_IRQMAP_Type; + +#endif /* IRQMAP_IRQ_SINK_PROCESSORID_Msk */ + +#ifndef NRF_IRQMAP +#define NRF_IRQMAP ((NRF_IRQMAP_Type *)0x5F924000UL) +#endif /* NRF_IRQMAP */ + +#ifndef GPIO_PIN_CNF_CTRLSEL_Pos + +#define GPIO_PIN_CNF_CTRLSEL_Pos (28UL) +#define GPIO_PIN_CNF_CTRLSEL_Msk (0x7UL << GPIO_PIN_CNF_CTRLSEL_Pos) +#define GPIO_PIN_CNF_CTRLSEL_Min (0x0UL) +#define GPIO_PIN_CNF_CTRLSEL_Max (0x7UL) +#define GPIO_PIN_CNF_CTRLSEL_GPIO (0x0UL) +#define GPIO_PIN_CNF_CTRLSEL_VPR (0x1UL) +#define GPIO_PIN_CNF_CTRLSEL_GRC (0x1UL) +#define GPIO_PIN_CNF_CTRLSEL_SecureDomain (0x2UL) +#define GPIO_PIN_CNF_CTRLSEL_PWM (0x2UL) +#define GPIO_PIN_CNF_CTRLSEL_I3C (0x2UL) +#define GPIO_PIN_CNF_CTRLSEL_Serial (0x3UL) +#define GPIO_PIN_CNF_CTRLSEL_HSSPI (0x3UL) +#define GPIO_PIN_CNF_CTRLSEL_RadioCore (0x4UL) +#define GPIO_PIN_CNF_CTRLSEL_EXMIF (0x4UL) +#define GPIO_PIN_CNF_CTRLSEL_CELL (0x4UL) +#define GPIO_PIN_CNF_CTRLSEL_DTB (0x6UL) +#define GPIO_PIN_CNF_CTRLSEL_TND (0x7UL) + +#endif /* GPIO_PIN_CNF_CTRLSEL_Pos */ + +#endif /* SOC_NORDIC_COMMON_UICR_UICR_H_ */ diff --git a/soc/nordic/common/uicr/uicr.ld b/soc/nordic/common/uicr/uicr.ld new file mode 100644 index 00000000000..210495b1c66 --- /dev/null +++ b/soc/nordic/common/uicr/uicr.ld @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +SECTION_PROLOGUE(uicr_periphconf_entry,(COPY),SUBALIGN(Z_LINK_ITERABLE_SUBALIGN)) +{ + Z_LINK_ITERABLE(uicr_periphconf_entry); +} GROUP_ROM_LINK_IN(DEVNULL_REGION, DEVNULL_REGION) diff --git a/soc/nordic/nrf54h/CMakeLists.txt b/soc/nordic/nrf54h/CMakeLists.txt index 23c1cab1e77..a7deb7d66de 100644 --- a/soc/nordic/nrf54h/CMakeLists.txt +++ b/soc/nordic/nrf54h/CMakeLists.txt @@ -9,6 +9,7 @@ if(CONFIG_ARM) endif() zephyr_library_sources_ifdef(CONFIG_PM_S2RAM pm_s2ram.c) +zephyr_library_sources_ifdef(CONFIG_NRF_PERIPHCONF_SECTION uicr_periphconf_table.c) zephyr_include_directories(.) diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig index c0e619cd1e2..268c8db7bac 100644 --- a/soc/nordic/nrf54h/Kconfig +++ b/soc/nordic/nrf54h/Kconfig @@ -10,6 +10,7 @@ config SOC_SERIES_NRF54HX select SOC_EARLY_INIT_HOOK if ARM select SOC_LATE_INIT_HOOK if SOC_NRF54H20_CPURAD_ENABLE select NRF_PLATFORM_HALTIUM + select EXPERIMENTAL if MCUBOOT config SOC_NRF54H20_CPUAPP_COMMON bool @@ -77,6 +78,13 @@ config SOC_NRF54H20_CPURAD_ENABLE Radiocore, and also power will be requested to the Radiocore subsystem. The Radiocore will then start executing instructions. +config SOC_NRF54H20_CPURAD_ENABLE_CHECK_VTOR + bool "Check VTOR before booting Radio core" + default y + depends on SOC_NRF54H20_CPURAD_ENABLE + help + Verify that VTOR is not 0xFFFFFFFF before booting the Radiocore. + config SOC_NRF54H20_CPURAD select SOC_NRF54H20_CPURAD_COMMON @@ -88,6 +96,3 @@ config SOC_NRF54H20_CPUFLPR rsource "bicr/Kconfig" rsource "gpd/Kconfig" - -config SOC_NRF54H20_IRON - select EXPERIMENTAL if MCUBOOT diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp index 595cc2d3886..69bde826ba4 100644 --- a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp @@ -8,9 +8,6 @@ if SOC_NRF54H20_CPUAPP config NUM_IRQS default 471 -config NRF_REGTOOL_GENERATE_UICR - default y - config SHELL_BACKEND_SERIAL default n if NRF_ETR_SHELL diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad index 1fffdeae6d2..8f86835b92c 100644 --- a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpurad @@ -8,9 +8,6 @@ if SOC_NRF54H20_CPURAD config NUM_IRQS default 471 -config NRF_REGTOOL_GENERATE_UICR - default y - config PM default y diff --git a/soc/nordic/nrf54h/Kconfig.soc b/soc/nordic/nrf54h/Kconfig.soc index ac9101c177c..459854e13b2 100644 --- a/soc/nordic/nrf54h/Kconfig.soc +++ b/soc/nordic/nrf54h/Kconfig.soc @@ -33,10 +33,5 @@ config SOC_NRF54H20_CPUFLPR help nRF54H20 CPUFLPR -config SOC_NRF54H20_IRON - bool - help - Indicates that local domain firmware is compatible with Nordic IRONside SE. - config SOC default "nrf54h20" if SOC_NRF54H20 diff --git a/soc/nordic/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c index 87eda3a13a4..dc0a0edf90c 100644 --- a/soc/nordic/nrf54h/soc.c +++ b/soc/nordic/nrf54h/soc.c @@ -181,20 +181,29 @@ void soc_late_init_hook(void) size_t msg_size = 0; void *radiocore_address = NULL; - if (PARTITION_IS_RUNNING_APP_PARTITION(slot0_partition)) { - radiocore_address = - (void *)(DT_REG_ADDR(DT_GPARENT(DT_NODELABEL(cpurad_slot0_partition))) + - DT_REG_ADDR(DT_NODELABEL(cpurad_slot0_partition)) + - CONFIG_ROM_START_OFFSET); #if DT_NODE_EXISTS(DT_NODELABEL(cpurad_slot1_partition)) - } else if (PARTITION_IS_RUNNING_APP_PARTITION(slot1_partition)) { + if (PARTITION_IS_RUNNING_APP_PARTITION(slot1_partition)) { radiocore_address = (void *)(DT_REG_ADDR(DT_GPARENT(DT_NODELABEL(cpurad_slot1_partition))) + DT_REG_ADDR(DT_NODELABEL(cpurad_slot1_partition)) + CONFIG_ROM_START_OFFSET); -#endif } else { - __ASSERT(radiocore_address != NULL, "Unable to find radio core code parition"); + radiocore_address = + (void *)(DT_REG_ADDR(DT_GPARENT(DT_NODELABEL(cpurad_slot0_partition))) + + DT_REG_ADDR(DT_NODELABEL(cpurad_slot0_partition)) + + CONFIG_ROM_START_OFFSET); + } +#else + radiocore_address = + (void *)(DT_REG_ADDR(DT_GPARENT(DT_NODELABEL(cpurad_slot0_partition))) + + DT_REG_ADDR(DT_NODELABEL(cpurad_slot0_partition)) + + CONFIG_ROM_START_OFFSET); +#endif + + if (IS_ENABLED(CONFIG_SOC_NRF54H20_CPURAD_ENABLE_CHECK_VTOR) && + sys_read32((mem_addr_t)radiocore_address) == 0xFFFFFFFFUL) { + LOG_ERR("Radiocore is not programmed, it will not be started"); + return; } diff --git a/soc/nordic/nrf54h/uicr_periphconf_table.c b/soc/nordic/nrf54h/uicr_periphconf_table.c new file mode 100644 index 00000000000..bf7f85402a6 --- /dev/null +++ b/soc/nordic/nrf54h/uicr_periphconf_table.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +#define SPU131_ADDR (0x5F920000UL) +#define SPU133_ADDR (0x5F990000UL) +#define PPIB130_ADDR (0x5f925000UL) +#define PPIB133_ADDR (0x5f99d000UL) + +/* GRTC channels used by the radio core. */ +UICR_SPU_FEATURE_GRTC_CC_SET(SPU133_ADDR, 8, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_GRTC_CC_SET(SPU133_ADDR, 9, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_GRTC_CC_SET(SPU133_ADDR, 10, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_GRTC_CC_SET(SPU133_ADDR, 11, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_GRTC_CC_SET(SPU133_ADDR, 12, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_GRTC_CC_SET(SPU133_ADDR, 13, true, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_GRTC_CC_SET(SPU133_ADDR, 14, true, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_GRTC_CC_SET(SPU133_ADDR, 15, true, NRF_OWNER_RADIOCORE); + +/* DPPIC130 channels used by the radio core. */ +UICR_SPU_FEATURE_DPPIC_CH_SET(SPU131_ADDR, 0, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_DPPIC_CH_SET(SPU131_ADDR, 2, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_DPPIC_CH_SET(SPU131_ADDR, 3, false, NRF_OWNER_RADIOCORE); + +/* DPPIC132 channels used by the radio core. */ +UICR_SPU_FEATURE_DPPIC_CH_SET(SPU133_ADDR, 0, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_DPPIC_CH_SET(SPU133_ADDR, 2, false, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_DPPIC_CH_SET(SPU133_ADDR, 3, false, NRF_OWNER_RADIOCORE); + +/* Link (DPPIC130 ch.0) <== (DPPIC132 ch.0) */ +UICR_PPIB_PUBLISH_RECEIVE_ENABLE(PPIB130_ADDR, 8); +UICR_PPIB_SUBSCRIBE_SEND_ENABLE(PPIB133_ADDR, 0); + +/* Link (DPPIC130 ch.2) <== (DPPIC132 ch.2) */ +UICR_PPIB_PUBLISH_RECEIVE_ENABLE(PPIB130_ADDR, 10); +UICR_PPIB_SUBSCRIBE_SEND_ENABLE(PPIB133_ADDR, 2); + +/* Link (DPPIC130 ch.3) ==> (DPPIC132 ch.3) */ +UICR_PPIB_SUBSCRIBE_SEND_ENABLE(PPIB130_ADDR, 11); +UICR_PPIB_PUBLISH_RECEIVE_ENABLE(PPIB133_ADDR, 3); + +/* IPCT channels used by the radio core. */ +UICR_SPU_FEATURE_IPCT_CH_SET(SPU131_ADDR, 0, true, NRF_OWNER_RADIOCORE); +UICR_SPU_FEATURE_IPCT_CH_SET(SPU131_ADDR, 2, true, NRF_OWNER_RADIOCORE); + +/* Cross-domain mapping of the IPCT channels. */ +UICR_IPCMAP_CHANNEL_CFG(0, NRF_DOMAIN_RADIOCORE, 2, NRF_DOMAIN_GLOBALSLOW, 2); +UICR_IPCMAP_CHANNEL_CFG(1, NRF_DOMAIN_GLOBALSLOW, 0, NRF_DOMAIN_RADIOCORE, 0); +UICR_IPCMAP_CHANNEL_CFG(2, NRF_DOMAIN_GLOBALSLOW, 2, NRF_DOMAIN_RADIOCORE, 2); diff --git a/soc/nordic/nrf92/Kconfig.soc b/soc/nordic/nrf92/Kconfig.soc index 49891687a29..6ad2fb8a014 100644 --- a/soc/nordic/nrf92/Kconfig.soc +++ b/soc/nordic/nrf92/Kconfig.soc @@ -65,7 +65,7 @@ config SOC_NRF9280_CPUPPR config SOC_NRF9280_IRON bool help - Indicates that local domain firmware is compatible with Nordic IRONside SE. + Indicates that local domain firmware is compatible with Nordic IronSide SE. config SOC default "nrf9280" if SOC_NRF9280 diff --git a/soc/nordic/validate_base_addresses.c b/soc/nordic/validate_base_addresses.c index 1c5c39f74ec..f3c9c8bf214 100644 --- a/soc/nordic/validate_base_addresses.c +++ b/soc/nordic/validate_base_addresses.c @@ -335,7 +335,11 @@ CHECK_DT_REG(uart134, NRF_UARTE134); CHECK_DT_REG(uart135, NRF_UARTE135); CHECK_DT_REG(uart136, NRF_UARTE136); CHECK_DT_REG(uart137, NRF_UARTE137); +#if !defined(CONFIG_SOC_SERIES_NRF54HX) CHECK_DT_REG(uicr, NRF_UICR); +#else +CHECK_DT_REG(uicr, NRF_APPLICATION_UICR); +#endif CHECK_DT_REG(cpuapp_uicr, NRF_APPLICATION_UICR); CHECK_DT_REG(bicr, NRF_APPLICATION_BICR); CHECK_DT_REG(cpurad_uicr, NRF_RADIOCORE_UICR); diff --git a/tests/arch/common/ramfunc/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/arch/common/ramfunc/boards/nrf54h20dk_nrf54h20_cpuapp.overlay deleted file mode 100644 index ad84324a3e9..00000000000 --- a/tests/arch/common/ramfunc/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -&cpuapp_ram0x_region { - nordic,access = ; -}; diff --git a/tests/boards/nrf/coresight_stm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/boards/nrf/coresight_stm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index bf5ba18d204..970377c4d89 100644 --- a/tests/boards/nrf/coresight_stm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/boards/nrf/coresight_stm/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -7,10 +7,6 @@ status = "okay"; }; -&cpuppr_ram3x_region { - status = "okay"; -}; - &cpuflpr_vpr { status = "okay"; }; diff --git a/tests/boards/nrf/nrfs/Kconfig.sysbuild b/tests/boards/nrf/nrfs/Kconfig.sysbuild index f281257725f..6cc7dc9575a 100644 --- a/tests/boards/nrf/nrfs/Kconfig.sysbuild +++ b/tests/boards/nrf/nrfs/Kconfig.sysbuild @@ -6,4 +6,3 @@ source "${ZEPHYR_BASE}/share/sysbuild/Kconfig" config REMOTE_BOARD string default "$(BOARD)/nrf54h20/cpurad" if SOC_NRF54H20_CPUAPP - default "$(BOARD)/nrf54h20/cpuapp" if SOC_NRF54H20_CPURAD diff --git a/tests/boards/nrf/nrfs/prj.conf b/tests/boards/nrf/nrfs/prj.conf index c1a01949d60..ee3da6976c4 100644 --- a/tests/boards/nrf/nrfs/prj.conf +++ b/tests/boards/nrf/nrfs/prj.conf @@ -19,3 +19,5 @@ CONFIG_LOG=y CONFIG_LOG_MODE_IMMEDIATE=n CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y + +CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y diff --git a/tests/boards/nrf/nrfs/testcase.yaml b/tests/boards/nrf/nrfs/testcase.yaml index 315c3cf7f37..d1974f00d7c 100644 --- a/tests/boards/nrf/nrfs/testcase.yaml +++ b/tests/boards/nrf/nrfs/testcase.yaml @@ -1,10 +1,8 @@ common: platform_allow: - nrf54h20dk/nrf54h20/cpuapp - - nrf54h20dk/nrf54h20/cpurad integration_platforms: - nrf54h20dk/nrf54h20/cpuapp - - nrf54h20dk/nrf54h20/cpurad tags: - nrfs harness: ztest diff --git a/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay b/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay deleted file mode 100644 index 0e01ff40bb9..00000000000 --- a/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "nrf54h20dk_nrf54h20_common.dtsi" diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf b/tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf deleted file mode 100644 index 45e31e2fae4..00000000000 --- a/tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Disable dcache -CONFIG_DCACHE=n diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay deleted file mode 100644 index 102abfc8ef2..00000000000 --- a/tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright 2025 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -&wdt010 { - status = "okay"; -}; diff --git a/tests/kconfig/functions/Kconfig b/tests/kconfig/functions/Kconfig index 50868eb7b6a..1e46730c98a 100644 --- a/tests/kconfig/functions/Kconfig +++ b/tests/kconfig/functions/Kconfig @@ -6,60 +6,60 @@ config KCONFIG_ARITHMETIC_ADD_10 default $(add, 10) config KCONFIG_ARITHMETIC_ADD_10_3 - int - default $(add, 10, 3) + hex + default $(add_hex, 10, 3) config KCONFIG_ARITHMETIC_ADD_10_3_2 int - default $(add, 10, 3, 2) + default $(add, 0xa, 3, 0b10) config KCONFIG_ARITHMETIC_SUB_10 int default $(sub, 10) config KCONFIG_ARITHMETIC_SUB_10_3 - int - default $(sub, 10, 3) + hex + default $(sub_hex, 10, 3) config KCONFIG_ARITHMETIC_SUB_10_3_2 int - default $(sub, 10, 3, 2) + default $(sub, 0xa, 3, 0b10) config KCONFIG_ARITHMETIC_MUL_10 int default $(mul, 10) config KCONFIG_ARITHMETIC_MUL_10_3 - int - default $(mul, 10, 3) + hex + default $(mul_hex, 10, 3) config KCONFIG_ARITHMETIC_MUL_10_3_2 int - default $(mul, 10, 3, 2) + default $(mul, 0xa, 3, 0b10) config KCONFIG_ARITHMETIC_DIV_10 int default $(div, 10) config KCONFIG_ARITHMETIC_DIV_10_3 - int - default $(div, 10, 3) + hex + default $(div_hex, 10, 3) config KCONFIG_ARITHMETIC_DIV_10_3_2 int - default $(div, 10, 3, 2) + default $(div, 0xa, 3, 0b10) config KCONFIG_ARITHMETIC_MOD_10 int default $(mod, 10) config KCONFIG_ARITHMETIC_MOD_10_3 - int - default $(mod, 10, 3) + hex + default $(mod_hex, 10, 3) config KCONFIG_ARITHMETIC_MOD_10_3_2 int - default $(mod, 10, 3, 2) + default $(mod, 0xa, 3, 0b10) config KCONFIG_ARITHMETIC_INC_1 int @@ -67,11 +67,11 @@ config KCONFIG_ARITHMETIC_INC_1 config KCONFIG_ARITHMETIC_INC_1_1 string - default "$(inc, 1, 1)" + default "$(inc_hex, 1, 1)" config KCONFIG_ARITHMETIC_INC_INC_1_1 string - default "$(inc, $(inc, 1, 1))" + default "$(inc, $(inc_hex, 0x1, 0b1))" config KCONFIG_ARITHMETIC_DEC_1 int @@ -79,38 +79,38 @@ config KCONFIG_ARITHMETIC_DEC_1 config KCONFIG_ARITHMETIC_DEC_1_1 string - default "$(dec, 1, 1)" + default "$(dec_hex, 1, 1)" config KCONFIG_ARITHMETIC_DEC_DEC_1_1 string - default "$(dec, $(dec, 1, 1))" + default "$(dec, $(dec_hex, 0x1, 0b1))" config KCONFIG_ARITHMETIC_ADD_INC_1_1 int - default $(add, $(inc, 1, 1)) + default $(add, $(inc_hex, 1, 1)) config KCONFIG_MIN_10 int default $(min, 10) config KCONFIG_MIN_10_3 - int - default $(min, 10, 3) + hex + default $(min_hex, 10, 3) config KCONFIG_MIN_10_3_2 int - default $(min, 10, 3, 2) + default $(min, 0xa, 3, 0b10) config KCONFIG_MAX_10 int default $(max, 10) config KCONFIG_MAX_10_3 - int - default $(max, 10, 3) + hex + default $(max_hex, 10, 3) config KCONFIG_MAX_10_3_2 int - default $(max, 10, 3, 2) + default $(max, 0xa, 3, 0b10) source "Kconfig.zephyr" diff --git a/tests/kconfig/functions/src/main.c b/tests/kconfig/functions/src/main.c index 39962c2a4f8..7492e3b5b93 100644 --- a/tests/kconfig/functions/src/main.c +++ b/tests/kconfig/functions/src/main.c @@ -27,10 +27,10 @@ ZTEST(test_kconfig_functions, test_arithmetic) zassert_equal(CONFIG_KCONFIG_ARITHMETIC_MOD_10_3, 10 % 3); zassert_equal(CONFIG_KCONFIG_ARITHMETIC_MOD_10_3_2, 10 % 3 % 2); zassert_equal(CONFIG_KCONFIG_ARITHMETIC_INC_1, 1 + 1); - zassert_str_equal(CONFIG_KCONFIG_ARITHMETIC_INC_1_1, "2,2"); + zassert_str_equal(CONFIG_KCONFIG_ARITHMETIC_INC_1_1, "0x2,0x2"); zassert_str_equal(CONFIG_KCONFIG_ARITHMETIC_INC_INC_1_1, "3,3"); zassert_equal(CONFIG_KCONFIG_ARITHMETIC_DEC_1, 1 - 1); - zassert_str_equal(CONFIG_KCONFIG_ARITHMETIC_DEC_1_1, "0,0"); + zassert_str_equal(CONFIG_KCONFIG_ARITHMETIC_DEC_1_1, "0x0,0x0"); zassert_str_equal(CONFIG_KCONFIG_ARITHMETIC_DEC_DEC_1_1, "-1,-1"); zassert_equal(CONFIG_KCONFIG_ARITHMETIC_ADD_INC_1_1, (1 + 1) + (1 + 1)); } diff --git a/tests/kernel/interrupt/src/nested_irq.c b/tests/kernel/interrupt/src/nested_irq.c index e1edfc3442f..6bfc81b8965 100644 --- a/tests/kernel/interrupt/src/nested_irq.c +++ b/tests/kernel/interrupt/src/nested_irq.c @@ -56,7 +56,8 @@ */ #define IRQ0_PRIO IRQ_DEFAULT_PRIORITY #define IRQ1_PRIO 0x0 -#elif defined(CONFIG_SOC_SERIES_NRF54LX) && defined(CONFIG_RISCV_CORE_NORDIC_VPR) +#elif (defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_NRF54H20_CPUFLPR)) && \ + defined(CONFIG_RISCV_CORE_NORDIC_VPR) #define IRQ0_LINE 16 #define IRQ1_LINE 17 diff --git a/tests/subsys/ipc/ipc_sessions/testcase.yaml b/tests/subsys/ipc/ipc_sessions/testcase.yaml index f76a61b8d68..a4d34a394dd 100644 --- a/tests/subsys/ipc/ipc_sessions/testcase.yaml +++ b/tests/subsys/ipc/ipc_sessions/testcase.yaml @@ -20,6 +20,7 @@ tests: - nrf54h20dk/nrf54h20/cpuapp extra_args: - CONFIG_IPC_TEST_SKIP_CORE_RESET=y + - CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpuppr: platform_allow: - nrf54h20dk/nrf54h20/cpuapp