diff --git a/.github/ISSUE_TEMPLATE/001_bug_report.md b/.github/ISSUE_TEMPLATE/001_bug_report.md deleted file mode 100644 index a3d0677184b..00000000000 --- a/.github/ISSUE_TEMPLATE/001_bug_report.md +++ /dev/null @@ -1,71 +0,0 @@ ---- -name: Bug report -about: Create a report to help us improve Zephyr -title: '' -labels: bug -assignees: '' - ---- - - -**Describe the bug** - - -**To Reproduce** - - -**Expected behavior** - - -**Impact** - - -**Logs and console output** - - -**Environment (please complete the following information):** - - - OS: (e.g. Linux, MacOS, Windows) - - Toolchain (e.g Zephyr SDK, ...) - - Commit SHA or Version used - -**Additional context** - diff --git a/.github/ISSUE_TEMPLATE/001_bug_report.yml b/.github/ISSUE_TEMPLATE/001_bug_report.yml new file mode 100644 index 00000000000..38e7107524c --- /dev/null +++ b/.github/ISSUE_TEMPLATE/001_bug_report.yml @@ -0,0 +1,85 @@ +name: Bug Report +description: File a bug report. +labels: ["bug"] +type: "Bug" +assignees: [] +body: + - type: markdown + attributes: + value: | + Thanks for taking the time to fill out this bug report! + - type: textarea + id: what-happened + attributes: + label: Describe the bug + description: | + A clear and concise description of what the bug is. + + placeholder: | + Please also mention any information which could help others to understand + the problem you're facing: + - What target platform are you using? + - What have you tried to diagnose or workaround this issue? + - Is this a regression? If yes, have you been able to "git bisect" it to a + specific commit? + validations: + required: true + - type: checkboxes + id: regression + attributes: + label: Regression + description: | + Check this box if this is a regression and provide a SHA if you were able to "git bisect" to a specific commit. + options: + - label: This is a regression. + required: false + - type: textarea + id: reproduce + attributes: + label: Steps to reproduce + description: | + Steps to reproduce the behavior. + + placeholder: | + Steps to reproduce the behavior: + 1. mkdir build; cd build + 2. cmake -DBOARD=board\_xyz + 3. make + 4. See error + validations: + required: false + - type: textarea + id: logs + attributes: + label: Relevant log output + description: Please copy and paste any relevant log output. This will be automatically formatted into code, so no need for backticks. + render: shell + - type: dropdown + attributes: + label: Impact + description: Impact of this bug + multiple: false + options: + - Showstopper – Prevents release or major functionality; system unusable. + - Major – Severely degrades functionality; workaround is difficult or unavailable. + - Functional Limitation – Some features not working as expected, but system usable. + - Annoyance – Minor irritation; no significant impact on usability or functionality. + - Intermittent – Occurs occasionally; hard to reproduce. + - Not sure + default: 3 + validations: + required: true + - type: textarea + id: env + attributes: + label: Environment + description: please complete the following information + placeholder: | + - OS: (e.g. Linux, MacOS, Windows) + - Toolchain (e.g Zephyr SDK, ...) + - Commit SHA or Version used + - type: textarea + id: context + attributes: + label: Additional Context + description: Provide other context that could be relevant to the bug, such as pin setting, target configuration,etc. diff --git a/.github/ISSUE_TEMPLATE/008_bin-blobs.md b/.github/ISSUE_TEMPLATE/008_bin-blobs.md deleted file mode 100644 index cde55e03bef..00000000000 --- a/.github/ISSUE_TEMPLATE/008_bin-blobs.md +++ /dev/null @@ -1,41 +0,0 @@ ---- -name: Binary blobs -about: Submit a proposal to integrate binary blob(s) -title: '' -labels: TSC -assignees: '' - ---- - -## Origin - -Describe where the binary blob(s) originate from - -## Type - -- [ ] Precompiled library -- [ ] Firmware image - -## Module - -The Zephyr module that this blob(s) will be referenced from - -## Purpose - -Brief description of what the blob(s) do. It is especially important to describe -the functionality that the blob(s) provide, to the largest extent possible - -## Pull Request - -Link to the Pull request with the actual implementation of the integration. If -you are submitting this as part of a new module you may link to the same Pull -Request that introduced the new module. - -## Dependencies - -What other components do the blob(s) depend on, if any? - -## License - -Document the license the blob(s) are distributed under - diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 00000000000..b9ea2c585a4 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1,5 @@ +blank_issues_enabled: false +contact_links: + - name: Zephyr Community Support + url: https://github.com/zephyrproject-rtos/zephyr/discussions + about: Please ask and answer questions here. diff --git a/.github/workflows/assigner.yml b/.github/workflows/assigner.yml index 3e5988fc698..b4edf9c02a6 100644 --- a/.github/workflows/assigner.yml +++ b/.github/workflows/assigner.yml @@ -32,7 +32,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/backport_issue_check.yml b/.github/workflows/backport_issue_check.yml index a285113aad2..29ec4785246 100644 --- a/.github/workflows/backport_issue_check.yml +++ b/.github/workflows/backport_issue_check.yml @@ -29,7 +29,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/bsim-tests-publish.yaml b/.github/workflows/bsim-tests-publish.yaml index 1cb30f2cfa9..4e9ed86b082 100644 --- a/.github/workflows/bsim-tests-publish.yaml +++ b/.github/workflows/bsim-tests-publish.yaml @@ -24,7 +24,7 @@ jobs: run_id: ${{ github.event.workflow_run.id }} - name: Publish BabbleSim Test Results - uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0 + uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 with: check_name: BabbleSim Test Results comment_mode: off diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 951adc4d267..81473f734e7 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -42,7 +42,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' env: ZEPHYR_TOOLCHAIN_VARIANT: zephyr @@ -98,7 +98,7 @@ jobs: echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - name: Check common triggering files - uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-common-files with: files: | @@ -117,7 +117,7 @@ jobs: modules/hal_nordic/** - name: Check if Bluethooth files changed - uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-bluetooth-files with: files: | @@ -127,7 +127,7 @@ jobs: tests/bsim/bluetooth/ - name: Check if Networking files changed - uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-networking-files with: files: | @@ -140,7 +140,7 @@ jobs: include/zephyr/net/ieee802154* - name: Check if UART files changed - uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-uart-files with: files: | @@ -193,7 +193,7 @@ jobs: junit.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0 + uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 with: check_name: Bsim Test Results files: "junit.xml" diff --git a/.github/workflows/bug_snapshot.yaml b/.github/workflows/bug_snapshot.yaml index e4cc5b7fdda..befa8cdb8bf 100644 --- a/.github/workflows/bug_snapshot.yaml +++ b/.github/workflows/bug_snapshot.yaml @@ -27,7 +27,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 2e085c2bb36..04bc190fd13 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -18,7 +18,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -29,7 +29,7 @@ jobs: CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" CCACHE_REMOTE_ONLY: "true" CCACHE_IGNOREOPTIONS: '-specs=* --specs=*' - LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16 + LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-20 BASE_REF: ${{ github.base_ref }} steps: - name: Apply container owner mismatch workaround @@ -142,12 +142,12 @@ jobs: persist-credentials: false - name: Download Artifacts - uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1 + uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 with: path: artifacts - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip @@ -172,7 +172,7 @@ jobs: junit-clang.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0 + uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 if: always() with: check_name: Unit Test Results diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 74ca259c91f..0a048b95f28 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -17,7 +17,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -69,7 +69,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.4.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip @@ -145,7 +145,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip @@ -156,7 +156,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts - uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1 + uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 with: path: coverage/reports @@ -232,7 +232,7 @@ jobs: - name: Upload coverage to Codecov if: always() - uses: codecov/codecov-action@0565863a31f2c772f9f0395002a31e3f06189574 # v5.4.0 + uses: codecov/codecov-action@ad3126e916f78f00edff4ed0317cf185271ccc2d # v5.4.2 with: env_vars: OS,PYTHON fail_ci_if_error: false diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index f9295f68cd7..869467e030a 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -39,7 +39,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Initialize CodeQL - uses: github/codeql-action/init@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13 + uses: github/codeql-action/init@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 with: languages: ${{ matrix.language }} build-mode: ${{ matrix.build-mode }} @@ -53,6 +53,6 @@ jobs: exit 0 - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13 + uses: github/codeql-action/analyze@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 with: category: "/language:${{matrix.language}}" diff --git a/.github/workflows/coding_guidelines.yml b/.github/workflows/coding_guidelines.yml index cf3d7182f18..b574199cff1 100644 --- a/.github/workflows/coding_guidelines.yml +++ b/.github/workflows/coding_guidelines.yml @@ -17,7 +17,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 62e209860be..22744e8a6ac 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -44,7 +44,7 @@ jobs: git log --pretty=oneline | head -n 10 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/daily_test_version.yml b/.github/workflows/daily_test_version.yml index 02eef3c776f..4b89661a8af 100644 --- a/.github/workflows/daily_test_version.yml +++ b/.github/workflows/daily_test_version.yml @@ -32,7 +32,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index 00a498bbc45..bf61725c260 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -36,7 +36,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index 144f872e5f5..bc147ee3817 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -32,7 +32,7 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 - name: Check if Documentation related files changed - uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3 + uses: tj-actions/changed-files@ed68ef82c095e0d48ec87eccea555d944a631a4c # v46.0.5 id: check-doc-files with: files: | @@ -101,7 +101,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip @@ -203,7 +203,7 @@ jobs: path: zephyr - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index 54ac20d6ad4..9552d72b3d9 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -43,7 +43,7 @@ jobs: - name: Check PR number if: steps.download-artifacts.outputs.found_artifact == 'true' id: check-pr - uses: carpentries/actions/check-valid-pr@e27aa6c531dadd357d2aa4c9a21e90849e23e963 # v0.14.0 + uses: carpentries/actions/check-valid-pr@2e20fd5ee53b691e27455ce7ca3b16ea885140e8 # v0.15.0 with: pr: ${{ env.PR_NUM }} sha: ${{ github.event.workflow_run.head_sha }} diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml index a035936216f..d41d97b9d42 100644 --- a/.github/workflows/errno.yml +++ b/.github/workflows/errno.yml @@ -13,7 +13,7 @@ jobs: check-errno: runs-on: ubuntu-24.04 container: - image: ghcr.io/zephyrproject-rtos/ci:v0.27.4 + image: ghcr.io/zephyrproject-rtos/ci:v0.28.0 steps: - name: Apply container owner mismatch workaround diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index c974b0ded25..1e4eeaa76b4 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -29,7 +29,7 @@ jobs: group: zephyr-runner-v2-linux-x64-4xlarge if: github.repository_owner == 'zephyrproject-rtos' container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' defaults: run: @@ -69,7 +69,7 @@ jobs: fetch-depth: 0 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index 8fb8b11597b..27166aa993a 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -54,7 +54,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.11 @@ -62,7 +62,7 @@ jobs: uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 with: app-path: zephyr - toolchains: all + toolchains: aarch64-zephyr-elf:arc-zephyr-elf:arc64-zephyr-elf:arm-zephyr-eabi:mips-zephyr-elf:riscv64-zephyr-elf:sparc-zephyr-elf:x86_64-zephyr-elf:xtensa-dc233c_zephyr-elf:xtensa-sample_controller32_zephyr-elf - name: Build firmware working-directory: zephyr diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml index fdd6f75e38c..c0ab05502fd 100644 --- a/.github/workflows/manifest.yml +++ b/.github/workflows/manifest.yml @@ -21,7 +21,7 @@ jobs: persist-credentials: false - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip @@ -42,7 +42,7 @@ jobs: west init -l . || true - name: Manifest - uses: zephyrproject-rtos/action-manifest@cb8f6fba6f20b5f8649bd573e80a7583a239894c # v1.7.0 + uses: zephyrproject-rtos/action-manifest@1729cded3fc798cf0de4a789c596dcb9c40eb14c # v1.9.1 with: github-token: ${{ secrets.GITHUB_TOKEN }} manifest-path: 'west.yml' @@ -53,3 +53,5 @@ jobs: verbosity-level: '1' labels: 'manifest' dnm-labels: 'DNM (manifest)' + blobs-added-labels: 'Binary Blobs Added' + blobs-modified-labels: 'Binary Blobs Modified' diff --git a/.github/workflows/pinned-gh-actions.yml b/.github/workflows/pinned-gh-actions.yml index 12ca5963221..c89eb7464f7 100644 --- a/.github/workflows/pinned-gh-actions.yml +++ b/.github/workflows/pinned-gh-actions.yml @@ -16,4 +16,4 @@ jobs: - name: Checkout code uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Ensure SHA pinned actions - uses: zgosalvez/github-actions-ensure-sha-pinned-actions@4830be28ce81da52ec70d65c552a7403821d98d4 # v3.0.23 + uses: zgosalvez/github-actions-ensure-sha-pinned-actions@2d6823da4039243036c86d76f503c84e2ded2517 # v3.0.24 diff --git a/.github/workflows/pr_metadata_check.yml b/.github/workflows/pr_metadata_check.yml index 3564c6352c8..91c997279df 100644 --- a/.github/workflows/pr_metadata_check.yml +++ b/.github/workflows/pr_metadata_check.yml @@ -18,16 +18,23 @@ jobs: name: Prevent Merging runs-on: ubuntu-24.04 steps: - - name: Check for label - if: ${{ contains(github.event.*.labels.*.name, 'DNM') || - contains(github.event.*.labels.*.name, 'DNM (manifest)') || - contains(github.event.*.labels.*.name, 'TSC') || - contains(github.event.*.labels.*.name, 'Architecture Review') || - contains(github.event.*.labels.*.name, 'dev-review') }} + - name: Checkout + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python dependencies run: | - echo "Pull request is labeled as 'DNM', 'TSC', 'Architecture Review' or 'dev-review'." - echo "This workflow fails so that the pull request cannot be merged." - exit 1 + pip install -r scripts/requirements-actions.txt --require-hashes + + - name: Run the check script + run: | + ./scripts/ci/do_not_merge.py -p "${{ github.event.pull_request.number }}" empty_pr_description: if: ${{ github.event.pull_request.body == '' }} diff --git a/.github/workflows/pylib_tests.yml b/.github/workflows/pylib_tests.yml index 29cfd1a5273..edf38bad2b9 100644 --- a/.github/workflows/pylib_tests.yml +++ b/.github/workflows/pylib_tests.yml @@ -35,7 +35,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/scorecards.yml b/.github/workflows/scorecards.yml index d54e76cdcb8..3d4471e70a5 100644 --- a/.github/workflows/scorecards.yml +++ b/.github/workflows/scorecards.yml @@ -56,6 +56,6 @@ jobs: # Upload the results to GitHub's code scanning dashboard (optional). # Commenting out will disable upload of results to your repo's Code Scanning dashboard - name: "Upload to code-scanning" - uses: github/codeql-action/upload-sarif@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13 + uses: github/codeql-action/upload-sarif@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 with: sarif_file: results.sarif diff --git a/.github/workflows/scripts_tests.yml b/.github/workflows/scripts_tests.yml index 0664dbcebc5..4140dacbd63 100644 --- a/.github/workflows/scripts_tests.yml +++ b/.github/workflows/scripts_tests.yml @@ -52,7 +52,7 @@ jobs: git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/stats_merged_prs.yml b/.github/workflows/stats_merged_prs.yml index bb79f772801..5ca8eb9aa9d 100644 --- a/.github/workflows/stats_merged_prs.yml +++ b/.github/workflows/stats_merged_prs.yml @@ -19,7 +19,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/twister-publish.yaml b/.github/workflows/twister-publish.yaml index ceac5a7736b..8c700a81f38 100644 --- a/.github/workflows/twister-publish.yaml +++ b/.github/workflows/twister-publish.yaml @@ -28,7 +28,7 @@ jobs: fetch-depth: 0 persist-credentials: false - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index 946cfff778e..b8ddd8e82ca 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -12,8 +12,8 @@ on: - v*-branch - collab-* schedule: - # Run at 17:00 UTC on every Saturday - - cron: '0 17 * * 6' + # Run at 02:00 UTC on every Sunday + - cron: '0 2 * * 0' permissions: contents: read @@ -51,7 +51,7 @@ jobs: - name: Set up Python if: github.event_name == 'pull_request' - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip @@ -127,7 +127,7 @@ jobs: needs: twister-build-prep if: needs.twister-build-prep.outputs.size != 0 container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -148,7 +148,7 @@ jobs: PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered -j 16' COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} BASE_REF: ${{ github.base_ref }} - LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16 + LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-20 steps: - name: Print cloud service information run: | @@ -325,7 +325,7 @@ jobs: persist-credentials: false - name: Set up Python - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: 3.12 cache: pip @@ -336,7 +336,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Download Artifacts - uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1 + uses: actions/download-artifact@d3f86a106a0bac45b974a628896c90dbdf5c8093 # v4.3.0 with: path: artifacts @@ -356,7 +356,7 @@ jobs: junit.xml - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0 + uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 with: check_name: Unit Test Results files: "**/twister.xml" diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index 394936a29aa..bb95812b7be 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -42,7 +42,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 1e9303e24dd..6cc922adb61 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -18,13 +18,18 @@ on: permissions: contents: read +env: + PYTHONIOENCODING: utf-8 + jobs: twister-tests: name: Twister Black Box Tests - runs-on: ubuntu-24.04 strategy: matrix: python-version: ['3.10', '3.11', '3.12', '3.13'] + os: [ubuntu-24.04, macos-14, windows-2022] + fail-fast: false + runs-on: ${{ matrix.os }} steps: - name: Checkout uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 @@ -33,19 +38,12 @@ jobs: fetch-depth: 0 - name: Set Up Python ${{ matrix.python-version }} - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} cache: pip cache-dependency-path: scripts/requirements-actions.txt - - name: install-packages - working-directory: zephyr - run: | - pip install -r scripts/requirements-actions.txt --require-hashes - sudo apt-get update -y - sudo apt-get install -y lcov - - name: Setup Zephyr project uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 with: @@ -53,6 +51,7 @@ jobs: toolchains: all - name: Run Pytest For Twister Black Box Tests + if: ${{ startsWith(runner.os, 'ubuntu') }} working-directory: zephyr shell: bash env: @@ -63,3 +62,125 @@ jobs: echo "Run twister tests" source zephyr-env.sh PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox/ + + - name: Build firmware No. 1 - basic + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + ./scripts/twister --runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS + + - name: Build firmware No. 2 - save and load with emulation only + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --save-tests tests.file $BASIC_FLAGS + ./scripts/twister --load-tests tests.file --emulation-only $BASIC_FLAGS + rm tests.file + + - name: Build firmware No. 3 - print out test plan + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --test-tree -T tests/kernel/spinlock $BASIC_FLAGS + + - name: Build firmware No. 4 - integration, exclude tag, filter, shuffle, dry run + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --dry-run --integration --subset 1/3 --shuffle-tests --shuffle-tests-seed 1 --filter runnable --exclude-tag audio --exclude-tag driver $BASIC_FLAGS + + - name: Build firmware No. 5 - test, arch, vendor, exclude-platform, platform-reports + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --test kernel.multiprocessing.spinlock --arch x86 --exclude-platform qemu_x86_64 --vendor qemu --platform-reports $BASIC_FLAGS + + - name: Build firmware No. 6 - subtest, platform, rom-ram report, ROM footprint report from buildlog, size report + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --create-rom-ram-report --footprint-report ROM --enable-size-report --footprint-from-buildlog $BASIC_FLAGS + + - name: Build firmware No. 7 - list tags + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --list-tags $BASIC_FLAGS + + - name: Build firmware No. 8 - list tests + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister -T tests/posix/common --list-tests $BASIC_FLAGS + + - name: Build firmware No. 9 - report flags - dir, name, suffix, summary, all-options, filtered + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --report-dir . --report-name test_name --report-suffix suffix --report-summary 0 --report-all-options --report-filtered $BASIC_FLAGS + + - name: Build firmware No. 10 - force platform and toolchain, log level, timestamps, logfile + working-directory: zephyr + shell: bash + run: | + if [ "${{ runner.os }}" = "macOS" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --build-only" + elif [ "${{ runner.os }}" = "Windows" ]; then + EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" + fi + BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --force-platform --platform qemu_x86 --force-toolchain --log-level WARNING --log-file log.file $BASIC_FLAGS + rm log.file diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index 1756664303d..c391148b581 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -39,7 +39,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Set up Python ${{ matrix.python-version }} - uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0 + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: python-version: ${{ matrix.python-version }} cache: pip diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml index 276bdcdd546..e7d51e2294f 100644 --- a/.ruff-excludes.toml +++ b/.ruff-excludes.toml @@ -43,6 +43,9 @@ "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] +"./doc/_scripts/gen_devicetree_rest.py" = [ + "SIM905", # https://docs.astral.sh/ruff/rules/split-static-string +] "./doc/_scripts/redirects.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long ] @@ -233,15 +236,7 @@ "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting ] "./scripts/build/gen_relocate_app.py" = [ - "B028", # https://docs.astral.sh/ruff/rules/no-explicit-stacklevel "E101", # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if - "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get - "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import - "UP037", # https://docs.astral.sh/ruff/rules/quoted-annotation ] "./scripts/build/gen_strerror_table.py" = [ "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders @@ -421,11 +416,10 @@ "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./scripts/dts/gen_driver_kconfig_dts.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] "./scripts/dts/gen_dts_cmake.py" = [ @@ -436,10 +430,11 @@ "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./scripts/dts/python-devicetree/src/devicetree/dtlib.py" = [ - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union ] "./scripts/dts/python-devicetree/src/devicetree/edtlib.py" = [ - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "SIM905", # https://docs.astral.sh/ruff/rules/split-static-string + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union ] "./scripts/dts/python-devicetree/src/devicetree/grutils.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long @@ -453,7 +448,7 @@ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union ] "./scripts/dts/python-devicetree/tests/test_edtlib.py" = [ "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict @@ -578,7 +573,7 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes "UP032", # https://docs.astral.sh/ruff/rules/f-string "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import @@ -620,7 +615,6 @@ ] "./scripts/logging/dictionary/dictionary_parser/log_parser_v3.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get ] "./scripts/logging/dictionary/dictionary_parser/mipi_syst.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -677,9 +671,6 @@ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] -"./scripts/pylib/pytest-twister-harness/src/twister_harness/device/utils.py" = [ - "SIM105", # https://docs.astral.sh/ruff/rules/suppressible-exception -] "./scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -734,6 +725,9 @@ "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler "UP012", # https://docs.astral.sh/ruff/rules/unnecessary-encode-utf8 ] +"./scripts/pylib/pytest-twister-harness/tests/resources/zen_of_python.py" = [ + "SIM905", # https://docs.astral.sh/ruff/rules/split-static-string +] "./scripts/pylib/twister/expr_parser.py" = [ "SIM103", # https://docs.astral.sh/ruff/rules/needless-bool "SIM110", # https://docs.astral.sh/ruff/rules/reimplemented-builtin @@ -780,7 +774,7 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM117", # https://docs.astral.sh/ruff/rules/multiple-with-statements "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./scripts/set_assignees.py" = [ @@ -797,11 +791,6 @@ "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] -"./scripts/support/quartus-flash.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler -] "./scripts/tests/twister/conftest.py" = [ "E402", # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -814,6 +803,14 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "UP026", # https://docs.astral.sh/ruff/rules/deprecated-mock-import ] +"./scripts/tests/twister/test_config_parser.py" = [ + "B017", # https://docs.astral.sh/ruff/rules/assert-raises-exception + "B033", # https://docs.astral.sh/ruff/rules/duplicate-value + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM117", # https://docs.astral.sh/ruff/rules/multiple-with-statements + "UP026", # https://docs.astral.sh/ruff/rules/deprecated-mock-import +] "./scripts/tests/twister/test_data/mixins/test_to_ignore.py" = [ "B011", # https://docs.astral.sh/ruff/rules/assert-false ] @@ -1078,42 +1075,9 @@ "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler "UP004", # https://docs.astral.sh/ruff/rules/useless-object-inheritance "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] -"./scripts/west_commands/bindesc.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP038", # https://docs.astral.sh/ruff/rules/non-pep604-isinstance -] -"./scripts/west_commands/blobs.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] -"./scripts/west_commands/build.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM105", # https://docs.astral.sh/ruff/rules/suppressible-exception - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes - "UP032", # https://docs.astral.sh/ruff/rules/f-string -] -"./scripts/west_commands/build_helpers.py" = [ - "E402", # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP032", # https://docs.astral.sh/ruff/rules/f-string -] -"./scripts/west_commands/completion.py" = [ - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes - "UP032", # https://docs.astral.sh/ruff/rules/f-string -] -"./scripts/west_commands/debug.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/export.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] "./scripts/west_commands/fetchers/__init__.py" = [ "UP032", # https://docs.astral.sh/ruff/rules/f-string ] @@ -1126,14 +1090,6 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler ] -"./scripts/west_commands/flash.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/robot.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] "./scripts/west_commands/run_common.py" = [ "B904", # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict @@ -1161,12 +1117,7 @@ "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters "UP032", # https://docs.astral.sh/ruff/rules/f-string ] -"./scripts/west_commands/simulate.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] "./scripts/west_commands/spdx.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] @@ -1205,9 +1156,8 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] "./scripts/west_commands/tests/test_nrf.py" = [ - "B011", # https://docs.astral.sh/ruff/rules/assert-false "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union ] "./scripts/west_commands/tests/test_nxp_s32dbg.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long @@ -1240,51 +1190,6 @@ "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes "UP032", # https://docs.astral.sh/ruff/rules/f-string ] -"./scripts/west_commands/zspdx/cmakecache.py" = [ - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] -"./scripts/west_commands/zspdx/cmakefileapi.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/zspdx/cmakefileapijson.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM116", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-lookup - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] -"./scripts/west_commands/zspdx/datatypes.py" = [ - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/zspdx/getincludes.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP021", # https://docs.astral.sh/ruff/rules/replace-universal-newlines - "UP022", # https://docs.astral.sh/ruff/rules/replace-stdout-stderr -] -"./scripts/west_commands/zspdx/sbom.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/zspdx/scanner.py" = [ - "SIM113", # https://docs.astral.sh/ruff/rules/enumerate-for-loop - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] -"./scripts/west_commands/zspdx/walker.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters -] -"./scripts/west_commands/zspdx/writer.py" = [ - "E501", # https://docs.astral.sh/ruff/rules/line-too-long - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] "./scripts/zephyr_module.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports @@ -1351,7 +1256,7 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import ] "./tests/drivers/can/host/pytest/test_can.py" = [ @@ -1366,6 +1271,11 @@ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports "UP032", # https://docs.astral.sh/ruff/rules/f-string ] +"./tests/lib/devicetree/memory_region_flags/pytest/test_memory_region_flags.py" = [ + "E402", # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports +] "./tests/misc/check_init_priorities/validate_check_init_priorities_output.py" = [ "E501", # https://docs.astral.sh/ruff/rules/line-too-long "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes @@ -1425,6 +1335,7 @@ exclude = [ "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py", "./doc/_extensions/zephyr/api_overview.py", "./doc/_extensions/zephyr/application.py", + "./doc/_extensions/zephyr/domain/__init__.py", "./doc/_extensions/zephyr/doxybridge.py", "./doc/_extensions/zephyr/doxyrunner.py", "./doc/_extensions/zephyr/doxytooltip/__init__.py", @@ -1476,7 +1387,6 @@ exclude = [ "./scripts/build/gen_kobject_list.py", "./scripts/build/gen_kobject_placeholders.py", "./scripts/build/gen_offset_header.py", - "./scripts/build/gen_relocate_app.py", "./scripts/build/gen_strerror_table.py", "./scripts/build/gen_strsignal_table.py", "./scripts/build/gen_symtab.py", @@ -1495,6 +1405,7 @@ exclude = [ "./scripts/ci/guideline_check.py", "./scripts/ci/stats/merged_prs.py", "./scripts/ci/test_plan.py", + "./scripts/ci/twister_report_analyzer.py", "./scripts/ci/upload_test_results_es.py", "./scripts/ci/version_mgr.py", "./scripts/coredump/coredump_gdbserver.py", @@ -1559,7 +1470,6 @@ exclude = [ "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/qemu_adapter.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/mcumgr.py", - "./scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/shell.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py", "./scripts/pylib/pytest-twister-harness/src/twister_harness/twister_harness_config.py", "./scripts/pylib/pytest-twister-harness/tests/conftest.py", @@ -1597,7 +1507,6 @@ exclude = [ "./scripts/release/list_devicetree_bindings_changes.py", "./scripts/set_assignees.py", "./scripts/snippets.py", - "./scripts/support/quartus-flash.py", "./scripts/tests/twister/conftest.py", "./scripts/tests/twister/pytest_integration/test_harness_pytest.py", "./scripts/tests/twister/test_cmakecache.py", @@ -1664,6 +1573,7 @@ exclude = [ "./scripts/west_commands/fetchers/core.py", "./scripts/west_commands/fetchers/http.py", "./scripts/west_commands/flash.py", + "./scripts/west_commands/patch.py", "./scripts/west_commands/robot.py", "./scripts/west_commands/run_common.py", "./scripts/west_commands/run_tests.py", @@ -1685,7 +1595,6 @@ exclude = [ "./scripts/west_commands/runners/mdb.py", "./scripts/west_commands/runners/misc.py", "./scripts/west_commands/runners/native.py", - "./scripts/west_commands/runners/nios2.py", "./scripts/west_commands/runners/nrf_common.py", "./scripts/west_commands/runners/nrfjprog.py", "./scripts/west_commands/runners/nrfutil.py", @@ -1747,6 +1656,7 @@ exclude = [ "./soc/nuvoton/npcx/common/ecst/ecst.py", "./soc/nuvoton/npcx/common/ecst/ecst_args.py", "./soc/silabs/silabs_sim3/sim3u/gen_crossbar_config.py", + "./tests/bluetooth/classic/sdp_s/pytest/test_sdp.py", "./tests/boot/with_mcumgr/pytest/test_downgrade_prevention.py", "./tests/boot/with_mcumgr/pytest/test_upgrade.py", "./tests/boot/with_mcumgr/pytest/west_sign_wrapper.py", @@ -1755,8 +1665,8 @@ exclude = [ "./tests/drivers/can/host/pytest/test_can.py", "./tests/kernel/timer/timer_behavior/pytest/saleae_logic2.py", "./tests/kernel/timer/timer_behavior/pytest/test_timer.py", + "./tests/lib/devicetree/memory_region_flags/pytest/test_memory_region_flags.py", "./tests/misc/check_init_priorities/validate_check_init_priorities_output.py", - "./tests/misc/llext-edk/pytest/test_edk.py", "./tests/net/lib/lwm2m/interop/pytest/conftest.py", "./tests/net/lib/lwm2m/interop/pytest/leshan.py", "./tests/net/lib/lwm2m/interop/pytest/test_blockwise.py", diff --git a/CMakeLists.txt b/CMakeLists.txt index 74052ded692..0effc0c381c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1104,10 +1104,19 @@ if(CONFIG_CODE_DATA_RELOCATION) endif() if(CONFIG_USERSPACE) - zephyr_get_compile_options_for_lang_as_string(C compiler_flags_priv) + # Go for raw properties here since zephyr_get_compile_options_for_lang() + # processes the list of options, and wraps it in a $" "" - NO_COVERAGE_FLAGS "${compiler_flags_priv}" - ) + KOBJECT_HASH_COMPILE_OPTIONS "${compiler_flags_priv}") + + list(APPEND KOBJECT_HASH_COMPILE_OPTIONS + $ + $) set(PROCESS_GPERF ${ZEPHYR_BASE}/scripts/build/process_gperf.py) endif() @@ -1305,11 +1314,13 @@ if(CONFIG_USERSPACE) add_library( kobj_prebuilt_hash_output_lib OBJECT ${CMAKE_CURRENT_BINARY_DIR}/${KOBJECT_PREBUILT_HASH_OUTPUT_SRC} - ) + ) - set_source_files_properties(${KOBJECT_PREBUILT_HASH_OUTPUT_SRC} - PROPERTIES COMPILE_FLAGS - "${NO_COVERAGE_FLAGS} -fno-function-sections -fno-data-sections") + # set_target_properties sets ALL properties, target_compile_options() adds + # and KOBJECT_HASH_COMPILE_OPTIONS contains all the options. + set_target_properties(kobj_prebuilt_hash_output_lib PROPERTIES + COMPILE_OPTIONS "${KOBJECT_HASH_COMPILE_OPTIONS}" + ) target_compile_definitions(kobj_prebuilt_hash_output_lib PRIVATE $ @@ -1514,9 +1525,9 @@ if(CONFIG_USERSPACE) OBJECT ${CMAKE_CURRENT_BINARY_DIR}/${KOBJECT_HASH_OUTPUT_SRC} ) - set_source_files_properties(${KOBJECT_HASH_OUTPUT_SRC} - PROPERTIES COMPILE_FLAGS - "${NO_COVERAGE_FLAGS} -fno-function-sections -fno-data-sections") + set_target_properties(kobj_hash_output_lib PROPERTIES + COMPILE_OPTIONS "${KOBJECT_HASH_COMPILE_OPTIONS}" + ) target_compile_definitions(kobj_hash_output_lib PRIVATE $ diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 99295612b68..070b4231eee 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -542,9 +542,18 @@ config LTO config COMPILER_WARNINGS_AS_ERRORS bool "Treat warnings as errors" + depends on !DEPRECATION_TEST help Turn on "warning as error" toolchain flags +config DEPRECATION_TEST + bool "Indicate test for deprecated feature" + help + This option is selected by tests which check functionality of + deprecated features. It ensures that COMPILER_WARNINGS_AS_ERRORS + is not selected as that would generate errors when the deprecated + features are used. + config COMPILER_SAVE_TEMPS bool "Save temporary object files" help diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 1d6ce194239..77296a734a6 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -126,6 +126,19 @@ ACPI: tests: - acpi +Aesc Platform: + status: maintained + maintainers: + - dnltz + files: + - soc/aesc/ + - dts/riscv/aesc/ + - boards/aesc/ + files-regex: + - ^drivers/.*aesc(\.c)?$ + labels: + - "area: Aesc Silicon Platform" + Antmicro platforms: status: maintained maintainers: @@ -170,6 +183,7 @@ Arduino Platforms: - facchinm files: - boards/arduino/ + - drivers/*/*modulino* ARM arch: status: maintained @@ -522,6 +536,7 @@ Bluetooth Audio: - tests/bsim/bluetooth/audio_samples/ - tests/bluetooth/shell/audio.conf - tests/bluetooth/tester/overlay-le-audio.conf + - tests/bluetooth/tester/overlay-bt_ll_sw_split.conf - tests/bluetooth/tester/src/audio/ - doc/connectivity/bluetooth/api/audio/ - doc/connectivity/bluetooth/shell/audio/ @@ -853,22 +868,15 @@ Debug: - scripts/coredump/ - samples/subsys/debug/ - doc/services/debugging/ - labels: - - "area: Debugging" - tests: - - debug - -"Debug: Profiling: Perf": - status: odd fixes - files: - doc/services/profiling/perf.rst - samples/subsys/profiling/perf/ - scripts/profiling/stackcollapse.py - subsys/profiling/perf/ labels: - - "area: Profiling / Perf" + - "area: Debugging" tests: - - debug.profiling.perf + - debug + "Debug: Symtab": status: maintained @@ -955,8 +963,6 @@ Devicetree: - include/zephyr/dt-bindings/dt-util.h - dts/binding-template.yaml - dts/bindings/base/ - files-exclude: - - dts/common/nordic/ labels: - "area: Devicetree" tests: @@ -993,6 +999,7 @@ Display drivers: - jfischer-no - danieldegrasse - VynDragon + - jarmouniA files: - drivers/display/ - dts/bindings/display/ @@ -1699,10 +1706,11 @@ Release Notes: - drivers.memc "Drivers: MDIO": - status: odd fixes + status: maintained + maintainers: + - maass-hamburg collaborators: - decsny - - maass-hamburg files: - doc/hardware/peripherals/mdio.rst - drivers/mdio/ @@ -1762,6 +1770,10 @@ Release Notes: "Interrupt Handling": status: odd fixes + collaborators: + - ycsin + - dcpleung + - nashif files: - drivers/interrupt_controller/ - dts/bindings/interrupt-controller/ @@ -1837,6 +1849,8 @@ Release Notes: status: odd fixes collaborators: - aasinclair + - nordic-auko + - seov-nordic files: - drivers/mfd/ - include/zephyr/drivers/mfd/ @@ -1864,7 +1878,8 @@ Release Notes: "Drivers: Regulators": status: maintained maintainers: - - gmarull + - nordic-auko + - seov-nordic collaborators: - danieldegrasse - aasinclair @@ -1978,7 +1993,7 @@ Release Notes: "Drivers: PTP Clock": status: maintained maintainers: - - tbursztyka + - yangbolu1991 files: - drivers/ptp_clock/ - include/zephyr/drivers/ptp_clock.h @@ -2131,6 +2146,7 @@ Release Notes: - jbehrensnx files: - drivers/stepper/ + - include/zephyr/drivers/stepper/ - include/zephyr/drivers/stepper.h - dts/bindings/stepper/ - doc/hardware/peripherals/stepper.rst @@ -2157,11 +2173,13 @@ Release Notes: - "area: Timer" "Drivers: Video": - status: odd fixes - collaborators: - - loicpoulain + status: maintained + maintainers: - josuah - ngphibang + collaborators: + - loicpoulain + - avolmat-st files: - drivers/video/ - include/zephyr/drivers/video.h @@ -2175,6 +2193,20 @@ Release Notes: tests: - drivers.video +"Drivers: VIRTIO": + status: maintained + maintainers: + - fkokosinski + - tgorochowik + collaborators: + - kgugala + files: + - drivers/virtio/ + - dts/bindings/virtio/ + - include/zephyr/virtio/ + labels: + - "area: VIRTIO" + "Drivers: W1": status: maintained maintainers: @@ -2291,9 +2323,7 @@ Release Notes: - "area: Display Controller" "Drivers: Virtualization": - status: maintained - maintainers: - - tbursztyka + status: odd fixes files: - drivers/virtualization/ - tests/drivers/virtualization/ @@ -2856,7 +2886,6 @@ Networking: - jukkar collaborators: - pdgendt - - tbursztyka - ssharks files: - scripts/net/ @@ -2925,7 +2954,6 @@ Networking: - jhedberg collaborators: - rlubos - - tbursztyka - jukkar files: - doc/services/net_buf/ @@ -3137,25 +3165,6 @@ Networking: tests: - net.http -NIOS-2 arch: - status: maintained - maintainers: - - nashif - files: - - arch/nios2/ - - dts/nios2/intel/ - - boards/common/nios2.board.cmake - - soc/altr/*nios2*/ - - include/zephyr/arch/nios2/ - - tests/boards/altera_max10/ - - boards/qemu/nios2/ - - boards/altr/max10/ - - scripts/support/quartus-flash.py - labels: - - "area: NIOS2" - tests: - - boards.altera_max10 - nRF BSIM: status: maintained maintainers: @@ -3508,19 +3517,20 @@ Bouffalolab Platforms: status: maintained maintainers: - nandojve + - VynDragon files: - - boards/bouffalolab/ + - boards/bflb/ - drivers/*/*bflb* - - dts/riscv/bouffalolab/ + - dts/riscv/bflb/ - dts/bindings/*/bflb,* - - soc/bouffalolab/ + - soc/bflb/ labels: - "platform: bouffalolab" Broadcom Platforms: status: odd fixes files: - - dts/arm/broadcom/ + - dts/*/broadcom/ - soc/brcm/ - boards/brcm/ @@ -3785,7 +3795,7 @@ Intel Platforms (Agilex): labels: - "platform: Intel SoC FPGA Agilex" -NXP Drivers: +NXP Platform Drivers: status: maintained maintainers: - dleach02 @@ -3826,21 +3836,23 @@ NXP Drivers: - "platform: NXP Drivers" description: NXP Drivers -NXP Wireless: +NXP Platform Wireless: status: maintained maintainers: - dleach02 collaborators: - MaochenWang1 - axelnxp + - George-Stefan files: - drivers/wifi/nxp/ - drivers/bluetooth/hci/*nxp* - drivers/ieee802154/ieee802154_kw41z.c + - drivers/*/*mcxw*.c labels: - "platform: NXP Drivers" -NXP MCUX USB: +NXP Platform MCUX USB: status: maintained maintainers: - mmahadevan108 @@ -3893,6 +3905,7 @@ NXP Platforms (S32): - manuargue collaborators: - Dat-NguyenDuy + - congnguyenhuu files: - boards/nxp/*s32*/ - boards/common/*nxp_s32* @@ -3905,6 +3918,8 @@ NXP Platforms (S32): - include/zephyr/dt-bindings/*/nxp-s32* - include/zephyr/dt-bindings/*/nxp_s32* - include/zephyr/drivers/*/*nxp_s32* + files-exclude: + - boards/nxp/ucans32k1sic/ labels: - "platform: NXP S32" description: NXP S32 platforms and S32-specific drivers @@ -3917,6 +3932,8 @@ NXP Platforms (MPU): - dleach02 - dbaluta - iuliana-prodan + - yangbolu1991 + - Zhiqiang-Hou files: - dts/arm64/nxp/ - dts/arm/nxp/nxp_imx* @@ -3947,10 +3964,13 @@ NXP Platforms (Robotics Products): maintainers: - bperseghetti - PetervdPerk-NXP + collaborators: + - manuargue files: - boards/nxp/vmu*/ - boards/nxp/rddrone_fmuk66/ - boards/nxp/mr_canhubk3/ + - boards/nxp/ucans32k1sic/ labels: - "platform: NXP Robotics" description: NXP Robotics Module Platform Products @@ -4019,13 +4039,19 @@ nRF Platforms: files: - boards/nordic/ - drivers/*/*nrf*.c + - drivers/*/*nrf*/ - drivers/*/*nordic*/ - soc/nordic/ - samples/boards/nordic/ - dts/*/nordic/ - dts/bindings/*/nordic,* + - include/zephyr/drivers/*/*nrf*.h + - include/zephyr/drivers/*/*nrf*/ + - include/zephyr/dt-bindings/*/nordic*.h + - include/zephyr/dt-bindings/*/nrf*.h - tests/drivers/*/*nrf*/ - snippets/nordic*/ + - tests/boards/nrf/ labels: - "platform: nRF" @@ -4171,6 +4197,7 @@ STM32 Platforms: - marwaiehm-st - mathieuchopstm - djiatsaf-st + - etienne-lms files: - boards/st/ - drivers/*/*stm32*.c @@ -4238,8 +4265,7 @@ Espressif Platforms: - drivers/*/*esp32*.c - boards/espressif/ - soc/espressif/ - - dts/xtensa/espressif/ - - dts/riscv/espressif/ + - dts/*/espressif/ - dts/bindings/*/*esp32* - samples/boards/espressif/ - tests/boards/espressif/ @@ -4269,6 +4295,20 @@ ITE Platforms: labels: - "platform: ITE" +TI MSPM0 Platforms: + status: maintained + maintainers: + - ssekar15 + files: + - soc/ti/mspm0/ + - boards/ti/lp_mspm0g3507/ + - dts/arm/ti/mspm0/ + - dts/bindings/*/*mspm0* + - drivers/*/*_mspm0* + - modules/Kconfig.mspm0 + labels: + - "platform: Texas Instruments MSPM0" + TI SimpleLink Platforms: status: maintained maintainers: @@ -4282,7 +4322,7 @@ TI SimpleLink Platforms: - drivers/*/*cc25* - drivers/*/*cc26* - drivers/*/*cc32* - - dts/arm/ti/ + - dts/arm/ti/cc* - dts/bindings/*/ti,* - soc/ti/simplelink/ - dts/bindings/*/ti,* @@ -4303,6 +4343,8 @@ TI K3 Platforms: - drivers/*/*davinci* - drivers/*/*omap* - drivers/*/*ti_k3* + - dts/arm/ti/am6* + - dts/arm/ti/j7* - dts/bindings/*/ti,k3* - soc/ti/k3/ labels: @@ -4571,6 +4613,9 @@ TDK Sensors: status: maintained maintainers: - RobinKastberg + collaborators: + - bjorniuppsala + - LoveKarlsson files: - cmake/*/iar/ - include/zephyr/toolchain/iar.h @@ -4917,14 +4962,17 @@ West: labels: - "platform: ADI" -"West project: hal_altera": - status: odd fixes +"West project: hal_afbr": + status: maintained + maintainers: + - ubieda + - bperseghetti collaborators: - - nashif - files: - - modules/Kconfig.altera + - PetervdPerk-NXP + - jgoppert + files: [] labels: - - "platform: Altera" + - "platform: Broadcom" "West project: hal_ambiq": status: odd fixes @@ -4952,6 +5000,7 @@ West: status: maintained maintainers: - nandojve + - VynDragon files: - modules/hal_bouffalolab/ labels: @@ -5652,6 +5701,7 @@ Continuous Integration: - kartben files: - .github/ + - scripts/requirements-actions.* - scripts/ci/ - scripts/make_bugs_pickle.py - .checkpatch.conf @@ -5791,3 +5841,19 @@ zbus: - "area: llext" tests: - llext + +RX arch: + status: maintained + maintainers: + - duynguyenxa + files: + - arch/rx/ + - include/zephyr/arch/rx/ + - dts/rx/ + - boards/qemu/rx/ + - soc/renesas/rx/ + - tests/arch/rx/ + labels: + - "area: RX" + tests: + - arch.rx diff --git a/README.rst b/README.rst index 9472db6d5ee..a82f73b6fb0 100644 --- a/README.rst +++ b/README.rst @@ -24,7 +24,7 @@ resource-constrained systems: from simple embedded environmental sensors and LED wearables to sophisticated smart watches and IoT wireless gateways. The Zephyr kernel supports multiple architectures, including ARM (Cortex-A, -Cortex-R, Cortex-M), Intel x86, ARC, Nios II, Tensilica Xtensa, and RISC-V, +Cortex-R, Cortex-M), Intel x86, ARC, Tensilica Xtensa, and RISC-V, SPARC, MIPS, and a large number of `supported boards`_. .. below included in doc/introduction/introduction.rst diff --git a/SDK_VERSION b/SDK_VERSION index c5523bd09b1..7cca7711a0d 100644 --- a/SDK_VERSION +++ b/SDK_VERSION @@ -1 +1 @@ -0.17.0 +0.17.1 diff --git a/arch/Kconfig b/arch/Kconfig index 8e9b7040b11..646b83c9d65 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -104,15 +104,6 @@ config X86 help x86 architecture -config NIOS2 - bool - select ARCH_IS_SET - select ATOMIC_OPERATIONS_C - imply XIP - select ARCH_HAS_TIMING_FUNCTIONS - help - Nios II Gen 2 architecture - config RISCV bool select ARCH_IS_SET @@ -167,6 +158,15 @@ config ARCH_POSIX help POSIX (native) architecture +config RX + bool + select ARCH_IS_SET + select ATOMIC_OPERATIONS_C + select USE_SWITCH + select USE_SWITCH_SUPPORTED + help + Renesas RX architecture + config ARCH_IS_SET bool help @@ -228,7 +228,7 @@ config SRAM_BASE_ADDRESS /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files. -if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV +if ARC || ARM || ARM64 || X86 || RISCV || RX # Workaround for not being able to have commas in macro arguments DT_CHOSEN_Z_FLASH := zephyr,flash @@ -251,7 +251,7 @@ config FLASH_BASE_ADDRESS normally set by the board's defconfig file and the user should generally avoid modifying it via the menu configuration. -endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV +endif # ARM || ARM64 || ARC || X86 || RISCV || RX if ARCH_HAS_TRUSTED_EXECUTION @@ -515,6 +515,12 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN to be aligned to architecture specific size. The default size is 0 for no alignment. +config ARCH_DEVICE_STATE_ALIGN + int "Alignment size of device state" + default 4 + help + This option controls alignment size of device state. + choice IRQ_VECTOR_TABLE_TYPE prompt "IRQ vector table type" depends on GEN_IRQ_VECTOR_TABLE diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index bf3ab454a2c..113ac502973 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -26,49 +26,6 @@ #include #include -/* XXX - keep for future use in full-featured cache APIs */ -#if 0 -/** - * @brief Disable the i-cache if present - * - * For those ARC CPUs that have a i-cache present, - * invalidate the i-cache and then disable it. - */ - -static void disable_icache(void) -{ - unsigned int val; - - val = z_arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD); - val &= 0xff; /* version field */ - if (val == 0) { - return; /* skip if i-cache is not present */ - } - z_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0); - __builtin_arc_nop(); - z_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1); -} - -/** - * @brief Invalidate the data cache if present - * - * For those ARC CPUs that have a data cache present, - * invalidate the data cache. - */ - -static void invalidate_dcache(void) -{ - unsigned int val; - - val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD); - val &= 0xff; /* version field */ - if (val == 0) { - return; /* skip if d-cache is not present */ - } - z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1); -} -#endif - #ifdef CONFIG_ISA_ARCV3 /* NOTE: it will be called from early C code - we must NOT use global / static variables in it! */ static void arc_cluster_scm_enable(void) @@ -92,8 +49,8 @@ static void arc_cluster_scm_enable(void) /* Invalidate SCM before enabling. */ arc_cln_write_reg_nolock(ARC_CLN_CACHE_CMD, ARC_CLN_CACHE_CMD_OP_REG_INV | ARC_CLN_CACHE_CMD_INCR); - while (arc_cln_read_reg_nolock(ARC_CLN_CACHE_STATUS) & ARC_CLN_CACHE_STATUS_BUSY) - ; + while (arc_cln_read_reg_nolock(ARC_CLN_CACHE_STATUS) & ARC_CLN_CACHE_STATUS_BUSY) { + } arc_cln_write_reg_nolock(ARC_CLN_CACHE_STATUS, ARC_CLN_CACHE_STATUS_EN); } diff --git a/arch/archs.yml b/arch/archs.yml index e07d10ffe80..352a296dde2 100644 --- a/arch/archs.yml +++ b/arch/archs.yml @@ -7,8 +7,6 @@ archs: path: arm64 - name: mips path: mips - - name: nios2 - path: nios2 - name: posix path: posix - name: riscv @@ -19,3 +17,5 @@ archs: path: xtensa - name: x86 path: x86 + - name: rx + path: rx diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c index 07c5b32bf32..cab76d32f49 100644 --- a/arch/arm/core/cortex_a_r/cache.c +++ b/arch/arm/core/cortex_a_r/cache.c @@ -63,13 +63,13 @@ void arch_dcache_disable(void) { uint32_t val; + L1C_CleanInvalidateDCacheAll(); + val = __get_SCTLR(); val &= ~SCTLR_C_Msk; barrier_dsync_fence_full(); __set_SCTLR(val); barrier_isync_fence_full(); - - arch_dcache_flush_and_invd_all(); } int arch_dcache_flush_all(void) diff --git a/arch/arm/core/cortex_a_r/fault.c b/arch/arm/core/cortex_a_r/fault.c index eac07cbf9b2..b6916706d6f 100644 --- a/arch/arm/core/cortex_a_r/fault.c +++ b/arch/arm/core/cortex_a_r/fault.c @@ -141,9 +141,9 @@ static uint32_t dump_fault(uint32_t status, uint32_t addr) reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL; LOG_ERR("2nd Level Synchronous External Abort Translation Table @ 0x%08x", addr); break; - case FSR_FS_TLB_CONFLICT_FAULT: - reason = K_ERR_ARM_TLB_CONFLICT_FAULT; - LOG_ERR("Table Conflict Fault @ 0x%08x", addr); + case FSR_FS_TLB_CONFLICT_ABORT: + reason = K_ERR_ARM_TLB_CONFLICT_ABORT; + LOG_ERR("TLB Conflict Abort @ 0x%08x", addr); break; case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL: reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL; diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c index d0e31acb1ed..170a5943f39 100644 --- a/arch/arm/core/cortex_a_r/smp.c +++ b/arch/arm/core/cortex_a_r/smp.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/core/cortex_m/CMakeLists.txt b/arch/arm/core/cortex_m/CMakeLists.txt index 54bca650084..3de8e544bc1 100644 --- a/arch/arm/core/cortex_m/CMakeLists.txt +++ b/arch/arm/core/cortex_m/CMakeLists.txt @@ -2,6 +2,23 @@ zephyr_library() +if(CONFIG_ARMV8_1_M_PACBTI_STANDARD) + zephyr_compile_options(-mbranch-protection=standard) +elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET) + zephyr_compile_options(-mbranch-protection=pac-ret) +elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_LEAF) + zephyr_compile_options(-mbranch-protection=pac-ret+leaf) +elseif(CONFIG_ARMV8_1_M_PACBTI_BTI) + zephyr_compile_options(-mbranch-protection=bti) +elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_BTI) + zephyr_compile_options(-mbranch-protection=pac-ret+bti) +elseif(CONFIG_ARMV8_1_M_PACBTI_PACRET_LEAF_BTI) + zephyr_compile_options(-mbranch-protection=pac-ret+leaf+bti) +elseif(CONFIG_ARMV8_1_M_PACBTI_NONE) + #TODO: Enable this after Zephyr SDK updates to GCC version >=14.2 + # zephyr_compile_options(-mbranch-protection=none) +endif() + zephyr_library_sources( exc_exit.c fault.c diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index c018574429a..eb54301c30c 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -1,6 +1,7 @@ # ARM Cortex-M platform configuration options # Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright 2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 # NOTE: We have the specific core implementations first and outside of the @@ -298,6 +299,60 @@ config ARMV8_1_M_PMU This option is enabled when the CPU implements ARMv8-M Performance Monitoring Unit (PMU). +choice ARMV8_1_M_PACBTI + prompt "Pointer Authentication and Branch Target Identification" + default ARMV8_1_M_PACBTI_NONE + depends on ARMV8_1_M_MAINLINE + +config ARMV8_1_M_PACBTI_STANDARD + bool "Standard (PACRET + LEAF + BTI)" + help + This option instructs the compiler to generate code with all branch protection features + enabled at their standard level. + +config ARMV8_1_M_PACBTI_PACRET + bool "PACRET only" + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory. + +config ARMV8_1_M_PACBTI_PACRET_LEAF + bool "PACRET + Leaf" + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + also sign leaf functions even if they do not write the return address to memory. + +config ARMV8_1_M_PACBTI_BTI + bool "BTI only" + help + This option enables Branch Target Identification (BTI), which inserts special landing + pad instructions at valid indirect branch targets. This option does not enable Pointer + Authentication (PAC). + +config ARMV8_1_M_PACBTI_PACRET_BTI + bool "PACRET + BTI" + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + add landing-pad instructions at the permitted targets of indirect branch instructions + +config ARMV8_1_M_PACBTI_PACRET_LEAF_BTI + bool "PACRET + Leaf + BTI" + help + This option instructs the compiler to generate code with return address signing for + all functions that save the return address to memory and, + also sign leaf functions even if they do not write the return address to memory and, + add landing-pad instructions at the permitted targets of indirect branch instructions + +config ARMV8_1_M_PACBTI_NONE + bool "None" + help + This option instructs the compiler to generate code without branch protection or return + address signing + +endchoice + config ARMV8_M_PMU_EVENTCNT int "Number of event counters in the Performance Monitoring Unit" depends on ARMV8_1_M_PMU diff --git a/arch/arm/core/cortex_m/isr_wrapper.c b/arch/arm/core/cortex_m/isr_wrapper.c index f75963c413f..cb72797e2ec 100644 --- a/arch/arm/core/cortex_m/isr_wrapper.c +++ b/arch/arm/core/cortex_m/isr_wrapper.c @@ -68,9 +68,12 @@ void _isr_wrapper(void) #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) int32_t irq_number = z_soc_irq_get_active(); #else - /* _sw_isr_table does not map the exceptions, only the interrupts. */ int32_t irq_number = __get_IPSR(); #endif + /* _sw_isr_table does not map the core system exceptions, + * which take first 16 interrupt numbers, only the external + * interrupts. + */ irq_number -= 16; struct _isr_table_entry *entry = &_sw_isr_table[irq_number]; diff --git a/arch/arm/core/cortex_m/pm_s2ram.S b/arch/arm/core/cortex_m/pm_s2ram.S index 3e797c749c3..530fc65835e 100644 --- a/arch/arm/core/cortex_m/pm_s2ram.S +++ b/arch/arm/core/cortex_m/pm_s2ram.S @@ -219,13 +219,17 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_resume) push {r0, lr} bl pm_s2ram_mark_check_and_clear cmp r0, #0x1 - pop {r0, lr} beq .L_resume - bx lr + pop {r0, pc} .L_resume: /* - * Restore the CPU context + * Switch to the stack used to execute "arch_pm_s2ram_suspend" + * and restore CPU context backed up by that function, then + * return to the call site of "arch_pm_s2ram_suspend". + * + * Note: the "push {r0, lr}" performed earlier doesn't + * need to be balanced out since we are switching stacks. */ ldr r0, =_cpu_context diff --git a/arch/arm/core/mpu/Kconfig b/arch/arm/core/mpu/Kconfig index ff48692ec65..698b2bb270a 100644 --- a/arch/arm/core/mpu/Kconfig +++ b/arch/arm/core/mpu/Kconfig @@ -71,6 +71,7 @@ config CUSTOM_SECTION_MIN_ALIGN_SIZE config ARM_MPU_PXN bool + default y depends on ARMV8_1_M_MAINLINE help Enable support for Armv8.1-m MPU's Privileged Execute Never (PXN) attr. diff --git a/arch/arm/core/mpu/arm_mpu_v7_internal.h b/arch/arm/core/mpu/arm_mpu_v7_internal.h index 9641ab25000..40d03865d07 100644 --- a/arch/arm/core/mpu/arm_mpu_v7_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v7_internal.h @@ -145,7 +145,7 @@ static inline int get_dyn_region_min_index(void) /* Only a single bit is set for all user accessible permissions. * In ARMv7-M MPU this is bit AP[1]. */ -#define MPU_USER_READ_ACCESSIBLE_Msk (P_RW_U_RO & P_RW_U_RW & P_RO_U_RO & RO) +#define MPU_USER_READ_ACCESSIBLE_Msk (P_RW_U_RO & P_RW_U_RW & P_RO_U_RO) /** * This internal function checks if the region is user accessible or not. diff --git a/arch/arm/include/cortex_m/dwt.h b/arch/arm/include/cortex_m/dwt.h index 947b35dca92..fe946ecb590 100644 --- a/arch/arm/include/cortex_m/dwt.h +++ b/arch/arm/include/cortex_m/dwt.h @@ -32,12 +32,18 @@ extern "C" { /* Define DWT LSR masks which are currently not defined by the CMSIS V5.1.2. * (LSR register is defined but not its bitfields). * Reuse ITM LSR mask as it is the same offset than DWT LSR one. + * TODO: update these to use only CMSIS_6 when all of zephyr and modules have + * update to CMSIS_6. */ #if !defined DWT_LSR_Present_Msk -#define DWT_LSR_Present_Msk ITM_LSR_Present_Msk +#define DWT_LSR_Present_Msk \ + IF_ENABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_Present_Msk)) \ + IF_DISABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_PRESENT_Msk)) #endif #if !defined DWT_LSR_Access_Msk -#define DWT_LSR_Access_Msk ITM_LSR_Access_Msk +#define DWT_LSR_Access_Msk \ + IF_ENABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_Access_Msk)) \ + IF_DISABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_ACCESS_Msk)) #endif static inline void dwt_access(bool ena) diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h index 0800a16436f..cbac2724587 100644 --- a/arch/arm/include/cortex_m/exception.h +++ b/arch/arm/include/cortex_m/exception.h @@ -47,7 +47,7 @@ extern volatile irq_offload_routine_t offload_routine; /* Prefix. Indicates that this is an EXC_RETURN value. * This field reads as 0b11111111. */ -#define EXC_RETURN_INDICATOR_PREFIX (0xFF << 24) +#define EXC_RETURN_INDICATOR_PREFIX (0xFFU << 24) /* bit[0]: Exception Secure. The security domain the exception was taken to. */ #define EXC_RETURN_EXCEPTION_SECURE_Pos 0 #define EXC_RETURN_EXCEPTION_SECURE_Msk BIT(EXC_RETURN_EXCEPTION_SECURE_Pos) diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c index e7480c9de15..cb5f485c0d5 100644 --- a/arch/arm64/core/fatal.c +++ b/arch/arm64/core/fatal.c @@ -207,24 +207,28 @@ static bool is_address_mapped(uint64_t *addr) { uintptr_t *phys = NULL; - if (*addr == 0U) + if (*addr == 0U) { return false; + } /* Check alignment. */ - if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) + if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) { return false; + } return !arch_page_phys_get((void *) addr, phys); } static bool is_valid_jump_address(uint64_t *addr) { - if (*addr == 0U) + if (*addr == 0U) { return false; + } /* Check alignment. */ - if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) + if ((*addr & (sizeof(uint32_t) - 1U)) != 0U) { return false; + } return ((*addr >= (uint64_t)__text_region_start) && (*addr <= (uint64_t)(__text_region_end))); @@ -266,8 +270,9 @@ static void walk_stackframe(arm64_stacktrace_cb cb, void *cookie, const struct a if (!is_address_mapped(fp)) break; lr = fp[1]; - if (!is_valid_jump_address(&lr)) + if (!is_valid_jump_address(&lr)) { break; + } if (!cb(cookie, lr, fp)) { break; } diff --git a/arch/arm64/core/switch.S b/arch/arm64/core/switch.S index 333b8f0b21e..06a95d37b7a 100644 --- a/arch/arm64/core/switch.S +++ b/arch/arm64/core/switch.S @@ -74,6 +74,13 @@ SECTION_FUNC(TEXT, z_arm64_context_switch) ldp x0, x1, [sp], #16 #endif +#ifdef CONFIG_SMP + /* Write barrier: ensure all preceding writes are executed + * before writing the switch handle + */ + dmb sy +#endif + /* save old thread into switch handle which is required by * z_sched_switch_spin() */ diff --git a/arch/nios2/CMakeLists.txt b/arch/nios2/CMakeLists.txt deleted file mode 100644 index f0424b169b6..00000000000 --- a/arch/nios2/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_GP_NONE) -set(gpopt none) -elseif(CONFIG_GP_LOCAL) -set(gpopt local) -elseif(CONFIG_GP_GLOBAL) -set(gpopt global) -elseif(CONFIG_GP_ALL_DATA) -set(gpopt data) -endif() - -# Set Global Pointer option based on Kconfig. -zephyr_cc_option(-mgpopt=${gpopt}) - -# TODO Find a way to pull this out of system.h somehow -# instead of having Kconfig for it - -if(CONFIG_HAS_MUL_INSTRUCTION) -zephyr_cc_option(-mhw-mul) -else() -zephyr_cc_option(-mno-hw-mul) -endif() - -if(CONFIG_HAS_MULX_INSTRUCTION) -zephyr_cc_option(-mhw-mulx) -else() -zephyr_cc_option(-mno-hw-mulx) -endif() - -if(CONFIG_HAS_DIV_INSTRUCTION) -zephyr_cc_option(-mhw-div) -else() -zephyr_cc_option(-mno-hw-div) -endif() - -add_subdirectory(core) diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig deleted file mode 100644 index 6e147119421..00000000000 --- a/arch/nios2/Kconfig +++ /dev/null @@ -1,96 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -menu "Nios II Options" - depends on NIOS2 - -config ARCH - string - default "nios2" - -menu "Nios II Gen 2 Processor Options" - -config CPU_NIOS2_GEN2 - bool - default y - select BUILD_OUTPUT_HEX - select ARCH_HAS_EXTRA_EXCEPTION_INFO - help - This option signifies the use of a Nios II Gen 2 CPU - -endmenu - -menu "Nios II Family Options" - -config GEN_ISR_TABLES - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config NUM_IRQS - int - default 32 - -config HAS_MUL_INSTRUCTION - bool - -config HAS_DIV_INSTRUCTION - bool - -config HAS_MULX_INSTRUCTION - bool - -config INCLUDE_RESET_VECTOR - bool "Include Reset vector" - default y - help - Include the reset vector stub, which enables instruction/data caches - and then jumps to __start. This code is typically located at the very - beginning of flash memory. You may need to omit this if using the - nios2-download tool since it refuses to load data anywhere other than - RAM. - -config EXTRA_EXCEPTION_INFO - bool "Extra exception debug information" - help - Have exceptions print additional useful debugging information in - human-readable form, at the expense of code size. For example, - the cause code for an exception will be supplemented by a string - describing what that cause code means. - -choice - prompt "Global Pointer options" - default GP_GLOBAL - -config GP_NONE - bool "No global pointer" - help - Do not use global pointer relative offsets at all - -config GP_LOCAL - bool "Local data global pointer references" - help - Use global pointer relative offsets for small globals declared in the - same C file as the code that uses it. - -config GP_GLOBAL - bool "Global data global pointer references" - help - Use global pointer relative offsets for small globals declared - anywhere in the executable. Note that if any small globals that are put - in alternate sections they must be declared - in headers with proper __attribute__((section)) or the linker will - error out. - -config GP_ALL_DATA - bool "All data global pointer references" - help - Use GP relative access for all data in the program, not just - small data. Use this if your board has 64K or less of RAM. - -endchoice - -endmenu - -endmenu diff --git a/arch/nios2/core/CMakeLists.txt b/arch/nios2/core/CMakeLists.txt deleted file mode 100644 index 84fa0b49b3f..00000000000 --- a/arch/nios2/core/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources( - thread.c - cpu_idle.c - fatal.c - irq_manage.c - swap.S - prep_c.c - reset.S - cache.c - exception.S - crt0.S - ) - -zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) -zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c) diff --git a/arch/nios2/core/cache.c b/arch/nios2/core/cache.c deleted file mode 100644 index c13c43c7188..00000000000 --- a/arch/nios2/core/cache.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - - -/** - * Flush the entire instruction cache and pipeline. - * - * You will need to call this function if the application writes new program - * text to memory, such as a boot copier or runtime synthesis of code. If the - * new text was written with instructions that do not bypass cache memories, - * this should immediately be followed by an invocation of - * z_nios2_dcache_flush_all() so that cached instruction data is committed to - * RAM. - * - * See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more - * information on cache considerations. - */ -#if ALT_CPU_ICACHE_SIZE > 0 -void z_nios2_icache_flush_all(void) -{ - uint32_t i; - - for (i = 0U; i < ALT_CPU_ICACHE_SIZE; i += ALT_CPU_ICACHE_LINE_SIZE) { - z_nios2_icache_flush(i); - } - - /* Get rid of any stale instructions in the pipeline */ - z_nios2_pipeline_flush(); -} -#endif - -/** - * Flush the entire data cache. - * - * This will be typically needed after writing new program text to memory - * after flushing the instruction cache. - * - * The Nios II does not support hardware cache coherency for multi-master - * or multi-processor systems and software coherency must be implemented - * when communicating with shared memory. If support for this is introduced - * in Zephyr additional APIs for flushing ranges of the data cache will need - * to be implemented. - * - * See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more - * information on cache considerations. - */ -#if ALT_CPU_DCACHE_SIZE > 0 -void z_nios2_dcache_flush_all(void) -{ - uint32_t i; - - for (i = 0U; i < ALT_CPU_DCACHE_SIZE; i += ALT_CPU_DCACHE_LINE_SIZE) { - z_nios2_dcache_flush(i); - } -} -#endif - -/* - * z_nios2_dcache_flush_no_writeback() is called to flush the data cache for a - * memory region of length "len" bytes, starting at address "start". - * - * Any dirty lines in the data cache are NOT written back to memory. - * Make sure you really want this behavior. If you aren't 100% sure, - * use the z_nios2_dcache_flush() routine instead. - */ -#if ALT_CPU_DCACHE_SIZE > 0 -void z_nios2_dcache_flush_no_writeback(void *start, uint32_t len) -{ - uint8_t *i; - uint8_t *end = ((char *) start) + len; - - for (i = start; i < end; i += ALT_CPU_DCACHE_LINE_SIZE) { - __asm__ volatile ("initda (%0)" :: "r" (i)); - } - - /* - * For an unaligned flush request, we've got one more line left. - * Note that this is dependent on ALT_CPU_DCACHE_LINE_SIZE to be a - * multiple of 2 (which it always is). - */ - - if (((uint32_t) start) & (ALT_CPU_DCACHE_LINE_SIZE - 1)) { - __asm__ volatile ("initda (%0)" :: "r" (i)); - } -} -#endif diff --git a/arch/nios2/core/cpu_idle.c b/arch/nios2/core/cpu_idle.c deleted file mode 100644 index b201ecfa84e..00000000000 --- a/arch/nios2/core/cpu_idle.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE -void arch_cpu_idle(void) -{ - /* Do nothing but unconditionally unlock interrupts and return to the - * caller. This CPU does not have any kind of power saving instruction. - */ - irq_unlock(NIOS2_STATUS_PIE_MSK); -} -#endif - -#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE -void arch_cpu_atomic_idle(unsigned int key) -{ - /* Do nothing but restore IRQ state. This CPU does not have any - * kind of power saving instruction. - */ - irq_unlock(key); -} -#endif diff --git a/arch/nios2/core/crt0.S b/arch/nios2/core/crt0.S deleted file mode 100644 index 2f708bf26f4..00000000000 --- a/arch/nios2/core/crt0.S +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/* exports */ -GTEXT(__start) -GTEXT(__reset) - -/* imports */ -GTEXT(z_prep_c) -GTEXT(z_interrupt_stacks) - - /* Allow use of r1/at (the assembler temporary register) in this - * code, normally reserved for internal assembler use - */ - .set noat - - -#if CONFIG_INCLUDE_RESET_VECTOR -/* - * Reset vector entry point into the system. Placed into special 'reset' - * section so that the linker puts this at ALT_CPU_RESET_ADDR defined in - * system.h - * - * This code can be at most 0x20 bytes, since the exception vector for Nios II - * is usually configured to be 0x20 past the reset vector. - */ -SECTION_FUNC(reset, __reset) - -#if ALT_CPU_ICACHE_SIZE > 0 - /* Aside from the instruction cache line associated with the reset - * vector, the contents of the cache memories are indeterminate after - * reset. To ensure cache coherency after reset, the reset handler - * located at the reset vector must immediately initialize the - * instruction cache. Next, either the reset handler or a subsequent - * routine should proceed to initialize the data cache. - * - * The cache memory sizes are *always* a power of 2. - */ -#if ALT_CPU_ICACHE_SIZE > 0x8000 - movhi r2, %hi(ALT_CPU_ICACHE_SIZE) -#else - movui r2, ALT_CPU_ICACHE_SIZE -#endif -0: - /* If ECC present, need to execute initd for each word address - * to ensure ECC parity bits in data RAM get initialized - */ -#ifdef ALT_CPU_ECC_PRESENT - subi r2, r2, 4 -#else - subi r2, r2, ALT_CPU_ICACHE_LINE_SIZE -#endif - initi r2 - bgt r2, zero, 0b -#endif /* ALT_CPU_ICACHE_SIZE > 0 */ - - /* Done all we need to do here, jump to __text_start */ - movhi r1, %hi(__start) - ori r1, r1, %lo(__start) - jmp r1 -#endif /* CONFIG_INCLUDE_RESET_VECTOR */ - -/* Remainder of asm-land initialization code before we can jump into - * the C domain - */ -SECTION_FUNC(TEXT, __start) - - /* TODO if shadow register sets enabled, ensure we are in set 0 - * GH-1821 - */ - - /* Initialize the data cache if booting from bare metal. If - * we're not booting from our reset vector, either by a bootloader - * or JTAG, assume caches already initialized. - */ -#if ALT_CPU_DCACHE_SIZE > 0 && defined(CONFIG_INCLUDE_RESET_VECTOR) - /* Per documentation data cache size is always a power of two. */ -#if ALT_CPU_DCACHE_SIZE > 0x8000 - movhi r2, %hi(ALT_CPU_DCACHE_SIZE) -#else - movui r2, ALT_CPU_DCACHE_SIZE -#endif -0: - /* If ECC present, need to execute initd for each word address - * to ensure ECC parity bits in data RAM get initialized - */ -#ifdef ALT_CPU_ECC_PRESENT - subi r2, r2, 4 -#else - subi r2, r2, ALT_CPU_DCACHE_LINE_SIZE -#endif - initd 0(r2) - bgt r2, zero, 0b -#endif /* ALT_CPU_DCACHE_SIZE && defined(CONFIG_INCLUDE_RESET_VECTOR) */ - -#ifdef CONFIG_INIT_STACKS - /* Pre-populate all bytes in z_interrupt_stacks with 0xAA - * init.c enforces that the z_interrupt_stacks pointer - * and CONFIG_ISR_STACK_SIZE are a multiple of ARCH_STACK_PTR_ALIGN (4) - */ - movhi r1, %hi(z_interrupt_stacks) - ori r1, r1, %lo(z_interrupt_stacks) - movhi r2, %hi(CONFIG_ISR_STACK_SIZE) - ori r2, r2, %lo(CONFIG_ISR_STACK_SIZE) - /* Put constant 0xaaaaaaaa in r3 */ - movhi r3, 0xaaaa - ori r3, r3, 0xaaaa -1: - /* Loop through the z_interrupt_stacks treating it as an array of - * uint32_t, setting each element to r3 */ - stw r3, (r1) - subi r2, r2, 4 - addi r1, r1, 4 - blt r0, r2, 1b -#endif - - /* Set up the initial stack pointer to the interrupt stack, safe - * to use this as the CPU boots up with interrupts disabled and we - * don't turn them on until much later, when the kernel is on - * the main stack */ - movhi sp, %hi(z_interrupt_stacks) - ori sp, sp, %lo(z_interrupt_stacks) - addi sp, sp, CONFIG_ISR_STACK_SIZE - -#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL) || \ - defined(CONFIG_GP_ALL_DATA) - /* Initialize global pointer with the linker variable we set */ - movhi gp, %hi(_gp) - ori gp, gp, %lo(_gp) -#endif - - /* TODO if shadow register sets enabled, interate through them to set - * up. Need to clear r0, write gp, set the exception stack pointer - * GH-1821 - */ - - /* Jump into C domain. z_prep_c zeroes BSS, copies rw data into RAM, - * and then enters z_cstart */ - call z_prep_c - diff --git a/arch/nios2/core/exception.S b/arch/nios2/core/exception.S deleted file mode 100644 index 8dd7e0b9b9b..00000000000 --- a/arch/nios2/core/exception.S +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -/* exports */ -GTEXT(_exception) - -/* import */ -GTEXT(z_nios2_fault) -GTEXT(arch_swap) -#ifdef CONFIG_IRQ_OFFLOAD -GTEXT(z_irq_do_offload) -GTEXT(_offload_routine) -#endif - -/* Allows use of r1/at register, otherwise reserved for assembler use */ -.set noat - -/* Placed into special 'exception' section so that the linker can put this code - * at ALT_CPU_EXCEPTION_ADDR defined in system.h - * - * This is the common entry point for processor exceptions and interrupts from - * the Internal Interrupt Controller (IIC). - * - * If the External (EIC) controller is in use, then we will never get here on - * behalf of an interrupt, instead the EIC driver will have set up a vector - * table and the processor will jump directly into the appropriate table - * entry. - */ -SECTION_FUNC(exception.entry, _exception) - /* Reserve thread stack space for saving context */ - subi sp, sp, __struct_arch_esf_SIZEOF - - /* Preserve all caller-saved registers onto the thread's stack */ - stw ra, __struct_arch_esf_ra_OFFSET(sp) - stw r1, __struct_arch_esf_r1_OFFSET(sp) - stw r2, __struct_arch_esf_r2_OFFSET(sp) - stw r3, __struct_arch_esf_r3_OFFSET(sp) - stw r4, __struct_arch_esf_r4_OFFSET(sp) - stw r5, __struct_arch_esf_r5_OFFSET(sp) - stw r6, __struct_arch_esf_r6_OFFSET(sp) - stw r7, __struct_arch_esf_r7_OFFSET(sp) - stw r8, __struct_arch_esf_r8_OFFSET(sp) - stw r9, __struct_arch_esf_r9_OFFSET(sp) - stw r10, __struct_arch_esf_r10_OFFSET(sp) - stw r11, __struct_arch_esf_r11_OFFSET(sp) - stw r12, __struct_arch_esf_r12_OFFSET(sp) - stw r13, __struct_arch_esf_r13_OFFSET(sp) - stw r14, __struct_arch_esf_r14_OFFSET(sp) - stw r15, __struct_arch_esf_r15_OFFSET(sp) - - /* Store value of estatus control register */ - rdctl et, estatus - stw et, __struct_arch_esf_estatus_OFFSET(sp) - - /* ea-4 is the address of the instruction when the exception happened, - * put this in the stack frame as well - */ - addi r15, ea, -4 - stw r15, __struct_arch_esf_instr_OFFSET(sp) - - /* Figure out whether we are here because of an interrupt or an - * exception. If an interrupt, switch stacks and enter IRQ handling - * code. If an exception, remain on current stack and enter exception - * handing code. From the CPU manual, ipending must be nonzero and - * estatis.PIE must be enabled for this to be considered an interrupt. - * - * Stick ipending in r4 since it will be an arg for _enter_irq - */ - rdctl r4, ipending - beq r4, zero, not_interrupt - /* We stashed estatus in et earlier */ - andi r15, et, 1 - beq r15, zero, not_interrupt - -is_interrupt: - /* If we get here, this is an interrupt */ - - /* Grab a reference to _kernel in r10 so we can determine the - * current irq stack pointer - */ - movhi r10, %hi(_kernel) - ori r10, r10, %lo(_kernel) - - /* Stash a copy of thread's sp in r12 so that we can put it on the IRQ - * stack - */ - mov r12, sp - - /* Switch to interrupt stack */ - ldw sp, _kernel_offset_to_irq_stack(r10) - - /* Store thread stack pointer onto IRQ stack */ - addi sp, sp, -4 - stw r12, 0(sp) - -on_irq_stack: - - /* Enter C interrupt handling code. Value of ipending will be the - * function parameter since we put it in r4 - */ - call _enter_irq - - /* Interrupt handler finished and the interrupt should be serviced - * now, the appropriate bits in ipending should be cleared */ - - /* Get a reference to _kernel again in r10 */ - movhi r10, %hi(_kernel) - ori r10, r10, %lo(_kernel) - -#ifdef CONFIG_PREEMPT_ENABLED - ldw r11, _kernel_offset_to_current(r10) - /* Determine whether the exception of the ISR requires context - * switch - */ - - /* Call into the kernel to see if a scheduling decision is necessary */ - ldw r2, _kernel_offset_to_ready_q_cache(r10) - beq r2, r11, no_reschedule - - /* - * A context reschedule is required: keep the volatile registers of - * the interrupted thread on the context's stack. Utilize - * the existing arch_swap() primitive to save the remaining - * thread's registers (including floating point) and perform - * a switch to the new thread. - */ - - /* We put the thread stack pointer on top of the IRQ stack before - * we switched stacks. Restore it to go back to thread stack - */ - ldw sp, 0(sp) - - /* Argument to Swap() is estatus since that's the state of the - * status register before the exception happened. When coming - * out of the context switch we need this info to restore - * IRQ lock state. We put this value in et earlier. - */ - mov r4, et - - call arch_swap - jmpi _exception_exit -#else - jmpi no_reschedule -#endif /* CONFIG_PREEMPT_ENABLED */ - -not_interrupt: - - /* Since this wasn't an interrupt we're not going to restart the - * faulting instruction. - * - * We earlier put ea - 4 in the stack frame, replace it with just ea - */ - stw ea, __struct_arch_esf_instr_OFFSET(sp) - -#ifdef CONFIG_IRQ_OFFLOAD - /* Check the contents of _offload_routine. If non-NULL, jump into - * the interrupt code anyway. - */ - movhi r10, %hi(_offload_routine) - ori r10, r10, %lo(_offload_routine) - ldw r11, (r10) - bne r11, zero, is_interrupt -#endif - -_exception_enter_fault: - /* If we get here, the exception wasn't in interrupt or an - * invocation of irq_offload(). Let z_nios2_fault() handle it in - * C domain - */ - - mov r4, sp - call z_nios2_fault - jmpi _exception_exit - -no_reschedule: - - /* We put the thread stack pointer on top of the IRQ stack before - * we switched stacks. Restore it to go back to thread stack - */ - ldw sp, 0(sp) - - /* Fall through */ - -_exception_exit: - /* We are on the thread stack. Restore all saved registers - * and return to the interrupted context */ - - /* Return address from the exception */ - ldw ea, __struct_arch_esf_instr_OFFSET(sp) - - /* Restore estatus - * XXX is this right??? */ - ldw r5, __struct_arch_esf_estatus_OFFSET(sp) - wrctl estatus, r5 - - /* Restore caller-saved registers */ - ldw ra, __struct_arch_esf_ra_OFFSET(sp) - ldw r1, __struct_arch_esf_r1_OFFSET(sp) - ldw r2, __struct_arch_esf_r2_OFFSET(sp) - ldw r3, __struct_arch_esf_r3_OFFSET(sp) - ldw r4, __struct_arch_esf_r4_OFFSET(sp) - ldw r5, __struct_arch_esf_r5_OFFSET(sp) - ldw r6, __struct_arch_esf_r6_OFFSET(sp) - ldw r7, __struct_arch_esf_r7_OFFSET(sp) - ldw r8, __struct_arch_esf_r8_OFFSET(sp) - ldw r9, __struct_arch_esf_r9_OFFSET(sp) - ldw r10, __struct_arch_esf_r10_OFFSET(sp) - ldw r11, __struct_arch_esf_r11_OFFSET(sp) - ldw r12, __struct_arch_esf_r12_OFFSET(sp) - ldw r13, __struct_arch_esf_r13_OFFSET(sp) - ldw r14, __struct_arch_esf_r14_OFFSET(sp) - ldw r15, __struct_arch_esf_r15_OFFSET(sp) - - /* Put the stack pointer back where it was when we entered - * exception state - */ - addi sp, sp, __struct_arch_esf_SIZEOF - - /* All done, copy estatus into status and transfer to ea */ - eret diff --git a/arch/nios2/core/fatal.c b/arch/nios2/core/fatal.c deleted file mode 100644 index 3f34c1e8fc7..00000000000 --- a/arch/nios2/core/fatal.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); - -FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, - const struct arch_esf *esf) -{ -#if CONFIG_EXCEPTION_DEBUG - if (esf != NULL) { - /* Subtract 4 from EA since we added 4 earlier so that the - * faulting instruction isn't retried. - * - * TODO: Only caller-saved registers get saved upon exception - * entry. We may want to introduce a config option to save and - * dump all registers, at the expense of some stack space. - */ - LOG_ERR("Faulting instruction: 0x%08x", esf->instr - 4); - LOG_ERR(" r1: 0x%08x r2: 0x%08x r3: 0x%08x r4: 0x%08x", - esf->r1, esf->r2, esf->r3, esf->r4); - LOG_ERR(" r5: 0x%08x r6: 0x%08x r7: 0x%08x r8: 0x%08x", - esf->r5, esf->r6, esf->r7, esf->r8); - LOG_ERR(" r9: 0x%08x r10: 0x%08x r11: 0x%08x r12: 0x%08x", - esf->r9, esf->r10, esf->r11, esf->r12); - LOG_ERR(" r13: 0x%08x r14: 0x%08x r15: 0x%08x ra: 0x%08x", - esf->r13, esf->r14, esf->r15, esf->ra); - LOG_ERR("estatus: %08x", esf->estatus); - } -#endif /* CONFIG_EXCEPTION_DEBUG */ - - z_fatal_error(reason, esf); - CODE_UNREACHABLE; -} - -#if defined(CONFIG_EXTRA_EXCEPTION_INFO) && \ - (defined(CONFIG_PRINTK) || defined(CONFIG_LOG)) \ - && defined(ALT_CPU_HAS_EXTRA_EXCEPTION_INFO) -static char *cause_str(uint32_t cause_code) -{ - switch (cause_code) { - case 0: - return "reset"; - case 1: - return "processor-only reset request"; - case 2: - return "interrupt"; - case 3: - return "trap"; - case 4: - return "unimplemented instruction"; - case 5: - return "illegal instruction"; - case 6: - return "misaligned data address"; - case 7: - return "misaligned destination address"; - case 8: - return "division error"; - case 9: - return "supervisor-only instruction address"; - case 10: - return "supervisor-only instruction"; - case 11: - return "supervisor-only data address"; - case 12: - return "TLB miss"; - case 13: - return "TLB permission violation (execute)"; - case 14: - return "TLB permission violation (read)"; - case 15: - return "TLB permission violation (write)"; - case 16: - return "MPU region violation (instruction)"; - case 17: - return "MPU region violation (data)"; - case 18: - return "ECC TLB error"; - case 19: - return "ECC fetch error (instruction)"; - case 20: - return "ECC register file error"; - case 21: - return "ECC data error"; - case 22: - return "ECC data cache writeback error"; - case 23: - return "bus instruction fetch error"; - case 24: - return "bus data region violation"; - default: - return "unknown"; - } -} -#endif - -FUNC_NORETURN void z_nios2_fault(const struct arch_esf *esf) -{ -#if defined(CONFIG_PRINTK) || defined(CONFIG_LOG) - /* Unfortunately, completely unavailable on Nios II/e cores */ -#ifdef ALT_CPU_HAS_EXTRA_EXCEPTION_INFO - uint32_t exc_reg, badaddr_reg, eccftl; - enum nios2_exception_cause cause; - - exc_reg = z_nios2_creg_read(NIOS2_CR_EXCEPTION); - - /* Bit 31 indicates potentially fatal ECC error */ - eccftl = (exc_reg & NIOS2_EXCEPTION_REG_ECCFTL_MASK) != 0U; - - /* Bits 2-6 contain the cause code */ - cause = (exc_reg & NIOS2_EXCEPTION_REG_CAUSE_MASK) - >> NIOS2_EXCEPTION_REG_CAUSE_OFST; - - LOG_ERR("Exception cause: %d ECCFTL: 0x%x", cause, eccftl); -#if CONFIG_EXTRA_EXCEPTION_INFO - LOG_ERR("reason: %s", cause_str(cause)); -#endif - if (BIT(cause) & NIOS2_BADADDR_CAUSE_MASK) { - badaddr_reg = z_nios2_creg_read(NIOS2_CR_BADADDR); - LOG_ERR("Badaddr: 0x%x", badaddr_reg); - } -#endif /* ALT_CPU_HAS_EXTRA_EXCEPTION_INFO */ -#endif /* CONFIG_PRINTK || CONFIG_LOG */ - - z_nios2_fatal_error(K_ERR_CPU_EXCEPTION, esf); -} - -#ifdef ALT_CPU_HAS_DEBUG_STUB -FUNC_NORETURN void arch_system_halt(unsigned int reason) -{ - ARG_UNUSED(reason); - - z_nios2_break(); - CODE_UNREACHABLE; -} -#endif diff --git a/arch/nios2/core/irq_manage.c b/arch/nios2/core/irq_manage.c deleted file mode 100644 index 6f4b2bdf10c..00000000000 --- a/arch/nios2/core/irq_manage.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Nios II C-domain interrupt management code for use with Internal - * Interrupt Controller (IIC) - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); - -FUNC_NORETURN void z_irq_spurious(const void *unused) -{ - ARG_UNUSED(unused); - LOG_ERR("Spurious interrupt detected! ipending: %x", - z_nios2_creg_read(NIOS2_CR_IPENDING)); - z_nios2_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); -} - - -void arch_irq_enable(unsigned int irq) -{ - uint32_t ienable; - unsigned int key; - - key = irq_lock(); - - ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); - ienable |= BIT(irq); - z_nios2_creg_write(NIOS2_CR_IENABLE, ienable); - - irq_unlock(key); -}; - - - -void arch_irq_disable(unsigned int irq) -{ - uint32_t ienable; - unsigned int key; - - key = irq_lock(); - - ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); - ienable &= ~BIT(irq); - z_nios2_creg_write(NIOS2_CR_IENABLE, ienable); - - irq_unlock(key); -}; - -int arch_irq_is_enabled(unsigned int irq) -{ - uint32_t ienable; - - ienable = z_nios2_creg_read(NIOS2_CR_IENABLE); - return ienable & BIT(irq); -} - -/** - * @brief Interrupt demux function - * - * Given a bitfield of pending interrupts, execute the appropriate handler - * - * @param ipending Bitfield of interrupts - */ -void _enter_irq(uint32_t ipending) -{ - int index; - - _kernel.cpus[0].nested++; - -#ifdef CONFIG_IRQ_OFFLOAD - z_irq_do_offload(); -#endif - - while (ipending) { - struct _isr_table_entry *ite; - -#ifdef CONFIG_TRACING_ISR - sys_trace_isr_enter(); -#endif - - index = find_lsb_set(ipending) - 1; - ipending &= ~BIT(index); - - ite = &_sw_isr_table[index]; - - ite->isr(ite->arg); -#ifdef CONFIG_TRACING_ISR - sys_trace_isr_exit(); -#endif - } - - _kernel.cpus[0].nested--; -#ifdef CONFIG_STACK_SENTINEL - z_check_stack_sentinel(); -#endif -} - -#ifdef CONFIG_DYNAMIC_INTERRUPTS -int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(const void *parameter), - const void *parameter, uint32_t flags) -{ - ARG_UNUSED(flags); - ARG_UNUSED(priority); - - z_isr_install(irq, routine, parameter); - return irq; -} -#endif /* CONFIG_DYNAMIC_INTERRUPTS */ diff --git a/arch/nios2/core/irq_offload.c b/arch/nios2/core/irq_offload.c deleted file mode 100644 index 0c918896be9..00000000000 --- a/arch/nios2/core/irq_offload.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -volatile irq_offload_routine_t _offload_routine; -static volatile const void *offload_param; - -/* Called by _enter_irq if it was passed 0 for ipending. - * Just in case the offload routine itself generates an unhandled - * exception, clear the offload_routine global before executing. - */ -void z_irq_do_offload(void) -{ - irq_offload_routine_t tmp; - - if (!_offload_routine) { - return; - } - - tmp = _offload_routine; - _offload_routine = NULL; - - tmp((const void *)offload_param); -} - -void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) -{ - unsigned int key; - - key = irq_lock(); - _offload_routine = routine; - offload_param = parameter; - - __asm__ volatile ("trap"); - - irq_unlock(key); -} - -void arch_irq_offload_init(void) -{ -} diff --git a/arch/nios2/core/offsets/offsets.c b/arch/nios2/core/offsets/offsets.c deleted file mode 100644 index 9d381d87446..00000000000 --- a/arch/nios2/core/offsets/offsets.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Nios II kernel structure member offset definition file - * - * This module is responsible for the generation of the absolute symbols whose - * value represents the member offsets for various Nios II kernel - * structures. - * - * All of the absolute symbols defined by this module will be present in the - * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms - * symbol). - * - * INTERNAL - * It is NOT necessary to define the offset for every member of a structure. - * Typically, only those members that are accessed by assembly language routines - * are defined; however, it doesn't hurt to define all fields for the sake of - * completeness. - */ - - -#include -#include -#include -#include - -/* struct coop member offsets */ -GEN_OFFSET_SYM(_callee_saved_t, r16); -GEN_OFFSET_SYM(_callee_saved_t, r17); -GEN_OFFSET_SYM(_callee_saved_t, r18); -GEN_OFFSET_SYM(_callee_saved_t, r19); -GEN_OFFSET_SYM(_callee_saved_t, r20); -GEN_OFFSET_SYM(_callee_saved_t, r21); -GEN_OFFSET_SYM(_callee_saved_t, r22); -GEN_OFFSET_SYM(_callee_saved_t, r23); -GEN_OFFSET_SYM(_callee_saved_t, r28); -GEN_OFFSET_SYM(_callee_saved_t, ra); -GEN_OFFSET_SYM(_callee_saved_t, sp); -GEN_OFFSET_SYM(_callee_saved_t, key); -GEN_OFFSET_SYM(_callee_saved_t, retval); - -GEN_OFFSET_STRUCT(arch_esf, ra); -GEN_OFFSET_STRUCT(arch_esf, r1); -GEN_OFFSET_STRUCT(arch_esf, r2); -GEN_OFFSET_STRUCT(arch_esf, r3); -GEN_OFFSET_STRUCT(arch_esf, r4); -GEN_OFFSET_STRUCT(arch_esf, r5); -GEN_OFFSET_STRUCT(arch_esf, r6); -GEN_OFFSET_STRUCT(arch_esf, r7); -GEN_OFFSET_STRUCT(arch_esf, r8); -GEN_OFFSET_STRUCT(arch_esf, r9); -GEN_OFFSET_STRUCT(arch_esf, r10); -GEN_OFFSET_STRUCT(arch_esf, r11); -GEN_OFFSET_STRUCT(arch_esf, r12); -GEN_OFFSET_STRUCT(arch_esf, r13); -GEN_OFFSET_STRUCT(arch_esf, r14); -GEN_OFFSET_STRUCT(arch_esf, r15); -GEN_OFFSET_STRUCT(arch_esf, estatus); -GEN_OFFSET_STRUCT(arch_esf, instr); -GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, sizeof(struct arch_esf)); - -GEN_ABS_SYM_END diff --git a/arch/nios2/core/prep_c.c b/arch/nios2/core/prep_c.c deleted file mode 100644 index c5996205956..00000000000 --- a/arch/nios2/core/prep_c.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2014 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Full C support initialization - * - * - * Initialization of full C support: zero the .bss, copy the .data if XIP, - * call z_cstart(). - * - * Stack is available in this module, but not the global data/bss until their - * initialization is performed. - */ - -#include -#include -#include -#include -#include -#include -#include - -/** - * @brief Prepare to and run C code - * - * This routine prepares for the execution of and runs C code. - */ - -void z_prep_c(void) -{ -#if defined(CONFIG_SOC_PREP_HOOK) - soc_prep_hook(); -#endif - - z_bss_zero(); - z_data_copy(); - /* In most XIP scenarios we copy the exception code into RAM, so need - * to flush instruction cache. - */ -#ifdef CONFIG_XIP - z_nios2_icache_flush_all(); -#if ALT_CPU_ICACHE_SIZE > 0 - /* Only need to flush the data cache here if there actually is an - * instruction cache, so that the cached instruction data written is - * actually committed. - */ - z_nios2_dcache_flush_all(); -#endif -#endif -#if CONFIG_ARCH_CACHE - arch_cache_init(); -#endif - z_cstart(); - CODE_UNREACHABLE; -} diff --git a/arch/nios2/core/reset.S b/arch/nios2/core/reset.S deleted file mode 100644 index 6ec3ff3044d..00000000000 --- a/arch/nios2/core/reset.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -GTEXT(__start) - diff --git a/arch/nios2/core/swap.S b/arch/nios2/core/swap.S deleted file mode 100644 index fa1cd597bc4..00000000000 --- a/arch/nios2/core/swap.S +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -/* exports */ -GTEXT(arch_swap) -GTEXT(z_thread_entry_wrapper) - -/* imports */ -GTEXT(_k_neg_eagain) - -/* unsigned int arch_swap(unsigned int key) - * - * Always called with interrupts locked - */ -SECTION_FUNC(exception.other, arch_swap) - -#if defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) - /* Need to preserve r4 as it has the function argument. */ - addi sp, sp, -12 - stw ra, 8(sp) - stw fp, 4(sp) - stw r4, 0(sp) - - call z_thread_mark_switched_out - - ldw r4, 0(sp) - ldw fp, 4(sp) - ldw ra, 8(sp) - addi sp, sp, 12 -#endif - - /* Get a reference to _kernel in r10 */ - movhi r10, %hi(_kernel) - ori r10, r10, %lo(_kernel) - - /* Get the pointer to kernel->current */ - ldw r11, _kernel_offset_to_current(r10) - - /* Store all the callee saved registers. We either got here via - * an exception or from a cooperative invocation of arch_swap() from C - * domain, so all the caller-saved registers have already been - * saved by the exception asm or the calling C code already. - */ - stw r16, _thread_offset_to_r16(r11) - stw r17, _thread_offset_to_r17(r11) - stw r18, _thread_offset_to_r18(r11) - stw r19, _thread_offset_to_r19(r11) - stw r20, _thread_offset_to_r20(r11) - stw r21, _thread_offset_to_r21(r11) - stw r22, _thread_offset_to_r22(r11) - stw r23, _thread_offset_to_r23(r11) - stw r28, _thread_offset_to_r28(r11) - stw ra, _thread_offset_to_ra(r11) - stw sp, _thread_offset_to_sp(r11) - - /* r4 has the 'key' argument which is the result of irq_lock() - * before this was called - */ - stw r4, _thread_offset_to_key(r11) - - /* Populate default return value */ - movhi r5, %hi(_k_neg_eagain) - ori r5, r5, %lo(_k_neg_eagain) - ldw r4, (r5) - stw r4, _thread_offset_to_retval(r11) - - /* get cached thread to run */ - ldw r2, _kernel_offset_to_ready_q_cache(r10) - - /* At this point r2 points to the next thread to be swapped in */ - - /* the thread to be swapped in is now the current thread */ - stw r2, _kernel_offset_to_current(r10) - - /* Restore callee-saved registers and switch to the incoming - * thread's stack - */ - ldw r16, _thread_offset_to_r16(r2) - ldw r17, _thread_offset_to_r17(r2) - ldw r18, _thread_offset_to_r18(r2) - ldw r19, _thread_offset_to_r19(r2) - ldw r20, _thread_offset_to_r20(r2) - ldw r21, _thread_offset_to_r21(r2) - ldw r22, _thread_offset_to_r22(r2) - ldw r23, _thread_offset_to_r23(r2) - ldw r28, _thread_offset_to_r28(r2) - ldw ra, _thread_offset_to_ra(r2) - ldw sp, _thread_offset_to_sp(r2) - - /* We need to irq_unlock(current->coopReg.key); - * key was supplied as argument to arch_swap(). Fetch it. - */ - ldw r3, _thread_offset_to_key(r2) - - /* - * Load return value into r2 (return value register). -EAGAIN unless - * someone previously called arch_thread_return_value_set(). Do this - * before we potentially unlock interrupts. - */ - ldw r2, _thread_offset_to_retval(r2) - - /* Now do irq_unlock(current->coopReg.key) */ -#if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \ - (defined ALT_CPU_EIC_PRESENT) || \ - (defined ALT_CPU_MMU_PRESENT) || \ - (defined ALT_CPU_MPU_PRESENT) - andi r3, r3, NIOS2_STATUS_PIE_MSK - beq r3, zero, no_unlock - rdctl r3, status - ori r3, r3, NIOS2_STATUS_PIE_MSK - wrctl status, r3 - -no_unlock: -#else - wrctl status, r3 -#endif - -#if defined(CONFIG_INSTRUMENT_THREAD_SWITCHING) - /* Also need to preserve r2, r3 as return values */ - addi sp, sp, -20 - stw ra, 16(sp) - stw fp, 12(sp) - stw r4, 8(sp) - stw r3, 4(sp) - stw r2, 0(sp) - - call z_thread_mark_switched_in - - ldw r2, 0(sp) - ldw r3, 4(sp) - ldw r4, 8(sp) - ldw fp, 12(sp) - ldw ra, 16(sp) - addi sp, sp, 20 -#endif - ret - - -/* void z_thread_entry_wrapper(void) - */ -SECTION_FUNC(TEXT, z_thread_entry_wrapper) - /* This all corresponds to struct init_stack_frame defined in - * thread.c. We need to take this stuff off the stack and put - * it in the appropriate registers - */ - - /* Can't return from here, just put NULL in ra */ - movi ra, 0 - - /* Calling convention has first 4 arguments in registers r4-r7. */ - ldw r4, 0(sp) - ldw r5, 4(sp) - ldw r6, 8(sp) - ldw r7, 12(sp) - - /* pop all the stuff that we just loaded into registers */ - addi sp, sp, 16 - - call z_thread_entry - diff --git a/arch/nios2/core/thread.c b/arch/nios2/core/thread.c deleted file mode 100644 index c2f674a3fb0..00000000000 --- a/arch/nios2/core/thread.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/* forward declaration to asm function to adjust setup the arguments - * to z_thread_entry() since this arch puts the first four arguments - * in r4-r7 and not on the stack - */ -void z_thread_entry_wrapper(k_thread_entry_t, void *, void *, void *); - -struct init_stack_frame { - /* top of the stack / most recently pushed */ - - /* Used by z_thread_entry_wrapper. pulls these off the stack and - * into argument registers before calling z_thread_entry() - */ - k_thread_entry_t entry_point; - void *arg1; - void *arg2; - void *arg3; - - /* least recently pushed */ -}; - - -void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, - char *stack_ptr, k_thread_entry_t entry, - void *arg1, void *arg2, void *arg3) -{ - struct init_stack_frame *iframe; - - /* Initial stack frame data, stored at the base of the stack */ - iframe = Z_STACK_PTR_TO_FRAME(struct init_stack_frame, stack_ptr); - - /* Setup the initial stack frame */ - iframe->entry_point = entry; - iframe->arg1 = arg1; - iframe->arg2 = arg2; - iframe->arg3 = arg3; - - thread->callee_saved.sp = (uint32_t)iframe; - thread->callee_saved.ra = (uint32_t)z_thread_entry_wrapper; - thread->callee_saved.key = NIOS2_STATUS_PIE_MSK; - /* Leave the rest of thread->callee_saved junk */ -} diff --git a/arch/nios2/core/timing.c b/arch/nios2/core/timing.c deleted file mode 100644 index 80ee73c6f06..00000000000 --- a/arch/nios2/core/timing.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2020 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include "altera_avalon_timer_regs.h" - -#define NIOS2_SUBTRACT_CLOCK_CYCLES(val) \ - ((IORD_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE) << 16 | \ - (IORD_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE))) - \ - ((uint32_t)val)) - -#define TIMING_INFO_OS_GET_TIME() \ - (NIOS2_SUBTRACT_CLOCK_CYCLES( \ - ((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) \ - << 16) | \ - ((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE)))) - -void arch_timing_init(void) -{ -} - -void arch_timing_start(void) -{ -} - -void arch_timing_stop(void) -{ -} - -timing_t arch_timing_counter_get(void) -{ - IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE, 10); - return TIMING_INFO_OS_GET_TIME(); -} - -uint64_t arch_timing_cycles_get(volatile timing_t *const start, - volatile timing_t *const end) -{ - timing_t start_ = *start; - timing_t end_ = *end; - - if (end_ >= start_) { - return (end_ - start_); - } - return (end_ + NIOS2_SUBTRACT_CLOCK_CYCLES(start_)); -} - -uint64_t arch_timing_freq_get(void) -{ - return sys_clock_hw_cycles_per_sec(); -} - -uint64_t arch_timing_cycles_to_ns(uint64_t cycles) -{ - return k_cyc_to_ns_floor64(cycles); -} - -uint64_t arch_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count) -{ - return arch_timing_cycles_to_ns(cycles) / count; -} - -uint32_t arch_timing_freq_get_mhz(void) -{ - return (uint32_t)(arch_timing_freq_get() / 1000000U); -} diff --git a/arch/nios2/include/kernel_arch_data.h b/arch/nios2/include/kernel_arch_data.h deleted file mode 100644 index 2f1dbdd1f91..00000000000 --- a/arch/nios2/include/kernel_arch_data.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * Copyright (c) 2016 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Private kernel definitions - * - * This file contains private kernel structures definitions and various - * other definitions for the Nios II processor architecture. - * - * This file is also included by assembly language files which must #define - * _ASMLANGUAGE before including this header file. Note that kernel - * assembly source files obtains structure offset values via "absolute - * symbols" in the offsets.o module. - */ - -#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ -#define ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ - -#include -#include -#include - -#ifndef _ASMLANGUAGE - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _ASMLANGUAGE */ - -#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_DATA_H_ */ diff --git a/arch/nios2/include/kernel_arch_func.h b/arch/nios2/include/kernel_arch_func.h deleted file mode 100644 index c325ea49b49..00000000000 --- a/arch/nios2/include/kernel_arch_func.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Private kernel definitions - * - * This file contains private kernel function/macro definitions and various - * other definitions for the Nios II processor architecture. - * - * This file is also included by assembly language files which must #define - * _ASMLANGUAGE before including this header file. Note that kernel - * assembly source files obtains structure offset values via "absolute - * symbols" in the offsets.o module. - */ - -#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ -#define ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ - -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef _ASMLANGUAGE - -static ALWAYS_INLINE void arch_kernel_init(void) -{ -#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK - soc_per_core_init_hook(); -#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ -} - -static ALWAYS_INLINE void -arch_thread_return_value_set(struct k_thread *thread, unsigned int value) -{ - thread->callee_saved.retval = value; -} - -FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason, - const struct arch_esf *esf); - -static inline bool arch_is_in_isr(void) -{ - return _kernel.cpus[0].nested != 0U; -} - -int arch_swap(unsigned int key); - -#ifdef CONFIG_IRQ_OFFLOAD -void z_irq_do_offload(void); -#endif - -#if ALT_CPU_ICACHE_SIZE > 0 -void z_nios2_icache_flush_all(void); -#else -#define z_nios2_icache_flush_all() do { } while (false) -#endif - -#if ALT_CPU_DCACHE_SIZE > 0 -void z_nios2_dcache_flush_all(void); -void z_nios2_dcache_flush_no_writeback(void *start, uint32_t len); -#else -#define z_nios2_dcache_flush_all() do { } while (false) -#define z_nios2_dcache_flush_no_writeback(x, y) do { } while (false) -#endif - -#endif /* _ASMLANGUAGE */ - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/nios2/include/offsets_short_arch.h b/arch/nios2/include/offsets_short_arch.h deleted file mode 100644 index 3b961e1fcb9..00000000000 --- a/arch/nios2/include/offsets_short_arch.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2016 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#define ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ - -#include - -/* kernel */ - -/* nothing for now */ - -/* end - kernel */ - -/* threads */ - -#define _thread_offset_to_r16 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r16_OFFSET) - -#define _thread_offset_to_r17 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r17_OFFSET) - -#define _thread_offset_to_r18 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r18_OFFSET) - -#define _thread_offset_to_r19 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r19_OFFSET) - -#define _thread_offset_to_r20 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r20_OFFSET) - -#define _thread_offset_to_r21 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r21_OFFSET) - -#define _thread_offset_to_r22 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r22_OFFSET) - -#define _thread_offset_to_r23 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r23_OFFSET) - -#define _thread_offset_to_r28 \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_r28_OFFSET) - -#define _thread_offset_to_ra \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_ra_OFFSET) - -#define _thread_offset_to_sp \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET) - -#define _thread_offset_to_key \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_key_OFFSET) - -#define _thread_offset_to_retval \ - (___thread_t_callee_saved_OFFSET + ___callee_saved_t_retval_OFFSET) - -/* end - threads */ - -#endif /* ZEPHYR_ARCH_NIOS2_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/posix/core/irq.c b/arch/posix/core/irq.c index a1d3568c154..eba9cda41d2 100644 --- a/arch/posix/core/irq.c +++ b/arch/posix/core/irq.c @@ -17,6 +17,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) void arch_irq_offload_init(void) { + /* Nothing to be done for this architecture */ } #endif diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 72907a41fee..7f4f57eb283 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -428,6 +428,7 @@ config MAIN_STACK_SIZE default 2048 if PMP_STACK_GUARD config TEST_EXTRA_STACK_SIZE + default 4096 if CPP_EXCEPTIONS default 1536 config CMSIS_THREAD_MAX_STACK_SIZE diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa index 7ac915865d1..29fc8cf9225 100644 --- a/arch/riscv/Kconfig.isa +++ b/arch/riscv/Kconfig.isa @@ -162,3 +162,11 @@ config RISCV_ISA_EXT_ZBS The Zbs instructions can be used for single-bit instructions that provide a mechanism to set, clear, invert, or extract a single bit in a register. + +config RISCV_ISA_EXT_ZMMUL + bool + help + (Zmmul) - Zmmul Extension for Integer Multiplication + + The Zmmul extension implements the multiplication subset of the M + extension. diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c index e29c8abd76d..f6784d28201 100644 --- a/arch/riscv/core/pmp.c +++ b/arch/riscv/core/pmp.c @@ -204,6 +204,7 @@ static bool set_pmp_entry(unsigned int *index_p, uint8_t perm, return ok; } +#ifdef CONFIG_PMP_STACK_GUARD static inline bool set_pmp_mprv_catchall(unsigned int *index_p, unsigned long *pmp_addr, unsigned long *pmp_cfg, unsigned int index_limit) @@ -231,6 +232,7 @@ static inline bool set_pmp_mprv_catchall(unsigned int *index_p, return ok; } +#endif /* CONFIG_PMP_STACK_GUARD */ /** * @brief Write a range of PMP entries to corresponding PMP registers @@ -447,6 +449,7 @@ void z_riscv_pmp_init(void) /** * @Brief Initialize the per-thread PMP register copy with global values. */ +#if (defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)) || defined(CONFIG_USERSPACE) static inline unsigned int z_riscv_pmp_thread_init(unsigned long *pmp_addr, unsigned long *pmp_cfg, unsigned int index_limit) @@ -466,6 +469,7 @@ static inline unsigned int z_riscv_pmp_thread_init(unsigned long *pmp_addr, return global_pmp_end_index; } +#endif #ifdef CONFIG_PMP_STACK_GUARD diff --git a/arch/rx/CMakeLists.txt b/arch/rx/CMakeLists.txt new file mode 100644 index 00000000000..f7c57ff76b9 --- /dev/null +++ b/arch/rx/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2020 KT-Elektronik, Klaucke und Partner GmbH +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(core) +set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-rx-le) # needed for e.g. objcopy diff --git a/arch/rx/Kconfig b/arch/rx/Kconfig new file mode 100644 index 00000000000..9e34a16ea09 --- /dev/null +++ b/arch/rx/Kconfig @@ -0,0 +1,74 @@ +# Renesas RX architecture configuration options + +# Copyright (c) 2020 KT-Elektronik, Klaucke und Partner GmbH +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +menu "Renesas RX Options" + depends on RX + +config ARCH + string + default "rx" + +config CPU_RXV1 + bool + help + Set if the processor supports the Renesas RXv1 instruction set. + +config CPU_RXV2 + bool + help + Set if the processor supports the Renesas RXv2 instruction set. + +config CPU_RXV3 + bool + help + Set if the processor supports the Renesas RXv3 instruction set. + +config HAS_EXCEPT_VECTOR_TABLE + bool + help + Set if the processor has the exception vector table. + +config XIP + default y + +config NUM_IRQ_PRIO_LEVELS + int "Number of supported interrupt priority levels" + range 1 16 + default 16 + help + Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. The + minimum value is 1. The BSP must provide a valid default for proper + operation. + +config NUM_IRQS + int + default 256 + +config GEN_ISR_TABLES + default y + +config GEN_SW_ISR_TABLE + default y + +config GEN_IRQ_VECTOR_TABLE + default n + +config GEN_IRQ_START_VECTOR + default 16 + +config DYNAMIC_INTERRUPTS + default y + +config MAIN_STACK_SIZE + default 1024 + +config INITIALIZATION_STACK_SIZE + int "Initialization stack size (in bytes)" + default 512 + help + Stack size for initialization process of kernel (in bytes) + +endmenu diff --git a/arch/rx/core/CMakeLists.txt b/arch/rx/core/CMakeLists.txt new file mode 100644 index 00000000000..5b3e888db6a --- /dev/null +++ b/arch/rx/core/CMakeLists.txt @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources( + switch.S + cpu_idle.c + prep_c.c + irq_manage.c + reset.S + thread.c + vects.c + isr_exit.S +) + +zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) diff --git a/arch/rx/core/cpu_idle.c b/arch/rx/core/cpu_idle.c new file mode 100644 index 00000000000..a109057f88d --- /dev/null +++ b/arch/rx/core/cpu_idle.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +void arch_cpu_idle(void) +{ + sys_trace_idle(); + + /* The assembler instruction "wait" switches the processor to sleep mode, + * which stops program execution until an interrupt is triggered. + * All clocks that are not in a stop state continue operating, including + * the system timer. + * + * Also, "wait" sets the PSW I bit, activating + * interrupts (otherwise, the processor would never return from sleep + * mode). This is consistent with the Zephyr API description, according + * to which "In some architectures, before returning, the function + * unmasks interrupts unconditionally." - this is such an architecture. + */ + __asm__ volatile("wait"); +} + +void arch_cpu_atomic_idle(unsigned int key) +{ + sys_trace_idle(); + + /* The assembler instruction "wait" switches the processor to sleep mode, + * which stops program execution until an interrupt is triggered. + * All clocks that are not in a stop state continue operating, including + * the system timer. + */ + __asm__ volatile("wait"); + + /* "wait" unconditionally unlocks interrupts. To restore the interrupt + * lockout state before calling arch_cpu_atomic_idle, interrupts have + * to be locked after returning from "wait" if irq_lock would NOT have + * unlocked interrupts (i.e. if the key indicates nested interrupt + * locks) + */ + if (key == 0) { + irq_lock(); + } +} diff --git a/arch/rx/core/irq_manage.c b/arch/rx/core/irq_manage.c new file mode 100644 index 00000000000..7bbba890738 --- /dev/null +++ b/arch/rx/core/irq_manage.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include + +#define IR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IR) +#define IER_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IER) +#define IPR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), IPR) + +#define NUM_IRQS_PER_REG 8 +#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) +#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) +#define REG(addr) *((uint8_t *)(addr)) + +/** + * @brief Enable an IRQ by setting the corresponding IEN bit. + * + * Note that this will have no effect for IRQs 0-15 as the + * Renesas rx chip ignores write operations on the corresponding + * Registers + * + * @param irq interrupt to enable (16-255) + */ +void arch_irq_enable(unsigned int irq) +{ + __ASSERT(irq < CONFIG_NUM_IRQS, "trying to enable invalid interrupt (%u)", irq); + __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "trying to enable reserved interrupt (%u)", + irq); + + uint32_t key = irq_lock(); + + /* reset interrupt before activating */ + WRITE_BIT(REG(IR_BASE_ADDRESS + irq), 0, false); + WRITE_BIT(REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)), BIT_FROM_IRQ(irq), true); + irq_unlock(key); +} + +/** + * @brief Disable an IRQ by clearing the corresponding IEN bit. + * + * Note that this will have no effect for IRQs 0-15 as the + * Renesas rx chip ignores write operations on the corresponding + * Registers. + * + * @param irq interrupt to disable (16-255) + */ +void arch_irq_disable(unsigned int irq) +{ + __ASSERT(irq < CONFIG_NUM_IRQS, "trying to disable invalid interrupt (%u)", irq); + __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "trying to disable reserved interrupt (%u)", + irq); + + uint32_t key = irq_lock(); + + WRITE_BIT(REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)), BIT_FROM_IRQ(irq), false); + irq_unlock(key); +} + +/** + * @brief Determine if an IRQ is enabled by reading the corresponding IEN bit. + * + * @param irq interrupt number + * + * @return true if the interrupt is enabled + */ +int arch_irq_is_enabled(unsigned int irq) +{ + __ASSERT(irq < CONFIG_NUM_IRQS, "is_enabled on invalid interrupt (%u)", irq); + __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "is_enabled on reserved interrupt (%u)", irq); + + return (REG(IER_BASE_ADDRESS + REG_FROM_IRQ(irq)) & BIT(BIT_FROM_IRQ(irq))) != 0; +} + +/* + * @brief Spurious interrupt handler + * + * Installed in all dynamic interrupt slots at boot time. Throws an error if + * called. + * + * @return N/A + */ + +void z_irq_spurious(const void *unused) +{ + ARG_UNUSED(unused); + z_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); +} + +/* + * @internal + * + * @brief Set an interrupt's priority + * + * Higher values take priority over lower values. + * + * @return N/A + */ + +void z_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) +{ + __ASSERT(irq < CONFIG_NUM_IRQS, "irq_priority_set on invalid interrupt (%u)", irq); + __ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "irq_priority_set on reserved interrupt (%u)", + irq); + __ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS, "invalid priority (%u) for interrupt %u", prio, + irq); + + uint32_t key = irq_lock(); + + if (irq >= 34) { + /* for interrupts >= 34, the IPR is regular */ + REG(IPR_BASE_ADDRESS + irq) = prio; + } else { + switch (irq) { + /* 0-15: no IPR */ + case 16: + /* 17: no IPR */ + case 18: + REG(IPR_BASE_ADDRESS) = prio; + break; + /* 19,20: no IPR */ + case 21: + REG(IPR_BASE_ADDRESS + 1) = prio; + break; + /* 22: no IPR */ + case 23: + REG(IPR_BASE_ADDRESS + 2) = prio; + break; + /* 24,25: no IPR */ + case 26: + case 27: + REG(IPR_BASE_ADDRESS + 3) = prio; + break; + case 28: + REG(IPR_BASE_ADDRESS + 4) = prio; + break; + case 29: + REG(IPR_BASE_ADDRESS + 5) = prio; + break; + case 30: + REG(IPR_BASE_ADDRESS + 6) = prio; + break; + case 31: + REG(IPR_BASE_ADDRESS + 7) = prio; + break; + /* 32,33: no IPR */ + } + } + irq_unlock(key); +} + +#ifdef CONFIG_DYNAMIC_INTERRUPTS +/** + * @brief connect a callback function to an interrupt at runtime + * + * @param irq interrupt number + * @param priority priority of the interrupt + * @param routine routine to call when the interrupt is triggered + * @param parameter parameter to supply to the routine on call + * @param flags flags for the interrupt + * + * @return the interrupt number + */ +int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, + void (*routine)(const void *parameter), const void *parameter, + uint32_t flags) +{ + z_isr_install(irq, routine, parameter); + z_irq_priority_set(irq, priority, flags); + return irq; +} +#endif /* CONFIG_DYNAMIC_INTERRUPTS */ diff --git a/arch/rx/core/irq_offload.c b/arch/rx/core/irq_offload.c new file mode 100644 index 00000000000..9845bb4da87 --- /dev/null +++ b/arch/rx/core/irq_offload.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Software interrupts utility code - Renesas rx architecture implementation. + * + * The code is using the first software interrupt (SWINT) of the RX processor + * should this interrupt ever be used for something else, this has to be + * changed - maybe to the second software interrupt (SWINT2). + */ + +#include +#include +#include + +#define SWINT1_IRQ_LINE 27 +#define SWINT1_PRIO 14 +/* Address of the software interrupt trigger register for SWINT1 */ +#define SWINT_REGISTER_ADDRESS 0x872E0 +#define SWINTR_SWINT *(uint8_t *)(SWINT_REGISTER_ADDRESS) + +static irq_offload_routine_t _offload_routine; +static const void *offload_param; + +void z_irq_do_offload(void) +{ + irq_offload_routine_t tmp; + + if (!_offload_routine) { + return; + } + + tmp = _offload_routine; + _offload_routine = NULL; + + tmp((const void *)offload_param); +} + +static void swi0_handler(void) +{ + z_irq_do_offload(); +} + +void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) +{ + _offload_routine = routine; + offload_param = parameter; + + SWINTR_SWINT = 1; +} + +void arch_irq_offload_init(void) +{ + IRQ_CONNECT(SWINT1_IRQ_LINE, SWINT1_PRIO, swi0_handler, NULL, 0); + irq_enable(SWINT1_IRQ_LINE); +} diff --git a/arch/rx/core/isr_exit.S b/arch/rx/core/isr_exit.S new file mode 100644 index 00000000000..69fcd0482d9 --- /dev/null +++ b/arch/rx/core/isr_exit.S @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +.list +.section .text +GTEXT(_z_rx_irq_exit) + +_z_rx_irq_exit: + mov #__kernel, r1 ; Load the base address of _kernel into r1 + mov r1, r3 ; Load the base address of _kernel into r1 + + add #___cpu_t_current_OFFSET, r1 ; Add the offset for the 'current' field to r1 + mov [r1], r2 ; Load the value of _kernel.cpus[0].current into r2 + + push r2 ; Save old_thread to the stack + + ; Get the next thread to schedule + mov #0,r1 ; Use r1 to pass NULL since we haven't saved the context yet + bsr _z_get_next_switch_handle ; Call the function + + ; The return value of z_get_next_switch_handle will now be in r1 + ; Restore old_thread from the stack + pop r2 ; Restore old_thread from the stack + + ; Check if a switch is necessary + cmp #0, r1 + bz no_switch ; If new_thread (in r1) is NULL, jump to no_switch + + add #___thread_t_switch_handle_OFFSET, r2 + + ; Call arch_switch to perform the context switch + bsr _z_rx_arch_switch ; r1: new_thread->switch_handle, r2: old_thread->switch_handle + +no_switch: + rts diff --git a/arch/rx/core/offsets/offsets.c b/arch/rx/core/offsets/offsets.c new file mode 100644 index 00000000000..b0ac1b4dd5c --- /dev/null +++ b/arch/rx/core/offsets/offsets.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief RX Kernel structure member offset definition file + * + * This module is responsible for the generation of the absolute symbols whose + * value represents the member offsets for various structures. + * + * All of the absolute symbols defined by this module will be present in the + * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms + * symbol). + * + * INTERNAL + * It is NOT necessary to define the offset for every member of a structure. + * Typically, only those members that are accessed by assembly language routines + * are defined; however, it doesn't hurt to define all fields for the sake of + * completeness. + */ +#ifndef _RX_OFFSETS_INC_ +#define _RX_OFFSETS_INC_ + +#include +#include +#include +#include + +GEN_ABSOLUTE_SYM(__callee_saved_t_SIZEOF, sizeof(_callee_saved_t)); +GEN_ABSOLUTE_SYM(__thread_arch_t_SIZEOF, sizeof(_thread_arch_t)); + +GEN_ABS_SYM_END + +#endif /* _RX_OFFSETS_INC_ */ diff --git a/arch/rx/core/prep_c.c b/arch/rx/core/prep_c.c new file mode 100644 index 00000000000..09d86d10d36 --- /dev/null +++ b/arch/rx/core/prep_c.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Full C support initialization + * + * + * Initialization of full C support: zero the .bss and call z_cstart(). + * + * Stack is available in this module, but not the global data/bss until their + * initialization is performed. + */ + +#include +#include +#include +#include +#include + +K_KERNEL_PINNED_STACK_ARRAY_DEFINE(z_initialization_process_stacks, CONFIG_MP_MAX_NUM_CPUS, + CONFIG_INITIALIZATION_STACK_SIZE); +/** + * @brief Prepare to and run C code + * + * This routine prepares for the execution of and runs C code. + * + * @return N/A + */ +void z_prep_c(void) +{ + z_bss_zero(); + + z_data_copy(); + + z_cstart(); + CODE_UNREACHABLE; +} diff --git a/arch/rx/core/reset.S b/arch/rx/core/reset.S new file mode 100644 index 00000000000..80246fe397e --- /dev/null +++ b/arch/rx/core/reset.S @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +.list +.section .text +GTEXT(__start) +__start : + +/* during initialization (before the main thread is started), z_initialization_process_stacks + * is used to do the kernel initialization. + */ + mvtc #(_z_initialization_process_stacks + CONFIG_INITIALIZATION_STACK_SIZE),USP + +/* initialise interrupt stack pointer */ + mvtc #(_z_interrupt_stacks + CONFIG_ISR_STACK_SIZE),ISP + +/* set exception vector address (_ExceptVectors is defined in vects.c) */ +#if CONFIG_HAS_EXCEPT_VECTOR_TABLE + mvtc #_ExceptVectors, extb +#endif + +/* set interrupt vector address (_rvectors_start is defined in vects.c) */ + mvtc #_rvectors_start, intb + +/* load data section from ROM to RAM */ + + mov #_mdata,r2 /* src ROM address of data section in R2 */ + mov #_data,r1 /* dest start RAM address of data section in R1 */ + mov #_edata,r3 /* end RAM address of data section in R3 */ + sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ +#ifdef __RX_ALLOW_STRING_INSNS__ + smovf /* block copy R3 bytes from R2 to R1 */ +#else + cmp #0, r3 + beq 2f + +1: mov.b [r2+], r5 + mov.b r5, [r1+] + sub #1, r3 + bne 1b +2: +#endif + +/* bss initialisation: zero out bss */ + mov #0,r2 /* load R2 reg with zero */ + mov #_ebss, r3 /* store the end address of bss in R3 */ + mov #_bss, r1 /* store the start address of bss in R1 */ + sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */ + sstr.b + +#ifdef CONFIG_INIT_STACKS + /* initialize the irq stack (it is located in the bss section) */ + mov #0xaa,r2 /* initialization value 0xaa */ + mov #_z_interrupt_stacks, r1 /* start address */ + mov #CONFIG_ISR_STACK_SIZE, r3 /* stack size */ + sstr.b +#endif + +/* setup PSW - use user stack register and lock interrupts during initialization */ + mvtc #0x20000, psw + +#ifdef CPPAPP + bsr __rx_init +#endif + +/* start user program */ + bsr _z_cstart + bsr _exit + +#ifdef CPPAPP + .global _rx_run_preinit_array + .type _rx_run_preinit_array,@function +_rx_run_preinit_array: + mov #__preinit_array_start,r1 + mov #__preinit_array_end,r2 + mov #_rx_run_inilist,r7 + jsr r7 + + .global _rx_run_init_array + .type _rx_run_init_array,@function +_rx_run_init_array: + mov #__init_array_start,r1 + mov #__init_array_end,r2 + mov #4, r3 + mov #_rx_run_inilist,r7 + jsr r7 + + .global _rx_run_fini_array + .type _rx_run_fini_array,@function +_rx_run_fini_array: + mov #__fini_array_start,r2 + mov #__fini_array_end,r1 + mov #-4, r3 + /* fall through */ + +_rx_run_inilist: +next_inilist: + cmp r1,r2 + beq.b done_inilist + mov.l [r1],r4 + cmp #-1, r4 + beq.b skip_inilist + cmp #0, r4 + beq.b skip_inilist + pushm r1-r3 + jsr r4 + popm r1-r3 +skip_inilist: + add r3,r1 + mov #next_inilist,r7 + jsr r7 +done_inilist: + rts + + .section .init,"ax" + .balign 4 + + .global __rx_init +__rx_init: + + .section .fini,"ax" + .balign 4 + + .global __rx_fini +__rx_fini: + mov #_rx_run_fini_array,r7 + jsr r7 + + .section .sdata + .balign 4 + .global __gp + .weak __gp +__gp: + + .section .data + .global ___dso_handle + .weak ___dso_handle +___dso_handle: + .long 0 + + .section .init,"ax" + mov #_rx_run_preinit_array,r7 + jsr r7 + mov #_rx_run_init_array,r7 + jsr r7 + rts + + .global __rx_init_end +__rx_init_end: + + .section .fini,"ax" + + rts + .global __rx_fini_end +__rx_fini_end: + +#endif + +/* call to exit*/ +_exit: + bra _loop_here +_loop_here: + bra _loop_here + + .text + .end diff --git a/arch/rx/core/switch.S b/arch/rx/core/switch.S new file mode 100644 index 00000000000..5894530b3af --- /dev/null +++ b/arch/rx/core/switch.S @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +GTEXT(_z_rx_arch_switch) +GTEXT(_switch_isr_wrapper) + +/* void z_rx_arch_switch(void *switch_to, void **switched_from) + * + * @brief switch between threads + * + * @param switch_to (r1) pointer to switch handle of the new thread + * @param switched_from (r2) pointer to pointer to switch handle of the old + * thread + * + * Thread-switching is treated differently depending on whether it is a + * cooperative switch triggered by old thread itself or a preemptive switch + * triggered by an interrupt (in this case the function has been called from an + * ISR). + */ +.section .text._z_rx_arch_switch +.align 4 +_z_rx_arch_switch: + + mvfc psw,r3 + tst #0x130000, r3 /* test if PM, U or I bit are set*/ + bz _z_rx_context_switch_isr /* if none of them are set, this is an isr */ + + mov #_coop_switch_to,r3 + mov r1,[r3] + mov #_coop_switched_from,r3 + mov r2,[r3] + + /* trigger unconditional interrupt dedicated to thread switching. The content of r1 and r2 + * will not change by invoking the interrupt so the parameters switch_to and switched_from + * will be available in _z_rx_context_switch_isr, which has been entered into the vector + * table as ISR for interrupt 1 + */ + int #1 + + /* at this point, r0 points to the entry point, so RTS will enter it */ + rts + +/* void switch_isr_wrapper(void) + * + * @brief isr for interrupt 1 as wrapper for _z_rx_context_switch_isr + * + * _z_rx_context_switch_isr ends in rts, so it does not return from the interrupt context + */ +.section .text._switch_isr_wrapper +.align 4 +_switch_isr_wrapper: + pushm r1-r15 + + /* Save the accumulator. */ + mvfachi r15 /* Accumulator high 32 bits. */ + push r15 + mvfacmi r15 /* Accumulator middle 32 bits. */ + shll #16, r15 /* Shifted left as it is restored to the low order word.*/ + push r15 + + mov #_coop_switch_to,r3 + mov [r3],r1 + mov #_coop_switched_from,r3 + mov [r3],r2 + + bsr _z_rx_context_switch_isr + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + pop r15 + mvtaclo r15 /* Accumulator low 32 bits. */ + pop r15 + mvtachi r15 /* Accumulator high 32 bits. */ + + popm r1-r15 + rte + +/* void z_rx_context_switch_isr(void *switch_to, void **switched_from) + * + * @brief switch between threads in the interrupt context + * + * @param switch_to (r1) pointer to switch handle of the new thread + * @param switched_from (r2) pointer to pointer to switch handle of the old thread + * + * since this is part of an ISR, PSW, PC and general registers of the old thread are already + * stored in the interrupt stack, so copy the corresponding part of the interrupt stack to the + * stack of the interrupted thread + */ +_z_rx_context_switch_isr: + + /* store arguments switch_to and switched_from to registers r4 and r5 as + * registers r2 and r3 are needed for the smovf operation */ + mov r1,r4 + mov r2,r5 + + /* set r2 (smovb source address) to the beginning of the interrupt stack */ + mov #(_z_interrupt_stacks + CONFIG_ISR_STACK_SIZE)-1,r2 + + mvfc usp,r1 /* set r1 (smovb dest) to USP */ + + sub #1,r1 /* correct by one byte to use smovb compared to push/pop */ + + /* set r3 to number of bytes to move + * Accumulator 64bit (4byte * 2) + * 15*4 byte for 15 general registers + * + PSW (4 byte) + * + PC (4 byte) + */ + mov #76,r3 + smovb /* block copy from interrupt stack to old thread stack */ + + add #1,r1 /* smovb leaves r1 pointing 1 byte before the stack */ + add #1,r2 /* same with r2 */ + + mov r1,[r5] /* store stack pointer of old thread in *switched_from */ + + mov r2,r1 /* set r1 (smovf dest) to the beginning of the interrupt stack */ + + mov r4,r2 /* set r2 (smovf source) to the sp of the new thread*/ + mov #76,r3 /* set r3 to number of bytes to move */ + + smovf /* block copy from new thread stack to interrupt stack */ + + mvtc r2,usp /* set USP to the new thread stack */ + +#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING + bsr _z_thread_mark_switched_in +#endif + + rts diff --git a/arch/rx/core/thread.c b/arch/rx/core/thread.c new file mode 100644 index 00000000000..88670bf75da --- /dev/null +++ b/arch/rx/core/thread.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); + +/* variables to store the arguments of z_rx_context_switch_isr() (zephyr\arch\rx\core\switch.S) + * when performing a cooperative thread switch. In that case, z_rx_context_switch_isr() triggerss + * unmaskable interrupt 1 to actually perform the switch. The ISR to interrupt 1 + * (switch_isr_wrapper()) reads the arguments from these variables. + */ +void *coop_switch_to; +void **coop_switched_from; + +void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *stack_ptr, + k_thread_entry_t entry, void *arg1, void *arg2, void *arg3) +{ + struct arch_esf *iframe; + + iframe = Z_STACK_PTR_TO_FRAME(struct arch_esf, stack_ptr); + + /* initial value for the PSW (bits U and I are set) */ + iframe->psw = 0x30000; + /* the initial entry point is the function z_thread_entry */ + iframe->entry_point = (uint32_t)z_thread_entry; + /* arguments for the call of z_thread_entry (to be written to r1-r4) */ + iframe->r1 = (uint32_t)entry; + iframe->r2 = (uint32_t)arg1; + iframe->r3 = (uint32_t)arg2; + iframe->r4 = (uint32_t)arg3; + /* for debugging: */ + iframe->r5 = 5; + iframe->r6 = 6; + iframe->r7 = 7; + iframe->r8 = 8; + iframe->r9 = 9; + iframe->r10 = 10; + iframe->r11 = 11; + iframe->r12 = 12; + iframe->r13 = 13; + iframe->r14 = 14; + iframe->r15 = 15; + iframe->acc_l = 16; + iframe->acc_h = 17; + + thread->switch_handle = (void *)iframe; +} diff --git a/arch/rx/core/vects.c b/arch/rx/core/vects.c new file mode 100644 index 00000000000..836e9d3adb2 --- /dev/null +++ b/arch/rx/core/vects.c @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +typedef void (*fp)(void); +extern void _start(void); +extern void z_rx_irq_exit(void); + +/* this is mainly to give Visual Studio Code peace of mind */ +#ifndef CONFIG_GEN_IRQ_START_VECTOR +#define CONFIG_GEN_IRQ_START_VECTOR 0 +#endif + +#define EXVECT_SECT __attribute__((section(".exvectors"))) +#define RVECT_SECT __attribute__((section(".rvectors"))) +#define FVECT_SECT __attribute__((section(".fvectors"))) + +#define __ISR__ __attribute__((interrupt, naked)) + +static ALWAYS_INLINE void REGISTER_SAVE(void) +{ + __asm volatile( + /* Save the Registers to ISP at the top of ISR. */ + /* This code is relate on arch_new_thread() at thread.c */ + /* You should store the registers at the same registers arch_new_thread() */ + /* except PC and PSW. */ + "PUSHM R1-R15\n" + + "MVFACHI R15\n" + "PUSH.L R15\n" + "MVFACMI R15\n" + "SHLL #16, R15\n" + "PUSH.L R15\n"); +} + +static ALWAYS_INLINE void REGISTER_RESTORE_EXIT(void) +{ + __asm volatile( + /* Restore the registers and do the RTE at the End of ISR. */ + "POP R15\n" + "MVTACLO R15\n" + "POP R15\n" + "MVTACHI R15\n" + + "POPM R1-R15\n" + "RTE\n"); +} + +/* Privileged instruction execption */ +static void __ISR__ INT_Excep_SuperVisorInst(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* Access exception */ +static void __ISR__ INT_Excep_AccessInst(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* Undefined instruction exception */ +static void __ISR__ INT_Excep_UndefinedInst(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* floating point exception */ +static void __ISR__ INT_Excep_FloatingPoint(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* Non-maskable interrupt */ +static void __ISR__ INT_NonMaskableInterrupt(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* dummy function */ +static void __ISR__ Dummy(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/** + * @brief select Zephyr ISR and argument from software ISR table and call + * function + * + * @param irq interrupt to handle + */ +static ALWAYS_INLINE void handle_interrupt(uint8_t irq) +{ + ISR_DIRECT_HEADER(); + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + ISR_DIRECT_FOOTER(1); +} + +/** + * @brief isr for reserved interrupts (0-15) that are not handled through + * the zephyr sw isr table + */ +static void __ISR__ reserved_isr(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + +/* wrapper for z_rx_context_switch_isr, defined in switch.S */ +extern void __ISR__ switch_isr_wrapper(void); + +/* this macro is used to define "demuxing" ISRs for all interrupts that are + * handled through Zephyr's software isr table. + */ + +#define INT_DEMUX(irq) \ + static __attribute__((interrupt, naked)) void int_demux_##irq(void) \ + { \ + REGISTER_SAVE(); \ + handle_interrupt(irq - CONFIG_GEN_IRQ_START_VECTOR); \ + REGISTER_RESTORE_EXIT(); \ + } + +INT_DEMUX(16); +INT_DEMUX(17); +INT_DEMUX(18); +INT_DEMUX(19); +INT_DEMUX(20); +INT_DEMUX(21); +INT_DEMUX(22); +INT_DEMUX(23); +INT_DEMUX(24); +INT_DEMUX(25); +INT_DEMUX(27); +INT_DEMUX(26); +INT_DEMUX(28); +INT_DEMUX(29); +INT_DEMUX(30); +INT_DEMUX(31); +INT_DEMUX(32); +INT_DEMUX(33); +INT_DEMUX(34); +INT_DEMUX(35); +INT_DEMUX(36); +INT_DEMUX(37); +INT_DEMUX(38); +INT_DEMUX(39); +INT_DEMUX(40); +INT_DEMUX(41); +INT_DEMUX(42); +INT_DEMUX(43); +INT_DEMUX(44); +INT_DEMUX(45); +INT_DEMUX(46); +INT_DEMUX(47); +INT_DEMUX(48); +INT_DEMUX(49); +INT_DEMUX(50); +INT_DEMUX(51); +INT_DEMUX(52); +INT_DEMUX(53); +INT_DEMUX(54); +INT_DEMUX(55); +INT_DEMUX(56); +INT_DEMUX(57); +INT_DEMUX(58); +INT_DEMUX(59); +INT_DEMUX(60); +INT_DEMUX(61); +INT_DEMUX(62); +INT_DEMUX(63); +INT_DEMUX(64); +INT_DEMUX(65); +INT_DEMUX(66); +INT_DEMUX(67); +INT_DEMUX(68); +INT_DEMUX(69); +INT_DEMUX(70); +INT_DEMUX(71); +INT_DEMUX(72); +INT_DEMUX(73); +INT_DEMUX(74); +INT_DEMUX(75); +INT_DEMUX(76); +INT_DEMUX(77); +INT_DEMUX(78); +INT_DEMUX(79); +INT_DEMUX(80); +INT_DEMUX(81); +INT_DEMUX(82); +INT_DEMUX(83); +INT_DEMUX(84); +INT_DEMUX(85); +INT_DEMUX(86); +INT_DEMUX(87); +INT_DEMUX(88); +INT_DEMUX(89); +INT_DEMUX(90); +INT_DEMUX(91); +INT_DEMUX(92); +INT_DEMUX(93); +INT_DEMUX(94); +INT_DEMUX(95); +INT_DEMUX(96); +INT_DEMUX(97); +INT_DEMUX(98); +INT_DEMUX(99); +INT_DEMUX(100) +INT_DEMUX(101); +INT_DEMUX(102); +INT_DEMUX(103); +INT_DEMUX(104); +INT_DEMUX(105); +INT_DEMUX(106); +INT_DEMUX(107); +INT_DEMUX(108); +INT_DEMUX(109); +INT_DEMUX(110); +INT_DEMUX(111); +INT_DEMUX(112); +INT_DEMUX(113); +INT_DEMUX(114); +INT_DEMUX(115); +INT_DEMUX(116); +INT_DEMUX(117); +INT_DEMUX(118); +INT_DEMUX(119); +INT_DEMUX(120); +INT_DEMUX(121); +INT_DEMUX(122); +INT_DEMUX(123); +INT_DEMUX(124); +INT_DEMUX(125); +INT_DEMUX(126); +INT_DEMUX(127); +INT_DEMUX(128); +INT_DEMUX(129); +INT_DEMUX(130); +INT_DEMUX(131); +INT_DEMUX(132); +INT_DEMUX(133); +INT_DEMUX(134); +INT_DEMUX(135); +INT_DEMUX(136); +INT_DEMUX(137); +INT_DEMUX(138); +INT_DEMUX(139); +INT_DEMUX(140); +INT_DEMUX(141); +INT_DEMUX(142); +INT_DEMUX(143); +INT_DEMUX(144); +INT_DEMUX(145); +INT_DEMUX(146); +INT_DEMUX(147); +INT_DEMUX(148); +INT_DEMUX(149); +INT_DEMUX(150); +INT_DEMUX(151); +INT_DEMUX(152); +INT_DEMUX(153); +INT_DEMUX(154); +INT_DEMUX(155); +INT_DEMUX(156); +INT_DEMUX(157); +INT_DEMUX(158); +INT_DEMUX(159); +INT_DEMUX(160); +INT_DEMUX(161); +INT_DEMUX(162); +INT_DEMUX(163); +INT_DEMUX(164); +INT_DEMUX(165); +INT_DEMUX(166); +INT_DEMUX(167); +INT_DEMUX(168); +INT_DEMUX(169); +INT_DEMUX(170); +INT_DEMUX(171); +INT_DEMUX(172); +INT_DEMUX(173); +INT_DEMUX(174); +INT_DEMUX(175); +INT_DEMUX(176); +INT_DEMUX(177); +INT_DEMUX(178); +INT_DEMUX(179); +INT_DEMUX(180); +INT_DEMUX(181); +INT_DEMUX(182); +INT_DEMUX(183); +INT_DEMUX(184); +INT_DEMUX(185); +INT_DEMUX(186); +INT_DEMUX(187); +INT_DEMUX(188); +INT_DEMUX(189); +INT_DEMUX(190); +INT_DEMUX(191); +INT_DEMUX(192); +INT_DEMUX(193); +INT_DEMUX(194); +INT_DEMUX(195); +INT_DEMUX(196); +INT_DEMUX(197); +INT_DEMUX(198); +INT_DEMUX(199); +INT_DEMUX(200); +INT_DEMUX(201); +INT_DEMUX(202); +INT_DEMUX(203); +INT_DEMUX(204); +INT_DEMUX(205); +INT_DEMUX(206); +INT_DEMUX(207); +INT_DEMUX(208); +INT_DEMUX(209); +INT_DEMUX(210); +INT_DEMUX(211); +INT_DEMUX(212); +INT_DEMUX(213); +INT_DEMUX(214); +INT_DEMUX(215); +INT_DEMUX(216); +INT_DEMUX(217); +INT_DEMUX(218); +INT_DEMUX(219); +INT_DEMUX(220); +INT_DEMUX(221); +INT_DEMUX(222); +INT_DEMUX(223); +INT_DEMUX(224); +INT_DEMUX(225); +INT_DEMUX(226); +INT_DEMUX(227); +INT_DEMUX(228); +INT_DEMUX(229); +INT_DEMUX(230); +INT_DEMUX(231); +INT_DEMUX(232); +INT_DEMUX(233); +INT_DEMUX(234); +INT_DEMUX(235); +INT_DEMUX(236); +INT_DEMUX(237); +INT_DEMUX(238); +INT_DEMUX(239); +INT_DEMUX(240); +INT_DEMUX(241); +INT_DEMUX(242); +INT_DEMUX(243); +INT_DEMUX(244); +INT_DEMUX(245); +INT_DEMUX(246); +INT_DEMUX(247); +INT_DEMUX(248); +INT_DEMUX(249); +INT_DEMUX(250); +INT_DEMUX(251); +INT_DEMUX(252); +INT_DEMUX(253); +INT_DEMUX(254); +INT_DEMUX(255); + +const void *FixedVectors[] FVECT_SECT = { + /* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */ + /* Reserved for OFSM */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* Reserved area */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* Reserved for ID Code */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* Reserved area */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* Reserved area */ + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + (fp)0xFFFFFFFF, + /* 0x50: Privileged instruction exception */ + INT_Excep_SuperVisorInst, + /* 0x54: Access exception */ + INT_Excep_AccessInst, + /* 0x58: Reserved */ + Dummy, + /* 0x5c: Undefined Instruction Exception */ + INT_Excep_UndefinedInst, + /* 0x60: Reserved */ + Dummy, + /* 0x64: Floating Point Exception */ + INT_Excep_FloatingPoint, + /* 0x68-0x74: Reserved */ + Dummy, + Dummy, + Dummy, + Dummy, + /* 0x78: Non-maskable interrupt */ + INT_NonMaskableInterrupt, + _start, +}; + +const fp RelocatableVectors[] RVECT_SECT = { + reserved_isr, switch_isr_wrapper, reserved_isr, reserved_isr, reserved_isr, + reserved_isr, reserved_isr, reserved_isr, reserved_isr, reserved_isr, + reserved_isr, reserved_isr, reserved_isr, reserved_isr, reserved_isr, + reserved_isr, int_demux_16, int_demux_17, int_demux_18, int_demux_19, + int_demux_20, int_demux_21, int_demux_22, int_demux_23, int_demux_24, + int_demux_25, int_demux_26, int_demux_27, int_demux_28, int_demux_29, + int_demux_30, int_demux_31, int_demux_32, int_demux_33, int_demux_34, + int_demux_35, int_demux_36, int_demux_37, int_demux_38, int_demux_39, + int_demux_40, int_demux_41, int_demux_42, int_demux_43, int_demux_44, + int_demux_45, int_demux_46, int_demux_47, int_demux_48, int_demux_49, + int_demux_50, int_demux_51, int_demux_52, int_demux_53, int_demux_54, + int_demux_55, int_demux_56, int_demux_57, int_demux_58, int_demux_59, + int_demux_60, int_demux_61, int_demux_62, int_demux_63, int_demux_64, + int_demux_65, int_demux_66, int_demux_67, int_demux_68, int_demux_69, + int_demux_70, int_demux_71, int_demux_72, int_demux_73, int_demux_74, + int_demux_75, int_demux_76, int_demux_77, int_demux_78, int_demux_79, + int_demux_80, int_demux_81, int_demux_82, int_demux_83, int_demux_84, + int_demux_85, int_demux_86, int_demux_87, int_demux_88, int_demux_89, + int_demux_90, int_demux_91, int_demux_92, int_demux_93, int_demux_94, + int_demux_95, int_demux_96, int_demux_97, int_demux_98, int_demux_99, + int_demux_100, int_demux_101, int_demux_102, int_demux_103, int_demux_104, + int_demux_105, int_demux_106, int_demux_107, int_demux_108, int_demux_109, + int_demux_110, int_demux_111, int_demux_112, int_demux_113, int_demux_114, + int_demux_115, int_demux_116, int_demux_117, int_demux_118, int_demux_119, + int_demux_120, int_demux_121, int_demux_122, int_demux_123, int_demux_124, + int_demux_125, int_demux_126, int_demux_127, int_demux_128, int_demux_129, + int_demux_130, int_demux_131, int_demux_132, int_demux_133, int_demux_134, + int_demux_135, int_demux_136, int_demux_137, int_demux_138, int_demux_139, + int_demux_140, int_demux_141, int_demux_142, int_demux_143, int_demux_144, + int_demux_145, int_demux_146, int_demux_147, int_demux_148, int_demux_149, + int_demux_150, int_demux_151, int_demux_152, int_demux_153, int_demux_154, + int_demux_155, int_demux_156, int_demux_157, int_demux_158, int_demux_159, + int_demux_160, int_demux_161, int_demux_162, int_demux_163, int_demux_164, + int_demux_165, int_demux_166, int_demux_167, int_demux_168, int_demux_169, + int_demux_170, int_demux_171, int_demux_172, int_demux_173, int_demux_174, + int_demux_175, int_demux_176, int_demux_177, int_demux_178, int_demux_179, + int_demux_180, int_demux_181, int_demux_182, int_demux_183, int_demux_184, + int_demux_185, int_demux_186, int_demux_187, int_demux_188, int_demux_189, + int_demux_190, int_demux_191, int_demux_192, int_demux_193, int_demux_194, + int_demux_195, int_demux_196, int_demux_197, int_demux_198, int_demux_199, + int_demux_200, int_demux_201, int_demux_202, int_demux_203, int_demux_204, + int_demux_205, int_demux_206, int_demux_207, int_demux_208, int_demux_209, + int_demux_210, int_demux_211, int_demux_212, int_demux_213, int_demux_214, + int_demux_215, int_demux_216, int_demux_217, int_demux_218, int_demux_219, + int_demux_220, int_demux_221, int_demux_222, int_demux_223, int_demux_224, + int_demux_225, int_demux_226, int_demux_227, int_demux_228, int_demux_229, + int_demux_230, int_demux_231, int_demux_232, int_demux_233, int_demux_234, + int_demux_235, int_demux_236, int_demux_237, int_demux_238, int_demux_239, + int_demux_240, int_demux_241, int_demux_242, int_demux_243, int_demux_244, + int_demux_245, int_demux_246, int_demux_247, int_demux_248, int_demux_249, + int_demux_250, int_demux_251, int_demux_252, int_demux_253, int_demux_254, + int_demux_255, +}; diff --git a/arch/rx/include/kernel_arch_data.h b/arch/rx/include/kernel_arch_data.h new file mode 100644 index 00000000000..43762032f63 --- /dev/null +++ b/arch/rx/include/kernel_arch_data.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Private kernel definitions (rx) + * + * This file contains private kernel structures definitions and various + * other definitions for the Renesas rx architecture. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that kernel + * assembly source files obtains structure offset values via "absolute symbols" + * in the offsets.o module. + */ + +#ifndef ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ +#define ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ + +#include +#include +#include + +#ifndef _ASMLANGUAGE +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* place C-code here */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _ASMLANGUAGE */ + +#endif /* ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_DATA_H_ */ diff --git a/arch/rx/include/kernel_arch_func.h b/arch/rx/include/kernel_arch_func.h new file mode 100644 index 00000000000..70058fb5c96 --- /dev/null +++ b/arch/rx/include/kernel_arch_func.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ +#define ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ + +#ifndef _ASMLANGUAGE +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static ALWAYS_INLINE void arch_kernel_init(void) +{ + /* check if: further device initialization functions must be called here */ +} + +static inline bool arch_is_in_isr(void) +{ + return arch_curr_cpu()->nested != 0U; +} + +extern void z_rx_arch_switch(void *switch_to, void **switched_from); + +static inline void arch_switch(void *switch_to, void **switched_from) +{ + z_rx_arch_switch(switch_to, switched_from); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* ZEPHYR_ARCH_RX_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/rx/include/offsets_short_arch.h b/arch/rx/include/offsets_short_arch.h new file mode 100644 index 00000000000..796d4512b26 --- /dev/null +++ b/arch/rx/include/offsets_short_arch.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ +#define ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ + +#include + +/* kernel */ +#define KERNEL_OFFSET(field) _kernel_offset_to_##field + +#define _kernel_offset_to_flags (___kernel_t_arch_OFFSET + ___kernel_arch_t_flags_OFFSET) + +/* end - kernel */ + +/* threads */ +#define THREAD_OFFSET(field) _thread_offset_to_##field + +#define _thread_offset_to_sp (___thread_t_callee_saved_OFFSET + ___callee_saved_t_topOfStack_OFFSET) + +#define _thread_offset_to_retval (___thread_t_callee_saved_OFFSET + ___callee_saved_t_retval_OFFSET) + +#define _thread_offset_to_coopCoprocReg \ + (___thread_t_arch_OFFSET + ___thread_arch_t_coopCoprocReg_OFFSET) + +#define _thread_offset_to_preempCoprocReg \ + (___thread_t_arch_OFFSET + ___thread_arch_t_preempCoprocReg_OFFSET) + +#define _thread_offset_to_cpStack \ + (_thread_offset_to_preempCoprocReg + __tPreempCoprocReg_cpStack_OFFSET) + +#define _thread_offset_to_cpEnable (_thread_offset_to_cpStack + XT_CPENABLE) + +/* end - threads */ + +#endif /* ZEPHYR_ARCH_RX_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/arch/x86/core/CMakeLists.txt b/arch/x86/core/CMakeLists.txt index abbc052a624..c34c6909b01 100644 --- a/arch/x86/core/CMakeLists.txt +++ b/arch/x86/core/CMakeLists.txt @@ -27,6 +27,8 @@ zephyr_library_sources_ifdef(CONFIG_X86_VERY_EARLY_CONSOLE early_serial.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c) +zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) + if(CONFIG_X86_64) include(intel64.cmake) else() diff --git a/arch/x86/core/Kconfig.intel64 b/arch/x86/core/Kconfig.intel64 index 7b5359a7ecd..e1f5869c772 100644 --- a/arch/x86/core/Kconfig.intel64 +++ b/arch/x86/core/Kconfig.intel64 @@ -35,7 +35,6 @@ config ARCH_HAS_STACKWALK select DEBUG_INFO select THREAD_STACK_INFO depends on !OMIT_FRAME_POINTER - depends on NO_OPTIMIZATIONS help Internal config to indicate that the arch_stack_walk() API is implemented and it can be enabled. diff --git a/arch/x86/core/elf.c b/arch/x86/core/elf.c new file mode 100644 index 00000000000..a1660387d0e --- /dev/null +++ b/arch/x86/core/elf.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); + +#ifdef CONFIG_64BIT +#define R_X86_64_64 1 +#define R_X86_64_PC32 2 +#define R_X86_64_PLT32 4 +#define R_X86_64_32 10 +#define R_X86_64_32S 11 + +/** + * @brief Architecture specific function for relocating shared elf + * + * Elf files contain a series of relocations described in multiple sections. + * These relocation instructions are architecture specific and each architecture + * supporting modules must implement this. + * + * The relocation codes are well documented: + * + * https://refspecs.linuxfoundation.org/elf/x86_64-abi-0.95.pdf (intel64) + */ +int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, + const elf_shdr_t *shdr) +{ + int ret = 0; + const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); + elf_sym_t sym; + uintptr_t sym_base_addr; + const char *sym_name; + + ret = llext_read_symbol(ldr, ext, rel, &sym); + + if (ret != 0) { + LOG_ERR("Could not read symbol from binary!"); + return ret; + } + + sym_name = llext_symbol_name(ldr, ext, &sym); + + ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); + + if (ret != 0) { + LOG_ERR("Could not find symbol %s!", sym_name); + return ret; + } + + sym_base_addr += rel->r_addend; + + int reloc_type = ELF32_R_TYPE(rel->r_info); + + switch (reloc_type) { + case R_X86_64_PC32: + case R_X86_64_PLT32: + *(uint32_t *)loc = sym_base_addr - loc; + break; + case R_X86_64_64: + case R_X86_64_32: + case R_X86_64_32S: + *(uint32_t *)loc = sym_base_addr; + break; + default: + LOG_ERR("unknown relocation: %u\n", reloc_type); + ret = -ENOEXEC; + break; + } + + return ret; +} +#else +#define R_386_32 1 +#define R_286_PC32 2 + +/** + * @brief Architecture specific function for relocating shared elf + * + * Elf files contain a series of relocations described in multiple sections. + * These relocation instructions are architecture specific and each architecture + * supporting modules must implement this. + * + * The relocation codes are well documented: + * + * https://docs.oracle.com/cd/E19683-01/817-3677/chapter6-26/index.html (ia32) + */ +int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel, + const elf_shdr_t *shdr) +{ + int ret = 0; + const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel); + elf_sym_t sym; + uintptr_t sym_base_addr; + const char *sym_name; + + /* x86 uses elf_rel_t records with no addends */ + uintptr_t addend = *(uintptr_t *)loc; + + ret = llext_read_symbol(ldr, ext, rel, &sym); + + if (ret != 0) { + LOG_ERR("Could not read symbol from binary!"); + return ret; + } + + sym_name = llext_symbol_name(ldr, ext, &sym); + + ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr); + + if (ret != 0) { + LOG_ERR("Could not find symbol %s!", sym_name); + return ret; + } + + sym_base_addr += addend; + + int reloc_type = ELF32_R_TYPE(rel->r_info); + + switch (reloc_type) { + case R_386_32: + *(uint32_t *)loc = sym_base_addr; + break; + case R_286_PC32: + *(uint32_t *)loc = sym_base_addr - loc; + break; + default: + LOG_ERR("unknown relocation: %u\n", reloc_type); + ret = -ENOEXEC; + break; + } + + return ret; +} +#endif diff --git a/arch/x86/core/intel64/cpu.c b/arch/x86/core/intel64/cpu.c index 8d68afa2a19..31dbf060d6c 100644 --- a/arch/x86/core/intel64/cpu.c +++ b/arch/x86/core/intel64/cpu.c @@ -97,7 +97,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, */ FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot) { -#if defined(CONFIG_ACPI) +#if defined(CONFIG_ACPI) && !defined(CONFIG_ACRN_COMMON) __ASSERT(z_x86_cpuid_get_current_physical_apic_id() == x86_cpu_loapics[cpuboot->cpu_id], "APIC ID miss match!"); #endif diff --git a/arch/x86/core/intel64/smp.c b/arch/x86/core/intel64/smp.c index 90bd9724667..d6c18cec9e6 100644 --- a/arch/x86/core/intel64/smp.c +++ b/arch/x86/core/intel64/smp.c @@ -8,6 +8,7 @@ #include #include #include +#include #define NR_IRQ_VECTORS (IV_NR_VECTORS - IV_IRQS) /* # vectors free for IRQs */ diff --git a/arch/x86/core/prep_c.c b/arch/x86/core/prep_c.c index 96c76f6af26..2b371d8bfb1 100644 --- a/arch/x86/core/prep_c.c +++ b/arch/x86/core/prep_c.c @@ -61,7 +61,7 @@ FUNC_NORETURN void z_prep_c(void *arg) #ifdef CONFIG_X86_VERY_EARLY_CONSOLE z_x86_early_serial_init(); -#if defined(CONFIG_BOARD_QEMU_X86) || defined(CONFIG_BOARD_QEMU_X86_64) +#if defined(CONFIG_QEMU_TARGET) /* * Under QEMU and SeaBIOS, everything gets to be printed * immediately after "Booting from ROM.." as there is no newline. diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 19ce69b011b..143607a2295 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -226,6 +226,13 @@ config PRIVILEGED_STACK_SIZE # Must be multiple of CONFIG_MMU_PAGE_SIZE default 4096 +config XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP + bool "Flush all auto-refill data TLBs when swapping page tables" + depends on USERSPACE + help + This flushes (invalidates) all auto-refill data TLBs when page + tables are swapped. + endif # XTENSA_MMU endif # CPU_HAS_MMU diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index f3a4419f32c..e3d6025a91f 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -39,6 +39,17 @@ if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc") zephyr_library_sources(xcc_stubs.c) endif() +# ...where to find core-isa.h for custom compilation commands below. +if(CONFIG_SOC_FAMILY_ESPRESSIF_ESP32) + set(XTENSA_CONFIG_HAL_INCLUDE_DIR + -I${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/components/xtensa/${CONFIG_SOC}/include + ) +else() + set(XTENSA_CONFIG_HAL_INCLUDE_DIR + -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} + ) +endif() + add_subdirectory(startup) # This produces a preprocessed and regenerated (in the sense of gcc @@ -54,7 +65,7 @@ set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c) file(WRITE ${CORE_ISA_IN} "#include \n") add_custom_command(OUTPUT ${CORE_ISA_DM} COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ ${XTENSA_CORE_LOCAL_C_FLAG} - -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} + ${XTENSA_CONFIG_HAL_INCLUDE_DIR} -I${SOC_FULL_DIR} ${CORE_ISA_IN} -o ${CORE_ISA_DM}) @@ -98,7 +109,7 @@ set(HANDLERS ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_handlers) add_custom_command( OUTPUT ${HANDLERS}_tmp.c COMMAND ${CMAKE_C_COMPILER} -E -U__XCC__ - -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} + ${XTENSA_CONFIG_HAL_INCLUDE_DIR} -o ${HANDLERS}_tmp.c - < ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.tmpl) diff --git a/arch/xtensa/core/elf.c b/arch/xtensa/core/elf.c index 6b83a9c0c61..d16f51e61a2 100644 --- a/arch/xtensa/core/elf.c +++ b/arch/xtensa/core/elf.c @@ -52,8 +52,9 @@ static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, for (sh_ndx = 0; sh_ndx < ext->sect_cnt; sh_ndx++) { if (ext->sect_hdrs[sh_ndx].sh_addr <= *got_entry && *got_entry < - ext->sect_hdrs[sh_ndx].sh_addr + ext->sect_hdrs[sh_ndx].sh_size) + ext->sect_hdrs[sh_ndx].sh_addr + ext->sect_hdrs[sh_ndx].sh_size) { break; + } } if (sh_ndx == ext->sect_cnt) { diff --git a/arch/xtensa/core/gdbstub.c b/arch/xtensa/core/gdbstub.c index 0ebc9cc68cc..91a1d58f801 100644 --- a/arch/xtensa/core/gdbstub.c +++ b/arch/xtensa/core/gdbstub.c @@ -427,14 +427,14 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) struct xtensa_register *reg; int idx, num_laddr_regs; - uint32_t *bsa = *(int **)stack; + uint32_t *bsa = *(const int **)stack; - if ((int *)bsa - stack > 4) { - num_laddr_regs = 8; - } else if ((int *)bsa - stack > 8) { - num_laddr_regs = 12; - } else if ((int *)bsa - stack > 12) { + if (bsa - (const uint32_t *)stack > 12) { num_laddr_regs = 16; + } else if (bsa - (const uint32_t *)stack > 8) { + num_laddr_regs = 12; + } else if (bsa - (const uint32_t *)stack > 4) { + num_laddr_regs = 8; } else { num_laddr_regs = 4; } @@ -445,8 +445,7 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) if (reg->regno == SOC_GDB_REGNO_A1) { /* A1 is calculated */ - reg->val = POINTER_TO_UINT( - ((char *)bsa) + BASE_SAVE_AREA_SIZE); + reg->val = POINTER_TO_UINT(((char *)bsa) + sizeof(_xtensa_irq_bsa_t)); reg->seqno = ctx->seqno; } else { reg->val = bsa[reg->stack_offset / 4]; @@ -518,14 +517,14 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) struct xtensa_register *reg; int idx, num_laddr_regs; - _xtensa_irq_bsa_t *bsa = (void *)*(int **)stack; + _xtensa_irq_bsa_t *bsa = (void *)*(const int **)stack; - if ((int *)bsa - stack > 4) { - num_laddr_regs = 8; - } else if ((int *)bsa - stack > 8) { - num_laddr_regs = 12; - } else if ((int *)bsa - stack > 12) { + if ((uint32_t *)bsa - (const uint32_t *)stack > 12) { num_laddr_regs = 16; + } else if ((uint32_t *)bsa - (const uint32_t *)stack > 8) { + num_laddr_regs = 12; + } else if ((uint32_t *)bsa - (const uint32_t *)stack > 4) { + num_laddr_regs = 8; } else { num_laddr_regs = 4; } @@ -547,7 +546,7 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) /* Shouldn't be changing stack pointer */ continue; } else { - bsa[reg->stack_offset / 4] = reg->val; + ((uint32_t *)bsa)[reg->stack_offset / 4] = reg->val; } } @@ -559,7 +558,7 @@ static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) continue; } else if (reg->stack_offset != 0) { /* For those registers stashed in stack */ - bsa[reg->stack_offset / 4] = reg->val; + ((uint32_t *)bsa)[reg->stack_offset / 4] = reg->val; } else if (gdb_xtensa_is_special_reg(reg)) { /* * Currently not writing back any special diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c index fa7d4fb0f70..b66a9bc30f1 100644 --- a/arch/xtensa/core/ptables.c +++ b/arch/xtensa/core/ptables.c @@ -1122,4 +1122,20 @@ int arch_buffer_validate(const void *addr, size_t size, int write) return mem_buffer_validate(addr, size, write, XTENSA_MMU_USER_RING); } +#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP +/* This is only used when swapping page tables and auto-refill DTLBs + * needing to be invalidated. Otherwise, SWAP_PAGE_TABLE assembly + * is used to avoid a function call. + */ +void xtensa_swap_update_page_tables(struct k_thread *incoming) +{ + struct arch_mem_domain *domain = + &(incoming->mem_domain_info.mem_domain->arch); + + xtensa_mmu_set_paging(domain); + + xtensa_dtlb_autorefill_invalidate(); +} +#endif + #endif /* CONFIG_USERSPACE */ diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S index be143ed1f3a..56d53d59b0b 100644 --- a/arch/xtensa/core/userspace.S +++ b/arch/xtensa/core/userspace.S @@ -270,8 +270,12 @@ xtensa_userspace_enter: l32i a6, a1, 24 #ifdef CONFIG_XTENSA_MMU +#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP + call4 xtensa_swap_update_page_tables +#else SWAP_PAGE_TABLE a6, a3, a7 #endif +#endif #ifdef CONFIG_XTENSA_MPU call4 xtensa_mpu_map_write #endif diff --git a/arch/xtensa/core/xtensa_asm2_util.S b/arch/xtensa/core/xtensa_asm2_util.S index 6892831f52a..c488aeee1ce 100644 --- a/arch/xtensa/core/xtensa_asm2_util.S +++ b/arch/xtensa/core/xtensa_asm2_util.S @@ -251,8 +251,12 @@ xtensa_switch: rsr a6, ZSR_CPU l32i a6, a6, ___cpu_t_current_OFFSET #ifdef CONFIG_XTENSA_MMU +#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP + call4 xtensa_swap_update_page_tables +#else SWAP_PAGE_TABLE a6, a4, a7 #endif +#endif #ifdef CONFIG_XTENSA_MPU call4 xtensa_mpu_map_write #endif diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index 198f04f80e8..d7799ac1125 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -395,8 +395,12 @@ _xstack_call0_\@: l32i a6, a6, ___cpu_t_current_OFFSET #ifdef CONFIG_XTENSA_MMU +#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP + call4 xtensa_swap_update_page_tables +#else SWAP_PAGE_TABLE a6, a3, a7 #endif +#endif #ifdef CONFIG_XTENSA_MPU call4 xtensa_mpu_map_write #endif diff --git a/arch/xtensa/include/xtensa_mmu_priv.h b/arch/xtensa/include/xtensa_mmu_priv.h index b4491ff0bc3..7cd51f13293 100644 --- a/arch/xtensa/include/xtensa_mmu_priv.h +++ b/arch/xtensa/include/xtensa_mmu_priv.h @@ -364,6 +364,29 @@ static inline void xtensa_tlb_autorefill_invalidate(void) __asm__ volatile("isync"); } +/** + * @brief Invalidate all autorefill DTLB entries. + * + * This should be used carefully since all refill entries in the data + * TLBs are affected. The current stack page will be repopulated by + * this code as it returns. + */ +static inline void xtensa_dtlb_autorefill_invalidate(void) +{ + uint8_t way, i, entries; + + entries = BIT(XCHAL_DTLB_ARF_ENTRIES_LOG2); + + for (way = 0; way < XTENSA_MMU_NUM_TLB_AUTOREFILL_WAYS; way++) { + for (i = 0; i < entries; i++) { + uint32_t entry = way + (i << XTENSA_MMU_PTE_PPN_SHIFT); + + xtensa_dtlb_entry_invalidate(entry); + } + } + __asm__ volatile("isync"); +} + /** * @brief Set the page tables. * diff --git a/boards/96boards/stm32_sensor_mez/board.yml b/boards/96boards/stm32_sensor_mez/board.yml index 19d96543563..4011ccbd220 100644 --- a/boards/96boards/stm32_sensor_mez/board.yml +++ b/boards/96boards/stm32_sensor_mez/board.yml @@ -1,6 +1,6 @@ board: name: 96b_stm32_sensor_mez full_name: STM32 Sensor Mezzanine - vendor: st + vendor: 96boards socs: - name: stm32f446xx diff --git a/boards/acrn/acrn/Kconfig.defconfig b/boards/acrn/acrn/Kconfig.defconfig index 678c8a5e378..dbc4a23333c 100644 --- a/boards/acrn/acrn/Kconfig.defconfig +++ b/boards/acrn/acrn/Kconfig.defconfig @@ -5,6 +5,11 @@ config MP_MAX_NUM_CPUS default 2 -config HEAP_MEM_POOL_ADD_SIZE_ACPI +configdefault HEAP_MEM_POOL_ADD_SIZE_ACPI default 32768 - depends on ACPI + +configdefault MAIN_STACK_SIZE + default 32000 if ACPI + +configdefault SHELL_STACK_SIZE + default 32000 if SHELL && ACPI diff --git a/boards/acrn/acrn/acrn_adl_crb.dts b/boards/acrn/acrn/acrn_adl_crb.dts index c13054d3891..064b9d46231 100644 --- a/boards/acrn/acrn/acrn_adl_crb.dts +++ b/boards/acrn/acrn/acrn_adl_crb.dts @@ -4,4 +4,49 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "acrn.dts" +/dts-v1/; + +#include + +#define DT_DRAM_SIZE DT_SIZE_K(8192) +#define DT_DRAM_BASE 0 + +#include + +/ { + model = "ACRN"; + compatible = "acrn"; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + }; + + chosen { + zephyr,sram = &dram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + pcie0: pcie0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "pcie-controller"; + acpi-hid = "PNP0A03"; + ranges; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; + +&cpu { + compatible = "intel,x86_64"; +}; diff --git a/boards/acrn/acrn/acrn_adl_crb_defconfig b/boards/acrn/acrn/acrn_adl_crb_defconfig index de5dfe547e7..765fc7e3071 100644 --- a/boards/acrn/acrn/acrn_adl_crb_defconfig +++ b/boards/acrn/acrn/acrn_adl_crb_defconfig @@ -13,3 +13,6 @@ CONFIG_BUILD_OUTPUT_BIN=y CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n CONFIG_KERNEL_VM_SIZE=0x5000000 CONFIG_APIC_TSC_DEADLINE_TIMER=y +CONFIG_MP_MAX_NUM_CPUS=1 +CONFIG_ACPI=y +CONFIG_PCIE=y diff --git a/boards/acrn/acrn/board.yml b/boards/acrn/acrn/board.yml index 6efec2b876e..bb41da4f828 100644 --- a/boards/acrn/acrn/board.yml +++ b/boards/acrn/acrn/board.yml @@ -2,15 +2,18 @@ boards: - name: acrn full_name: ACRN hypervisor + vendor: acrn socs: - name: atom - name: acrn_ehl_crb full_name: ACRN on EHL hypervisor + vendor: acrn socs: - name: atom - name: acrn_adl_crb full_name: ACRN Hypervisor on ADL + vendor: acrn socs: - name: atom diff --git a/boards/actinius/icarus/actinius_icarus_common.dtsi b/boards/actinius/icarus/actinius_icarus_common.dtsi index 39616df663f..b44370babb1 100644 --- a/boards/actinius/icarus/actinius_icarus_common.dtsi +++ b/boards/actinius/icarus/actinius_icarus_common.dtsi @@ -170,4 +170,4 @@ #include "feather_connector.dtsi" /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi index 4d302d006fb..bd692cdc9ea 100644 --- a/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi @@ -157,4 +157,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi index 605b2bdd3e7..99eaab08dd3 100644 --- a/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi +++ b/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi @@ -66,4 +66,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi index f084595540f..c5ff38367b6 100644 --- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi @@ -159,4 +159,4 @@ neopixel_spi: &spi1 { #include "arduino_connector.dtsi" /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 index 63f45c11300..5baed3c43d4 100644 --- a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Philipp Steiner +# Copyright (c) 2025 Philipp Steiner # SPDX-License-Identifier: Apache-2.0 config BOARD_ADAFRUIT_FEATHER_ESP32S2 diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft index e54cad03d42..bdf0d84d47c 100644 --- a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Philipp Steiner +# Copyright (c) 2025 Philipp Steiner # SPDX-License-Identifier: Apache-2.0 config BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse index 1d470f87490..1025c63cf4d 100644 --- a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse +++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Philipp Steiner +# Copyright (c) 2025 Philipp Steiner # SPDX-License-Identifier: Apache-2.0 config BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE diff --git a/boards/adafruit/feather_esp32s2/Kconfig.defconfig b/boards/adafruit/feather_esp32s2/Kconfig.defconfig index 734863a6654..a2559a48619 100644 --- a/boards/adafruit/feather_esp32s2/Kconfig.defconfig +++ b/boards/adafruit/feather_esp32s2/Kconfig.defconfig @@ -1,4 +1,4 @@ -# Copyright (c) 2025 Philipp Steiner +# Copyright (c) 2025 Philipp Steiner # SPDX-License-Identifier: Apache-2.0 if BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT || BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi index a6c67847bbb..bd19e0ddc44 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner . + * Copyright (c) 2025 Philipp Steiner . * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts index e7e3f8efb7b..4cf4d79c29a 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay index 096357d93eb..0fdd649728b 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay index 94550a53acd..c8f08e5b344 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi index 257ea650a29..ae0eaf92ade 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts index c57ebdc8b8b..114a2d9cb91 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts index fbb4b0993ae..be28841df3a 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/board.c b/boards/adafruit/feather_esp32s2/board.c index e7f65a4ba53..aa4053f60fa 100644 --- a/boards/adafruit/feather_esp32s2/board.c +++ b/boards/adafruit/feather_esp32s2/board.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2024 Leon Rinkel - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/adafruit/feather_esp32s2/feather_connector.dtsi b/boards/adafruit/feather_esp32s2/feather_connector.dtsi index 8414fbbfb10..f4bfbc1c3b5 100644 --- a/boards/adafruit/feather_esp32s2/feather_connector.dtsi +++ b/boards/adafruit/feather_esp32s2/feather_connector.dtsi @@ -1,7 +1,7 @@ /* * Copyright (c) 2020 Richard Osterloh * Copyright (c) 2024 Leon Rinkel - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi index 3a2eb8c3e0d..a593471c787 100644 --- a/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi +++ b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi @@ -1,7 +1,7 @@ /* * Copyright (c) 2020 Richard Osterloh * Copyright (c) 2024 Leon Rinkel - * Copyright (c) 2025 Philipp Steiner + * Copyright (c) 2025 Philipp Steiner * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts index 4de11b92848..f291e50a806 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.dts +++ b/boards/adi/apard32690/apard32690_max32690_m4.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -82,6 +83,37 @@ <20 0 &gpio2 17 0>, /* D14 */ <21 0 &gpio2 18 0>; /* D15 */ }; + + pmod_header: pmod-header { + compatible = "digilent,pmod"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 0 0>, /* IO1/CS */ + <1 0 &gpio1 1 0>, /* IO2/MOSI */ + <2 0 &gpio1 2 0>, /* IO3/MISO */ + <3 0 &gpio1 3 0>, /* IO4/SCK */ + <4 0 &gpio2 21 0>, /* IO5/INT */ + <5 0 &gpio1 6 0>, /* IO6/RESET */ + <6 0 &gpio1 4 0>, /* IO7/CS2 */ + <7 0 &gpio1 5 0>; /* IO8/CS3 */ + }; + + sdram1: sdram1@60000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + status = "disabled"; + device_type = "memory"; + reg = <0x60000000 DT_SIZE_M(64)>; + zephyr,memory-region = "SDRAM1"; + }; + + sdram2: sdram2@70000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + status = "disabled"; + device_type = "memory"; + reg = <0x70000000 DT_SIZE_M(64)>; + zephyr,memory-region = "SDRAM2"; + }; }; &clk_ipo { @@ -227,3 +259,52 @@ pmod_spi: &spi4 { pinctrl-0 = <&owm_io_p0_8 &owm_pe_p0_7>; pinctrl-names = "default"; }; + +&hpb { + pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_cs1n_p1_17 &hyp_rwds_p1_14 + &hyp_d0_p1_12 &hyp_d1_p1_15 + &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13 + &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>; + pinctrl-names = "default"; + enable-emcc; + + mem@0 { + reg = <0>; + base-address = <0x60000000>; + device-type = ; + + latency-cycles = ; + read-cs-high = ; + write-cs-high = ; + read-cs-setup = ; + write-cs-setup = ; + read-cs-hold = ; + write-cs-hold = ; + + /* CR0 settings. Key setting is enabling 6-clock latency, since + * HPB doesn't support 7-clock latency which is default + */ + config-regs = <0x1000>; + config-reg-vals = <0x801F>; + }; + + mem@1 { + reg = <1>; + base-address = <0x70000000>; + device-type = ; + + latency-cycles = ; + read-cs-high = ; + write-cs-high = ; + read-cs-setup = ; + write-cs-setup = ; + read-cs-hold = ; + write-cs-hold = ; + + /* CR0 settings. Key setting is enabling 6-clock latency, since + * HPB doesn't support 7-clock latency which is default + */ + config-regs = <0x1000>; + config-reg-vals = <0x801F>; + }; +}; diff --git a/boards/adi/apard32690/apard32690_max32690_m4.yaml b/boards/adi/apard32690/apard32690_max32690_m4.yaml index bf6486d175b..ba9f690d054 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.yaml +++ b/boards/adi/apard32690/apard32690_max32690_m4.yaml @@ -11,11 +11,13 @@ supported: - arduino_serial - arduino_spi - pmod_spi + - pmod_gpio - gpio - serial - spi - trng - counter - w1 + - memc ram: 1024 flash: 3072 diff --git a/boards/adi/max32650evkit/max32650evkit.dts b/boards/adi/max32650evkit/max32650evkit.dts index 2292bfd8b8a..48d8e177a89 100644 --- a/boards/adi/max32650evkit/max32650evkit.dts +++ b/boards/adi/max32650evkit/max32650evkit.dts @@ -18,7 +18,7 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; + zephyr,sram = &sram4; zephyr,flash = &flash0; }; @@ -56,6 +56,7 @@ aliases { led0 = &led1; led1 = &led2; + watchdog0 = &wdt0; }; }; @@ -87,3 +88,27 @@ &gpio3 { status = "okay"; }; + +&dma0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_scl_p2_8 &i2c0_sda_p2_7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi2 { + status = "okay"; + pinctrl-0 = <&spi2_mosi_p2_4 &spi2_miso_p2_3 &spi2_sck_p2_2 &spi2_ss0_p2_5>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32650evkit/max32650evkit.yaml b/boards/adi/max32650evkit/max32650evkit.yaml index 8e3ced3c437..21b8ce3bfa0 100644 --- a/boards/adi/max32650evkit/max32650evkit.yaml +++ b/boards/adi/max32650evkit/max32650evkit.yaml @@ -9,5 +9,11 @@ toolchain: supported: - gpio - serial + - spi + - i2c + - dma + - watchdog + - counter + - rtc_counter ram: 1024 flash: 3072 diff --git a/boards/adi/max32650fthr/max32650fthr.dts b/boards/adi/max32650fthr/max32650fthr.dts index b471e2523ce..aa6fcf4e441 100644 --- a/boards/adi/max32650fthr/max32650fthr.dts +++ b/boards/adi/max32650fthr/max32650fthr.dts @@ -18,7 +18,7 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; + zephyr,sram = &sram4; zephyr,flash = &flash0; }; @@ -56,6 +56,7 @@ aliases { led0 = &led1; led1 = &led2; + watchdog0 = &wdt0; }; }; @@ -87,3 +88,21 @@ &gpio3 { status = "okay"; }; + +&dma0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_mosi_p1_29 &spi1_miso_p1_28 &spi1_sck_p1_26 &spi1_ss0_p1_23>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32650fthr/max32650fthr.yaml b/boards/adi/max32650fthr/max32650fthr.yaml index f967621e702..880af88f9c4 100644 --- a/boards/adi/max32650fthr/max32650fthr.yaml +++ b/boards/adi/max32650fthr/max32650fthr.yaml @@ -9,5 +9,11 @@ toolchain: supported: - gpio - serial + - spi + - i2c + - dma + - watchdog + - counter + - rtc_counter ram: 1024 flash: 3072 diff --git a/boards/adi/max32657evkit/Kconfig.defconfig b/boards/adi/max32657evkit/Kconfig.defconfig new file mode 100644 index 00000000000..dc6e2838d63 --- /dev/null +++ b/boards/adi/max32657evkit/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32657EVKIT + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +if BOARD_MAX32657EVKIT_MAX32657_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +# MAX32657 has one UART interface, +# It can be used either on TFM or Zephyr +# Enabling debug (TFM_SPM_LOG_LEVEL || TFM_PARTITION_LOG_LEVEL) will transfer it to the TFM side +# Disabling TFM debug will transfer it to the Zephyr side. + +choice TFM_SPM_LOG_LEVEL + default TFM_SPM_LOG_LEVEL_SILENCE +endchoice + +choice TFM_PARTITION_LOG_LEVEL + default TFM_PARTITION_LOG_LEVEL_SILENCE +endchoice + +endif # BOARD_MAX32657EVKIT_MAX32657_NS + +endif # BOARD_MAX32657EVKIT diff --git a/boards/adi/max32657evkit/Kconfig.max32657evkit b/boards/adi/max32657evkit/Kconfig.max32657evkit new file mode 100644 index 00000000000..c43a70cd6f7 --- /dev/null +++ b/boards/adi/max32657evkit/Kconfig.max32657evkit @@ -0,0 +1,6 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32657EVKIT + select SOC_MAX32657 if BOARD_MAX32657EVKIT_MAX32657 || \ + BOARD_MAX32657EVKIT_MAX32657_NS diff --git a/boards/adi/max32657evkit/board.cmake b/boards/adi/max32657evkit/board.cmake new file mode 100644 index 00000000000..ecf66679a23 --- /dev/null +++ b/boards/adi/max32657evkit/board.cmake @@ -0,0 +1,12 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_MAX32657EVKIT_MAX32657_NS) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +board_runner_args(jlink "--device=MAX32657" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32657evkit/board.yml b/boards/adi/max32657evkit/board.yml new file mode 100644 index 00000000000..6fa072a593c --- /dev/null +++ b/boards/adi/max32657evkit/board.yml @@ -0,0 +1,10 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32657evkit + vendor: adi + socs: + - name: max32657 + variants: + - name: "ns" diff --git a/boards/adi/max32657evkit/doc/img/max32657evkit.webp b/boards/adi/max32657evkit/doc/img/max32657evkit.webp new file mode 100644 index 00000000000..dfdd54a34da Binary files /dev/null and b/boards/adi/max32657evkit/doc/img/max32657evkit.webp differ diff --git a/boards/adi/max32657evkit/doc/index.rst b/boards/adi/max32657evkit/doc/index.rst new file mode 100644 index 00000000000..e96410f6a1e --- /dev/null +++ b/boards/adi/max32657evkit/doc/index.rst @@ -0,0 +1,575 @@ +.. zephyr:board:: max32657evkit + +Overview +******** + +The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an Arm® Cortex®-M33 core with single-precision floating point unit (FPU) +with digital signal processing (DSP) instructions, large flash and SRAM memories, +and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. +The nano-power modes increase battery life substantially. + +The MAX32657 is qualified to operate at a temperature range of -20°C to +85°C. +Bluetooth 5.4 LE radio supports Mesh, long-range (coded), and high-throughput modes. +A cryptographic toolbox (CTB) provides advanced root of trust security features, +including an Advanced Encryption Standard (AES) Engine, TRNG, and secure boot. +TrustZone is also included in the M33 Core. +Many high-speed interfaces are supported on the device, including multiple SPI, UART, +and I3C/I2C serial interfaces. +All interfaces support efficient DMA-driven transfers between peripheral and memory. + +The Zephyr port is running on the MAX32657 MCU. + +Hardware +******** + +- MAX32657 MCU: + + - Arm Cortex-M33 CPU with TrustZone® and FPU + - 1.2V to 1.6V Input Range for Integrated Boost DC-DC Converter + - 50MHz Low Power Oscillator + - External Crystal Support + + - 32MHz required for BLE + + - 1MB Internal Flash with ECC + - 256kB Internal SRAM + - 8kB Cache + - 32.768kHz RTC external crystal + + - Typical Electrical Characteristics + + - ACTIVE: 50μA/MHz Arm Cortex-M33 Running Coremark (50MHz) + + - Bluetooth 5.4 LE Radio + + - Rx Sensitivity: -96dBm; Tx Power: +4.5dBm + - 15mW Tx Power at 0dBm at 1.5Vin + - 14mW Rx Power at 1.5Vin + - Single-Ended Antenna Connection (50Ω) + - Supports 802.15.4, and LE Audio + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + + - Optimal Peripheral Mix Provides Platform Scalability + + - 2 DMA Controllers (Secure and non-Secure) + - One SPI Controller/Peripheral + - One I2C/I3C + - 1 Low-Power UART (LPUART) + - Six 32-Bit Low Power Timers with PWM + - 14 Configurable GPIO with Internal Pullup/Pulldown Resistors + + - Cryptographic Tool Box (CTB) for IP/Data Security + + - True Random Number Generator (TRNG) + - AES-128/192/256 + - Unique ID + + - Secure Boot ROM + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | VLDO SEL | | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Sets the LDO output used for system power according to the value of resistor R4. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | Sets the LDO output used for system power to 1.2V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | Sets the LDO output used for system power to 1.5V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Sets the LDO output used for system power to 1.6V. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | VIN SEL | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | VIN Powered from LDO. (USB Type-C connector is board's power source) | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 2-3 | | | VIN Powered from Battery | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | VIN EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the board's power source to system power by connecting VIN to VSYS_IN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power by disconnecting VIN from VSYS_IN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | VDD12 EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects system power to the MAX32657 by connecting VDD12 to VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power from the MAX32657 by disconnecting VDD12 from VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | VTREF EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects a reference voltage to the OBD circuit. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects a reference voltage from the OBD circuit. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | OBD VBUS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the OBD by connecting OBD_VBUS to VBUS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the OBD by disconnecting OBD_VBUS from VBUS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| J7 | VSYS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects system power to all peripherals by connecting VSYS to VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power to all peripherals by disconnecting VSYS from VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | ACC VS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the accelerometer by connecting its supply voltage pin VS to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the accelerometer by disconnecting its supply voltage pin VS from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | ACC VDD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the accelerometer by connecting its VDDIO pin to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the accelerometer by disconnecting its VDDIO pin from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | ACC I2C EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Accelerometer SDA Pin is connected to MAX32657 I2C0_SDA. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Accelerometer SDA Pin is disconnected from MAX32657 I2C0_SDA. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | ACC I2C EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Accelerometer SCL Pin is connected to MAX32657 I2C0_SCL. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Accelerometer SCL Pin is disconnected from MAX32657 I2C0_SCL. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | BYP MAG SW | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Bypass Magnetic Switch. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Enables magnetic switch. The output of the switch is controlled by the AFE pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | LOCK RSTN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | AFE Lock Pin is connected to MAX32657 RSTN pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | AFE Lock Pin is disconnected from MAX32657 RSTN pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | LATCH CTRL | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the AFE (LOCK) to the magnetic switch (OUTPUT LATCH CONTROL). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the AFE (WAKE) to the magnetic switch (OUTPUT LATCH CONTROL). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | AFE EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the AFE (VBAT) by connecting it to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the AFE (VBAT) by disconnecting it from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | AFE SPI EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | AFE CSB is connected to MAX32657 SPI0_CS0. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | AFE SDI is connected to MAX32657 SPI0_MOSI. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | AFE SCLK is connected to MAX32657 SPI0_SCK. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | AFE SDO is connected to MAX32657 SPI0_MISO. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | AFE INTB is connected to MAX32657 P0.7. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 11-12 | | | AFE GPIO2 is connected to MAX32657 P0.8. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open All | | | Disconnect SPI Interface from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | I2C PU EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enable SCL PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable SCL PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | I2C PU EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enable SDA PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable SDA PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | OBD SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | OBD SWDIO is connected to the MAX32657 SWDIO. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | OBD SWCLK is connected to the MAX32657 SWCLK. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | OBD JTAG TDO Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | OBD JTAG TDI Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 11-12 | | | OBD RSTN is connected to the MAX32657 RSTN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 13-14 | | | OBD JTAG TRST Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open All | | | Disable OBD SWD Connection from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | OBD VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | OBD VCOM TXD is connected VCOM EN RX Jumper. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | OBD VCOM RXD is connected VCOM EN TX Jumper. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | OBD VCOM CTS Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | OBD VCOM RTS Enable Jumper (It's not used on MAX32657). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable OBD VCOM connection from MAX32657. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects OBD VCOM RXD to the MAX32657 UART0A_TX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects OBD VCOM RXD from the MAX32657 UART0A_TX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects OBD VCOM TXD to the MAX32657 UART0A_RX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects OBD VCOM TXD from the MAX32657 UART0A_RX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | EXT SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects EXT SWD Connector Data Signals to the MAX32657 SWDIO pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects EXT SWD Connector Data Signals from the MAX32657 SWDIO pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | EXT SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects EXT SWD Connector Clock Signals to the MAX32657 SWDCLK pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects EXT SWD Connector Clock Signals from the MAX32657 SWDCLK pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Zephyr board options +******************** + +The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an ARM Cortex-M33 architecture that provides Trustzone technology +which allow define secure and non-secure application. +Zephyr provides support for building for both Secure (S) and Non-Secure (NS) firmware. + +The BOARD options are summarized below: + ++-------------------------------+-------------------------------------------+ +| BOARD | Description | ++===============================+===========================================+ +| max32657evkit/max32657 | For building Trust Zone Disabled firmware | ++-------------------------------+-------------------------------------------+ +| max32657evkit/max32657/ns | Building with TF-M (includes NS+S images) | ++-------------------------------+-------------------------------------------+ + + +BOARD: max32657evkit/max32657 +============================= + +Build the zephyr app for ``max32657evkit/max32657`` board target will generate secure firmware +for zephyr. In this configuration 960KB of flash is used to store the code and 64KB +is used for storage section. In this mode tf-m is off and secure mode flag is on +(:kconfig:option:`CONFIG_TRUSTED_EXECUTION_SECURE` to ``y`` and +:kconfig:option:`CONFIG_BUILD_WITH_TFM` to ``n``) + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| slot0 | 0x1000000[960k] | Secure zephyr image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | File system, persistent storage | ++----------+------------------+---------------------------------+ + +Here are the instructions to build zephyr with a secure configuration, +using :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: max32657evkit/max32657 + :goals: build + + +BOARD: max32657evkit/max32657/ns +================================ + +The ``max32657evkit/max32657/ns`` board target is used to build the secure firmware +image using TF-M (:kconfig:option:`CONFIG_BUILD_WITH_TFM` to ``y``) and +the non-secure firmware image using Zephyr +(:kconfig:option:`CONFIG_TRUSTED_EXECUTION_NONSECURE` to ``y``). + +Here are the instructions to build zephyr with a non-secure configuration, +using :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: max32657evkit/max32657/ns + :goals: build + +The above command will: + * Build a bootloader image (MCUboot) + * Build a TF-M (secure) firmware image + * Build Zephyr application as non-secure firmware image + * Merge them as ``tfm_merged.hex`` which contain all images. + + +Note: + +Zephyr build TF-M with :kconfig:option:`CONFIG_TFM_PROFILE_TYPE_NOT_SET` mode +that meet most use case configuration especially for BLE related applications. +if TF-M small profile meet your application requirement you can set TF-M profile as small +:kconfig:option:`CONFIG_TFM_PROFILE_TYPE_SMALL` to ``y`` to decrease TF-M RAM and flash use. + + +Memory mappings +--------------- + +MAX32657 1MB flash and 256KB RAM split to define section for MCUBoot, +TF-M (S), Zephyr (NS) and storage that used for secure services and configurations. +Default layout of MAX32657 is listed in below table. + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| boot | 0x1000000[64K] | MCU Bootloader | ++----------+------------------+---------------------------------+ +| slot0 | 0x1010000[320k] | Secure image slot0 (TF-M) | ++----------+------------------+---------------------------------+ +| slot0_ns | 0x1060000[576k] | Non-secure image slot0 (Zephyr) | ++----------+------------------+---------------------------------+ +| slot1 | 0x10F0000[0k] | Updates slot0 image | ++----------+------------------+---------------------------------+ +| slot1_ns | 0x10F0000[0k] | Updates slot0_ns image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | Persistent storage | ++----------+------------------+---------------------------------+ + + ++----------------+------------------+-------------------+ +| RAM | Address[Size] | Comment | ++================+==================+===================+ +| secure_ram | 0x20000000[64k] | Secure memory | ++----------------+------------------+-------------------+ +| non_secure_ram | 0x20010000[192k] | Non-Secure memory | ++----------------+------------------+-------------------+ + + +Flash memory layout are defines both on zephyr board file and `Trusted Firmware M`_ (TF-M) project +these definition shall be match. Zephyr defines it in +:zephyr_file:`boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi` +file under flash section. TF-M project define them in +../modules/tee/tf-m/trusted-firmware-m/platform/ext/target/adi/max32657/partition/flash_layout.h file.` +If you would like to update flash region for your application you shall update related section in +these files. + +Additionally if firmware update feature requires slot1 and slot1_ns section need to be +defined. On default the section size set as 0 due to firmware update not requires on default. + + +Peripherals and Memory Ownership +-------------------------------- + +The ARM Security Extensions model allows system developers to partition device hardware and +software resources, so that they exist in either the Secure world for the security subsystem, +or the Normal world for everything else. Correct system design can ensure that no Secure world +assets can be accessed from the Normal world. A Secure design places all sensitive resources +in the Secure world, and ideally has robust software running that can protect assets against +a wide range of possible software attacks (`1`_). + +MPC (Memory Protection Controller) and PPC (Peripheral Protection Controller) are allow to +protect memory and peripheral. Incase of need peripheral and flash ownership can be updated in +../modules/tee/tf-m/trusted-firmware-m/platform/ext/target/adi/max32657/s_ns_access.cmake` +file by updating cmake flags to ON/OFF. + +As an example for below configuration TRNG, SRAM_0 and SRAM_1 is not going to be accessible +by non-secure. All others is going to be accessible by NS world. + +.. code-block:: + + set(ADI_NS_PRPH_GCR ON CACHE BOOL "") + set(ADI_NS_PRPH_SIR ON CACHE BOOL "") + set(ADI_NS_PRPH_FCR ON CACHE BOOL "") + set(ADI_NS_PRPH_WDT ON CACHE BOOL "") + set(ADI_NS_PRPH_AES OFF CACHE BOOL "") + set(ADI_NS_PRPH_AESKEY OFF CACHE BOOL "") + set(ADI_NS_PRPH_CRC ON CACHE BOOL "") + set(ADI_NS_PRPH_GPIO0 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER0 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER1 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER2 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER3 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER4 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER5 ON CACHE BOOL "") + set(ADI_NS_PRPH_I3C ON CACHE BOOL "") + set(ADI_NS_PRPH_UART ON CACHE BOOL "") + set(ADI_NS_PRPH_SPI ON CACHE BOOL "") + set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") + set(ADI_NS_PRPH_BTLE_DBB ON CACHE BOOL "") + set(ADI_NS_PRPH_BTLE_RFFE ON CACHE BOOL "") + set(ADI_NS_PRPH_RSTZ ON CACHE BOOL "") + set(ADI_NS_PRPH_BOOST ON CACHE BOOL "") + set(ADI_NS_PRPH_BBSIR ON CACHE BOOL "") + set(ADI_NS_PRPH_BBFCR ON CACHE BOOL "") + set(ADI_NS_PRPH_RTC ON CACHE BOOL "") + set(ADI_NS_PRPH_WUT0 ON CACHE BOOL "") + set(ADI_NS_PRPH_WUT1 ON CACHE BOOL "") + set(ADI_NS_PRPH_PWR ON CACHE BOOL "") + set(ADI_NS_PRPH_MCR ON CACHE BOOL "") + + # SRAMs + set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_2 ON CACHE BOOL "Size: 64KB") + set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") + set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") + + # Ramfuncs section size + set(ADI_S_RAM_CODE_SIZE "0x800" CACHE STRING "Default: 2KB") + + # Flash: BL2, TFM and Zephyr are contiguous sections. + set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") + set(ADI_FLASH_S_PARTITION_SIZE "0x50000" CACHE STRING "Default: 320KB") + set(ADI_FLASH_NS_PARTITION_SIZE "0x90000" CACHE STRING "Default: 576KB") + set(ADI_FLASH_PS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") + set(ADI_FLASH_ITS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") + + # + # Allow user set S-NS resources ownership by overlay file + # + if(EXISTS "${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake") + include(${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake) + endif() + + +As an alternative method (which recommended) user can configurate ownership peripheral by +an cmake overlay file too without touching TF-M source files. For this path +create ``s_ns_access_overlay.cmake`` file under your project root folder and put peripheral/memory +you would like to be accessible by secure world. + +As an example if below configuration files been put in the ``s_ns_access_overlay.cmake`` file +TRNG, SRAM_0 and SRAM_1 will be accessible by secure world only. + +.. code-block:: + + set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") + set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32657evkit/max32657 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32657evkit/max32657 + +Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| +---------------------------------------------------------------------- +The TF-M integration samples can be run using the +``max32657evkit/max32657/ns`` board target. To run we need to manually flash +the resulting image (``tfm_merged.hex``) with a J-Link as follows +(reset and erase are for recovering a locked core): + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32657evkit/max32657/ns + :goals: build + +.. code-block:: console + + west flash --hex-file build/zephyr/tfm_merged.hex + +.. code-block:: console + + [INF] Starting bootloader + [WRN] This device was provisioned with dummy keys. This device is NOT SECURE + [INF] PSA Crypto init done, sig_type: RSA-3072 + [WRN] Cannot upgrade: slots have non-compatible sectors + [WRN] Cannot upgrade: slots have non-compatible sectors + [INF] Bootloader chainload address offset: 0x10000 + [INF] Jumping to the first image slot + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32657evkit/max32657/ns + + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32657evkit/max32657 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32657evkit/max32657 + +References +********** + +.. _1: + https://developer.arm.com/documentation/100935/0100/The-TrustZone-hardware-architecture- + +.. _Trusted Firmware M: + https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html diff --git a/boards/adi/max32657evkit/max32657evkit_max32657.dts b/boards/adi/max32657evkit/max32657evkit_max32657.dts new file mode 100644 index 00000000000..7cee4e11277 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "max32657evkit_max32657_common.dtsi" + +/ { + chosen { + zephyr,sram = &secure_ram; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + secure_ram: partition@30000000 { + label = "secure-memory"; + reg = <0x30000000 DT_SIZE_K(256)>; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(960)>; + read-only; + }; + + storage_partition: partition@f0000 { + label = "storage"; + reg = <0xf0000 DT_SIZE_K(64)>; + }; + }; +}; + +&trng { + status = "okay"; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657.yaml b/boards/adi/max32657evkit/max32657evkit_max32657.yaml new file mode 100644 index 00000000000..8290aa1fdd5 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657.yaml @@ -0,0 +1,14 @@ +identifier: max32657evkit/max32657 +name: max32657evkit-max32657 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - serial + - gpio + - trng +ram: 256 +flash: 960 diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi b/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi new file mode 100644 index 00000000000..5bc950bc167 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_common.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32657EVKIT"; + compatible = "adi,max32657evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + pb1: pb1 { + gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + sw0 = &pb1; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_p0_9 &uart0_rx_p0_5>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_defconfig b/boards/adi/max32657evkit/max32657evkit_max32657_defconfig new file mode 100644 index 00000000000..25ef03ee513 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# It is secure fw, enable flags +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts b/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts new file mode 100644 index 00000000000..a8e9369eeed --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_ns.dts @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "max32657evkit_max32657_common.dtsi" + +/ { + chosen { + zephyr,sram = &non_secure_ram; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_ns_partition; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* RAM split used by TFM */ + secure_ram: partition@20000000 { + label = "secure-memory"; + reg = <0x20000000 DT_SIZE_K(64)>; + }; + + non_secure_ram: partition@20010000 { + label = "non-secure-memory"; + reg = <0x20010000 DT_SIZE_K(192)>; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(320)>; + }; + + slot0_ns_partition: partition@60000 { + label = "image-0-nonsecure"; + reg = <0x60000 DT_SIZE_K(576)>; + }; + + /* + * slot1_partition: partition@f0000 { + * label = "image-1"; + * reg = <0xf0000 DT_SIZE_K(0)>; + * }; + * slot1_ns_partition: partition@f0000 { + * label = "image-1-nonsecure"; + * reg = <0xf0000 DT_SIZE_K(0)>; + * }; + */ + + storage_partition: partition@f0000 { + label = "storage"; + reg = <0xf0000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml b/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml new file mode 100644 index 00000000000..82703d9e354 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml @@ -0,0 +1,13 @@ +identifier: max32657evkit/max32657/ns +name: max32657evkit-max32657-Non-Secure +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - serial + - gpio +ram: 192 +flash: 576 diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig b/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig new file mode 100644 index 00000000000..d808f79c545 --- /dev/null +++ b/boards/adi/max32657evkit/max32657evkit_max32657_ns_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# It is non-secure fw, enable flags +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Set TFM and Zephyr sign key +CONFIG_TFM_MCUBOOT_SIGNATURE_TYPE="RSA-3072" diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts index 132f29f3041..8e2aabb71f8 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -95,6 +96,30 @@ mosi-gpios = <&gpio2 24 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; cs-gpios = <&gpio2 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; }; + + sdram1: sdram1@60000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + status = "disabled"; + device_type = "memory"; + reg = <0x60000000 DT_SIZE_M(8)>; + zephyr,memory-region = "SDRAM1"; + }; +}; + +&hpb { + pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_rwds_p1_14 &hyp_d0_p1_12 &hyp_d1_p1_15 + &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13 + &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>; + pinctrl-names = "default"; + enable-emcc; + + mem@0 { + reg = <0>; + base-address = <0x60000000>; + device-type = ; + config-regs = <1>; + config-reg-vals = <2>; + }; }; &clk_ipo { diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml index 8278d3fe168..83c03c9715d 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml @@ -21,5 +21,6 @@ supported: - w1 - flash - usbd + - memc ram: 1024 flash: 3072 diff --git a/boards/adi/max32690fthr/doc/max32690fthr.webp b/boards/adi/max32690fthr/doc/max32690fthr.webp new file mode 100644 index 00000000000..cf4062dcbe9 Binary files /dev/null and b/boards/adi/max32690fthr/doc/max32690fthr.webp differ diff --git a/boards/aesc/elemrv/Kconfig.elemrv b/boards/aesc/elemrv/Kconfig.elemrv new file mode 100644 index 00000000000..9c22c252583 --- /dev/null +++ b/boards/aesc/elemrv/Kconfig.elemrv @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Aesc Silicon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ELEMRV + select SOC_ELEMRV_N diff --git a/boards/aesc/elemrv/board.yml b/boards/aesc/elemrv/board.yml new file mode 100644 index 00000000000..8a4890dd13a --- /dev/null +++ b/boards/aesc/elemrv/board.yml @@ -0,0 +1,6 @@ +board: + name: elemrv + full_name: ElemRV-N + vendor: aesc + socs: + - name: elemrv_n diff --git a/boards/aesc/elemrv/doc/index.rst b/boards/aesc/elemrv/doc/index.rst new file mode 100644 index 00000000000..cae642e0a27 --- /dev/null +++ b/boards/aesc/elemrv/doc/index.rst @@ -0,0 +1,72 @@ +.. zephyr:board:: elemrv + +Overview +******** + +ElemRV-N is an end-to-end open-source RISC-V microcontroller designed using SpinalHDL. + +Version 0.2 of ElemRV-N was successfully fabricated using `IHP's Open PDK`_, a 130nm open semiconductor process, with support from `FMD-QNC`_. + +For more details, refer to the official `GitHub Project`_. + +.. note:: + The currently supported silicon version is ElemRV-N 0.2. + +Supported Features +****************** + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The system clock for the RISC-V core is set to 20 MHz. This value is specified in the ``cpu0`` devicetree node using the ``clock-frequency`` property. + +CPU +=== + +ElemRV-N integrates a VexRiscv RISC-V core featuring a 5-stage pipeline and the following ISA extensions: + +* M (Integer Multiply/Divide) +* C (Compressed Instructions) + +It also includes the following general-purpose ``Z`` extensions: + +* Zicntr – Base Counter and Timer extensions +* Zicsr – Control and Status Register operations +* Zifencei – Instruction-fetch fence + +The complete ISA string for this CPU is: ``RV32IMC_Zicntr_Zicsr_Zifencei`` + +Hart-Level Interrupt Controller (HLIC) +====================================== + +Each CPU core is equipped with a Hart-Level Interrupt Controller, configurable through Control and Status Registers (CSRs). + +Machine Timer +============= + +A RISC-V compliant machine timer is enabled by default. + +Serial +====== + +The UART (Universal Asynchronous Receiver-Transmitter) interface is a configurable serial communication peripheral used for transmitting and receiving data. + +By default, ``uart0`` operates at a baud rate of ``115200``, which can be adjusted via the elemrv device tree. + +To evaluate the UART interface, build and run the following sample: + +.. zephyr-app-commands:: + :board: elemrv/elemrv_n + :zephyr-app: samples/hello_world + :goals: build + +.. _GitHub Project: + https://github.com/aesc-silicon/elemrv + +.. _IHP's Open PDK: + https://github.com/IHP-GmbH/IHP-Open-PDK + +.. _FMD-QNC: + https://www.elektronikforschung.de/projekte/fmd-qnc diff --git a/boards/aesc/elemrv/elemrv_elemrv_n.dts b/boards/aesc/elemrv/elemrv_elemrv_n.dts new file mode 100644 index 00000000000..4b9ea13bf84 --- /dev/null +++ b/boards/aesc/elemrv/elemrv_elemrv_n.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2025 Aesc Silicon + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "ElemRV-N"; + compatible = "aesc,elemrv-n"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &hyperbus; + zephyr,flash = &flash; + }; + + soc { + ocram: memory@80000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x80000000 DT_SIZE_K(1)>; + }; + + hyperbus: memory@90000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x90000000 DT_SIZE_K(32)>; + }; + + flash: flash@a0010000 { + compatible = "soc-nv-flash"; + reg = <0xa0010000 DT_SIZE_K(32)>; + }; + }; +}; + +&uart0 { + clock-frequency = ; + current-speed = <115200>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = ; +}; diff --git a/boards/aesc/elemrv/elemrv_elemrv_n.yaml b/boards/aesc/elemrv/elemrv_elemrv_n.yaml new file mode 100644 index 00000000000..4c9c3a99174 --- /dev/null +++ b/boards/aesc/elemrv/elemrv_elemrv_n.yaml @@ -0,0 +1,9 @@ +identifier: elemrv/elemrv_n +name: ElemRV-N +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +ram: 32 +flash: 32 diff --git a/boards/aesc/elemrv/elemrv_elemrv_n_defconfig b/boards/aesc/elemrv/elemrv_elemrv_n_defconfig new file mode 100644 index 00000000000..ac046a3cbbc --- /dev/null +++ b/boards/aesc/elemrv/elemrv_elemrv_n_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Aesc Silicon +# SPDX-License-Identifier: Apache-2.0 + +# Serial Driver +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/aesc/index.rst b/boards/aesc/index.rst new file mode 100644 index 00000000000..2471cc5acc0 --- /dev/null +++ b/boards/aesc/index.rst @@ -0,0 +1,10 @@ +.. _boards-aesc: + +Aesc Silicon +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f b/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f new file mode 100644 index 00000000000..9c4fa2f57d7 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/Kconfig.ai_wb2_12f @@ -0,0 +1,6 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_AI_WB2_12F + select SOC_BL602C00Q2I diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi b/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi new file mode 100644 index 00000000000..2ca49209287 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f-pinctrl.dtsi @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = , + ; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + pinmux = , + ; + bias-high-impedance; + }; + }; +}; diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts new file mode 100644 index 00000000000..d3e99d7a45f --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ai_wb2_12f-pinctrl.dtsi" + +/ { + model = "Ai-Thinker WB2-12F development board"; + compatible = "bflb,bl602"; + + chosen { + zephyr,flash = &flash0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000b000 0x1000 0x23000000 0x400000>; + + flash0: flash@0 { + compatible = "zb,25vq32", "jedec,spi-nor"; + status = "disabled"; + size = ; + jedec-id = [5e 40 16]; + reg = <0>; + spi-max-frequency = ; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml new file mode 100644 index 00000000000..e7c5a4dc59e --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: ai_wb2_12f +name: Ai-Thinker WB2-12F development board +type: mcu +arch: riscv +ram: 64 +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth +supported: + - pinctrl + - uart +vendor: bflb diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig b/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig new file mode 100644 index 00000000000..7836442f7c4 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_UART_CONSOLE=y diff --git a/boards/aithinker/ai_wb2_12f/board.cmake b/boards/aithinker/ai_wb2_12f/board.cmake new file mode 100644 index 00000000000..82839f83894 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/board.cmake @@ -0,0 +1,25 @@ +# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space) +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]") + +board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") +board_runner_args(openocd --gdb-init "set architecture riscv:rv32") +board_runner_args(openocd --gdb-init "set remotetimeout 250") +board_runner_args(openocd --gdb-init "set print asm-demangle on") +board_runner_args(openocd --gdb-init "set backtrace limit 32") +board_runner_args(openocd --gdb-init "mem 0x22008000 0x22014000 rw") +board_runner_args(openocd --gdb-init "mem 0x42008000 0x42014000 rw") +board_runner_args(openocd --gdb-init "mem 0x22014000 0x22020000 rw") +board_runner_args(openocd --gdb-init "mem 0x42014000 0x42020000 rw") +board_runner_args(openocd --gdb-init "mem 0x22020000 0x2203C000 rw") +board_runner_args(openocd --gdb-init "mem 0x42020000 0x4203C000 rw") +board_runner_args(openocd --gdb-init "mem 0x23000000 0x23400000 ro") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(bflb_mcu_tool --chipname bl602) +include(${ZEPHYR_BASE}/boards/common/bflb_mcu_tool.board.cmake) + +board_set_flasher(bflb_mcu_tool) diff --git a/boards/aithinker/ai_wb2_12f/board.yml b/boards/aithinker/ai_wb2_12f/board.yml new file mode 100644 index 00000000000..fad47a56aff --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/board.yml @@ -0,0 +1,6 @@ +board: + name: ai_wb2_12f + full_name: Ai-Thinker WB2-12F development board + vendor: aithinker + socs: + - name: bl602c00q2i diff --git a/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp b/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp new file mode 100644 index 00000000000..ae6ef3f02dc Binary files /dev/null and b/boards/aithinker/ai_wb2_12f/doc/img/ai_wb2_12f.webp differ diff --git a/boards/aithinker/ai_wb2_12f/doc/index.rst b/boards/aithinker/ai_wb2_12f/doc/index.rst new file mode 100644 index 00000000000..b68fc820bbc --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/doc/index.rst @@ -0,0 +1,105 @@ +.. zephyr:board:: ai_wb2_12f + +Overview +******** + +BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used +for low power consumption and high performance application development. The +wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0 +baseband/MAC design. The microcontroller subsystem includes a 32-bit RISC CPU +with low power consumption, cache and memory. The power management unit +controls the low power consumption mode. In addition, it also supports +various security features. The external interfaces include SDIO, SPI, UART, +I2C, IR remote, PWM, ADC, DAC, PIR and GPIO. + +This WB2 (BL602) 12F format Module Development Board features a SiFive E24 32 bit +RISC-V CPU with FPU, it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM, +2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0 +with 2MB phy. It is a secure MCU which supports Secure boot, ECC-256 signed +image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key +Accelerator). + +Hardware +******** + +For more information about the Bouffalo Lab BL-60x MCU: + +- `Bouffalo Lab BL60x MCU Website`_ +- `Bouffalo Lab BL60x MCU Datasheet`_ +- `Bouffalo Lab Development Zone`_ +- `ai_wb2_12f Schematics`_ +- `The RISC-V BL602 Book`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The WB2 (BL602) Development Board is configured to run at max speed (192MHz). + +Serial Port +=========== + +The ``ai_wb2_12f`` board uses UART0 as default serial port. It is connected +to USB Serial converter and port is used for both program and console. + + +Programming and Debugging +************************* + +Samples +======= + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample +application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ai_wb2_12f + :goals: build flash + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ screen /dev/ttyUSB0 115200 + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Then, press and release RST button + + .. code-block:: console + + *** Booting Zephyr OS build v4.1.0 *** + Hello World! ai_wb2_12f/bl602c00q2i + +Congratulations, you have ``ai_wb2_12f`` configured and running Zephyr. + + +.. _Bouffalo Lab BL60x MCU Website: + https://en.bouffalolab.com/product/?type=detail&id=6 + +.. _Bouffalo Lab BL60x MCU Datasheet: + https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en + +.. _Bouffalo Lab Development Zone: + https://dev.bouffalolab.com/home?id=guest + +.. _ai_wb2_12f Schematics: + https://docs.ai-thinker.com/en/wb2 + +.. _The RISC-V BL602 Book: + https://lupyuen.github.io/articles/book + +.. _Flashing Firmware to BL602: + https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/support/bl60x.cfg b/boards/aithinker/ai_wb2_12f/support/bl60x.cfg similarity index 100% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/support/bl60x.cfg rename to boards/aithinker/ai_wb2_12f/support/bl60x.cfg diff --git a/boards/aithinker/ai_wb2_12f/support/openocd.cfg b/boards/aithinker/ai_wb2_12f/support/openocd.cfg new file mode 100644 index 00000000000..9a3b1644e96 --- /dev/null +++ b/boards/aithinker/ai_wb2_12f/support/openocd.cfg @@ -0,0 +1,5 @@ +# For WCH linkE in DAP mode + +interface cmsis-dap + +adapter speed 1000 diff --git a/boards/aithinker/index.rst b/boards/aithinker/index.rst new file mode 100644 index 00000000000..cdefd628132 --- /dev/null +++ b/boards/aithinker/index.rst @@ -0,0 +1,10 @@ +.. _boards-aithinker: + +Ai-Thinker Co. +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/altr/index.rst b/boards/altr/index.rst deleted file mode 100644 index 83220f8c905..00000000000 --- a/boards/altr/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-altera: - -Altera Corporation -################## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/altr/max10/Kconfig.altera_max10 b/boards/altr/max10/Kconfig.altera_max10 deleted file mode 100644 index b0b39da8448..00000000000 --- a/boards/altr/max10/Kconfig.altera_max10 +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -config BOARD_ALTERA_MAX10 - select SOC_ZEPHYR_NIOS2F diff --git a/boards/altr/max10/Kconfig.defconfig b/boards/altr/max10/Kconfig.defconfig deleted file mode 100644 index d0617d44c33..00000000000 --- a/boards/altr/max10/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -if BOARD_ALTERA_MAX10 - -if FLASH - -config SOC_FLASH_NIOS2_QSPI - default y - -endif # FLASH - -endif # BOARD_ALTERA_MAX10 diff --git a/boards/altr/max10/altera_max10.dts b/boards/altr/max10/altera_max10.dts deleted file mode 100644 index 30c7e442505..00000000000 --- a/boards/altr/max10/altera_max10.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ -/* Copyright (c) 2018 Intel */ - -/dts-v1/; - -#include -#include - -/ { - model = "altera_max10"; - compatible = "altr,nios2-max10"; - - aliases { - uart-0 = &uart0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; -}; - -&qspi { - status = "okay"; - n25q512ax3: n25q512ax3@0 { - compatible = "altr,nios2-qspi-nor"; - size = ; /* in bits */ - reg = <0>; - }; -}; diff --git a/boards/altr/max10/altera_max10.yaml b/boards/altr/max10/altera_max10.yaml deleted file mode 100644 index eb068f21f47..00000000000 --- a/boards/altr/max10/altera_max10.yaml +++ /dev/null @@ -1,7 +0,0 @@ -identifier: altera_max10 -name: Altera MAX10 -type: mcu -arch: nios2 -toolchain: - - zephyr -vendor: altr diff --git a/boards/altr/max10/altera_max10_defconfig b/boards/altr/max10/altera_max10_defconfig deleted file mode 100644 index ac9a2e96e4d..00000000000 --- a/boards/altr/max10/altera_max10_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -CONFIG_HAS_ALTERA_HAL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/altr/max10/board.cmake b/boards/altr/max10/board.cmake deleted file mode 100644 index 9e7a8dd873d..00000000000 --- a/boards/altr/max10/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(nios2 "--cpu-sof=${ZEPHYR_BASE}/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof") -include(${ZEPHYR_BASE}/boards/common/nios2.board.cmake) diff --git a/boards/altr/max10/board.yml b/boards/altr/max10/board.yml deleted file mode 100644 index 9106b7e15ec..00000000000 --- a/boards/altr/max10/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: altera_max10 - full_name: MAX10 - vendor: altr - socs: - - name: zephyr_nios2f diff --git a/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg b/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg deleted file mode 100644 index 5c71d7bf80d..00000000000 Binary files a/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg and /dev/null differ diff --git a/boards/altr/max10/doc/img/altera_max10.jpg b/boards/altr/max10/doc/img/altera_max10.jpg deleted file mode 100644 index 51d5424c2f8..00000000000 Binary files a/boards/altr/max10/doc/img/altera_max10.jpg and /dev/null differ diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst deleted file mode 100644 index 1e5064b0f0d..00000000000 --- a/boards/altr/max10/doc/index.rst +++ /dev/null @@ -1,324 +0,0 @@ -.. zephyr:board:: altera_max10 - -Overview -******** - -The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using -the Nios II Gen 2 soft CPU. - -Hardware -******** - -DIP Switch settings -=================== - -There are two sets of switches on the back of the board. Of particular -importance is SW2: - -* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first - boot image is CFM0 -* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing - scripts won't work -* Switch 4 (HSMC_BYPASSN) should be OFF (up) - -.. image:: img/Altera_MAX10_switches.jpg - :align: center - :alt: Altera's MAX* 10 Switches - -Other switches are user switches, their position is application-specific. - -Necessary Software -================== - -You will need the Altera Quartus SDK in order to work with this device. The -`Altera Lite Distribution`_ of Quartus may be obtained without -charge. - -For your convenience using the SDK tools (such as ``nios2-configure-sof``), -you should put the binaries provided by the SDK -in your path. Below is an example, adjust ALTERA_BASE to where you installed the -SDK: - -.. code-block:: console - - export ALTERA_BASE=/opt/altera_lite/16.0 - export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin - -You may need to adjust your udev rules so that you can talk to the USB Blaster -II peripheral, which is the built-in JTAG interface for this device. - -The following works for Fedora 23: - -.. code-block:: console - - # For Altera USB-Blaster permissions. - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6010",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6810",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - -You can test connectivity with the SDK jtagconfig tool, you should see something -like: - -.. code-block:: console - - $ jtagconfig - 1) USB-BlasterII [1-1.2] - 031050DD 10M50DA(.|ES)/10M50DC - 020D10DD VTAP10 - - -Reference CPU -============= - -A reference CPU design of a Nios II/f core is included in the Zephyr tree -in the :zephyr_file:`soc/altr/zephyr_nios2f/cpu` directory. - -Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA -configuration file -:zephyr_file:`soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof`: - -.. code-block:: console - - $ nios2-configure-sof ghrd_10m50da.sof - -This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer. -For any Nios II SOC definition, you can find out more details about the CPU -configuration by inspecting system.h in the SOC's include directory. - -Console Output -============== - -16550 UART ----------- - -By default, the kernel is configured to send console output to the 16550 UART. -You can monitor this on your workstation by connecting to the top right mini USB -port on the board (it will show up in /dev as a ttyUSB node), and then running -minicom with flow control disabled, 115200-8N1 settings. - -JTAG UART ---------- - -You can also have it send its console output to the JTAG UART. -Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: - -.. code-block:: devicetree - - &jtag_uart { - status = "okay"; - current-speed = <115200>; - }; - -To view these messages on your local workstation, run the terminal application -in the SDK: - -.. code-block:: console - - $ nios2-terminal - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Flashing -======== - -Flashing Kernel into UFM ------------------------- - -The usual ``flash`` target will work with the ``altera_max10`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: flash - -Refer to :ref:`build_an_application` and :ref:`application_run` for -more details. - -This provisions the Zephyr kernel and the CPU configuration onto the board, -using the scripts/support/quartus-flash.py script. After it completes the kernel -will immediately boot. - - -Flashing Kernel directly into RAM over JTAG -------------------------------------------- - -The SDK included the nios2-download tool which will let you flash a kernel -directly into RAM and then boot it from the __start symbol. - -In order for this to work, your entire kernel must be located in RAM. Make sure -the following config options are disabled: - -.. code-block:: cfg - - CONFIG_XIP=n - CONFIG_INCLUDE_RESET_VECTOR=n - -Then, after building your kernel, push it into device's RAM by running -this from the build directory: - -.. code-block:: console - - $ nios2-download --go zephyr/zephyr.elf - -If you have a console session running (either minicom or nios2-terminal) you -should see the application's output. There are additional arguments you can pass -to nios2-download so that it spawns a GDB server that you can connect to, -although it's typically simpler to just use nios2-gdb-server as described below. - -Debugging -========= - -The Altera SDK includes a GDB server which can be used to debug a MAX10 board. -You can either debug a running image that was flashed onto the device in User -Flash Memory (UFM), or load an image over the JTAG using GDB. - -Debugging With UFM Flashed Image --------------------------------- - -You can debug an application in the usual way. Here is an example. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: debug - -You will see output similar to the following: - -.. code-block:: console - - Nios II GDB server running on port 3335 - Ignoring --stop option because --tcpport also specified - GNU gdb (GDB) 7.11.0.20160511-git - Copyright (C) 2016 Free Software Foundation, Inc. - License GPLv3+: GNU GPL version 3 or later - This is free software: you are free to change and redistribute it. - There is NO WARRANTY, to the extent permitted by law. Type "show copying" - and "show warranty" for details. - This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf". - Type "show configuration" for configuration details. - For bug reporting instructions, please see: - . - Find the GDB manual and other documentation resources online at: - . - For help, type "help". - Type "apropos word" to search for commands related to "word"... - Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done. - Remote debugging using :3335 - Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00 - Resetting and pausing target processor: OK - Listening on port 3335 for connection from GDB: accepted - isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63 - 63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list)); - (gdb) b z_prep_c - Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36. - (gdb) b z_cstart - Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348. - (gdb) c - Continuing. - - Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348 - 348 { - (gdb) - -To start debugging manually: - - -.. code-block:: console - - nios2-gdb-server --tcpport 1234 --stop --reset-target - -And then connect with GDB from the build directory: - - -.. code-block:: console - - nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234" - -Debugging With JTAG Flashed Image ---------------------------------- - -In order for this to work, execute-in-place must be disabled, since the GDB -'load' command can only put text and data in RAM. Ensure this is in your -configuration: - -.. code-block:: cfg - - CONFIG_XIP=n - -It is OK for this procedure to leave the reset vector enabled, unlike -nios2-download (which errors out if it finds sections outside of SRAM) it will -be ignored. - -In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if -any) is on the device, but you should have at least flashed a CPU using -nios2-configure-sof. You can leave this process running. - -.. code-block:: console - - $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target - -Build your Zephyr kernel, and load it into a GDB built for Nios II (included in -the Zephyr SDK) from the build directory: - -.. code-block:: console - - $ nios2-poky-elf-gdb zephyr/zephyr.elf - -Then connect to the GDB server: - -.. code-block:: console - - (gdb) target remote :1234 - -And then load the kernel image over the wire. The CPU will not start from the -reset vector, instead it will boot from the __start symbol: - - -.. code-block:: console - - (gdb) load - Loading section reset, size 0xc lma 0x0 - Loading section exceptions, size 0x1b0 lma 0x400020 - Loading section text, size 0x8df0 lma 0x4001d0 - Loading section devconfig, size 0x30 lma 0x408fc0 - Loading section rodata, size 0x3f4 lma 0x408ff0 - Loading section datas, size 0x888 lma 0x4093e4 - Loading section initlevel, size 0x30 lma 0x409c6c - Loading section _k_task_list, size 0x58 lma 0x409c9c - Loading section _k_task_ptr, size 0x8 lma 0x409cf4 - Loading section _k_event_list, size 0x10 lma 0x409cfc - Start address 0x408f54, load size 40184 - Transfer rate: 417 KB/sec, 368 bytes/write. - After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again. - - - -References -********** - -* `CPU Documentation `_ -* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ -* `Embedded Peripherals IP User Guide `_ -* `MAX 10 FPGA Configuration User Guide `_ -* `MAX 10 FPGA Development Kit User Guide `_ -* `Nios II Command-Line Tools `_ -* `Quartus II Scripting Reference Manual `_ - - -.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.dts b/boards/ambiq/apollo3_evb/apollo3_evb.dts index b6cf18bc1c6..ed7a0494a70 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb.dts +++ b/boards/ambiq/apollo3_evb/apollo3_evb.dts @@ -30,7 +30,6 @@ sw1 = &button1; bootloader-led0 = &led0; mcuboot-led0 = &led0; - rtc = &rtc0; }; leds { @@ -145,7 +144,7 @@ pinctrl-names = "default"; cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = ; - status = "okay"; + status = "disabled"; }; }; @@ -156,44 +155,16 @@ clock-frequency = ; scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "okay"; + status = "disabled"; }; }; &counter0 { - status = "okay"; -}; - -&counter1 { - status = "okay"; -}; - -&counter2 { - status = "okay"; -}; - -&counter3 { - status = "okay"; -}; - -&counter4 { - status = "okay"; -}; - -&counter5 { - status = "okay"; -}; - -&counter6 { - status = "okay"; -}; - -&counter7 { - status = "okay"; + status = "disabled"; }; &rtc0 { - status = "okay"; + status = "disabled"; clock = "XTAL"; }; diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts index a40767bd371..8b337138974 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts @@ -26,7 +26,6 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; - rtc = &rtc0; }; leds { @@ -123,7 +122,7 @@ pinctrl-names = "default"; cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = ; - status = "okay"; + status = "disabled"; }; }; @@ -134,44 +133,16 @@ clock-frequency = ; scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "okay"; + status = "disabled"; }; }; &counter0 { - status = "okay"; -}; - -&counter1 { - status = "okay"; -}; - -&counter2 { - status = "okay"; -}; - -&counter3 { - status = "okay"; -}; - -&counter4 { - status = "okay"; -}; - -&counter5 { - status = "okay"; -}; - -&counter6 { - status = "okay"; -}; - -&counter7 { - status = "okay"; + status = "disabled"; }; &rtc0 { - status = "okay"; + status = "disabled"; clock = "XTAL"; }; diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts index a4e8fdd6b43..f33e454272e 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts @@ -26,7 +26,6 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; - rtc = &rtc0; }; leds { @@ -77,11 +76,11 @@ }; &counter0 { - status = "okay"; + status = "disabled"; }; &rtc0 { - status = "okay"; + status = "disabled"; clock = "XTAL"; }; @@ -96,7 +95,7 @@ clock-frequency = ; scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "okay"; + status = "disabled"; }; }; @@ -106,7 +105,7 @@ pinctrl-names = "default"; cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = ; - status = "okay"; + status = "disabled"; }; }; @@ -121,7 +120,7 @@ &mspi0 { pinctrl-0 = <&mspi0_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &flash0 { diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts index cdac604591c..567ec2143fe 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts @@ -25,8 +25,6 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; - rtc = &rtc0; - sdhc0 = &sdio0; }; leds { @@ -79,15 +77,15 @@ &adc0 { pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &counter0 { - status = "okay"; + status = "disabled"; }; &rtc0 { - status = "okay"; + status = "disabled"; clock = "XTAL"; }; @@ -102,7 +100,7 @@ clock-frequency = ; scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; - status = "okay"; + status = "disabled"; }; }; @@ -112,26 +110,26 @@ pinctrl-names = "default"; cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>; clock-frequency = <1000000>; - status = "okay"; + status = "disabled"; }; }; &mspi0 { pinctrl-0 = <&mspi0_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &mspi1 { pinctrl-0 = <&mspi1_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &mspi2 { pinctrl-0 = <&mspi2_default>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &flash0 { @@ -160,11 +158,11 @@ pinctrl-names = "default"; txdelay = <0>; rxdelay = <0>; - status = "okay"; + status = "disabled"; mmc { compatible = "zephyr,mmc-disk"; disk-name = "SD2"; - status = "okay"; + status = "disabled"; }; }; diff --git a/boards/ambiq/apollo510_evb/Kconfig.defconfig b/boards/ambiq/apollo510_evb/Kconfig.defconfig index 9f9c9b2a196..8fd84d081a0 100644 --- a/boards/ambiq/apollo510_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo510_evb/Kconfig.defconfig @@ -12,4 +12,11 @@ config LOG_BACKEND_SWO_FREQ_HZ default 1000000 depends on LOG_BACKEND_SWO +if MSPI + +config MSPI_INIT_PRIORITY + default 40 + +endif # MSPI + endif # BOARD_APOLLO510_EVB diff --git a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi index 3f173b61a03..2f1472fc061 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi @@ -11,14 +11,256 @@ group1 { pinmux = ; }; + group2 { pinmux = ; input-enable; }; }; + swo_default: swo_default { group0 { pinmux = ; }; }; + + adc0_default: adc0_default{ + group1 { + pinmux = , ; + drive-strength = "0.1"; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c3_default: i2c3_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c5_default: i2c5_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c6_default: i2c6_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c7_default: i2c7_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + spid0_default: spid0_default { + group1 { + pinmux = , , , ; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + }; + + spi1_default: spi1_default { + group1 { + pinmux = , , ; + }; + }; + + spi2_default: spi2_default { + group1 { + pinmux = , , ; + }; + }; + + spi3_default: spi3_default { + group1 { + pinmux = , , ; + }; + }; + + spi4_default: spi4_default { + group1 { + pinmux = , , ; + }; + }; + + spi5_default: spi5_default { + group1 { + pinmux = , , ; + }; + }; + + spi6_default: spi6_default { + group1 { + pinmux = , , ; + }; + }; + + spi7_default: spi7_default { + group1 { + pinmux = , , ; + }; + }; + + mspi0_default: mspi0_default { + group0 { + pinmux = , + , + ; + drive-strength = "0.5"; + }; + + group1 { + pinmux = ; + drive-strength = "0.75"; + }; + }; + + mspi1_default: mspi1_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "0.5"; + }; + }; + + mspi0_sleep: mspi0_sleep { + group1 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + mspi1_sleep: mspi1_sleep { + group1 { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + mspi0_psram: mspi0_psram { + group0 { + pinmux = , /* D0 */ + , /* D1 */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* DQS0 */ + , /* D8 */ + , /* D9 */ + , /* D10 */ + , /* D11 */ + , /* D12 */ + , /* D13 */ + , /* D14 */ + , /* D15 */ + , /* DQS1 */ + ; /* CE0 */ + drive-strength = "0.5"; + }; + + group1 { + pinmux = ; /* SCK */ + drive-strength = "0.75"; + }; + }; + + mspi1_flash: mspi1_flash { + group0 { + pinmux = , + , + , + , + , + , + , + , + , + ; + drive-strength = "1.0"; + }; + + group1 { + pinmux = ; + drive-strength = "0.5"; + }; + }; }; diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.dts b/boards/ambiq/apollo510_evb/apollo510_evb.dts index 2303e43e125..4d4b898629c 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb.dts +++ b/boards/ambiq/apollo510_evb/apollo510_evb.dts @@ -43,14 +43,17 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio160_191 5 GPIO_ACTIVE_LOW>; label = "LED 0"; }; + led1: led_1 { gpios = <&gpio64_95 25 GPIO_ACTIVE_LOW>; label = "LED 1"; }; + led2: led_2 { gpios = <&gpio64_95 28 GPIO_ACTIVE_LOW>; label = "LED 2"; @@ -60,12 +63,14 @@ buttons { compatible = "gpio-keys"; polling-mode; + button0: button_0 { gpios = <&gpio64_95 29 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "BTN0"; zephyr,code = ; status = "okay"; }; + button1: button_1 { gpios = <&gpio64_95 30 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "BTN1"; @@ -84,6 +89,21 @@ pinctrl-names = "default"; }; +&adc0 { + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&counter0 { + status = "disabled"; +}; + +&rtc0 { + status = "disabled"; + clock = "XTAL"; +}; + &uart0 { current-speed = <115200>; pinctrl-0 = <&uart0_default>; diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.yaml b/boards/ambiq/apollo510_evb/apollo510_evb.yaml index 704c2c00208..ca2353540b4 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb.yaml +++ b/boards/ambiq/apollo510_evb/apollo510_evb.yaml @@ -9,9 +9,16 @@ toolchain: - gnuarmemb supported: - uart + - adc - watchdog + - counter - gpio + - spi + - i2c + - rtc + - hwinfo - clock_control + - mspi testing: ignore_tags: - net diff --git a/boards/amd/versal2_rpu/CMakeLists.txt b/boards/amd/versal2_rpu/CMakeLists.txt new file mode 100644 index 00000000000..bd0a687ea48 --- /dev/null +++ b/boards/amd/versal2_rpu/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# + +find_package(Dtc 1.4.6 REQUIRED) + +# Check if the board-specific qemu.dts file exists +if(EXISTS "${BOARD_DIR}/${BOARD}-qemu.dts") + # Ensure DTC executable is available + if(DTC_FOUND) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${DTC} -I dts -O dtb -q "${BOARD_DIR}/${BOARD}-qemu.dts" -o "${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb" + ) + else() + message(FATAL_ERROR "DTC not found, but required for compiling ${BOARD}-qemu.dts") + endif() +endif() diff --git a/boards/amd/versal2_rpu/Kconfig.versal2_rpu b/boards/amd/versal2_rpu/Kconfig.versal2_rpu new file mode 100644 index 00000000000..8317003f3ff --- /dev/null +++ b/boards/amd/versal2_rpu/Kconfig.versal2_rpu @@ -0,0 +1,8 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_VERSAL2_RPU + select SOC_AMD_VERSAL2_RPU diff --git a/boards/amd/versal2_rpu/board.cmake b/boards/amd/versal2_rpu/board.cmake new file mode 100644 index 00000000000..c03f2a1a98e --- /dev/null +++ b/boards/amd/versal2_rpu/board.cmake @@ -0,0 +1,22 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake) +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH xilinx-aarch64) +set(QEMU_CPU_TYPE_${ARCH} cortex-a78ae) + +set(QEMU_FLAGS_${ARCH} + -machine arm-generic-fdt + -hw-dtb ${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb + -device loader,addr=0xEB5E0310,data=0x2,data-len=4 + -nographic + -m 2g +) + +set(QEMU_KERNEL_OPTION + -device loader,cpu-num=8,file=\$ +) diff --git a/boards/amd/versal2_rpu/board.yml b/boards/amd/versal2_rpu/board.yml new file mode 100644 index 00000000000..744fc6acdd5 --- /dev/null +++ b/boards/amd/versal2_rpu/board.yml @@ -0,0 +1,6 @@ +board: + name: versal2_rpu + full_name: Versal 2 RPU development board + vendor: amd + socs: + - name: amd_versal2_rpu diff --git a/boards/amd/versal2_rpu/doc/index.rst b/boards/amd/versal2_rpu/doc/index.rst new file mode 100644 index 00000000000..44e4b707e05 --- /dev/null +++ b/boards/amd/versal2_rpu/doc/index.rst @@ -0,0 +1,73 @@ +.. zephyr:board:: versal2_rpu + +Overview +******** +This configuration provides support for the RPU(R52), real-time processing unit on Xilinx +Versal2 SOC, it can operate as following: + +* Two independent R52 cores with their own TCMs (tightly coupled memories) +* Or as a single dual lock step unit with the TCM. + +This processing unit is based on an ARM Cortex-R52 CPU, it also enables the following devices: + +* ARM GIC v3 Interrupt Controller +* Global Timer Counter +* SBSA UART + +Hardware +******** +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Devices +======== +System Timer +------------ + +This board configuration uses a system timer tick frequency of 100 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +on-chip UART0. + +Memories +-------- + +Although Flash, DDR and OCM memory regions are defined in the DTS file, +all the code plus data of the application will be loaded in the sram0 region, +which points to the DDR memory. The ocm0 memory area is currently available +for usage, although nothing is placed there by default. + +Known Problems or Limitations +============================== + +The following platform features are unsupported: + +* Only the first core of the R52 subsystem is supported. + +Programming and Debugging +************************* + +Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: versal2_rpu + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! versal2_rpu/amd_versal2_rpu + + +References +********** + +1. ARMv8-R Architecture Reference Manual (ARM DDI 0568A.c ID110520) +2. Cortex-R52 and Cortex-R52F Technical Reference Manual (ARM DDI r1p4 100026_0104_01_en) diff --git a/boards/amd/versal2_rpu/support/xsdb.cfg b/boards/amd/versal2_rpu/support/xsdb.cfg new file mode 100644 index 00000000000..88313923170 --- /dev/null +++ b/boards/amd/versal2_rpu/support/xsdb.cfg @@ -0,0 +1,78 @@ +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +proc rpu0_core0_rst { {mem "default"} } { + targets -set -filter {name =~ "DAP*"} + #CRL write protect + mwr -force 0xeb5e001c 0x0 + mwr -force 0xEB580000 1 + mwr -force 0xbbf20000 0xeafffffe + # write BASE_HI and BASE_LO + if {$mem eq "ddr"} { + set addr 0x100000 + } elseif {$mem eq "tcm"} { + set addr 0x0 + } elseif {$mem eq "default"} { + set addr 0xbbf20000 + } + mwr -force 0xEB588008 $addr + # write TCMBOOT as one + mask_write 0xEB588000 0x10 0x10 + # reset CORE0A_RESET out of reset A_TOPRESET and CORE0A_POR + mask_write 0xEB5E0310 0x10101 0x1 + # out of reset CORE0A_RESET + mask_write 0xEB5E0310 0x1 0x0 + targets -set -filter {name =~ "Cortex-R52*0" && parent =~ "*0x00100000"} + after 300 + stop + after 1000 + ta +} + + +proc load_image args { + set elf_file [lindex $args 0] + + if { [info exists ::env(HW_SERVER_URL)] } { + connect -url $::env(HW_SERVER_URL) + } else { + connect + } + + if { [info exists ::env(PDI_FILE_PATH)] } { + device program $::env(PDI_FILE_PATH) + } else { + puts "Error: env variable PDI_FILE_PATH is not set" + exit + } + + if { [info exists ::env(HW_SERVER_URL)] } { + set hw_server_url [split $::env(HW_SERVER_URL) ":"] + set host [lindex $hw_server_url 0] + set port [lindex $hw_server_url 1] + disconnect + after 2000 + connect -host $host -port $port + after 3000 + ta + } + after 1000 + targets -set -nocase -filter {name =~ "DAP*"} + after 100 + # Configure timestamp generator to run global timer gracefully + # Ideally these registers should be set from bootloader (cdo) + + mwr -force 0xea470020 100000000 + mwr -force 0xea470000 0x1 + after 100 + + rpu0_core0_rst + + after 100 + dow -force $elf_file + con + exit +} + +load_image {*}$argv diff --git a/boards/amd/versal2_rpu/versal2_rpu-qemu.dts b/boards/amd/versal2_rpu/versal2_rpu-qemu.dts new file mode 100644 index 00000000000..f888f1a17c5 --- /dev/null +++ b/boards/amd/versal2_rpu/versal2_rpu-qemu.dts @@ -0,0 +1,7832 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + + pmc_ppu0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x248>; + phandle = <0x108>; + }; + + pmc_ppu1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x249>; + phandle = <0x109>; + }; + + psm_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x238>; + phandle = <0x10a>; + }; + + ddrmc_ub0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x00>; + phandle = <0x10b>; + }; + + ddrmc_ub1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x00>; + phandle = <0x10c>; + }; + + pmc_dma0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x24a>; + phandle = <0x8b>; + }; + + pmc_dma1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x24b>; + phandle = <0x8c>; + }; + + pmc_qspi_dma_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x244>; + phandle = <0x7d>; + }; + + pmc_qspi_dma_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x244>; + phandle = <0x7b>; + }; + + apu0_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x260>; + phandle = <0xd3>; + }; + + apu0_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x260>; + phandle = <0xd4>; + }; + + apu1_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x261>; + phandle = <0xd5>; + }; + + apu1_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x261>; + phandle = <0xd6>; + }; + + rpu0_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x200>; + phandle = <0xe4>; + }; + + rpu1_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x204>; + phandle = <0xe7>; + }; + + gem0_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x234>; + phandle = <0x18>; + }; + + gem0_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x234>; + phandle = <0x19>; + }; + + gem1_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x235>; + phandle = <0x1d>; + }; + + gem1_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x235>; + phandle = <0x1e>; + }; + + ospi_dma_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x245>; + phandle = <0x81>; + }; + + ospi_dma_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x245>; + phandle = <0x7c>; + }; + + sd0_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x242>; + phandle = <0x77>; + }; + + sd0_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x242>; + phandle = <0x78>; + }; + + sd1_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x243>; + phandle = <0x79>; + }; + + sd1_w_ma_smid { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x243>; + phandle = <0x7a>; + }; + + usb0_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x230>; + phandle = <0x20>; + }; + + amba_root@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0xffff>; + interrupt-map = <0x00 0x00 0x00 0x01 0x00 0x00 0x04 0x00 0x00 0x01 0x01 0x00 0x01 +0x04 0x00 0x00 0x02 0x01 0x00 0x02 0x04 0x00 0x00 0x03 0x01 0x00 0x03 0x04 0x00 0x00 0x04 0x01 +0x00 0x04 0x04 0x00 0x00 0x05 0x01 0x00 0x05 0x04 0x00 0x00 0x06 0x01 0x00 0x06 0x04 0x00 +0x00 0x07 0x01 0x00 0x07 0x04 0x00 0x00 0x08 0x01 0x00 0x08 0x04 0x00 0x00 0x09 0x01 0x00 +0x09 0x04 0x00 0x00 0x0a 0x01 0x00 0x0a 0x04 0x00 0x00 0x0b 0x01 0x00 0x0b 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0x00 0x00 0xa7 +0x07 0x00 0xa7 0x04 0x00 0x00 0xa8 0x07 0x00 0xa8 0x04 0x00 0x00 0xa9 0x07 0x00 0xa9 0x04 +0x00 0x00 0xaa 0x07 0x00 0xaa 0x04 0x00 0x00 0xab 0x07 0x00 0xab 0x04 0x00 0x00 0xac 0x07 +0x00 0xac 0x04 0x00 0x00 0xad 0x07 0x00 0xad 0x04 0x00 0x00 0xae 0x07 0x00 0xae 0x04 0x00 +0x00 0xaf 0x07 0x00 0xaf 0x04 0x00 0x00 0xb0 0x07 0x00 0xb0 0x04 0x00 0x00 0xb1 0x07 0x00 +0xb1 0x04 0x00 0x00 0xb2 0x07 0x00 0xb2 0x04 0x00 0x00 0xb3 0x07 0x00 0xb3 0x04 0x00 0x00 +0xb4 0x07 0x00 0xb4 0x04 0x00 0x00 0xb5 0x07 0x00 0xb5 0x04 0x00 0x00 0xb6 0x07 0x00 0xb6 +0x04 0x00 0x00 0xb7 0x07 0x00 0xb7 0x04 0x00 0x00 0xb8 0x07 0x00 0xb8 0x04 0x00 0x00 0xb9 +0x07 0x00 0xb9 0x04 0x00 0x00 0xba 0x07 0x00 0xba 0x04 0x00 0x00 0xbb 0x07 0x00 0xbb 0x04 +0x00 0x00 0xbc 0x07 0x00 0xbc 0x04 0x00 0x00 0xbd 0x07 0x00 0xbd 0x04 0x00 0x00 0xbe 0x07 +0x00 0xbe 0x04 0x00 0x00 0xbf 0x07 0x00 0xbf 0x04 0x00 0x00 0xc0 0x07 0x00 0xc0 0x04 0x00 +0x00 0xc1 0x07 0x00 0xc1 0x04 0x00 0x00 0xc2 0x07 0x00 0xc2 0x04 0x00 0x00 0xc3 0x07 0x00 +0xc3 0x04 0x00 0x00 0xc4 0x07 0x00 0xc4 0x04 0x00 0x00 0xc5 0x07 0x00 0xc5 0x04 0x00 0x00 +0xc6 0x07 0x00 0xc6 0x04 0x00 0x00 0xc7 0x07 0x00 0xc7 0x04 0x00 0x00 0xc8 0x07 0x00 0xc8 +0x04 0x00 0x00 0xc9 0x07 0x00 0xc9 0x04 0x00 0x00 0xca 0x07 0x00 0xca 0x04 0x00 0x00 0xcb +0x07 0x00 0xcb 0x04 0x00 0x00 0xcc 0x07 0x00 0xcc 0x04 0x00 0x00 0xcd 0x07 0x00 0xcd 0x04 +0x00 0x00 0xce 0x07 0x00 0xce 0x04 0x00 0x00 0xcf 0x07 0x00 0xcf 0x04 0x00 0x00 0xd0 0x07 +0x00 0xd0 0x04 0x00 0x00 0xd1 0x07 0x00 0xd1 0x04 0x00 0x00 0xd2 0x07 0x00 0xd2 0x04 0x00 +0x00 0xd3 0x07 0x00 0xd3 0x04 0x00 0x00 0xd4 0x07 0x00 0xd4 0x04 0x00 0x00 0xd5 0x07 0x00 +0xd5 0x04 0x00 0x00 0xd6 0x07 0x00 0xd6 0x04 0x00 0x00 0xd7 0x07 0x00 0xd7 0x04 0x00 0x00 +0xd8 0x07 0x00 0xd8 0x04 0x00 0x00 0xd9 0x07 0x00 0xd8 0x04 0x00 0x00 0xda 0x07 0x00 0xda +0x04 0x00 0x00 0xdb 0x07 0x00 0xdb 0x04 0x00 0x00 0xdc 0x07 0x00 0xdc 0x04 0x00 0x00 0xdd +0x07 0x00 0xdd 0x04 0x00 0x00 0xde 0x07 0x00 0xde 0x04 0x00 0x00 0xdf 0x07 0x00 0xdf 0x04 +0x00 0x00 0xe0 0x07 0x00 0xe0 0x04 0x00 0x00 0xe1 0x07 0x00 0xe1 0x04 0x00 0x00 0xe2 0x07 +0x00 0xe2 0x04 0x00 0x00 0xe3 0x07 0x00 0xe3 0x04 0x00 0x00 0xe4 0x07 0x00 0xe4 0x04 0x00 +0x00 0xe5 0x07 0x00 0xe5 0x04 0x00 0x00 0xe6 0x07 0x00 0xe6 0x04 0x00 0x00 0xe7 0x07 0x00 +0xe7 0x04 0x00 0x00 0xe8 0x07 0x00 0xe8 0x04 0x00 0x00 0xe9 0x07 0x00 0xe9 0x04 0x00 0x00 +0xea 0x07 0x00 0xea 0x04 0x00 0x00 0xeb 0x07 0x00 0xeb 0x04 0x00 0x00 0xec 0x07 0x00 0xec +0x04 0x00 0x00 0xed 0x07 0x00 0xed 0x04 0x00 0x00 0xee 0x07 0x00 0xee 0x04 0x00 0x00 0xef +0x07 0x00 0xef 0x04 0x00 0x00 0xf0 0x07 0x00 0xf0 0x04 0x00 0x00 0xf1 0x07 0x00 0xf1 0x04 +0x00 0x00 0xf2 0x07 0x00 0xf2 0x04 0x00 0x00 0xf3 0x07 0x00 0xf3 0x04 0x00 0x00 0xf4 0x07 +0x00 0xf4 0x04 0x00 0x00 0xf5 0x07 0x00 0xf5 0x04 0x00 0x00 0xf6 0x07 0x00 0xf6 0x04 0x00 +0x00 0xf7 0x07 0x00 0xf7 0x04 0x00 0x00 0xf8 0x07 0x00 0xf8 0x04 0x00 0x00 0xf9 0x07 0x00 +0xf9 0x04 0x00 0x00 0xfa 0x07 0x00 0xfa 0x04 0x00 0x00 0xfb 0x07 0x00 0xfb 0x04 0x00 0x00 +0xfc 0x07 0x00 0xfc 0x04 0x00 0x00 0xfd 0x07 0x00 0xfd 0x04 0x00 0x00 0xfe 0x07 0x00 0xfe +0x04 0x00 0x00 0xff 0x07 0x00 0xff 0x04 0x00 0x00 0xa0 0x07 0x00 0xa0 0x04 0x00 0x00 0xbca +0x08 0x12 0x00 0x00 0xbd4 0x08 0x1c 0x00 0x00 0xbd5 0x08 0x1d 0x00 0x00 0xfbc 0x09 0x1c>; + phandle = <0x10d>; + + amba@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0d>; + + downstream_amba_lpd { + compatible = "qemu:memory-region"; + alias = <0x0a>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_fpd { + compatible = "qemu:memory-region"; + alias = <0x0b>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_internal { + compatible = "qemu:memory-region"; + alias = <0x0c>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_ocm@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x10>; + reg-extended = <0x0d 0x00 0xeb400000 0x00 0x10000 0x00 0x0d 0x00 +0xbbf00000 0x00 0x80000 0x02>; + protected-mr = <0x0e>; + mr-0 = <0x0d>; + protected-base = <0xbbf00000>; + phandle = <0x10e>; + }; + + xmpu_ocm2@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x10>; + reg-extended = <0x0d 0x00 0xeb9e0000 0x00 0x10000 0x00 0x0d 0x00 +0xbbe00000 0x00 0x80000 0x00>; + protected-mr = <0x0e>; + mr-0 = <0x0d>; + protected-base = <0xbbe00000>; + phandle = <0x10f>; + }; + + loader_write_cpu0_0x1@0xF1110880 { + compatible = "loader"; + addr = <0xf1110880>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x110>; + }; + + loader_write_cpu0_0x5@0xFD1A0050 { + compatible = "loader"; + addr = <0xfd1a0050>; + data = <0x05>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x111>; + }; + + loader_write_cpu0_0xFF@0xF111010C { + compatible = "loader"; + addr = <0xf111010c>; + data = <0xff>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x112>; + }; + + s_axi_tcm_a@0 { + compatible = "qemu:memory-region"; + alias = <0x0f>; + reg = <0x00 0xeba00000 0x00 0x800000 0x00>; + phandle = <0x34>; + }; + + s_axi_tcm_b@0 { + compatible = "qemu:memory-region"; + alias = <0x10>; + reg = <0x00 0xeba80000 0x00 0x800000 0x00>; + phandle = <0x38>; + }; + + s_axi_tcm_c@0 { + compatible = "qemu:memory-region"; + alias = <0x11>; + reg = <0x00 0xebb00000 0x00 0x800000 0x00>; + phandle = <0x3c>; + }; + + s_axi_tcm_d@0 { + compatible = "qemu:memory-region"; + alias = <0x12>; + reg = <0x00 0xebb80000 0x00 0x800000 0x00>; + phandle = <0x40>; + }; + + s_axi_tcm_e@0 { + compatible = "qemu:memory-region"; + alias = <0x13>; + reg = <0x00 0xebc00000 0x00 0x800000 0x00>; + phandle = <0x44>; + }; + + loader_write_cpu0_0x80C@0xF12B0100 { + compatible = "loader"; + addr = <0xf12b0100>; + data = <0x80c>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x113>; + }; + + loader_write_cpu0_0x77@0xF1260320 { + compatible = "loader"; + addr = <0xf1260320>; + data = <0x77>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x114>; + }; + + xmpu_ocm1@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x10>; + reg-extended = <0x0d 0x00 0xeb980000 0x00 0x10000 0x00 0x0d 0x00 +0xbbf80000 0x00 0x80000 0x00>; + protected-mr = <0x0e>; + mr-0 = <0x0d>; + protected-base = <0xbbf80000>; + phandle = <0x115>; + }; + + xmpu_ocm3@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x10>; + reg-extended = <0x0d 0x00 0xeaa10000 0x00 0x10000 0x00 0x0d 0x00 +0xbbe80000 0x00 0x80000 0x00>; + protected-mr = <0x0e>; + mr-0 = <0x0d>; + protected-base = <0xbbe80000>; + phandle = <0x116>; + }; + }; + + amba_lpd@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0a>; + + downstream_amba_psm { + compatible = "qemu:memory-region"; + alias = <0x14>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_xram { + compatible = "qemu:memory-region"; + alias = <0x15>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xppu_lpd@0xeb990000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x0a 0x00 0xeb990000 0x00 0x10000 0x00 0x16 0x00 +0xeb000000 0x00 0x1000000 0x02 0x16 0x00 0xea000000 0x00 0x1000000 0x02>; + mr = <0x0a>; + interrupts = <0x13>; + phandle = <0x117>; + }; + + ethernet@0xf1a60000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "cdns,gem"; + interrupts = <0x27 0x27>; + dma = <0x17>; + memattr = <0x18>; + memattr-write = <0x19>; + reg = <0x00 0xf1a60000 0x00 0x10000 0x00>; + num-priority-queues = <0x02>; + reset-gpios = <0x1a 0x01>; + power-gpios = <0x1b 0x2c>; + mdio = <0x1c>; + phandle = <0x118>; + }; + + ethernet@0xf1a70000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "cdns,gem"; + interrupts = <0x29 0x29>; + dma = <0x17>; + memattr = <0x1d>; + memattr-write = <0x1e>; + reg = <0x00 0xf1a70000 0x00 0x10000 0x00>; + num-priority-queues = <0x02>; + reset-gpios = <0x1a 0x02>; + power-gpios = <0x1b 0x2d>; + mdio = <0x1c>; + phandle = <0x119>; + }; + + serial@0xf1920000 { + compatible = "pl011"; + interrupts = <0x19>; + reg = <0x00 0xf1920000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x05>; + chardev = "serial2"; + phandle = <0x11a>; + }; + + serial@0xf1930000 { + compatible = "pl011"; + interrupts = <0x1a>; + reg = <0x00 0xf1930000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x06>; + chardev = "con"; + phandle = <0x11b>; + }; + + canfdbus@0 { + compatible = "can-bus"; + phandle = <0x1f>; + }; + + can@0xf19e0000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1f>; + interrupts = <0x1b>; + reg = <0x00 0xf19e0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x09>; + phandle = <0x11c>; + }; + + can@0xf19f0000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1f>; + interrupts = <0x1c>; + reg = <0x00 0xf19f0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x0a>; + phandle = <0x11d>; + }; + + crl@0xeb5e0000 { + compatible = "xlnx,psxc_crl"; + reg = <0x00 0xeb5e0000 0x00 0x300000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1a>; + }; + + slcr@0xf1a20000 { + compatible = "xlnx,versal-lpd-iou-slcr"; + reg = <0x00 0xf1a20000 0x00 0x20000 0x00>; + phandle = <0x11e>; + }; + + ipi@0xeb300000 { + compatible = "xlnx,versal-ipi"; + reg = <0x00 0xeb300000 0x00 0x100000 0x00>; + interrupts = <0xfbc 0xbd4 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0xbd5 +0x46 0x40 0x41 0x42 0x43 0x44 0x45>; + reset-gpios = <0x1a 0x19>; + num-master-ids = <0x20>; + phandle = <0x11f>; + }; + + spi@0xf19c0000 { + compatible = "cdns,spi-r1p6"; + interrupts = <0x17>; + num-ss-bits = <0x04>; + reg = <0x00 0xf19c0000 0x00 0x10000 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + reset-gpios = <0x1a 0x07>; + phandle = <0x120>; + + spi0_flash0@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25p80\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + blockdev-node-name = "spi0_flash0"; + phandle = <0x121>; + + spi0_flash0@0x00000000 { + label = "spi0_flash0"; + reg = <0x00 0x100000>; + }; + }; + }; + + spi@0xf19d0000 { + compatible = "cdns,spi-r1p6"; + interrupts = <0x18>; + num-ss-bits = <0x04>; + reg = <0x00 0xf19d0000 0x00 0x10000 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + reset-gpios = <0x1a 0x08>; + phandle = <0x122>; + + spi1_flash0@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25p80\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + blockdev-node-name = "spi1_flash0"; + phandle = <0x123>; + + spi1_flash0@0x00000000 { + label = "spi1_flash0"; + reg = <0x00 0x100000>; + }; + }; + }; + + usb2@USB2_0_XHCI { + compatible = "usb_dwc3"; + reg = <0x00 0xf1b0c100 0x00 0x600 0x00 0x00 0xf1b00000 0x00 +0x100000 0x00>; + interrupts = <0x1d 0x1e 0x1f 0x20>; + dma = <0x17>; + memattr = <0x20>; + reset-gpios = <0x1a 0x03>; + intrs = <0x04>; + slots = <0x02>; + phandle = <0x124>; + }; + + timer@0xf1e60000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2b 0x2b 0x2b>; + reg = <0x00 0xf1e60000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x12>; + phandle = <0x125>; + }; + + timer@0xf1e70000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2c 0x2c 0x2c>; + reg = <0x00 0xf1e70000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x13>; + phandle = <0x126>; + }; + + timer@0xf1e80000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2d 0x2d 0x2d>; + reg = <0x00 0xf1e80000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x14>; + phandle = <0x127>; + }; + + timer@0xf1e90000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2e 0x2e 0x2e>; + reg = <0x00 0xf1e90000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x15>; + phandle = <0x128>; + }; + + adma0mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x210>; + phandle = <0x21>; + }; + + dma-controller@0xebd00000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd00000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x48>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x21>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x00>; + phandle = <0x129>; + }; + + adma1mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x212>; + phandle = <0x23>; + }; + + dma-controller@0xebd10000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd10000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x49>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x23>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x01>; + phandle = <0x12a>; + }; + + adma2mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x214>; + phandle = <0x24>; + }; + + dma-controller@0xebd20000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd20000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4a>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x24>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x02>; + phandle = <0x12b>; + }; + + adma3mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x216>; + phandle = <0x25>; + }; + + dma-controller@0xebd30000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd30000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4b>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x25>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x03>; + phandle = <0x12c>; + }; + + adma4mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x218>; + phandle = <0x26>; + }; + + dma-controller@0xebd40000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd40000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4c>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x26>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x04>; + phandle = <0x12d>; + }; + + adma5mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21a>; + phandle = <0x27>; + }; + + dma-controller@0xebd50000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd50000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4d>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x27>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x05>; + phandle = <0x12e>; + }; + + adma6mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21c>; + phandle = <0x28>; + }; + + dma-controller@0xebd60000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd60000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4e>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x28>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x06>; + phandle = <0x12f>; + }; + + adma7mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x21e>; + phandle = <0x29>; + }; + + dma-controller@0xebd70000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd70000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x4f>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x29>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x07>; + phandle = <0x130>; + }; + + afi_fm@0xeb9b0000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xeb9b0000 0x00 0x10000 0x00>; + }; + + lpd_i2c_wrapper { + + ps_i2c@0xf1940000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x15>; + reg-extended = <0x0a 0x00 0xf1940000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x0b>; + phandle = <0x131>; + }; + + ps_i2c@0xf1950000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x16>; + reg-extended = <0x0a 0x00 0xf1950000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x0c>; + phandle = <0x132>; + }; + + ps_i2c@0xf1960000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x0b>; + reg-extended = <0x0a 0x00 0xf1960000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x30>; + phandle = <0x133>; + }; + + ps_i2c@0xf1970000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x0c>; + reg-extended = <0x0a 0x00 0xf1970000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x31>; + phandle = <0x134>; + }; + + ps_i2c@0xf1980000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x0d>; + reg-extended = <0x0a 0x00 0xf1980000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x32>; + phandle = <0x135>; + }; + + ps_i2c@0xf1990000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x64>; + reg-extended = <0x0a 0x00 0xf1990000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x33>; + phandle = <0x136>; + }; + + ps_i2c@0xf19a0000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x65>; + reg-extended = <0x0a 0x00 0xf19a0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x34>; + phandle = <0x137>; + }; + + ps_i2c@0xf19b0000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0x66>; + reg-extended = <0x0a 0x00 0xf19b0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x35>; + phandle = <0x138>; + }; + }; + + ocm_ctrl@OCM { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x10>; + memsize = <0x80000>; + reg = <0x00 0xeb5d0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x18>; + phandle = <0x139>; + }; + + lpd_slcr@0xeb410000 { + compatible = "xlnx.psxc-lpx-slcr"; + reg = <0x00 0xeb410000 0x00 0x100000 0x00>; + interrupt-parent = <0x08>; + interrupts = <0x1e>; + #gpio-cells = <0x01>; + gpio-controller; + num-rpu = <0x0a>; + core-0 = <0x2a>; + core-1 = <0x2b>; + core-2 = <0x2c>; + core-3 = <0x2d>; + core-4 = <0x2e>; + core-5 = <0x2f>; + core-6 = <0x30>; + core-7 = <0x31>; + core-8 = <0x32>; + core-9 = <0x33>; + phandle = <0x1b>; + }; + + lpd_slcr_secure@0xeb510000 { + compatible = "xlnx.versal2-psxc-lpx-slcr-secure"; + reg = <0x00 0xeb510000 0x00 0x40000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x22>; + }; + + lpd_iou_slcr_secure@0xf1a40000 { + compatible = "xlnx,versal-lpd-iou-slcr-secure"; + reg = <0x00 0xf1a40000 0x00 0x10000 0x00>; + memattr-gem0 = <0x18>; + memattr-write-gem0 = <0x19>; + memattr-gem1 = <0x1d>; + memattr-write-gem1 = <0x1e>; + phandle = <0x13a>; + }; + + wwdt@0xeb000000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xeb000000 0x00 0x10000 0x00>; + interrupts = <0xec 0xed 0xee 0xef>; + pclk = <0x5f5e100>; + reset-gpios = <0x1a 0x17>; + phandle = <0x13b>; + }; + + lpd_gpio@0xf1a50000 { + #gpio-cells = <0x01>; + compatible = "xlnx,zynqmp-gpio"; + gpio-controller; + interrupts = <0x14>; + reg = <0x00 0xf1a50000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x11>; + phandle = <0x13c>; + }; + + virtio_mmio_0 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e00000 0x00 0x1000 0x00>; + interrupts = <0x10e>; + }; + + virtio_mmio_1 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e01000 0x00 0x1000 0x00>; + interrupts = <0x10f>; + }; + + virtio_mmio_2 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e02000 0x00 0x1000 0x00>; + interrupts = <0x110>; + }; + + virtio_mmio_3 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e03000 0x00 0x1000 0x00>; + interrupts = <0x111>; + }; + + virtio_mmio_4 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e04000 0x00 0x1000 0x00>; + interrupts = <0x112>; + }; + + virtio_mmio_5 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e05000 0x00 0x1000 0x00>; + interrupts = <0x113>; + }; + + virtio_mmio_6 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e06000 0x00 0x1000 0x00>; + interrupts = <0x114>; + }; + + virtio_mmio_7 { + compatible = "virtio-mmio"; + reg = <0x00 0xf5e07000 0x00 0x1000 0x00>; + interrupts = <0x115>; + }; + + rpu_ctrl@0 { + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x13d>; + }; + + rpu_cluster@0xeb580000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb580000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x34>; + phandle = <0x36>; + }; + + rpu_ctrl_a0@0xeb588000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb588000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x23>; + core = <0x2a>; + tcm-mr = <0x35>; + phandle = <0xe5>; + }; + + rpu_ctrl_a1@0xeb58c000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb58c000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x24 0x36 0x00>; + core = <0x2b>; + tcm-mr = <0x37>; + phandle = <0xe8>; + }; + + rpu_cluster@0xeb590000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb590000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x38>; + phandle = <0x3a>; + }; + + rpu_ctrl_b0@0xeb598000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb598000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x25>; + core = <0x2c>; + tcm-mr = <0x39>; + phandle = <0xeb>; + }; + + rpu_ctrl_b1@0xeb59c000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb59c000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x26 0x3a 0x00>; + core = <0x2d>; + tcm-mr = <0x3b>; + phandle = <0xee>; + }; + + rpu_cluster@0xeb5a0000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb5a0000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x3c>; + phandle = <0x3e>; + }; + + rpu_ctrl_c0@0xeb5a8000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5a8000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x27>; + core = <0x2e>; + tcm-mr = <0x3d>; + phandle = <0xf1>; + }; + + rpu_ctrl_c1@0xeb5ac000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5ac000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x28 0x3e 0x00>; + core = <0x2f>; + tcm-mr = <0x3f>; + phandle = <0xf4>; + }; + + rpu_cluster@0xeb5b0000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb5b0000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x40>; + phandle = <0x42>; + }; + + rpu_ctrl_d0@0xeb5b8000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5b8000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x29>; + core = <0x30>; + tcm-mr = <0x41>; + phandle = <0xf7>; + }; + + rpu_ctrl_d1@0xeb5bc000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5bc000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x2a 0x42 0x00>; + core = <0x31>; + tcm-mr = <0x43>; + phandle = <0xfa>; + }; + + rpu_cluster@0xeb5c0000 { + compatible = "xlnx,psx_rpu_cluster_2.0"; + reg = <0x00 0xeb5c0000 0x00 0x8000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + tcm-mr = <0x44>; + phandle = <0x46>; + }; + + rpu_ctrl_e0@0xeb5c8000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5c8000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x2b>; + core = <0x32>; + tcm-mr = <0x45>; + phandle = <0xfd>; + }; + + rpu_ctrl_e1@0xeb5cc000 { + compatible = "xlnx,psxc-rpu-cluster-core"; + version = <0x01>; + reg = <0x00 0xeb5cc000 0x00 0x4000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + gpios = <0x1a 0x2c 0x46 0x00>; + core = <0x33>; + tcm-mr = <0x47>; + phandle = <0x100>; + }; + + usb2@USB2_0_XHCI1 { + compatible = "usb_dwc3"; + reg = <0x00 0xf1c0c100 0x00 0x600 0x00 0x00 0xf1c00000 0x00 +0x100000 0x00>; + interrupts = <0x22 0x23 0x24 0x25>; + dma = <0x17>; + memattr = <0x48>; + reset-gpios = <0x1a 0x04>; + intrs = <0x04>; + slots = <0x02>; + phandle = <0x13e>; + }; + + i3c0@0xf1940000 { + compatible = "dwc.i3c"; + reg = <0x00 0xf1948000 0x00 0x10000 0x00>; + num-devices = <0x0b>; + interrupts = <0x15>; + phandle = <0x13f>; + }; + + i3c1@0xf1950000 { + compatible = "dwc.i3c"; + reg = <0x00 0xf1958000 0x00 0x10000 0x00>; + slave-static-addr-en = <0x01>; + device-id = <0x01>; + interrupts = <0x16>; + phandle = <0x140>; + }; + + ocm_ctrl@0xeb960000 { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x11>; + memsize = <0x80000>; + reg = <0x00 0xeb960000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0xf1>; + phandle = <0x141>; + }; + + ocm_ctrl@0xeb9d0000 { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x0e>; + memsize = <0x80000>; + reg = <0x00 0xeb9d0000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0xf2>; + phandle = <0x142>; + }; + + ocm_ctrl@0xeaa00000 { + compatible = "xlnx,zynqmp-ocmc"; + interrupts = <0x0f>; + memsize = <0x80000>; + reg = <0x00 0xeaa00000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0xf3>; + phandle = <0x143>; + }; + + can@0xf1a00000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1f>; + interrupts = <0x5f>; + reg = <0x00 0xf1a00000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x2e>; + phandle = <0x144>; + }; + + can@0xf1a10000 { + compatible = "xlnx,versal-canfd"; + rx-fifo0 = <0x40>; + rx-fifo1 = <0x40>; + enable-rx-fifo1 = <0x01>; + canfdbus = <0x1f>; + interrupts = <0x60>; + reg = <0x00 0xf1a10000 0x00 0x10000 0x00>; + reset-gpios = <0x1a 0x2f>; + phandle = <0x145>; + }; + + timer@0xf1ea0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x2f 0x2f 0x2f>; + reg = <0x00 0xf1ea0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x36>; + phandle = <0x146>; + }; + + timer@0xf1eb0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x30 0x30 0x30>; + reg = <0x00 0xf1eb0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x37>; + phandle = <0x147>; + }; + + timer@0xf1ec0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x31 0x31 0x31>; + reg = <0x00 0xf1ec0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x38>; + phandle = <0x148>; + }; + + timer@0xf1ed0000 { + compatible = "xlnx,ps7-ttc-1.00.a"; + interrupts = <0x32 0x32 0x32>; + reg = <0x00 0xf1ed0000 0x00 0x10000 0x00>; + width = <0x20>; + reset-gpios = <0x1a 0x39>; + phandle = <0x149>; + }; + + sdma0mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x220>; + phandle = <0x49>; + }; + + dma-controller@0xebd80000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd80000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x70>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x49>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x08>; + phandle = <0x14a>; + }; + + sdma1mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x222>; + phandle = <0x4a>; + }; + + dma-controller@0xebd90000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebd90000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x71>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4a>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x09>; + phandle = <0x14b>; + }; + + sdma2mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x224>; + phandle = <0x4b>; + }; + + dma-controller@0xebda0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebda0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x72>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4b>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0a>; + phandle = <0x14c>; + }; + + sdma3mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x226>; + phandle = <0x4c>; + }; + + dma-controller@0xebdb0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebdb0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x73>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4c>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0b>; + phandle = <0x14d>; + }; + + sdma4mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x228>; + phandle = <0x4d>; + }; + + dma-controller@0xebdc0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebdc0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x74>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4d>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0c>; + phandle = <0x14e>; + }; + + sdma5mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x22a>; + phandle = <0x4e>; + }; + + dma-controller@0xebdd0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebdd0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x75>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4e>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0d>; + phandle = <0x14f>; + }; + + sdma6mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x22c>; + phandle = <0x4f>; + }; + + dma-controller@0xebde0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebde0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x76>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x4f>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0e>; + phandle = <0x150>; + }; + + sdma7mattr { + compatible = "qemu:memory-transaction-attr"; + requester-id = <0x22e>; + phandle = <0x50>; + }; + + dma-controller@0xebdf0000 { + compatible = "xlnx,zdma"; + reg = <0x00 0xebdf0000 0x00 0x10000 0x00>; + bus-width = <0x80>; + has-parity = <0x01>; + interrupts = <0x77>; + #stream-id-cells = <0x01>; + dma = <0x17>; + memattr = <0x50>; + reset-gpios = <0x1a 0x00>; + #gpio-cells = <0x01>; + gpio-names = "memattr-secure"; + gpios = <0x22 0x0f>; + phandle = <0x151>; + }; + + wwdt@0xeb010000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xeb010000 0x00 0x10000 0x00>; + interrupts = <0xf0 0xf1 0xf2 0xf3>; + pclk = <0x5f5e100>; + reset-gpios = <0x1a 0x3a>; + phandle = <0x152>; + }; + + lpd_afi_fs@0xeb560000 { + compatible = "xlnx.psxc_afi_fs"; + reg = <0x00 0xeb560000 0x00 0x8000 0x00>; + phandle = <0x153>; + }; + + downstream_amba_asu { + compatible = "qemu:memory-region"; + alias = <0x51>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + }; + + amba_fpd@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0b>; + + afi_fm@0xec880000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xec880000 0x00 0x10000 0x00>; + }; + + afi_fm@0xec8a0000 { + compatible = "xlnx,versal-afi-fm"; + reg = <0x00 0xec8a0000 0x00 0x10000 0x00>; + }; + + cpm_crcpm@0xfca00000 { + compatible = "xlnx,versal_cpm_crcpm"; + reg = <0x00 0xfca00000 0x00 0x10000 0x00>; + }; + + cpm_pcsr@0xfcff0000 { + compatible = "xlnx,versal_cpm_pcsr"; + reg = <0x00 0xfcff0000 0x00 0x10000 0x00>; + }; + + cpm_slcr_secure@0xfca20000 { + compatible = "xlnx.cpm_slcr_secure"; + reg = <0x00 0xfca20000 0x00 0x10000 0x00>; + }; + + fpd_slcr@0xec8c0000 { + compatible = "xlnx,versal-fpd-slcr"; + interrupts = <0x8c>; + reg = <0x00 0xec8c0000 0x00 0x10000 0x00>; + }; + + fpd_slcr_secure@0xec8c0000 { + compatible = "xlnx,versal-fpd-slcr-secure"; + interrupts = <0x8c>; + reg = <0x00 0xec8e0000 0x00 0x10000 0x00>; + }; + + watchdog@0xecc10000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xecc10000 0x00 0x10000 0x00>; + interrupts = <0xec 0xed 0xee 0xef>; + pclk = <0x5f5e100>; + reset-gpios = <0x52 0x1b>; + phandle = <0x154>; + }; + + apu_cluster@0xecc00000 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecc00000 0x00 0x10000 0x00>; + cpu0 = <0x53>; + cpu1 = <0x54>; + cpu2 = <0x55>; + cpu3 = <0x55>; + cores-per-cluster = <0x02>; + phandle = <0x155>; + }; + + apu_cluster@0xecd00000 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecd00000 0x00 0x10000 0x00>; + cpu0 = <0x56>; + cpu1 = <0x57>; + cpu2 = <0x55>; + cpu3 = <0x55>; + cores-per-cluster = <0x02>; + phandle = <0x156>; + }; + + apu_cluster@0xece00000 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xece00000 0x00 0x10000 0x00>; + cpu0 = <0x58>; + cpu1 = <0x59>; + cpu2 = <0x55>; + cpu3 = <0x55>; + cores-per-cluster = <0x02>; + phandle = <0x157>; + }; + + apu_cluster@0xecf00000 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,versal-apu-ctrl"; + reg = <0x00 0xecf00000 0x00 0x10000 0x00>; + cpu0 = <0x5a>; + cpu1 = <0x5b>; + cpu2 = <0x55>; + cpu3 = <0x55>; + cores-per-cluster = <0x02>; + phandle = <0x158>; + }; + + cmn600ae@0xa0000000 { + compatible = "arm,cmn600ae"; + reg = <0x00 0xa0000000 0x00 0x3000000 0x00>; + }; + + smmuv3@MM_FPD_SMMU { + compatible = "arm-smmuv3"; + reg-extended = <0x0b 0x00 0xec000000 0x00 0x200000 0x00 0x17 0x00 +0x00 0xffffffff 0xffffffff 0x00 0x5c 0x00 0x00 0xffffffff 0xffffffff 0x00 0x5d 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x5e 0x00 0x00 0xffffffff 0xffffffff 0x00 0x5f 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x60 0x00 0x00 0xffffffff 0xffffffff 0x00 0x61 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x62 0x00 0x00 0xffffffff 0xffffffff 0x00 0x63 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x64 0x00 0x00 0xffffffff 0xffffffff 0x00 0x65 0x00 0x00 +0xffffffff 0xffffffff 0x00 0x66 0x00 0x00 0xffffffff 0xffffffff 0x00 0x67 0x00 0x00 +0xffffffff 0xffffffff 0x00>; + mr-0 = <0x0d>; + mr-1 = <0x0d>; + mr-2 = <0x0d>; + mr-3 = <0x0d>; + mr-4 = <0x0d>; + mr-5 = <0x0d>; + mr-6 = <0x0d>; + mr-7 = <0x0d>; + mr-8 = <0x0d>; + mr-9 = <0x0d>; + mr-10 = <0x0d>; + mr-11 = <0x0d>; + mr-12 = <0x0d>; + dma_mr = <0x0d>; + primary-bus = <0x68>; + phandle = <0x159>; + }; + + dummy_pcie@0x6_0000_0000 { + compatible = "PCI"; + phandle = <0x68>; + }; + + apu_pcil@0xecb10000 { + compatible = "xlnx.apu_pcil"; + reg = <0x00 0xecb10000 0x00 0x10000 0x00>; + core-mask = <0x3333>; + cluster-mask = <0x0f>; + gpios = <0x1b 0x52 0x1b 0x53 0x1b 0x54 0x1b 0x55 0x1b 0x56 0x1b 0x57 +0x1b 0x58 0x1b 0x59 0x1b 0x5a 0x1b 0x5b 0x1b 0x5c 0x1b 0x5d 0x1b 0x5e 0x1b 0x5f 0x1b 0x60 0x1b 0x61 +0x1b 0x62 0x1b 0x63 0x1b 0x64 0x1b 0x65 0x1b 0x66 0x1b 0x67 0x1b 0x68 0x1b 0x69>; + core-0 = <0x53>; + core-1 = <0x54>; + core-4 = <0x56>; + core-5 = <0x57>; + core-8 = <0x58>; + core-9 = <0x59>; + core-12 = <0x5a>; + core-13 = <0x5b>; + phandle = <0x15a>; + }; + + lpd_afi_fs@0xec860000 { + compatible = "xlnx.psxc_afi_fs"; + reg = <0x00 0xec860000 0x00 0x8000 0x00>; + phandle = <0x15b>; + }; + + mmi_gem_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x25e>; + phandle = <0x69>; + }; + + mmi_usb_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x20e>; + phandle = <0x6b>; + }; + + amba_mmi@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x6d>; + + mdio_10gbe@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "mdio"; + phandle = <0x6a>; + + phy@1 { + compatible = "phy-clause45-generic"; + device_type = "ethernet-phy"; + reg = <0x01>; + phandle = <0x15c>; + }; + }; + + ethernet@0xed920000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "cdns,gem"; + reg = <0x00 0xed920000 0x00 0x10000 0x00>; + interrupts = <0xa4 0xa4 0xa4 0xa4>; + dma = <0x5d>; + memattr = <0x69>; + num-priority-queues = <0x04>; + mdio = <0x6a>; + has-usxgmii = <0x01>; + phandle = <0x15d>; + }; + + usb_drd@0xedec0000 { + compatible = "usb_dwc3"; + reg = <0x00 0xedec0000 0x00 0x10000 0x00>; + interrupts = <0xbf 0xc0>; + dma = <0x5d>; + memattr = <0x6b>; + intrs = <0x02>; + slots = <0x02>; + phandle = <0x15e>; + }; + + mmi_crs@0xedc00000 { + compatible = "xlnx.mmi_crx"; + reg = <0x00 0xedc00000 0x00 0x10000 0x00>; + phandle = <0x15f>; + }; + + mmi_pcsr@0xeb2f0000 { + compatible = "xlnx,noc-npi-dev"; + reg = <0x00 0xeb2f0000 0x00 0x10000 0x01>; + map-size = <0x10000>; + custom = <0x01>; + pcsr-status = <0x7ffe>; + phandle = <0x160>; + }; + + mmi_gtyp@0xed900000 { + compatible = "xlnx,noc-npi-dev"; + reg = <0x00 0xed900000 0x00 0x20000 0x01>; + map-size = <0xed900000>; + custom = <0x01>; + pcsr-status = <0x3a00d0>; + phandle = <0x161>; + }; + + mmi_slcr_sec@0 { + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + reg = <0x00 0xedc30000 0x00 0x10000 0x00>; + read-only; + phandle = <0x162>; + }; + + trng@0xede80000 { + doc-status = "complete"; + compatible = "xlnx,versal-trng"; + reg = <0x00 0xede80000 0x00 0x10000 0x00>; + interrupts = <0xc7>; + #gpio-cells = <0x01>; + phandle = <0x6c>; + }; + + udh_slcr@0xedea0000 { + compatible = "xlnx.mmi_udh_slcr"; + reg = <0x00 0xedea0000 0x00 0x8000 0x00>; + gpios = <0x6c 0x00>; + phandle = <0x163>; + }; + + udh_pll@0xede90000 { + compatible = "xlnx.mmi_udh_pll"; + reg = <0x00 0xede90000 0x00 0x10000 0x00>; + phandle = <0x164>; + }; + + mmi_gpu_a@0 { + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + reg = <0x00 0xed0a0098 0x00 0x10 0x00>; + read-only; + phandle = <0x165>; + }; + + loader_write_cpu0_0x1@0xEDC30440 { + compatible = "loader"; + addr = <0xedc30440>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x166>; + }; + + loader_write_cpu0_0x7F@0xEDC30444 { + compatible = "loader"; + addr = <0xedc30444>; + data = <0x7f>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x167>; + }; + + loader_write_cpu0_0x1@0xEDC3044c { + compatible = "loader"; + addr = <0xedc3044c>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x168>; + }; + + loader_write_cpu0_0x1@0xEDC30450 { + compatible = "loader"; + addr = <0xedc30450>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x169>; + }; + + loader_write_cpu0_0x1@0xEDC30460 { + compatible = "loader"; + addr = <0xedc30460>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16a>; + }; + + loader_write_cpu0_0x7f@0xEDC30464 { + compatible = "loader"; + addr = <0xedc30464>; + data = <0x7f>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16b>; + }; + + loader_write_cpu0_0x1@0xEDC3046c { + compatible = "loader"; + addr = <0xedc3046c>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16c>; + }; + + loader_write_cpu0_0x1@0xEDC30470 { + compatible = "loader"; + addr = <0xedc30470>; + data = <0x01>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16d>; + }; + + loader_write_cpu0_0x3@0xED0A0098 { + compatible = "loader"; + addr = <0xed0a0098>; + data = <0x03>; + data-len = <0x04>; + cpu-num = <0x00>; + attrs-debug = <0x01>; + attrs-secure = <0x00>; + attrs-requester-id = <0x00>; + phandle = <0x16e>; + }; + }; + + downstream_amba_mmi { + compatible = "qemu:memory-region"; + alias = <0x6d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + }; + + amba_pmc_internal@0 { + doc-ignore = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x0c>; + + downstream_amba_pmc_ppu { + compatible = "qemu:memory-region"; + alias = <0x6e>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_iou { + compatible = "qemu:memory-region"; + alias = <0x16>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_sec { + compatible = "qemu:memory-region"; + alias = <0x6f>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_sys { + compatible = "qemu:memory-region"; + alias = <0x70>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_pl { + compatible = "qemu:memory-region"; + alias = <0x71>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_bat { + compatible = "qemu:memory-region"; + alias = <0x72>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_pmc@0 { + compatible = "xlnx,versal-xmpu"; + interrupts = <0x13>; + reg-extended = <0x0c 0x00 0xf12f0000 0x00 0x10000 0x00 0x0c 0x00 +0xf2000000 0x00 0x20000 0x02>; + protected-mr = <0x73>; + mr-0 = <0x0c>; + protected-base = <0xf2000000>; + phandle = <0x16f>; + }; + + xppu_pmc_npi@0xf1300000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x0c 0x00 0xf1300000 0x00 0x10000 0x00 0x0c 0x00 +0xf6000000 0x00 0x1000000 0x02 0x0c 0x00 0xf7000000 0x00 0x1000000 0x02>; + mr = <0x71>; + interrupts = <0x13>; + phandle = <0x170>; + }; + + xppu_pmc@0xf1310000 { + compatible = "xlnx,versal-xppu"; + reg-extended = <0x0c 0x00 0xf1310000 0x00 0x10000 0x00 0x0d 0x00 +0xf1000000 0x00 0x1000000 0x02 0x0d 0x00 0xf0000000 0x00 0x1000000 0x02 0x0d 0x00 0xc0000000 0x00 +0x20000000 0x02>; + mr = <0x0c>; + interrupts = <0x13>; + phandle = <0x171>; + }; + }; + + amba_pmc@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x74>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + downstream_amba_pmc_internal { + compatible = "qemu:memory-region"; + alias = <0x0c>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + xmpu_pmc_cfu@0xf1340000 { + compatible = "xlnx,versal-xmpu"; + reg-extended = <0x74 0x00 0xf1340000 0x00 0x10000 0x00 0x71 0x00 +0xf12b0000 0x00 0x11000 0x02 0x71 0x00 0xf1f80000 0x00 0x40000 0x02>; + protected-mr = <0x75>; + mr-0 = <0x71>; + protected-base = <0xf12b0000>; + phandle = <0x172>; + }; + + pmx_err_mng@0xf1110000 { + compatible = "xlnx,pmxc-err-mng"; + reg = <0x00 0xf1130000 0x00 0x10000 0x01>; + gpios = <0x76 0x03 0x1b 0x2e 0x1b 0x2f 0x1b 0x30 0x1b 0x31>; + interrupts = <0xbca>; + phandle = <0x173>; + }; + + intpmxc_config@0xf1400000 { + compatible = "xlnx.pmxc_intpmx_config"; + reg = <0x00 0xf1400000 0x00 0x300000 0x00>; + phandle = <0x174>; + }; + }; + + amba_pmc_iou@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC IOU"; + doc-status = "partial"; + phandle = <0x16>; + + pmc_iou_slcr@0xf1060000 { + doc-status = "partial"; + compatible = "xlnx,versal-pmx-iou-slcr"; + reg = <0x00 0xf1060000 0x00 0x1000 0x00>; + interrupts = <0xde>; + gpio-controller; + #gpio-cells = <0x02>; + phandle = <0x85>; + }; + + pmc_iou_slcr_secure@0xf1070000 { + compatible = "xlnx,versal-pmc-iou-slcr-secure"; + reg = <0x00 0xf1070000 0x00 0x10000 0x00>; + interrupts = <0xbca>; + memattr-sd0 = <0x77>; + memattr-write-sd0 = <0x78>; + memattr-sd1 = <0x79>; + memattr-write-sd1 = <0x7a>; + memattr-write-qspi = <0x7b>; + memattr-write-ospi = <0x7c>; + phandle = <0x175>; + }; + + pmc_qspi_dma@QSPI_DMA { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xd9>; + #stream-id-cells = <0x01>; + reg = <0x00 0xf1030800 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x7d>; + memattr-write = <0x7b>; + is-dst = <0x01>; + reset-gpios = <0x7e 0x00>; + phandle = <0x7f>; + }; + + pmc_qspi@0xf1030000 { + doc-status = "complete"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "xlnx,usmp-gqspi\0cdns,spi-r1p6"; + stream-connected-dma = <0x7f>; + dma = <0x74>; + interrupts = <0xd9>; + num-ss-bits = <0x02>; + reg-extended = <0x16 0x00 0xf1030000 0x00 0x1000 0x00 0x80 0x00 0x00 +0x00 0x20000000 0x00>; + speed-hz = <0x989680>; + xlnx,fb-clk = <0x01>; + xlnx,qspi-clk-freq-hz = <0xbebc200>; + xlnx,qspi-mode = <0x02>; + reset-gpios = <0x7e 0x00>; + phandle = <0x176>; + + qspi_flash_lcs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + drive-index = <0x00>; + phandle = <0x177>; + + qspi_flash_lcs_lb@0x00000000 { + label = "qspi_flash_lcs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + qspi_flash_lcs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x02 0x01>; + drive-index = <0x01>; + phandle = <0x178>; + + qspi_flash_lcs_ub@0x00000000 { + label = "qspi_flash_lcs_ub"; + reg = <0x00 0x2000000>; + }; + }; + + qspi_flash_ucs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x01 0x00>; + drive-index = <0x02>; + phandle = <0x179>; + + qspi_flash_ucs_lb@0x00000000 { + label = "qspi_flash_ucs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + qspi_flash_ucs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "m25qu02gcbb\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x03 0x01>; + drive-index = <0x03>; + phandle = <0x17a>; + + qspi_flash_ucs_ub@0x00000000 { + label = "qspi_flash_ucs_ub"; + reg = <0x00 0x2000000>; + }; + }; + }; + + ospi_dst_dma@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xd8>; + reg = <0x00 0xf1011800 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x81>; + memattr-write = <0x7c>; + is-dst = <0x01>; + reset-gpios = <0x7e 0x01>; + phandle = <0x83>; + }; + + ospi_src_dma@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + interrupts = <0xd8>; + reg = <0x00 0xf1011000 0x00 0x800 0x00>; + dma = <0x82>; + memattr = <0x81>; + memattr-write = <0x7c>; + stream-connected-dma = <0x83>; + reset-gpios = <0x7e 0x01>; + phandle = <0x84>; + }; + + spi@0xf1010000 { + doc-status = "complete"; + #address-cells = <0x01>; + #size-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "xlnx,versal-ospi"; + reg-extended = <0x16 0x00 0xf1010000 0x00 0x1000 0x00 0x82 0x00 0x00 +0x00 0x20000000 0x00>; + dma-src = <0x84>; + interrupts = <0xd8>; + reset-gpios = <0x7e 0x01>; + gpios = <0x85 0x03 0x00>; + phandle = <0x17b>; + + ospi_flash_lcs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "mt35xu02gbba"; + spi-max-frequency = <0x2faf080>; + reg = <0x00 0x00>; + drive-index = <0x04>; + phandle = <0x17c>; + + ospi_flash_lcs_lb@0x00000000 { + label = "ospi_flash_lcs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + ospi_flash_lcs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "mt35xu02gbba"; + spi-max-frequency = <0x2faf080>; + reg = <0x01 0x00>; + drive-index = <0x05>; + phandle = <0x17d>; + + ospi_flash_lcs_ub@0x00000000 { + label = "ospi_flash_lcs_ub"; + reg = <0x00 0x2000000>; + }; + }; + + ospi_flash_ucs_lb@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "mt35xu01gbba\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x02 0x00>; + drive-index = <0x06>; + phandle = <0x17e>; + + ospi_flash_ucs_lb@0x00000000 { + label = "ospi_flash_ucs_lb"; + reg = <0x00 0x2000000>; + }; + }; + + ospi_flash_ucs_ub@0 { + #address-cells = <0x01>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + #bus-cells = <0x01>; + compatible = "mt35xu01gbba\0st,m25p80"; + spi-max-frequency = <0x2faf080>; + reg = <0x03 0x00>; + drive-index = <0x07>; + phandle = <0x17f>; + + ospi_flash_ucs_ub@0x00000000 { + label = "ospi_flash_ucs_ub"; + reg = <0x00 0x2000000>; + }; + }; + }; + + gpio_mr_mux@0xc0000000 { + doc-status = "complete"; + compatible = "gpio-mr-mux"; + reg = <0x00 0xc0000000 0x00 0x20000000 0x00>; + gpios = <0x85 0x02 0x00 0x85 0x03 0x00>; + mr-size = <0x20000000>; + mr0 = <0x80>; + mr1 = <0x82>; + mr2 = <0x80>; + mr3 = <0x82>; + phandle = <0x180>; + }; + + pmc_gpio@0xf1020000 { + #gpio-cells = <0x01>; + compatible = "xlnx,zynqmp-gpio"; + gpio-controller; + interrupts = <0xca>; + reg = <0x00 0xf1020000 0x00 0x10000 0x00>; + reset-gpios = <0x7e 0x05>; + phandle = <0x181>; + }; + + mmc@0xf1040000 { + doc-status = "complete"; + compatible = "xilinx,zynqmp-sdhci\0generic-sdhci"; + drive-index = <0x00>; + reg = <0x00 0xf1040000 0x00 0x10000 0x00>; + interrupts = <0xda>; + dma = <0x17>; + memattr = <0x77>; + memattr-write = <0x78>; + gpios = <0x85 0x00 0x00>; + gpio-names = "SLOTTYPE"; + reset-gpios = <0x7e 0x08>; + is-mmc = <0x00>; + xlnx,has-cd = <0x01>; + xlnx,has-power = <0x00>; + xlnx,has-wp = <0x01>; + xlnx,sdio-clk-freq-hz = <0x2faf080>; + phandle = <0x182>; + }; + + mmc@0xf1050000 { + doc-status = "complete"; + compatible = "xlnx,versalnet-emmc"; + drive-index = <0x01>; + reg = <0x00 0xf1050200 0x00 0x100 0x00 0x00 0xf1050000 0x00 +0x100 0x00>; + interrupts = <0xdc>; + dma = <0x17>; + memattr = <0x79>; + memattr-write = <0x7a>; + gpios = <0x85 0x01 0x00>; + gpio-names = "SLOTTYPE"; + reset-gpios = <0x7e 0x03>; + is-mmc = <0x00>; + xlnx,has-cd = <0x01>; + xlnx,has-power = <0x00>; + xlnx,has-wp = <0x01>; + xlnx,sdio-clk-freq-hz = <0x2faf080>; + phandle = <0x183>; + }; + + pmc_tap@0xf11a0000 { + doc-status = "complete"; + doc-comments = "Just a stub."; + compatible = "xlnx,pmc-tap"; + interrupts-extended = <0x86 0x1e>; + interrupt-names = "sec-dbg-int"; + reg = <0x00 0xf11a0000 0x00 0x80000 0x00>; + idcode = <0x14ca8093>; + platform-ver = <0x01>; + phandle = <0x184>; + }; + + pmc_i2c_wrapper { + + pmc_i2c@0xf1000000 { + compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10"; + interrupts = <0xcb>; + reg-extended = <0x16 0x00 0xf1000000 0x00 0x10000 0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + reset-gpios = <0x7e 0x04>; + phandle = <0x185>; + }; + }; + + wwdt@0xf03f0000 { + compatible = "xlnx,versal-wwdt"; + reg = <0x00 0xf03f0000 0x00 0x10000 0x00>; + pclk = <0x5f5e100>; + phandle = <0x186>; + }; + + pmc_ufshc@0xf10b0000 { + compatible = "ufshc-sysbus"; + reg = <0x00 0xf10b0000 0x00 0x10000 0x00>; + interrupts = <0xea>; + ufs-target = <0x87>; + unipro-mphy = <0x88>; + dma = <0x74>; + phandle = <0x89>; + }; + + unipro@0 { + compatible = "unipro-mphy"; + ufshc = <0x89>; + #gpio-cells = <0x01>; + phandle = <0x88>; + }; + + ufs_dev@0 { + compatible = "ufs-dev"; + num-luns = <0x08>; + phandle = <0x87>; + }; + + ufs_reg@0xf1060000 { + compatible = "dwc.ufs_reg"; + reg = <0x00 0xf1061000 0x00 0x100 0x01>; + gpios = <0x88 0x00>; + phandle = <0x187>; + }; + }; + + amba_pmc_sec@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC Secure"; + doc-status = "in-progress"; + qemu-fdt-abort-on-error = "Unable to create PMC security models. +Cannot continue.\nTry installing libgcrypt."; + phandle = <0x6f>; + + trng@0xf1230000 { + doc-status = "complete"; + compatible = "xlnx,versal-trng"; + reg = <0x00 0xf1230000 0x00 0x1000 0x00>; + interrupts = <0xe9>; + }; + + pmc_dma0_src@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + stream-connected-dma0 = <0x8a>; + reg = <0x00 0xf11c0000 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x8b>; + dma-width = <0x10>; + interrupts = <0xe0>; + reset-gpios = <0x7e 0x13>; + byte-align = <0x01>; + phandle = <0x188>; + }; + + pmc_dma0_dst@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xf11c0800 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x8b>; + is-dst = <0x01>; + dma-width = <0x10>; + interrupts = <0xe0>; + reset-gpios = <0x7e 0x13>; + byte-align = <0x01>; + phandle = <0x8d>; + }; + + pmc_dma1_src@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + stream-connected-dma1 = <0x8a>; + reg = <0x00 0xf11d0000 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x8c>; + dma-width = <0x10>; + interrupts = <0xe1>; + reset-gpios = <0x7e 0x14>; + byte-align = <0x01>; + phandle = <0x189>; + }; + + pmc_dma1_dst@0 { + doc-status = "complete"; + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xf11d0800 0x00 0x800 0x00>; + dma = <0x74>; + memattr = <0x8c>; + is-dst = <0x01>; + dma-width = <0x10>; + interrupts = <0xe1>; + reset-gpios = <0x7e 0x14>; + byte-align = <0x01>; + phandle = <0x8e>; + }; + + pmc_stream_switch@0 { + doc-status = "complete"; + compatible = "versal,pmc-sss"; + reg-extended = <0x70 0x00 0xf1110500 0x00 0x04 0x01>; + stream-connected-dma0 = <0x8d>; + stream-connected-dma1 = <0x8e>; + stream-connected-aes = <0x8f>; + stream-connected-sha = <0x90>; + stream-connected-sbi = <0x91>; + stream-connected-sha1 = <0x92>; + phandle = <0x8a>; + }; + + pmc_sha@0xf1210000 { + doc-status = "complete"; + compatible = "xlnx,asu_sha3"; + reg = <0x00 0xf1210000 0x00 0x100 0x00>; + interrupts = <0xe7>; + phandle = <0x90>; + }; + + pmc_aes@0xf11e0000 { + doc-status = "in-progress"; + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx-pmxc-aes"; + stream-connected-aes = <0x8a>; + reg = <0x00 0xf11e0000 0x00 0x100 0x00>; + interrupts = <0xe4>; + gpios = <0x93 0x00 0x93 0x01>; + gpio-names = "busy\0done"; + aes-core = <0x93>; + integrated-endianness-swap = <0x01>; + asu-aes = <0x94>; + phandle = <0x8f>; + + xlnx_aes@0 { + #gpio-cells = <0x01>; + compatible = "xlnx-aes"; + gpios = <0x8f 0x00>; + gpio-names = "reset"; + phandle = <0x93>; + }; + }; + + pmc_rsa@0xf1200000 { + doc-status = "complete"; + compatible = "xlnx,versal-ecdsa-rsa"; + reg = <0x00 0xf1200000 0x00 0x6c 0x00>; + interrupts = <0xe5>; + ram-nr-words = <0x100>; + phandle = <0x18a>; + }; + + xlnx_pmc_efuse_cache@0xf1250000 { + doc-status = "complete"; + compatible = "xlnx,pmx_efuse_cache"; + reg = <0x00 0xf1250000 0x00 0x10000 0x00>; + efuse = <0x95>; + phandle = <0x99>; + }; + + pmc_puf_ctrl@0 { + compatible = "xlnx,versal-puf-ctrl"; + zynqmp-aes-key-sink-puf = <0x8f>; + efuse = <0x95>; + reg = <0x00 0xf1150000 0x00 0x10000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x97>; + }; + + pmc_efuse@0xf1240000 { + doc-status = "complete"; + compatible = "xlnx,pmx_efuse_ctrl"; + #gpio-cells = <0x02>; + zynqmp-aes-key-sink-efuses = <0x8f>; + zynqmp-aes-key-sink-efuses-user0 = <0x8f>; + zynqmp-aes-key-sink-efuses-user1 = <0x8f>; + reg = <0x00 0xf1240000 0x00 0x10000 0x00>; + interrupts = <0xe6>; + efuse = <0x95>; + phandle = <0x18b>; + + xlnx_efuse@0 { + doc-ignore = <0x01>; + compatible = "xlnx,efuse"; + efuse-nr = <0x03>; + efuse-size = <0x2000>; + init-factory-extidcode = <0x01>; + phandle = <0x95>; + }; + }; + + pmc_bbram@0xf11f0000 { + doc-status = "partial"; + doc-limitations = "Missing AES key connections."; + compatible = "xlnx,bbram-ctrl"; + reg = <0x00 0xf11f0000 0x00 0x10000 0x00>; + interrupts = <0xbca>; + zynqmp-aes-key-sink-bbram = <0x8f>; + crc-zpads = <0x00>; + phandle = <0x98>; + }; + + pmc_sbi@0xf1220000 { + doc-status = "complete"; + compatible = "pmc,slave-boot"; + reg = <0x00 0xf1220000 0x00 0x10000 0x00 0x00 0xf2100000 +0x00 0x10000 0x00>; + interrupts = <0xe3>; + stream-connected-sbi = <0x8a>; + reset-gpios = <0x7e 0x12>; + phandle = <0x91>; + }; + + pmc_sha1@0xF1800000 { + doc-status = "complete"; + compatible = "xlnx,asu_sha2"; + reg = <0x00 0xf1800000 0x00 0x10000 0x00>; + phandle = <0x92>; + }; + }; + + amba_pmc_ppu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x6e>; + + pmc_gic_proxy@0 { + doc-status = "complete"; + #interrupt-cells = <0x03>; + interrupt-controller; + compatible = "xlnx,zynqmp-gicp"; + reg = <0x00 0xf1140000 0x00 0x100 0x00>; + interrupt-parent = <0x08>; + interrupts = <0x10>; + max-ints = <0x100>; + phandle = <0x07>; + }; + }; + + amba_pmc_sys@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC System"; + doc-status = "partial"; + phandle = <0x70>; + + pmc_clk_rst@0xf1260000 { + doc-status = "partial"; + compatible = "xlnx,pmx_crp"; + reg = <0x00 0xf1260000 0x00 0x80000 0x00>; + interrupts = <0xbca>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x7e>; + }; + + pmc_int@0xf1400000 { + doc-status = "partial"; + compatible = "xlnx,versal-pmc-int"; + reg = <0x00 0xf1400000 0x00 0x300000 0x00>; + interrupts = <0xe2>; + phandle = <0x18c>; + }; + + pmc_reset_domain@0 { + compatible = "qemu,reset-device"; + gpios = <0x7e 0x02>; + }; + + pmc_global@0xf1110000 { + doc-status = "partial"; + #gpio-cells = <0x01>; + gpio-controller; + interrupts-extended = <0x08 0x10 0x08 0x1b 0x08 0x1b 0x08 0x1b 0x08 +0x1b 0x08 0x11 0x08 0x11 0x96 0x00 0x86 0x10 0x86 0x11 0x86 0x12 0x86 0x13 0x86 0x14 0x86 0x15 0x86 +0x16 0x86 0x17 0x86 0x18 0x86 0x19 0x86 0x1a 0x86 0x1b 0x96 0x00 0x86 0x1d>; + reg = <0x00 0xf1110000 0x00 0x50000 0x00>; + gpios = <0x97 0x00>; + bbram = <0x98>; + efuse = <0x99>; + compatible = "xlnx,pmxc_global"; + phandle = <0x76>; + }; + + pmc_stream_zero@ { + compatible = "xlnx,pmc-stream-zero"; + reg = <0x00 0xf1110518 0x00 0x04 0x01>; + stream-connected-pzm = <0x8a>; + phandle = <0x18d>; + }; + + pmc_analog@0xf1160000 { + compatible = "xlnx,pmxc_anlg"; + reg = <0x00 0xf1160000 0x00 0x40000 0x00>; + interrupts-extended = <0x07 0x00 0x13 0x00>; + tamper-sink = <0x76>; + phandle = <0x18e>; + }; + + pmc_sysmon@0xf1270000 { + compatible = "xlnx,pmc-sysmon"; + reg = <0x00 0xf1270000 0x00 0x30000 0x00>; + interrupts = <0x12 0x79>; + reset-gpios = <0x7e 0x15>; + efuse = <0x99>; + ams-sats = <0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0>; + tamper-sink = <0x76>; + phandle = <0x18f>; + }; + + pmc_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xf1280000 0x00 0x10000 0x01>; + phandle = <0x9a>; + }; + + pmc_ams_sat@1 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xf1290000 0x00 0x10000 0x01>; + phandle = <0x9b>; + }; + + versal_pmc_tamper@ { + compatible = "xlnx,pmc_tamper"; + reg-extended = <0x70 0x00 0xf1110530 0x00 0x38 0x01 0xa1 0x00 +0xf0041100 0x00 0x38 0x02>; + phandle = <0x190>; + }; + + lpd_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xeb550000 0x00 0x10000 0x01>; + phandle = <0x9c>; + }; + + fpd_ams_sat@0 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecc30000 0x00 0x10000 0x01>; + phandle = <0x9d>; + }; + + fpd_ams_sat@1 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecd30000 0x00 0x10000 0x01>; + phandle = <0x9e>; + }; + + fpd_ams_sat@2 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xece30000 0x00 0x10000 0x01>; + phandle = <0x9f>; + }; + + fpd_ams_sat@3 { + compatible = "xlnx,ams-sat"; + reg = <0x00 0xecf30000 0x00 0x10000 0x01>; + phandle = <0xa0>; + }; + }; + + amba_pmc_pl@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC PL"; + doc-status = "partial"; + phandle = <0x71>; + + noc_npi_nir@0xf6000000 { + compatible = "xlnx.npi-nir"; + reg = <0x00 0xf6000000 0x00 0x10000 0x01>; + phandle = <0x191>; + }; + + npi_ddrmc_ub0@0xf62c0000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf62c0000 0x00 0x40000 0x01>; + reset-gpios = <0x7e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x192>; + }; + + npi_ddrmc_main0@0xf6290000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6290000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0xcf>; + }; + + npi_ddrmc_noc0@0xf62a0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf62a0000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x193>; + }; + + npi_ddrmc_ub1@0xf63b0000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf63b0000 0x00 0x40000 0x01>; + reset-gpios = <0x7e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x194>; + }; + + npi_ddrmc_main1@0xf6380000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6380000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x195>; + }; + + npi_ddrmc_noc1@0xf6390000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6390000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x196>; + }; + + npi_ddrmc_ub2@0xf6940000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf6940000 0x00 0x40000 0x01>; + reset-gpios = <0x7e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x197>; + }; + + npi_ddrmc_main2@0xf6910000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf6910000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x198>; + }; + + npi_ddrmc_noc2@0xf6920000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6920000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x199>; + }; + + npi_ddrmc_ub3@0xf6a20000 { + doc-limitations = "Only the uB rst is supported"; + compatible = "xlnx,ddrmc5_ub"; + reg = <0x00 0xf6a20000 0x00 0x40000 0x01>; + reset-gpios = <0x7e 0x0f>; + #gpio-cells = <0x01>; + gpio-controller; + phandle = <0x19a>; + }; + + npi_ddrmc_main3@0xf69f0000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-main"; + reg = <0x00 0xf69f0000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x19b>; + }; + + npi_ddrmc_noc3@0xf6a00000 { + doc-limitations = "Just a stub"; + compatible = "xlnx,versal-ddrmc-noc"; + reg = <0x00 0xf6a00000 0x00 0x20000 0xffffffff>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x19c>; + }; + + npi_ddrmc_xmpu0@0xf62a0000 { + compatible = "xlnx,versal-ddrmc-xmpu"; + reg-extended = <0x71 0x00 0xf62b2000 0x00 0x10000 0x01 0x0d 0x00 +0x00 0x00 0x80000000 0x00>; + protected-mr = <0xa2>; + mr-0 = <0x0d>; + protected-base = <0x00>; + phandle = <0x19d>; + }; + + npi_me@0xf6540000 { + compatible = "xlnx.aie2p_s_npi"; + reg = <0x00 0xf6540000 0x00 0x10000 0x01>; + reset-gpios = <0x7e 0x0f>; + phandle = <0x19e>; + }; + + noc_npi_devs@0 { + compatible = "xlnx,noc-npi-dev"; + reg = <0x00 0xf6000000 0x00 0x2000000 0x00>; + phandle = <0x19f>; + }; + + cfu_fdro@0xf12c2000 { + compatible = "xlnx,versal-cfu-fdro"; + reg = <0x00 0xf12c2000 0x00 0x1000 0x00>; + phandle = <0xa4>; + }; + + cfu_sfr@0xf12c1000 { + compatible = "xlnx,versal-cfu-sfr"; + reg = <0x00 0xf12c1000 0x00 0x1000 0x00>; + cfu = <0xa3>; + phandle = <0x1a0>; + }; + + cframe0_reg@0xf12d0000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d0000 0x00 0x1000 0x00 0x00 0xf12d1000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + blktype0-frames = <0x853f>; + blktype1-frames = <0xdc8>; + blktype2-frames = <0x3200>; + blktype3-frames = <0x0b>; + blktype4-frames = <0x05>; + blktype5-frames = <0x01>; + blktype6-frames = <0x01>; + phandle = <0xa5>; + }; + + cframe1_reg@0xf12d2000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d2000 0x00 0x1000 0x00 0x00 0xf12d3000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0xa6>; + }; + + cframe2_reg@0xf12d4000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d4000 0x00 0x1000 0x00 0x00 0xf12d5000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0xa7>; + }; + + cframe3_reg@0xf12d6000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d6000 0x00 0x1000 0x00 0x00 0xf12d7000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + blktype0-frames = <0x9662>; + blktype1-frames = <0xf01>; + blktype2-frames = <0x3c01>; + blktype3-frames = <0x0d>; + blktype4-frames = <0x07>; + blktype5-frames = <0x03>; + blktype6-frames = <0x01>; + phandle = <0xa8>; + }; + + cframe4_reg@0xf12d8000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12d8000 0x00 0x1000 0x00 0x00 0xf12d9000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xa9>; + }; + + cframe5_reg@0xf12da000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12da000 0x00 0x1000 0x00 0x00 0xf12db000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xaa>; + }; + + cframe6_reg@0xf12dc000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12dc000 0x00 0x1000 0x00 0x00 0xf12dd000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xab>; + }; + + cframe7_reg@0xf12de000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12de000 0x00 0x1000 0x00 0x00 0xf12df000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xac>; + }; + + cframe8_reg@0xf12e0000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e0000 0x00 0x1000 0x00 0x00 0xf12e1000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xad>; + }; + + cframe9_reg@0xf12e2000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e2000 0x00 0x1000 0x00 0x00 0xf12e3000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xae>; + }; + + cframe10_reg@0xf12e4000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e4000 0x00 0x1000 0x00 0x00 0xf12e5000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xaf>; + }; + + cframe11_reg@0xf12e6000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e6000 0x00 0x1000 0x00 0x00 0xf12e7000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xb0>; + }; + + cframe12_reg@0xf12e8000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12e8000 0x00 0x1000 0x00 0x00 0xf12e9000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xb1>; + }; + + cframe13_reg@0xf12ea000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12ea000 0x00 0x1000 0x00 0x00 0xf12eb000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xb2>; + }; + + cframe14_reg@0xf12ec000 { + compatible = "xlnx.cframe_reg"; + reg = <0x00 0xf12ec000 0x00 0x1000 0x00 0x00 0xf12ed000 +0x00 0x1000 0x00>; + interrupts = <0x13>; + cfu-fdro = <0xa4>; + phandle = <0xb3>; + }; + + cframe_bcast_reg@0xf12ee000 { + compatible = "xlnx.cframe-bcast-reg"; + reg = <0x00 0xf12ee000 0x00 0x1000 0x00 0x00 0xf12ef000 +0x00 0x1000 0x00>; + cframe0 = <0xa5>; + cframe1 = <0xa6>; + cframe2 = <0xa7>; + cframe3 = <0xa8>; + cframe4 = <0xa9>; + cframe5 = <0xaa>; + cframe6 = <0xab>; + cframe7 = <0xac>; + cframe8 = <0xad>; + cframe9 = <0xae>; + cframe10 = <0xaf>; + cframe11 = <0xb0>; + cframe12 = <0xb1>; + cframe13 = <0xb2>; + cframe14 = <0xb3>; + phandle = <0x1a1>; + }; + + gtyp_npi_slave_0@0xf65a0000 { + compatible = "xlnx,xlnx,gtyp_npi_slave"; + reg = <0x00 0xf65a0000 0x00 0x20000 0x00>; + }; + + gtyp_npi_slave_1@0xf66c0000 { + compatible = "xlnx,xlnx,gtyp_npi_slave"; + reg = <0x00 0xf66c0000 0x00 0x20000 0x00>; + }; + + gtyp_npi_slave_2@0xf6720000 { + compatible = "xlnx,xlnx,gtyp_npi_slave"; + reg = <0x00 0xf6720000 0x00 0x20000 0x00>; + }; + + dummy_cfu_mem@0xf12b0000 { + compatible = "qemu:memory-region"; + phandle = <0x75>; + + cfu@0x0 { + doc-status = "partial"; + doc-comments = "Stub"; + doc-limitations = "No way to extract CFRAME data."; + compatible = "xlnx,versal-cfu"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x10000 0x00 0x1000 +0x00 0x00 0xcd0000 0x00 0x40000 0x00>; + chardev = "pmc-cfu"; + dma = <0x74>; + phandle = <0xa3>; + }; + }; + }; + + amba_pmc_bat@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "PMC BAT"; + doc-status = "partial"; + phandle = <0x72>; + + rtc@0xf12a0000 { + doc-status = "complete"; + doc-comments = "Versal PMC RTC"; + compatible = "xlnx,zynqmp-rtc"; + interrupts = <0xbca 0xc8 0xc9>; + reg = <0x00 0xf12a0000 0x00 0x10000 0x00>; + xlnx,version = "2.0.0"; + phandle = <0x1a2>; + }; + }; + + amba_psm@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x14>; + }; + + amba_xram@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x15>; + + xram_ctrl_0 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb8e0000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_1 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb8f0000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_2 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb900000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + + xram_ctrl_3 { + compatible = "xlnx,versal-xramc"; + reg = <0x00 0xeb910000 0x00 0x10000 0x00>; + interrupts = <0x4f>; + alloc-ram = <0x00>; + }; + }; + + crf@0xec200000 { + compatible = "xlnx,versal-psx-crf"; + reg-extended = <0x0b 0x00 0xec200000 0x00 0x100000 0x00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x52>; + }; + + amba_asu_cpu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + #interrupt-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xb4>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + }; + + amba_asu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x51>; + + asu_instr_ram@0xebe00000 { + compatible = "qemu:memory-region"; + device_type = "memory"; + qemu,ram = <0x01>; + reg = <0x00 0xebe00000 0x00 0x40000 0x00>; + phandle = <0x1a3>; + }; + + io-module@0xebe80000 { + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; + container = <0xb4>; + priority = <0xffffffff>; + xlnx,freq = <0x47868c0>; + xlnx,instance = "iomodule_0"; + xlnx,io-mask = <0xfffe0000>; + xlnx,lmb-awidth = <0x20>; + xlnx,lmb-dwidth = <0x20>; + xlnx,mask = <0xffffff80>; + xlnx,use-io-bus = <0x01>; + phandle = <0x1a4>; + + asu_io_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xb5 0x0b>; + reg = <0x00 0xebe8000c 0x04 0x00 0xebe80030 0x10 0x00 +0xebe80080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x09>; + }; + + asu_gpi@20 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x09>; + interrupts = <0x0b>; + reg = <0x00 0xebe80020 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1a5>; + }; + + asu_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xebe80010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x03>; + xlnx,use-gpo = <0x01>; + phandle = <0xb6>; + }; + + asu_gpo@14 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xebe80014 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1a6>; + }; + + asu_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x09>; + interrupts = <0x03>; + reg = <0x00 0xebe80040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xb6 0x01 0xb7 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1a7>; + }; + + asu_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x09>; + interrupts = <0x04>; + reg = <0x00 0xebe80050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xb7>; + }; + + asu_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x09>; + interrupts = <0x05>; + reg = <0x00 0xebe80060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xb6 0x02 0xb8 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1a8>; + }; + + asu_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x09>; + interrupts = <0x06>; + reg = <0x00 0xebe80070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xb8>; + }; + }; + + asu_mdm_uart@0xebef0000 { + compatible = "xlnx,xps-uartlite"; + reg = <0x00 0xebef0000 0x00 0x10 0x01>; + chardev = "serial4"; + phandle = <0x1a9>; + }; + + asu_global@0xebf80000 { + compatible = "xlnx,asu_global"; + reg = <0x00 0xebf80000 0x00 0x20000 0x00>; + gpios = <0xb9 0x00>; + phandle = <0x1aa>; + }; + + asu_global_pmc@0xebf80000 { + compatible = "xlnx,asu_global_pmc"; + reg = <0x00 0xebf90000 0x00 0x20000 0x00>; + phandle = <0x1ab>; + }; + + asu_local@0xebe8e000 { + compatible = "xlnx,asu_local_reg"; + reg = <0x00 0xebe8e000 0x00 0x2000 0x00>; + phandle = <0x1ac>; + }; + + asu_sss@0xebe8e000 { + compatible = "asu-sss"; + reg = <0x00 0xebe8e000 0x00 0x08 0x01>; + stream-connected-dma0 = <0xba>; + stream-connected-sha2 = <0xbb>; + stream-connected-sha3 = <0xbc>; + stream-connected-dma1 = <0xbd>; + stream-connected-aes = <0xb9>; + phandle = <0xbe>; + }; + + asu_dma_src@0xebe8c000 { + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xebe8c000 0x00 0x800 0x00>; + interrupts = <0x13>; + stream-connected-dma0 = <0xbe>; + dma = <0xb4>; + memattr = <0x8b>; + dma-width = <0x10>; + byte-align = <0x01>; + phandle = <0x1ad>; + }; + + asu_dma_dst@0xebe8c000 { + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xebe8c800 0x00 0x800 0x00>; + interrupts = <0x13>; + dma = <0xb4>; + memattr = <0x8b>; + dma-width = <0x10>; + is-dst = <0x01>; + byte-align = <0x01>; + phandle = <0xba>; + }; + + asu_dma1_src@0xebe8d000 { + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xebe8d000 0x00 0x800 0x00>; + interrupts = <0x13>; + stream-connected-dma1 = <0xbe>; + dma = <0xb4>; + memattr = <0x8c>; + dma-width = <0x10>; + byte-align = <0x01>; + phandle = <0x1ae>; + }; + + asu_dma1_dst@0xebe8d000 { + compatible = "zynqmp,csu-dma"; + reg = <0x00 0xebe8d800 0x00 0x800 0x00>; + interrupts = <0x14>; + dma = <0xb4>; + memattr = <0x8c>; + dma-width = <0x10>; + is-dst = <0x01>; + byte-align = <0x01>; + phandle = <0xbd>; + }; + + asu_xmpu@0xebf60000 { + compatible = "xlnx,versal-xmpu"; + reg-extended = <0x51 0x00 0xebf60000 0x00 0x10000 0x00 0x51 0x00 +0xebe40000 0x00 0x20000 0x02>; + protected-mr = <0xbf>; + mr-0 = <0x0d>; + protected-base = <0xebe40000>; + phandle = <0x1af>; + }; + + asu_aes@0xebe88000 { + doc-status = "complete"; + compatible = "xlnx,asu-aes"; + reg = <0x00 0xebe88000 0x00 0x2000 0x00>; + #gpio-cells = <0x01>; + gpio-controller; + interrupts = <0x12 0x1a>; + keyvault = <0x94>; + stream-connected-aes = <0xbe>; + phandle = <0xb9>; + }; + + asu_kv@0xebe8a000 { + compatible = "xlnx,asu-kv"; + reg = <0x00 0xebe8a000 0x00 0x2000 0x00>; + pmxc-aes = <0x8f>; + aes-engine = <0xb9>; + phandle = <0x94>; + }; + + asu_sha3@0xebf40000 { + doc-status = "complete"; + compatible = "xlnx,asu_sha3"; + reg = <0x00 0xebf40000 0x00 0x10000 0x00>; + interrupts = <0x15>; + phandle = <0xbc>; + }; + + asu_sha2@0xebf30000 { + doc-status = "complete"; + compatible = "xlnx,asu_sha2"; + reg = <0x00 0xebf30000 0x00 0x10000 0x00>; + phandle = <0xbb>; + }; + + pmc_rsa@0xebf50000 { + doc-status = "complete"; + compatible = "xlnx,asu-ecdsa-rsa"; + reg = <0x00 0xebf50000 0x00 0x10000 0x00>; + interrupts = <0x17>; + phandle = <0x1b0>; + }; + + trng@0xebf20000 { + doc-status = "complete"; + compatible = "xlnx-asu-trng"; + reg = <0x00 0xebf10000 0x00 0x20000 0x00>; + interrupts = <0x18>; + phandle = <0x1b1>; + }; + + asu_ecc@0xebf00000 { + doc-status = "complete"; + compatible = "xlnx,asu_ecc"; + reg = <0x00 0xebf00000 0x00 0x10000 0x00>; + interrupts = <0x16>; + phandle = <0x1b2>; + }; + }; + }; + + lmb_pmc_ppu0@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB PPU0"; + doc-status = "complete"; + phandle = <0xa1>; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x74>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + pmc_rom@0xf0000000 { + reg = <0x00 0xf0000000 0x00 0x40000 0x01>; + compatible = "qemu:memory-region"; + container = <0xa1>; + qemu,ram = <0x01>; + read-only; + phandle = <0x1b3>; + }; + + ppu0_ram@0xf0060000 { + reg = <0x00 0xf0060000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + container = <0xa1>; + qemu,ram = <0x01>; + phandle = <0x1b4>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; + container = <0xa1>; + priority = <0xffffffff>; + xlnx,freq = <0x47868c0>; + xlnx,instance = "iomodule_1"; + xlnx,io-mask = <0xfffe0000>; + xlnx,lmb-awidth = <0x20>; + xlnx,lmb-dwidth = <0x20>; + xlnx,mask = <0xffffff80>; + xlnx,use-io-bus = <0x01>; + phandle = <0x1b5>; + + pmc_ppu0_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xc0 0x00>; + reg = <0x00 0xf008000c 0x04 0x00 0xf0080030 0x10 0x00 +0xf0080080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x86>; + }; + + pmc_ppu0_gpi@20 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x86>; + interrupts = <0x0b>; + reg = <0x00 0xf0080020 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1b6>; + }; + + pmc_ppu0_gpi@24 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x86>; + interrupts = <0x0c>; + reg = <0x00 0xf0080024 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1b7>; + }; + + pmc_ppu0_gpi@28 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x86>; + interrupts = <0x0d>; + reg = <0x00 0xf0080028 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1b8>; + }; + + pmc_ppu0_gpi@2c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x86>; + interrupts = <0x0e>; + reg = <0x00 0xf008002c 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1b9>; + }; + + pmc_ppu0_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x09>; + xlnx,use-gpo = <0x01>; + phandle = <0xc1>; + }; + + pmc_ppu0_gpo@14 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080014 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1ba>; + }; + + pmc_ppu0_gpo@18 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0080018 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1bb>; + }; + + pmc_ppu0_gpo@1c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf008001c 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1bc>; + }; + + pmc_ppu0_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x86>; + interrupts = <0x03>; + reg = <0x00 0xf0080040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xc1 0x01 0xc2 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1bd>; + }; + + pmc_ppu0_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x86>; + interrupts = <0x04>; + reg = <0x00 0xf0080050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xc2>; + }; + + pmc_ppu0_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x86>; + interrupts = <0x05>; + reg = <0x00 0xf0080060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xc1 0x06 0xc3 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1be>; + }; + + pmc_ppu0_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x86>; + interrupts = <0x06>; + reg = <0x00 0xf0080070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xc3>; + }; + }; + }; + + lmb_pmc_ppu1@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB PPU1"; + doc-status = "complete"; + phandle = <0xc4>; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x74>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus"; + container = <0xc4>; + priority = <0xffffffff>; + xlnx,freq = <0x47868c0>; + xlnx,instance = "iomodule_1"; + xlnx,io-mask = <0xfffe0000>; + xlnx,lmb-awidth = <0x20>; + xlnx,lmb-dwidth = <0x20>; + xlnx,mask = <0xffffff80>; + xlnx,use-io-bus = <0x01>; + phandle = <0x1bf>; + + pmc_ppu1_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xc5 0x00>; + reg = <0x00 0xf030000c 0x04 0x00 0xf0300030 0x10 0x00 +0xf0300080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0x08>; + }; + + pmc_ppu1_gpi@20 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x08>; + interrupts = <0x0b>; + reg = <0x00 0xf0300020 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1c0>; + }; + + pmc_ppu1_gpi@24 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x08>; + interrupts = <0x0c>; + reg = <0x00 0xf0300024 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1c1>; + }; + + pmc_ppu1_gpi@28 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x08>; + interrupts = <0x0d>; + reg = <0x00 0xf0300028 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1c2>; + }; + + pmc_ppu1_gpi@2c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi"; + interrupt-parent = <0x08>; + interrupts = <0x0e>; + reg = <0x00 0xf030002c 0x04>; + xlnx,gpi-interrupt = <0x01>; + xlnx,gpi-size = <0x20>; + xlnx,use-gpi = <0x01>; + phandle = <0x1c3>; + }; + + pmc_ppu1_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x09>; + xlnx,use-gpo = <0x01>; + phandle = <0xc6>; + }; + + pmc_ppu1_gpo@14 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300014 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1c4>; + }; + + pmc_ppu1_gpo@18 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf0300018 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1c5>; + }; + + pmc_ppu1_gpo@1c { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0xf030001c 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x20>; + xlnx,use-gpo = <0x01>; + phandle = <0x1c6>; + }; + + pmc_ppu1_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x08>; + interrupts = <0x03>; + reg = <0x00 0xf0300040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpios = <0xc6 0x01 0xc7 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1c7>; + }; + + pmc_ppu1_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x08>; + interrupts = <0x04>; + reg = <0x00 0xf0300050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xc7>; + }; + + pmc_ppu1_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x08>; + interrupts = <0x05>; + reg = <0x00 0xf0300060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpios = <0xc6 0x06 0xc8 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + windows-frequency = <0x13d620>; + phandle = <0x1c8>; + }; + + pmc_ppu1_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0x08>; + interrupts = <0x06>; + reg = <0x00 0xf0300070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x5f5e100>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xc8>; + }; + }; + }; + + lmb_psm@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x1c9>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + main_bus_for_pmc { + compatible = "qemu:memory-region"; + alias = <0x14>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + lmb_ddrmc@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + doc-name = "LMB DDRMC0"; + doc-status = "partial"; + phandle = <0xc9>; + + ddrmc0_ram_data@0x1c000 { + reg = <0x00 0x1c000 0x00 0x4000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1ca>; + }; + + ddrmc0_ram_instr@0x20000 { + reg = <0x00 0x20000 0x00 0x20000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1cb>; + }; + + ddrmc0_ram_exchange@0x08000 { + reg = <0x00 0x8000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1cc>; + }; + + io-module@00 { + doc-status = "complete"; + #address-cells = <0x02>; + #size-cells = <0x01>; + #priority-cells = <0x00>; + compatible = "simple-bus"; + container = <0xc9>; + priority = <0xffffffff>; + phandle = <0x1cd>; + + ddrmc0_intc@0C { + #interrupt-cells = <0x01>; + compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc"; + interrupt-controller; + interrupts-extended = <0xca 0x00>; + reg = <0x00 0x1b00c 0x04 0x00 0x1b030 0x10 0x00 0x1b080 0x7c>; + xlnx,intc-addr-width = <0x20>; + xlnx,intc-base-vectors = <0x00>; + xlnx,intc-has-fast = <0x00>; + xlnx,intc-intr-size = <0x10>; + xlnx,intc-level-edge = <0x00>; + xlnx,intc-positive = <0xffff>; + xlnx,intc-use-ext-intr = <0x01>; + phandle = <0xcb>; + }; + + ddrmc0_gpo@10 { + #gpio-cells = <0x01>; + gpio-controller; + compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo"; + reg = <0x00 0x1b010 0x04>; + xlnx,gpo-init = <0x00>; + xlnx,gpo-size = <0x03>; + xlnx,use-gpo = <0x01>; + phandle = <0xcc>; + }; + + ddrmc0_pit@40 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xcb>; + interrupts = <0x03>; + reg = <0x00 0x1b040 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xcc 0x01 0xcd 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1ce>; + }; + + ddrmc0_pit@50 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xcb>; + interrupts = <0x04>; + reg = <0x00 0x1b050 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xcd>; + }; + + ddrmc0_pit@60 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xcb>; + interrupts = <0x05>; + reg = <0x00 0x1b060 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpios = <0xcc 0x06 0xce 0x00>; + gpio-names = "ps_config\0ps_hit_in"; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x1cf>; + }; + + ddrmc0_pit@70 { + compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit"; + interrupt-parent = <0xcb>; + interrupts = <0x06>; + reg = <0x00 0x1b070 0x0c>; + xlnx,pit-interrupt = <0x01>; + xlnx,pit-prescaler = <0x09>; + xlnx,pit-readable = <0x01>; + xlnx,pit-size = <0x20>; + xlnx,use-pit = <0x01>; + frequency = <0x1b6b0b00>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0xce>; + }; + }; + + ddrmc_uart0@0 { + compatible = "xlnx,io_uart"; + reg = <0x00 0x1b000 0x0c 0x1b04c 0x04>; + xlnx,use-uart-rx = <0x01>; + xlnx,use-uart-tx = <0x01>; + chardev = "ddrmc-uart0\0serial1"; + phandle = <0x1d0>; + }; + + alias_npi_ddrmc_main { + compatible = "qemu:memory-region"; + alias = <0xcf>; + reg = <0x00 0x00 0x00 0x8000 0x00>; + }; + }; + + lmb_ddrmc@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x1d1>; + + ddrmc1_ram_data@0x1c000 { + reg = <0x00 0x1c000 0x00 0x4000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1d2>; + }; + + ddrmc1_ram_instr@0x20000 { + reg = <0x00 0x20000 0x00 0x20000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1d3>; + }; + + ddrmc1_ram_exchange@0x08000 { + reg = <0x00 0x8000 0x00 0x8000 0x01>; + compatible = "qemu:memory-region"; + qemu,ram = <0x01>; + phandle = <0x1d4>; + }; + }; + + amba_rpu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xd0>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + timer_a { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x02>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_b { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x03>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_c { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x04>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_d { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x05>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + + timer_e { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x06>; + interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>; + clock-frequency = <0x5f5e100>; + }; + }; + + amba_r5@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xe3>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x35>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic0 { + compatible = "qemu:memory-region"; + alias = <0xd1>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + }; + + amba_r5@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xe6>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x37>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic0 { + compatible = "qemu:memory-region"; + alias = <0xd1>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + }; + + dummy1@0 { + doc-ignore = <0x01>; + interrupt-controller; + #interrupt-cells = <0x01>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x96>; + }; + + tbu0_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x17>; + }; + + tbu1_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x5c>; + }; + + tbu2_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x5d>; + }; + + tbu3_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x5e>; + }; + + tbu4_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x5f>; + }; + + tbu5_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x60>; + }; + + tbu6_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x61>; + }; + + memory@00000000 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0d>; + phandle = <0x102>; + }; + + memory@8_0000_0000 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0d>; + phandle = <0x103>; + }; + + memory@0x50000000000ULL { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0d>; + phandle = <0x1d5>; + }; + + ocm_mem_bank_0@ { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x100000 0x00 0x80000 0x00>; + phandle = <0x1d6>; + }; + + ocm_mem_bank_1@ { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x180000 0x00 0x80000 0x00>; + phandle = <0x1d7>; + }; + + ocm_mem_bank_2@ { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x80000 0x00>; + phandle = <0x1d8>; + }; + + ocm_mem_bank_3@ { + compatible = "qemu:memory-region"; + container = <0x0e>; + qemu,ram = <0x01>; + reg = <0x00 0x80000 0x00 0x80000 0x00>; + phandle = <0x1d9>; + }; + + xram_mem@0xbbe00000 { + compatible = "qemu:memory-region"; + phandle = <0x1da>; + }; + + ipi_msgbuf@0 { + compatible = "qemu:memory-region"; + device_type = "memory"; + container = <0x0a>; + qemu,ram = <0x01>; + reg = <0x00 0xeb3f0000 0x00 0x1000 0x00>; + phandle = <0x1db>; + }; + + pmc_ram@0xf2000000 { + compatible = "qemu:memory-region"; + phandle = <0x73>; + }; + + pmc_ram_bank_0@0x0 { + compatible = "qemu:memory-region"; + container = <0x73>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x20000 0x00>; + phandle = <0x1dc>; + }; + + pmc_ppu1_ram@0xf0200000 { + compatible = "qemu:memory-region"; + container = <0x0d>; + qemu,ram = <0x01>; + reg = <0x00 0xf0200000 0x00 0x80000 0x00>; + phandle = <0x1dd>; + }; + + pmc_ppu1_ram@0xf0280000 { + compatible = "qemu:memory-region"; + container = <0x0d>; + qemu,ram = <0x01>; + reg = <0x00 0xf0280000 0x00 0x20000 0x00>; + phandle = <0x1de>; + }; + + ppu0_mdm_uart@0xf0110000 { + doc-status = "complete"; + compatible = "xlnx,xps-uartlite"; + reg-extended = <0xa1 0x00 0xf0110000 0x00 0x10 0x01>; + chardev = "serial0"; + }; + + ppu1_mdm_uart@0xf0310000 { + doc-status = "complete"; + compatible = "xlnx,xps-uartlite"; + reg-extended = <0xc4 0x00 0xf0310000 0x00 0x10 0x01>; + chardev = "serial1"; + }; + + lqspi_mr@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x80>; + }; + + lospi_mr@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x82>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + apu_cpu@0 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x00>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 0"; + #interrupt-cells = <0x01>; + memattr_s = <0xd3>; + memattr_ns = <0xd4>; + reset-gpios = <0x52 0x00>; + gpios = <0x1b 0x40>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x00>; + mp-affinity = <0x1000000>; + generic-timer-frequency = <0x298100>; + phandle = <0x53>; + }; + + apu_cpu@1 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x01>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 1"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xd5>; + memattr_ns = <0xd6>; + reset-gpios = <0x52 0x01>; + gpios = <0x1b 0x41>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x01>; + mp-affinity = <0x1000100>; + generic-timer-frequency = <0x298100>; + phandle = <0x54>; + }; + + apu_cpu@2 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x02>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 2"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xd7>; + memattr_ns = <0xd8>; + reset-gpios = <0x52 0x04>; + gpios = <0x1b 0x42>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x02>; + mp-affinity = <0x1010000>; + generic-timer-frequency = <0x298100>; + phandle = <0x56>; + }; + + apu_cpu@3 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x03>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 3"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xd9>; + memattr_ns = <0xda>; + reset-gpios = <0x52 0x05>; + gpios = <0x1b 0x43>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x03>; + mp-affinity = <0x1010100>; + generic-timer-frequency = <0x298100>; + phandle = <0x57>; + }; + + apu_cpu@4 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x04>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 4"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xdb>; + memattr_ns = <0xdc>; + reset-gpios = <0x52 0x08>; + gpios = <0x1b 0x44>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x04>; + mp-affinity = <0x1020000>; + generic-timer-frequency = <0x298100>; + phandle = <0x58>; + }; + + apu_cpu@5 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x05>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 5"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xdd>; + memattr_ns = <0xde>; + reset-gpios = <0x52 0x09>; + gpios = <0x1b 0x45>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x05>; + mp-affinity = <0x1020100>; + generic-timer-frequency = <0x298100>; + phandle = <0x59>; + }; + + apu_cpu@6 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x06>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 6"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xdf>; + memattr_ns = <0xe0>; + reset-gpios = <0x52 0x0c>; + gpios = <0x1b 0x46>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x06>; + mp-affinity = <0x1030000>; + generic-timer-frequency = <0x298100>; + phandle = <0x5a>; + }; + + apu_cpu@7 { + compatible = "cortex-a78-arm-cpu"; + device_type = "cpu"; + arm,ccsidr0 = <0x701fe00a>; + arm,ccsidr1 = <0x201fe012>; + reg = <0x07>; + core-count = <0x02>; + arm,reset-hivecs = <0x01>; + arm,rvbar = <0xffff0000>; + arm,reset-cbar = <0xe2060000>; + mr = <0xd2>; + memory = <0xd2>; + qemu,halt = <0x01>; + gdb-id = "Cortex-A78 7"; + #interrupt-cells = <0x01>; + direct-lnx-start-powered-off = <0x01>; + start-powered-off = <0x00>; + memattr_s = <0xe1>; + memattr_ns = <0xe2>; + reset-gpios = <0x52 0x0d>; + gpios = <0x1b 0x47>; + gpio-names = "wfi"; + power-gpios = <0x1b 0x07>; + mp-affinity = <0x1030100>; + generic-timer-frequency = <0x298100>; + phandle = <0x5b>; + }; + + rpu_a@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1df>; + + rpu_cpu_a@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x00>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xe3>; + qemu,halt = <0x01>; + memattr_ns = <0xe4>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #a0"; + gpios = <0x1a 0x23 0xe5 0x00 0x1b 0x48>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x08>; + phandle = <0x2a>; + }; + + rpu_cpu_a@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x01>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xe6>; + qemu,halt = <0x01>; + memattr_ns = <0xe7>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #a1"; + gpios = <0x1a 0x24 0xe8 0x00 0x1b 0x49>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x09>; + phandle = <0x2b>; + }; + }; + + rpu_b@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e0>; + + rpu_cpu_b@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x100>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xe9>; + qemu,halt = <0x01>; + memattr_ns = <0xea>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #b0"; + gpios = <0x1a 0x25 0xeb 0x00 0x1b 0x4a>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0a>; + phandle = <0x2c>; + }; + + rpu_cpu_b@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x101>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xec>; + qemu,halt = <0x01>; + memattr_ns = <0xed>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #b1"; + gpios = <0x1a 0x26 0xee 0x00 0x1b 0x4b>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0b>; + phandle = <0x2d>; + }; + }; + + rpu_c@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e1>; + + rpu_cpu_c@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x200>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xef>; + qemu,halt = <0x01>; + memattr_ns = <0xf0>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #c0"; + gpios = <0x1a 0x27 0xf1 0x00 0x1b 0x4c>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0c>; + phandle = <0x2e>; + }; + + rpu_cpu_c@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x201>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xf2>; + qemu,halt = <0x01>; + memattr_ns = <0xf3>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #c1"; + gpios = <0x1a 0x28 0xf4 0x00 0x1b 0x4d>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0d>; + phandle = <0x2f>; + }; + }; + + rpu_d@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e2>; + + rpu_cpu_d@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x300>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xf5>; + qemu,halt = <0x01>; + memattr_ns = <0xf6>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #d0"; + gpios = <0x1a 0x29 0xf7 0x00 0x1b 0x4e>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0e>; + phandle = <0x30>; + }; + + rpu_cpu_d@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x301>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xf8>; + qemu,halt = <0x01>; + memattr_ns = <0xf9>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #d1"; + gpios = <0x1a 0x2a 0xfa 0x00 0x1b 0x4f>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x0f>; + phandle = <0x31>; + }; + }; + + rpu_e@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1e3>; + + rpu_cpu_e@0 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x400>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xfb>; + qemu,halt = <0x01>; + memattr_ns = <0xfc>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #e0"; + gpios = <0x1a 0x2b 0xfd 0x00 0x1b 0x50>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x10>; + phandle = <0x32>; + }; + + rpu_cpu_e@1 { + compatible = "cortex-r52-arm-cpu"; + device_type = "cpu"; + arm,tcmtr = <0x10001>; + arm,ctr = <0x8003c003>; + arm,clidr = <0x9200003>; + arm,ccsidr0 = <0xf01fe019>; + arm,ccsidr1 = <0xf01fe019>; + arm,mp-affinity = <0x401>; + arm,id_pfr0 = <0x131>; + arm,reset-hivecs = <0x01>; + #interrupt-cells = <0x01>; + memory = <0xfe>; + qemu,halt = <0x01>; + memattr_ns = <0xff>; + core-count = <0x02>; + gdb-id = "Cortex-R52 #e1"; + gpios = <0x1a 0x2c 0x100 0x00 0x1b 0x51>; + gpio-names = "reset\0halt\0wfi"; + reset-cbar = <0xe2000000>; + power-gpios = <0x1b 0x11>; + phandle = <0x33>; + }; + }; + }; + + amba_apu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xd2>; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <0x01>; + interrupts = <0x1000001 0x0d 0xffffff01 0x1000001 0x0e 0xffffff01 0x1000001 +0x0b 0xffffff01 0x1000001 0x0a 0xffffff01>; + clock-frequency = <0x5f5e100>; + phandle = <0x1e4>; + }; + }; + + amba_apu_gic@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + container = <0x0b>; + priority = <0xffffffff>; + phandle = <0x1e5>; + + interrupt-controller@0xe2000000 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0xe2000000 0x00 0x10000 0x00 0x00 0xe2060000 +0x00 0x400000 0x00>; + interrupt-controller; + interrupts-extended = <0x53 0x00 0x54 0x00 0x56 0x00 0x57 0x00 0x58 0x00 +0x59 0x00 0x5a 0x00 0x5b 0x00 0x53 0x01 0x54 0x01 0x56 0x01 0x57 0x01 0x58 0x01 0x59 0x01 0x5a +0x01 0x5b 0x01 0x53 0x02 0x54 0x02 0x56 0x02 0x57 0x02 0x58 0x02 0x59 0x02 0x5a 0x02 0x5b 0x02 +0x53 0x03 0x54 0x03 0x56 0x03 0x57 0x03 0x58 0x03 0x59 0x03 0x5a 0x03 0x5b 0x03 0x01 0x01 0x09 +0x104 0x01 0x01 0x09 0x204 0x01 0x01 0x09 0x404 0x01 0x01 0x09 0x804 0x01 0x01 0x09 0x1004 +0x01 0x01 0x09 0x2004 0x01 0x01 0x09 0x4004 0x01 0x01 0x09 0x8004>; + num-cpu = <0x08>; + num-irq = <0x220>; + has-security-extensions = <0x01>; + redist-region-count = <0x08>; + has-lpi = <0x01>; + sysmem = <0x0d>; + phandle = <0x01>; + }; + + git_its@0xe2040000 { + compatible = "arm-gicv3-its"; + reg = <0x00 0xe2040000 0x00 0x20000 0x00>; + parent-gicv3 = <0x01>; + }; + }; + + lpd_reset_domain@0 { + compatible = "qemu,reset-domain"; + mr0 = <0x0a>; + reset-gpios = <0x7e 0x07 0x7e 0x0a>; + }; + + fpd_reset_domain@0 { + compatible = "qemu,reset-domain"; + mr0 = <0x0b>; + reset-gpios = <0x7e 0x07 0x7e 0x0a 0x1a 0x1c 0x1a 0x1d>; + }; + + amba_alias@0 { + compatible = "qemu:memory-region"; + container = <0x101>; + alias = <0x0d>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x01>; + phandle = <0x1e6>; + }; + + qemu_sysmem@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:system-memory"; + phandle = <0x101>; + }; + + dummy_ppu0@0 { + #interrupt-cells = <0x01>; + phandle = <0xc0>; + }; + + dummy_ppu1@0 { + #interrupt-cells = <0x01>; + phandle = <0xc5>; + }; + + dummy_ddrmc0@0 { + #interrupt-cells = <0x01>; + phandle = <0xca>; + }; + + dummy_ddrmc1@0 { + #interrupt-cells = <0x01>; + phandle = <0x1e7>; + }; + + ddr@0x00000000 { + compatible = "qemu:memory-region"; + container = <0x102>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x80000000 0x00>; + phandle = <0xa2>; + }; + + ddr_2@0x800000000ULL { + compatible = "qemu:memory-region-spec"; + container = <0x103>; + qemu,ram = <0x01>; + reg = <0x08 0x00 0x08 0x00 0x00>; + phandle = <0x1e8>; + }; + + mdio { + #address-cells = <0x01>; + #size-cells = <0x00>; + #priority-cells = <0x00>; + compatible = "mdio"; + phandle = <0x1c>; + + phy@1 { + compatible = "dp83867"; + device_type = "ethernet-phy"; + reg = <0x01>; + phandle = <0x1e9>; + }; + + phy@2 { + compatible = "88e1118r"; + device_type = "ethernet-phy"; + reg = <0x02>; + phandle = <0x1ea>; + }; + }; + + cpu_dummy { + phandle = <0x55>; + }; + + tbu7_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x62>; + }; + + tbu8_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x63>; + }; + + tbu9_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x64>; + }; + + tbu10_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x65>; + }; + + tbu11_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x66>; + }; + + tbu12_slave@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x67>; + }; + + mr_rpu_gic_a@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0xd1>; + + rpu_gic_a@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x2a 0x00 0x2b 0x00 0x2a 0x01 0x2b 0x01 0x2a 0x02 +0x2b 0x02 0x2a 0x03 0x2b 0x03 0x02 0x01 0x09 0x104 0x02 0x01 0x09 0x204>; + first-cpu-idx = <0x08>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x02>; + }; + }; + + mr_rpu_gic_b@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0x104>; + + rpu_gic_b@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x2c 0x00 0x2d 0x00 0x2c 0x01 0x2d 0x01 0x2c 0x02 +0x2d 0x02 0x2c 0x03 0x2d 0x03 0x03 0x01 0x09 0x104 0x03 0x01 0x09 0x204>; + first-cpu-idx = <0x0a>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x03>; + }; + }; + + mr_rpu_gic_c@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0x105>; + + rpu_gic_c@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x2e 0x00 0x2f 0x00 0x2e 0x01 0x2f 0x01 0x2e 0x02 +0x2f 0x02 0x2e 0x03 0x2f 0x03 0x04 0x01 0x09 0x104 0x04 0x01 0x09 0x204>; + first-cpu-idx = <0x0c>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x04>; + }; + }; + + mr_rpu_gic_d@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0x106>; + + rpu_gic_d@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x30 0x00 0x31 0x00 0x30 0x01 0x31 0x01 0x30 0x02 +0x31 0x02 0x30 0x03 0x31 0x03 0x05 0x01 0x09 0x104 0x05 0x01 0x09 0x204>; + first-cpu-idx = <0x0e>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x05>; + }; + }; + + mr_rpu_gic_e@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + phandle = <0x107>; + + rpu_gic_e@0x0 { + #address-cells = <0x00>; + #size-cells = <0x00>; + #interrupt-cells = <0x03>; + compatible = "arm-gicv3"; + reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>; + interrupt-controller; + interrupts-extended = <0x32 0x00 0x33 0x00 0x32 0x01 0x33 0x01 0x32 0x02 +0x33 0x02 0x32 0x03 0x33 0x03 0x06 0x01 0x09 0x104 0x06 0x01 0x09 0x204>; + first-cpu-idx = <0x10>; + num-cpu = <0x02>; + num-irq = <0x120>; + redist-region-count = <0x02>; + gpio-controller; + #gpio-cells = <0x01>; + phandle = <0x06>; + }; + }; + + tcm_core@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x35>; + + atcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0x35>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1eb>; + }; + + btcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0x35>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1ec>; + }; + + ctcm_rpu_core0@0x00000 { + compatible = "qemu:memory-region"; + container = <0x35>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1ed>; + }; + }; + + tcm_core@1 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x37>; + + atcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0x37>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1ee>; + }; + + btcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0x37>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1ef>; + }; + + ctcm_rpu_core1@0x00000 { + compatible = "qemu:memory-region"; + container = <0x37>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1f0>; + }; + }; + + tcm_core@2 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x39>; + + atcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0x39>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1f1>; + }; + + btcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0x39>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1f2>; + }; + + ctcm_rpu_core2@0x00000 { + compatible = "qemu:memory-region"; + container = <0x39>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1f3>; + }; + }; + + tcm_core@3 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x3b>; + + atcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3b>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1f4>; + }; + + btcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3b>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1f5>; + }; + + ctcm_rpu_core3@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3b>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1f6>; + }; + }; + + tcm_core@4 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x3d>; + + atcm_rpu_core4@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3d>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1f7>; + }; + + btcm_rpu_core4@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3d>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1f8>; + }; + + ctcm_rpu_core4@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3d>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1f9>; + }; + }; + + tcm_core@5 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x3f>; + + atcm_rpu_core5@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3f>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1fa>; + }; + + btcm_rpu_core5@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3f>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1fb>; + }; + + ctcm_rpu_core5@0x00000 { + compatible = "qemu:memory-region"; + container = <0x3f>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1fc>; + }; + }; + + tcm_core@6 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x41>; + + atcm_rpu_core6@0x00000 { + compatible = "qemu:memory-region"; + container = <0x41>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x1fd>; + }; + + btcm_rpu_core6@0x00000 { + compatible = "qemu:memory-region"; + container = <0x41>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x1fe>; + }; + + ctcm_rpu_core6@0x00000 { + compatible = "qemu:memory-region"; + container = <0x41>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x1ff>; + }; + }; + + tcm_core@7 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x43>; + + atcm_rpu_core7@0x00000 { + compatible = "qemu:memory-region"; + container = <0x43>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x200>; + }; + + btcm_rpu_core7@0x00000 { + compatible = "qemu:memory-region"; + container = <0x43>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x201>; + }; + + ctcm_rpu_core7@0x00000 { + compatible = "qemu:memory-region"; + container = <0x43>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x202>; + }; + }; + + tcm_core@8 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x45>; + + atcm_rpu_core8@0x00000 { + compatible = "qemu:memory-region"; + container = <0x45>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x203>; + }; + + btcm_rpu_core8@0x00000 { + compatible = "qemu:memory-region"; + container = <0x45>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x204>; + }; + + ctcm_rpu_core8@0x00000 { + compatible = "qemu:memory-region"; + container = <0x45>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x205>; + }; + }; + + tcm_core@9 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x47>; + + atcm_rpu_core9@0x00000 { + compatible = "qemu:memory-region"; + container = <0x47>; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x10000 0x00>; + phandle = <0x206>; + }; + + btcm_rpu_core9@0x00000 { + compatible = "qemu:memory-region"; + container = <0x47>; + qemu,ram = <0x01>; + reg = <0x00 0x10000 0x00 0x10000 0x00>; + phandle = <0x207>; + }; + + ctcm_rpu_core9@0x00000 { + compatible = "qemu:memory-region"; + container = <0x47>; + qemu,ram = <0x01>; + reg = <0x00 0x20000 0x00 0x10000 0x00>; + phandle = <0x208>; + }; + }; + + tcm_cluster_a@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x0f>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x35>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x37>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_b@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x10>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x39>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x3b>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_c@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x11>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x3d>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x3f>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_d@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x12>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x41>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x43>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + tcm_cluster_e@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "qemu:memory-region"; + phandle = <0x13>; + + tcm_core_0 { + compatible = "qemu:memory-region"; + alias = <0x45>; + reg = <0x00 0x00 0x00 0x40000 0x00>; + }; + + tcm_core_1 { + compatible = "qemu:memory-region"; + alias = <0x47>; + reg = <0x00 0x40000 0x00 0x40000 0x00>; + }; + }; + + amba_r5@2 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xe9>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x39>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic1 { + compatible = "qemu:memory-region"; + alias = <0x104>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@3 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xec>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x3b>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic1 { + compatible = "qemu:memory-region"; + alias = <0x104>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@4 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xef>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x3d>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic2 { + compatible = "qemu:memory-region"; + alias = <0x105>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@5 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xf2>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x3f>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic2 { + compatible = "qemu:memory-region"; + alias = <0x105>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@6 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xf5>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x41>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic3 { + compatible = "qemu:memory-region"; + alias = <0x106>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@7 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xf8>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x43>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic3 { + compatible = "qemu:memory-region"; + alias = <0x106>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@8 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xfb>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x45>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic4 { + compatible = "qemu:memory-region"; + alias = <0x107>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + amba_r5@9 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0xfe>; + + downstream_tcm { + compatible = "qemu:memory-region"; + alias = <0x47>; + reg = <0x00 0x00 0x00 0x400000 0x01>; + }; + + downstream_gic4 { + compatible = "qemu:memory-region"; + alias = <0x107>; + reg = <0x00 0xe2000000 0x00 0x140000 0x01>; + }; + + downstream_amba { + compatible = "qemu:memory-region"; + alias = <0xd0>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + rpu2_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xea>; + }; + + rpu3_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xed>; + }; + + rpu4_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xf0>; + }; + + rpu5_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xf3>; + }; + + rpu6_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xf6>; + }; + + rpu7_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xf9>; + }; + + rpu8_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x208>; + phandle = <0xfc>; + }; + + rpu9_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x20c>; + phandle = <0xff>; + }; + + usb1_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x231>; + phandle = <0x48>; + }; + + apu2_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x262>; + phandle = <0xd7>; + }; + + apu2_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x262>; + phandle = <0xd8>; + }; + + apu3_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x263>; + phandle = <0xd9>; + }; + + apu3_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x263>; + phandle = <0xda>; + }; + + apu4_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x268>; + phandle = <0xdb>; + }; + + apu4_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x268>; + phandle = <0xdc>; + }; + + apu5_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x269>; + phandle = <0xdd>; + }; + + apu5_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x269>; + phandle = <0xde>; + }; + + apu6_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x26a>; + phandle = <0xdf>; + }; + + apu6_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x26a>; + phandle = <0xe0>; + }; + + apu7_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x26b>; + phandle = <0xe1>; + }; + + apu7_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x26b>; + phandle = <0xe2>; + }; + + apu8_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x270>; + phandle = <0x209>; + }; + + apu8_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x270>; + phandle = <0x20a>; + }; + + apu9_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x271>; + phandle = <0x20b>; + }; + + apu9_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x271>; + phandle = <0x20c>; + }; + + apu10_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x272>; + phandle = <0x20d>; + }; + + apu10_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x272>; + phandle = <0x20e>; + }; + + apu11_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x273>; + phandle = <0x20f>; + }; + + apu11_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x273>; + phandle = <0x210>; + }; + + apu12_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x278>; + phandle = <0x211>; + }; + + apu12_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x278>; + phandle = <0x212>; + }; + + apu13_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x279>; + phandle = <0x213>; + }; + + apu13_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x279>; + phandle = <0x214>; + }; + + apu14_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x27a>; + phandle = <0x215>; + }; + + apu14_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x27a>; + phandle = <0x216>; + }; + + apu15_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x27b>; + phandle = <0x217>; + }; + + apu15_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x27b>; + phandle = <0x218>; + }; + + apu16_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x280>; + phandle = <0x219>; + }; + + apu16_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x280>; + phandle = <0x21a>; + }; + + apu17_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x281>; + phandle = <0x21b>; + }; + + apu17_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x281>; + phandle = <0x21c>; + }; + + apu18_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x282>; + phandle = <0x21d>; + }; + + apu18_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x282>; + phandle = <0x21e>; + }; + + apu19_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x283>; + phandle = <0x21f>; + }; + + apu19_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x283>; + phandle = <0x220>; + }; + + apu20_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x288>; + phandle = <0x221>; + }; + + apu20_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x288>; + phandle = <0x222>; + }; + + apu21_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x289>; + phandle = <0x223>; + }; + + apu21_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x289>; + phandle = <0x224>; + }; + + apu22_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x28a>; + phandle = <0x225>; + }; + + apu22_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x28a>; + phandle = <0x226>; + }; + + apu23_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x28b>; + phandle = <0x227>; + }; + + apu23_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x28b>; + phandle = <0x228>; + }; + + apu24_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x290>; + phandle = <0x229>; + }; + + apu24_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x290>; + phandle = <0x22a>; + }; + + apu25_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x291>; + phandle = <0x22b>; + }; + + apu25_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x291>; + phandle = <0x22c>; + }; + + apu26_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x292>; + phandle = <0x22d>; + }; + + apu26_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x292>; + phandle = <0x22e>; + }; + + apu27_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x293>; + phandle = <0x22f>; + }; + + apu27_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x293>; + phandle = <0x230>; + }; + + apu28_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x298>; + phandle = <0x231>; + }; + + apu28_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x298>; + phandle = <0x232>; + }; + + apu29_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x299>; + phandle = <0x233>; + }; + + apu29_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x299>; + phandle = <0x234>; + }; + + apu30_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x29a>; + phandle = <0x235>; + }; + + apu30_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x29a>; + phandle = <0x236>; + }; + + apu31_s_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x01>; + requester-id = <0x29b>; + phandle = <0x237>; + }; + + apu31_ns_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x29b>; + phandle = <0x238>; + }; + + asu_cpu_ma { + doc-ignore = <0x01>; + compatible = "qemu:memory-transaction-attr"; + secure = <0x00>; + requester-id = <0x00>; + phandle = <0x239>; + }; + + lmb_amba_asu@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + #priority-cells = <0x01>; + compatible = "simple-bus"; + ranges; + phandle = <0x23a>; + + main_bus_for_asu { + compatible = "qemu:memory-region"; + alias = <0xb4>; + reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>; + }; + }; + + ocm_mem@0xbbe00000 { + compatible = "qemu:memory-region"; + phandle = <0x0e>; + }; + + asu_data_ram_wrapper@0xebe40000 { + compatible = "qemu:memory-region"; + phandle = <0xbf>; + + asu_data_ram@0 { + compatible = "qemu:memory-region"; + device_type = "memory"; + qemu,ram = <0x01>; + reg = <0x00 0x00 0x00 0x20000 0x00>; + }; + }; + + psm_gic_proxy@0 { + #interrupt-cells = <0x03>; + interrupt-controller; + phandle = <0x23b>; + }; + + asu_cpu@0 { + #interrupt-cells = <0x01>; + phandle = <0xb5>; + }; + + __symbols__ { + pmc_ppu0_memattr = "/pmc_ppu0_ma"; + pmc_ppu1_memattr = "/pmc_ppu1_ma"; + psm_memattr = "/psm_ma"; + ddrmc_ub0_memattr = "/ddrmc_ub0_ma"; + ddrmc_ub1_memattr = "/ddrmc_ub1_ma"; + pmc_dma0_memattr = "/pmc_dma0_ma"; + pmc_dma1_memattr = "/pmc_dma1_ma"; + pmc_qspi_dma_memattr_smid = "/pmc_qspi_dma_ma_smid"; + pmc_qspi_dma_w_memattr_smid = "/pmc_qspi_dma_w_ma_smid"; + apu0_s_memattr = "/apu0_s_ma"; + apu0_ns_memattr = "/apu0_ns_ma"; + apu1_s_memattr = "/apu1_s_ma"; + apu1_ns_memattr = "/apu1_ns_ma"; + rpu0_s_memattr = "/rpu0_s_ma"; + rpu1_s_memattr = "/rpu1_s_ma"; + gem0_memattr_smid = "/gem0_ma_smid"; + gem0_w_memattr_smid = "/gem0_w_ma_smid"; + gem1_memattr_smid = "/gem1_ma_smid"; + gem1_w_memattr_smid = "/gem1_w_ma_smid"; + ospi_dma_memattr_smid = "/ospi_dma_ma_smid"; + ospi_dma_w_memattr_smid = "/ospi_dma_w_ma_smid"; + sd0_memattr_smid = "/sd0_ma_smid"; + sd0_w_memattr_smid = "/sd0_w_ma_smid"; + sd1_memattr_smid = "/sd1_ma_smid"; + sd1_w_memattr_smid = "/sd1_w_ma_smid"; + usb0_memattr = "/usb0_ma"; + amba_root = "/amba_root@0"; + amba = "/amba_root@0/amba@0"; + xmpu_ocm = "/amba_root@0/amba@0/xmpu_ocm@0"; + xmpu_ocm2 = "/amba_root@0/amba@0/xmpu_ocm2@0"; + loader_write_0xF1110880 = "/amba_root@0/amba@0/loader_write_cpu0_0x1@0xF1110880"; + loader_write_0xFD1A0050 = "/amba_root@0/amba@0/loader_write_cpu0_0x5@0xFD1A0050"; + loader_write_0xF111010C = "/amba_root@0/amba@0/loader_write_cpu0_0xFF@0xF111010C"; + s_axi_tcm_a = "/amba_root@0/amba@0/s_axi_tcm_a@0"; + s_axi_tcm_b = "/amba_root@0/amba@0/s_axi_tcm_b@0"; + s_axi_tcm_c = "/amba_root@0/amba@0/s_axi_tcm_c@0"; + s_axi_tcm_d = "/amba_root@0/amba@0/s_axi_tcm_d@0"; + s_axi_tcm_e = "/amba_root@0/amba@0/s_axi_tcm_e@0"; + loader_write_0xF12B0100 = "/amba_root@0/amba@0/loader_write_cpu0_0x80C@0xF12B0100"; + loader_write_0xF1260320 = "/amba_root@0/amba@0/loader_write_cpu0_0x77@0xF1260320"; + xmpu_ocm1 = "/amba_root@0/amba@0/xmpu_ocm1@0"; + xmpu_ocm3 = "/amba_root@0/amba@0/xmpu_ocm3@0"; + amba_lpd = "/amba_root@0/amba_lpd@0"; + xppu_lpd = "/amba_root@0/amba_lpd@0/xppu_lpd@0xeb990000"; + gem0 = "/amba_root@0/amba_lpd@0/ethernet@0xf1a60000"; + gem1 = "/amba_root@0/amba_lpd@0/ethernet@0xf1a70000"; + serial0 = "/amba_root@0/amba_lpd@0/serial@0xf1920000"; + serial1 = "/amba_root@0/amba_lpd@0/serial@0xf1930000"; + canfdbus0 = "/amba_root@0/amba_lpd@0/canfdbus@0"; + can0 = "/amba_root@0/amba_lpd@0/can@0xf19e0000"; + can1 = "/amba_root@0/amba_lpd@0/can@0xf19f0000"; + crl = "/amba_root@0/amba_lpd@0/crl@0xeb5e0000"; + lpd_iou_slcr = "/amba_root@0/amba_lpd@0/slcr@0xf1a20000"; + ipi = "/amba_root@0/amba_lpd@0/ipi@0xeb300000"; + spi0 = "/amba_root@0/amba_lpd@0/spi@0xf19c0000"; + spi0_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf19c0000/spi0_flash0@0"; + spi1 = "/amba_root@0/amba_lpd@0/spi@0xf19d0000"; + spi1_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf19d0000/spi1_flash0@0"; + dwc3_0 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI"; + ttc0 = "/amba_root@0/amba_lpd@0/timer@0xf1e60000"; + ttc1 = "/amba_root@0/amba_lpd@0/timer@0xf1e70000"; + ttc2 = "/amba_root@0/amba_lpd@0/timer@0xf1e80000"; + ttc3 = "/amba_root@0/amba_lpd@0/timer@0xf1e90000"; + adma0_mattr = "/amba_root@0/amba_lpd@0/adma0mattr"; + adma0 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd00000"; + adma1_mattr = "/amba_root@0/amba_lpd@0/adma1mattr"; + adma1 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd10000"; + adma2_mattr = "/amba_root@0/amba_lpd@0/adma2mattr"; + adma2 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd20000"; + adma3_mattr = "/amba_root@0/amba_lpd@0/adma3mattr"; + adma3 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd30000"; + adma4_mattr = "/amba_root@0/amba_lpd@0/adma4mattr"; + adma4 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd40000"; + adma5_mattr = "/amba_root@0/amba_lpd@0/adma5mattr"; + adma5 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd50000"; + adma6_mattr = "/amba_root@0/amba_lpd@0/adma6mattr"; + adma6 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd60000"; + adma7_mattr = "/amba_root@0/amba_lpd@0/adma7mattr"; + adma7 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd70000"; + ps_i2c0 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1940000"; + ps_i2c1 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1950000"; + ps_i2c2 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1960000"; + ps_i2c3 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1970000"; + ps_i2c4 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1980000"; + ps_i2c5 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf1990000"; + ps_i2c6 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf19a0000"; + ps_i2c7 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c@0xf19b0000"; + ocm_ctrl0 = "/amba_root@0/amba_lpd@0/ocm_ctrl@OCM"; + lpd_slcr = "/amba_root@0/amba_lpd@0/lpd_slcr@0xeb410000"; + lpd_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_slcr_secure@0xeb510000"; + lpd_iou_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_iou_slcr_secure@0xf1a40000"; + lpd_wwdt0 = "/amba_root@0/amba_lpd@0/wwdt@0xeb000000"; + lpd_gpio = "/amba_root@0/amba_lpd@0/lpd_gpio@0xf1a50000"; + rpu_ctrl = "/amba_root@0/amba_lpd@0/rpu_ctrl@0"; + rpu_ctrl_a = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb580000"; + rpu_ctrl_a0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a0@0xeb588000"; + rpu_ctrl_a1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a1@0xeb58c000"; + rpu_ctrl_b = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb590000"; + rpu_ctrl_b0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b0@0xeb598000"; + rpu_ctrl_b1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b1@0xeb59c000"; + rpu_ctrl_c = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5a0000"; + rpu_ctrl_c0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_c0@0xeb5a8000"; + rpu_ctrl_c1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_c1@0xeb5ac000"; + rpu_ctrl_d = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5b0000"; + rpu_ctrl_d0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_d0@0xeb5b8000"; + rpu_ctrl_d1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_d1@0xeb5bc000"; + rpu_ctrl_e = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb5c0000"; + rpu_ctrl_e0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_e0@0xeb5c8000"; + rpu_ctrl_e1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_e1@0xeb5cc000"; + dwc3_1 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI1"; + psx_i3c0 = "/amba_root@0/amba_lpd@0/i3c0@0xf1940000"; + psx_i3c1 = "/amba_root@0/amba_lpd@0/i3c1@0xf1950000"; + ocm_ctrl1 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeb960000"; + ocm_ctrl2 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeb9d0000"; + ocm_ctrl3 = "/amba_root@0/amba_lpd@0/ocm_ctrl@0xeaa00000"; + can2 = "/amba_root@0/amba_lpd@0/can@0xf1a00000"; + can3 = "/amba_root@0/amba_lpd@0/can@0xf1a10000"; + ttc4 = "/amba_root@0/amba_lpd@0/timer@0xf1ea0000"; + ttc5 = "/amba_root@0/amba_lpd@0/timer@0xf1eb0000"; + ttc6 = "/amba_root@0/amba_lpd@0/timer@0xf1ec0000"; + ttc7 = "/amba_root@0/amba_lpd@0/timer@0xf1ed0000"; + sdma0_mattr = "/amba_root@0/amba_lpd@0/sdma0mattr"; + sdma0 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd80000"; + sdma1_mattr = "/amba_root@0/amba_lpd@0/sdma1mattr"; + sdma1 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd90000"; + sdma2_mattr = "/amba_root@0/amba_lpd@0/sdma2mattr"; + sdma2 = "/amba_root@0/amba_lpd@0/dma-controller@0xebda0000"; + sdma3_mattr = "/amba_root@0/amba_lpd@0/sdma3mattr"; + sdma3 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdb0000"; + sdma4_mattr = "/amba_root@0/amba_lpd@0/sdma4mattr"; + sdma4 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdc0000"; + sdma5_mattr = "/amba_root@0/amba_lpd@0/sdma5mattr"; + sdma5 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdd0000"; + sdma6_mattr = "/amba_root@0/amba_lpd@0/sdma6mattr"; + sdma6 = "/amba_root@0/amba_lpd@0/dma-controller@0xebde0000"; + sdma7_mattr = "/amba_root@0/amba_lpd@0/sdma7mattr"; + sdma7 = "/amba_root@0/amba_lpd@0/dma-controller@0xebdf0000"; + lpd_wwdt1 = "/amba_root@0/amba_lpd@0/wwdt@0xeb010000"; + lpd_afi_fs = "/amba_root@0/amba_lpd@0/lpd_afi_fs@0xeb560000"; + amba_fpd = "/amba_root@0/amba_fpd@0"; + wwdt0 = "/amba_root@0/amba_fpd@0/watchdog@0xecc10000"; + apu_cluster0 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecc00000"; + apu_cluster1 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecd00000"; + apu_cluster2 = "/amba_root@0/amba_fpd@0/apu_cluster@0xece00000"; + apu_cluster3 = "/amba_root@0/amba_fpd@0/apu_cluster@0xecf00000"; + smmu = "/amba_root@0/amba_fpd@0/smmuv3@MM_FPD_SMMU"; + pcie = "/amba_root@0/amba_fpd@0/dummy_pcie@0x6_0000_0000"; + apu_pcil = "/amba_root@0/amba_fpd@0/apu_pcil@0xecb10000"; + fpd_afi_fs = "/amba_root@0/amba_fpd@0/lpd_afi_fs@0xec860000"; + mmi_gem_memattr = "/amba_root@0/amba_fpd@0/mmi_gem_ma"; + mmi_usb_memattr = "/amba_root@0/amba_fpd@0/mmi_usb_ma"; + amba_mmi = "/amba_root@0/amba_fpd@0/amba_mmi@0"; + mdio_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/mdio_10gbe@0"; + phy_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/mdio_10gbe@0/phy@1"; + mmi_10gbe = "/amba_root@0/amba_fpd@0/amba_mmi@0/ethernet@0xed920000"; + mmi_usb_drd = "/amba_root@0/amba_fpd@0/amba_mmi@0/usb_drd@0xedec0000"; + mmi_crx = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_crs@0xedc00000"; + mmi_pcsr = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_pcsr@0xeb2f0000"; + mmi_gtyp = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_gtyp@0xed900000"; + mmi_slcr_secure = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_slcr_sec@0"; + mmi_trng = "/amba_root@0/amba_fpd@0/amba_mmi@0/trng@0xede80000"; + mmi_udh_slcr = "/amba_root@0/amba_fpd@0/amba_mmi@0/udh_slcr@0xedea0000"; + mmi_udh_pll = "/amba_root@0/amba_fpd@0/amba_mmi@0/udh_pll@0xede90000"; + mmi_gpu_a = "/amba_root@0/amba_fpd@0/amba_mmi@0/mmi_gpu_a@0"; + loader_write_0xEDC30440 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC30440"; + loader_write_0xEDC30444 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x7F@0xEDC30444"; + loader_write_0xEDC3044c = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC3044c"; + loader_write_0xEDC30450 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC30450"; + loader_write_0xEDC30460 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC30460"; + loader_write_0xEDC30464 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x7f@0xEDC30464"; + loader_write_0xEDC3046c = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC3046c"; + loader_write_0xEDC30470 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x1@0xEDC30470"; + loader_write_0xED0A0098 = "/amba_root@0/amba_fpd@0/amba_mmi@0/ +loader_write_cpu0_0x3@0xED0A0098"; + amba_pmc_internal = "/amba_root@0/amba_pmc_internal@0"; + xmpu_pmc = "/amba_root@0/amba_pmc_internal@0/xmpu_pmc@0"; + xppu_pmc_npi = "/amba_root@0/amba_pmc_internal@0/xppu_pmc_npi@0xf1300000"; + xppu_pmc = "/amba_root@0/amba_pmc_internal@0/xppu_pmc@0xf1310000"; + amba_pmc = "/amba_root@0/amba_pmc@0"; + xmpu_pmc_cfu = "/amba_root@0/amba_pmc@0/xmpu_pmc_cfu@0xf1340000"; + pmx_err_mng = "/amba_root@0/amba_pmc@0/pmx_err_mng@0xf1110000"; + intpmxc_config = "/amba_root@0/amba_pmc@0/intpmxc_config@0xf1400000"; + amba_pmc_iou = "/amba_root@0/amba_pmc_iou@0"; + pmc_iou_slcr = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr@0xf1060000"; + pmc_iou_slcr_secure = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr_secure@0xf1070000"; + pmc_qspi_dma_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi_dma@QSPI_DMA"; + pmc_qspi_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000"; + qspi_flash_lcs_lb = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_lcs_lb@0"; + qspi_flash_lcs_ub = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_lcs_ub@0"; + qspi_flash_ucs_lb = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_ucs_lb@0"; + qspi_flash_ucs_ub = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/ +qspi_flash_ucs_ub@0"; + ospi_dma_dst = "/amba_root@0/amba_pmc_iou@0/ospi_dst_dma@0"; + ospi_dma_src = "/amba_root@0/amba_pmc_iou@0/ospi_src_dma@0"; + ospi = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000"; + ospi_flash_lcs_lb = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ +ospi_flash_lcs_lb@0"; + ospi_flash_lcs_ub = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ +ospi_flash_lcs_ub@0"; + ospi_flash_ucs_lb = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ +ospi_flash_ucs_lb@0"; + ospi_flash_ucs_ub = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000/ +ospi_flash_ucs_ub@0"; + gpio_mr_mux = "/amba_root@0/amba_pmc_iou@0/gpio_mr_mux@0xc0000000"; + pmc_gpio = "/amba_root@0/amba_pmc_iou@0/pmc_gpio@0xf1020000"; + sdhci0 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1040000"; + sdhci1 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1050000"; + pmc_tap = "/amba_root@0/amba_pmc_iou@0/pmc_tap@0xf11a0000"; + pmc_i2c = "/amba_root@0/amba_pmc_iou@0/pmc_i2c_wrapper/pmc_i2c@0xf1000000"; + pmx_wwdt = "/amba_root@0/amba_pmc_iou@0/wwdt@0xf03f0000"; + pmc_ufshc = "/amba_root@0/amba_pmc_iou@0/pmc_ufshc@0xf10b0000"; + unipro = "/amba_root@0/amba_pmc_iou@0/unipro@0"; + ufs_dev = "/amba_root@0/amba_pmc_iou@0/ufs_dev@0"; + ufs_reg = "/amba_root@0/amba_pmc_iou@0/ufs_reg@0xf1060000"; + amba_pmc_sec = "/amba_root@0/amba_pmc_sec@0"; + pmc_dma0_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_src@0"; + pmc_dma0_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_dst@0"; + pmc_dma1_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_src@0"; + pmc_dma1_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_dst@0"; + pmc_stream_switch = "/amba_root@0/amba_pmc_sec@0/pmc_stream_switch@0"; + pmc_sha3 = "/amba_root@0/amba_pmc_sec@0/pmc_sha@0xf1210000"; + pmc_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000"; + xlnx_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000/xlnx_aes@0"; + pmc_rsa = "/amba_root@0/amba_pmc_sec@0/pmc_rsa@0xf1200000"; + xlnx_pmc_efuse_cache = "/amba_root@0/amba_pmc_sec@0/ +xlnx_pmc_efuse_cache@0xf1250000"; + pmc_puf_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_puf_ctrl@0"; + pmc_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000"; + xlnx_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000/xlnx_efuse@0"; + pmc_bbram_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_bbram@0xf11f0000"; + pmc_sbi = "/amba_root@0/amba_pmc_sec@0/pmc_sbi@0xf1220000"; + pmc_sha3_1 = "/amba_root@0/amba_pmc_sec@0/pmc_sha1@0xF1800000"; + amba_pmc_ppu = "/amba_root@0/amba_pmc_ppu@0"; + pmc_gic_proxy = "/amba_root@0/amba_pmc_ppu@0/pmc_gic_proxy@0"; + amba_pmc_sys = "/amba_root@0/amba_pmc_sys@0"; + pmc_clk_rst = "/amba_root@0/amba_pmc_sys@0/pmc_clk_rst@0xf1260000"; + pmc_int = "/amba_root@0/amba_pmc_sys@0/pmc_int@0xf1400000"; + pmc_global = "/amba_root@0/amba_pmc_sys@0/pmc_global@0xf1110000"; + pmc_stream_zero = "/amba_root@0/amba_pmc_sys@0/pmc_stream_zero@"; + pmx_analog = "/amba_root@0/amba_pmc_sys@0/pmc_analog@0xf1160000"; + pmc_sysmon = "/amba_root@0/amba_pmc_sys@0/pmc_sysmon@0xf1270000"; + pmc_ams_sat0 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@0"; + pmc_ams_sat1 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@1"; + pmc_global_tamper = "/amba_root@0/amba_pmc_sys@0/versal_pmc_tamper@"; + lpd_sysmon_sat = "/amba_root@0/amba_pmc_sys@0/lpd_ams_sat@0"; + fpd_sysmon_sat0 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@0"; + fpd_sysmon_sat1 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@1"; + fpd_sysmon_sat2 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@2"; + fpd_sysmon_sat3 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@3"; + amba_pmc_pl = "/amba_root@0/amba_pmc_pl@0"; + noc_npi_nir = "/amba_root@0/amba_pmc_pl@0/noc_npi_nir@0xf6000000"; + npi_ddrmc_ub0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub0@0xf62c0000"; + npi_ddrmc_main0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main0@0xf6290000"; + npi_ddrmc_noc0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc0@0xf62a0000"; + npi_ddrmc_ub1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub1@0xf63b0000"; + npi_ddrmc_main1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main1@0xf6380000"; + npi_ddrmc_noc1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc1@0xf6390000"; + npi_ddrmc_ub2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub2@0xf6940000"; + npi_ddrmc_main2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main2@0xf6910000"; + npi_ddrmc_noc2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc2@0xf6920000"; + npi_ddrmc_ub3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub3@0xf6a20000"; + npi_ddrmc_main3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main3@0xf69f0000"; + npi_ddrmc_noc3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc3@0xf6a00000"; + npi_ddrmc_xmpu0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_xmpu0@0xf62a0000"; + npi_me = "/amba_root@0/amba_pmc_pl@0/npi_me@0xf6540000"; + npi_me0 = "/amba_root@0/amba_pmc_pl@0/npi_me@0xf6540000"; + noc_npi_devs = "/amba_root@0/amba_pmc_pl@0/noc_npi_devs@0"; + cfu_fdro = "/amba_root@0/amba_pmc_pl@0/cfu_fdro@0xf12c2000"; + cfu_sfr = "/amba_root@0/amba_pmc_pl@0/cfu_sfr@0xf12c1000"; + cframe0_reg = "/amba_root@0/amba_pmc_pl@0/cframe0_reg@0xf12d0000"; + cframe1_reg = "/amba_root@0/amba_pmc_pl@0/cframe1_reg@0xf12d2000"; + cframe2_reg = "/amba_root@0/amba_pmc_pl@0/cframe2_reg@0xf12d4000"; + cframe3_reg = "/amba_root@0/amba_pmc_pl@0/cframe3_reg@0xf12d6000"; + cframe4_reg = "/amba_root@0/amba_pmc_pl@0/cframe4_reg@0xf12d8000"; + cframe5_reg = "/amba_root@0/amba_pmc_pl@0/cframe5_reg@0xf12da000"; + cframe6_reg = "/amba_root@0/amba_pmc_pl@0/cframe6_reg@0xf12dc000"; + cframe7_reg = "/amba_root@0/amba_pmc_pl@0/cframe7_reg@0xf12de000"; + cframe8_reg = "/amba_root@0/amba_pmc_pl@0/cframe8_reg@0xf12e0000"; + cframe9_reg = "/amba_root@0/amba_pmc_pl@0/cframe9_reg@0xf12e2000"; + cframe10_reg = "/amba_root@0/amba_pmc_pl@0/cframe10_reg@0xf12e4000"; + cframe11_reg = "/amba_root@0/amba_pmc_pl@0/cframe11_reg@0xf12e6000"; + cframe12_reg = "/amba_root@0/amba_pmc_pl@0/cframe12_reg@0xf12e8000"; + cframe13_reg = "/amba_root@0/amba_pmc_pl@0/cframe13_reg@0xf12ea000"; + cframe14_reg = "/amba_root@0/amba_pmc_pl@0/cframe14_reg@0xf12ec000"; + cframe_bcast_reg = "/amba_root@0/amba_pmc_pl@0/cframe_bcast_reg@0xf12ee000"; + dummy_cfu_mem = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000"; + cfu = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000/cfu@0x0"; + amba_pmc_bat = "/amba_root@0/amba_pmc_bat@0"; + rtc = "/amba_root@0/amba_pmc_bat@0/rtc@0xf12a0000"; + amba_psm = "/amba_root@0/amba_psm@0"; + amba_xram = "/amba_root@0/amba_xram@0"; + crf = "/amba_root@0/crf@0xec200000"; + amba_asu_cpu = "/amba_root@0/amba_asu_cpu@0"; + amba_asu = "/amba_root@0/amba_asu@0"; + asu_iram = "/amba_root@0/amba_asu@0/asu_instr_ram@0xebe00000"; + asu_io_module = "/amba_root@0/amba_asu@0/io-module@0xebe80000"; + asu_io_intc = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_io_intc@0C"; + asu_io_gpi1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpi@20"; + asu_io_gpo1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpo@10"; + asu_io_gpo2 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_gpo@14"; + asu_io_pit1 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@40"; + asu_io_pit2 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@50"; + asu_io_pit3 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@60"; + asu_io_pit4 = "/amba_root@0/amba_asu@0/io-module@0xebe80000/asu_pit@70"; + asu_mdm_uart = "/amba_root@0/amba_asu@0/asu_mdm_uart@0xebef0000"; + asu_global = "/amba_root@0/amba_asu@0/asu_global@0xebf80000"; + asu_global_pmc = "/amba_root@0/amba_asu@0/asu_global_pmc@0xebf80000"; + asu_local = "/amba_root@0/amba_asu@0/asu_local@0xebe8e000"; + asu_sss = "/amba_root@0/amba_asu@0/asu_sss@0xebe8e000"; + asu_dma_src = "/amba_root@0/amba_asu@0/asu_dma_src@0xebe8c000"; + asu_dma_dst = "/amba_root@0/amba_asu@0/asu_dma_dst@0xebe8c000"; + asu_dma1_src = "/amba_root@0/amba_asu@0/asu_dma1_src@0xebe8d000"; + asu_dma1_dst = "/amba_root@0/amba_asu@0/asu_dma1_dst@0xebe8d000"; + asu_xmpu = "/amba_root@0/amba_asu@0/asu_xmpu@0xebf60000"; + asu_aes = "/amba_root@0/amba_asu@0/asu_aes@0xebe88000"; + asu_kv = "/amba_root@0/amba_asu@0/asu_kv@0xebe8a000"; + asu_sha3 = "/amba_root@0/amba_asu@0/asu_sha3@0xebf40000"; + asu_sha2 = "/amba_root@0/amba_asu@0/asu_sha2@0xebf30000"; + asu_rsa = "/amba_root@0/amba_asu@0/pmc_rsa@0xebf50000"; + asu_trng = "/amba_root@0/amba_asu@0/trng@0xebf20000"; + asu_ecc = "/amba_root@0/amba_asu@0/asu_ecc@0xebf00000"; + lmb_pmc_ppu0 = "/lmb_pmc_ppu0@0"; + pmc_rom = "/lmb_pmc_ppu0@0/pmc_rom@0xf0000000"; + pmc_ppu0_ram = "/lmb_pmc_ppu0@0/ppu0_ram@0xf0060000"; + pmc_ppu0_io_module = "/lmb_pmc_ppu0@0/io-module@00"; + pmc_ppu0_io_intc = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_intc@0C"; + pmc_ppu0_io_gpi1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@20"; + pmc_ppu0_io_gpi2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@24"; + pmc_ppu0_io_gpi3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@28"; + pmc_ppu0_io_gpi4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@2c"; + pmc_ppu0_io_gpo1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@10"; + pmc_ppu0_io_gpo2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@14"; + pmc_ppu0_io_gpo3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@18"; + pmc_ppu0_io_gpo4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@1c"; + pmc_ppu0_io_pit1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@40"; + pmc_ppu0_io_pit2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@50"; + pmc_ppu0_io_pit3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@60"; + pmc_ppu0_io_pit4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@70"; + lmb_pmc_ppu1 = "/lmb_pmc_ppu1@0"; + pmc_ppu1_io_module = "/lmb_pmc_ppu1@0/io-module@00"; + pmc_ppu1_io_intc = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_intc@0C"; + pmc_ppu1_io_gpi1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@20"; + pmc_ppu1_io_gpi2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@24"; + pmc_ppu1_io_gpi3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@28"; + pmc_ppu1_io_gpi4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@2c"; + pmc_ppu1_io_gpo1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@10"; + pmc_ppu1_io_gpo2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@14"; + pmc_ppu1_io_gpo3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@18"; + pmc_ppu1_io_gpo4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@1c"; + pmc_ppu1_io_pit1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@40"; + pmc_ppu1_io_pit2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@50"; + pmc_ppu1_io_pit3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@60"; + pmc_ppu1_io_pit4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@70"; + lmb_psm = "/lmb_psm@0"; + lmb_ddrmc0 = "/lmb_ddrmc@0"; + ddrmc0_ram_data = "/lmb_ddrmc@0/ddrmc0_ram_data@0x1c000"; + ddrmc0_ram_instr = "/lmb_ddrmc@0/ddrmc0_ram_instr@0x20000"; + ddrmc0_ram_exchange = "/lmb_ddrmc@0/ddrmc0_ram_exchange@0x08000"; + ddrmc_0_io_module = "/lmb_ddrmc@0/io-module@00"; + ddrmc0_io_intc = "/lmb_ddrmc@0/io-module@00/ddrmc0_intc@0C"; + ddrmc0_io_gpo1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_gpo@10"; + ddrmc0_io_pit1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@40"; + ddrmc0_io_pit2 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@50"; + ddrmc0_io_pit3 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@60"; + ddrmc0_io_pit4 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@70"; + ddrmc_uart0 = "/lmb_ddrmc@0/ddrmc_uart0@0"; + lmb_ddrmc1 = "/lmb_ddrmc@1"; + ddrmc1_ram_data = "/lmb_ddrmc@1/ddrmc1_ram_data@0x1c000"; + ddrmc1_ram_instr = "/lmb_ddrmc@1/ddrmc1_ram_instr@0x20000"; + ddrmc1_ram_exchange = "/lmb_ddrmc@1/ddrmc1_ram_exchange@0x08000"; + amba_rpu = "/amba_rpu@0"; + amba_r5_0 = "/amba_r5@0"; + amba_r5_1 = "/amba_r5@1"; + dummy1 = "/dummy1@0"; + smmu_tbu0 = "/tbu0_slave@0"; + smmu_tbu1 = "/tbu1_slave@0"; + smmu_tbu2 = "/tbu2_slave@0"; + smmu_tbu3 = "/tbu3_slave@0"; + smmu_tbu4 = "/tbu4_slave@0"; + smmu_tbu5 = "/tbu5_slave@0"; + smmu_tbu6 = "/tbu6_slave@0"; + ddr_mem = "/memory@00000000"; + ddr_2_mem = "/memory@8_0000_0000"; + ddr_3_mem = "/memory@0x50000000000ULL"; + ocm_mem_bank_0 = "/ocm_mem_bank_0@"; + ocm_mem_bank_1 = "/ocm_mem_bank_1@"; + ocm_mem_bank_2 = "/ocm_mem_bank_2@"; + ocm_mem_bank_3 = "/ocm_mem_bank_3@"; + xram_mem = "/xram_mem@0xbbe00000"; + ipi_msgbuf = "/ipi_msgbuf@0"; + pmc_ram = "/pmc_ram@0xf2000000"; + pmc_ram_bank_0 = "/pmc_ram_bank_0@0x0"; + pmc_ppu1_insn_ram = "/pmc_ppu1_ram@0xf0200000"; + pmc_ppu1_data_ram = "/pmc_ppu1_ram@0xf0280000"; + lqspi_mr = "/lqspi_mr@0"; + lospi_mr = "/lospi_mr@0"; + cpu0 = "/cpus/apu_cpu@0"; + cpu1 = "/cpus/apu_cpu@1"; + cpu2 = "/cpus/apu_cpu@2"; + cpu3 = "/cpus/apu_cpu@3"; + cpu4 = "/cpus/apu_cpu@4"; + cpu5 = "/cpus/apu_cpu@5"; + cpu6 = "/cpus/apu_cpu@6"; + cpu7 = "/cpus/apu_cpu@7"; + rpu_a = "/cpus/rpu_a@0"; + rpu_cpu0 = "/cpus/rpu_a@0/rpu_cpu_a@0"; + rpu_cpu1 = "/cpus/rpu_a@0/rpu_cpu_a@1"; + rpu_b = "/cpus/rpu_b@0"; + rpu_cpu2 = "/cpus/rpu_b@0/rpu_cpu_b@0"; + rpu_cpu3 = "/cpus/rpu_b@0/rpu_cpu_b@1"; + rpu_c = "/cpus/rpu_c@0"; + rpu_cpu4 = "/cpus/rpu_c@0/rpu_cpu_c@0"; + rpu_cpu5 = "/cpus/rpu_c@0/rpu_cpu_c@1"; + rpu_d = "/cpus/rpu_d@0"; + rpu_cpu6 = "/cpus/rpu_d@0/rpu_cpu_d@0"; + rpu_cpu7 = "/cpus/rpu_d@0/rpu_cpu_d@1"; + rpu_e = "/cpus/rpu_e@0"; + rpu_cpu8 = "/cpus/rpu_e@0/rpu_cpu_e@0"; + rpu_cpu9 = "/cpus/rpu_e@0/rpu_cpu_e@1"; + amba_apu = "/amba_apu@0"; + timer = "/amba_apu@0/timer"; + amba_apu_gic = "/amba_apu_gic@0"; + gic = "/amba_apu_gic@0/interrupt-controller@0xe2000000"; + amba_alias = "/amba_alias@0"; + qemu_sysmem = "/qemu_sysmem@0"; + psm0 = "/dummy_ppu0@0"; + pmc_ppu0 = "/dummy_ppu0@0"; + pmc_ppu1 = "/dummy_ppu1@0"; + ddrmc_ub0 = "/dummy_ddrmc0@0"; + ddrmc_ub1 = "/dummy_ddrmc1@0"; + ddr = "/ddr@0x00000000"; + ddr_2 = "/ddr_2@0x800000000ULL"; + mdio0 = "/mdio"; + phy0 = "/mdio/phy@1"; + phy1 = "/mdio/phy@2"; + cpunone = "/cpu_dummy"; + smmu_tbu7 = "/tbu7_slave@0"; + smmu_tbu8 = "/tbu8_slave@0"; + smmu_tbu9 = "/tbu9_slave@0"; + smmu_tbu10 = "/tbu10_slave@0"; + smmu_tbu11 = "/tbu11_slave@0"; + smmu_tbu12 = "/tbu12_slave@0"; + mr_rpu_gic_a = "/mr_rpu_gic_a@0"; + rpu_gic_a = "/mr_rpu_gic_a@0/rpu_gic_a@0x0"; + mr_rpu_gic_b = "/mr_rpu_gic_b@0"; + rpu_gic_b = "/mr_rpu_gic_b@0/rpu_gic_b@0x0"; + mr_rpu_gic_c = "/mr_rpu_gic_c@0"; + rpu_gic_c = "/mr_rpu_gic_c@0/rpu_gic_c@0x0"; + mr_rpu_gic_d = "/mr_rpu_gic_d@0"; + rpu_gic_d = "/mr_rpu_gic_d@0/rpu_gic_d@0x0"; + mr_rpu_gic_e = "/mr_rpu_gic_e@0"; + rpu_gic_e = "/mr_rpu_gic_e@0/rpu_gic_e@0x0"; + tcm_core0 = "/tcm_core@0"; + atcm_rpu_core0 = "/tcm_core@0/atcm_rpu_core0@0x00000"; + btcm_rpu_core0 = "/tcm_core@0/btcm_rpu_core0@0x00000"; + ctcm_rpu_core0 = "/tcm_core@0/ctcm_rpu_core0@0x00000"; + tcm_core1 = "/tcm_core@1"; + atcm_rpu_core1 = "/tcm_core@1/atcm_rpu_core1@0x00000"; + btcm_rpu_core1 = "/tcm_core@1/btcm_rpu_core1@0x00000"; + ctcm_rpu_core1 = "/tcm_core@1/ctcm_rpu_core1@0x00000"; + tcm_core2 = "/tcm_core@2"; + atcm_rpu_core2 = "/tcm_core@2/atcm_rpu_core2@0x00000"; + btcm_rpu_core2 = "/tcm_core@2/btcm_rpu_core2@0x00000"; + ctcm_rpu_core2 = "/tcm_core@2/ctcm_rpu_core2@0x00000"; + tcm_core3 = "/tcm_core@3"; + atcm_rpu_core3 = "/tcm_core@3/atcm_rpu_core3@0x00000"; + btcm_rpu_core3 = "/tcm_core@3/btcm_rpu_core3@0x00000"; + ctcm_rpu_core3 = "/tcm_core@3/ctcm_rpu_core3@0x00000"; + tcm_core4 = "/tcm_core@4"; + atcm_rpu_core4 = "/tcm_core@4/atcm_rpu_core4@0x00000"; + btcm_rpu_core4 = "/tcm_core@4/btcm_rpu_core4@0x00000"; + ctcm_rpu_core4 = "/tcm_core@4/ctcm_rpu_core4@0x00000"; + tcm_core5 = "/tcm_core@5"; + atcm_rpu_core5 = "/tcm_core@5/atcm_rpu_core5@0x00000"; + btcm_rpu_core5 = "/tcm_core@5/btcm_rpu_core5@0x00000"; + ctcm_rpu_core5 = "/tcm_core@5/ctcm_rpu_core5@0x00000"; + tcm_core6 = "/tcm_core@6"; + atcm_rpu_core6 = "/tcm_core@6/atcm_rpu_core6@0x00000"; + btcm_rpu_core6 = "/tcm_core@6/btcm_rpu_core6@0x00000"; + ctcm_rpu_core6 = "/tcm_core@6/ctcm_rpu_core6@0x00000"; + tcm_core7 = "/tcm_core@7"; + atcm_rpu_core7 = "/tcm_core@7/atcm_rpu_core7@0x00000"; + btcm_rpu_core7 = "/tcm_core@7/btcm_rpu_core7@0x00000"; + ctcm_rpu_core7 = "/tcm_core@7/ctcm_rpu_core7@0x00000"; + tcm_core8 = "/tcm_core@8"; + atcm_rpu_core8 = "/tcm_core@8/atcm_rpu_core8@0x00000"; + btcm_rpu_core8 = "/tcm_core@8/btcm_rpu_core8@0x00000"; + ctcm_rpu_core8 = "/tcm_core@8/ctcm_rpu_core8@0x00000"; + tcm_core9 = "/tcm_core@9"; + atcm_rpu_core9 = "/tcm_core@9/atcm_rpu_core9@0x00000"; + btcm_rpu_core9 = "/tcm_core@9/btcm_rpu_core9@0x00000"; + ctcm_rpu_core9 = "/tcm_core@9/ctcm_rpu_core9@0x00000"; + tcm_cluster_a = "/tcm_cluster_a@0"; + tcm_cluster_b = "/tcm_cluster_b@0"; + tcm_cluster_c = "/tcm_cluster_c@0"; + tcm_cluster_d = "/tcm_cluster_d@0"; + tcm_cluster_e = "/tcm_cluster_e@0"; + amba_r5_2 = "/amba_r5@2"; + amba_r5_3 = "/amba_r5@3"; + amba_r5_4 = "/amba_r5@4"; + amba_r5_5 = "/amba_r5@5"; + amba_r5_6 = "/amba_r5@6"; + amba_r5_7 = "/amba_r5@7"; + amba_r5_8 = "/amba_r5@8"; + amba_r5_9 = "/amba_r5@9"; + rpu2_s_memattr = "/rpu2_s_ma"; + rpu3_s_memattr = "/rpu3_s_ma"; + rpu4_s_memattr = "/rpu4_s_ma"; + rpu5_s_memattr = "/rpu5_s_ma"; + rpu6_s_memattr = "/rpu6_s_ma"; + rpu7_s_memattr = "/rpu7_s_ma"; + rpu8_s_memattr = "/rpu8_s_ma"; + rpu9_s_memattr = "/rpu9_s_ma"; + usb1_memattr = "/usb1_ma"; + apu2_s_memattr = "/apu2_s_ma"; + apu2_ns_memattr = "/apu2_ns_ma"; + apu3_s_memattr = "/apu3_s_ma"; + apu3_ns_memattr = "/apu3_ns_ma"; + apu4_s_memattr = "/apu4_s_ma"; + apu4_ns_memattr = "/apu4_ns_ma"; + apu5_s_memattr = "/apu5_s_ma"; + apu5_ns_memattr = "/apu5_ns_ma"; + apu6_s_memattr = "/apu6_s_ma"; + apu6_ns_memattr = "/apu6_ns_ma"; + apu7_s_memattr = "/apu7_s_ma"; + apu7_ns_memattr = "/apu7_ns_ma"; + apu8_s_memattr = "/apu8_s_ma"; + apu8_ns_memattr = "/apu8_ns_ma"; + apu9_s_memattr = "/apu9_s_ma"; + apu9_ns_memattr = "/apu9_ns_ma"; + apu10_s_memattr = "/apu10_s_ma"; + apu10_ns_memattr = "/apu10_ns_ma"; + apu11_s_memattr = "/apu11_s_ma"; + apu11_ns_memattr = "/apu11_ns_ma"; + apu12_s_memattr = "/apu12_s_ma"; + apu12_ns_memattr = "/apu12_ns_ma"; + apu13_s_memattr = "/apu13_s_ma"; + apu13_ns_memattr = "/apu13_ns_ma"; + apu14_s_memattr = "/apu14_s_ma"; + apu14_ns_memattr = "/apu14_ns_ma"; + apu15_s_memattr = "/apu15_s_ma"; + apu15_ns_memattr = "/apu15_ns_ma"; + apu16_s_memattr = "/apu16_s_ma"; + apu16_ns_memattr = "/apu16_ns_ma"; + apu17_s_memattr = "/apu17_s_ma"; + apu17_ns_memattr = "/apu17_ns_ma"; + apu18_s_memattr = "/apu18_s_ma"; + apu18_ns_memattr = "/apu18_ns_ma"; + apu19_s_memattr = "/apu19_s_ma"; + apu19_ns_memattr = "/apu19_ns_ma"; + apu20_s_memattr = "/apu20_s_ma"; + apu20_ns_memattr = "/apu20_ns_ma"; + apu21_s_memattr = "/apu21_s_ma"; + apu21_ns_memattr = "/apu21_ns_ma"; + apu22_s_memattr = "/apu22_s_ma"; + apu22_ns_memattr = "/apu22_ns_ma"; + apu23_s_memattr = "/apu23_s_ma"; + apu23_ns_memattr = "/apu23_ns_ma"; + apu24_s_memattr = "/apu24_s_ma"; + apu24_ns_memattr = "/apu24_ns_ma"; + apu25_s_memattr = "/apu25_s_ma"; + apu25_ns_memattr = "/apu25_ns_ma"; + apu26_s_memattr = "/apu26_s_ma"; + apu26_ns_memattr = "/apu26_ns_ma"; + apu27_s_memattr = "/apu27_s_ma"; + apu27_ns_memattr = "/apu27_ns_ma"; + apu28_s_memattr = "/apu28_s_ma"; + apu28_ns_memattr = "/apu28_ns_ma"; + apu29_s_memattr = "/apu29_s_ma"; + apu29_ns_memattr = "/apu29_ns_ma"; + apu30_s_memattr = "/apu30_s_ma"; + apu30_ns_memattr = "/apu30_ns_ma"; + apu31_s_memattr = "/apu31_s_ma"; + apu31_ns_memattr = "/apu31_ns_ma"; + asu_cpu_memattr = "/asu_cpu_ma"; + lmb_amba_asu = "/lmb_amba_asu@0"; + ocm_mem = "/ocm_mem@0xbbe00000"; + asu_dram = "/asu_data_ram_wrapper@0xebe40000"; + psm_gic_proxy = "/psm_gic_proxy@0"; + asu_cpu = "/asu_cpu@0"; + }; +}; diff --git a/boards/amd/versal2_rpu/versal2_rpu.dts b/boards/amd/versal2_rpu/versal2_rpu.dts new file mode 100644 index 00000000000..36e8c2ed7e9 --- /dev/null +++ b/boards/amd/versal2_rpu/versal2_rpu.dts @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,ocm = &ocm; + }; +}; + +&cpu0 { + clock-frequency = <100000000>; +}; + +&soc { + sram0: memory@30000 { + compatible = "mmio-sram"; + reg = <0x30000 0x7ffd0000>; + }; +}; + +&ocm { + status = "okay"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <100000000>; +}; diff --git a/boards/amd/versal2_rpu/versal2_rpu.yaml b/boards/amd/versal2_rpu/versal2_rpu.yaml new file mode 100644 index 00000000000..91753bea822 --- /dev/null +++ b/boards/amd/versal2_rpu/versal2_rpu.yaml @@ -0,0 +1,13 @@ +identifier: versal2_rpu +name: AMD Development board for Versal Gen 2 RPU +arch: arm +toolchain: + - zephyr +supported: + - scsi + - ufs +testing: + ignore_tags: + - net + - bluetooth +vendor: amd diff --git a/boards/amd/versal2_rpu/versal2_rpu_defconfig b/boards/amd/versal2_rpu/versal2_rpu_defconfig new file mode 100644 index 00000000000..ed6209ff2af --- /dev/null +++ b/boards/amd/versal2_rpu/versal2_rpu_defconfig @@ -0,0 +1,13 @@ +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_PL011=y + +# Enable cache and arch timer +CONFIG_CACHE_MANAGEMENT=y +CONFIG_ARM_ARCH_TIMER=y diff --git a/boards/amd/versalnet_rpu/versalnet_rpu.dts b/boards/amd/versalnet_rpu/versalnet_rpu.dts index 73d034e20cb..f9ff1722567 100644 --- a/boards/amd/versalnet_rpu/versalnet_rpu.dts +++ b/boards/amd/versalnet_rpu/versalnet_rpu.dts @@ -14,6 +14,12 @@ zephyr,shell-uart = &uart0; zephyr,ocm = &ocm; }; + + sdhci_ref_clk: sdhci-ref-clk { + compatible = "fixed-clock"; + clock-frequency = <200000000>; + #clock-cells = <0>; + }; }; &cpu0 { @@ -42,3 +48,14 @@ current-speed = <115200>; clock-frequency = <100000000>; }; + +&sdhci0 { + status = "okay"; + power-delay-ms = <10>; + clocks = <&sdhci_ref_clk>; +}; + +&sdhci1 { + status = "okay"; + clocks = <&sdhci_ref_clk>; +}; diff --git a/boards/amd/versalnet_rpu/versalnet_rpu.yaml b/boards/amd/versalnet_rpu/versalnet_rpu.yaml index eccdf0ae37b..21f19ea6cce 100644 --- a/boards/amd/versalnet_rpu/versalnet_rpu.yaml +++ b/boards/amd/versalnet_rpu/versalnet_rpu.yaml @@ -8,3 +8,5 @@ testing: - net - bluetooth vendor: amd +supported: + - sdhc diff --git a/boards/arduino/mkrzero/arduino_mkr_connector.dtsi b/boards/arduino/mkrzero/arduino_mkr_connector.dtsi index 0f16581d8b8..0fba02ef759 100644 --- a/boards/arduino/mkrzero/arduino_mkr_connector.dtsi +++ b/boards/arduino/mkrzero/arduino_mkr_connector.dtsi @@ -3,34 +3,36 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + / { arduino_mkr_header: connector { compatible = "arduino-mkr-header"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &porta 22 0>, /* D0 */ - <1 0 &porta 23 0>, /* D1 */ - <2 0 &porta 10 0>, /* D2 */ - <3 0 &porta 11 0>, /* D3 */ - <4 0 &portb 10 0>, /* D4 */ - <5 0 &portb 11 0>, /* D5 */ - <6 0 &porta 20 0>, /* D6 */ - <7 0 &porta 21 0>, /* D7 */ - <8 0 &porta 16 0>, /* D8 / SPI-COPI */ - <9 0 &porta 17 0>, /* D9 / SPI-SCK */ - <10 0 &porta 19 0>, /* D10 / SPI-CIPO */ - <11 0 &porta 8 0>, /* D11 / I2C-SDA */ - <12 0 &porta 9 0>, /* D12 / I2C-SCL */ - <13 0 &portb 23 0>, /* D13 / UART-RX */ - <14 0 &portb 22 0>, /* D14 / UART-TX */ - <15 0 &porta 2 0>, /* D15 / A0 */ - <16 0 &portb 2 0>, /* D16 / A1 */ - <17 0 &portb 3 0>, /* D17 / A2 */ - <18 0 &porta 4 0>, /* D18 / A3 */ - <19 0 &porta 5 0>, /* D19 / A4 */ - <20 0 &porta 6 0>, /* D20 / A5 */ - <21 0 &porta 7 0>; /* D21 / A6 */ + gpio-map = , /* D0 */ + , /* D1 */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 / SPI-COPI */ + , /* D9 / SPI-SCK */ + , /* D10 / SPI-CIPO */ + , /* D11 / I2C-SDA */ + , /* D12 / I2C-SCL */ + , /* D13 / UART-RX */ + , /* D14 / UART-TX */ + , /* D15 / A0 */ + , /* D16 / A1 */ + , /* D17 / A2 */ + , /* D18 / A3 */ + , /* D19 / A4 */ + , /* D20 / A5 */ + ; /* D21 / A6 */ }; }; diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts b/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts index 598d206bd31..03963cfe009 100644 --- a/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts @@ -7,7 +7,7 @@ #include #include "arduino_nano_33_ble-common.dtsi" #include "arduino_nano_33_ble-pinctrl.dtsi" -#include "arduino_nano_r3_connector.dtsi" +#include "arduino_nano_connector.dtsi" / { model = "Arduino Nano 33 BLE"; diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts index e5b18d2b120..1593360220d 100644 --- a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts @@ -7,7 +7,7 @@ #include #include "arduino_nano_33_ble-common.dtsi" #include "arduino_nano_33_ble-pinctrl.dtsi" -#include "arduino_nano_r3_connector.dtsi" +#include "arduino_nano_connector.dtsi" / { model = "Arduino Nano 33 BLE Sense"; diff --git a/boards/arduino/nano_33_ble/arduino_nano_connector.dtsi b/boards/arduino/nano_33_ble/arduino_nano_connector.dtsi new file mode 100644 index 00000000000..bec8b3b8775 --- /dev/null +++ b/boards/arduino/nano_33_ble/arduino_nano_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 Huawei Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + arduino_nano_header: connector { + compatible = "arduino-nano-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , /* D0 / UART-TX */ + , /* D1 / UART-RX */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 */ + , /* D9 */ + , /* D10 */ + , /* D11 / SPI-MOSI */ + , /* D12 / SPI-MISO */ + , /* D13 / SPI-SCK */ + , /* D14 / A0 */ + , /* D15 / A1 */ + , /* D16 / A2 */ + , /* D17 / A3 */ + , /* D18 / A4 / I2C-SDA */ + , /* D19 / A5 / I2C-SCL */ + , /* D20 / A6 */ + ; /* D21 / A7 */ + }; +}; + +arduino_nano_i2c: &i2c0 {}; +arduino_nano_spi: &spi2 {}; +arduino_nano_serial: &uart0 {}; diff --git a/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi deleted file mode 100644 index af20cc6c755..00000000000 --- a/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2022 Huawei Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - arduino_nano_header: connector { - compatible = "arduino-nano-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 3 0>, /* D0 / UART-TX */ - <1 0 &gpio1 10 0>, /* D1 / UART-RX */ - <2 0 &gpio1 11 0>, /* D2 */ - <3 0 &gpio1 12 0>, /* D3 */ - <4 0 &gpio1 15 0>, /* D4 */ - <5 0 &gpio1 13 0>, /* D5 */ - <6 0 &gpio1 14 0>, /* D6 */ - <7 0 &gpio0 23 0>, /* D7 */ - <8 0 &gpio0 21 0>, /* D8 */ - <9 0 &gpio0 27 0>, /* D9 */ - <10 0 &gpio1 2 0>, /* D10 */ - <11 0 &gpio1 1 0>, /* D11 / SPI-MOSI */ - <12 0 &gpio1 8 0>, /* D12 / SPI-MISO */ - <13 0 &gpio0 13 0>, /* D13 / SPI-SCK */ - <14 0 &gpio0 4 0>, /* D14 / A0 */ - <15 0 &gpio0 5 0>, /* D15 / A1 */ - <16 0 &gpio0 30 0>, /* D16 / A2 */ - <17 0 &gpio0 29 0>, /* D17 / A3 */ - <18 0 &gpio0 31 0>, /* D18 / A4 / I2C-SDA */ - <19 0 &gpio0 2 0>, /* D19 / A5 / I2C-SCL */ - <20 0 &gpio0 28 0>, /* D20 / A6 */ - <21 0 &gpio0 3 0>; /* D21 / A7 */ - }; -}; - -arduino_nano_i2c: &i2c0 {}; -arduino_nano_spi: &spi2 {}; -arduino_nano_serial: &uart0 {}; diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts index 7a8e3b7e745..f3af145110b 100644 --- a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts +++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts @@ -8,7 +8,7 @@ #include #include #include "arduino_nano_33_iot-pinctrl.dtsi" -#include "arduino_nano_r3_connector.dtsi" +#include "arduino_nano_connector.dtsi" / { model = "Arduino Nano 33 IOT"; diff --git a/boards/arduino/nano_33_iot/arduino_nano_connector.dtsi b/boards/arduino/nano_33_iot/arduino_nano_connector.dtsi new file mode 100644 index 00000000000..697e5684403 --- /dev/null +++ b/boards/arduino/nano_33_iot/arduino_nano_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 Joylab AG + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + arduino_nano_header: connector { + compatible = "arduino-nano-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , /* D0 / UART-RX */ + , /* D1 / UART-TX */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 */ + , /* D9 */ + , /* D10 */ + , /* D11 / SPI-MOSI */ + , /* D12 / SPI-MISO */ + , /* D13 / SPI-SCK */ + , /* D14 / A0 */ + , /* D15 / A1 */ + , /* D16 / A2 */ + , /* D17 / A3 */ + , /* D18 / A4 / I2C-SDA */ + , /* D19 / A5 / I2C-SCL */ + , /* D20 / A6 */ + ; /* D21 / A7 */ + }; +}; + +arduino_nano_i2c: &sercom4 {}; +arduino_nano_spi: &sercom1 {}; +arduino_nano_serial: &sercom5 {}; diff --git a/boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi deleted file mode 100644 index 9c69abdcacb..00000000000 --- a/boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2022 Joylab AG - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - arduino_nano_header: connector { - compatible = "arduino-nano-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &portb 23 0>, /* D0 / UART-RX */ - <1 0 &portb 22 0>, /* D1 / UART-TX */ - <2 0 &portb 10 0>, /* D2 */ - <3 0 &portb 11 0>, /* D3 */ - <4 0 &porta 7 0>, /* D4 */ - <5 0 &porta 5 0>, /* D5 */ - <6 0 &porta 4 0>, /* D6 */ - <7 0 &porta 6 0>, /* D7 */ - <8 0 &porta 18 0>, /* D8 */ - <9 0 &porta 20 0>, /* D9 */ - <10 0 &porta 21 0>, /* D10 */ - <11 0 &porta 16 0>, /* D11 / SPI-MOSI */ - <12 0 &porta 19 0>, /* D12 / SPI-MISO */ - <13 0 &porta 17 0>, /* D13 / SPI-SCK */ - <14 0 &porta 2 0>, /* D14 / A0 */ - <15 0 &portb 2 0>, /* D15 / A1 */ - <16 0 &porta 11 0>, /* D16 / A2 */ - <17 0 &porta 10 0>, /* D17 / A3 */ - <18 0 &portb 8 0>, /* D18 / A4 / I2C-SDA */ - <19 0 &portb 9 0>, /* D19 / A5 / I2C-SCL */ - <20 0 &porta 9 0>, /* D20 / A6 */ - <21 0 &portb 3 0>; /* D21 / A7 */ - }; -}; - -arduino_nano_i2c: &sercom4 {}; -arduino_nano_spi: &sercom1 {}; -arduino_nano_serial: &sercom5 {}; diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts index 0028128f8e2..e9f39b173ae 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts @@ -225,7 +225,7 @@ zephyr_udc0: &usbotg_hs { port { gc2145_ep_out: endpoint { - remote-endpoint = <&dcmi_ep_in>; + remote-endpoint-label = "dcmi_ep_in"; }; }; @@ -240,19 +240,13 @@ zephyr_udc0: &usbotg_hs { pinctrl-names = "default"; status = "okay"; - sensor = <&gc2145>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - capture-rate = <1>; - dmas = <&dma1 0 38 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | - STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | - STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; - port { dcmi_ep_in: endpoint { - remote-endpoint = <&gc2145_ep_out>; + remote-endpoint-label = "gc2145_ep_out"; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; }; }; }; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts index 9580656581f..c3e45f6184e 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts @@ -122,3 +122,34 @@ zephyr_udc0: &usbotg_fs { reg = <0x00>; }; }; + +&quadspi { + pinctrl-0 = < &quadspi_bk1_io0_pd11 + &quadspi_bk1_io1_pd12 + &quadspi_bk1_io2_pe2 + &quadspi_bk1_io3_pd13 + &quadspi_bk1_ncs_pg6 + &quadspi_clk_pb2 >; + pinctrl-names = "default"; + status = "okay"; + + at25sf128a: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = < 0x90000000 DT_SIZE_M(16) >; /* 128 MBits */ + qspi-max-frequency = ; + status = "okay"; + spi-bus-width = <2>; + st,read-id-dummy-cycles = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = < 1 >; + #size-cells = < 1 >; + + storage_partition: partition@0 { + label = "storage"; + reg=< 0x0 DT_SIZE_K(15872) >; + }; + }; + }; +}; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml index 6169f1b3364..d2d60fe33fc 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml @@ -10,6 +10,7 @@ flash: 768 supported: - gpio - netif:eth + - qspi testing: ignore_tags: - mpu diff --git a/boards/arm/mps3/mps3_corstone300_fvp.yaml b/boards/arm/mps3/mps3_corstone300_fvp.yaml index e6cb88bc5a7..520e69fc271 100644 --- a/boards/arm/mps3/mps3_corstone300_fvp.yaml +++ b/boards/arm/mps3/mps3_corstone300_fvp.yaml @@ -17,6 +17,7 @@ supported: - gpio testing: default: true + timeout_multiplier: 4 ignore_tags: - bluetooth - net diff --git a/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml b/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml index 52de52a2a1b..f0561b716c3 100644 --- a/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml +++ b/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml @@ -1,4 +1,4 @@ -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 identifier: mps3/corstone300/fvp/ns @@ -12,5 +12,6 @@ toolchain: - zephyr testing: default: true + timeout_multiplier: 4 only_tags: - trusted-firmware-m diff --git a/boards/arm/mps3/mps3_corstone310_fvp.yaml b/boards/arm/mps3/mps3_corstone310_fvp.yaml index 7259d65a238..3a9cc5e70a7 100644 --- a/boards/arm/mps3/mps3_corstone310_fvp.yaml +++ b/boards/arm/mps3/mps3_corstone310_fvp.yaml @@ -17,6 +17,7 @@ supported: - gpio testing: default: true + timeout_multiplier: 4 ignore_tags: - drivers - bluetooth diff --git a/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml b/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml index 307329bcf90..bfbc54dc16b 100644 --- a/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml +++ b/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml @@ -1,4 +1,4 @@ -# Copyright 2024 Arm Limited and/or its affiliates +# Copyright 2024-2025 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 identifier: mps3/corstone310/fvp/ns @@ -12,5 +12,6 @@ toolchain: - zephyr testing: default: true + timeout_multiplier: 4 only_tags: - trusted-firmware-m diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi index d6190e050f9..8875e53e511 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi @@ -17,6 +17,7 @@ led0 = &green_led; sw0 = &sw0_user_button; watchdog0 = &wdt; + sdhc0 = &hsmci; }; chosen { @@ -238,3 +239,17 @@ zephyr_udc0: &usbhs { pinctrl-names = "default"; }; }; + +&hsmci { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&hsmci_default>; + cd-gpios = <&pioc 16 GPIO_ACTIVE_LOW>; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi index 443bb39651f..bf09abaf1d0 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi @@ -182,4 +182,15 @@ ; }; }; + + hsmci_default: hsmci_default { + group1 { + pinmux = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml index 3cec4f75182..6f958557d7b 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml @@ -18,6 +18,7 @@ supported: - i2s - pwm - netif:eth + - sdhc - spi - usb_device - watchdog diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml index 7a70dbc5844..2007e30e92e 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml @@ -18,6 +18,7 @@ supported: - i2s - pwm - netif:eth + - sdhc - spi - usb_device - watchdog diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi index d5500da2bfc..b156ff7a91f 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi @@ -21,6 +21,7 @@ sw0 = &sw0_user_button; sw1 = &sw1_user_button; watchdog0 = &wdt; + sdhc0 = &hsmci; }; chosen { @@ -341,6 +342,20 @@ zephyr_udc0: &usbhs { status = "okay"; }; +&hsmci { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&hsmci_default>; + cd-gpios = <&piod 18 GPIO_ACTIVE_LOW>; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + ext1_spi: &spi0 { }; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi index fa7d4922743..fdd5ff1e8ad 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi @@ -153,4 +153,15 @@ ; }; }; + + hsmci_default: hsmci_default { + group1 { + pinmux = , + , + , + , + , + ; + }; + }; }; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml index c1873f6aaae..1e3a867ebba 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml @@ -22,6 +22,7 @@ supported: - pwm - netif:eth - rtc + - sdhc - spi - usb_device - watchdog diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml index b0a226550c9..68d06bd6699 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml @@ -22,6 +22,7 @@ supported: - pwm - netif:eth - rtc + - sdhc - spi - usb_device - watchdog diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml index 2ffa9435ca5..cdecfc36450 100644 --- a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml @@ -21,5 +21,6 @@ supported: - spi - uart - usb_device + - usbd - watchdog vendor: atmel diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml index bd46418551f..346c7fe0869 100644 --- a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml +++ b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml @@ -22,4 +22,5 @@ supported: - spi - uart - usb_device + - usbd vendor: atmel diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml index 77e032878b2..0513a8f6023 100644 --- a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml @@ -23,6 +23,7 @@ supported: - spi - uart - usb_device + - usbd - xpro_gpio - xpro_i2c - xpro_serial diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts index 804abfd9566..c8676ebce82 100644 --- a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts +++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts @@ -19,6 +19,9 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,ipc = &ipc0; + zephyr,ipc_shm = &ddr0; }; cpus { @@ -43,6 +46,12 @@ reg = <0xa2200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; + + ipc0: ipc { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox1 0>, <&mbox1 1>; + mbox-names = "tx", "rx"; + }; }; &i2c6 { diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts index 3191eccb625..ec24ee9f6bf 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts @@ -23,6 +23,7 @@ mcuboot-button0 = &button0; sensor0 = &light; sensor1 = &humidity; + watchdog0 = &wdt0; }; chosen { @@ -285,3 +286,7 @@ zephyr,resolution = <12>; }; }; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts index 43dd64f9c1c..b72290420e4 100644 --- a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts +++ b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts @@ -16,6 +16,7 @@ aliases { led0 = &led0; led1 = &led1; + watchdog0 = &wdt0; }; chosen { @@ -93,3 +94,7 @@ &ieee802154g { status = "okay"; }; + +&wdt0 { + status = "okay"; +}; diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts index 5bf213b6444..ac4d2b46e2e 100644 --- a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts +++ b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts @@ -18,6 +18,9 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,ipc = &ipc0; + zephyr,ipc_shm = &ddr0; }; cpus { @@ -42,6 +45,12 @@ reg = <0xa2200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; + + ipc0: ipc { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox3 0>, <&mbox3 1>; + mbox-names = "tx", "rx"; + }; }; &uart1 { diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts index e2957226a66..2c6f9f8c5f4 100644 --- a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts +++ b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts @@ -18,6 +18,9 @@ chosen { zephyr,sram = &atcm; zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,ipc = &ipc0; + zephyr,ipc_shm = &ddr0; }; cpus { @@ -42,6 +45,12 @@ reg = <0xa1200000 DT_SIZE_M(14)>; zephyr,memory-region = "DRAM"; }; + + ipc0: ipc { + compatible = "zephyr,mbox-ipm"; + mboxes = <&mbox1 0>, <&mbox1 1>; + mbox-names = "tx", "rx"; + }; }; &uart1 { diff --git a/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2 b/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2 index b154f4e2e4e..6a74baa3460 100644 --- a/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2 +++ b/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2 @@ -5,4 +5,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_POCKETBEAGLE_2 + select SOC_AM6232_A53 if BOARD_POCKETBEAGLE_2_AM6232_A53 select SOC_AM6232_M4 if BOARD_POCKETBEAGLE_2_AM6232_M4 diff --git a/boards/beagle/pocketbeagle_2/doc/index.rst b/boards/beagle/pocketbeagle_2/doc/index.rst index ecd9542919c..51852ffb8c4 100644 --- a/boards/beagle/pocketbeagle_2/doc/index.rst +++ b/boards/beagle/pocketbeagle_2/doc/index.rst @@ -17,9 +17,11 @@ cluster with an Arm Cortex-M4F microcontroller, Imagination Technologies AXE-1-1 graphics processor (from revision A1) and TI programmable real-time unit subsystem microcontroller cluster coprocessors. -Zephyr is ported to run on the M4F core and the following listed hardware -specifications are used: +Zephyr is ported to run on the both A53 cores and/or M4F core. +The following listed hardware specifications are used: + +- Dual ARM Cortex-A53 cores - Low-power ARM Cortex-M4F - Memory @@ -51,12 +53,31 @@ allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). Serial Port ----------- +A53 Cores +^^^^^^^^^ + +This board configuration uses single serial communication channel with the MAIN domain UART +(MAIN_UART6, i.e. debug port). + +M4F Core +^^^^^^^^ + This board configuration uses a single serial communication channel with the MCU domain UART (MCU_UART0, i.e. P2.05 as RX and P2.07 as TX). SD Card ******* +A53 Cores +========= + +Download BeagleBoard.org's official `BeagleBoard Imaging Utility`_ to create bootable +SD-card with the Zephyr image. Optionally, the Zephyr SD Card images can be downloaded from +`bb-zephyr-images`_. + +M4F Core +======== + Download BeagleBoard.org's official `BeagleBoard Imaging Utility`_ to create bootable SD-card with the Linux distro image. This will boot Linux on the A53 application cores. These cores will then load the Zephyr binary on the M4 core using remoteproc. @@ -64,6 +85,35 @@ cores. These cores will then load the Zephyr binary on the M4 core using remotep Flashing ******** +A53 Core +======== + +The testing requires the binary to be copied to the BOOT partition in SD card. + +To test the A53 core, we build the :zephyr:code-sample:`hello_world` sample with the following command. + +.. zephyr-app-commands:: + :board: pocketbeagle_2/am6232/a53 + :zephyr-app: samples/hello_world + :goals: build + +We now copy this binary onto the SD card in the :file:`/boot/` directory and name it as +:file:`zephyr.bin`. + +.. code-block:: console + + # Mount the SD card at sdcard for example + sudo mount /dev/sdX sdcard + # copy the bin to the /boot/ + sudo cp --remove-destination zephyr.bin sdcard/boot/zephyr.bin + +The SD card can now be used for booting. + +The binary will run and print Hello world to the debug port. + +M4F Core +======== + The board supports remoteproc using the OpenAMP resource table. The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. @@ -95,8 +145,11 @@ The binary will run and print Hello world to the MCU_UART0 port. Debugging ********* +M4F Core +======== + The board supports debugging M4 core from the A53 cores running Linux. Since the target needs -superuser privilege, openocd needs to be launched seperately for now: +superuser privilege, openocd needs to be launched separately for now: .. code-block:: console @@ -119,3 +172,6 @@ References .. _BeagleBoard Imaging Utility: https://github.com/beagleboard/bb-imager-rs/releases + +.. _bb-zephyr-images: + https://github.com/beagleboard/bb-zephyr-images/releases diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi new file mode 100644 index 00000000000..862a798952c --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + main_uart6_rx_default: main_uart6_rx_default { + pinmux = ; + }; + + main_uart6_tx_default: main_uart6_tx_default { + pinmux = ; + }; + + main_i2c2_sda_default: main_i2c2_sda_default { + /* (K24) GPMC0_CSn3.I2C2_SDA */ + pinmux = ; + }; + + main_i2c2_scl_default: main_i2c2_scl_default { + /* (K22) GPMC0_CSn2.I2C2_SCL */ + pinmux = ; + }; +}; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts new file mode 100644 index 00000000000..b035519f59e --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "pocketbeagle_2_am6232_a53-pinctrl.dtsi" + +/ { + model = "BeagleBoard.org PocketBeagle 2"; + compatible = "beagle,pocketbeagle_2_a53"; + + chosen { + zephyr,console = &uart6; + zephyr,shell-uart = &uart6; + zephyr,sram = &ddr0; + }; + + cpus { + cpu@0 { + status = "okay"; + }; + + cpu@1 { + status = "okay"; + }; + }; + + ddr0: memory@80000000 { + reg = <0x80000000 DT_SIZE_M(512)>; + }; +}; + +&uart6 { + pinctrl-0 = <&main_uart6_rx_default &main_uart6_tx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-0 = <&main_i2c2_sda_default &main_i2c2_scl_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml new file mode 100644 index 00000000000..30d04fc3551 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml @@ -0,0 +1,12 @@ +identifier: pocketbeagle_2/am6232/a53 +name: BeagleBoard.org PocketBeagle 2 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 524288 +vendor: beagle +supported: + - uart + - i2c diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig new file mode 100644 index 00000000000..d7ee894fcf4 --- /dev/null +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53_defconfig @@ -0,0 +1,32 @@ +# BeagleBoard.org PocketBeagle 2 +# +# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Platform Configuration + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Multicore Support +CONFIG_SMP=y diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk b/boards/bflb/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk similarity index 100% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk rename to boards/bflb/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi similarity index 100% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi rename to boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts similarity index 96% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts rename to boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts index e81d9cc6b37..87e986cbfe4 100644 --- a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts +++ b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "bl604e_iot_dvk-pinctrl.dtsi" / { diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml similarity index 100% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml rename to boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig similarity index 81% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig rename to boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig index 2b274c4a841..a512dfb34f7 100644 --- a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig +++ b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig @@ -6,4 +6,4 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_UART_BFLB=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake b/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake new file mode 100644 index 00000000000..29a318dbdb8 --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/board.cmake @@ -0,0 +1,26 @@ +# Copyright (c) 2022-2025 ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]") + +board_runner_args(openocd --use-elf --no-load --no-init) +board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") +board_runner_args(openocd --gdb-init "set architecture riscv:rv32") +board_runner_args(openocd --gdb-init "set remotetimeout 250") +board_runner_args(openocd --gdb-init "set print asm-demangle on") +board_runner_args(openocd --gdb-init "set backtrace limit 32") +board_runner_args(openocd --gdb-init "mem 0x22008000 0x22014000 rw") +board_runner_args(openocd --gdb-init "mem 0x42008000 0x42014000 rw") +board_runner_args(openocd --gdb-init "mem 0x22014000 0x22020000 rw") +board_runner_args(openocd --gdb-init "mem 0x42014000 0x42020000 rw") +board_runner_args(openocd --gdb-init "mem 0x22020000 0x2203C000 rw") +board_runner_args(openocd --gdb-init "mem 0x42020000 0x4203C000 rw") +board_runner_args(openocd --gdb-init "mem 0x23000000 0x23400000 ro") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(bflb_mcu_tool --chipname bl602) +board_runner_args(bflb_mcu_tool --dev-id /dev/ttyACM0) +include(${ZEPHYR_BASE}/boards/common/bflb_mcu_tool.board.cmake) + +board_set_flasher(bflb_mcu_tool) diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.yml b/boards/bflb/bl60x/bl604e_iot_dvk/board.yml similarity index 100% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/board.yml rename to boards/bflb/bl60x/bl604e_iot_dvk/board.yml diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp b/boards/bflb/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp similarity index 100% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp rename to boards/bflb/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/doc/index.rst b/boards/bflb/bl60x/bl604e_iot_dvk/doc/index.rst new file mode 100644 index 00000000000..0c440d59691 --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/doc/index.rst @@ -0,0 +1,103 @@ +.. zephyr:board:: bl604e_iot_dvk + +Overview +******** + +BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used +for low power consumption and high performance application development. The +wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0 +baseband/MAC design. The microcontroller subsystem includes a 32-bit RISC CPU +with low power consumption, cache and memory. The power management unit +controls the low power consumption mode. In addition, it also supports +various security features. The external interfaces include SDIO, SPI, UART, +I2C, IR remote, PWM, ADC, DAC, PIR and GPIO. + +The BL602 Development Board features a SiFive E24 32 bit RISC-V CPU with FPU, +it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM, +2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0 +with 2MB phy. It is a secure MCU which supports Secure boot, ECC-256 signed +image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key +Accelerator). + +Hardware +******** + +For more information about the Bouffalo Lab BL-60x MCU: + +- `Bouffalo Lab BL60x MCU Website`_ +- `Bouffalo Lab BL60x MCU Datasheet`_ +- `Bouffalo Lab Development Zone`_ +- `The RISC-V BL602 Book`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The BL604E Development Board is configured to run at max speed (192MHz). + +Serial Port +=========== + +The ``bl604e_iot_dvk`` board uses UART0 as default serial port. It is connected +to USB Serial converter and port is used for both program and console. + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Samples +======= + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample +application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bl604e_iot_dvk + :goals: build flash + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Then, press and release RST button + + .. code-block:: console + + *** Booting Zephyr OS build v4.1.0 *** + Hello World! bl604e_iot_dvk/bl604e20q2i + +Congratulations, you have ``bl604e_iot_dvk`` configured and running Zephyr. + + +.. _Bouffalo Lab BL60x MCU Website: + https://en.bouffalolab.com/product/?type=detail&id=6 + +.. _Bouffalo Lab BL60x MCU Datasheet: + https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en + +.. _Bouffalo Lab Development Zone: + https://dev.bouffalolab.com/home?id=guest + +.. _The RISC-V BL602 Book: + https://lupyuen.github.io/articles/book + +.. _Flashing Firmware to BL602: + https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/support/bl60x.cfg b/boards/bflb/bl60x/bl604e_iot_dvk/support/bl60x.cfg new file mode 100644 index 00000000000..fcabb2c4e7c --- /dev/null +++ b/boards/bflb/bl60x/bl604e_iot_dvk/support/bl60x.cfg @@ -0,0 +1,79 @@ +# Copyright (c) 2022-2025 ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME riscv +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +if { [info exists WORKAREAADDR] } { + set _WORKAREAADDR $WORKAREAADDR +} else { + set _WORKAREAADDR 0x22020000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x20000c05 +} + +transport select jtag +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME + +$_TARGETNAME.0 configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1 + +echo "Ready for Remote Connections" + +$_TARGETNAME.0 configure -event reset-assert-pre { + echo "reset-assert-pre" + adapter speed 100 +} + +$_TARGETNAME.0 configure -event reset-deassert-post { + echo "reset-deassert-post" + + adapter speed 100 + + reg mstatus 0x7800 + reg mie 0x0 +# reg pc 0x23000000 +} + +$_TARGETNAME.0 configure -event reset-init { + echo "reset-init" + + adapter speed 3000 +} + +$_TARGETNAME.0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME.0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +gdb_memory_map enable +gdb_flash_program enable + +# 'progbuf', 'sysbus' or 'abstract' +riscv set_mem_access sysbus +riscv set_command_timeout_sec 1 + +init +reset init diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/support/openocd.cfg b/boards/bflb/bl60x/bl604e_iot_dvk/support/openocd.cfg similarity index 100% rename from boards/bouffalolab/bl60x/bl604e_iot_dvk/support/openocd.cfg rename to boards/bflb/bl60x/bl604e_iot_dvk/support/openocd.cfg diff --git a/boards/bouffalolab/index.rst b/boards/bflb/index.rst similarity index 100% rename from boards/bouffalolab/index.rst rename to boards/bflb/index.rst diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.cmake b/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.cmake deleted file mode 100644 index a8e089640bd..00000000000 --- a/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2022-2025 ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]") - -board_runner_args(openocd --use-elf --no-load --no-init) -board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off") -board_runner_args(openocd --gdb-init "set architecture riscv:rv32") -board_runner_args(openocd --gdb-init "set remotetimeout 250") -board_runner_args(openocd --gdb-init "set print asm-demangle on") -board_runner_args(openocd --gdb-init "set backtrace limit 32") -board_runner_args(openocd --gdb-init "mem 0x22008000 0x22014000 rw") -board_runner_args(openocd --gdb-init "mem 0x42008000 0x42014000 rw") -board_runner_args(openocd --gdb-init "mem 0x22014000 0x22020000 rw") -board_runner_args(openocd --gdb-init "mem 0x42014000 0x42020000 rw") -board_runner_args(openocd --gdb-init "mem 0x22020000 0x2203C000 rw") -board_runner_args(openocd --gdb-init "mem 0x42020000 0x4203C000 rw") -board_runner_args(openocd --gdb-init "mem 0x23000000 0x23400000 ro") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/index.rst b/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/index.rst deleted file mode 100644 index 76522129e41..00000000000 --- a/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/index.rst +++ /dev/null @@ -1,104 +0,0 @@ -.. zephyr:board:: bl604e_iot_dvk - -Overview -******** - -BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used -for low power consumption and high performance application development. The -wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0 -baseband/MAC design. The microcontroller subsystem includes a 32-bit RISC CPU -with low power consumption, cache and memory. The power management unit -controls the low power consumption mode. In addition, it also supports -various security features. The external interfaces include SDIO, SPI, UART, -I2C, IR remote, PWM, ADC, DAC, PIR and GPIO. - -The BL602 Development Board features a SiFive E24 32 bit RISC-V CPU with FPU, -it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM, -2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0 -with 2MB phy. It is a secure MCU which supports Secure boot, ECC-256 signed -image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key -Accelerator). - -Hardware -******** - -For more information about the Bouffalo Lab BL-60x MCU: - -- `Bouffalo Lab BL60x MCU Website`_ -- `Bouffalo Lab BL60x MCU Datasheet`_ -- `Bouffalo Lab Development Zone`_ -- `The RISC-V BL602 Book`_ - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig`. - -System Clock -============ - -The BL604E Development Board is configured to run at max speed (192MHz). - -Serial Port -=========== - -The ``bl604e_iot_dvk`` board uses UART0 as default serial port. It is connected -to USB Serial converter and port is used for both program and console. - - -Programming and Debugging -************************* - -Samples -======= - -#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample -application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: bl604e_iot_dvk - :goals: build flash - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - - Then, press and release RST button - - .. code-block:: console - - *** Booting Zephyr OS build v4.1.0 *** - Hello World! bl604e_iot_dvk/bl604e20q2i - -Congratulations, you have ``bl604e_iot_dvk`` configured and running Zephyr. - - -.. _Bouffalo Lab BL60x MCU Website: - https://en.bouffalolab.com/product/?type=detail&id=6 - -.. _Bouffalo Lab BL60x MCU Datasheet: - https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en - -.. _Bouffalo Lab Development Zone: - https://dev.bouffalolab.com/home?id=guest - -.. _The RISC-V BL602 Book: - https://lupyuen.github.io/articles/book - -.. _Flashing Firmware to BL602: - https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi index 186f6ef4662..d99760f762c 100644 --- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi +++ b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi @@ -183,4 +183,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/common/bflb_mcu_tool.board.cmake b/boards/common/bflb_mcu_tool.board.cmake new file mode 100644 index 00000000000..73862b0f5e1 --- /dev/null +++ b/boards/common/bflb_mcu_tool.board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(bflb_mcu_tool) +board_finalize_runner_args(bflb_mcu_tool) diff --git a/boards/common/nios2.board.cmake b/boards/common/nios2.board.cmake deleted file mode 100644 index 4a59927171b..00000000000 --- a/boards/common/nios2.board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(nios2) -board_set_debugger_ifnset(nios2) - -board_finalize_runner_args(nios2 - # TODO: merge this script into nios2.py - "--quartus-flash=${ZEPHYR_BASE}/scripts/support/quartus-flash.py" - ) diff --git a/boards/common/openocd-adi-max32.boards.cmake b/boards/common/openocd-adi-max32.boards.cmake index c231f5ad1cf..c815a0db64f 100644 --- a/boards/common/openocd-adi-max32.boards.cmake +++ b/boards/common/openocd-adi-max32.boards.cmake @@ -14,13 +14,15 @@ endif() # MAX32666 share the same target configuration file with MAX32665 if(CONFIG_SOC_MAX32666) set(MAX32_TARGET_CFG "max32665.cfg") +elseif(CONFIG_SOC_MAX32657) + set(MAX32_INTERFACE_CFG "jlink.cfg") endif() board_runner_args(openocd --cmd-pre-init "source [find interface/${MAX32_INTERFACE_CFG}]") board_runner_args(openocd --cmd-pre-init "source [find target/${MAX32_TARGET_CFG}]") board_runner_args(openocd "--target-handle=_CHIPNAME.cpu") -if(CONFIG_SOC_FAMILY_MAX32_M4) +if(CONFIG_SOC_FAMILY_MAX32_M4 OR CONFIG_SOC_FAMILY_MAX32_M33) board_runner_args(openocd --cmd-pre-init "allow_low_pwr_dbg") board_runner_args(openocd "--cmd-erase=max32xxx mass_erase 0") endif() diff --git a/boards/common/openocd-stm32.board.cmake b/boards/common/openocd-stm32.board.cmake index 855411fa34b..cecaba23529 100644 --- a/boards/common/openocd-stm32.board.cmake +++ b/boards/common/openocd-stm32.board.cmake @@ -18,3 +18,5 @@ elseif(CONFIG_SOC_SERIES_STM32F2X OR CONFIG_SOC_SERIES_STM32F7X) board_runner_args(openocd "--cmd-erase=stm32f2x mass_erase 0") endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/common/openocd.board.cmake b/boards/common/openocd.board.cmake index b1d09fe0a2d..14d32d4be25 100644 --- a/boards/common/openocd.board.cmake +++ b/boards/common/openocd.board.cmake @@ -20,6 +20,3 @@ board_finalize_runner_args(openocd --cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}" --cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}" ) - -# Manufacturer common options -include(${CMAKE_CURRENT_LIST_DIR}/openocd-stm32.board.cmake) diff --git a/boards/ct/ctcc/board.yml b/boards/ct/ctcc/board.yml index 826b1846af5..e36afe64d4c 100644 --- a/boards/ct/ctcc/board.yml +++ b/boards/ct/ctcc/board.yml @@ -1,6 +1,7 @@ board: name: ctcc full_name: CTHINGS.CO Connectivity Card + vendor: ct socs: - name: nrf52840 - name: nrf9161 diff --git a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi index 00e53a5262c..38b48f9f5ee 100644 --- a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi +++ b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi @@ -76,4 +76,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 1dd7b14a629..29959964a85 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -52,3 +52,15 @@ set(neorv32_DEPRECATED set(xiao_esp32c6_DEPRECATED xiao_esp32c6/esp32c6/hpcore ) +set(esp32_devkitc_wroom/esp32/procpu_DEPRECATED + esp32_devkitc/esp32/procpu +) +set(esp32_devkitc_wrover/esp32/procpu_DEPRECATED + esp32_devkitc/esp32/procpu +) +set(esp32_devkitc_wroom/esp32/appcpu_DEPRECATED + esp32_devkitc/esp32/appcpu +) +set(esp32_devkitc_wrover/esp32/appcpu_DEPRECATED + esp32_devkitc/esp32/appcpu +) diff --git a/boards/doiting/dt_bl10_devkit/Kconfig.dt_bl10_devkit b/boards/doiting/dt_bl10_devkit/Kconfig.dt_bl10_devkit new file mode 100644 index 00000000000..634561d9d12 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/Kconfig.dt_bl10_devkit @@ -0,0 +1,5 @@ +# Copyright (c) 2021-2025 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DT_BL10_DEVKIT + select SOC_BL602C20Q2I diff --git a/boards/doiting/dt_bl10_devkit/board.cmake b/boards/doiting/dt_bl10_devkit/board.cmake new file mode 100644 index 00000000000..d8e6ac40147 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2021-2025 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(bflb_mcu_tool --chipname bl602) +include(${ZEPHYR_BASE}/boards/common/bflb_mcu_tool.board.cmake) + +board_set_flasher(bflb_mcu_tool) diff --git a/boards/doiting/dt_bl10_devkit/board.yml b/boards/doiting/dt_bl10_devkit/board.yml new file mode 100644 index 00000000000..9c080ef4bce --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/board.yml @@ -0,0 +1,6 @@ +board: + name: dt_bl10_devkit + full_name: DT-BL10 coexistence Module Development Kit + vendor: doiting + socs: + - name: bl602c20q2i diff --git a/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_devkit.webp b/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_devkit.webp new file mode 100644 index 00000000000..e65768b9fab Binary files /dev/null and b/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_devkit.webp differ diff --git a/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_pinout.webp b/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_pinout.webp new file mode 100644 index 00000000000..2efa8764c61 Binary files /dev/null and b/boards/doiting/dt_bl10_devkit/doc/img/dt_bl10_pinout.webp differ diff --git a/boards/doiting/dt_bl10_devkit/doc/index.rst b/boards/doiting/dt_bl10_devkit/doc/index.rst new file mode 100644 index 00000000000..2f351a77f25 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/doc/index.rst @@ -0,0 +1,124 @@ +.. zephyr:board:: dt_bl10_devkit + +DT-BL10 Development Kit +####################### + +Overview +******** + +DT-BL10 Wi-Fi and BLE coexistence Module is a highly integrated single-chip +low power 802.11n Wireless LAN (WLAN) network controller. It combines an RISC +CPU, WLAN MAC, a lT1R capable WLAN baseband, RF, and Bluetooth in a single chip. +It also provides a bunch of configurable GPIO, which are configured as digital +peripherals for different applications and control usage. + +DT-BL10 WiFi Module use BL602 as Wi-Fi and BLE coexistence soc chip. DT-BL10 +WiFi Module integrates internal memories for complete WIFI protocol functions. +The embedded memory configuration also provides simple application developments. + +DT-BL10 WiFi module supports the standard IEEE 802.11 b/g/n/e/i protocol and the +complete TCP/IP protocol stack. User can use it to add the WiFi function for the +installed devices, and also can be viewed as a independent network controller. + +Hardware +******** + +For more information about the Bouffalo Lab BL-602 MCU: + +- `Bouffalo Lab BL602 MCU Website`_ +- `Bouffalo Lab BL602 MCU Datasheet`_ +- `Bouffalo Lab Development Zone`_ +- `dt_bl10_devkit Schematic`_ +- `Doctors of Intelligence & Technology (www.doiting.com)`_ +- `The RISC-V BL602 Book`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The DT-BL10 board is configured to run at max speed (192MHz). + +Serial Port +=========== + +The ``dt_bl10_devkit`` board uses UART0 as default serial port. It is connected +to USB Serial converter and port is used for both program and console. + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Samples +======= + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample +application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dt_bl10_devkit + :goals: build + +#. To flash an image using blflash runner: + + #. Press D8 button + + #. Press and release EN button + + #. Release D8 button + + .. code-block:: console + + west flash + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Then, press and release EN button + + .. code-block:: console + + *** Booting Zephyr OS build v4.1.0-4682-g21b20de1eb34 *** + Hello World! dt_bl10_devkit/bl602c20q2i + +Congratulations, you have ``dt_bl10_devkit`` configured and running Zephyr. + + +.. _Bouffalo Lab BL602 MCU Website: + https://www.bouffalolab.com/bl602 + +.. _Bouffalo Lab BL602 MCU Datasheet: + https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en + +.. _Bouffalo Lab Development Zone: + https://dev.bouffalolab.com/home?id=guest + +.. _dt_bl10_devkit Schematic: + https://github.com/SmartArduino/Doiting_BL/blob/master/board/DT-BL10%20User%20Mannual.pdf + +.. _Doctors of Intelligence & Technology (www.doiting.com): + https://www.doiting.com + +.. _The RISC-V BL602 Book: + https://lupyuen.github.io/articles/book + +.. _Flashing Firmware to BL602: + https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi new file mode 100644 index 00000000000..6909cc44715 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021-2025 ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = , + ; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + pinmux = , + ; + bias-high-impedance; + }; + }; +}; diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts new file mode 100644 index 00000000000..34ce0613736 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021-2025 ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "dt_bl10_devkit-pinctrl.dtsi" + +/ { + model = "2.4GHz Wi-Fi and BLE coexistence Module Development Kit"; + compatible = "bflb,bl602"; + + chosen { + zephyr,flash = &flash0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000b000 0x1000 0x23000000 0xc00000>; + + flash0: flash@0 { + compatible = "issi,is25lp128", "jedec,spi-nor"; + status = "disabled"; + size = ; + jedec-id = [96 60 18]; + reg = <0>; + spi-max-frequency = ; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.yaml b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.yaml new file mode 100644 index 00000000000..8a0921fd9d8 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2021-2025 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +identifier: dt_bl10_devkit +name: DT-BL10 coexistence Module Development Kit +type: mcu +arch: riscv +ram: 64 +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth +supported: + - pinctrl + - uart +vendor: doiting diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit_defconfig b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit_defconfig new file mode 100644 index 00000000000..b4c911b77c4 --- /dev/null +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2025 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/doiting/index.rst b/boards/doiting/index.rst new file mode 100644 index 00000000000..8be7f522dbd --- /dev/null +++ b/boards/doiting/index.rst @@ -0,0 +1,10 @@ +.. _boards-doiting: + +Doctors of Intelligence & Technology +#################################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.yaml b/boards/element14/warp7/warp7_mcimx7d_m4.yaml index 24bcdb296fb..db5295b3b69 100644 --- a/boards/element14/warp7/warp7_mcimx7d_m4.yaml +++ b/boards/element14/warp7/warp7_mcimx7d_m4.yaml @@ -20,4 +20,3 @@ testing: supported: - gpio - i2c -vendor: nxp diff --git a/boards/enjoydigital/litex_vexriscv/board.yml b/boards/enjoydigital/litex_vexriscv/board.yml index c5cd6829183..c74d1ff2321 100644 --- a/boards/enjoydigital/litex_vexriscv/board.yml +++ b/boards/enjoydigital/litex_vexriscv/board.yml @@ -1,6 +1,6 @@ board: name: litex_vexriscv full_name: LiteX VexRiscv - vendor: litex + vendor: enjoydigital socs: - name: litex_vexriscv diff --git a/boards/espressif/esp32_devkitc/Kconfig b/boards/espressif/esp32_devkitc/Kconfig new file mode 100644 index 00000000000..3187645aa97 --- /dev/null +++ b/boards/espressif/esp32_devkitc/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32_DEVKITC_ESP32_PROCPU + default 256 if BOARD_ESP32_DEVKITC_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc/Kconfig.esp32_devkitc b/boards/espressif/esp32_devkitc/Kconfig.esp32_devkitc new file mode 100644 index 00000000000..b843530ace2 --- /dev/null +++ b/boards/espressif/esp32_devkitc/Kconfig.esp32_devkitc @@ -0,0 +1,7 @@ +# Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC + select SOC_ESP32_WROVER_E_N4R8 + select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.sysbuild b/boards/espressif/esp32_devkitc/Kconfig.sysbuild similarity index 100% rename from boards/espressif/esp32_devkitc_wroom/Kconfig.sysbuild rename to boards/espressif/esp32_devkitc/Kconfig.sysbuild diff --git a/boards/espressif/esp32_devkitc_wroom/board.cmake b/boards/espressif/esp32_devkitc/board.cmake similarity index 100% rename from boards/espressif/esp32_devkitc_wroom/board.cmake rename to boards/espressif/esp32_devkitc/board.cmake diff --git a/boards/espressif/esp32_devkitc/board.yml b/boards/espressif/esp32_devkitc/board.yml new file mode 100644 index 00000000000..fbd9c38a48a --- /dev/null +++ b/boards/espressif/esp32_devkitc/board.yml @@ -0,0 +1,6 @@ +board: + name: esp32_devkitc + full_name: ESP32-DevKitC + vendor: espressif + socs: + - name: esp32 diff --git a/boards/espressif/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg b/boards/espressif/esp32_devkitc/doc/img/esp32_devkitc_wrover.jpg similarity index 100% rename from boards/espressif/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg rename to boards/espressif/esp32_devkitc/doc/img/esp32_devkitc_wrover.jpg diff --git a/boards/espressif/esp32_devkitc/doc/index.rst b/boards/espressif/esp32_devkitc/doc/index.rst new file mode 100644 index 00000000000..b7bf86406b0 --- /dev/null +++ b/boards/espressif/esp32_devkitc/doc/index.rst @@ -0,0 +1,256 @@ +.. zephyr:board:: esp32_devkitc + +Overview +******** + +ESP32 is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +Tensilica Xtensa LX6 microprocessor in both dual-core and single-core +variations. ESP32 is created and developed by Espressif Systems, a +Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm +process. For more information, check `ESP32-DevKitC`_. + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz +- 520KB of SRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- Various peripherals: + + - 12-bit ADC with up to 18 channels + - 2x 8-bit DACs + - 10x touch sensors + - Temperature sensor + - 4x SPI + - 2x I2S + - 2x I2C + - 3x UART + - SD/SDIO/MMC host + - Slave (SDIO/SPI) + - Ethernet MAC + - CAN bus 2.0 + - IR (RX/TX) + - Motor PWM + - LED PWM with up to 16 channels + - Hall effect sensor + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +- 5uA deep sleep current + +For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference +manual at `ESP32 Technical Reference Manual`_. + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32-DevKitC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as code reference. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +.. zephyr:board-supported-runners:: + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32_devkitc + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32_devkitc`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32_devkitc + +Debugging +********* + +ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. + +On the ESP32-DevKitC board, the JTAG pins are not run to a +standard connector (e.g. ARM 20-pin) and need to be manually connected +to the external programmer (e.g. a Flyswatter2): + ++------------+-----------+ +| ESP32 pin | JTAG pin | ++============+===========+ +| 3V3 | VTRef | ++------------+-----------+ +| EN | nTRST | ++------------+-----------+ +| IO14 | TMS | ++------------+-----------+ +| IO12 | TDI | ++------------+-----------+ +| GND | GND | ++------------+-----------+ +| IO13 | TCK | ++------------+-----------+ +| IO15 | TDO | ++------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc/esp32/procpu + :goals: debug + +Note on Debugging with GDB Stub +=============================== + +GDB stub is enabled on ESP32. + +* When adding breakpoints, please use hardware breakpoints with command + ``hbreak``. Command ``break`` uses software breakpoints which requires + modifying memory content to insert break/trap instructions. + This does not work as the code is on flash which cannot be randomly + accessed for modification. + +References +********** + +.. target-notes:: + +.. _`ESP32-DevKitC`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-devkitc/index.html +.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf +.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi b/boards/espressif/esp32_devkitc/esp32_devkitc-pinctrl.dtsi similarity index 100% rename from boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi rename to boards/espressif/esp32_devkitc/esp32_devkitc-pinctrl.dtsi diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.dts b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.dts new file mode 100644 index 00000000000..62427d3d2de --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "Espressif ESP32-DevkitC APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.yaml b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.yaml new file mode 100644 index 00000000000..8f2cf6b9cb8 --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32_devkitc/esp32/appcpu +name: ESP32-DevkitC APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig b/boards/espressif/esp32_devkitc/esp32_devkitc_appcpu_defconfig similarity index 100% rename from boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig rename to boards/espressif/esp32_devkitc/esp32_devkitc_appcpu_defconfig diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.dts b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.dts new file mode 100644 index 00000000000..b92d20ec136 --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.dts @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32_devkitc-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Espressif ESP32-DevkitC PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + sw0 = &button0; + watchdog0 = &wdt0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml new file mode 100644 index 00000000000..7a1a124e7d7 --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu.yaml @@ -0,0 +1,22 @@ +identifier: esp32_devkitc/esp32/procpu +name: ESP32-DevkitC PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - i2s + - watchdog + - uart + - nvs + - pwm + - dac + - spi + - counter + - entropy + - input +vendor: espressif diff --git a/boards/espressif/esp32_devkitc/esp32_devkitc_procpu_defconfig b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu_defconfig new file mode 100644 index 00000000000..ea5684dc83e --- /dev/null +++ b/boards/espressif/esp32_devkitc/esp32_devkitc_procpu_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/espressif/esp32_devkitc_wroom/support/openocd.cfg b/boards/espressif/esp32_devkitc/support/openocd.cfg similarity index 100% rename from boards/espressif/esp32_devkitc_wroom/support/openocd.cfg rename to boards/espressif/esp32_devkitc/support/openocd.cfg diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig deleted file mode 100644 index 39114996412..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU - default 256 if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom b/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom deleted file mode 100644 index 148838c4318..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_DEVKITC_WROOM - select SOC_ESP32_WROOM_32UE_N4 - select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU - select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/board.yml b/boards/espressif/esp32_devkitc_wroom/board.yml deleted file mode 100644 index e0d766da0d1..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: esp32_devkitc_wroom - full_name: ESP32-DevKitC-WROOM - vendor: espressif - socs: - - name: esp32 diff --git a/boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg b/boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg deleted file mode 100644 index 2b8317e29eb..00000000000 Binary files a/boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg and /dev/null differ diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst deleted file mode 100644 index 9b5bc1c6baf..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/doc/index.rst +++ /dev/null @@ -1,256 +0,0 @@ -.. zephyr:board:: esp32_devkitc_wroom - -Overview -******** - -ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. For more information, check `ESP32-DevKitC-WROOM`_. - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference -manual at `ESP32 Technical Reference Manual`_. - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-DevKitC-WROOM allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as code reference. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -.. zephyr:board-supported-runners:: - -Simple boot -=========== - -The board could be loaded using the single binary image, without 2nd stage bootloader. -It is the default option when building the application without additional configuration. - -.. note:: - - Simple boot does not provide any security features nor OTA updates. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be built (and flashed) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - - .. code:: cfg - - CONFIG_BOOTLOADER_MCUBOOT=y - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be built one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom/esp32/procpu - :goals: build - -The usual ``flash`` target will work with the ``esp32_devkitc_wroom`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom/esp32/procpu - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_devkitc_wroom - -Debugging -********* - -ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. - -On the ESP32-DevKitC-WROOM board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. - -Here is an example for building the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom/esp32/procpu - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom/esp32/procpu - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -References -********** - -.. target-notes:: - -.. _`ESP32-DevKitC-WROOM`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# -.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf -.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi deleted file mode 100644 index 1089af3047e..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -&pinctrl { - - uart0_default: uart0_default { - group1 { - pinmux = ; - output-high; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - uart1_default: uart1_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - uart2_default: uart2_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - bias-pull-up; - }; - }; - - spim2_default: spim2_default { - group1 { - pinmux = , - , - ; - }; - group2 { - pinmux = ; - output-low; - }; - }; - - spim3_default: spim3_default { - group1 { - pinmux = , - , - ; - }; - group2 { - pinmux = ; - output-low; - }; - }; - - i2c0_default: i2c0_default { - group1 { - pinmux = , - ; - bias-pull-up; - drive-open-drain; - output-high; - }; - }; - - i2s0_default: i2s0_default { - group1 { - pinmux = , - , - , - , - ; - output-enable; - }; - group2 { - pinmux = ; - input-enable; - }; - }; - - i2s1_default: i2s1_default { - group1 { - pinmux = , - , - , - , - ; - output-enable; - }; - group2 { - pinmux = ; - input-enable; - }; - }; -}; - diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts deleted file mode 100644 index c88ae757867..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include - -/ { - model = "Espressif ESP32-DevkitC APPCPU"; - compatible = "espressif,esp32"; - - chosen { - zephyr,sram = &sram1; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_appcpu_partition; - }; -}; - -&ipm0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml deleted file mode 100644 index 26d4e67df3f..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32_devkitc_wroom/esp32/appcpu -name: ESP32 DEVKITC WROOM APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig deleted file mode 100644 index cc70c277960..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CLOCK_CONTROL=y -CONFIG_CONSOLE=n -CONFIG_SERIAL=n -CONFIG_UART_CONSOLE=n -CONFIG_GPIO=n diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts deleted file mode 100644 index e9d5e2855ab..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_devkitc_wroom-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "Espressif ESP32-DevkitC PROCPU"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci = &esp32_bt_hci; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_default>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&i2s1 { - pinctrl-0 = <&i2s1_default>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&psram0 { - status = "disabled"; -}; - -&esp32_bt_hci { - status = "okay"; -}; - -&wifi { - status = "okay"; -}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml deleted file mode 100644 index c3e9af32006..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: esp32_devkitc_wroom/esp32/procpu -name: ESP32-DevkitC-WROOM-32D -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - i2s - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy - - input -vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig deleted file mode 100644 index 172a46d1005..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig deleted file mode 100644 index 6442ca47279..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU - default 256 if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover b/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover deleted file mode 100644 index 1e107bf8b4a..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_DEVKITC_WROVER - select SOC_ESP32_WROVER_E_N4R8 - select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU - select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild b/boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild deleted file mode 100644 index 3a2d17ac5cf..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice BOOTLOADER - default BOOTLOADER_MCUBOOT -endchoice - -choice BOOT_SIGNATURE_TYPE - default BOOT_SIGNATURE_TYPE_NONE -endchoice diff --git a/boards/espressif/esp32_devkitc_wrover/board.cmake b/boards/espressif/esp32_devkitc_wrover/board.cmake deleted file mode 100644 index ad53de11770..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") - set(OPENOCD OPENOCD-NOTFOUND) -endif() - -find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) - -include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32_devkitc_wrover/board.yml b/boards/espressif/esp32_devkitc_wrover/board.yml deleted file mode 100644 index 2a8e2a226fd..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: esp32_devkitc_wrover - full_name: ESP32-DevKitC-WROVER - vendor: espressif - socs: - - name: esp32 diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst deleted file mode 100644 index 5bab845c938..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/doc/index.rst +++ /dev/null @@ -1,256 +0,0 @@ -.. zephyr:board:: esp32_devkitc_wrover - -Overview -******** - -ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. For more information, check `ESP32-DevKitC-WROVER`_. - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference -manual at `ESP32 Technical Reference Manual`_. - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-DevKitC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as code reference. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -.. zephyr:board-supported-runners:: - -Simple boot -=========== - -The board could be loaded using the single binary image, without 2nd stage bootloader. -It is the default option when building the application without additional configuration. - -.. note:: - - Simple boot does not provide any security features nor OTA updates. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be built (and flashed) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - - .. code:: cfg - - CONFIG_BOOTLOADER_MCUBOOT=y - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be built one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover/esp32/procpu - :goals: build - -The usual ``flash`` target will work with the ``esp32_devkitc_wrover`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover/esp32/procpu - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_devkitc_wrover - -Debugging -********* - -ESP32 support on OpenOCD is available at `OpenOCD ESP32`_. - -On the ESP32-DevKitC-WROVER board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. - -Here is an example for building the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover/esp32/procpu - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover/esp32/procpu - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -References -********** - -.. target-notes:: - -.. _`ESP32-DevKitC-WROVER`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# -.. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf -.. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts deleted file mode 100644 index f6fb39576f2..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include - -/ { - model = "Espressif ESP32-DevkitC WROVER-E APPCPU"; - compatible = "espressif,esp32"; - - chosen { - zephyr,sram = &sram1; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_appcpu_partition; - }; -}; - -&ipm0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml deleted file mode 100644 index 04082823801..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32_devkitc_wrover/esp32/appcpu -name: ESP32-DevkitC-WROVER-E APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts deleted file mode 100644 index c91a7178113..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_devkitc_wrover-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "Espressif ESP32-DevkitC WROVER-E PROCPU"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci = &esp32_bt_hci; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_default>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&i2s1 { - pinctrl-0 = <&i2s1_default>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&esp32_bt_hci { - status = "okay"; -}; - -&wifi { - status = "okay"; -}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml deleted file mode 100644 index 32de7a52bd3..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: esp32_devkitc_wrover/esp32/procpu -name: ESP32-DevkitC-WROVER-E PROCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - i2s - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy - - input -vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig deleted file mode 100644 index 172a46d1005..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/espressif/esp32_devkitc_wrover/support/openocd.cfg b/boards/espressif/esp32_devkitc_wrover/support/openocd.cfg deleted file mode 100644 index 338e6e4e6ea..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/support/openocd.cfg +++ /dev/null @@ -1,5 +0,0 @@ -set ESP_RTOS none -set ESP32_ONLYCPU 1 - -source [find interface/ftdi/esp32_devkitj_v1.cfg] -source [find target/esp32.cfg] diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml index 6eed11176b0..4bc3c0cde26 100644 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml @@ -16,6 +16,7 @@ supported: - counter - entropy - i2c + - i2s testing: ignore_tags: - bluetooth diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig index 42ee26028f9..04974098f6c 100644 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig @@ -17,3 +17,4 @@ CONFIG_CBPRINTF_NANO=y # Build CONFIG_SIZE_OPTIMIZATIONS=y +CONFIG_BUSYWAIT_CPU_LOOPS_PER_USEC=4 diff --git a/boards/espressif/esp32s3_eye/doc/index.rst b/boards/espressif/esp32s3_eye/doc/index.rst index e7b7643cbba..0657fa20180 100644 --- a/boards/espressif/esp32s3_eye/doc/index.rst +++ b/boards/espressif/esp32s3_eye/doc/index.rst @@ -3,8 +3,8 @@ Overview ******** -The ESP32-S3-EYE is a small-sized AI development board produced by [Espressif](https://espressif.com). -It is based on the [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) SoC. +The ESP32-S3-EYE is a small-sized AI development board produced by `Espressif`_. +It is based on the `ESP32-S3`_ SoC. It features a 2-Megapixel camera, an LCD display, and a microphone, which are used for image recognition and audio processing. ESP32-S3-EYE offers plenty of storage, with an 8 MB Octal PSRAM and a 8 MB flash. @@ -258,7 +258,7 @@ Debugging ESP32-S3 modules require patches to OpenOCD that are not upstreamed yet. Espressif maintains their own fork of the project. The custom OpenOCD can be obtained at -`OpenOCD ESP32`_ +`OpenOCD ESP32`_. The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the @@ -282,3 +282,7 @@ application. :goals: debug .. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases + +.. _`Espressif`: https://espressif.com + +.. _`ESP32-S3`: https://www.espressif.com/en/products/socs/esp32-s3 diff --git a/boards/ezurio/bl5340_dvk/Kconfig b/boards/ezurio/bl5340_dvk/Kconfig deleted file mode 100644 index e84a37972a0..00000000000 --- a/boards/ezurio/bl5340_dvk/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2019-2021 Nordic Semiconductor ASA -# Copyright (c) 2021-2023 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUNET_BOARD - string - default "bl5340_dvk/nrf5340/cpunet" - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the bl5340_dvk_cpunet for - Bluetooth applications. - -endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS - -if BOARD_BL5340_DVK_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "bl5340_dvk/nrf5340/cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/franzininho/esp32s2_franzininho/board.yml b/boards/franzininho/esp32s2_franzininho/board.yml index 530d5dcec4e..25b481d709d 100644 --- a/boards/franzininho/esp32s2_franzininho/board.yml +++ b/boards/franzininho/esp32s2_franzininho/board.yml @@ -1,6 +1,6 @@ board: name: esp32s2_franzininho full_name: ESP32-S2 Franzininho - vendor: espressif + vendor: franzininho socs: - name: esp32s2 diff --git a/boards/gardena/sgrm/sgrm.dts b/boards/gardena/sgrm/sgrm.dts index 58a9e90e97e..c261592c6b9 100644 --- a/boards/gardena/sgrm/sgrm.dts +++ b/boards/gardena/sgrm/sgrm.dts @@ -15,9 +15,9 @@ chosen { zephyr,console = &usart1; zephyr,flash = &flash0; + zephyr,ppp-uart = &usart0; zephyr,shell-uart = &usart1; zephyr,sram = &sram0; - zephyr,ppp-uart = &usart0; }; }; @@ -41,9 +41,9 @@ &usart0 { current-speed = <500000>; + hw-flow-control; pinctrl-0 = <&usart0_default>; pinctrl-names = "default"; - hw-flow-control; status = "okay"; }; @@ -80,13 +80,13 @@ #size-cells = <1>; slot0_partition: partition@0 { - label = "image-0"; reg = <0x00000000 DT_SIZE_K(192)>; + label = "image-0"; }; storage_partition: partition@30000 { - label = "storage"; reg = <0x00030000 DT_SIZE_K(64)>; + label = "storage"; }; }; }; diff --git a/boards/index.rst b/boards/index.rst index 9b83276abbf..3cc92770cfe 100644 --- a/boards/index.rst +++ b/boards/index.rst @@ -3,26 +3,28 @@ Supported Boards and Shields ############################ -If you are looking to add Zephyr support for a new board, please start with the -:ref:`board_porting_guide`. +This page lists all the boards and shields that are currently supported in Zephyr. -When adding support documentation for a board, remember to use the template -available under :zephyr_file:`doc/templates/board.tmpl`. +If you are looking to add Zephyr support for a new board, please start with the +:ref:`board_porting_guide`. When adding support documentation for a board, remember to use the +template available under :zephyr_file:`doc/templates/board.tmpl`. -Shields are hardware add-ons that can be stacked on top of a board to add extra -functionality. They are listed separately from boards, towards :ref:`the end of -this page `. +Shields are hardware add-ons that can be stacked on top of a board to add extra functionality. +Refer to the :ref:`shield_porting_guide` for more information on how to port a shield. .. admonition:: Search Tips :class: dropdown - * Use the form below to filter the list of supported boards. If a field is left empty, it will - not be used in the filtering process. + * Use the form below to filter the list of supported boards and shields. If a field is left + empty, it will not be used in the filtering process. + + * Filtering by name and vendor is available for both boards and shields. The rest of the fields + apply only to boards. - * A board must meet **all** criteria selected across different fields. For example, if you select - both a vendor and an architecture, only boards that match both will be displayed. Within a - single field, selecting multiple options (such as two architectures) will show boards matching - **either** option. + * A board/shield must meet **all** criteria selected across different fields. For example, if you + select both a vendor and an architecture, only boards that match both will be displayed. Within + a single field, selecting multiple options (such as two architectures) will show boards + matching **either** option. * The list of supported hardware features for each board is automatically generated using information from the Devicetree. It may not be reflecting the full list of supported features @@ -40,14 +42,3 @@ this page `. */index .. zephyr:board-catalog:: - -.. _boards-shields: - -Shields -####### - -.. toctree:: - :maxdepth: 1 - :glob: - - shields/**/* diff --git a/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig b/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig index 645567a40c7..f58a5582d26 100644 --- a/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig +++ b/boards/infineon/cyw920829m2evk_02/Kconfig.defconfig @@ -11,3 +11,6 @@ endchoice config HEAP_MEM_POOL_ADD_SIZE_BOARD int default 10096 + +config ROM_START_OFFSET + default 0x0 if BOOTLOADER_MCUBOOT diff --git a/boards/infineon/cyw920829m2evk_02/board.cmake b/boards/infineon/cyw920829m2evk_02/board.cmake index be95fa715a3..76fe7d1bdc4 100644 --- a/boards/infineon/cyw920829m2evk_02/board.cmake +++ b/boards/infineon/cyw920829m2evk_02/board.cmake @@ -2,6 +2,21 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(openocd "--target-handle=TARGET.cm33") + +# MCUboot requires a flashloader with 64k erase size, please use 'west blobs fetch hal_infineon' to download it. +if(CONFIG_BOOTLOADER_MCUBOOT) + set(flashloader_blobs_path ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/zephyr/blobs/flashloader/TARGET_CYW920829M2EVK-02) + + if(NOT EXISTS ${flashloader_blobs_path}/CYW208xx_SMIF_64K.FLM) + message(WARNING "MCUboot requires a flashloader with 64k erase size, please use 'west blobs fetch hal_infineon' to download it") + else() + board_runner_args(openocd "--openocd-search=${flashloader_blobs_path}") + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_CYW208xx_SMIF_64K.cfg") + endif() +endif() + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) board_runner_args(jlink "--device=CYW20829_tm") include (${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +set_property(TARGET runners_yaml_props_target PROPERTY hex_file zephyr_merged.hex) diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts index 92a748d2ee1..b3988367980 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts @@ -19,7 +19,8 @@ chosen { zephyr,sram = &sram0; - zephyr,flash = &app_region; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; zephyr,console = &uart2; zephyr,shell-uart = &uart2; zephyr,bt-hci = &bluetooth; @@ -99,45 +100,48 @@ uart2: &scb2 { status = "okay"; }; -/ { - qspi_flash: qspi_flash@40890000 { - compatible = "infineon,cat1-qspi-flash"; - reg = <0x40890000 0x30000>; + +&qspi_flash { + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + reg = <0x08000000 DT_SIZE_M(1)>; + write-block-size = <1>; + erase-block-size = ; #address-cells = <1>; #size-cells = <1>; - flash0: flash@8000000 { - compatible = "soc-nv-flash"; - reg = <0x08000000 DT_SIZE_K(512)>; - write-block-size = <1>; - erase-block-size = ; + /* Keep bootstrap_region node to know size, finaly it will + * locate on beginning of code-partition. The BootROM copies + * bootstrap application in RAM and launches it. + */ + bootstrap_region: bootstrap_region@0 { + reg = <0 BOOTSTRAP_SIZE>; + }; + + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - toc2_region: toc2_region@8000000 { - compatible = "zephyr,memory-region", "soc-nv-flash"; - zephyr,memory-region = "APP_HEADER_FLASH"; - reg = <0x08000000 0x50>; - }; - bootstrap_region: bootstrap_region@8000050 { - compatible = "zephyr,memory-region", "soc-nv-flash"; - zephyr,memory-region = "BOOTSTRAP_FLASH"; - reg = <0x08000050 DT_SIZE_K(12)>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x20000>; + read-only; }; - app_region: app_region@8003050 { - compatible = "soc-nv-flash"; - reg = <0x08003050 0x6CFB0>; /* 435kb */ + + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x20000 0x60000>; }; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x80000 0x60000>; + }; - storage_partition: storage_partition@60000 { - compatible = "soc-nv-flash"; - reg = <0x60000 DT_SIZE_K(64)>; - }; + storage_partition: storage_partition@E0000 { + compatible = "soc-nv-flash"; + reg = <0xE0000 DT_SIZE_K(64)>; }; }; }; diff --git a/boards/infineon/cyw920829m2evk_02/doc/index.rst b/boards/infineon/cyw920829m2evk_02/doc/index.rst index 0dd56962c15..f1101dc3e9c 100644 --- a/boards/infineon/cyw920829m2evk_02/doc/index.rst +++ b/boards/infineon/cyw920829m2evk_02/doc/index.rst @@ -3,9 +3,19 @@ Overview ******** -The AIROC™ CYW20829 Bluetooth® LE MCU Evaluation Kit (CYW920829M2EVK-02) with its included on-board peripherals enables evaluation, prototyping, and development of a wide array of Bluetooth® Low Energy applications, all on Infineon's low power, high performance AIROC™ CYW20829. The AIROC™ CYW20829's robust RF performance and 10 dBm TX output power without an external power amplifier (PA). This provides enough link budget for the entire spectrum of Bluetooth® LE use cases including industrial IoT applications, smart home, asset tracking, beacons and sensors, and medical devices. - -The system features Dual Arm® Cortex® - M33s for powering the MCU and Bluetooth subsystem with programmable and reconfigurable analog and digital blocks. In addition, on the kit, there is a suite of on-board peripherals including six-axis inertial measurement unit (IMU), thermistor, analog mic, user programmable buttons (2), LEDs (2), and RGB LED. There is also extensive GPIO support with extended headers and Arduino Uno R3 compatibility for third-party shields. +The AIROC™ CYW20829 Bluetooth® LE MCU Evaluation Kit (CYW920829M2EVK-02) with its included on-board +peripherals enables evaluation, prototyping, and development of a wide array of +Bluetooth® Low Energy applications, all on Infineon's low power, high performance AIROC™ CYW20829. +The AIROC™ CYW20829's robust RF performance and 10 dBm TX output power without an external power +amplifier (PA). This provides enough link budget for the entire spectrum of Bluetooth® LE use cases +including industrial IoT applications, smart home, asset tracking, beacons and sensors, and +medical devices. + +The system features Dual Arm® Cortex® - M33s for powering the MCU and Bluetooth subsystem with +programmable and reconfigurable analog and digital blocks. In addition, on the kit, there is a +suite of on-board peripherals including six-axis inertial measurement unit (IMU), thermistor, +analog mic, user programmable buttons (2), LEDs (2), and RGB LED. There is also extensive GPIO +support with extended headers and Arduino Uno R3 compatibility for third-party shields. Hardware ******** @@ -20,7 +30,8 @@ Kit Features: - AIROC™ CYW20829 Bluetooth® LE MCU in 56 pin QFN package - Arduino compatible headers for hardware expansion -- On-board sensors - 6-axis IMU, Thermistor, Infineon analog microphone, and Infineon digital microphone +- On-board sensors - 6-axis IMU, Thermistor, Infineon analog microphone, + and Infineon digital microphone - User switches, RGB LED and user LEDs - USB connector for power, programming and USB-UART bridge @@ -71,24 +82,38 @@ Programming and Debugging .. zephyr:board-supported-runners:: -The CYW920829M2EVK-02 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. +The CYW920829M2EVK-02 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, +flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and +require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. -The CYW920829M2EVK-02 supports RTT via a SEGGER JLink device, under the target name cyw20829_tm. This can be enabled for an application by building with the rtt-console snippet or setting the following config values: CONFIG_UART_CONSOLE=n, CONFIG_RTT_CONSOLE=y, and CONFIG_USE_SEGGER_RTT=y. +The CYW920829M2EVK-02 supports RTT via a SEGGER JLink device, under the target name cyw20829_tm. +This can be enabled for an application by building with the rtt-console snippet or setting the +following config values: CONFIG_UART_CONSOLE=n, CONFIG_RTT_CONSOLE=y, and CONFIG_USE_SEGGER_RTT=y. e.g. west build -p always -b cyw920829m2evk_02 samples/basic/blinky -S rtt-console -As an additional note there is currently a discrepancy in RAM address between SEGGER and the CYW920829M2EVK-02 device. So, for RTT control block, do not use "Auto Detection". Instead, set the search range to something reflecting: RAM RangeStart at 0x20000000 and RAM RangeSize of 0x3d000. +As an additional note there is currently a discrepancy in RAM address between SEGGER and the +CYW920829M2EVK-02 device. So, for RTT control block, do not use "Auto Detection". Instead, set +the search range to something reflecting: RAM RangeStart at 0x20000000 and RAM RangeSize of 0x3d000. Infineon OpenOCD Installation ============================= -Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon +OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package +is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for +your system and manually extract the files to a location of your choice. -.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled + automatically by the ModusToolbox and ModusToolbox Programming Tools installations. + When doing a minimal installation, this can be done manually by executing the + script ``openocd/udev_rules/install_rules.sh``. West Commands ============= -The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool +commands. There are multiple ways of doing this. The example below uses a permanent CMake argument +to set the CMake variable ``OPENOCD``. .. tabs:: .. group-tab:: Windows @@ -117,7 +142,101 @@ The path to the installed Infineon OpenOCD executable must be available to the ` west flash west debug -Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the CYW20829 CM33 core. +Once the gdb console starts after executing the west debug command, you may now set breakpoints and +perform other standard GDB debugging on the CYW20829 CM33 core. + +Operate in SECURE Lifecycle Stage +********************************* + +The device lifecycle stage (LCS) is a key aspect of the security of the AIROC™ +CYW20829 Bluetooth® MCU. The lifecycle stages follow a strict, irreversible progression dictated by +the programming of the eFuse bits (changing the value from "0" to "1"). This system is used to +protect the device's data and code at the level required by the user. +SECURE is the lifecycle stage of a secured device. +Follow the instructions in `AN239590 Provision CYW20829 to SECURE LCS`_ to transition the device +to SECURE LCS. In the SECURE LCS stage, the protection state is set to secure. A secured device +will only boot if the authentication of its flash content is successful. + +The following configuration options can be used to build for a device which has been provisioned +to SECURE LCS and configured to use an encrypted flash interface: + +- :kconfig:option:`CONFIG_INFINEON_SECURE_LCS`: Enable if the target device is in SECURE LCS +- :kconfig:option:`CONFIG_INFINEON_SECURE_POLICY`: Path to the policy JSON file, + which was created for provisioning the device to SECURE LCS (refer to section 3.2 "Key creation" + of `AN239590 Provision CYW20829 to SECURE LCS`_) +- :kconfig:option:`CONFIG_INFINEON_SMIF_ENCRYPTION`: Enable to use encrypted flash interface when provisioned to + SECURE LCS. + +Here is an example for building the :zephyr:code-sample:`blinky` sample application for SECURE LCS. + +.. zephyr-app-commands:: + :goals: build + :board: cyw920829m2evk_02 + :zephyr-app: samples/basic/blinky + :west-args: -p always + :gen-args: -DCONFIG_INFINEON_SECURE_LCS=y -DCONFIG_INFINEON_SECURE_POLICY=\"policy/policy_secure.json\" + +Using MCUboot +************* + +CYW20829 devices are supported by the Cypress MCU bootloader (MCUBootApp) from the +`Cypress branch of MCUboot`_. + +Building Cypress MCU Bootloader MCUBootApp +========================================== + +Please refer to the `CYW20829 platform description`_ and follow the instructions to understand the +MCUBootApp building process for normal/secure silicon and its overall usage as a bootloader. +Place keys and policy-related folders in the cypress directory ``mcuboot/boot/cypress/``. + +Ensure the default memory map matches the memory map of the Zephyr application (refer to partitions +of flash0 in :zephyr_file:`boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts`). + +You can use ``west flash`` to flash MCUBootApp: + +.. code-block:: shell + + # Flash MCUBootApp.hex + west flash --skip-rebuild --hex-file /path/to/cypress/mcuboot/boot/cypress/MCUBootApp/out/CYW20829/Debug/MCUBootApp.hex + +.. note:: ``west flash`` requires an existing Zephyr build directory which can be created by first + building any Zephyr application for the target board. + +Build Zephyr application +======================== +Here is an example for building and flashing the :zephyr:code-sample:`blinky` sample application +for MCUboot. + +.. zephyr-app-commands:: + :goals: build flash + :board: cyw920829m2evk_02 + :zephyr-app: samples/basic/blinky + :west-args: -p always + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"/path/to/cypress/mcuboot/boot/cypress/keys/cypress-test-ec-p256.pem\" + +If you use :kconfig:option:`CONFIG_MCUBOOT_ENCRYPTION_KEY_FILE` to generate an encrypted image then the final +hex will be ``zephyr.signed.encrypted.hex`` and the corresponding bin file will +be ``zephyr.signed.encrypted.bin``. Use these files for flashing and ota uploading respectively. +For example, to build and flash an encrypted :zephyr:code-sample:`blinky` sample application +image for MCUboot: + +.. zephyr-app-commands:: + :goals: build flash + :board: cyw920829m2evk_02 + :zephyr-app: samples/basic/blinky + :west-args: -p always + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"/path/to/cypress/mcuboot/boot/cypress/keys/cypress-test-ec-p256.pem\" -DCONFIG_MCUBOOT_ENCRYPTION_KEY_FILE=\"/path/to/cypress/mcuboot/enc-ec256-pub.pem\" + :flash-args: --hex-file build/zephyr/zephyr.signed.encrypted.hex + + +.. _CYW20829 platform description: + https://github.com/mcu-tools/mcuboot/blob/v1.9.4-cypress/boot/cypress/platforms/CYW20829.md + +.. _Cypress branch of MCUboot: + https://github.com/mcu-tools/mcuboot/tree/cypress + +.. _AN239590 Provision CYW20829 to SECURE LCS: + https://www.infineon.com/dgdl/Infineon-AN239590_Provision_CYW20829_CYW89829_to_Secure_LCS-ApplicationNotes-v02_00-EN.pdf?fileId=8ac78c8c8d2fe47b018e3677dd517258 .. _CYW20829 SoC Website: https://www.infineon.com/cms/en/product/wireless-connectivity/airoc-bluetooth-le-bluetooth-multiprotocol/airoc-bluetooth-le/cyw20829/ diff --git a/boards/infineon/cyw920829m2evk_02/support/openocd.cfg b/boards/infineon/cyw920829m2evk_02/support/openocd.cfg index fe70fb383a8..d6578e98a03 100644 --- a/boards/infineon/cyw920829m2evk_02/support/openocd.cfg +++ b/boards/infineon/cyw920829m2evk_02/support/openocd.cfg @@ -2,7 +2,6 @@ # Copyright (c) 2018 Linaro Limited. # # SPDX-License-Identifier: Apache-2.0 - source [find interface/kitprog3.cfg] transport select swd diff --git a/boards/infineon/cyw920829m2evk_02/support/openocd_CYW208xx_SMIF_64K.cfg b/boards/infineon/cyw920829m2evk_02/support/openocd_CYW208xx_SMIF_64K.cfg new file mode 100644 index 00000000000..d1f0a09f855 --- /dev/null +++ b/boards/infineon/cyw920829m2evk_02/support/openocd_CYW208xx_SMIF_64K.cfg @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 Linaro Limited. +# +# SPDX-License-Identifier: Apache-2.0 +set QSPI_FLASHLOADER "CYW208xx_SMIF_64K.FLM" + +source [find openocd.cfg] diff --git a/boards/infineon/kit_xmc72_evk/Kconfig.kit_xmc72_evk b/boards/infineon/kit_xmc72_evk/Kconfig.kit_xmc72_evk new file mode 100644 index 00000000000..aced322b302 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/Kconfig.kit_xmc72_evk @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KIT_XMC72_EVK + select SOC_XMC7200D_E272K8384_M0PLUS if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M0P + select SOC_XMC7200D_E272K8384_M7_0 if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M7_0 + select SOC_XMC7200D_E272K8384_M7_1 if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M7_1 diff --git a/boards/infineon/kit_xmc72_evk/board.cmake b/boards/infineon/kit_xmc72_evk/board.cmake new file mode 100644 index 00000000000..f1b6975385b --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +# Connect to CM0P core. +board_runner_args(openocd "--target-handle=cat1c.cpu.cm0") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/infineon/kit_xmc72_evk/board.yml b/boards/infineon/kit_xmc72_evk/board.yml new file mode 100644 index 00000000000..84d3c3898eb --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/board.yml @@ -0,0 +1,6 @@ +board: + name: kit_xmc72_evk + full_name: XMC7200 Evaluation Kit + vendor: infineon + socs: + - name: xmc7200d_e272k8384 diff --git a/boards/infineon/kit_xmc72_evk/doc/img/kit_xmc72_evk.webp b/boards/infineon/kit_xmc72_evk/doc/img/kit_xmc72_evk.webp new file mode 100644 index 00000000000..18338ea90ca Binary files /dev/null and b/boards/infineon/kit_xmc72_evk/doc/img/kit_xmc72_evk.webp differ diff --git a/boards/infineon/kit_xmc72_evk/doc/index.rst b/boards/infineon/kit_xmc72_evk/doc/index.rst new file mode 100644 index 00000000000..dcb62ea0e10 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/doc/index.rst @@ -0,0 +1,146 @@ +.. zephyr:board:: kit_xmc72_evk + +Overview +******** + +The XMC7200 evaluation kit enables you to evaluate and develop your applications using the XMC7200D +microcontroller(hereafter called “XMC7200D”). The XMC7200D is designed for industrial applications +and it is a true programmable embedded system-on-chip, integrating up to two 350-MHz Arm® Cortex®-M7 +as the primary application processor, a 100-MHz Arm® Cortex®-M0+ that supports the following: + +- Low-power operations +- Up to 8 MB flash and 1 MB SRAM +- Gigabit Ethernet +- CAN FD +- Secure Digital Host Controller (SDHC) supporting SD/SDIO/eMMC interfaces +- Programmable analog and digital peripherals that allow faster time-to-market + +The evaluation board has a M.2 interface connector for interfacing radio modules-based on +AIROC™ Wi-Fi & Bluetooth combos, SMIF dual header compatible with Digilent Pmod for interfacing +HYPERBUS™ memories, and headers compatible with Arduino for interfacing Arduino shields. +In addition, the board features an onboard programmer/debugger(KitProg3), a 512-Mbit QSPI NOR flash, +CAN FD transceiver, Gigabit Ethernet PHY transceiver with RJ45 connector interface, a micro-B +connector for USB device interface, three user LEDs, one potentiometer, and two push buttons. +The board supports operating voltages from 3.3 V to 5.0 V for XMC7200D. + +Hardware +******** + +For more information about XMC7200D and KIT_XMC72_EVK: + +- `XMC7200D SoC Website`_ +- `kit_xmc72_evk Board Website`_ + +Kit Features +============= + +- Evaluation board for XMC7200D-E272K8384 in BGA package with 272 pins, dual-core Arm®Cortex® M7 CPUs running at 350-MHz and an Arm® Cortex® M0+ CPU running at 100-MHz +- Full-system approach on the board, featuring Gigabit Ethernet PHY and connector, CAN FD transceiver, user LEDs, buttons, and potentiometer +- M.2 interface connector for interfacing radio modules based on AIROC™ Wi-Fi & Bluetooth®combos (currently not - supported) +- Headers compatible with Arduino for interfacing Arduino shields +- Fully compatible with ModusToolbox™ v3.0 +- KitProg3 on-board SWD programmer/debugger, USB-UART, and USB-I2C bridge functionality through USB connector +- Digilent dual PMOD SMIF header for interfacing HYPERBUS™ memories (currently not supported) +- A 512-Mbit external QSPI NOR flash +- Evaluation board supports operating voltages from 3.3 V to 5.0 V for XMC7200D + +Kit Contents +============= + +- XMC7200 evaluation board +- USB Type-A to Mirco-B cable +- 12V/3A DC power adapter with additional blades +- Six jumper wires (five inches each) +- Quick start guide + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Building +======== + +Here is an example for building the :zephyr:code-sample:`blinky` sample application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: kit_xmc72_evk + :goals: build + +Flashing +======== + +The KIT_XMC72_EVK includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. +Installing either of these packages will also install Infineon OpenOCD. + +If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. + +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b kit_xmc72_evk -p always samples/basic/blinky + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b kit_xmc72_evk -p always samples/basic/blinky + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging. + +References +********** + +.. target-notes:: + +.. _XMC7200D SoC Website: + https://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-cortex-m/32-bit-xmc7000-industrial-microcontroller-arm-cortex-m7/xmc7200d-e272k8384aa/ + +.. _kit_xmc72_evk Board Website: + https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc72_evk + +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi new file mode 100644 index 00000000000..66cc3376f4a --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2025 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + aliases { + uart-3 = &uart3; + led0 = &user_led0; + led1 = &user_led1; + led2 = &user_led2; + sw0 = &user_bt0; + sw1 = &user_bt1; + }; + + leds { + compatible = "gpio-leds"; + + user_led0: led_0 { + label = "LED_0"; + gpios = <&gpio_prt16 1 GPIO_ACTIVE_LOW>; + }; + + user_led1: led_1 { + label = "LED_1"; + gpios = <&gpio_prt16 2 GPIO_ACTIVE_LOW>; + }; + + user_led2: led_2 { + label = "LED_2"; + gpios = <&gpio_prt16 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_bt0: user_btn0 { + label = "SW_1"; + gpios = <&gpio_prt21 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + + user_bt1: user_btn1 { + label = "SW_2"; + gpios = <&gpio_prt17 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +uart3: &scb3 { + compatible = "infineon,cat1-uart"; + status = "okay"; + current-speed = <115200>; + + /* UART pins */ + pinctrl-0 = <&p13_1_scb3_uart_tx &p13_0_scb3_uart_rx + &p13_2_scb3_uart_rts &p13_3_scb3_uart_cts>; + pinctrl-names = "default"; +}; + +&gpio_prt13 { + status = "okay"; +}; + +&gpio_prt16 { + status = "okay"; +}; + +&gpio_prt21 { + status = "okay"; +}; + +&gpio_prt17 { + status = "okay"; +}; + +&path_mux0 { + status = "okay"; +}; + +&path_mux1 { + status = "okay"; +}; + +&path_mux2 { + status = "okay"; +}; + +&path_mux3 { + status = "okay"; +}; + +&clk_mem { + status = "okay"; +}; + +&clk_peri { + status = "okay"; +}; + +&clk_slow { + status = "okay"; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi new file mode 100644 index 00000000000..56433a55d12 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin control bias mode for uart2 pins */ +&p13_1_scb3_uart_tx { + drive-push-pull; +}; + +&p13_0_scb3_uart_rx { + input-enable; +}; + +&p13_2_scb3_uart_rts { + drive-push-pull; +}; + +&p13_3_scb3_uart_cts { + input-enable; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts new file mode 100644 index 00000000000..0820c7d6693 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi" +#include "kit_xmc72_evk_common.dtsi" + +/ { + model = "Infineon Evaluation board for XMC7200D-E272K8384 M0"; + compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200"; + + chosen { + zephyr,sram = &m0p_code; + zephyr,flash = &m0p_data; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.yaml b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.yaml new file mode 100644 index 00000000000..f9c85c01943 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.yaml @@ -0,0 +1,15 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: kit_xmc72_evk/xmc7200d_e272k8384/m0p +name: XMC7200 Evaluation Kit (M0P) +type: mcu +arch: arm +ram: 1024 +flash: 8384 +toolchain: + - zephyr + - gnuarmemb +vendor: infineon diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p_defconfig b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p_defconfig new file mode 100644 index 00000000000..092553cedd5 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p_defconfig @@ -0,0 +1,24 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_BIN=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts new file mode 100644 index 00000000000..ba9993f34c5 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi" +#include "kit_xmc72_evk_common.dtsi" + +/ { + + model = "Infineon Evaluation board for XMC7200D-E272K8384 M7"; + compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200"; + + aliases { + uart-3 = &uart3; + }; + + chosen { + zephyr,sram = &cm7_0_code; + zephyr,flash = &cm7_0_data; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.yaml b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.yaml new file mode 100644 index 00000000000..745e4a09d58 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: kit_xmc72_evk/xmc7200d_e272k8384/m7_0 +name: XMC7200 Evaluation Kit (M7_0) +type: mcu +arch: arm +ram: 1024 +flash: 8384 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: infineon diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0_defconfig b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0_defconfig new file mode 100644 index 00000000000..ad327f90539 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0_defconfig @@ -0,0 +1,25 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_BIN=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CACHE_MANAGEMENT=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts new file mode 100644 index 00000000000..ce8b078d7e4 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi" +#include "kit_xmc72_evk_common.dtsi" + +/ { + + model = "Infineon Evaluation board for XMC7200D-E272K8384 M7"; + compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200"; + + aliases { + uart-3 = &uart3; + }; + + chosen { + zephyr,sram = &cm7_1_code; + zephyr,flash = &cm7_1_data; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.yaml b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.yaml new file mode 100644 index 00000000000..e74a7b3f821 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: kit_xmc72_evk/xmc7200d_e272k8384/m7_1 +name: XMC7200 Evaluation Kit (M7_1) +type: mcu +arch: arm +ram: 1024 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: infineon diff --git a/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1_defconfig b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1_defconfig new file mode 100644 index 00000000000..ad327f90539 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1_defconfig @@ -0,0 +1,25 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_BIN=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_CACHE_MANAGEMENT=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/kit_xmc72_evk/support/openocd.cfg b/boards/infineon/kit_xmc72_evk/support/openocd.cfg new file mode 100644 index 00000000000..4d4249c5631 --- /dev/null +++ b/boards/infineon/kit_xmc72_evk/support/openocd.cfg @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + #default connect over Debug USB port + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +source [find target/cat1c.cfg] \ No newline at end of file diff --git a/boards/innblue/innblue21/innblue21_common.dtsi b/boards/innblue/innblue21/innblue21_common.dtsi index fbe58ffbe22..6e638823e3e 100644 --- a/boards/innblue/innblue21/innblue21_common.dtsi +++ b/boards/innblue/innblue21/innblue21_common.dtsi @@ -160,4 +160,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/innblue/innblue22/innblue22_common.dtsi b/boards/innblue/innblue22/innblue22_common.dtsi index 6ba2b69bf72..433cc38c7ab 100644 --- a/boards/innblue/innblue22/innblue22_common.dtsi +++ b/boards/innblue/innblue22/innblue22_common.dtsi @@ -163,4 +163,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp index 225a2747ad5..ac62b9e2d52 100644 --- a/boards/intel/adsp/Kconfig.intel_adsp +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -10,3 +10,5 @@ config BOARD_INTEL_ADSP select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM + select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL + select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM diff --git a/boards/intel/adsp/board.cmake b/boards/intel/adsp/board.cmake index 0add6586426..e6055be6f37 100644 --- a/boards/intel/adsp/board.cmake +++ b/boards/intel/adsp/board.cmake @@ -1,4 +1,4 @@ -# Copyright (c) 2022-2024 Intel Corporation +# Copyright (c) 2022-2025 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 @@ -47,4 +47,12 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SI board_finalize_runner_args(intel_adsp) +elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_WCL OR CONFIG_BOARD_INTEL_ADSP_ACE30_WCL_SIM) + + board_set_rimage_target(wcl) + + set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key") + + board_finalize_runner_args(intel_adsp) + endif() diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml index c169a14487b..5bc812edb37 100644 --- a/boards/intel/adsp/board.yml +++ b/boards/intel/adsp/board.yml @@ -17,3 +17,6 @@ boards: - name: 'ptl' variants: - name: 'sim' + - name: 'wcl' + variants: + - name: 'sim' diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl.dts b/boards/intel/adsp/intel_adsp_ace30_wcl.dts new file mode 100644 index 00000000000..e488d77181d --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_wcl.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace30_wcl"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &mem_window3; + }; +}; diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig b/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig new file mode 100644 index 00000000000..85f377409f7 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts b/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts new file mode 100644 index 00000000000..fab0812265e --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace30_wcl_sim"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &mem_window3; + }; +}; diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig new file mode 100644 index 00000000000..5373f0c0bf8 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_INTEL_ADSP_SIM=y +CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/twister.yaml b/boards/intel/adsp/twister.yaml index 866f8ff7a90..c5d8c9f2759 100644 --- a/boards/intel/adsp/twister.yaml +++ b/boards/intel/adsp/twister.yaml @@ -12,6 +12,20 @@ testing: - bluetooth - mcumgr variants: + intel_adsp/ace30/wcl: + toolchain: + - xt-clang + - zephyr + intel_adsp/ace30/wcl/sim: + type: sim + simulation: + - name: custom + exec: acesim + toolchain: + - xt-clang + - zephyr + testing: + timeout_multiplier: 8 intel_adsp/ace30/ptl: toolchain: - xt-clang diff --git a/boards/intel/btl/intel_btl_s_crb.yaml b/boards/intel/btl/intel_btl_s_crb.yaml index a569213d394..cb340c11d13 100644 --- a/boards/intel/btl/intel_btl_s_crb.yaml +++ b/boards/intel/btl/intel_btl_s_crb.yaml @@ -8,6 +8,16 @@ ram: 2048 supported: - acpi - smp + - spi + - nvme + - gpio + - uart + - tgpio + - pwm + - smbus + - rtc + - watchdog + - i2c testing: ignore_tags: - net diff --git a/boards/intel/niosv_g/board.yml b/boards/intel/niosv_g/board.yml index 811aee73f34..3ab04d5103f 100644 --- a/boards/intel/niosv_g/board.yml +++ b/boards/intel/niosv_g/board.yml @@ -1,5 +1,6 @@ board: name: niosv_g full_name: INTEL FPGA niosv_g + vendor: intel socs: - name: niosv_g diff --git a/boards/intel/niosv_m/board.yml b/boards/intel/niosv_m/board.yml index cc7b9bb3bf5..aeb8d988667 100644 --- a/boards/intel/niosv_m/board.yml +++ b/boards/intel/niosv_m/board.yml @@ -1,5 +1,6 @@ board: name: niosv_m full_name: INTEL FPGA niosv_m + vendor: intel socs: - name: niosv_m diff --git a/boards/intel/rpl/board.yml b/boards/intel/rpl/board.yml index 9f35b648699..58f24d3becd 100644 --- a/boards/intel/rpl/board.yml +++ b/boards/intel/rpl/board.yml @@ -7,5 +7,11 @@ boards: - name: intel_rpl_s_crb full_name: Raptor Lake S CRB vendor: intel + revision: + format: number + default: "600" + revisions: + - name: "600" + - name: "700" socs: - name: raptor_lake diff --git a/boards/intel/rpl/doc/index.rst b/boards/intel/rpl/doc/index.rst index e6bc4015256..9a256300050 100644 --- a/boards/intel/rpl/doc/index.rst +++ b/boards/intel/rpl/doc/index.rst @@ -12,7 +12,10 @@ architecture, utilizing P-cores for performance and E-Cores for efficiency. Raptor Lake S and Raptor Lake P processor lines are supported. The S-Processor line is a 2-Chip Platform that includes the Processor Die and -Platform Controller Hub (PCH-S) Die in the Package. +Platform Controller Hub (PCH-S) Die in the Package. There are 2 PCH-s versions +supported for S-Processor line 600 series (ADL) and 700 series (RPL). Default +600 series revision is selected, to select 700 series revision the board name +during build should be ``intel_rpl_s_crb@700``. The P-Processor line is a 2-Die Multi Chip Package (MCP) that includes the Processor Die and Platform Controller Hub (PCH-P) Die on the same package as diff --git a/boards/intel/rpl/intel_rpl_s_crb_700.overlay b/boards/intel/rpl/intel_rpl_s_crb_700.overlay new file mode 100644 index 00000000000..7e1aa5ba8e6 --- /dev/null +++ b/boards/intel/rpl/intel_rpl_s_crb_700.overlay @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2024 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&smbus0 { + device-id = <0x7a23>; +}; + +&i2c0 { + device-id = <0x7a4c>; +}; + +&i2c1 { + device-id = <0x7a4c>; +}; + +&i2c2 { + device-id = <0x7a4d>; +}; + +&i2c3 { + device-id = <0x7a4e>; +}; + +&i2c4 { + device-id = <0x7a7c>; +}; + +&i2c5 { + device-id = <0x7a7d>; +}; + +&spi0 { + device-id = <0x7a2a>; +}; + +&spi1 { + device-id = <0x7a2b>; +}; + +&spi2 { + device-id = <0x7a7b>; +}; + +&uart0 { + device-id = <0x7a28>; +}; + +&uart1 { + device-id = <0x7a29>; +}; + +&uart2 { + device-id = <0x7a7e>; +}; diff --git a/boards/intel/socfpga/agilex5_socdk/board.yml b/boards/intel/socfpga/agilex5_socdk/board.yml index f8ccbf5d8c5..13726af50a6 100644 --- a/boards/intel/socfpga/agilex5_socdk/board.yml +++ b/boards/intel/socfpga/agilex5_socdk/board.yml @@ -1,5 +1,6 @@ board: name: intel_socfpga_agilex5_socdk full_name: Agilex™ 5 SoC FPGA Development Kit + vendor: intel socs: - name: agilex5 diff --git a/boards/intel/socfpga/agilex_socdk/board.yml b/boards/intel/socfpga/agilex_socdk/board.yml index 80763baa41b..fe7d24f4b39 100644 --- a/boards/intel/socfpga/agilex_socdk/board.yml +++ b/boards/intel/socfpga/agilex_socdk/board.yml @@ -1,5 +1,6 @@ board: name: intel_socfpga_agilex_socdk full_name: Agilex SoC Development Kit + vendor: intel socs: - name: agilex diff --git a/boards/intel/socfpga_std/cyclonev_socdk/board.yml b/boards/intel/socfpga_std/cyclonev_socdk/board.yml index 222de69429a..4c47d3f9a5b 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/board.yml +++ b/boards/intel/socfpga_std/cyclonev_socdk/board.yml @@ -1,5 +1,6 @@ board: name: cyclonev_socdk full_name: Cyclone® V SoC Development Kit + vendor: intel socs: - name: cyclonev diff --git a/boards/ite/it515xx_evb/it515xx_evb.dts b/boards/ite/it515xx_evb/it515xx_evb.dts index 4d0ccfb7485..926c93bd921 100644 --- a/boards/ite/it515xx_evb/it515xx_evb.dts +++ b/boards/ite/it515xx_evb/it515xx_evb.dts @@ -15,8 +15,10 @@ compatible = "ite,it515xx-evb"; aliases { + i2c-0 = &i2c0; led0 = &led0; watchdog0 = &twd0; + pwm-0 = &pwm0; }; chosen { @@ -38,6 +40,14 @@ }; }; +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_clk_gpf2_default + &i2c0_data_gpf3_default>; + pinctrl-names = "default"; +}; + &uart1 { status = "okay"; current-speed = <115200>; @@ -111,6 +121,26 @@ pinctrl-names = "default"; }; +/* + * test pwm: + * If we need pwm output in ITE chip power saving mode, + * then we should set pwm output frequency <=324Hz. + */ +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; + +/* test fan */ +&pwm7 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm7_gpa7_default>; + pinctrl-names = "default"; +}; + /* test fan tachometer sensor */ &tach0 { status = "okay"; @@ -119,3 +149,7 @@ pinctrl-0 = <&tach0a_gpd6_default>; pinctrl-names = "default"; }; + +&sha256 { + status = "okay"; +}; diff --git a/boards/ite/it515xx_evb/it515xx_evb.yaml b/boards/ite/it515xx_evb/it515xx_evb.yaml index cddae71d22d..5ac8ab272d7 100644 --- a/boards/ite/it515xx_evb/it515xx_evb.yaml +++ b/boards/ite/it515xx_evb/it515xx_evb.yaml @@ -8,6 +8,7 @@ ram: 128 supported: - flash - gpio + - i2c - pinctrl - pm - uart diff --git a/boards/ite/it82xx2_evb/it82xx2_evb.dts b/boards/ite/it82xx2_evb/it82xx2_evb.dts index 3aa16d53df1..8dc3188edc1 100644 --- a/boards/ite/it82xx2_evb/it82xx2_evb.dts +++ b/boards/ite/it82xx2_evb/it82xx2_evb.dts @@ -134,15 +134,14 @@ pinctrl-names = "default"; }; -/* pwm for test */ +/* + * pwm for test: + * If we need pwm output in ITE chip power saving mode, + * then we should set frequency <=324Hz. + */ &pwm0 { status = "okay"; prescaler-cx = ; - /* - * If we need pwm output in ITE chip power saving mode, - * then we should set frequency <=324Hz. - */ - pwm-output-frequency = <324>; pinctrl-0 = <&pwm0_gpa0_default>; pinctrl-names = "default"; }; @@ -151,7 +150,6 @@ &pwm7 { status = "okay"; prescaler-cx = ; - pwm-output-frequency = <30000>; pinctrl-0 = <&pwm7_gpa7_default>; pinctrl-names = "default"; }; diff --git a/boards/ite/it8xxx2_evb/board.cmake b/boards/ite/it8xxx2_evb/board.cmake index 6a3abe8ddd9..a9763a8bad4 100644 --- a/boards/ite/it8xxx2_evb/board.cmake +++ b/boards/ite/it8xxx2_evb/board.cmake @@ -1,4 +1,2 @@ -set(SUPPORTED_EMU_PLATFORMS renode) -set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/it8xxx2_evb.resc) board_set_flasher_ifnset(misc-flasher) board_finalize_runner_args(misc-flasher) diff --git a/boards/ite/it8xxx2_evb/it8xxx2_evb.dts b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts index 59b4af711c9..2116f89b20c 100644 --- a/boards/ite/it8xxx2_evb/it8xxx2_evb.dts +++ b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts @@ -121,15 +121,14 @@ &uart2_tx_gph2_default>; pinctrl-names = "default"; }; -/* pwm for test */ +/* + * pwm for test: + * If we need pwm output in ITE chip power saving mode, + * then we should set frequency <=324Hz. + */ &pwm0 { status = "okay"; prescaler-cx = ; - /* - * If we need pwm output in ITE chip power saving mode, - * then we should set frequency <=324Hz. - */ - pwm-output-frequency = <324>; pinctrl-0 = <&pwm0_gpa0_default>; pinctrl-names = "default"; }; @@ -137,7 +136,6 @@ &pwm7 { status = "okay"; prescaler-cx = ; - pwm-output-frequency = <30000>; pinctrl-0 = <&pwm7_gpa7_default>; pinctrl-names = "default"; }; diff --git a/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc b/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc deleted file mode 100644 index 5ef1ae4e5bb..00000000000 --- a/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc +++ /dev/null @@ -1,17 +0,0 @@ -:name: ITE-evb -:description: This script is prepared to run Zephyr on a Mi-V RISC-V board. - -$name?="ITE-evb" - -using sysbus -mach create $name -machine LoadPlatformDescription @platforms/boards/it8xxx2_evb.repl - -showAnalyzer uart -cpu PerformanceInMips 80 - -macro reset -""" - sysbus LoadELF $elf -""" -runMacro $reset diff --git a/boards/kws/pico2_spe/doc/index.rst b/boards/kws/pico2_spe/doc/index.rst index 48bccacea86..09302b967ad 100644 --- a/boards/kws/pico2_spe/doc/index.rst +++ b/boards/kws/pico2_spe/doc/index.rst @@ -44,8 +44,19 @@ Programming and Debugging .. zephyr:board-supported-runners:: -As with the Pico-SPE, the SWD interface can be used to program and debug the -device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . +As with the Pico-SPE, the SWD interface can be used to program and debug the device, +e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . + +The overall explanation regarding flashing and debugging is the same as for :zephyr:board:`rpi_pico`. +Refer to :ref:`rpi_pico_programming_and_debugging` for more information. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. + +Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: pico2_spe/rp2350a/m33 + :goals: build flash + :flash-args: --openocd /usr/local/bin/openocd References ********** diff --git a/boards/kws/pico_spe/doc/index.rst b/boards/kws/pico_spe/doc/index.rst index 3246d36a972..1352905638b 100644 --- a/boards/kws/pico_spe/doc/index.rst +++ b/boards/kws/pico_spe/doc/index.rst @@ -84,144 +84,19 @@ Programming and Debugging .. zephyr:board-supported-runners:: -Flashing -======== +The SWD interface can be used to program and debug the device, +e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . -Using SEGGER JLink ------------------- +The overall explanation regarding flashing and debugging is the same as for :zephyr:board:`rpi_pico`. +Refer to :ref:`rpi_pico_programming_and_debugging` for more information. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. -You can Flash the pico_spe with a SEGGER JLink debug probe as described in -:ref:`Building, Flashing and Debugging `. - -Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: pico_spe - :goals: build - -.. code-block:: bash - - west flash --runner jlink - -Using OpenOCD -------------- - -To use CMSIS-DAP, you must configure **udev**. - -Create a file in /etc/udev.rules.d with any name, and write the line below. - -.. code-block:: bash - - ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess" - -This example is valid for the case that the user joins to ``plugdev`` groups. - -The Pico-SPE has an SWD interface that can be used to program -and debug the on board RP2040. This interface can be utilized by OpenOCD. -To use it with the RP2040, OpenOCD version 0.12.0 or later is needed. - -If you are using a Debian based system (including RaspberryPi OS, Ubuntu. and more), -using the `pico_setup.sh`_ script is a convenient way to set up the forked version of OpenOCD. - -Depending on the interface used (such as JLink), you might need to -checkout to a branch that supports this interface, before proceeding. -Build and install OpenOCD as described in the README. - -Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. +Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky :board: pico_spe :goals: build flash - :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap - -Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd` -and **OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should work -with the OpenOCD that was installed with the default configuration. -This configuration also works with an environment that is set up by the `pico_setup.sh`_ script. - -**RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. - -If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``cmsis-dap`` is used by default. -The other supported adapters are ``raspberrypi-swd``, ``jlink`` and ``blackmagicprobe``. -How to connect ``cmsis-dap`` and ``raspberrypi-swd`` is described in `Getting Started with Pico-SPE-Series`_. -Any other SWD debug adapter maybe also work with this configuration. - -The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from -``west flash`` and ``west debug`` if it was previously set while running -``west build``. - -**RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as ``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. -Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter. - -You can also flash the board with the following -command that directly calls OpenOCD (assuming a SEGGER JLink adapter is used): - -.. code-block:: console - - $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0' -c 'program path/to/zephyr.elf verify reset exit' - -Using UF2 ---------- - -If you don't have an SWD adapter, you can flash the Pico-SPE with -a UF2 file. By default, building an app for this board will generate a -:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` -button pressed, it will appear on the host as a mass storage device. The -UF2 file should be drag-and-dropped to the device, which will flash the Pico. - -Debugging -========= - -The SWD interface can also be used to debug the board. To achieve this, you can -either use SEGGER JLink or OpenOCD. - -Using SEGGER JLink ------------------- - -Use a SEGGER JLink debug probe and follow the instruction in -:ref:`Building, Flashing and Debugging`. - - -Using OpenOCD -------------- - -Install OpenOCD as described for flashing the board. - -Here is an example for debugging the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: pico_spe - :maybe-skip-config: - :goals: debug - :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd - -As with flashing, you can specify the debug adapter by specifying **RPI_PICO_DEBUG_ADAPTER** -at ``west build`` time. No needs to specify it at ``west debug`` time. - -You can also debug with OpenOCD and gdb launching from command-line. -Run the following command: - -.. code-block:: console - - $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0' - -On another terminal, run: - -.. code-block:: console - - $ gdb-multiarch - -Inside gdb, run: - -.. code-block:: console - - (gdb) tar ext :3333 - (gdb) file path/to/zephyr.elf - -You can then start debugging the board. + :flash-args: --openocd /usr/local/bin/openocd .. target-notes:: diff --git a/boards/lilygo/ttgo_tbeam/Kconfig b/boards/lilygo/ttgo_tbeam/Kconfig index c52379f257a..c95a97a11aa 100644 --- a/boards/lilygo/ttgo_tbeam/Kconfig +++ b/boards/lilygo/ttgo_tbeam/Kconfig @@ -5,3 +5,6 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD int default 4096 if BOARD_TTGO_TBEAM_ESP32_PROCPU default 256 if BOARD_TTGO_TBEAM_ESP32_APPCPU + +config GNSS_INIT_PRIORITY + default 87 diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts index 43143525fb5..88deaae04d2 100644 --- a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts @@ -118,6 +118,17 @@ regulator-boot-on; }; }; + + charger: charger { + compatible = "x-powers,axp2101-charger"; + charge-term-current-microamp = <25000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4200000>; + }; + + fuel_gauge: fuel_gauge { + compatible = "x-powers,axp2101-fuel-gauge"; + }; }; }; diff --git a/boards/madmachine/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts index ea9dd21d797..cd398cc5234 100644 --- a/boards/madmachine/mm_feather/mm_feather.dts +++ b/boards/madmachine/mm_feather/mm_feather.dts @@ -60,11 +60,13 @@ reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; }; }; @@ -171,6 +173,12 @@ pinctrl-2 = <&pinmux_usdhc1_med>; pinctrl-3 = <&pinmux_usdhc1_fast>; pinctrl-names = "default", "slow", "med", "fast"; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; }; &edma0 { diff --git a/boards/madmachine/mm_feather/mm_feather.yaml b/boards/madmachine/mm_feather/mm_feather.yaml index a4541bc88a8..dfd28db8b7a 100644 --- a/boards/madmachine/mm_feather/mm_feather.yaml +++ b/boards/madmachine/mm_feather/mm_feather.yaml @@ -22,4 +22,3 @@ supported: - uart - pwm - spi -vendor: nxp diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts index 814c448c1d8..54ad772396c 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.dts +++ b/boards/madmachine/mm_swiftio/mm_swiftio.dts @@ -60,11 +60,13 @@ reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; }; }; diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.yaml b/boards/madmachine/mm_swiftio/mm_swiftio.yaml index dbd5b79b7b6..fa4ad27a5c6 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.yaml +++ b/boards/madmachine/mm_swiftio/mm_swiftio.yaml @@ -16,4 +16,3 @@ flash: 8192 supported: - counter - sdhc -vendor: nxp diff --git a/boards/microchip/sam/sama7g54_ek/Kconfig.sama7g54_ek b/boards/microchip/sam/sama7g54_ek/Kconfig.sama7g54_ek new file mode 100644 index 00000000000..23880df7541 --- /dev/null +++ b/boards/microchip/sam/sama7g54_ek/Kconfig.sama7g54_ek @@ -0,0 +1,7 @@ +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_SAMA7G54_EK + select SOC_SAMA7G54 diff --git a/boards/microchip/sam/sama7g54_ek/board.yml b/boards/microchip/sam/sama7g54_ek/board.yml new file mode 100644 index 00000000000..4b4c3da4f19 --- /dev/null +++ b/boards/microchip/sam/sama7g54_ek/board.yml @@ -0,0 +1,6 @@ +board: + name: sama7g54_ek + full_name: SAMA7G54 Evaluation Kit + vendor: microchip + socs: + - name: sama7g54 diff --git a/boards/microchip/sam/sama7g54_ek/doc/img/sama7g54_ek.webp b/boards/microchip/sam/sama7g54_ek/doc/img/sama7g54_ek.webp new file mode 100644 index 00000000000..d7cecc6f778 Binary files /dev/null and b/boards/microchip/sam/sama7g54_ek/doc/img/sama7g54_ek.webp differ diff --git a/boards/microchip/sam/sama7g54_ek/doc/index.rst b/boards/microchip/sam/sama7g54_ek/doc/index.rst new file mode 100644 index 00000000000..89ee4c83c6b --- /dev/null +++ b/boards/microchip/sam/sama7g54_ek/doc/index.rst @@ -0,0 +1,64 @@ +.. zephyr:board:: sama7g54_ek + +Overview +******** + +The SAMA7G54-EK evaluation kit is intended for evaluating and prototyping with +the SAMA7G54 microprocessor (MPU). The SAMA7G54 is a Arm Cortex-A7 based MPU +running up to 1GHz supporting up to 2GBytes of 16-bit DDR2, DDR3, DDR3L, LPDDR2, +LPDDR3, with octal/quad SPI, NAND and e.MMC Flash support. + +The SAMA7G54 integrates a complete imaging and audio subsystems with 12-bit +parallel and MIPI-CSI2 camera interfaces up to 8 Mp and 720p @ 60 fps, up to +four I2S, one SPDIF transmitter and receiver and a 4-stereo channel audio sample +rate converter. The device also features a large number of connectivity options +including Dual Ethernet (one Gigabit ethernet and one 10/100 Ethernet), six +CAN-FD and three high-speed USB and offers advanced security functions such as: +secure boot, secure key storage, high-performance crypto accelerators for AES, +SHA, RSA and ECC. + +The SAMA7G54-EK board itself features connectors and expansion headers for easy +customization and quick access to leading edge embedded features such as MIKROE +Click boards™ and Raspberry Pi expansion header plus MIPI CSI camera. + +Hardware +******** + +- SAMA7G54-V/4HB Microprocessor +- Raspberry Pi CSI camera interface +- One 16-bit, 4Gb DDR3L +- One 32Gb e.MMC +- 1Gb Octal SPI Flash +- 2 EEPROMs w/ EUI-48TM MAC ID +- 1 SD card slot +- 3 HS USB ports +- 2 CAN interfaces +- 2 Ethernet ports (Gigabit and 10/100) +- Pad for ATWILC3000 Wi-Fi/BT module (unpopulated) +- S/PDIF RX and TX ports +- 4 digital microphone ports +- 40-pin Raspberry Pi expansion header +- 2 mikroBUS™ connectors +- USB powered + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The `SAMA7G54-EK User Guide`_ has detailed information about board connections. + +References +********** + +SAMA7G54 Product Page: + https://www.microchip.com/en-us/product/sama7g54 + +SAMA7G54 Evaluation Kit Page: + https://www.microchip.com/en-us/development-tool/EV21H18A + +.. _SAMA7G54-EK User Guide: + https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ProductDocuments/UserGuides/SAMA7G54-EK-User%27s-Guide-DS50003273.pdf diff --git a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts new file mode 100644 index 00000000000..82648923842 --- /dev/null +++ b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include +#include +#include + +/ { + model = "SAMA7G54-EK board"; + compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; + + chosen { + zephyr,sram = &ddram; + zephyr,console = &usart3; + zephyr,shell-uart = &usart3; + }; + + clocks { + main_xtal { + clock-frequency = ; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + }; + + ddram: ddram@60000000 { + compatible = "ddram"; + reg = <0x60000000 DT_SIZE_M(512)>; + }; +}; + +&flx3 { + mchp,flexcom-mode = ; + status = "okay"; + + usart3: serial@200 { + current-speed = <115200>; + pinctrl-0 = <&pinctrl_flx3_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&pinctrl { + pinctrl_flx3_default: flx3_default { + group1 { + pinmux = , + ; + bias-pull-up; + }; + }; +}; + +&pit64b0 { + clock-frequency = ; +}; diff --git a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml new file mode 100644 index 00000000000..f13a42f23ba --- /dev/null +++ b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml @@ -0,0 +1,14 @@ +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# SPDX-License-Identifier: Apache-2.0 + +identifier: sama7g54_ek +name: SAMA7G54-EK +type: mcu +arch: arm +toolchain: + - zephyr +ram: 128 +supported: + - shell + - uart +vendor: microchip diff --git a/boards/microchip/sam/sama7g54_ek/sama7g54_ek_defconfig b/boards/microchip/sam/sama7g54_ek/sama7g54_ek_defconfig new file mode 100644 index 00000000000..10b06d0f7f4 --- /dev/null +++ b/boards/microchip/sam/sama7g54_ek/sama7g54_ek_defconfig @@ -0,0 +1,9 @@ +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/mikroe/quail/Kconfig.defconfig b/boards/mikroe/quail/Kconfig.defconfig new file mode 100644 index 00000000000..ea45af09da9 --- /dev/null +++ b/boards/mikroe/quail/Kconfig.defconfig @@ -0,0 +1,10 @@ +# MikroE Quail board configuration + +# Copyright (c) 2025 ThoseBoards +# SPDX-License-Identifier: Apache-2.0 + +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" + +config SPI_STM32_INTERRUPT + default y + depends on SPI diff --git a/boards/mikroe/quail/Kconfig.mikroe_quail b/boards/mikroe/quail/Kconfig.mikroe_quail new file mode 100644 index 00000000000..f711abe5738 --- /dev/null +++ b/boards/mikroe/quail/Kconfig.mikroe_quail @@ -0,0 +1,5 @@ +# Copyright (c) 2025 ThoseBoards +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIKROE_QUAIL + select SOC_STM32F427XX diff --git a/boards/mikroe/quail/board.cmake b/boards/mikroe/quail/board.cmake new file mode 100644 index 00000000000..7718f87e84a --- /dev/null +++ b/boards/mikroe/quail/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32F427VIT6" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/mikroe/quail/board.yml b/boards/mikroe/quail/board.yml new file mode 100644 index 00000000000..b363f83059c --- /dev/null +++ b/boards/mikroe/quail/board.yml @@ -0,0 +1,6 @@ +board: + name: mikroe_quail + full_name: MikroE Quail + vendor: mikroe + socs: + - name: stm32f427xx diff --git a/boards/mikroe/quail/doc/img/mikroe_quail.webp b/boards/mikroe/quail/doc/img/mikroe_quail.webp new file mode 100644 index 00000000000..801b29d3a48 Binary files /dev/null and b/boards/mikroe/quail/doc/img/mikroe_quail.webp differ diff --git a/boards/mikroe/quail/doc/mikroe_quail.rst b/boards/mikroe/quail/doc/mikroe_quail.rst new file mode 100644 index 00000000000..5e2f7d82947 --- /dev/null +++ b/boards/mikroe/quail/doc/mikroe_quail.rst @@ -0,0 +1,99 @@ +.. zephyr:board:: mikroe_quail + +Overview +******** +MikroE Quail for STM32 is a development board containing an `STM32F427`_ +microcontroller. It is equipped with four mikroBUS sockets. +The edges of the board are lined with screw terminals and USB ports for +additional connectivity. + +Hardware +******** +The Quail board contains the following connections: + + - Four mikroBUS connectors + - 32 screw terminals + - two USB ports, one for programming and one for external storage + +Furthermore the board contains three LEDs that are connected +to the microcontroller. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The four mikroBUS interfaces are aliased in the device tree so that their +peripherals can be accessed using ``mikrobus_N_INTERFACE`` so e.g. the SPI on +bus 2 can be found by the alias ``mikrobus_2_spi``. The numbering corresponds +with the marking on the board. + +For connections on the edge connectors, please refer to `Quail for STM32 User Manual`_. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``mikroe_quail`` board can be built and flashed in the usual way +(see :ref:`build_an_application` and :ref:`application_run` for more details). + + +Flashing +======== +The board ships with a locked flash, and will fail with the message: + +.. code-block:: console + + Error: stm32x device protected + +Unlocking with OpenOCD makes it possible to flash. + +.. code-block:: console + + $ openocd -f /usr/share/openocd/scripts/interface/stlink-v2.cfg \ + -f /usr/share/openocd/scripts/target/stm32f4x.cfg -c init\ + -c "reset halt" -c "stm32f4x unlock 0" -c "reset run" -c shutdown + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mikroe_quail + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! mikroe_quail + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mikroe_quail + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Quail website: + https://www.mikroe.com/quail +.. _Quail for STM32 User Manual: + https://download.mikroe.com/documents/starter-boards/other/quail/quail-board-manual-v100.pdf +.. _STM32F427VIT6 Website: + https://www.st.com/en/microcontrollers-microprocessors/stm32f427vi.html +.. _STM32F427: + https://www.st.com/resource/en/datasheet/stm32f427vg.pdf diff --git a/boards/mikroe/quail/mikroe_quail.dts b/boards/mikroe/quail/mikroe_quail.dts new file mode 100644 index 00000000000..c314f658c38 --- /dev/null +++ b/boards/mikroe/quail/mikroe_quail.dts @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2025 ThoseBoards + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "MikroE Quail for STM32"; + compatible = "mikroe,stm32-e427", "st,stm32f427"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &flash1; + zephyr,ccm = &ccm0; + }; + + leds { + compatible = "gpio-leds"; + + ld1: led_1 { + gpios = <&gpioe 15 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + + ld2: led_2 { + gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + + ld3: led_3 { + gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>; + label = "User LD3"; + }; + }; + + zephyr,user { + io-channels = <&adc1 0>, <&adc1 1>, <&adc2 0>, <&adc2 1>; + }; + + mikrobus_1_header: mikrobus-connector-1 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 6 0>, /* AN */ + <1 0 &gpioa 2 0>, /* RST */ + <2 0 &gpioa 3 0>, /* CS */ + <3 0 &gpiob 3 0>, /* SCK */ + <4 0 &gpiob 4 0>, /* MISO */ + <5 0 &gpiob 5 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpioe 9 0>, /* PWM */ + <7 0 &gpioa 1 0>, /* INT */ + <8 0 &gpiod 9 0>, /* RX */ + <9 0 &gpiod 8 0>, /* TX */ + <10 0 &gpiob 6 0>, /* SCL */ + <11 0 &gpiob 7 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + mikrobus_2_header: mikrobus-connector-2 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 4 0>, /* AN */ + <1 0 &gpioe 1 0>, /* RST */ + <2 0 &gpioe 0 0>, /* CS */ + <3 0 &gpiob 3 0>, /* SCK */ + <4 0 &gpiob 4 0>, /* MISO */ + <5 0 &gpiob 5 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpiod 15 0>, /* PWM */ + <7 0 &gpiob 9 0>, /* INT */ + <8 0 &gpiod 6 0>, /* RX */ + <9 0 &gpiod 5 0>, /* TX */ + <10 0 &gpiob 6 0>, /* SCL */ + <11 0 &gpiob 7 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + mikrobus_3_header: mikrobus-connector-3 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 7 0>, /* AN */ + <1 0 &gpiod 8 0>, /* RST */ + <2 0 &gpiod 11 0>, /* CS */ + <3 0 &gpioc 10 0>, /* SCK */ + <4 0 &gpioc 11 0>, /* MISO */ + <5 0 &gpioc 12 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpiod 13 0>, /* PWM */ + <7 0 &gpioc 8 0>, /* INT */ + <8 0 &gpioc 7 0>, /* RX */ + <9 0 &gpioc 6 0>, /* TX */ + <10 0 &gpiob 6 0>, /* SCL */ + <11 0 &gpiob 7 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + mikrobus_4_header: mikrobus-connector-4 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 5 0>, /* AN */ + <1 0 &gpiod 0 0>, /* RST */ + <2 0 &gpiod 1 0>, /* CS */ + <3 0 &gpioc 10 0>, /* SCK */ + <4 0 &gpioc 11 0>, /* MISO */ + <5 0 &gpioc 12 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpiod 14 0>, /* PWM */ + <7 0 &gpioa 14 0>, /* INT */ + <8 0 &gpioa 10 0>, /* RX */ + <9 0 &gpioa 9 0>, /* TX */ + <10 0 &gpiob 6 0>, /* SCL */ + <11 0 &gpiob 7 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + edge_header: connector { + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 5 0>, /* ,PC5 */ + <1 0 &gpiob 0 0>, /* ,PB0 */ + <2 0 &gpioe 7 0>, /* ,PE7 */ + <3 0 &gpioe 8 0>, /* ,PE8 */ + <4 0 &gpioe 11 0>, /* ,PE11 */ + <5 0 &gpioc 4 0>, /* ,PC4 */ + <6 0 &gpioe 13 0>, /* ,PE13 */ + <7 0 &gpioe 14 0>, /* ,PE14 */ + <8 0 &gpiob 10 0>, /* ,PB10 */ + <9 0 &gpiob 11 0>, /* ,PB11 */ + <10 0 &gpiob 12 0>, /* ,PB12 */ + <11 0 &gpiob 13 0>, /* ,PB13 */ + <12 0 &gpiob 6 0>, /* ,PB6 # I2C1 */ + <13 0 &gpiob 7 0>, /* ,PB7 # I2C1 */ + <14 0 &gpioc 10 0>, /* ,PC10 # SPI3 */ + <15 0 &gpioc 11 0>, /* ,PC11 # SPI3 */ + <16 0 &gpioc 12 0>, /* ,PC12 # SPI3 */ + <17 0 &gpiod 10 0>, /* ,PD10 # SPI3 */ + <18 0 &gpioa 15 0>, /* ,PA15 */ + <19 0 &gpioc 13 0>, /* ,PC13 */ + <20 0 &gpioe 6 0>, /* ,PE6 */ + <21 0 &gpioe 5 0>, /* ,PE5 */ + <22 0 &gpiod 2 0>, /* ,PD2 */ + <23 0 &gpiod 3 0>, /* ,PD3 */ + <24 0 &gpiod 4 0>, /* ,PD4 */ + <25 0 &gpiod 7 0>, /* ,PD7 */ + <26 0 &gpioe 2 0>, /* ,PE2 */ + <27 0 &gpioe 3 0>, /* ,PE3 */ + <28 0 &gpioe 4 0>; /* ,PE4 */ + }; + + aliases { + led0 = &ld1; + led1 = &ld2; + led2 = &ld3; + volt-sensor0 = &vref; + volt-sensor1 = &vbat; + }; + + skd1: socket_1_adc { + status = "okay"; + io-channels = <&adc2 0>; + }; + + skd2: socket_2_adc { + status = "okay"; + io-channels = <&adc1 0>; + }; + + skd3: socket_3_adc { + status = "okay"; + io-channels = <&adc2 1>; + }; + + skd4: socket_4_adc { + status = "okay"; + io-channels = <&adc1 1>; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hsi { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <8>; + mul-n = <96>; + div-p = <2>; + div-q = <4>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <4>; + apb2-prescaler = <2>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart3 { + pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart6 { + pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; + +zephyr_udc0: &usbotg_fs { + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> + +&spi1 { + pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pb4 &spi1_mosi_pb5>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>, <&gpioe 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi3 { + status = "okay"; + pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>; + pinctrl-names = "default"; + + cs-gpios = + <&gpiod 11 GPIO_ACTIVE_LOW>, // CS0 + <&gpiod 1 GPIO_ACTIVE_LOW>, // CS1 + <&gpioa 13 GPIO_ACTIVE_LOW>; // CS2 +}; + +/* Flash chip 1 (extra flash connected to CS2) */ +&spi3 { + flash1: flash@2 { + compatible = "jedec,spi-nor"; // Typical flash chip compatibility string + reg = <2>; // The CS0 pin on the SPI bus + // S25FL164K flash's actual JEDEC: Device ID = 16h, Device Type = 40h, + // Capacity = 17h + //jedec-id = [16 40 17]; + jedec-id = [01 60 17]; + spi-max-frequency = <50000000>; // Max frequency for the flash chip (e.g., 50 MHz) + size = <0x800000>; // Flash memory size (16MB example) + page-size = <256>; // Flash page size (usually 256 or 512 bytes) + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc1 { + status ="okay"; + pinctrl-0 = <&adc1_in4_pa4 &adc1_in5_pa5>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <2>; +}; + +&adc2 { + status ="okay"; + pinctrl-0 = <&adc2_in6_pa6 &adc2_in7_pa7>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <2>; +}; + +&vref { + status = "okay"; +}; + +&vbat { + status = "okay"; +}; + +mikrobus_1_adc: &skd1 {}; + +mikrobus_1_i2c: &i2c1 {}; + +mikrobus_1_spi: &spi1 {}; + +mikrobus_1_uart: &usart3 {}; + +mikrobus_2_adc: &skd2 {}; + +mikrobus_2_i2c: &i2c1 {}; + +mikrobus_2_spi: &spi1 {}; + +mikrobus_2_uart: &usart2 {}; + +mikrobus_3_adc: &skd3 {}; + +mikrobus_3_i2c: &i2c1 {}; + +mikrobus_3_spi: &spi3 {}; + +mikrobus_3_uart: &usart6 {}; + +mikrobus_4_adc: &skd4 {}; + +mikrobus_4_i2c: &i2c1 {}; + +mikrobus_4_spi: &spi3 {}; + +mikrobus_4_uart: &usart1 {}; + +mikrobus_adc: &skd1 {}; + +mikrobus_i2c: &i2c1 {}; + +mikrobus_spi: &spi1 {}; + +mikrobus_uart: &usart3 {}; + +mikrobus_header: &mikrobus_1_header {}; diff --git a/boards/mikroe/quail/mikroe_quail.yaml b/boards/mikroe/quail/mikroe_quail.yaml new file mode 100644 index 00000000000..f114861f6bc --- /dev/null +++ b/boards/mikroe/quail/mikroe_quail.yaml @@ -0,0 +1,17 @@ +identifier: mikroe_quail +name: MikroE Quail for STM32 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 256 +flash: 2048 +supported: + - spi + - i2c + - uart + - adc + - gpio + - flash +vendor: mikroe diff --git a/boards/mikroe/quail/mikroe_quail_defconfig b/boards/mikroe/quail/mikroe_quail_defconfig new file mode 100644 index 00000000000..e5819cf7950 --- /dev/null +++ b/boards/mikroe/quail/mikroe_quail_defconfig @@ -0,0 +1,11 @@ +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/native/common/extra_args/extra_args.c b/boards/native/common/extra_args/extra_args.c index b2e57dc674e..aa71b95552c 100644 --- a/boards/native/common/extra_args/extra_args.c +++ b/boards/native/common/extra_args/extra_args.c @@ -14,9 +14,7 @@ static void remove_one_char(char *str) { - int i; - - for (i = 0; str[i] != 0; i++) { + for (int i = 0; str[i] != 0; i++) { str[i] = str[i+1]; } } diff --git a/boards/native/native_sim/CMakeLists.txt b/boards/native/native_sim/CMakeLists.txt index 2bb964f49e8..014b0bb049c 100644 --- a/boards/native/native_sim/CMakeLists.txt +++ b/boards/native/native_sim/CMakeLists.txt @@ -13,6 +13,15 @@ zephyr_library_sources( posix_arch_if.c ) +if(CONFIG_NATIVE_SIM_REBOOT) + zephyr_library_sources(reboot.c) + if(CONFIG_NATIVE_LIBRARY) + target_sources(native_simulator INTERFACE reboot_bottom.c) + else() + zephyr_library_sources(reboot_bottom.c) + endif() +endif() + zephyr_include_directories( ${NSI_DIR}/common/src/include ${NSI_DIR}/native/src/include diff --git a/boards/native/native_sim/Kconfig b/boards/native/native_sim/Kconfig index 4ecdbf702f5..b04c6374691 100644 --- a/boards/native/native_sim/Kconfig +++ b/boards/native/native_sim/Kconfig @@ -1,4 +1,5 @@ # Copyright (c) 2023 Nordic Semiconductor ASA +# Copyright (c) 2025 GARDENA GmbH # SPDX-License-Identifier: Apache-2.0 config BOARD_NATIVE_SIM @@ -50,6 +51,12 @@ config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME Transitional option which allows applications which targeted native_posix to set the correct native_sim option (CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME) +config NATIVE_SIM_REBOOT + bool "Reboot support" + depends on REBOOT + help + Enables the reboot implementation for the native sim executable. + source "boards/native/common/sdl/Kconfig" source "boards/native/common/extra_args/Kconfig" diff --git a/boards/native/native_sim/reboot.c b/boards/native/native_sim/reboot.c new file mode 100644 index 00000000000..fb864cb2022 --- /dev/null +++ b/boards/native/native_sim/reboot.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 GARDENA GmbH + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "reboot_bottom.h" +#include "posix_board_if.h" + +void sys_arch_reboot(int type) +{ + (void)type; + native_set_reboot_on_exit(); + posix_exit(0); +} diff --git a/boards/native/native_sim/reboot_bottom.c b/boards/native/native_sim/reboot_bottom.c new file mode 100644 index 00000000000..21ec7a2634f --- /dev/null +++ b/boards/native/native_sim/reboot_bottom.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2025 GARDENA GmbH + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static const char module[] = "native_sim_reboot"; + +static long close_open_fds(void) +{ + /* close all open file descriptors except 0-2 */ + errno = 0; + + long max_fd = sysconf(_SC_OPEN_MAX); + + if (max_fd < 0) { + if (errno != 0) { + nsi_print_error_and_exit("%s: %s\n", module, strerror(errno)); + } else { + nsi_print_warning("%s: Cannot determine maximum number of file descriptors" + "\n", + module); + } + return max_fd; + } + for (int fd = 3; fd < max_fd; fd++) { + (void)close(fd); + } + return 0; +} + +static bool reboot_on_exit; + +void native_set_reboot_on_exit(void) +{ + reboot_on_exit = true; +} + +void maybe_reboot(void) +{ + char **argv; + int argc; + + if (!reboot_on_exit) { + return; + } + + reboot_on_exit = false; /* If we reenter it means we failed to reboot */ + + nsi_get_cmd_line_args(&argc, &argv); + + if (close_open_fds() < 0) { + nsi_exit(1); + } + + nsi_print_warning("%s: Restarting process.\n", module); + + (void)execv("/proc/self/exe", argv); + + nsi_print_error_and_exit("%s: Failed to restart process, exiting (%s)\n", module, + strerror(errno)); +} + +NSI_TASK(maybe_reboot, ON_EXIT_POST, 999); diff --git a/boards/native/native_sim/reboot_bottom.h b/boards/native/native_sim/reboot_bottom.h new file mode 100644 index 00000000000..3e4eef6d420 --- /dev/null +++ b/boards/native/native_sim/reboot_bottom.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 GARDENA GmbH + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef BOARDS_NATIVE_NATIVE_SIM_REBOOT_BOTTOM_H +#define BOARDS_NATIVE_NATIVE_SIM_REBOOT_BOTTOM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void native_set_reboot_on_exit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARDS_NATIVE_NATIVE_SIM_REBOOT_BOTTOM_H */ diff --git a/boards/native/nrf_bsim/common/bsim_control.h b/boards/native/nrf_bsim/common/bsim_control.h new file mode 100644 index 00000000000..ee32ea80e9f --- /dev/null +++ b/boards/native/nrf_bsim/common/bsim_control.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef BOARDS_NATIVE_BSIM_COMMON_BSIM_CONTROL_H +#define BOARDS_NATIVE_BSIM_COMMON_BSIM_CONTROL_H + +#include +#include "bsim_args_runner.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void bsim_set_terminate_on_exit(bool terminate); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARDS_NATIVE_BSIM_COMMON_BSIM_CONTROL_H */ diff --git a/boards/native/nrf_bsim/common/bstests.h b/boards/native/nrf_bsim/common/bstests.h index ee22240a380..7c892d0ead2 100644 --- a/boards/native/nrf_bsim/common/bstests.h +++ b/boards/native/nrf_bsim/common/bstests.h @@ -92,7 +92,7 @@ struct bst_test_instance { {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL} struct bst_test_list { - struct bst_test_instance *test_instance; + const struct bst_test_instance *test_instance; struct bst_test_list *next; }; diff --git a/boards/native/nrf_bsim/common/bstests_entry.c b/boards/native/nrf_bsim/common/bstests_entry.c index 7b22a50ebf5..6822afb0a8c 100644 --- a/boards/native/nrf_bsim/common/bstests_entry.c +++ b/boards/native/nrf_bsim/common/bstests_entry.c @@ -21,7 +21,7 @@ */ enum bst_result_t bst_result; -static struct bst_test_instance *current_test; +static const struct bst_test_instance *current_test; static struct bst_test_list *test_list_top; __attribute__((weak)) bst_test_install_t test_installers[] = { NULL }; @@ -42,8 +42,7 @@ struct bst_test_list *bst_add_tests(struct bst_test_list *tests, if (test_def[idx].test_id != NULL) { head = bs_malloc(sizeof(struct bst_test_list)); head->next = NULL; - head->test_instance = (struct bst_test_instance *) - &test_def[idx++]; + head->test_instance = &test_def[idx++]; tail = head; } } @@ -51,16 +50,14 @@ struct bst_test_list *bst_add_tests(struct bst_test_list *tests, while (test_def[idx].test_id != NULL) { tail->next = bs_malloc(sizeof(struct bst_test_list)); tail = tail->next; - tail->test_instance = (struct bst_test_instance *) - &test_def[idx++]; + tail->test_instance = &test_def[idx++]; tail->next = NULL; } return head; } -static struct bst_test_instance *bst_test_find(struct bst_test_list *tests, - char *test_id) +static const struct bst_test_instance *bst_test_find(struct bst_test_list *tests, char *test_id) { struct bst_test_list *top = tests; diff --git a/boards/native/nrf_bsim/common/runner_hooks.c b/boards/native/nrf_bsim/common/runner_hooks.c index e63567634b4..01ed27703a5 100644 --- a/boards/native/nrf_bsim/common/runner_hooks.c +++ b/boards/native/nrf_bsim/common/runner_hooks.c @@ -16,6 +16,20 @@ #include "NRF_HWLowL.h" #include "bsim_args_runner.h" +static bool bsim_disconnect_on_exit; + +/* + * Control what will happen to the overall simulation when this executable exists. + * If is true (default behavior) the Phy will be told to end the simulation + * when this executable exits. + * If is false, this device will just disconnect, but let the simulation continue + * otherwise. + */ +void bsim_set_terminate_on_exit(bool terminate) +{ + bsim_disconnect_on_exit = !terminate; +} + static uint8_t main_clean_up_trace_wrap(void) { return nsi_exit_inner(0); @@ -40,9 +54,33 @@ NSI_TASK(open_dumps, PRE_BOOT_2, 500); static void exit_hooks(void) { - hwll_terminate_simulation(); + if (bsim_disconnect_on_exit) { + hwll_disconnect_phy(); + } else { + hwll_terminate_simulation(); + } bs_dump_files_close_all(); bs_clean_back_channels(); } NSI_TASK(exit_hooks, ON_EXIT_PRE, 500); + +static void exit_control_args(void) +{ + static bs_args_struct_t args_struct_toadd[] = { + { + .option = "disconnect_on_exit", + .type = 'b', + .name = "term", + .dest = (void *)&bsim_disconnect_on_exit, + .descript = "If set to 1, on exit only disconnect this device from the Phy and let " + "the simulation continue. Otherwise (default) on exit terminate the " + "whole simulation." + }, + ARG_TABLE_ENDMARKER + }; + + bs_add_extra_dynargs(args_struct_toadd); +} + +NSI_TASK(exit_control_args, PRE_BOOT_1, 10); diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts index bdcd47f9440..00dc61bc024 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts @@ -132,4 +132,4 @@ /* We re-use the IPC shared buffer definition from the real HW. But note the start address of the * buffer won't be used. */ - #include + #include diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts index 0f098a7dd29..0214d4aa9a6 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts @@ -92,4 +92,4 @@ /* We re-use the IPC shared buffer definition from the real HW. But note the start address of the * buffer won't be used. */ - #include + #include diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi index 73083fd5d95..d1da980ec5c 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -31,6 +32,7 @@ psels = ; bias-pull-up; }; + group2 { psels = ; }; @@ -155,5 +157,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts index f4dc3058b2b..0874ef8fdf2 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts @@ -28,18 +28,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -48,6 +52,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -55,21 +60,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 25 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 3"; @@ -242,10 +251,10 @@ arduino_i2c: &i2c0 { fem_spi: &spi3 { status = "okay"; cs-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&spi3_default>; pinctrl-1 = <&spi3_sleep>; pinctrl-names = "default", "sleep"; + nrf_radio_fem_spi: nrf21540_fem_spi@0 { compatible = "nordic,nrf21540-fem-spi"; status = "okay"; @@ -263,7 +272,6 @@ fem_spi: &spi3 { }; &flash0 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -273,10 +281,12 @@ fem_spi: &spi3 { label = "mcuboot"; reg = <0x00000000 0x0000C000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0x00076000>; }; + slot1_partition: partition@82000 { label = "image-1"; reg = <0x00082000 0x00076000>; diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig index 8daa29dc473..14367293292 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig @@ -6,9 +6,6 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi b/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi index 4b82a01feab..c806e25f8ce 100644 --- a/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi @@ -86,5 +86,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts b/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts index 15e74d15f40..fed633e30ee 100644 --- a/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts @@ -26,18 +26,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -46,6 +50,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -53,21 +58,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 20 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 3"; @@ -151,7 +160,6 @@ }; &flash0 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -161,14 +169,17 @@ label = "mcuboot"; reg = <0x00000000 0x8000>; }; + slot0_partition: partition@8000 { label = "image-0"; reg = <0x00008000 0x1b000>; }; + slot1_partition: partition@23000 { label = "image-1"; reg = <0x00023000 0x1b000>; }; + storage_partition: partition@3e000 { label = "storage"; reg = <0x0003e000 0x00002000>; diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi index 410d78c37dc..8142a7e74b3 100644 --- a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi +++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi @@ -22,5 +22,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts index 746b2ca767c..48f1d498723 100644 --- a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts +++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts @@ -25,14 +25,17 @@ leds { compatible = "gpio-leds"; + led0_red: led_0 { gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; label = "Red LED 0"; }; + led0_green: led_1 { gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led0_blue: led_2 { gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; label = "Blue LED 0"; @@ -41,6 +44,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -83,7 +87,6 @@ }; &flash0 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -93,14 +96,17 @@ label = "mcuboot"; reg = <0x00000000 0x8000>; }; + slot0_partition: partition@8000 { label = "image-0"; reg = <0x00008000 0x1b000>; }; + slot1_partition: partition@23000 { label = "image-1"; reg = <0x00023000 0x1b000>; }; + storage_partition: partition@3e000 { label = "storage"; reg = <0x0003e000 0x00002000>; diff --git a/boards/nordic/nrf52833dk/doc/img/nrf52833dk.webp b/boards/nordic/nrf52833dk/doc/img/nrf52833dk.webp new file mode 100644 index 00000000000..918d197842f Binary files /dev/null and b/boards/nordic/nrf52833dk/doc/img/nrf52833dk.webp differ diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi index 89e33721507..0a2dd6da3ef 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -57,5 +58,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts index 0f9526fb21f..ddd49d23246 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts @@ -26,18 +26,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -46,6 +50,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -53,21 +58,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 25 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 3"; @@ -152,7 +161,6 @@ }; &flash0 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -162,14 +170,17 @@ label = "mcuboot"; reg = <0x00000000 0xC000>; }; + slot0_partition: partition@C000 { label = "image-0"; reg = <0x0000C000 0x17000>; }; + slot1_partition: partition@23000 { label = "image-1"; reg = <0x00023000 0x17000>; }; + storage_partition: partition@3a000 { label = "storage"; reg = <0x0003a000 0x00006000>; diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig index 8daa29dc473..14367293292 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig @@ -6,9 +6,6 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi index 420027e7073..9f6c5a920eb 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -31,6 +32,7 @@ psels = ; bias-pull-up; }; + group2 { psels = ; }; @@ -138,5 +140,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts index 386fac62e1d..f32ad7a220a 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts @@ -27,18 +27,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -47,6 +51,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -54,21 +59,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 25 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 3"; @@ -221,7 +230,6 @@ arduino_spi: &spi3 { }; &flash0 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -231,14 +239,17 @@ arduino_spi: &spi3 { label = "mcuboot"; reg = <0x00000000 0xC000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0x37000>; }; + slot1_partition: partition@43000 { label = "image-1"; reg = <0x00043000 0x37000>; }; + storage_partition: partition@7a000 { label = "storage"; reg = <0x0007A000 0x00006000>; diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig index 8daa29dc473..14367293292 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig @@ -6,9 +6,6 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi index 2b0ab3e75d3..c3706043f4f 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -88,5 +89,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts index b6631dea9cf..3a2b5ed87bc 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts @@ -26,18 +26,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -46,6 +50,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -53,21 +58,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 25 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 3"; @@ -155,7 +164,6 @@ }; &flash0 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -165,14 +173,17 @@ label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0xe000>; }; + slot1_partition: partition@1a000 { label = "image-1"; reg = <0x0001a000 0xe000>; }; + storage_partition: partition@28000 { label = "storage"; reg = <0x00028000 0x00008000>; diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi index 779d0d518a8..5b868c84f18 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -31,6 +32,7 @@ psels = ; bias-pull-up; }; + group2 { psels = ; }; @@ -160,6 +162,7 @@ ; low-power-enable; }; + group2 { psels = ; low-power-enable; @@ -183,5 +186,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts index f19cd48bb40..cda7bb6164d 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts @@ -26,18 +26,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -46,6 +50,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -53,21 +58,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 25 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 3"; @@ -243,6 +252,7 @@ arduino_i2c: &i2c0 { pinctrl-0 = <&qspi_default>; pinctrl-1 = <&qspi_sleep>; pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { compatible = "nordic,qspi-nor"; reg = <0>; diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig index 8daa29dc473..14367293292 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig @@ -6,9 +6,6 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf52840dongle/fstab-debugger.dtsi b/boards/nordic/nrf52840dongle/fstab-debugger.dtsi index 9fbbe7cd91b..dd3d12403c6 100644 --- a/boards/nordic/nrf52840dongle/fstab-debugger.dtsi +++ b/boards/nordic/nrf52840dongle/fstab-debugger.dtsi @@ -24,10 +24,12 @@ label = "image-0"; reg = <0x00012000 0x00075000>; }; + slot1_partition: partition@87000 { label = "image-1"; reg = <0x00087000 0x00075000>; }; + storage_partition: partition@fc000 { label = "storage"; reg = <0x000fc000 0x00004000>; diff --git a/boards/nordic/nrf52840dongle/fstab-stock.dtsi b/boards/nordic/nrf52840dongle/fstab-stock.dtsi index 26863679f60..b487f02c153 100644 --- a/boards/nordic/nrf52840dongle/fstab-stock.dtsi +++ b/boards/nordic/nrf52840dongle/fstab-stock.dtsi @@ -26,10 +26,12 @@ label = "image-0"; reg = <0x00010000 0x00066000>; }; + slot1_partition: partition@76000 { label = "image-1"; reg = <0x00076000 0x00066000>; }; + storage_partition: partition@dc000 { label = "storage"; reg = <0x000dc000 0x00004000>; diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi index ad2ce3463b4..cf2b8523b8e 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -107,5 +108,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts index 1f1de703ade..890570b7eee 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts @@ -23,18 +23,22 @@ leds { compatible = "gpio-leds"; + led0_green: led_0 { gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1_red: led_1 { gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; label = "Red LED 1"; }; + led1_green: led_2 { gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led1_blue: led_3 { gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; label = "Blue LED 1"; @@ -43,12 +47,15 @@ pwmleds { compatible = "pwm-leds"; + red_pwm_led: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; + green_pwm_led: pwm_led_1 { pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; + blue_pwm_led: pwm_led_2 { pwms = <&pwm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -56,6 +63,7 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio1 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 0"; @@ -71,9 +79,9 @@ led2 = &led1_green; led3 = &led1_blue; led0-green = &led0_green; - led1-red = &led1_red; + led1-red = &led1_red; led1-green = &led1_green; - led1-blue = &led1_blue; + led1-blue = &led1_blue; pwm-led0 = &red_pwm_led; pwm-led1 = &green_pwm_led; pwm-led2 = &blue_pwm_led; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi index 4ec1fa80a8c..00d60d2cbec 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi @@ -54,5 +54,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts index fd84761fe1b..037c0c46e1c 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts @@ -26,18 +26,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -46,21 +50,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { label = "Push button switch 0"; gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; zephyr,code = ; }; + button1: button_1 { label = "Push button switch 1"; gpios = <&gpio0 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; zephyr,code = ; }; + button2: button_2 { label = "Push button switch 2"; gpios = <&gpio0 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; zephyr,code = ; }; + button3: button_3 { label = "Push button switch 3"; gpios = <&gpio0 16 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; @@ -140,14 +148,17 @@ label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0xe000>; }; + slot1_partition: partition@1a000 { label = "image-1"; reg = <0x0001a000 0xe000>; }; + storage_partition: partition@28000 { label = "storage"; reg = <0x00028000 0x00008000>; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi index 78f1f279ede..bec21acc20f 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi @@ -54,5 +54,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts index 2bfcad26247..1e9901d60bb 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts @@ -28,18 +28,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -48,21 +52,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { label = "Push button switch 0"; gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; zephyr,code = ; }; + button1: button_1 { label = "Push button switch 1"; gpios = <&gpio0 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; zephyr,code = ; }; + button2: button_2 { label = "Push button switch 2"; gpios = <&gpio0 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; zephyr,code = ; }; + button3: button_3 { label = "Push button switch 3"; gpios = <&gpio0 16 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; @@ -133,7 +141,6 @@ }; &flash0 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -143,14 +150,17 @@ label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0xe000>; }; + slot1_partition: partition@1a000 { label = "image-1"; reg = <0x0001a000 0xe000>; }; + storage_partition: partition@28000 { label = "storage"; reg = <0x00028000 0x00008000>; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi index c859969e551..45b5ccb4e04 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi @@ -117,5 +117,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts index d132db9f423..7d1a09eb357 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts @@ -27,18 +27,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -47,6 +51,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -54,21 +59,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 16 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button switch 3"; @@ -218,7 +227,6 @@ arduino_spi: &spi2 { }; &flash0 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -228,14 +236,17 @@ arduino_spi: &spi2 { label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0x37000>; }; + slot1_partition: partition@43000 { label = "image-1"; reg = <0x00043000 0x37000>; }; + storage_partition: partition@7a000 { label = "storage"; reg = <0x0007a000 0x00006000>; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig b/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig index 8daa29dc473..14367293292 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig @@ -6,9 +6,6 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - # enable GPIO CONFIG_GPIO=y diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig b/boards/nordic/nrf5340_audio_dk/Kconfig deleted file mode 100644 index d872efa4d2e..00000000000 --- a/boards/nordic/nrf5340_audio_dk/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -# nRF5340 Audio DK board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUNET_BOARD - string - default "nrf5340_audio_dk/nrf5340/cpunet" - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "nrf5340_audio_dk/nrf5340/cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi index 5247c04429b..6f835be43c6 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi @@ -10,6 +10,7 @@ psels = ; nordic,drive-mode = ; }; + group2 { psels = , , @@ -34,6 +35,7 @@ psels = , ; }; + group2 { psels = , ; @@ -56,6 +58,7 @@ psels = , ; }; + group2 { psels = , ; @@ -114,6 +117,7 @@ */ nordic,drive-mode = ; }; + group2 { psels = ; }; diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi index 78a5020f31e..5c2b1545e26 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi @@ -20,6 +20,7 @@ gpio_fwd: nrf-gpio-forwarder { compatible = "nordic,nrf-gpio-forwarder"; status = "okay"; + uart { gpios = <&gpio1 9 0>, <&gpio1 8 0>, <&gpio1 11 0>, <&gpio1 10 0>; }; @@ -51,12 +52,15 @@ pwmleds { compatible = "pwm-leds"; + rgb1_red_pwm_led: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; + rgb1_green_pwm_led: pwm_led_1 { pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; + rgb1_blue_pwm_led: pwm_led_2 { pwms = <&pwm0 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; @@ -212,17 +216,18 @@ arduino_spi: &spi4 { pinctrl-0 = <&spi4_default>; pinctrl-1 = <&spi4_sleep>; pinctrl-names = "default", "sleep"; + sdhc0: sdhc@1 { compatible = "zephyr,sdhc-spi-slot"; reg = <1>; status = "okay"; + spi-max-frequency = <8000000>; + sdmmc { compatible = "zephyr,sdmmc-disk"; disk-name = "SD"; status = "okay"; }; - - spi-max-frequency = <8000000>; }; cs47l63: cs47l63@2 { @@ -259,5 +264,5 @@ zephyr_udc0: &usbd { }; /* Include default memory partition configuration file */ -#include +#include #include "nrf5340_audio_dk_nrf5340_shared.dtsi" diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi index 6804c040d12..86978843757 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -42,5 +43,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts index c50a51d3bc5..15d12185549 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts @@ -58,7 +58,6 @@ arduino_spi: &spi0 { }; &flash1 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -68,14 +67,17 @@ arduino_spi: &spi0 { label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0x12000>; }; + slot1_partition: partition@1e000 { label = "image-1"; reg = <0x0001E000 0x12000>; }; + storage_partition: partition@3a000 { label = "storage"; reg = <0x0003a000 0x6000>; @@ -84,5 +86,5 @@ arduino_spi: &spi0 { }; /* Include default shared RAM configuration file */ -#include +#include #include "nrf5340_audio_dk_nrf5340_shared.dtsi" diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi index 5d13b9288a6..aff29f4e9d3 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi @@ -1,40 +1,49 @@ #include / { - leds: leds { + leds: leds { compatible = "gpio-leds"; + rgb1_red: led_0 { gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; label = "0 LED_RGB_RED"; }; + rgb1_green: led_1 { gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; label = "0 LED_RGB_GREEN"; }; + rgb1_blue: led_2 { gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; label = "0 LED_RGB_BLUE"; }; + rgb2_red: led_3 { gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; label = "1 LED_RGB_RED"; }; + rgb2_green: led_4 { gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; label = "1 LED_RGB_GREEN"; }; + rgb2_blue: led_5 { gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; label = "1 LED_RGB_BLUE"; }; + led1_blue: led_6 { gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; label = "2 LED_MONO_BLUE"; }; + led2_green: led_7 { gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; label = "3 LED_MONO_GREEN"; }; + led3_green: led_8 { gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; label = "4 LED_MONO_GREEN"; @@ -43,26 +52,31 @@ buttons { compatible = "gpio-keys"; + button_1_vol_dn: button_1_vol_dn { gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button_2_vol_up: button_2_vol_up { gpios = <&gpio0 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 3"; zephyr,code = ; }; + button4: button_4 { gpios = <&gpio0 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 4"; zephyr,code = ; }; + button5: button_5 { gpios = <&gpio0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 5"; diff --git a/boards/nordic/nrf5340dk/Kconfig b/boards/nordic/nrf5340dk/Kconfig deleted file mode 100644 index ee53c973ae8..00000000000 --- a/boards/nordic/nrf5340dk/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -# nRF5340 DK board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUNET_BOARD - string - default "nrf5340dk/nrf5340/cpunet" - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "nrf5340dk/nrf5340/cpuapp" - depends on BOARD_NRF5340DK_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi index f93e3a69402..10db7ee52e2 100644 --- a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi @@ -24,6 +24,7 @@ psels = , ; }; + group2 { psels = , ; @@ -75,6 +76,7 @@ ; low-power-enable; }; + group2 { psels = ; low-power-enable; @@ -87,6 +89,7 @@ psels = , ; }; + group2 { psels = , ; @@ -120,5 +123,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi index 153e8e83458..8af1da7ae1c 100644 --- a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi @@ -22,6 +22,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; }; @@ -41,6 +42,7 @@ gpio_fwd: nrf-gpio-forwarder { compatible = "nordic,nrf-gpio-forwarder"; status = "okay"; + uart { gpios = <&gpio1 1 0>, <&gpio1 0 0>, <&gpio0 11 0>, <&gpio0 10 0>; }; @@ -118,6 +120,7 @@ pinctrl-0 = <&qspi_default>; pinctrl-1 = <&qspi_sleep>; pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { compatible = "nordic,qspi-nor"; reg = <0>; @@ -169,4 +172,4 @@ zephyr_udc0: &usbd { }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi b/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi index f5bbbaa03cd..8c447727d89 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi @@ -7,18 +7,22 @@ / { leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; label = "Green LED 3"; @@ -27,21 +31,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 3"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 4"; diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi index 210eb1de211..30f638a7eae 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -57,5 +58,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts index 7bc0cd9a4ba..0cb1e8db91c 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts @@ -76,7 +76,6 @@ arduino_spi: &spi0 { }; &flash1 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -86,14 +85,17 @@ arduino_spi: &spi0 { label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0x17000>; }; + slot1_partition: partition@23000 { label = "image-1"; reg = <0x00023000 0x17000>; }; + storage_partition: partition@3a000 { label = "storage"; reg = <0x0003a000 0x6000>; @@ -106,4 +108,4 @@ arduino_spi: &spi0 { }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/nordic/nrf54h20dk/doc/img/nrf54h20.webp b/boards/nordic/nrf54h20dk/doc/img/nrf54h20.webp new file mode 100644 index 00000000000..59e49bc8055 Binary files /dev/null and b/boards/nordic/nrf54h20dk/doc/img/nrf54h20.webp differ diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index 8734ff9f745..f6eccadc852 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -33,6 +33,7 @@ compatible = "nordic,entropy-prng"; status = "okay"; }; + aliases { ipc-to-cpusys = &cpurad_cpusys_ipc; resetinfo = &cpurad_resetinfo; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi index d3b0156e838..e1347c35948 100644 --- a/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi @@ -54,26 +54,32 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + boot_partition: partition@0 { label = "mcuboot"; reg = <0x0 DT_SIZE_K(64)>; }; + slot0_partition: partition@10000 { label = "image-0"; reg = <0x10000 DT_SIZE_K(212)>; }; + slot0_ns_partition: partition@45000 { label = "image-0-nonsecure"; reg = <0x45000 DT_SIZE_K(212)>; }; + slot1_partition: partition@7a000 { label = "image-1"; reg = <0x7a000 DT_SIZE_K(212)>; }; + slot1_ns_partition: partition@af000 { label = "image-1-nonsecure"; reg = <0xaf000 DT_SIZE_K(212)>; }; + storage_partition: partition@e4000 { label = "storage"; reg = <0xe4000 DT_SIZE_K(36)>; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi index f1e9ee9afd8..9dfe9412d9b 100644 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi +++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi @@ -9,10 +9,12 @@ / { leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; label = "Green LED 1"; }; + led1: led_1 { gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; label = "Green LED 2"; @@ -21,21 +23,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 3"; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi index ac08b201f93..a87ae590f23 100644 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi +++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi @@ -8,6 +8,7 @@ group1 { psels = ; }; + group2 { psels = ; bias-pull-up; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi b/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi index 36eb7eb294b..6740544b524 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi @@ -9,18 +9,22 @@ / { leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; label = "Green LED 3"; @@ -29,6 +33,7 @@ pwmleds { compatible = "pwm-leds"; + /* * PWM signal can be exposed on GPIO pin only within same domain. * There is only one domain which contains both PWM and GPIO: @@ -42,21 +47,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 3"; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.dts index e2215ce1294..23ae87ccb11 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.dts @@ -35,26 +35,32 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + boot_partition: partition@0 { label = "mcuboot"; reg = <0x0 DT_SIZE_K(64)>; }; + slot0_partition: partition@10000 { label = "image-0"; reg = <0x10000 DT_SIZE_K(100)>; }; + slot0_ns_partition: partition@29000 { label = "image-0-nonsecure"; reg = <0x29000 DT_SIZE_K(100)>; }; + slot1_partition: partition@42000 { label = "image-1"; reg = <0x42000 DT_SIZE_K(100)>; }; + slot1_ns_partition: partition@5b000 { label = "image-1-nonsecure"; reg = <0x5b000 DT_SIZE_K(100)>; }; + storage_partition: partition@74000 { label = "storage"; reg = <0x74000 DT_SIZE_K(36)>; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts index 79b16bd4125..b2d96daa192 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.dts @@ -24,27 +24,34 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + boot_partition: partition@0 { label = "mcuboot"; reg = <0x0 DT_SIZE_K(64)>; }; + slot0_partition: partition@10000 { label = "image-0"; reg = <0x10000 DT_SIZE_K(324)>; }; + slot0_ns_partition: partition@61000 { label = "image-0-nonsecure"; reg = <0x61000 DT_SIZE_K(324)>; }; + slot1_partition: partition@b2000 { label = "image-1"; reg = <0xb2000 DT_SIZE_K(324)>; }; + slot1_ns_partition: partition@103000 { label = "image-1-nonsecure"; reg = <0x103000 DT_SIZE_K(324)>; }; + /* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */ + storage_partition: partition@15c000 { label = "storage"; reg = <0x15c000 DT_SIZE_K(36)>; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi index 6b7457a2818..7beece98e62 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -31,6 +32,7 @@ psels = , ; }; + group2 { psels = , ; diff --git a/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi b/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi index 48a57eb15d5..6962fc4b087 100644 --- a/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi @@ -28,7 +28,7 @@ &lfxo { load-capacitors = "internal"; - load-capacitance-femtofarad = <15500>; + load-capacitance-femtofarad = <17000>; }; &hfxo { diff --git a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi index 771fd9762e7..f719b2d9392 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi @@ -49,26 +49,32 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + boot_partition: partition@0 { label = "mcuboot"; reg = <0x0 DT_SIZE_K(64)>; }; + slot0_partition: partition@10000 { label = "image-0"; reg = <0x10000 DT_SIZE_K(449)>; }; + slot0_ns_partition: partition@80400 { label = "image-0-nonsecure"; reg = <0x80400 DT_SIZE_K(449)>; }; + slot1_partition: partition@f0800 { label = "image-1"; reg = <0xf0800 DT_SIZE_K(449)>; }; + slot1_ns_partition: partition@160c00 { label = "image-1-nonsecure"; reg = <0x160c00 DT_SIZE_K(449)>; }; + storage_partition: partition@1d1000 { label = "storage"; reg = <0x1d1000 DT_SIZE_K(36)>; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi index 6eb67fe1bb3..7a10c8d07ac 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi @@ -9,18 +9,22 @@ / { leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; label = "Green LED 1"; }; + led2: led_2 { gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; label = "Green LED 2"; }; + led3: led_3 { gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; label = "Green LED 3"; @@ -29,6 +33,7 @@ pwmleds { compatible = "pwm-leds"; + /* * PWM signal can be exposed on GPIO pin only within same domain. * There is only one domain which contains both PWM and GPIO: @@ -42,21 +47,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 0"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 3"; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi index b70be2bfa5e..51ea27781c9 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi @@ -8,6 +8,7 @@ group1 { psels = ; }; + group2 { psels = ; bias-pull-up; diff --git a/boards/nordic/nrf7002dk/Kconfig b/boards/nordic/nrf7002dk/Kconfig index bf5b239c98c..d4b7030a65a 100644 --- a/boards/nordic/nrf7002dk/Kconfig +++ b/boards/nordic/nrf7002dk/Kconfig @@ -21,15 +21,6 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD int default 4096 if BT_HCI_IPC -config DOMAIN_CPUNET_BOARD - string - default "nrf7002dk/nrf5340/cpunet" - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - endif if BOARD_NRF7002DK_NRF5340_CPUNET @@ -37,15 +28,4 @@ if BOARD_NRF7002DK_NRF5340_CPUNET config BT_ECC default y if BT -config DOMAIN_CPUAPP_BOARD - string - default "nrf7002dk/nrf5340/cpuapp" if BOARD_NRF7002DK_NRF5340_CPUAPP - default "nrf7002dk/nrf5340/cpuapp/ns" if BOARD_NRF7002DK_NRF5340_CPUAPP_NS - default "nrf7002dk/nrf5340/cpuapp/nrf7001" if BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 - default "nrf7002dk/nrf5340/cpuapp/nrf7001/ns" if BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - endif diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi index 7056652e573..9029ae078c0 100644 --- a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi @@ -20,10 +20,12 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; label = "Green LED 0"; }; + led1: led_1 { gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; label = "Green LED 1"; @@ -32,6 +34,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; @@ -39,11 +42,13 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; @@ -94,6 +99,7 @@ gpio_fwd: nrf-gpio-forwarder { compatible = "nordic,nrf-gpio-forwarder"; status = "okay"; + uart { gpios = <&gpio1 1 0>, <&gpio1 0 0>, <&gpio1 5 0>, <&gpio1 4 0>; }; @@ -189,6 +195,7 @@ arduino_i2c: &i2c1 { pinctrl-1 = <&spi4_sleep>; pinctrl-names = "default", "sleep"; cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + mx25r64: mx25r6435f@0 { compatible = "jedec,spi-nor"; reg = <0>; @@ -240,4 +247,4 @@ zephyr_udc0: &usbd { }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi index 8fae269f748..d8f78cfd40c 100644 --- a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi @@ -19,6 +19,7 @@ psels = , ; }; + group2 { psels = , ; @@ -84,6 +85,7 @@ group1 { psels = ; }; + group2 { psels = ; bias-pull-up; diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts index faea5ee69e3..64b8519fb69 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts @@ -28,24 +28,28 @@ }; leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - label = "Green LED 0"; - }; - led1: led_1 { - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - label = "Green LED 1"; - }; + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; }; buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; @@ -85,7 +89,6 @@ nrf_radio_coex: coex { status = "okay"; compatible = "nordic,nrf7002-coex"; - req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; @@ -156,14 +159,17 @@ arduino_spi: &spi0 { label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0x17000>; }; + slot1_partition: partition@23000 { label = "image-1"; reg = <0x00023000 0x17000>; }; + storage_partition: partition@3a000 { label = "storage"; reg = <0x0003a000 0x6000>; @@ -176,4 +182,4 @@ arduino_spi: &spi0 { }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi index 2e19d95f7f9..0abcb4724d5 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi @@ -4,6 +4,7 @@ psels = , ; }; + group2 { psels = , ; diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi index 419e7c8d70c..edb6d869bf6 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -31,6 +32,7 @@ psels = , ; }; + group2 { psels = , ; diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi index 0442b1cf527..fb012ea8d3d 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi @@ -18,14 +18,17 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; label = "Red LED 1"; }; + led1: led_1 { gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; label = "Green LED 2"; }; + led2: led_2 { gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; label = "Blue LED 3"; @@ -34,12 +37,15 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(8) PWM_POLARITY_NORMAL>; }; + pwm_led1: pwm_led_1 { pwms = <&pwm0 1 PWM_MSEC(8) PWM_POLARITY_NORMAL>; }; + pwm_led2: pwm_led_2 { pwms = <&pwm0 2 PWM_MSEC(8) PWM_POLARITY_NORMAL>; }; @@ -47,6 +53,7 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; @@ -120,13 +127,16 @@ thermistor-beta = <3380>; charging-enable; }; + regulators { compatible = "nordic,npm1300-regulator"; + BUCK1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; }; + BUCK2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -171,4 +181,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf9151dk/doc/img/nrf9151dk.webp b/boards/nordic/nrf9151dk/doc/img/nrf9151dk.webp new file mode 100644 index 00000000000..fefad9a54c4 Binary files /dev/null and b/boards/nordic/nrf9151dk/doc/img/nrf9151dk.webp differ diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi index a1680e830f4..2685cc354ec 100644 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -31,6 +32,7 @@ psels = , ; }; + group2 { psels = , ; diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi index 8ed282fe49e..9c59a0e0cf9 100644 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi @@ -18,18 +18,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; label = "Green LED 1"; }; + led1: led_1 { gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; label = "Green LED 2"; }; + led2: led_2 { gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; label = "Green LED 3"; }; + led3: led_3 { gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; label = "Green LED 4"; @@ -38,6 +42,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; @@ -45,21 +50,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 3"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 4"; @@ -214,4 +223,4 @@ arduino_spi: &spi3 { }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi index 1681e3ecb9b..22eae1b3b6c 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -25,5 +26,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi index 4c7475f7e73..8ca261027d1 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -31,6 +32,7 @@ psels = , ; }; + group2 { psels = , ; diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi index f57b3fa17c2..5033dda84c1 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi @@ -18,18 +18,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 2 0>; label = "Green LED 1"; }; + led1: led_1 { gpios = <&gpio0 3 0>; label = "Green LED 2"; }; + led2: led_2 { gpios = <&gpio0 4 0>; label = "Green LED 3"; }; + led3: led_3 { gpios = <&gpio0 5 0>; label = "Green LED 4"; @@ -38,6 +42,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; @@ -52,21 +57,25 @@ * the usual "4 buttons per DK board" convention. */ compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Switch 1"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Switch 2"; @@ -217,4 +226,4 @@ arduino_spi: &spi3 { }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi index 896531d7580..3e3f149d69d 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi @@ -39,6 +39,7 @@ &arduino_spi { cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>, /* D10 */ <&gpio0 25 GPIO_ACTIVE_LOW>; + mx25r64: mx25r6435f@1 { compatible = "jedec,spi-nor"; status = "disabled"; diff --git a/boards/nordic/nrf9161dk/doc/img/nrf9161dk.webp b/boards/nordic/nrf9161dk/doc/img/nrf9161dk.webp new file mode 100644 index 00000000000..4ac5a43f95a Binary files /dev/null and b/boards/nordic/nrf9161dk/doc/img/nrf9161dk.webp differ diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi index a1680e830f4..2685cc354ec 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi @@ -9,6 +9,7 @@ psels = , ; }; + group2 { psels = , ; @@ -31,6 +32,7 @@ psels = , ; }; + group2 { psels = , ; diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi index 7dade3bc0f7..1dc9a473cf6 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi @@ -18,18 +18,22 @@ leds { compatible = "gpio-leds"; + led0: led_0 { gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; label = "Green LED 1"; }; + led1: led_1 { gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; label = "Green LED 2"; }; + led2: led_2 { gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; label = "Green LED 3"; }; + led3: led_3 { gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; label = "Green LED 4"; @@ -38,6 +42,7 @@ pwmleds { compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; @@ -45,21 +50,25 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; zephyr,code = ; }; + button2: button_2 { gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 3"; zephyr,code = ; }; + button3: button_3 { gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 4"; @@ -214,4 +223,4 @@ arduino_spi: &spi3 { }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts index 6abddbeafcc..4a99911fa21 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts @@ -99,6 +99,7 @@ pwmleds { compatible = "pwm-leds"; + /* * LEDs are connected to GPIO Port 9 - pins 2-5. There is no valid hardware * configuration to pass PWM signal on pins 0 and 1. First valid config is P9.2. diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts index f1f3af54132..d6c03bc4a51 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts @@ -34,6 +34,7 @@ compatible = "nordic,entropy-prng"; status = "okay"; }; + aliases { ipc-to-cpusys = &cpurad_cpusys_ipc; resetinfo = &cpurad_resetinfo; diff --git a/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi b/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi index 5c2fcb56895..df96e0c27c7 100644 --- a/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi +++ b/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi @@ -48,5 +48,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/thingy52/thingy52_nrf52832.dts b/boards/nordic/thingy52/thingy52_nrf52832.dts index 9db5f67c486..e081ae877ce 100644 --- a/boards/nordic/thingy52/thingy52_nrf52832.dts +++ b/boards/nordic/thingy52/thingy52_nrf52832.dts @@ -37,26 +37,27 @@ leds { compatible = "gpio-leds"; + /* Lightwell RGB */ led0: led_0 { gpios = <&sx1509b 7 GPIO_ACTIVE_LOW>; label = "Red LED"; - //vin-supply = <&vdd_pwr>; }; + led1: led_1 { gpios = <&sx1509b 5 GPIO_ACTIVE_LOW>; label = "Green LED"; - //vin-supply = <&vdd_pwr>; }; + led2: led_2 { gpios = <&sx1509b 6 GPIO_ACTIVE_LOW>; label = "Blue LED"; - //vin-supply = <&vdd_pwr>; }; }; buttons { compatible = "gpio-keys"; + button0: button_0 { /* gpio flags need validation */ gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; @@ -138,10 +139,10 @@ compatible = "nordic,nrf-twim"; status = "okay"; clock-frequency = ; - pinctrl-0 = <&i2c0_default>; pinctrl-1 = <&i2c0_sleep>; pinctrl-names = "default", "sleep"; + sx1509b: sx1509b@3e { compatible = "semtech,sx1509b"; reg = <0x3e>; @@ -181,10 +182,10 @@ compatible = "nordic,nrf-twim"; status = "okay"; clock-frequency = ; - pinctrl-0 = <&i2c1_default>; pinctrl-1 = <&i2c1_sleep>; pinctrl-names = "default", "sleep"; + lis2dh12: lis2dh12@19 { compatible = "st,lis2dh12", "st,lis2dh"; reg = <0x19>; @@ -202,14 +203,17 @@ label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; reg = <0x0000C000 0x32000>; }; + slot1_partition: partition@3e000 { label = "image-1"; reg = <0x0003E000 0x32000>; }; + scratch_partition: partition@70000 { label = "image-scratch"; reg = <0x00070000 0xa000>; diff --git a/boards/nordic/thingy53/Kconfig b/boards/nordic/thingy53/Kconfig index a6781f63b0e..f538ffc38cb 100644 --- a/boards/nordic/thingy53/Kconfig +++ b/boards/nordic/thingy53/Kconfig @@ -8,28 +8,3 @@ config THINGY53_INIT_PRIORITY default 79 help Initialization priority of the Thingy:53. - -if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -config DOMAIN_CPUNET_BOARD - string - default "thingy53/nrf5340/cpunet" - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -if BOARD_THINGY53_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "thingy53/nrf5340/cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/nordic/thingy53/doc/img/thingy53.webp b/boards/nordic/thingy53/doc/img/thingy53.webp new file mode 100644 index 00000000000..0d906110f81 Binary files /dev/null and b/boards/nordic/thingy53/doc/img/thingy53.webp differ diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi index 2a9fa480bab..75fe378a40f 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi @@ -125,5 +125,4 @@ low-power-enable; }; }; - }; diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi index c319248434b..900b9d06e65 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi @@ -18,11 +18,13 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio1 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; @@ -32,14 +34,17 @@ leds { compatible = "gpio-leds"; + red_led: led_1 { gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; label = "RGB red LED"; }; + green_led: led_2 { gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; label = "RGB green LED"; }; + blue_led: led_3 { gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; label = "RGB blue LED"; @@ -48,6 +53,7 @@ pwmleds { compatible = "pwm-leds"; + red_led_pwm: led_pwm_0 { pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; label = "Red PWM LED"; @@ -119,6 +125,7 @@ gpio_fwd: nrf-gpio-forwarder { compatible = "nordic,nrf-gpio-forwarder"; status = "okay"; + fem-gpio-if { gpios = <&gpio1 11 0>, <&gpio1 12 0>, @@ -131,6 +138,7 @@ spi_fwd: nrf-spi-forwarder { compatible = "nordic,nrf-gpio-forwarder"; status = "disabled"; + fem-spi-if { gpios = <&gpio0 24 0>, <&gpio0 29 0>, @@ -208,10 +216,10 @@ compatible = "nordic,nrf-twim"; status = "okay"; clock-frequency = ; - pinctrl-0 = <&i2c1_default>; pinctrl-1 = <&i2c1_sleep>; pinctrl-names = "default", "sleep"; + bmm150: bmm150@10 { compatible = "bosch,bmm150"; reg = <0x10>; @@ -235,10 +243,10 @@ cs-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>, <&gpio1 4 GPIO_ACTIVE_LOW>, <&gpio0 24 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&spi3_default>; pinctrl-1 = <&spi3_sleep>; pinctrl-names = "default", "sleep"; + adxl362: spi-dev-adxl362@0 { compatible = "adi,adxl362"; spi-max-frequency = <8000000>; @@ -276,6 +284,7 @@ pinctrl-0 = <&qspi_default>; pinctrl-1 = <&qspi_sleep>; pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { compatible = "nordic,qspi-nor"; reg = <0>; @@ -319,4 +328,4 @@ zephyr_udc0: &usbd { }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts index 3003d4924ce..6da36791d5e 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts @@ -29,11 +29,13 @@ buttons { compatible = "gpio-keys"; + button0: button_0 { gpios = <&gpio1 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 1"; zephyr,code = ; }; + button1: button_1 { gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "Push button 2"; @@ -43,14 +45,17 @@ leds { compatible = "gpio-leds"; + red_led: led_1 { gpios = <&gpio1 8 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; label = "RGB red LED"; }; + green_led: led_2 { gpios = <&gpio1 6 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; label = "RGB green LED"; }; + blue_led: led_3 { gpios = <&gpio1 7 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; label = "RGB blue LED"; @@ -60,8 +65,8 @@ nrf_radio_fem: fem { compatible = "nordic,nrf21540-fem"; rx-en-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - mode-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - pdn-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + mode-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pdn-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; tx-en-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; spi-if = <&nrf_radio_fem_spi>; supply-voltage-mv = <3000>; @@ -136,7 +141,6 @@ fem_spi: &spi0 { }; &flash1 { - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -146,18 +150,17 @@ fem_spi: &spi0 { label = "mcuboot"; reg = <0x00000000 0xc000>; }; + slot0_partition: partition@c000 { label = "image-0"; - reg = <0x0000C000 0x12000>; + reg = <0x0000C000 0x17000>; }; - slot1_partition: partition@1e000 { + + slot1_partition: partition@23000 { label = "image-1"; - reg = <0x0001E000 0x12000>; - }; - scratch_partition: partition@30000 { - label = "image-scratch"; - reg = <0x00030000 0xa000>; + reg = <0x00023000 0x17000>; }; + storage_partition: partition@3a000 { label = "storage"; reg = <0x0003a000 0x6000>; @@ -170,4 +173,4 @@ fem_spi: &spi0 { }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/norik/octopus_som/octopus_som_common.dtsi b/boards/norik/octopus_som/octopus_som_common.dtsi index 538dfa3c0ec..2f7fb529c05 100644 --- a/boards/norik/octopus_som/octopus_som_common.dtsi +++ b/boards/norik/octopus_som/octopus_som_common.dtsi @@ -91,4 +91,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi b/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi index 9139b82417e..b364e4e3d79 100644 --- a/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi +++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi @@ -25,6 +25,14 @@ }; }; + /* CAN TX/RX --> PJ10/PJ11 (J8) */ + canfd0_default: canfd0_default { + group0 { + pinmux = , + ; + }; + }; + /* EMAC multi-function pins for MDIO, TX, REFCLK, RX pins */ emac_default: emac_default { group0 { @@ -43,4 +51,14 @@ slew-rate = "fast"; }; }; + + /* USBD multi-function pins for VBUS, D+, D-, and ID pins */ + usbd_default: usbd_default { + group0 { + pinmux = , + , + , + ; + }; + }; }; diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts b/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts index edfb4bcc0a6..9f912039eaf 100644 --- a/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts +++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts @@ -17,6 +17,8 @@ aliases { led0 = &green_led; led1 = &yellow_led; + sw0 = &btn0; + sw1 = &btn1; }; chosen { @@ -27,6 +29,7 @@ zephyr,itcm = &itcm; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,canbus = &canfd0; }; leds { @@ -42,12 +45,34 @@ label = "User LD1"; }; }; + + gpio_keys { + compatible = "gpio-keys"; + btn0: btn0 { + label = "BTN0"; + gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + btn1: btn1 { + label = "BTN1"; + gpios = <&gpioh 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; }; &gpiod { status = "okay"; }; +&gpioh { + status = "okay"; +}; + +&gpioi { + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; @@ -87,8 +112,21 @@ status = "okay"; }; +&canfd0 { + pinctrl-0 = <&canfd0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &emac { pinctrl-0 = <&emac_default>; pinctrl-names = "default"; status = "okay"; }; + +/* On enabled, usbd is required to be clocked in 48MHz. */ +zephyr_udc0: &usbd { + pinctrl-0 = <&usbd_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml b/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml index 2563989c8ef..34e3fc4a4e6 100644 --- a/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml +++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml @@ -12,4 +12,5 @@ ram: 1536 flash: 2048 supported: - gpio + - can vendor: nuvoton diff --git a/boards/nxp/frdm_k22f/frdm_k22f.dts b/boards/nxp/frdm_k22f/frdm_k22f.dts index 69439718a36..75c3bd27858 100644 --- a/boards/nxp/frdm_k22f/frdm_k22f.dts +++ b/boards/nxp/frdm_k22f/frdm_k22f.dts @@ -178,6 +178,10 @@ zephyr_udc0: &usbotg { num-bidir-endpoints = <8>; }; +zephyr_uhc0: &usbh { + status = "okay"; +}; + &gpioa { status = "okay"; }; @@ -204,25 +208,26 @@ zephyr_udc0: &usbotg { #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 2KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(180) + DT_SIZE_K(6))>; + reg = <0x00010000 DT_SIZE_K(182)>; }; - slot1_partition: partition@3E800 { + slot1_partition: partition@3D800 { label = "image-1"; - reg = <0x0003E800 DT_SIZE_K(180)>; + reg = <0x0003D800 DT_SIZE_K(182)>; }; - storage_partition: partition@6B800 { + storage_partition: partition@6B000 { label = "storage"; - reg = <0x0006B800 DT_SIZE_K(82)>; + reg = <0x0006B000 DT_SIZE_K(84)>; }; }; diff --git a/boards/nxp/frdm_k64f/frdm_k64f.dts b/boards/nxp/frdm_k64f/frdm_k64f.dts index 100dd6e69dc..bc9a440a8dc 100644 --- a/boards/nxp/frdm_k64f/frdm_k64f.dts +++ b/boards/nxp/frdm_k64f/frdm_k64f.dts @@ -233,21 +233,22 @@ zephyr_udc0: &usbotg { #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(8))>; + reg = <0x00010000 DT_SIZE_K(420)>; }; - slot1_partition: partition@7a000 { + slot1_partition: partition@79000 { label = "image-1"; - reg = <0x0007a000 DT_SIZE_K(416)>; + reg = <0x00079000 DT_SIZE_K(420)>; }; storage_partition: partition@e2000 { label = "storage"; diff --git a/boards/nxp/frdm_k82f/frdm_k82f.dts b/boards/nxp/frdm_k82f/frdm_k82f.dts index d28c32e5127..f2c5290da35 100644 --- a/boards/nxp/frdm_k82f/frdm_k82f.dts +++ b/boards/nxp/frdm_k82f/frdm_k82f.dts @@ -158,20 +158,21 @@ #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x0 DT_SIZE_K(44)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@b000 { label = "image-0"; - reg = <0xb000 (DT_SIZE_K(96) + DT_SIZE_K(8))>; + reg = <0xb000 DT_SIZE_K(100)>; }; - slot1_partition: partition@25000 { + slot1_partition: partition@24000 { label = "image-1"; - reg = <0x25000 DT_SIZE_K(96)>; + reg = <0x24000 DT_SIZE_K(100)>; }; storage_partition: partition@3d000 { label = "storage"; diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.dts b/boards/nxp/frdm_ke17z/frdm_ke17z.dts index 08590e6ee66..adc5a836aa1 100644 --- a/boards/nxp/frdm_ke17z/frdm_ke17z.dts +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.dts @@ -141,20 +141,21 @@ #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 2KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x0 DT_SIZE_K(44)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@b000 { label = "image-0"; - reg = <0xb000 (DT_SIZE_K(98) + DT_SIZE_K(4))>; + reg = <0xb000 DT_SIZE_K(100)>; }; - slot1_partition: partition@24800 { + slot1_partition: partition@24000 { label = "image-1"; - reg = <0x24800 DT_SIZE_K(98)>; + reg = <0x24000 DT_SIZE_K(100)>; }; storage_partition: partition@3d000 { label = "storage"; diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts index c4c42776e29..aa6eec2348a 100644 --- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts @@ -158,25 +158,27 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 2KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(202) + DT_SIZE_K(6))>; + reg = <0x00010000 DT_SIZE_K(204)>; }; - slot1_partition: partition@44000 { + slot1_partition: partition@43000 { label = "image-1"; - reg = <0x00044000 DT_SIZE_K(202)>; + reg = <0x00043000 DT_SIZE_K(204)>; }; - storage_partition: partition@76800 { + storage_partition: partition@76000 { label = "storage"; - reg = <0x00076800 DT_SIZE_K(38)>; + reg = <0x00076000 DT_SIZE_K(40)>; }; }; }; diff --git a/boards/nxp/frdm_mcxa153/board.c b/boards/nxp/frdm_mcxa153/board.c index b6ededcb572..52968d73fab 100644 --- a/boards/nxp/frdm_mcxa153/board.c +++ b/boards/nxp/frdm_mcxa153/board.c @@ -10,8 +10,8 @@ #include /* Core clock frequency: 96MHz */ -#define CLOCK_INIT_CORE_CLOCK 960000000U -#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 960000000U +#define CLOCK_INIT_CORE_CLOCK 96000000U +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /* System clock frequency. */ extern uint32_t SystemCoreClock; @@ -66,6 +66,21 @@ void board_early_init_hook(void) CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer0)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER0, 1u); + CLOCK_AttachClk(kFRO_HF_to_CTIMER0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u); + CLOCK_AttachClk(kFRO_HF_to_CTIMER1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER2, 1u); + CLOCK_AttachClk(kFRO_HF_to_CTIMER2); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma0)) RESET_ReleasePeripheralReset(kDMA_RST_SHIFT_RSTn); #endif @@ -90,6 +105,59 @@ void board_early_init_hook(void) CLOCK_EnableClock(kCLOCK_GateGPIO3); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c0)) + /* Attach FRO_HF_DIV clock to I3C, 96MHz / 4 = 24MHz. */ + CLOCK_SetClockDiv(kCLOCK_DivI3C0_FCLK, 4U); + CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) + CLOCK_SetClockDiv(kCLOCK_DivADC0, 1u); + CLOCK_AttachClk(kFRO12M_to_ADC0); + + CLOCK_EnableClock(kCLOCK_GateADC0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0)) + CLOCK_AttachClk(kFRO12M_to_CMP0); + CLOCK_SetClockDiv(kCLOCK_DivCMP0_FUNC, 1U); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac)); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPI2C0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0)) + CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPSPI0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) + CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); + CLOCK_AttachClk(kFRO12M_to_LPSPI1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) + +/* + * Clock Select Decides what input source the lptmr will clock from + * + * 0 <- Reserved + * 1 <- 16K FRO + * 2 <- Reserved + * 3 <- Combination of clocks configured in MRCC_LPTMR0_CLKSEL[MUX] field + */ +#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1 + CLOCK_SetupFRO16KClocking(kCLKE_16K_SYSTEM | kCLKE_16K_COREMAIN); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3 + CLOCK_SetClockDiv(kCLOCK_DivLPTMR0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPTMR0); +#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */ + +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0)) CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); CLOCK_AttachClk(kFRO12M_to_LPUART0); @@ -121,6 +189,15 @@ void board_early_init_hook(void) RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb)) + RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn); + CLOCK_EnableUsbfsClock(); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; } diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi b/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi index 65419589b86..5e52d22250b 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi @@ -16,6 +16,65 @@ }; }; + pinmux_i3c0: pinmux_i3c0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + group1 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_lpadc0: pinmux_lpadc0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + + pinmux_lpcmp0: pinmux_lpcmp0 { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + bias-pull-up; + }; + }; + + pinmux_lpi2c0: pinmux_lpi2c0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + + pinmux_lpspi0: pinmux_lpspi0 { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + pinmux_lpuart0: pinmux_lpuart0 { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts index d2d96daf79e..4765b9cd9e0 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts @@ -9,6 +9,7 @@ #include #include "frdm_mcxa153-pinctrl.dtsi" #include +#include / { model = "NXP FRDM_MCXA153 board"; @@ -21,6 +22,8 @@ sw0 = &user_button_2; sw1 = &user_button_3; pwm-0 = &flexpwm0_pwm0; + watchdog0 = &wwdt0; + ambient-temp0 = &p3t1755; }; chosen { @@ -56,18 +59,26 @@ user_button_2: button_2 { label = "User SW2"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; zephyr,code = ; }; user_button_3: button_3 { label = "User SW3"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; zephyr,code = ; }; }; }; +&ctimer0 { + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + &flash { partitions { compatible = "fixed-partitions"; @@ -116,9 +127,68 @@ status = "okay"; }; +&i3c0 { + status = "okay"; + pinctrl-0 = <&pinmux_i3c0>; + pinctrl-names = "default"; + + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; + + p3t1755: p3t1755@4800000236152a0090 { + compatible = "nxp,p3t1755"; + reg = <0x48 0x0236 0x152a0090>; + status = "okay"; + }; +}; + +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&lpcmp0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpcmp0>; + pinctrl-names = "default"; +}; + +&lpi2c0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c0>; + pinctrl-names = "default"; +}; + +&lpspi0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpspi0>; + pinctrl-names = "default"; +}; + +&lptmr0 { + status = "okay"; +}; + &lpuart0 { status = "okay"; current-speed = <115200>; pinctrl-0 = <&pinmux_lpuart0>; pinctrl-names = "default"; }; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart2>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb { + status = "okay"; +}; + +&wwdt0 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml b/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml index ae838f08d70..63cb510600f 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml @@ -14,9 +14,16 @@ toolchain: - zephyr - gnuarmemb supported: + - adc + - counter - dma - flash - gpio + - i2c + - i3c - pwm + - spi - uart + - usb_device + - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153_defconfig b/boards/nxp/frdm_mcxa153/frdm_mcxa153_defconfig index a630917318f..e006f652503 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153_defconfig +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153_defconfig @@ -9,3 +9,4 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y +CONFIG_LPADC_DO_OFFSET_CALIBRATION=y diff --git a/boards/nxp/frdm_mcxa166/board.c b/boards/nxp/frdm_mcxa166/board.c index 1c0ffff6c07..3e6904a7cd6 100644 --- a/boards/nxp/frdm_mcxa166/board.c +++ b/boards/nxp/frdm_mcxa166/board.c @@ -158,6 +158,101 @@ void board_early_init_hook(void) CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); #endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer0)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER2, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer3)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER3, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer4)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER4, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER4); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) + CLOCK_SetClockDiv(kCLOCK_DivADC, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_ADC); + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) + CLOCK_EnableClock(kCLOCK_GateADC0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) + CLOCK_EnableClock(kCLOCK_GateADC1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C2, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c3)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C3, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C3); +#endif + +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0)) + /* Configure input clock to be able to reach the datasheet specified band rate. */ + CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) + /* Configure input clock to be able to reach the datasheet specified band rate. */ + CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) + +/* + * Clock Select Decides what input source the lptmr will clock from + * + * 0 <- Reserved + * 1 <- 16K FRO + * 2 <- Reserved + * 3 <- Combination of clocks configured in MRCC_LPTMR0_CLKSEL[MUX] field + */ +#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1 + CLOCK_SetupFRO16KClocking(kCLKE_16K_SYSTEM | kCLKE_16K_COREMAIN); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3 + CLOCK_AttachClk(kFRO_LF_DIV_to_LPTMR0); + CLOCK_SetClockDiv(kCLOCK_DivLPTMR0, 1u); +#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */ + +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; } diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi b/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi index ed6e8de8186..97e4a8c2f53 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi @@ -26,4 +26,58 @@ input-enable; }; }; + + pinmux_lpadc0: pinmux_lpadc0 { + group0 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + + pinmux_lpi2c1: pinmux_lpi2c1 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_lpi2c2: pinmux_lpi2c2 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_lpi2c3: pinmux_lpi2c3 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + + pinmux_lpspi0: pinmux_lpspi0 { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; }; diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts b/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts index 0305e2b5c41..d926b02bcc3 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts @@ -116,6 +116,34 @@ pinctrl-names = "default"; }; +&edma0 { + status = "okay"; +}; + +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&lpi2c1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; +}; + +&lpi2c3 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c3>; + pinctrl-names = "default"; +}; + +&lpspi0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpspi0>; + pinctrl-names = "default"; +}; + &flash { partitions { compatible = "fixed-partitions"; @@ -145,3 +173,17 @@ &wwdt0 { status = "okay"; }; + +&ctimer0 { + status = "okay"; +}; + +&lptmr0 { + status = "okay"; +}; + +&lpuart3 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart3>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml b/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml index 90ed90d1117..bcabde47bdc 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml @@ -17,5 +17,10 @@ supported: - gpio - uart - flash + - adc + - i2c + - spi - watchdog + - counter + - dma vendor: nxp diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig b/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig index a630917318f..7d2f14fdd3c 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig @@ -9,3 +9,5 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y +CONFIG_LPADC_DO_OFFSET_CALIBRATION=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 diff --git a/boards/nxp/frdm_mcxa276/board.c b/boards/nxp/frdm_mcxa276/board.c index 1c0ffff6c07..3e6904a7cd6 100644 --- a/boards/nxp/frdm_mcxa276/board.c +++ b/boards/nxp/frdm_mcxa276/board.c @@ -158,6 +158,101 @@ void board_early_init_hook(void) CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); #endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer0)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER2, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer3)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER3, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer4)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER4, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_CTIMER4); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) + CLOCK_SetClockDiv(kCLOCK_DivADC, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_ADC); + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) + CLOCK_EnableClock(kCLOCK_GateADC0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) + CLOCK_EnableClock(kCLOCK_GateADC1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C2, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c3)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C3, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C3); +#endif + +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0)) + /* Configure input clock to be able to reach the datasheet specified band rate. */ + CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) + /* Configure input clock to be able to reach the datasheet specified band rate. */ + CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u); + CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) + +/* + * Clock Select Decides what input source the lptmr will clock from + * + * 0 <- Reserved + * 1 <- 16K FRO + * 2 <- Reserved + * 3 <- Combination of clocks configured in MRCC_LPTMR0_CLKSEL[MUX] field + */ +#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1 + CLOCK_SetupFRO16KClocking(kCLKE_16K_SYSTEM | kCLKE_16K_COREMAIN); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3 + CLOCK_AttachClk(kFRO_LF_DIV_to_LPTMR0); + CLOCK_SetClockDiv(kCLOCK_DivLPTMR0, 1u); +#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */ + +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; } diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi b/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi index 4eb700d76b2..3d0eb7bc5e9 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi @@ -26,4 +26,58 @@ input-enable; }; }; + + pinmux_lpadc0: pinmux_lpadc0 { + group0 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + + pinmux_lpi2c1: pinmux_lpi2c1 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_lpi2c2: pinmux_lpi2c2 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_lpi2c3: pinmux_lpi2c3 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + + pinmux_lpspi0: pinmux_lpspi0 { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; }; diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts b/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts index 2858f54c094..0e0618e38aa 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts @@ -116,6 +116,34 @@ pinctrl-names = "default"; }; +&edma0 { + status = "okay"; +}; + +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&lpi2c1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; +}; + +&lpi2c3 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c3>; + pinctrl-names = "default"; +}; + +&lpspi0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpspi0>; + pinctrl-names = "default"; +}; + &flash { partitions { compatible = "fixed-partitions"; @@ -145,3 +173,17 @@ &wwdt0 { status = "okay"; }; + +&ctimer0 { + status = "okay"; +}; + +&lptmr0 { + status = "okay"; +}; + +&lpuart3 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart3>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml b/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml index 72c1be60f4e..075dfbac694 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml @@ -17,5 +17,10 @@ supported: - gpio - uart - flash + - adc + - i2c + - spi - watchdog + - counter + - dma vendor: nxp diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig b/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig index a630917318f..7d2f14fdd3c 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig @@ -9,3 +9,5 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y +CONFIG_LPADC_DO_OFFSET_CALIBRATION=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 diff --git a/boards/nxp/frdm_mcxn236/board.c b/boards/nxp/frdm_mcxn236/board.c index fff4c085a96..f990251a4f3 100644 --- a/boards/nxp/frdm_mcxn236/board.c +++ b/boards/nxp/frdm_mcxn236/board.c @@ -13,9 +13,13 @@ #include "usb.h" /* USB PHY configuration */ -#define BOARD_USB_PHY_D_CAL 0x04U -#define BOARD_USB_PHY_TXCAL45DP 0x07U -#define BOARD_USB_PHY_TXCAL45DM 0x07U +#define BOARD_USB_PHY_D_CAL (0x04U) +#define BOARD_USB_PHY_TXCAL45DP (0x07U) +#define BOARD_USB_PHY_TXCAL45DM (0x07U) + +usb_phy_config_struct_t usbPhyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, +}; #endif /* Board xtal frequency in Hz */ @@ -219,11 +223,7 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO_HF_to_ADC0); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI - usb_phy_config_struct_t usbPhyConfig = { - BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, - }; - +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI) SPC0->ACTIVE_VDELAY = 0x0500; /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, * CORELDO is 1.0V) @@ -259,8 +259,10 @@ void board_early_init_hook(void) CLOCK_EnableClock(kCLOCK_UsbHsPhy); CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhsClock(); +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig); #endif +#endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0)) CLOCK_SetClkDiv(kCLOCK_DivCmp0FClk, 1U); diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts index 01e64e97085..6751b42f87c 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts @@ -130,6 +130,14 @@ zephyr_udc0: &usb1 { status = "okay"; + phy-handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <4>; + tx-cal-45-dp-ohms = <7>; + tx-cal-45-dm-ohms = <7>; }; &lpcmp0 { diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml index 2453534b318..1a234da09cd 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml @@ -25,6 +25,6 @@ supported: - pwm - regulator - spi + - usbd - watchdog - - usb_device vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/CMakeLists.txt b/boards/nxp/frdm_mcxn947/CMakeLists.txt index df4c3939ca7..3ab25bf5e31 100644 --- a/boards/nxp/frdm_mcxn947/CMakeLists.txt +++ b/boards/nxp/frdm_mcxn947/CMakeLists.txt @@ -1,8 +1,16 @@ # -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: Apache-2.0 # zephyr_library() zephyr_library_sources(board.c) + +if(CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET) + # Include flash configuration block + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + set(BOARD_DIR "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/frdmmcxn947") + zephyr_library_sources(${BOARD_DIR}/xip/mcxn_flexspi_nor_config.c) + zephyr_library_include_directories(${BOARD_DIR}/xip) +endif() diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 40efcb3ab81..9e6195fd746 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -1,5 +1,5 @@ /* - * Copyright 2024-2025 NXP + * Copyright 2024 NXP * SPDX-License-Identifier: Apache-2.0 */ #include @@ -84,19 +84,6 @@ __ramfunc static void enable_cache64(void) } #endif -static void unsecure_gpio(GPIO_Type * base) -{ - /* Enables CPU1 to access GPIO registers - * Pins and interrupts can be configured in non-secure access - */ - base->PCNS = 0xFFFFFFFFU; - base->ICNS = GPIO_ICNS_NSE1_MASK | GPIO_ICNS_NSE0_MASK; - - /* Pins and interrupts can be configured in non-privilege access */ - base->PCNP = 0xFFFFFFFFU; - base->ICNP = GPIO_ICNP_NPE1_MASK | GPIO_ICNP_NPE0_MASK; -} - void board_early_init_hook(void) { power_mode_od(); @@ -112,6 +99,11 @@ void board_early_init_hook(void) /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */ FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); +#ifdef CONFIG_FLASH + /* Enable clock for internal FMU flash */ + CLOCK_SetupClockCtrl(SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK); +#endif + /* Enable FRO HF(48MHz) output */ CLOCK_SetupFROHFClocking(48000000U); @@ -196,27 +188,22 @@ void board_early_init_hook(void) #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) CLOCK_EnableClock(kCLOCK_Gpio0); - unsecure_gpio(GPIO0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) CLOCK_EnableClock(kCLOCK_Gpio1); - unsecure_gpio(GPIO1); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2)) CLOCK_EnableClock(kCLOCK_Gpio2); - unsecure_gpio(GPIO2); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3)) CLOCK_EnableClock(kCLOCK_Gpio3); - unsecure_gpio(GPIO3); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4)) CLOCK_EnableClock(kCLOCK_Gpio4); - unsecure_gpio(GPIO4); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0)) diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 3f7ca04a6ba..0c28e440404 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -206,43 +206,6 @@ Here is an example for the :zephyr:code-sample:`mbox_data` application. :goals: flash :west-args: --sysbuild -Flashing to QSPI -================ - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :app: zephyr/samples/hello_world - :board: frdm_mcxn947/mcxn947/cpu0/qspi - :gen-args: -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"bootloader/mcuboot/root-rsa-2048.pem\" -DCONFIG_BOOTLOADER_MCUBOOT=y - :goals: flash - - -In order to load Zephyr application from QSPI you should program a bootloader like -MCUboot bootloader to internal flash. Here are the steps. - -.. zephyr-app-commands:: - :app: bootloader/mcuboot/boot/zephyr - :board: frdm_mcxn947/mcxn947/cpu0/qspi - :goals: flash - -Open a serial terminal, reset the board (press the RESET button), and you should -see the following message in the terminal: - -.. code-block:: console - - *** Booting MCUboot v2.1.0-rc1-2-g9f034729d99a *** - *** Using Zephyr OS build v3.6.0-4046-gf279a03af8ab *** - I: Starting bootloader - I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 - I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 - I: Boot source: none - I: Image index: 0, Swap type: none - I: Bootloader chainload address offset: 0x0 - I: Jumping to the first image slot - *** Booting Zephyr OS build v3.6.0-4046-gf279a03af8ab *** - Hello World! frdm_mcxn947/mcxn947/cpu0/qspi - Debugging ========= @@ -269,6 +232,122 @@ then a debugger can be attached. As a reference please see (`AN13264`_, section 4.2.3 for more information). The reference is for the RT1170 but similar technique can be also used here. +Using QSPI board variant +======================== +The FRDM-MCXN947 board includes an external QSPI flash. The MCXN947 can boot and +XIP directly from this flash using the FlexSPI interface. The QSPI variant +enables building applications and code to execute from the QSPI. + +Programming the ROM bootloader for external QSPI +------------------------------------------------ +By default, the MCXN947 bootloader in ROM will boot using internal flash. But +the MCU can be programmed to boot from external memory on the FlexSPI interface. +Before using the QSPI board variant, the board should be programmed to boot from +QSPI using the steps below. + +To configure the ROM bootloader, the Protected Flash Region (PFR) must be +programmed. Programming the PFR is done using NXP's ROM bootloader tools. +Some simple steps are provided in NXP's +`MCUXpresso SDK example hello_world_qspi_xip readme`_. The binary to program +with blhost is found at `bootfromflexspi.bin`_. A much more detailed explanation +is available at this post `Running code from external memory with MCX N94x`_. +The steps below program the FRDM-MCXN947 board. Note that these steps interface +to the ROM bootloader through the UART serial port, but USB is another option. + +1. Disconnect any terminal from the UART serial port, since these steps use that + serial port. +#. Connect a USB Type-C cable to the host computer and J17 on the board, in the + upper left corner. This powers the board, connects the debug probe, and + connects the UART serial port used for the ``blhost`` command. +#. Place the MCU in ISP mode. On the FRDM-MCXN947 board, the ISP button + can be used for this. Press and hold the ISP button SW3, on the bottom right + corner of the board. Press and release the Reset button SW1 on the upper left + corner of the board. The MCU has booted into ISP mode. Release the ISP + button. +#. Run the ``blhost`` command: + +.. tabs:: + + .. group-tab:: Ubuntu + + This step assumes the MCU serial port is connected to `/dev/ttyACM0` + + .. code-block:: shell + + blhost -t 2000 -p /dev/ttyACM0,115200 -j -- write-memory 0x01004000 bootfromflexspi.bin + + .. group-tab:: Windows + + Change `COMxx` to match the COM port number connected to the MCU serial port. + + .. code-block:: shell + + blhost -t 2000 -p COMxx -j -- write-memory 0x01004000 bootfromflexspi.bin + +Successful programming should look something like this: + +.. code-block:: console + + $ blhost -t 2000 -p /dev/ttyACM0,115200 -j -- write-memory 0x01004000 bootfromflexspi.bin + { + "command": "write-memory", + "response": [ + 256 + ], + "status": { + "description": "0 (0x0) Success.", + "value": 0 + } + } + +5. Reset the board with SW1 to exit ISP mode. Now the MCU is ready to boot from + QSPI. + +The ROM bootloader can be configured to boot from internal flash again. Repeat +the steps above to program the PFR, and program the file `bootfromflash.bin`_. + +Build, flash, and debug with the QSPI variant +--------------------------------------------- + +Once the PFR is programmed to boot from QSPI, the normal Zephyr steps to build, +flash, and debug can be used with the QSPI board variant. Here are some examples. + +Here is an example for the :zephyr:code-sample:`hello_world` application: + +.. zephyr-app-commands:: + :app: zephyr/samples/hello_world + :board: frdm_mcxn947//cpu0/qspi + :goals: flash + +MCUboot can also be used with the QSPI variant. By default, this places the +MCUboot bootloader in the ``boot-partition`` in QSPI flash, with the application +images. The ROM bootloader will boot first and load MCUboot in the QSPI, which +will load the app. This example builds and loads the :zephyr:code-sample:`blinky` +sample with MCUboot using Sysbuild: + +.. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: frdm_mcxn947//cpu0/qspi + :west-args: --sysbuild + :gen-args: -DSB_CONFIG_BOOTLOADER_MCUBOOT=y + :goals: flash + +Open a serial terminal, reset the board with the SW1 button, and the console +will print: + +.. code-block:: console + + *** Booting MCUboot vX.Y.Z *** + *** Using Zephyr OS build vX.Y.Z *** + I: Starting bootloader + I: Image index: 0, Swap type: none + I: Bootloader chainload address offset: 0x14000 + I: Image version: v0.0.0 + I: Jumping to the first image slot + *** Booting Zephyr OS build vX.Y.Z *** + LED state: OFF + LED state: ON + Troubleshooting =============== @@ -301,3 +380,15 @@ Troubleshooting .. _AN13264: https://www.nxp.com/docs/en/application-note/AN13264.pdf + +.. _MCUXpresso SDK example hello_world_qspi_xip readme: + https://github.com/nxp-mcuxpresso/mcuxsdk-examples/blob/main/_boards/frdmmcxn947/demo_apps/hello_world_qspi_xip/example_board_readme.md + +.. _bootfromflash.bin: + https://github.com/nxp-mcuxpresso/mcuxsdk-examples/blob/main/_boards/frdmmcxn947/demo_apps/hello_world_qspi_xip/cm33_core0/bootfromflash.bin + +.. _bootfromflexspi.bin: + https://github.com/nxp-mcuxpresso/mcuxsdk-examples/blob/main/_boards/frdmmcxn947/demo_apps/hello_world_qspi_xip/cm33_core0/bootfromflexspi.bin + +.. _Running code from external memory with MCX N94x: + https://community.nxp.com/t5/MCX-Microcontrollers-Knowledge/Running-code-from-external-memory-with-MCX-N94x/ta-p/1792204 diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 3ebc13c0e9a..bc96afa35ed 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -7,6 +7,7 @@ #include "frdm_mcxn947-pinctrl.dtsi" #include #include +#include / { aliases{ @@ -95,24 +96,19 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { pinctrl-0 = <&pinmux_flexcomm7_lpi2c>; pinctrl-names = "default"; clock-frequency = ; - ov7670: ov7670@21 { - compatible = "ovti,ov7670"; - reset-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - reg = <0x21>; - }; }; /* SmartDMA is used for video driver on this board */ &smartdma { + /* Shields do not enable video-sdma parent node so enable it by default */ status = "okay"; program-mem = <0x4000000>; + video_sdma: video-sdma { - status = "okay"; + status = "disabled"; compatible = "nxp,video-smartdma"; pinctrl-0 = <&pinmux_smartdma_camera>; pinctrl-names = "default"; - sensor = <&ov7670>; vsync-pin = <4>; hsync-pin = <11>; pclk-pin = <5>; @@ -289,3 +285,22 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd { pinctrl-0 = <&pinmux_sctimer>; pinctrl-names = "default"; }; + +/* + * Connection with camera modules such as the dvp_20pin_ov7670 shield + */ + +/ { + dvp_20pin_connector: dvp-20pin-connector { + compatible = "arducam,dvp-20pin-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + ; + }; +}; + +dvp_20pin_i2c: &flexcomm7_lpi2c7 {}; + +dvp_20pin_interface: &video_sdma {}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 057162bca26..1648313dc3d 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -24,6 +24,7 @@ supported: - i2c - i2s - i3c + - nvs - pwm - regulator - rtc diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts index d16e42561d4..48a35e2e661 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts @@ -8,6 +8,7 @@ #include "frdm_mcxn947_mcxn947_cpu0.dtsi" +/delete-node/ &boot_partition; /delete-node/ &slot0_partition; /delete-node/ &slot1_partition; /delete-node/ &storage_partition; @@ -28,17 +29,21 @@ #address-cells = <1>; #size-cells = <1>; - slot0_partition: partition@0 { + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(80)>; + }; + slot0_partition: partition@14000 { label = "image-0"; - reg = <0x00000000 DT_SIZE_M(3)>; + reg = <0x00014000 DT_SIZE_M(3)>; }; - slot1_partition: partition@300000 { + slot1_partition: partition@314000 { label = "image-1"; - reg = <0x00300000 DT_SIZE_M(3)>; + reg = <0x00314000 DT_SIZE_M(3)>; }; - storage_partition: partition@600000 { + storage_partition: partition@614000 { label = "storage"; - reg = <0x00600000 DT_SIZE_M(2)>; + reg = <0x00614000 DT_SIZE_K(1968)>; }; }; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index 99481630239..b8fc2e6aec4 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -135,17 +135,19 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 8KB. */ boot_partition: partition@0 { reg = <0x0 DT_SIZE_K(64)>; }; slot0_partition: partition@10000 { - reg = <0x10000 (DT_SIZE_K(416) + DT_SIZE_K(16))>; + reg = <0x10000 DT_SIZE_K(424)>; }; - slot1_partition: partition@7C000 { - reg = <0x7C000 DT_SIZE_K(416)>; + slot1_partition: partition@7A000 { + reg = <0x7A000 DT_SIZE_K(424)>; }; storage_partition: partition@E4000 { reg = <0xE4000 DT_SIZE_K(112)>; diff --git a/boards/nxp/frdm_rw612/CMakeLists.txt b/boards/nxp/frdm_rw612/CMakeLists.txt index 74480e24ba9..a86e4225c28 100644 --- a/boards/nxp/frdm_rw612/CMakeLists.txt +++ b/boards/nxp/frdm_rw612/CMakeLists.txt @@ -21,3 +21,12 @@ if (CONFIG_DT_HAS_NXP_ENET_MAC_ENABLED AND CONFIG_XTAL32K) "mutually exclusive on FRDM_RW612 due to shared PCB nets " "between the ethernet PHY and the external oscillator") endif() + +# Set TX power limit file to override the default one +if (CONFIG_WIFI_NXP) + zephyr_include_directories( + tx_pwr_limits + ) + + zephyr_compile_definitions(WIFI_BT_TX_PWR_LIMITS_OVERRIDE="wlan_txpwrlimit_cfg_WW_rw610.h") +endif() diff --git a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi index b54f0aa7e91..13611d653ca 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi @@ -79,4 +79,24 @@ slew-rate = "normal"; }; }; + + pinmux_hsgpio0: pinmux_hsgpio0 { + group0 { + pinmux = ; + slew-rate = "normal"; + }; + }; + + pinmux_hsgpio1: pinmux_hsgpio1 { + group0 { + pinmux = ; + slew-rate = "normal"; + }; + }; }; diff --git a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi index cf039cd59e7..31ef74793d3 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi @@ -63,6 +63,7 @@ current-speed = <115200>; pinctrl-0 = <&pinmux_flexcomm3_usart>; pinctrl-names = "default"; + wakeup-source; }; &flexcomm0 { @@ -75,6 +76,14 @@ &hsgpio0 { status = "okay"; + pinctrl-0 = <&pinmux_hsgpio0>; + pinctrl-names = "default"; +}; + +&hsgpio1 { + status = "okay"; + pinctrl-0 = <&pinmux_hsgpio1>; + pinctrl-names = "default"; }; &flexspi { @@ -101,24 +110,25 @@ #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@323000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x00323000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@623000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; + reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; }; }; }; @@ -229,6 +239,11 @@ wakeup-source; }; +&imu { + status = "okay"; + wakeup-source; +}; + zephyr_udc0: &usb_otg { status = "okay"; }; diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.dts b/boards/nxp/hexiwear/hexiwear_mk64f12.dts index b70479153d4..430b8169893 100644 --- a/boards/nxp/hexiwear/hexiwear_mk64f12.dts +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.dts @@ -187,21 +187,23 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(8))>; + reg = <0x00010000 DT_SIZE_K(420)>; }; - slot1_partition: partition@7a000 { + slot1_partition: partition@79000 { label = "image-1"; - reg = <0x0007a000 DT_SIZE_K(416)>; + reg = <0x00079000 DT_SIZE_K(420)>; }; storage_partition: partition@e2000 { label = "storage"; diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts b/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts index 6b4f464375b..1e48ac89b07 100644 --- a/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts +++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts @@ -8,6 +8,7 @@ #include #include "imx91_evk-pinctrl.dtsi" +#include / { model = "NXP i.MX91 A55"; @@ -24,6 +25,44 @@ reg = <0x80000000 DT_SIZE_M(1)>; }; + aliases { + led0 = &led_r; + led1 = &led_g; + sw0 = &btn_1; + }; + + leds { + compatible = "gpio-leds"; + led_r: led_r { + label = "LED_R"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + led_g: led_g { + label = "LED_G"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + }; + led_b: led_b { + label = "LED_B"; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn_1: btn_1{ + label = "BTN1"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn_2: btn_2{ + label = "BTN2"; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + }; &lpuart1 { @@ -32,3 +71,7 @@ pinctrl-0 = <&uart1_default>; pinctrl-names = "default"; }; + +&gpio2{ + status = "okay"; +}; diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml b/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml index 4302f9566b4..555e96cb20c 100644 --- a/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml +++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml @@ -13,5 +13,6 @@ toolchain: - cross-compile ram: 1024 supported: + - gpio - uart vendor: nxp diff --git a/boards/nxp/imx93_evk/CMakeLists.txt b/boards/nxp/imx93_evk/CMakeLists.txt index 39ae9ed0e4e..29ba502833b 100644 --- a/boards/nxp/imx93_evk/CMakeLists.txt +++ b/boards/nxp/imx93_evk/CMakeLists.txt @@ -5,12 +5,3 @@ zephyr_library() zephyr_library_sources(board.c) - -if(CONFIG_SOC_MIMX9352_A55) - file(WRITE ${CMAKE_BINARY_DIR}/zephyr/runner.jlinkscript - "LE - loadfile "${CMAKE_BINARY_DIR}/zephyr/zephyr.bin" ${CONFIG_SRAM_BASE_ADDRESS} - WReg PC ${CONFIG_SRAM_BASE_ADDRESS} - g - q") -endif() diff --git a/boards/nxp/imx93_evk/Kconfig.defconfig b/boards/nxp/imx93_evk/Kconfig.defconfig index 06b3e06736d..46bd77e3c32 100644 --- a/boards/nxp/imx93_evk/Kconfig.defconfig +++ b/boards/nxp/imx93_evk/Kconfig.defconfig @@ -67,4 +67,11 @@ endif # NETWORKING endif # BOARD_IMX93_EVK_MIMX9352_A55 +if IMX_USDHC + +config GPIO + default y + +endif # IMX_USDHC + endif # BOARD_IMX93_EVK diff --git a/boards/nxp/imx93_evk/board.cmake b/boards/nxp/imx93_evk/board.cmake index 97de8649143..dc8b9edc46a 100644 --- a/boards/nxp/imx93_evk/board.cmake +++ b/boards/nxp/imx93_evk/board.cmake @@ -5,7 +5,7 @@ if(CONFIG_SOC_MIMX9352_A55) -board_runner_args(jlink "--device=MIMX9352_A55_0" "--no-reset" "--flash-script=${CMAKE_BINARY_DIR}/zephyr/runner.jlinkscript") +board_runner_args(jlink "--device=MIMX9352_A55_0" "--no-reset" "--flash-sram") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst index ce5080d0755..906e395bf21 100644 --- a/boards/nxp/imx93_evk/doc/index.rst +++ b/boards/nxp/imx93_evk/doc/index.rst @@ -62,6 +62,37 @@ Serial Port This board configuration uses a single serial communication channel with the CPU's UART2 for A55 core and M33 core. +uSDHC (SD or eMMC Interface on A55) +----------------------------------- + +i.MX 93 processor has three ultra secured digital host controller (uSDHC) modules +for SD/eMMC interface support. On the MCIMX93-EVK board, the uSDHC2 interface of +the processor connects to the MicroSD card slot (J1002), and uSDHC1 interface connects +to the eMMC memory (located at the SOM board). DTS overlay file "usdhc1.overlay" and +"usdhc2.overlay" are provided to enable specified the uSDHC controller. + +Currently it rely on U-boot or Linux to boot Zephyr on Cortex-A Core, so Zephyr need +to use different uSDHC controller from U-boot or Linux to avoid resource conflict. +For example, if EVK board boots from SD Card which uses uSDHC2, Zephyr can use MMC +which uses uSDHC1 for testing: + +.. zephyr-app-commands:: + :zephyr-app: tests/subsys/sd/mmc + :host-os: unix + :board: imx93_evk/mimx9352/a55 + :goals: build + :gen-args: -DEXTRA_DTC_OVERLAY_FILE=usdhc1.overlay + +And if EVK board boots from MMC which uses uSDHC1, Zephyr can use SD Card which uses +uSDHC2 for testing: + +.. zephyr-app-commands:: + :zephyr-app: tests/subsys/sd/sdmmc + :host-os: unix + :board: imx93_evk/mimx9352/a55 + :goals: build + :gen-args: -DEXTRA_DTC_OVERLAY_FILE=usdhc2.overlay + Board MUX Control ----------------- diff --git a/boards/nxp/imx93_evk/dts/usdhc1.overlay b/boards/nxp/imx93_evk/dts/usdhc1.overlay new file mode 100644 index 00000000000..d020f5e31e5 --- /dev/null +++ b/boards/nxp/imx93_evk/dts/usdhc1.overlay @@ -0,0 +1,18 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &usdhc1; + }; +}; + +&usdhc1 { + status = "okay"; + sdmmc { + status = "okay"; + }; +}; diff --git a/boards/nxp/imx93_evk/dts/usdhc2.overlay b/boards/nxp/imx93_evk/dts/usdhc2.overlay new file mode 100644 index 00000000000..8e32620412d --- /dev/null +++ b/boards/nxp/imx93_evk/dts/usdhc2.overlay @@ -0,0 +1,18 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &usdhc2; + }; +}; + +&usdhc2 { + status = "okay"; + sdmmc { + status = "okay"; + }; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi index 8976def98b4..dbf35b8dc98 100644 --- a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi +++ b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi @@ -129,4 +129,198 @@ }; + pinmux_usdhc1: pinmux_usdhc1 { + group0 { + pinmux = <&iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk>, + <&iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe>; + drive-strength = "x1"; + bias-pull-down; + slew-rate = "fast"; + input-schmitt-enable; + }; + + group1 { + pinmux = <&iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd>, + <&iomuxc1_sd1_data0_usdhc_data_usdhc1_data0>, + <&iomuxc1_sd1_data1_usdhc_data_usdhc1_data1>, + <&iomuxc1_sd1_data2_usdhc_data_usdhc1_data2>, + <&iomuxc1_sd1_data3_usdhc_data_usdhc1_data3>, + <&iomuxc1_sd1_data4_usdhc_data_usdhc1_data4>, + <&iomuxc1_sd1_data5_usdhc_data_usdhc1_data5>, + <&iomuxc1_sd1_data6_usdhc_data_usdhc1_data6>, + <&iomuxc1_sd1_data7_usdhc_data_usdhc1_data7>; + drive-strength = "x1"; + slew-rate = "fast"; + input-schmitt-enable; + bias-pull-up; + input-enable; + }; + }; + + pinmux_usdhc1_100mhz: pinmux_usdhc1_100mhz { + group0 { + pinmux = <&iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk>, + <&iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe>; + drive-strength = "x3"; + bias-pull-down; + slew-rate = "fast"; + input-schmitt-enable; + }; + + group1 { + pinmux = <&iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd>, + <&iomuxc1_sd1_data0_usdhc_data_usdhc1_data0>, + <&iomuxc1_sd1_data1_usdhc_data_usdhc1_data1>, + <&iomuxc1_sd1_data2_usdhc_data_usdhc1_data2>, + <&iomuxc1_sd1_data3_usdhc_data_usdhc1_data3>, + <&iomuxc1_sd1_data4_usdhc_data_usdhc1_data4>, + <&iomuxc1_sd1_data5_usdhc_data_usdhc1_data5>, + <&iomuxc1_sd1_data6_usdhc_data_usdhc1_data6>, + <&iomuxc1_sd1_data7_usdhc_data_usdhc1_data7>; + drive-strength = "x3"; + slew-rate = "fast"; + input-schmitt-enable; + bias-pull-up; + input-enable; + }; + }; + + pinmux_usdhc1_200mhz: pinmux_usdhc1_200mhz { + group0 { + pinmux = <&iomuxc1_sd1_clk_usdhc_clk_usdhc1_clk>, + <&iomuxc1_sd1_strobe_usdhc_strobe_usdhc1_strobe>; + drive-strength = "x6"; + bias-pull-down; + slew-rate = "fast"; + input-schmitt-enable; + }; + + group1 { + pinmux = <&iomuxc1_sd1_cmd_usdhc_cmd_usdhc1_cmd>, + <&iomuxc1_sd1_data0_usdhc_data_usdhc1_data0>, + <&iomuxc1_sd1_data1_usdhc_data_usdhc1_data1>, + <&iomuxc1_sd1_data2_usdhc_data_usdhc1_data2>, + <&iomuxc1_sd1_data3_usdhc_data_usdhc1_data3>, + <&iomuxc1_sd1_data4_usdhc_data_usdhc1_data4>, + <&iomuxc1_sd1_data5_usdhc_data_usdhc1_data5>, + <&iomuxc1_sd1_data6_usdhc_data_usdhc1_data6>, + <&iomuxc1_sd1_data7_usdhc_data_usdhc1_data7>; + drive-strength = "x6"; + slew-rate = "fast"; + input-schmitt-enable; + bias-pull-up; + input-enable; + }; + }; + + pinmux_usdhc2: pinmux_usdhc2 { + group0 { + pinmux = <&iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk>; + drive-strength = "x1"; + bias-pull-down; + slew-rate = "fast"; + input-schmitt-enable; + }; + + group1 { + pinmux = <&iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd>, + <&iomuxc1_sd2_data0_usdhc_data_usdhc2_data0>, + <&iomuxc1_sd2_data1_usdhc_data_usdhc2_data1>, + <&iomuxc1_sd2_data2_usdhc_data_usdhc2_data2>, + <&iomuxc1_sd2_data3_usdhc_data_usdhc2_data3>; + drive-strength = "x1"; + slew-rate = "fast"; + input-schmitt-enable; + bias-pull-up; + input-enable; + }; + + group2 { + pinmux = <&iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect>; + drive-strength = "x4"; + slew-rate = "slightly_fast"; + }; + + group3 { + pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, + <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>; + drive-strength = "x4"; + slew-rate = "slightly_fast"; + bias-pull-up; + }; + }; + + pinmux_usdhc2_100mhz: pinmux_usdhc2_100mhz { + group0 { + pinmux = <&iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk>; + drive-strength = "x3"; + bias-pull-down; + slew-rate = "fast"; + input-schmitt-enable; + }; + + group1 { + pinmux = <&iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd>, + <&iomuxc1_sd2_data0_usdhc_data_usdhc2_data0>, + <&iomuxc1_sd2_data1_usdhc_data_usdhc2_data1>, + <&iomuxc1_sd2_data2_usdhc_data_usdhc2_data2>, + <&iomuxc1_sd2_data3_usdhc_data_usdhc2_data3>; + drive-strength = "x3"; + slew-rate = "fast"; + input-schmitt-enable; + bias-pull-up; + input-enable; + }; + + group2 { + pinmux = <&iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect>; + drive-strength = "x4"; + slew-rate = "slightly_fast"; + }; + + group3 { + pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, + <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>; + drive-strength = "x4"; + slew-rate = "slightly_fast"; + bias-pull-up; + }; + }; + + pinmux_usdhc2_200mhz: pinmux_usdhc2_200mhz { + group0 { + pinmux = <&iomuxc1_sd2_clk_usdhc_clk_usdhc2_clk>; + drive-strength = "x6"; + bias-pull-down; + slew-rate = "fast"; + input-schmitt-enable; + }; + + group1 { + pinmux = <&iomuxc1_sd2_cmd_usdhc_cmd_usdhc2_cmd>, + <&iomuxc1_sd2_data0_usdhc_data_usdhc2_data0>, + <&iomuxc1_sd2_data1_usdhc_data_usdhc2_data1>, + <&iomuxc1_sd2_data2_usdhc_data_usdhc2_data2>, + <&iomuxc1_sd2_data3_usdhc_data_usdhc2_data3>; + drive-strength = "x6"; + slew-rate = "fast"; + input-schmitt-enable; + bias-pull-up; + input-enable; + }; + + group2 { + pinmux = <&iomuxc1_sd2_vselect_usdhc_vselect_usdhc2_vselect>; + drive-strength = "x4"; + slew-rate = "slightly_fast"; + }; + + group3 { + pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, + <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>; + drive-strength = "x4"; + slew-rate = "slightly_fast"; + bias-pull-up; + }; + }; }; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts index 67272c846b5..20ed29fe6de 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -203,3 +203,40 @@ phys = <&can_phy0>; status = "okay"; }; + +&usdhc1 { + pinctrl-0 = <&pinmux_usdhc1>; + pinctrl-1 = <&pinmux_usdhc1_100mhz>; + pinctrl-2 = <&pinmux_usdhc1_200mhz>; + pinctrl-names = "default", "med", "fast"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + read-watermark = <0x10>; + write-watermark = <0x80>; + status = "disabled"; + sdmmc { + compatible = "zephyr,mmc-disk"; + disk-name = "SD2"; + status = "disabled"; + }; +}; + +&usdhc2 { + pinctrl-0 = <&pinmux_usdhc2>; + pinctrl-1 = <&pinmux_usdhc2_100mhz>; + pinctrl-2 = <&pinmux_usdhc2_200mhz>; + pinctrl-names = "default", "med", "fast"; + pwr-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + power-delay-ms = <20>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + read-watermark = <0x10>; + write-watermark = <0x80>; + status = "disabled"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "disabled"; + }; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts index cdc053f5c94..bfb43284081 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts @@ -79,3 +79,7 @@ pinctrl-names = "default"; status = "okay"; }; + +&lptmr2 { + status = "okay"; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml index 50cd837eb7b..2d4eade0557 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml @@ -19,4 +19,5 @@ supported: - pwm - spi - netif:eth + - counter vendor: nxp diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi index dbf467f3c16..f363d52a886 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi @@ -46,4 +46,22 @@ }; }; + pinmux_usbhfs: pinmux_usbhfs { + group0 { + pinmux = , + , + ; + bias-pull-up; + slew-rate = "standard"; + }; + }; + + pinmux_usbhhs: pinmux_usbhhs { + group0 { + pinmux = , + ; + bias-pull-up; + slew-rate = "standard"; + }; + }; }; diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts index a2407a2004a..d9d46ed50ed 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts @@ -127,3 +127,23 @@ zephyr_udc0: &usbhs { status = "okay"; }; + +zephyr_uhc0: &usbhfs { + pinctrl-0 = <&pinmux_usbhfs>; + pinctrl-names = "default"; + status = "okay"; +}; + +zephyr_uhc1: &usbhhs { + pinctrl-0 = <&pinmux_usbhhs>; + pinctrl-names = "default"; + status = "okay"; + phy_handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <5>; + tx-cal-45-dp-ohms = <10>; + tx-cal-45-dm-ohms = <10>; +}; diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi index 96997936388..bbc196e7eab 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi @@ -2,7 +2,7 @@ * NOTE: File generated by gen_board_pinctrl.py * from LPCXpresso55S69.mex * - * Copyright 2022 NXP + * Copyright 2022,2024 NXP * SPDX-License-Identifier: Apache-2.0 */ @@ -108,4 +108,23 @@ slew-rate = "standard"; }; }; + + pinmux_usbhfs: pinmux_usbhfs { + group0 { + pinmux = , + , + ; + bias-pull-up; + slew-rate = "standard"; + }; + }; + + pinmux_usbhhs: pinmux_usbhhs { + group0 { + pinmux = , + ; + bias-pull-up; + slew-rate = "standard"; + }; + }; }; diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts index b966c8545e6..44caca0d327 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts @@ -155,6 +155,19 @@ zephyr_udc0: &usbhs { phy-handle = <&usbphy1>; }; +zephyr_uhc0: &usbhfs { + pinctrl-0 = <&pinmux_usbhfs>; + pinctrl-names = "default"; + status = "okay"; +}; + +zephyr_uhc1: &usbhhs { + pinctrl-0 = <&pinmux_usbhhs>; + pinctrl-names = "default"; + status = "okay"; + phy_handle = <&usbphy1>; +}; + &usbphy1 { status = "okay"; tx-d-cal = <5>; diff --git a/boards/nxp/mcx_n9xx_evk/CMakeLists.txt b/boards/nxp/mcx_n9xx_evk/CMakeLists.txt index df4c3939ca7..39e5187bcab 100644 --- a/boards/nxp/mcx_n9xx_evk/CMakeLists.txt +++ b/boards/nxp/mcx_n9xx_evk/CMakeLists.txt @@ -1,8 +1,16 @@ # -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: Apache-2.0 # zephyr_library() zephyr_library_sources(board.c) + +if(CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET) + # Include flash configuration block + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + set(BOARD_DIR "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/mcxn9xxevk") + zephyr_library_sources(${BOARD_DIR}/xip/mcxn_flexspi_nor_config.c) + zephyr_library_include_directories(${BOARD_DIR}/xip) +endif() diff --git a/boards/nxp/mcx_n9xx_evk/board.c b/boards/nxp/mcx_n9xx_evk/board.c index 4d6c1f6d694..5b5a13c1ae9 100644 --- a/boards/nxp/mcx_n9xx_evk/board.c +++ b/boards/nxp/mcx_n9xx_evk/board.c @@ -99,6 +99,11 @@ void board_early_init_hook(void) /* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */ FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U)); +#ifdef CONFIG_FLASH + /* Enable clock for internal FMU flash */ + CLOCK_SetupClockCtrl(SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK); +#endif + /* Enable FRO HF(48MHz) output */ CLOCK_SetupFROHFClocking(48000000U); diff --git a/boards/nxp/mcx_n9xx_evk/doc/index.rst b/boards/nxp/mcx_n9xx_evk/doc/index.rst index c6fab3fd9a0..13a1324d21c 100644 --- a/boards/nxp/mcx_n9xx_evk/doc/index.rst +++ b/boards/nxp/mcx_n9xx_evk/doc/index.rst @@ -207,36 +207,6 @@ Here is an example for the :zephyr:code-sample:`mbox_data` application. :goals: flash :west-args: --sysbuild -Flashing to QSPI -================ - -In order to load Zephyr application from QSPI, program a bootloader like -MCUboot bootloader to internal flash. Here are the steps for the -:zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :app: zephyr/samples/hello_world - :board: mcx_n9xx_evk/mcxn947/cpu0/qspi - :gen-args: --sysbuild -- -DSB_CONFIG_BOOTLOADER_MCUBOOT=y - :goals: flash - -Open a serial terminal, reset the board (press the RESET button), and you should -see the following message in the terminal: - -.. code-block:: console - - *** Booting MCUboot vX.X.X *** - *** Using Zephyr OS build vX.X.X *** - I: Starting bootloader - I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 - I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3 - I: Boot source: none - I: Image index: 0, Swap type: none - I: Bootloader chainload address offset: 0x0 - I: Jumping to the first image slot - *** Booting Zephyr OS build vX.X.X *** - Hello World! mcx_n9xx_evk/mcxn947/cpu0/qspi - Debugging ========= @@ -263,6 +233,122 @@ then a debugger can be attached. As a reference please see (`AN13264`_, section 4.2.3 for more information). The reference is for the RT1170 but similar technique can be also used here. +Using QSPI board variant +======================== +The MCX-N9XX-EVK board includes an external QSPI flash. The MCXN947 can boot and +XIP directly from this flash using the FlexSPI interface. The QSPI variant +enables building applications and code to execute from the QSPI. + +Programming the ROM bootloader for external QSPI +------------------------------------------------ +By default, the MCXN947 bootloader in ROM will boot using internal flash. But +the MCU can be programmed to boot from external memory on the FlexSPI interface. +Before using the QSPI board variant, the board should be programmed to boot from +QSPI using the steps below. + +To configure the ROM bootloader, the Protected Flash Region (PFR) must be +programmed. Programming the PFR is done using NXP's ROM bootloader tools. +Some simple steps are provided in NXP's +`MCUXpresso SDK example hello_world_qspi_xip readme`_. The binary to program +with blhost is found at `bootfromflexspi.bin`_. A much more detailed explanation +is available at this post `Running code from external memory with MCX N94x`_. +The steps below program the MCX-N9XX-EVK board. Note that these steps interface +to the ROM bootloader through the UART serial port, but USB is another option. + +1. Disconnect any terminal from the UART serial port, since these steps use that + serial port. +#. Connect a micro USB cable to the host computer and J5 on the board, in the + upper left corner. This powers the board, connects the debug probe, and + connects the UART serial port used for the ``blhost`` command. +#. Place the MCU in ISP mode. On the MCX-N9XX-EVK board, the ISP button + can be used for this. Press and hold the ISP button SW3, on the bottom right + corner of the board. Press and release the Reset button SW1 on the lower left + corner of the board. The MCU has booted into ISP mode. Release the ISP + button. +#. Run the ``blhost`` command: + +.. tabs:: + + .. group-tab:: Ubuntu + + This step assumes the MCU serial port is connected to `/dev/ttyACM0` + + .. code-block:: shell + + blhost -t 2000 -p /dev/ttyACM0,115200 -j -- write-memory 0x01004000 bootfromflexspi.bin + + .. group-tab:: Windows + + Change `COMxx` to match the COM port number connected to the MCU serial port. + + .. code-block:: shell + + blhost -t 2000 -p COMxx -j -- write-memory 0x01004000 bootfromflexspi.bin + +Successful programming should look something like this: + +.. code-block:: console + + $ blhost -t 2000 -p /dev/ttyACM0,115200 -j -- write-memory 0x01004000 bootfromflexspi.bin + { + "command": "write-memory", + "response": [ + 256 + ], + "status": { + "description": "0 (0x0) Success.", + "value": 0 + } + } + +5. Reset the board with SW1 to exit ISP mode. Now the MCU is ready to boot from + QSPI. + +The ROM bootloader can be configured to boot from internal flash again. Repeat +the steps above to program the PFR, and program the file `bootfromflash.bin`_. + +Build, flash, and debug with the QSPI variant +--------------------------------------------- + +Once the PFR is programmed to boot from QSPI, the normal Zephyr steps to build, +flash, and debug can be used with the QSPI board variant. Here are some examples. + +Here is an example for the :zephyr:code-sample:`hello_world` application: + +.. zephyr-app-commands:: + :app: zephyr/samples/hello_world + :board: mcx_n9xx_evk//cpu0/qspi + :goals: flash + +MCUboot can also be used with the QSPI variant. By default, this places the +MCUboot bootloader in the ``boot-partition`` in QSPI flash, with the application +images. The ROM bootloader will boot first and load MCUboot in the QSPI, which +will load the app. This example builds and loads the :zephyr:code-sample:`blinky` +sample with MCUboot using Sysbuild: + +.. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: mcx_n9xx_evk//cpu0/qspi + :west-args: --sysbuild + :gen-args: -DSB_CONFIG_BOOTLOADER_MCUBOOT=y + :goals: flash + +Open a serial terminal, reset the board with the SW1 button, and the console +will print: + +.. code-block:: console + + *** Booting MCUboot vX.Y.Z *** + *** Using Zephyr OS build vX.Y.Z *** + I: Starting bootloader + I: Image index: 0, Swap type: none + I: Bootloader chainload address offset: 0x14000 + I: Image version: v0.0.0 + I: Jumping to the first image slot + *** Booting Zephyr OS build vX.Y.Z *** + LED state: OFF + LED state: ON + Troubleshooting =============== @@ -292,3 +378,15 @@ Troubleshooting .. _AN13264: https://www.nxp.com/docs/en/application-note/AN13264.pdf + +.. _MCUXpresso SDK example hello_world_qspi_xip readme: + https://github.com/nxp-mcuxpresso/mcuxsdk-examples/blob/main/_boards/mcxn9xxevk/demo_apps/hello_world_qspi_xip/example_board_readme.md + +.. _bootfromflash.bin: + https://github.com/nxp-mcuxpresso/mcuxsdk-examples/blob/main/_boards/mcxn9xxevk/demo_apps/hello_world_qspi_xip/cm33_core0/bootfromflash.bin + +.. _bootfromflexspi.bin: + https://github.com/nxp-mcuxpresso/mcuxsdk-examples/blob/main/_boards/mcxn9xxevk/demo_apps/hello_world_qspi_xip/cm33_core0/bootfromflexspi.bin + +.. _Running code from external memory with MCX N94x: + https://community.nxp.com/t5/MCX-Microcontrollers-Knowledge/Running-code-from-external-memory-with-MCX-N94x/ta-p/1792204 diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml index b7f1b052e2e..dd0b5d2e773 100644 --- a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml +++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml @@ -24,6 +24,7 @@ supported: - i2c - i2s - i3c + - nvs - pwm - regulator - rtc diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts index e9d45587553..f6e9db814cb 100644 --- a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts +++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts @@ -8,6 +8,7 @@ #include "mcx_n9xx_evk_mcxn947_cpu0.dtsi" +/delete-node/ &boot_partition; /delete-node/ &slot0_partition; /delete-node/ &slot1_partition; /delete-node/ &storage_partition; @@ -28,17 +29,21 @@ #address-cells = <1>; #size-cells = <1>; - slot0_partition: partition@0 { + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(80)>; + }; + slot0_partition: partition@14000 { label = "image-0"; - reg = <0x00000000 DT_SIZE_M(3)>; + reg = <0x00014000 DT_SIZE_M(3)>; }; - slot1_partition: partition@300000 { + slot1_partition: partition@314000 { label = "image-1"; - reg = <0x00300000 DT_SIZE_M(3)>; + reg = <0x00314000 DT_SIZE_M(3)>; }; - storage_partition: partition@600000 { + storage_partition: partition@614000 { label = "storage"; - reg = <0x00600000 DT_SIZE_M(2)>; + reg = <0x00614000 DT_SIZE_K(1968)>; }; }; }; diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts index fa2860dfe9b..93c22b64a90 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts @@ -105,24 +105,26 @@ arduino_serial: &lpuart1 {}; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; + reg = <0x00020000 DT_SIZE_M(7)>; }; - slot1_partition: partition@723000 { + slot1_partition: partition@720000 { label = "image-1"; - reg = <0x00723000 DT_SIZE_M(7)>; + reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E23000 { + storage_partition: partition@E20000 { label = "storage"; - reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; + reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts index 319d1ddb320..f79a57c2652 100644 --- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts @@ -102,24 +102,26 @@ arduino_serial: &lpuart4 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; + reg = <0x00020000 DT_SIZE_M(7)>; }; - slot1_partition: partition@723000 { + slot1_partition: partition@720000 { label = "image-1"; - reg = <0x00723000 DT_SIZE_M(7)>; + reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E23000 { + storage_partition: partition@E20000 { label = "storage"; - reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; + reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts index 6c3d096ff8e..29d52275d89 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts @@ -109,24 +109,26 @@ arduino_serial: &lpuart2 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@322000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x00322000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@622000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; + reg = <0x00620000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts index bc20298898a..6ccdb91db42 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts @@ -102,20 +102,22 @@ arduino_serial: &lpuart2 { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_K(1920) + DT_SIZE_K(8))>; + reg = <0x00020000 DT_SIZE_K(1924)>; }; - slot1_partition: partition@202000 { + slot1_partition: partition@201000 { label = "image-1"; - reg = <0x00202000 DT_SIZE_K(1920)>; + reg = <0x00201000 DT_SIZE_K(1924)>; }; storage_partition: partition@3E2000 { label = "storage"; diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst index db592aa16e8..34579205e11 100644 --- a/boards/nxp/mimxrt1040_evk/doc/index.rst +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -293,7 +293,7 @@ steps: Bluetooth Module ---------------- -For Murate 2EL M.2 Mdoule, the following hardware rework needs to be applied, +For the :ref:`nxp_m2_wifi_bt` shield, the following hardware rework needs to be applied, Solder 0 ohm resistors for R96, and R93. Remove resistors from R497, R498, R456 and R457. diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts index d5a31991ab1..744e8776dba 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts @@ -32,7 +32,6 @@ zephyr,flash-controller = &w25q64jvssiq; zephyr,code-partition = &slot0_partition; zephyr,uart-mcumgr = &lpuart1; - zephyr,bt-hci = &bt_hci_uart; }; sdram0: memory@80000000 { @@ -132,24 +131,26 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@322000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x00322000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@622000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; + reg = <0x00620000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; @@ -233,28 +234,6 @@ lpi2c3: &lpi2c3 { status = "okay"; }; -m2_hci_uart: &lpuart3 { - pinctrl-0 = <&pinmux_lpuart3_flowcontrol>; - pinctrl-1 = <&pinmux_lpuart3_sleep>; - pinctrl-names = "default", "sleep"; - - bt_hci_uart: bt_hci_uart { - compatible = "zephyr,bt-hci-uart"; - - m2_bt_module { - compatible = "nxp,bt-hci-uart"; - sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; - w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; - hci-operation-speed = <115200>; - hw-flow-control; - fw-download-primary-speed = <115200>; - fw-download-secondary-speed = <3000000>; - fw-download-secondary-flowcontrol; - }; - }; -}; +m2_hci_bt_uart: &lpuart3 {}; -&m2_hci_uart { - status = "okay"; - current-speed = <115200>; -}; +m2_wifi_sdio: &usdhc1 {}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi index 4fdca2496d3..0886b2ac912 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi @@ -211,6 +211,30 @@ zephyr_udc0: &usb1 { status = "okay"; }; +zephyr_uhc0: &usbh1 { + status = "okay"; + phy_handle = <&usbphy1>; +}; + +zephyr_uhc1: &usbh2 { + status = "okay"; + phy_handle = <&usbphy2>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <12>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + +&usbphy2 { + status = "okay"; + tx-d-cal = <12>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + &usdhc1 { status = "okay"; pwr-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts index e0aa389326a..fa124ba3570 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts @@ -48,24 +48,26 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 256KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(256)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@40000 { label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; + reg = <0x00040000 DT_SIZE_M(3)>; }; - slot1_partition: partition@3C0000 { + slot1_partition: partition@340000 { label = "image-1"; - reg = <0x003C0000 DT_SIZE_M(3)>; + reg = <0x00340000 DT_SIZE_M(3)>; }; - storage_partition: partition@6C0000 { + storage_partition: partition@640000 { label = "storage"; - reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; + reg = <0x00640000 (DT_SIZE_M(58) - DT_SIZE_K(256))>; }; }; }; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts index ca5a924d282..47e46ce6ee4 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts @@ -33,24 +33,26 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@322000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x00322000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@622000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; + reg = <0x00620000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst index 3f2265cb6a9..d2a04b18421 100644 --- a/boards/nxp/mimxrt1060_evk/doc/index.rst +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -137,6 +137,10 @@ The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers. +---------------+-----------------+---------------------------+ | GPIO_AD_B1_01 | LPI2C1_SDA | I2C | +---------------+-----------------+---------------------------+ +| GPIO_AD_B1_04 | LPUART3_CTS | UART BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_05 | LPUART3_RTS | UART BT HCI | ++---------------+-----------------+---------------------------+ | GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | +---------------+-----------------+---------------------------+ | GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | @@ -428,6 +432,14 @@ should see the following message in the terminal: ***** Booting Zephyr OS v1.14.0-rc1 ***** Hello World! mimxrt1060_evk//qspi +Shield for M.2 Wi-Fi and BT Interface +===================================== + +Rev C version is tested with :ref:`nxp_m2_wifi_bt` shield to attach any M.2 module +with BT HCI UART interface and Wi-Fi SDIO interface. The shield binds the required NXP +HCI driver or SDIO driver to perform firmware-load and other setup configurations +for NXP SoC IW416/IW612. + Troubleshooting =============== diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi index 2a26160c2a2..4143a7b6430 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2018,2024 NXP + * Copyright 2018,2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -188,6 +188,16 @@ zephyr_udc0: &usb1 { phy-handle = <&usbphy1>; }; +zephyr_uhc0: &usbh1 { + status = "okay"; + phy_handle = <&usbphy1>; +}; + +zephyr_uhc1: &usbh2 { + status = "okay"; + phy_handle = <&usbphy2>; +}; + &usbphy1 { status = "okay"; tx-d-cal = <12>; @@ -195,6 +205,13 @@ zephyr_udc0: &usb1 { tx-cal-45-dm-ohms = <6>; }; +&usbphy2 { + status = "okay"; + tx-d-cal = <12>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + &csi { pinctrl-0 = <&pinmux_csi>; pinctrl-names = "default"; @@ -308,3 +325,7 @@ arduino_spi: &lpspi1 { dvp_fpc24_i2c: &lpi2c1 {}; dvp_fpc24_interface: &csi {}; + +m2_hci_bt_uart: &lpuart3 {}; + +m2_wifi_sdio: &usdhc1 {}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts index 125f0fecd18..392675c9a0b 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts @@ -46,24 +46,26 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 256KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(256)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@40000 { label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; + reg = <0x00040000 DT_SIZE_M(3)>; }; - slot1_partition: partition@3C0000 { + slot1_partition: partition@340000 { label = "image-1"; - reg = <0x003C0000 DT_SIZE_M(3)>; + reg = <0x00340000 DT_SIZE_M(3)>; }; - storage_partition: partition@6C0000 { + storage_partition: partition@640000 { label = "storage"; - reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; + reg = <0x00640000 (DT_SIZE_M(58) - DT_SIZE_K(256))>; }; }; }; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts index 1e2876fc45d..bf24282e161 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts @@ -36,24 +36,26 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@322000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x00322000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@622000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; + reg = <0x00620000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts index de159e4ce24..af31e2168e1 100644 --- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts @@ -207,24 +207,26 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 256KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(256)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@40000 { label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; + reg = <0x00040000 DT_SIZE_M(3)>; }; - slot1_partition: partition@3C0000 { + slot1_partition: partition@340000 { label = "image-1"; - reg = <0x003C0000 DT_SIZE_M(3)>; + reg = <0x00340000 DT_SIZE_M(3)>; }; - storage_partition: partition@6C0000 { + storage_partition: partition@640000 { label = "storage"; - reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; + reg = <0x00640000 (DT_SIZE_M(58) - DT_SIZE_K(256))>; }; }; }; diff --git a/boards/nxp/mimxrt1064_evk/board.cmake b/boards/nxp/mimxrt1064_evk/board.cmake index e637428a1c3..3608ef269c7 100644 --- a/boards/nxp/mimxrt1064_evk/board.cmake +++ b/boards/nxp/mimxrt1064_evk/board.cmake @@ -8,6 +8,6 @@ board_runner_args(pyocd "--target=mimxrt1064") board_runner_args(jlink "--device=MIMXRT1064") board_runner_args(linkserver "--device=MIMXRT1064xxxxA:EVK-MIMXRT1064") +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst index 6ef06dfd77d..0c828258dba 100644 --- a/boards/nxp/mimxrt1064_evk/doc/index.rst +++ b/boards/nxp/mimxrt1064_evk/doc/index.rst @@ -263,7 +263,7 @@ This board supports 3 debug host tools. Please install your preferred host tool, then follow the instructions in `Configuring a Debug Probe`_ to configure the board appropriately. -* :ref:`jlink-debug-host-tools` (Default, Supported by NXP) +* :ref:`jlink-debug-host-tools` (Supported by NXP) * :ref:`linkserver-debug-host-tools` (Supported by NXP) * :ref:`pyocd-debug-host-tools` (Not supported by NXP) @@ -275,9 +275,10 @@ Configuring a Debug Probe ========================= .. note:: - When the device transitions into low power states, the debugger may be - unable to access the chip. Use caution when enabling ``CONFIG_PM``, and - if the debugger cannot flash the part, see :ref:`Troubleshooting RT1064` + * To boot from the QSPI flash, make sure SW7 is set to 0010 and SW5 is set to 0000. + * When the device transitions into low power states, the debugger may be + unable to access the chip. Use caution when enabling ``CONFIG_PM``, and + if the debugger cannot flash the part, see :ref:`Troubleshooting RT1064` For the RT1064, J47/J48 are the SWD isolation jumpers, J42 is the DFU mode jumper, and J21 is the 20 pin JTAG/SWD header. @@ -396,7 +397,7 @@ connected to the EVK properly. https://www.nxp.com/webapp/Download?colCode=IMXRT1064QSG .. _MIMXRT1064-EVK User Guide: - https://www.nxp.com/docs/en/data-sheet/MIMXRT10601064EKBHUG.pdf + https://www.nxp.com/webapp/Download?colCode=MIMXRT10601064EKBHUG .. _MIMXRT1064-EVK Debug Firmware: https://www.nxp.com/docs/en/application-note/AN13206.pdf diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts index 004c280362c..0ad53064524 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts @@ -162,11 +162,13 @@ nxp_parallel_i2c: &lpi2c1 {}; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; partitions { compatible = "fixed-partitions"; @@ -186,20 +188,22 @@ nxp_parallel_i2c: &lpi2c1 {}; compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_K(1980) + DT_SIZE_K(8))>; + reg = <0x00020000 DT_SIZE_K(1984)>; }; - slot1_partition: partition@211000 { + slot1_partition: partition@210000 { label = "image-1"; - reg = <0x00211000 DT_SIZE_K(1980)>; + reg = <0x00210000 DT_SIZE_K(1984)>; }; /* The storage partition is located in is25wp064 */ }; diff --git a/boards/nxp/mimxrt1160_evk/board.cmake b/boards/nxp/mimxrt1160_evk/board.cmake index 08c159f552a..01257666dc6 100644 --- a/boards/nxp/mimxrt1160_evk/board.cmake +++ b/boards/nxp/mimxrt1160_evk/board.cmake @@ -14,6 +14,6 @@ board_runner_args(pyocd "--target=mimxrt1160_cm4") board_runner_args(jlink "--device=MIMXRT1166xxx6_M4") endif() -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst index 1d97c49f0a4..f3f84a18960 100644 --- a/boards/nxp/mimxrt1160_evk/doc/index.rst +++ b/boards/nxp/mimxrt1160_evk/doc/index.rst @@ -209,15 +209,6 @@ The secondary core can be debugged normally in single core builds secondary core should be placed into a loop, then a debugger can be attached (see `AN13264`_, section 4.2.3 for more information) -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - Launching Images Targeting M4 Core ================================== If building targeting the M4 core, the M7 core must first run code to launch @@ -237,26 +228,34 @@ so: If desired, this behavior can be disabled by building with ``-DSB_CONFIG_SECOND_CORE_MCUX_LAUNCHER=n`` +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. The on-board +debugger :ref:`opensda-daplink-onboard-debug-probe` +works with the LinkServer runner, or can be reprogrammed with JLink firmware. + +Using LinkServer +---------------- + +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the default CMSIS-DAP firmware included in +the on-board debugger. + Using J-Link ------------ -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +The on-board debug circuit can be updated with Segger J-Link firmware, +or :ref:`jlink-external-debug-probe` can be attached to the EVK. See `Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. -Using LinkServer ----------------- +Use the ``-r jlink`` option with West to use the jlink runner. -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. LinkServer works with the CMSIS-DAP firmware include in LinkServer -install. Please follow the ``LPCScrypt\docs\Debug_Probe_Firmware_Programming.pdf`` -for more details. +.. code-block:: console -Linkserver is the default runner. You may also se the ``-r linkserver`` option -with West to use the LinkServer runner. + west flash -r jlink Configuring a Console ===================== diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi index 575c605c275..bf272c435fc 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi @@ -105,24 +105,26 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; + reg = <0x00020000 DT_SIZE_M(7)>; }; - slot1_partition: partition@723000 { + slot1_partition: partition@720000 { label = "image-1"; - reg = <0x00723000 DT_SIZE_M(7)>; + reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E23000 { + storage_partition: partition@E20000 { label = "storage"; - reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; + reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi index 91286ab6fb3..0ec66b87b2f 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi @@ -233,24 +233,25 @@ #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; + reg = <0x00020000 DT_SIZE_M(7)>; }; - slot1_partition: partition@723000 { + slot1_partition: partition@720000 { label = "image-1"; - reg = <0x00723000 DT_SIZE_M(7)>; + reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E23000 { + storage_partition: partition@E20000 { label = "storage"; - reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; + reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts index 5cd416c9c73..25978af90dc 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts @@ -35,8 +35,17 @@ device_type = "memory"; reg = <0x80000000 DT_SIZE_M(64)>; }; + + zephyr,user { + dac = <&dac>; + dac-channel-id = <0>; + dac-resolution = <12>; + }; }; +&dac { + status = "okay"; +}; &lpuart1 { status = "okay"; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml index dd213e258bf..4056069d8aa 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml @@ -14,6 +14,7 @@ toolchain: ram: 128 flash: 128 supported: + - dac - dma - flash - gpio diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay index b65621ee632..87486bc5cfa 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -36,24 +36,25 @@ #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; + reg = <0x00020000 DT_SIZE_M(7)>; }; - slot1_partition: partition@723000 { + slot1_partition: partition@720000 { label = "image-1"; - reg = <0x00723000 DT_SIZE_M(7)>; + reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E23000 { + storage_partition: partition@E20000 { label = "storage"; - reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>; + reg = <0x00E20000 (DT_SIZE_M(50) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml index e967a26465d..af866754ca7 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml @@ -14,6 +14,7 @@ toolchain: ram: 128 flash: 128 supported: + - dac - dma - flash - gpio diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts index 6d4a76fe260..0da2e365a25 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts @@ -75,6 +75,16 @@ gpio-map = <9 0 &gpio11 15 0>, /* Pin 9, RESETB */ <17 0 &gpio9 25 0>; /* Pin 17, PWDN */ }; + + zephyr,user { + dac = <&dac>; + dac-channel-id = <0>; + dac-resolution = <12>; + }; +}; + +&dac { + status = "okay"; }; zephyr_lcdif: &lcdif {}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml index 976b0e71f12..46587fb9547 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml @@ -17,6 +17,7 @@ supported: - adc - can - counter + - dac - display - dma - flash diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index c457d55fa54..2a13ccbd635 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,8 @@ aliases { /delete-property/ magn0; /delete-property/ accel0; + i2s-codec-tx = &sai1; + i2s-tx = &sai1; }; }; @@ -39,24 +41,25 @@ #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; + reg = <0x00020000 DT_SIZE_M(7)>; }; - slot1_partition: partition@723000 { + slot1_partition: partition@720000 { label = "image-1"; - reg = <0x00723000 DT_SIZE_M(7)>; + reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E23000 { + storage_partition: partition@E20000 { label = "storage"; - reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>; + reg = <0x00E20000 (DT_SIZE_M(50) - DT_SIZE_K(128))>; }; }; }; @@ -102,3 +105,19 @@ m2_hci_uart: &lpuart2 { status = "okay"; current-speed = <115200>; }; + +&lpi2c5 { + pinctrl-0 = <&pinmux_lpi2c5>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + audio_codec: wm8962@1a { + compatible = "wolfson,wm8962"; + reg = <0x1a>; + clock-source = "MCLK"; + clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>; + clock-names = "mclk"; + }; + +}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml index 6765cf82f25..009aebd98e2 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml @@ -17,6 +17,7 @@ supported: - adc - can - counter + - dac - dma - flash - gpio diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi index 699c1a6457d..38afe5b0445 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi @@ -199,24 +199,25 @@ #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; + reg = <0x00020000 DT_SIZE_M(7)>; }; - slot1_partition: partition@723000 { + slot1_partition: partition@720000 { label = "image-1"; - reg = <0x00723000 DT_SIZE_M(7)>; + reg = <0x00720000 DT_SIZE_M(7)>; }; - storage_partition: partition@E23000 { + storage_partition: partition@E20000 { label = "storage"; - reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; + reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts index efa9d9d244a..f0b56d3296a 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts @@ -406,24 +406,25 @@ zephyr_udc0: &usbhs { #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(3 * 4))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@323000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x00323000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@623000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(140))>; + reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/nxp/mimxrt685_evk/CMakeLists.txt b/boards/nxp/mimxrt685_evk/CMakeLists.txt index 53eb5a6e13e..56b32b94563 100644 --- a/boards/nxp/mimxrt685_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt685_evk/CMakeLists.txt @@ -1,16 +1,19 @@ # -# Copyright 2020-2022 NXP +# Copyright 2020-2022, 2025 NXP # # SPDX-License-Identifier: Apache-2.0 # if(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33) -zephyr_library() -zephyr_library_sources(init.c) + zephyr_library() + zephyr_library_sources(cm33/init.c) +elseif(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_HIFI4) + zephyr_library() + zephyr_library_sources(hifi4/init.c) endif() if(CONFIG_NXP_IMXRT_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33) + if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33 AND NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_HIFI4) message(WARNING "It appears you are using the board definition for " "the MIMXRT685-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") diff --git a/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk index a324f1157ea..997ed67df84 100644 --- a/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk +++ b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk @@ -4,3 +4,4 @@ config BOARD_MIMXRT685_EVK select SOC_PART_NUMBER_MIMXRT685SFVKB select SOC_MIMXRT685S_CM33 if BOARD_MIMXRT685_EVK_MIMXRT685S_CM33 + select SOC_MIMXRT685S_HIFI4 if BOARD_MIMXRT685_EVK_MIMXRT685S_HIFI4 diff --git a/boards/nxp/mimxrt685_evk/board.cmake b/boards/nxp/mimxrt685_evk/board.cmake index 79e6f768dd1..141af41a6d0 100644 --- a/boards/nxp/mimxrt685_evk/board.cmake +++ b/boards/nxp/mimxrt685_evk/board.cmake @@ -1,11 +1,16 @@ # -# Copyright (c) 2020, NXP +# Copyright 2020, 2025 NXP # # SPDX-License-Identifier: Apache-2.0 # -board_runner_args(jlink "--device=MIMXRT685S_M33" "--reset-after-load") -board_runner_args(linkserver "--device=MIMXRT685S:EVK-MIMXRT685") +if(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_CM33) + board_runner_args(jlink "--device=MIMXRT685S_M33" "--reset-after-load") + board_runner_args(linkserver "--device=MIMXRT685S:EVK-MIMXRT685") +elseif(CONFIG_BOARD_MIMXRT685_EVK_MIMXRT685S_HIFI4) + board_runner_args(jlink "--device=MIMXRT685S_HiFi4" "--reset-after-load") + board_runner_args(linkserver "--device=MIMXRT685S:EVK-MIMXRT685") +endif() include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/mimxrt685_evk/init.c b/boards/nxp/mimxrt685_evk/cm33/init.c similarity index 100% rename from boards/nxp/mimxrt685_evk/init.c rename to boards/nxp/mimxrt685_evk/cm33/init.c diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst index 6acc0cbdc6c..0c2caa9f1a6 100644 --- a/boards/nxp/mimxrt685_evk/doc/index.rst +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -294,6 +294,42 @@ steps: #. Reset by pressing SW3 +HiFi 4 DSP core +=============== + +The Cadence HiFi 4 DSP core instantiated in the i.MX RT685 microcontroller is +supported and works with both the proprietary Xtensa toolchains (``xcc`` in +earlier packages and ``xt-lang`` newer ones) and the +``xtensa-nxp_rt600_adsp_zephyr-elf`` GCC variant distributed in the Zephyr SDK. + +To build a project: + +- Set up toolchain environment + - No special configuration needed for the GCC variant in the Zephyr SDK. + - For the proprietary Xtensa toolchain, set ``XTENSA_CORE``, + ``XTENSA_TOOLCHAIN_PATH`` and ``TOOLCHAIN_VER`` according to your + installed version. ``ZEPHYR_TOOLCHAIN_VARIANT`` should be either ``xcc`` + or ``xt-clang``. +- Build the project with: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt685_evk/mimxrt685s/hifi4 + :goals: build + +Debugging can be directly carried out using the J-Link GDB server with +``xt-gdb`` (Xtensa proprietary) or ``gdb`` (Zephyr SDK) connected. It's +also possible to debug the HiFi 4 DSP in tandem with the CM33 core using the +``xt-ocd`` daemon. See `RT600 Dual-Core Communication and Debugging`_ +for details. + +As the HiFi 4 DSP is positioned as a secondary core, explicit initialisation +must be done in order for it to be functional. The ``nxp_rtxxx_adsp_ctrl``, +instantiated in the RT685's CM33 domain, takes care of this. Power domains +and clocks are set up upon it initialising. This is sufficient for +attaching a debugger to the core. For the use in an AMP system, this driver +handles code loading and run control. + .. include:: ../../common/board-footer.rst :start-after: nxp-board-footer @@ -314,3 +350,6 @@ steps: .. _i.MX RT685 Reference Manual: https://www.nxp.com/webapp/Download?colCode=UM11147 + +.. _RT600 Dual-Core Communication and Debugging: + https://www.nxp.com/docs/en/application-note/AN12789.pdf diff --git a/boards/nxp/mimxrt685_evk/hifi4/init.c b/boards/nxp/mimxrt685_evk/hifi4/init.c new file mode 100644 index 00000000000..77be78dfba1 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/hifi4/init.c @@ -0,0 +1,45 @@ +/* + * Copyright 2020-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +void board_early_init_hook(void) +{ +/* flexcomm1 and flexcomm3 are configured to loopback the TX signal to RX */ +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) && \ + (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) && \ + CONFIG_I2S + + /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */ + SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) | + SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(3); + +#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES + /* Select Data in from Transmit I2S - Flexcomm 3 */ + SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3); + /* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */ + SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1); +#endif + + /* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */ + SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | + SYSCTL1_FCCTRLSEL_WSINSEL(1); + + /* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */ + SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) | + SYSCTL1_FCCTRLSEL_WSINSEL(1); + +#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES + /* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */ + SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1); + /* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */ + SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1); +#endif + +#endif +} diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts index a92f00d2700..4b244bc4ef6 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts @@ -35,6 +35,7 @@ sdhc0 = &usdhc0; dmic-dev = &dmic0; mcuboot-button0 = &user_button_1; + mbox = &mbox; }; chosen { @@ -267,24 +268,25 @@ i2s1: &flexcomm3 { #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@323000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x00323000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@623000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; + reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; }; }; }; @@ -411,6 +413,10 @@ zephyr_udc0: &usbhs { status = "okay"; }; +&mbox { + status = "okay"; +}; + &dmic0 { status = "okay"; pinctrl-0 = <&pinmux_dmic0>; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.dts new file mode 100644 index 00000000000..5989b65dd88 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.dts @@ -0,0 +1,117 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "mimxrt685_evk-pinctrl.dtsi" + +/ { + model = "NXP MIMXRT685-EVK board, HiFi 4 DSP domain"; + compatible = "nxp,mimxrt685"; + + chosen { + zephyr,console = &flexcomm0; + zephyr,shell-uart = &flexcomm0; + }; + + aliases { + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + sw0 = &user_button_1; + mbox = &mbox; + }; + + leds: leds { + compatible = "gpio-leds"; + + green_led: led_1 { + gpios = <&gpio0 14 0>; + label = "User LED_GREEN"; + }; + + blue_led: led_2 { + gpios = <&gpio0 26 0>; + label = "User LED_BLUE"; + }; + + red_led: led_3 { + gpios = <&gpio0 31 0>; + label = "User LED_RED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_1: button_0 { + label = "User SW1"; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&flexcomm0 { + compatible = "nxp,lpc-usart"; + pinctrl-0 = <&pinmux_flexcomm0_usart>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +/* I2S receive channel */ +i2s0: &flexcomm1 { + status = "okay"; + compatible = "nxp,lpc-i2s"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 2>; + dma-names = "rx"; + pinctrl-0 = <&pinmux_flexcomm1_i2s>; + pinctrl-names = "default"; +}; + +/* I2S transmit channel */ +i2s1: &flexcomm3 { + status = "okay"; + compatible = "nxp,lpc-i2s"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 7>; + dma-names = "tx"; + pinctrl-0 = <&pinmux_flexcomm3_i2s>; + pinctrl-names = "default"; +}; + +&i3c0 { + status = "okay"; + pinctrl-0 = <&pinmux_i3c>; + pinctrl-names = "default"; + + audio_codec: wm8904@1a0000000000000000 { + compatible = "wolfson,wm8904"; + reg = <0x1a 0 0>; + clock-source = "MCLK"; + + clocks = <&clkctl0 MCUX_AUDIO_MCLK>; + clock-names = "mclk"; + }; +}; + +&mbox { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml new file mode 100644 index 00000000000..86cd87801ad --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4.yaml @@ -0,0 +1,26 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt685_evk/mimxrt685s/hifi4 +name: NXP MIMXRT685-EVK (HiFi 4) +type: mcu +arch: xtensa +ram: 64 +flash: 64 +toolchain: + - zephyr + - xt-clang + - xtools +supported: + - dma + - gpio + - i2c + - i3c + - i2s + - spi +testing: + only_tags: + - kernel diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4_defconfig b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4_defconfig new file mode 100644 index 00000000000..88f19d4360b --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_hifi4_defconfig @@ -0,0 +1,15 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y +CONFIG_NXP_IMXRT_BOOT_HEADER=n diff --git a/boards/nxp/mimxrt700_evk/board.c b/boards/nxp/mimxrt700_evk/board.c index ef162aab824..b50ea6b178d 100644 --- a/boards/nxp/mimxrt700_evk/board.c +++ b/boards/nxp/mimxrt700_evk/board.c @@ -497,6 +497,12 @@ void board_early_init_hook(void) /* Clear LCDIF reset. */ RESET_ClearPeripheralReset(kLCDIF_RST_SHIFT_RSTn); #endif + +#if (DT_NODE_HAS_STATUS(DT_NODELABEL(i3c2), okay) || \ + DT_NODE_HAS_STATUS(DT_NODELABEL(i3c3), okay)) + CLOCK_AttachClk(kSENSE_BASE_to_I3C23); + CLOCK_SetClkDiv(kCLOCK_DivI3c23Clk, 4U); +#endif } static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx) diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi b/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi index 80054f5b477..1ba82cd4c5e 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi @@ -84,4 +84,21 @@ input-enable; }; }; + + pinmux_i3c3: pinmux_i3c3 { + group0 { + pinmux = , + ; + slew-rate = "normal"; + drive-strength = "normal"; + input-enable; + bias-pull-up; + }; + group1 { + pinmux = ; + slew-rate = "normal"; + drive-strength = "normal"; + input-enable; + }; + }; }; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts index 92ecdc41aaf..78115a84e22 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts @@ -9,6 +9,7 @@ #include #include #include "mimxrt700_evk-pinctrl.dtsi" +#include / { model = "NXP MIMXRT700-EVK board"; @@ -17,6 +18,7 @@ aliases { led0 = &red_led; sw0 = &user_button_1; + ambient-temp0 = &p3t1755; }; chosen { @@ -80,3 +82,18 @@ &gpio8 { status = "okay"; }; + +&i3c3 { + status = "okay"; + pinctrl-0 = <&pinmux_i3c3>; + pinctrl-names = "default"; + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; + + p3t1755: p3t1755@4800000236152a0090 { + compatible = "nxp,p3t1755"; + reg = <0x48 0x0236 0x152a0090>; + status = "okay"; + }; +}; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml index 38c45ae9027..e562a648b4c 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml @@ -1,5 +1,5 @@ # -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: Apache-2.0 # @@ -18,4 +18,5 @@ supported: - gpio - uart - adc + - i3c vendor: nxp diff --git a/boards/nxp/rd_rw612_bga/CMakeLists.txt b/boards/nxp/rd_rw612_bga/CMakeLists.txt index e7ec1b7f361..8935c6b1d30 100644 --- a/boards/nxp/rd_rw612_bga/CMakeLists.txt +++ b/boards/nxp/rd_rw612_bga/CMakeLists.txt @@ -23,3 +23,12 @@ if (CONFIG_DT_HAS_NXP_ENET_MAC_ENABLED AND CONFIG_XTAL32K) "mutually exclusive on RD_RW612_BGA due to shared PCB nets " "between the ethernet PHY and the external oscillator") endif() + +# Set TX power limit file to override the default one +if (CONFIG_WIFI_NXP) + zephyr_include_directories( + tx_pwr_limits + ) + + zephyr_compile_definitions(WIFI_BT_TX_PWR_LIMITS_OVERRIDE="wlan_txpwrlimit_cfg_WW_rw610.h") +endif() diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index 4c050c63d91..005a9fd14ce 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -149,24 +149,25 @@ arduino_i2c: &flexcomm2 { #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@323000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x00323000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@623000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; + reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; }; }; }; @@ -310,3 +311,8 @@ nxp_8080_touch_panel_i2c: &arduino_i2c { status = "okay"; wakeup-source; }; + +&imu { + status = "okay"; + wakeup-source; +}; diff --git a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts index b2b3fefa4fe..7bd4792d18f 100644 --- a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts @@ -25,6 +25,7 @@ red-pwm-led = &red_pwm_led; green-pwm-led = &green_pwm_led; blue-pwm-led = &blue_pwm_led; + accel0 = &fxos8700; }; chosen { @@ -235,25 +236,26 @@ zephyr_udc0: &usbotg { #address-cells = <1>; #size-cells = <1>; + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(928) + DT_SIZE_K(12))>; + reg = <0x00010000 DT_SIZE_K(932)>; }; - slot1_partition: partition@FB000 { + slot1_partition: partition@F9000 { label = "image-1"; - reg = <0x000FB000 DT_SIZE_K(928)>; + reg = <0x000F9000 DT_SIZE_K(932)>; }; - storage_partition: partition@1E3000 { + storage_partition: partition@1E2000 { label = "storage"; - reg = <0x001E3000 DT_SIZE_K(116)>; + reg = <0x001E2000 DT_SIZE_K(120)>; }; }; }; @@ -347,7 +349,7 @@ zephyr_udc0: &usbotg { clock-frequency = ; - fxos8700@0 { + fxos8700: fxos8700@0 { compatible = "nxp,fxos8700"; reg = <0>; spi-max-frequency = ; @@ -357,7 +359,7 @@ zephyr_udc0: &usbotg { status = "okay"; }; - fxas21002@1 { + fxas21002: fxas21002@1 { compatible = "nxp,fxas21002"; reg = <1>; spi-max-frequency = ; diff --git a/boards/nxp/twr_ke18f/twr_ke18f.dts b/boards/nxp/twr_ke18f/twr_ke18f.dts index 66e10594521..c856b1bc12a 100644 --- a/boards/nxp/twr_ke18f/twr_ke18f.dts +++ b/boards/nxp/twr_ke18f/twr_ke18f.dts @@ -338,21 +338,23 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(200) + DT_SIZE_K(8))>; + reg = <0x00010000 DT_SIZE_K(204)>; }; - slot1_partition: partition@44000 { + slot1_partition: partition@43000 { label = "image-1"; - reg = <0x00044000 DT_SIZE_K(200)>; + reg = <0x00043000 DT_SIZE_K(204)>; }; storage_partition: partition@76000 { label = "storage"; diff --git a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts index 4a920fb39b9..e8a11851cf0 100644 --- a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts @@ -115,21 +115,23 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 8KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(416) + DT_SIZE_K(16))>; + reg = <0x00010000 DT_SIZE_K(424)>; }; - slot1_partition: partition@7C000 { + slot1_partition: partition@7A000 { label = "image-1"; - reg = <0x0007C000 DT_SIZE_K(416)>; + reg = <0x0007A000 DT_SIZE_K(424)>; }; storage_partition: partition@E4000 { label = "storage"; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi index 43dcb4b1d33..b8b8a0c06ae 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi @@ -212,24 +212,26 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* The MCUBoot swap-move algorithm uses the last 3 sectors - * of the primary slot0 for swap status and move. - */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(3 * 4))>; + reg = <0x00020000 DT_SIZE_M(3)>; }; - slot1_partition: partition@32E000 { + slot1_partition: partition@320000 { label = "image-1"; - reg = <0x0032E000 DT_SIZE_M(3)>; + reg = <0x00320000 DT_SIZE_M(3)>; }; - storage_partition: partition@62E000 { + storage_partition: partition@620000 { label = "storage"; - reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(140))>; + reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>; }; }; }; diff --git a/boards/others/esp32c3_supermini/esp32c3_supermini.dts b/boards/others/esp32c3_supermini/esp32c3_supermini.dts index 317494ca200..ff3b1945236 100644 --- a/boards/others/esp32c3_supermini/esp32c3_supermini.dts +++ b/boards/others/esp32c3_supermini/esp32c3_supermini.dts @@ -42,7 +42,7 @@ leds { compatible = "gpio-leds"; blue_led_0: led_0 { - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; label = "Blue LED 0"; }; }; diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst index d9a76304c15..b10d7a2f007 100644 --- a/boards/others/neorv32/doc/index.rst +++ b/boards/others/neorv32/doc/index.rst @@ -13,7 +13,7 @@ For more information about the NEORV32, see the following websites: - `The NEORV32 RISC-V Processor Datasheet`_ - `The NEORV32 RISC-V Processor User Guide`_ -The currently supported version is NEORV32 v1.11.2. +The currently supported version is NEORV32 v1.11.3. Supported Board Targets ======================= @@ -97,6 +97,13 @@ supporting the GPIOs, support can be enabled by setting the ``status`` property devicetree node to ``okay``. The number of supported GPIOs can be set via the ``ngpios`` devicetree property. +Pulse-Width Modulation +====================== + +The NEORV32 PWM controller is supported but disabled by default. For NEORV32 SoC implementations +supporting PWM, support can be enabled by setting the ``status`` property of the ``pwm`` devicetree +node to ``okay``. + True Random-Number Generator ============================ @@ -104,6 +111,14 @@ The True Random-Number Generator (TRNG) of the NEORV32 is supported, but disable NEORV32 SoC implementations supporting the TRNG, support can be enabled by setting the ``status`` property of the ``trng`` devicetree node to ``okay``. +General Purpose Timer +===================== + +The General Purpose Timer (GPTMR) of the NEORV32 is supported, but disabled by default. For NEORV32 +SoC implementations supporting the GPTMR, support can be enabled by setting the ``status`` property +of the ``gptmr`` devicetree node to ``okay`` and selecting the desired GPTMR clock prescaler using +the node's ``prescaler`` property. + Programming and Debugging ************************* diff --git a/boards/others/neorv32/neorv32_neorv32_minimalboot.dts b/boards/others/neorv32/neorv32_neorv32_minimalboot.dts index 8fd995f5c9b..690a5b16c46 100644 --- a/boards/others/neorv32/neorv32_neorv32_minimalboot.dts +++ b/boards/others/neorv32/neorv32_neorv32_minimalboot.dts @@ -8,6 +8,7 @@ #include #include +#include / { model = "NEORV32 MinimalBoot"; @@ -18,6 +19,13 @@ led1 = &led1; led2 = &led2; led3 = &led3; + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + pwm-led2 = &pwm_led2; + sw0 = &btn0; + sw1 = &btn1; + sw3 = &btn2; + sw4 = &btn3; }; chosen { @@ -51,6 +59,53 @@ label = "LED_3"; }; }; + + gpio_keys { + compatible = "gpio-keys"; + + btn0: btn0 { + label = "BTN0"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn1: btn1 { + label = "BTN1"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn2: btn2 { + label = "BTN2"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn3: btn3 { + label = "BTN3"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led0 { + pwms = <&pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED_0"; + }; + + pwm_led1: pwm_led1 { + pwms = <&pwm 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED_1"; + }; + + pwm_led2: pwm_led2 { + pwms = <&pwm 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED_2"; + }; + }; }; &cpu0 { @@ -88,3 +143,7 @@ status = "okay"; ngpios = <4>; }; + +&pwm { + status = "okay"; +}; diff --git a/boards/others/neorv32/neorv32_neorv32_minimalboot.yaml b/boards/others/neorv32/neorv32_neorv32_minimalboot.yaml index 88b24248d22..e55543f3eaa 100644 --- a/boards/others/neorv32/neorv32_neorv32_minimalboot.yaml +++ b/boards/others/neorv32/neorv32_neorv32_minimalboot.yaml @@ -9,3 +9,4 @@ ram: 64 flash: 64 supported: - gpio + - pwm diff --git a/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts b/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts index 43046f9398e..96f0546bcfa 100644 --- a/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts +++ b/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts @@ -8,6 +8,7 @@ #include #include +#include / { model = "NEORV32 UP5KDemo"; @@ -18,6 +19,13 @@ led1 = &led1; led2 = &led2; led3 = &led3; + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + pwm-led2 = &pwm_led2; + sw0 = &btn0; + sw1 = &btn1; + sw3 = &btn2; + sw4 = &btn3; }; chosen { @@ -51,6 +59,53 @@ label = "LED_3"; }; }; + + gpio_keys { + compatible = "gpio-keys"; + + btn0: btn0 { + label = "BTN0"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn1: btn1 { + label = "BTN1"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn2: btn2 { + label = "BTN2"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn3: btn3 { + label = "BTN3"; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led0 { + pwms = <&pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED_0"; + }; + + pwm_led1: pwm_led1 { + pwms = <&pwm 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED_1"; + }; + + pwm_led2: pwm_led2 { + pwms = <&pwm 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED_2"; + }; + }; }; &cpu0 { @@ -88,3 +143,7 @@ status = "okay"; ngpios = <32>; }; + +&pwm { + status = "okay"; +}; diff --git a/boards/others/neorv32/neorv32_neorv32_up5kdemo.yaml b/boards/others/neorv32/neorv32_neorv32_up5kdemo.yaml index 273e702c57a..b6c1f49e19e 100644 --- a/boards/others/neorv32/neorv32_neorv32_up5kdemo.yaml +++ b/boards/others/neorv32/neorv32_neorv32_up5kdemo.yaml @@ -9,3 +9,4 @@ ram: 64 flash: 64 supported: - gpio + - pwm diff --git a/boards/others/serpente/board.yml b/boards/others/serpente/board.yml index 0be3e94ffe6..5de65f6e2ce 100644 --- a/boards/others/serpente/board.yml +++ b/boards/others/serpente/board.yml @@ -1,6 +1,6 @@ board: name: serpente full_name: Arturo182 Serpente - vendor: solderparty + vendor: others socs: - name: samd21e18a diff --git a/boards/others/stm32f103_mini/board.cmake b/boards/others/stm32f103_mini/board.cmake index 20016aaba8e..12de9c0ee13 100644 --- a/boards/others/stm32f103_mini/board.cmake +++ b/boards/others/stm32f103_mini/board.cmake @@ -2,5 +2,5 @@ board_runner_args(jlink "--device=STM32F103RC" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/others/stm32f103_mini/board.yml b/boards/others/stm32f103_mini/board.yml index f88d33224dd..8f59073e36c 100644 --- a/boards/others/stm32f103_mini/board.yml +++ b/boards/others/stm32f103_mini/board.yml @@ -1,6 +1,6 @@ board: name: stm32f103_mini full_name: STM32F103 Mini - vendor: st + vendor: others socs: - name: stm32f103xe diff --git a/boards/panasonic/pan1783/Kconfig b/boards/panasonic/pan1783/Kconfig deleted file mode 100644 index 7951989cde3..00000000000 --- a/boards/panasonic/pan1783/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -# PAN1783 EVB board configuration - -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config DOMAIN_CPUNET_BOARD - string - default "pan1783_evb/nrf5340/cpunet" if BOARD_PAN1783_EVB_NRF5340_CPUAPP - default "pan1783a_evb/nrf5340/cpunet" if BOARD_PAN1783A_EVB_NRF5340_CPUAPP - default "pan1783a_pa_evb/nrf5340/cpunet" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # SOC_NRF5340_CPUAPP_QKAA - -config DOMAIN_CPUAPP_BOARD - string - default "pan1783_evb/nrf5340/cpuapp" if BOARD_PAN1783_EVB_NRF5340_CPUNET - default "pan1783a_evb/nrf5340/cpuapp" if BOARD_PAN1783A_EVB_NRF5340_CPUNET - default "pan1783a_pa_evb/nrf5340/cpuapp" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts index 81eff2968c3..b4b85e1a019 100644 --- a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts @@ -20,4 +20,4 @@ }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi index ad66cff5c5d..709934b9ad7 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi @@ -76,7 +76,7 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = <0 0 &gpio0 4 0>, /* AN */ - /* Not a GPIO*/ /* RST */ + <1 0 &gpio1 6 0>, /* RST */ <2 0 &gpio1 12 0>, /* CS */ <3 0 &gpio1 15 0>, /* SCK */ <4 0 &gpio1 14 0>, /* MISO */ @@ -271,4 +271,4 @@ zephyr_udc0: &usbd { }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi index 3fcdfba3dbb..fba45dba2aa 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi @@ -69,7 +69,7 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = <0 0 &gpio0 4 0>, /* AN */ - /* Not a GPIO*/ /* RST */ + <1 0 &gpio1 6 0>, /* RST */ <2 0 &gpio1 12 0>, /* CS */ <3 0 &gpio1 15 0>, /* SCK */ <4 0 &gpio1 14 0>, /* MISO */ @@ -204,4 +204,4 @@ arduino_spi: &spi0 { }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts index 52deb048576..5432047fd33 100644 --- a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts @@ -20,4 +20,4 @@ }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts index 54e580ffb75..8e7d4c3bdd3 100644 --- a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts @@ -30,4 +30,4 @@ }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/panasonic/panb511evb/Kconfig b/boards/panasonic/panb511evb/Kconfig new file mode 100644 index 00000000000..7b00e244121 --- /dev/null +++ b/boards/panasonic/panb511evb/Kconfig @@ -0,0 +1,30 @@ +# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +# PANB511EVB configuration + +if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS + +DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc) + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the flash region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral-specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the RAM region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral specific symbols. + +endif # BOARD_PANB511EVB_NRF54L15_CPUAPP_NS diff --git a/boards/panasonic/panb511evb/Kconfig.defconfig b/boards/panasonic/panb511evb/Kconfig.defconfig index 03c84b8f538..1c4e4be6637 100644 --- a/boards/panasonic/panb511evb/Kconfig.defconfig +++ b/boards/panasonic/panb511evb/Kconfig.defconfig @@ -1,9 +1,31 @@ # Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + if BOARD_PANB511EVB_NRF54L15_CPUAPP config ROM_START_OFFSET default 0x800 if BOOTLOADER_MCUBOOT endif # BOARD_PANB511EVB_NRF54L15_CPUAPP + +if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS + +config BT_CTLR + default BT + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y + +endif # BOARD_PANB511EVB_NRF54L15_CPUAPP_NS diff --git a/boards/panasonic/panb511evb/Kconfig.panb511evb b/boards/panasonic/panb511evb/Kconfig.panb511evb index 2454aba6270..12878fd47d4 100644 --- a/boards/panasonic/panb511evb/Kconfig.panb511evb +++ b/boards/panasonic/panb511evb/Kconfig.panb511evb @@ -2,6 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_PANB511EVB - select SOC_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP + select SOC_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP || BOARD_PANB511EVB_NRF54L15_CPUAPP_NS select SOC_NRF54L15_CPUFLPR if BOARD_PANB511EVB_NRF54L15_CPUFLPR || \ BOARD_PANB511EVB_NRF54L15_CPUFLPR_XIP diff --git a/boards/panasonic/panb511evb/board.cmake b/boards/panasonic/panb511evb/board.cmake index 3138d0b04d7..d6d51e58a39 100644 --- a/boards/panasonic/panb511evb/board.cmake +++ b/boards/panasonic/panb511evb/board.cmake @@ -4,8 +4,15 @@ if(CONFIG_SOC_NRF54L15_CPUAPP) board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") elseif(CONFIG_SOC_NRF54L15_CPUFLPR) - set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l15_cpuflpr.JLinkScript) - board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") + board_runner_args(jlink "--device=nRF54L15_RV32") +endif() + +if(CONFIG_BOARD_PANB511EVB_NRF54L15_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) endif() include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) diff --git a/boards/panasonic/panb511evb/board.yml b/boards/panasonic/panb511evb/board.yml index a7e9a5901a4..6e2d60bf4a0 100644 --- a/boards/panasonic/panb511evb/board.yml +++ b/boards/panasonic/panb511evb/board.yml @@ -7,3 +7,42 @@ board: variants: - name: xip cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp +runners: + run_once: + '--recover': + - runners: + - nrfjprog + - nrfutil + run: first + groups: + - boards: + - panb511evb/nrf54l15/cpuapp + - panb511evb/nrf54l15/cpuapp/ns + - panb511evb/nrf54l15/cpuflpr + - panb511evb/nrf54l15/cpuflpr/xip + '--erase': + - runners: + - nrfjprog + - jlink + - nrfutil + run: first + groups: + - boards: + - panb511evb/nrf54l15/cpuapp + - panb511evb/nrf54l15/cpuapp/ns + - panb511evb/nrf54l15/cpuflpr + - panb511evb/nrf54l15/cpuflpr/xip + '--reset': + - runners: + - nrfjprog + - jlink + - nrfutil + run: last + groups: + - boards: + - panb511evb/nrf54l15/cpuapp + - panb511evb/nrf54l15/cpuapp/ns + - panb511evb/nrf54l15/cpuflpr + - panb511evb/nrf54l15/cpuflpr/xip diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi b/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi index bc3a54459d9..143a744e792 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi @@ -75,4 +75,24 @@ low-power-enable; }; }; + + /* + * Note that P0.04 is the dedicated pin to output the LFCLK + * (32 KHz clock). Add the following line: + * + * to the grtc_default and grtc_sleep node. + * Note that this may will affect the uart30 (CTS) functionality. + */ + /omit-if-no-ref/ grtc_default: grtc_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ grtc_sleep: grtc_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; }; diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml index b30e5ffa106..e911ee9e54c 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml @@ -14,6 +14,7 @@ flash: 324 supported: - adc - counter + - dmic - gpio - i2c - pwm diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi index bf7922d8069..634f758d531 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi @@ -27,12 +27,12 @@ &lfxo { load-capacitors = "internal"; - load-capacitance-femtofarad = <15500>; + load-capacitance-femtofarad = <15000>; }; &hfxo { load-capacitors = "internal"; - load-capacitance-femtofarad = <15000>; + load-capacitance-femtofarad = <16000>; }; ®ulators { diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig index 41648ab5b23..638fe33f5d4 100644 --- a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig @@ -16,14 +16,3 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot -# be applied as the (0x0 - 0x400) is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable Cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Start SYSCOUNTER on driver init -CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts new file mode 100644 index 00000000000..f4aeab933f8 --- /dev/null +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include +#include "panb511evb_nrf54l15_cpuapp_common.dtsi" + +/ { + model = "Panasonic PAN B511 EVB nRF54L15 Application MCU"; + compatible = "panasonic-industrial-devices-europe-gmbh,panb511evb-cpuapp"; + + chosen { + zephyr,code-partition = &slot0_ns_partition; + zephyr,sram = &sram0_ns; + zephyr,entropy = &psa_rng; + }; + + /delete-node/ rng; + + psa_rng: psa-rng { + status = "okay"; + }; +}; + +/ { + /* + * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support + * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). + * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). + * + * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for + * the FLPR MCU. + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + reg = <0x20000000 DT_SIZE_K(80)>; + }; + + sram0_ns: image_ns@20014000 { + /* Non-Secure image memory */ + reg = <0x20014000 DT_SIZE_K(80)>; + }; + }; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the + * last 96kB are reserved for the FLPR MCU. + * + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0000000 DT_SIZE_K(512)>; + }; + + tfm_ps_partition: partition@80000 { + label = "tfm-ps"; + reg = <0x00080000 DT_SIZE_K(16)>; + }; + + tfm_its_partition: partition@84000 { + label = "tfm-its"; + reg = <0x00084000 DT_SIZE_K(16)>; + }; + + tfm_otp_partition: partition@88000 { + label = "tfm-otp"; + reg = <0x00088000 DT_SIZE_K(8)>; + }; + + slot0_ns_partition: partition@8A000 { + label = "image-0-nonsecure"; + reg = <0x0008A000 DT_SIZE_K(844)>; + }; + + storage_partition: partition@15D000 { + label = "storage"; + reg = <0x00015D000 DT_SIZE_K(32)>; + }; + }; +}; + +&uart20 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; + + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml new file mode 100644 index 00000000000..2a092dea13d --- /dev/null +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +identifier: panb511evb/nrf54l15/cpuapp/ns +name: PANB511-EVB-nRF54l15-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +ram: 256 +flash: 1524 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns_defconfig b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns_defconfig new file mode 100644 index 00000000000..5f6e098f452 --- /dev/null +++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns_defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +# Disable TFM BL2 since it is not supported +CONFIG_TFM_BL2=n + +# Support for silence logging is not supported at the moment +# Tracked by: NCSDK-31930 +CONFIG_TFM_LOG_LEVEL_SILENCE=n + +# The oscillators are configured as secure and cannot be configured +# from the non secure application directly. This needs to be set +# otherwise nrfx will try to configure them, resulting in a bus +# fault. +CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y diff --git a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml index 23d07a25c99..73d19a5a180 100644 --- a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml +++ b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml @@ -22,4 +22,3 @@ supported: - spi - gpio - can -vendor: nxp diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml index 2af3d88b937..e8e0208f8f6 100644 --- a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml +++ b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml @@ -20,4 +20,3 @@ testing: supported: - uart - gpio -vendor: nxp diff --git a/boards/pimoroni/pico_plus2/doc/index.rst b/boards/pimoroni/pico_plus2/doc/index.rst index 28f265e3898..bf77934242d 100644 --- a/boards/pimoroni/pico_plus2/doc/index.rst +++ b/boards/pimoroni/pico_plus2/doc/index.rst @@ -42,15 +42,16 @@ Programming and Debugging .. zephyr:board-supported-runners:: -The overall explanation regarding flashing and debugging is the same as or ``rpi_pico``. -See :ref:`rpi_pico_flashing_using_openocd` and :ref:`rpi_pico_flashing_using_uf2` -in ``rpi_pico`` documentation. +The overall explanation regarding flashing and debugging is the same as or :zephyr:board:`rpi_pico`. +See :ref:`rpi_pico_programming_and_debugging` in :zephyr:board:`rpi_pico` documentation. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. + +Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: pico_plus2 + :board: pico_plus2/rp2350b/m33 :goals: build flash - :gen-args: -DOPENOCD=/usr/local/bin/openocd + :flash-args: --openocd /usr/local/bin/openocd .. target-notes:: diff --git a/boards/pjrc/teensy4/Kconfig.defconfig b/boards/pjrc/teensy4/Kconfig.defconfig index 2af9d12ef9f..fbd4928b386 100644 --- a/boards/pjrc/teensy4/Kconfig.defconfig +++ b/boards/pjrc/teensy4/Kconfig.defconfig @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -if BOARD_TEENSY40 || BOARD_TEENSY41 +if BOARD_TEENSY40 || BOARD_TEENSY41 || BOARD_TEENSYMM config BUILD_OUTPUT_HEX bool diff --git a/boards/pjrc/teensy4/Kconfig.teensymm b/boards/pjrc/teensy4/Kconfig.teensymm new file mode 100644 index 00000000000..0e1f5da383c --- /dev/null +++ b/boards/pjrc/teensy4/Kconfig.teensymm @@ -0,0 +1,9 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_TEENSYMM + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/pjrc/teensy4/board.cmake b/boards/pjrc/teensy4/board.cmake index bd6ec2b59e0..b30dc4f7161 100644 --- a/boards/pjrc/teensy4/board.cmake +++ b/boards/pjrc/teensy4/board.cmake @@ -3,9 +3,11 @@ board_set_flasher_ifnset(teensy) if(CONFIG_BOARD_TEENSY40) -board_runner_args(teensy "--mcu=TEENSY40") + board_runner_args(teensy "--mcu=TEENSY40") +elseif(CONFIG_BOARD_TEENSYMM) + board_runner_args(teensy "--mcu=TEENSY_MICROMOD") else() -board_runner_args(teensy "--mcu=TEENSY41") + board_runner_args(teensy "--mcu=TEENSY41") endif() include(${ZEPHYR_BASE}/boards/common/teensy.board.cmake) diff --git a/boards/pjrc/teensy4/board.yml b/boards/pjrc/teensy4/board.yml index 0ae483ebc2c..2c9d0057467 100644 --- a/boards/pjrc/teensy4/board.yml +++ b/boards/pjrc/teensy4/board.yml @@ -9,3 +9,8 @@ boards: vendor: pjrc socs: - name: mimxrt1062 + - name: teensymm + full_name: Teensy MicroMod + vendor: pjrc + socs: + - name: mimxrt1062 diff --git a/boards/pjrc/teensy4/doc/img/teensymm.webp b/boards/pjrc/teensy4/doc/img/teensymm.webp new file mode 100644 index 00000000000..1a3267da237 Binary files /dev/null and b/boards/pjrc/teensy4/doc/img/teensymm.webp differ diff --git a/boards/pjrc/teensy4/doc/index.rst b/boards/pjrc/teensy4/doc/index.rst index 3517b1fb70f..6e767f37016 100644 --- a/boards/pjrc/teensy4/doc/index.rst +++ b/boards/pjrc/teensy4/doc/index.rst @@ -28,6 +28,14 @@ programming is done via the USB port. (Credit: https://www.pjrc.com) + .. group-tab:: Sparkfun Teensy Micromod + + .. figure:: img/teensymm.webp + :align: center + :alt: TEENSYMM + + (Credit: https://www.sparkfun.com) + Hardware ******** @@ -56,6 +64,17 @@ Hardware See the `Teensy 4.1 Website`_ for a complete hardware description. + .. group-tab:: Sparkfun Teensy Micromod + + - MIMXRT1062DVJ6A MCU (600 MHz, 1024 KB on-chip memory) + - 128 Mbit QSPI Flash + - User LED + - USB 2.0 host connector + - USB 2.0 OTG connector + - TF socket for SD card + + See the `Teensy Micromod Website`_ for a complete hardware description. + For more information, check the `i.MX RT1060 Datasheet`_. Supported Features @@ -188,7 +207,7 @@ Pin mappings from Teensy to MIMXRT1062 SoC. | 33 | EMC_07 | GPIO4_7 | +-----+------------+-------------------------------------+ -Only Teensy 4.0: +Only Teensy 4.0 and Teensy Micromod: +-----+------------+-------------------------------------+ | 34 | SD_B0_03 | GPIO3_15 | @@ -204,6 +223,22 @@ Only Teensy 4.0: | 39 | SD_B0_04 | GPIO3_16 | +-----+------------+-------------------------------------+ +Only Teensy Micromod + ++-----+------------+-------------------------------------+ +| 40 | B0_04 | GPIO2_4 / I2C2 SCL | ++-----+------------+-------------------------------------+ +| 41 | B0_05 | GPIO2_5 / I2C2 SDA | ++-----+------------+-------------------------------------+ +| 42 | B0_06 | GPIO2_6 | ++-----+------------+-------------------------------------+ +| 43 | B0_07 | GPIO2_7 | ++-----+------------+-------------------------------------+ +| 44 | B0_08 | GPIO2_8 / UART3 TX | ++-----+------------+-------------------------------------+ +| 45 | B0_09 | GPIO2_9 / UART3 RX | ++-----+------------+-------------------------------------+ + Only Teensy 4.1: +-----+------------+-------------------------------------+ @@ -221,8 +256,114 @@ Only Teensy 4.1: +-----+------------+-------------------------------------+ | 40 | AD_B1_04 | GPIO1_20 | +-----+------------+-------------------------------------+ -| 41 | AD_B1_05 | GPIO1_21 | -+-----+------------+-------------------------------------+ +| 41 | AD_B1_05 | GPIO1_21 / UART3_RX | ++-----+------------+-------------------------------------+ + +Pin mappings from Teensy Micromod pins to MIMXRT1062 SoC. + +Teensy Micromod only: + ++-----+-----+------+------------+-----------------------------------+ +|MMOD | MMC | Pin | Pad ID | Usage | ++=====+=====+======+============+===================================+ +| 8 | 16 | 27 | AD_B1_15 | / SPI3_SCK | ++-----+-----+------+------------+-----------------------------------+ +| 10 | 2 | 4 | EMC_06 | | ++-----+-----+------+------------+-----------------------------------+ +| 12 | | 18 | AD_B1_01 | / I2C1_SDA | ++-----+-----+------+------------+-----------------------------------+ +| 14 | | 19 | AD_B1_00 | / I2C1_SCL | ++-----+-----+------+------------+-----------------------------------+ +| 16 | 4 | 29 | EMC_31 | / UART7_TX | ++-----+-----+------+------------+-----------------------------------+ +| 17 | | 1 | AD_B0_02 | / UART6_TX / CAN2_TX | ++-----+-----+------+------------+-----------------------------------+ +| 18 | 3 | 5 | EMC_08 | | ++-----+-----+------+------------+-----------------------------------+ +| 19 | | 0 | AD_B0_03 | / UART6_RX / CAN2_RX | ++-----+-----+------+------------+-----------------------------------+ +| 20 | | 16 | AD_B1_07 | / UART3_RX / I2C3_SCL | ++-----+-----+------+------------+-----------------------------------+ +| 22 | | 17 | AD_B1_06 | / UART3_TX / I2C3_SDA | ++-----+-----+------+------------+-----------------------------------+ +| 32 | | 3 | EMC_05 | | ++-----+-----+------+------------+-----------------------------------+ +| 34 | 0 | 14 | AD_B1_02 | / UART2_TX | ++-----+-----+------+------------+-----------------------------------+ +| 38 | 1 | 15 | AD_B1_03 | / UART2_RX | ++-----+-----+------+------------+-----------------------------------+ +| 4 | | 28 | EMC_32 | / UART7_RX | ++-----+-----+------+------------+-----------------------------------+ +| 40 | 5 | 40 | B0_04 | / I2C2 SCL | ++-----+-----+------+------------+-----------------------------------+ +| 41 | | 30 | EMC_37 | / CAN3_RX | ++-----+-----+------+------------+-----------------------------------+ +| 42 | 6 | 41 | B0_05 | / I2C2 SDA | ++-----+-----+------+------------+-----------------------------------+ +| 43 | | 31 | EMC_36 | / CAN3_TX | ++-----+-----+------+------------+-----------------------------------+ +| 44 | 7 | 42 | B0_06 | | ++-----+-----+------+------------+-----------------------------------+ +| 46 | 8 | 43 | B0_07 | | ++-----+-----+------+------------+-----------------------------------+ +| 47 | | 2 | EMC_04 | | ++-----+-----+------+------------+-----------------------------------+ +| 48 | 9 | 44 | B0_08 | / UART3 TX | ++-----+-----+------+------------+-----------------------------------+ +| 49 | | 22 | AD_B1_08 | / CAN1_TX | ++-----+-----+------+------------+-----------------------------------+ +| 50 | | 21 | AD_B1_11 | / UART8_RX | ++-----+-----+------+------------+-----------------------------------+ +| 51 | | 25 | AD_B0_13 | / UART1_RX / I2C4_SDA | ++-----+-----+------+------------+-----------------------------------+ +| 52 | | 20 | AD_B1_10 | / UART8_TX | ++-----+-----+------+------------+-----------------------------------+ +| 53 | | 24 | AD_B0_12 | / UART1_TX / I2C4_SCL | ++-----+-----+------+------------+-----------------------------------+ +| 54 | | 8 | B1_00 | / UART4_TX | ++-----+-----+------+------------+-----------------------------------+ +| 55 | 17 | 10 | B0_00 | | ++-----+-----+------+------------+-----------------------------------+ +| 56 | | 7 | B1_01 | / UART4_RX | ++-----+-----+------+------------+-----------------------------------+ +| 57 | | 13 | B0_03 | / LED | ++-----+-----+------+------------+-----------------------------------+ +| 58 | | 23 | AD_B1_09 | / CAN1_RX | ++-----+-----+------+------------+-----------------------------------+ +| 59 | | 11 | B0_02 | | ++-----+-----+------+------------+-----------------------------------+ +| 60 | | 36 | SD_B0_01 | | ++-----+-----+------+------------+-----------------------------------+ +| 61 | | 12 | B0_01 | | ++-----+-----+------+------------+-----------------------------------+ +| 62 | | 37 | SD_B0_00 | | ++-----+-----+------+------------+-----------------------------------+ +| 63 | 15 | 33 | EMC_07 | | ++-----+-----+------+------------+-----------------------------------+ +| 64 | | 35 | SD_B0_02 | | ++-----+-----+------+------------+-----------------------------------+ +| 65 | 14 | 32 | B0_12 | | ++-----+-----+------+------------+-----------------------------------+ +| 66 | | 34 | SD_B0_03 | | ++-----+-----+------+------------+-----------------------------------+ +| 67 | 13 | 26 | AD_B1_14 | / SPI3_MOSI | ++-----+-----+------+------------+-----------------------------------+ +| 68 | | 38 | SD_B0_05 | | ++-----+-----+------+------------+-----------------------------------+ +| 69 | 12 | 9 | B0_11 | | ++-----+-----+------+------------+-----------------------------------+ +| 70 | | 39 | SD_B0_04 | | ++-----+-----+------+------------+-----------------------------------+ +| 71 | 11 | 6 | B0_10 | | ++-----+-----+------+------------+-----------------------------------+ +| 73 | 10 | 45 | B0_09 | / UART3 RX | ++-----+-----+------+------------+-----------------------------------+ + +MMOD = Physical Micromod pin number +MMC = Zephyr micromod_header connector pin number +Pin = Arduino Pin number +Pad ID = MIMXRT1062 pad id +Usage = Some usages of the pin Programming and Debugging ************************* @@ -230,9 +371,9 @@ Programming and Debugging Flashing ======== -Both the Teensy 4.0 and Teensy 4.1 ship with a dedicated bootloader chip, -which supports flashing using USB. This allows easy flashing of new images, -but does not support debugging the device. +The Teensy 4.0 and Teensy 4.1 and Micromod ship with a dedicated bootloader +chip, which supports flashing using USB. This allows easy flashing of new +images, but does not support debugging the device. #. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application. @@ -254,6 +395,14 @@ but does not support debugging the device. :goals: build :compact: + .. group-tab:: Teensy Micromod + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: teensymm + :goals: build + :compact: + #. Connect the board to your host computer using USB. #. Tap the reset button to enter bootloader mode. @@ -279,6 +428,15 @@ but does not support debugging the device. :goals: flash :compact: + .. group-tab:: Teensy Micromod + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: teensymm + :goals: flash + :compact: + + #. You should see the orange LED blink. Configuring a Console @@ -335,5 +493,8 @@ References .. _Teensy 4.1 Ethernet Kit: https://www.pjrc.com/store/ethernet_kit.html +.. _Teensy Micromod Website: + https://www.sparkfun.com/sparkfun-micromod-teensy-processor.html + .. _i.MX RT1060 Datasheet: https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf diff --git a/boards/pjrc/teensy4/teensy4-pinctrl.dtsi b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi index c12573cb6b3..16691972a41 100644 --- a/boards/pjrc/teensy4/teensy4-pinctrl.dtsi +++ b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi @@ -99,6 +99,19 @@ }; }; + /* LPI2C2 SCL, SDA on Teensy-Micromod-Pins 40/41 */ + pinmux_lpi2c2: pinmux_lpi2c2 { + group0 { + pinmux = <&iomuxc_gpio_b0_04_lpi2c2_scl>, + <&iomuxc_gpio_b0_05_lpi2c2_sda>; + drive-strength = "r0-6"; + drive-open-drain; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + input-enable; + }; + }; + /* LPI2C3 SCL, SDA on Teensy-Pins 16/17 */ pinmux_lpi2c3: pinmux_lpi2c3 { group0 { diff --git a/boards/pjrc/teensy4/teensy40.yaml b/boards/pjrc/teensy4/teensy40.yaml index a4908dc6abd..7adb0e38fe0 100644 --- a/boards/pjrc/teensy4/teensy40.yaml +++ b/boards/pjrc/teensy4/teensy40.yaml @@ -21,4 +21,3 @@ testing: ignore_tags: - net - posix -vendor: nxp diff --git a/boards/pjrc/teensy4/teensy41.yaml b/boards/pjrc/teensy4/teensy41.yaml index 659f6838ffa..78c71007aca 100644 --- a/boards/pjrc/teensy4/teensy41.yaml +++ b/boards/pjrc/teensy4/teensy41.yaml @@ -23,4 +23,3 @@ testing: ignore_tags: - net - posix -vendor: nxp diff --git a/boards/pjrc/teensy4/teensymm.dts b/boards/pjrc/teensy4/teensymm.dts new file mode 100644 index 00000000000..cfaff007a3e --- /dev/null +++ b/boards/pjrc/teensy4/teensymm.dts @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2020, Bernhard Kraemer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "teensy40.dts" + +/ { + model = "PJRC TEENSY Micromod board"; + + chosen { + zephyr,flash-controller = &w25q128jvxgim; + zephyr,flash = &w25q128jvxgim; + }; + + micromod_header: connector { + compatible = "sparkfun,micromod-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 18 0>, /* A0 MMOD 34 */ + <1 0 &gpio1 19 0>, /* A1 MMOD 38 */ + <2 0 &gpio4 6 0>, /* D0 MMOD 10 */ + <3 0 &gpio4 8 0>, /* D1/CAM_TRIG MMOD 18 */ + <4 0 &gpio4 31 0>, /* I2C_INT# MMOD 16 */ + <5 0 &gpio2 4 0>, /* G0/BUS0 MMOD 40 */ + <6 0 &gpio2 5 0>, /* G1/BUS1 MMOD 42 */ + <7 0 &gpio2 6 0>, /* G2/BUS2 MMOD 44 */ + <8 0 &gpio2 7 0>, /* G3/BUS3 MMOD 46 */ + <9 0 &gpio2 8 0>, /* G4/BUS4 MMOD 48 */ + <10 0 &gpio2 9 0>, /* G5/BUS5 MMOD 73 */ + <11 0 &gpio2 10 0>, /* G6/BUS6 MMOD 71 */ + <12 0 &gpio2 11 0>, /* G7/BUS7 MMOD 69 */ + <13 0 &gpio1 30 0>, /* G8 MMOD 67 */ + <14 0 &gpio2 12 0>, /* G9/ADC_D-/ MMOD 65 */ + <15 0 &gpio4 7 0>, /* G10/ADC_D+ MMOD 63 */ + <16 0 &gpio1 31 0>, /* G11/SWO MMOD 8 */ + <17 0 &gpio2 0 0>; /* SPI_CS MMOD 55 */ + }; +}; + +/delete-node/ &w25q16jvuxim; +&flexspi { + status = "okay"; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; + + /* WINBOND flash memory*/ + w25q128jvxgim: w25q128jvxgim@0 { + compatible = "nxp,imx-flexspi-nor"; + size = ; + reg = <0>; + spi-max-frequency = ; + status = "okay"; + jedec-id = [ef 70 18]; + + erase-block-size = <4096>; + write-block-size = <1>; + }; +}; + +&lpi2c2 { + pinctrl-0 = <&pinmux_lpi2c2>; + pinctrl-names = "default"; +}; + +&usdhc1 { + no-1-8-v; + pinctrl-0 = <&pinmux_usdhc1>; + pinctrl-1 = <&pinmux_usdhc1_slow>; + pinctrl-2 = <&pinmux_usdhc1_med>; + pinctrl-3 = <&pinmux_usdhc1_fast>; + pinctrl-names = "default", "slow", "med", "fast"; +}; + +// Sparkfun Micromod compatible pins +micromod_1_uart: &lpuart6 {}; +micromod_2_uart: &lpuart3 {}; +micromod_0_i2c: &lpi2c1 {}; +micromod_1_i2c: &lpi2c4 {}; +micromod_0_spi: &lpspi4 {}; diff --git a/boards/pjrc/teensy4/teensymm.yaml b/boards/pjrc/teensy4/teensymm.yaml new file mode 100644 index 00000000000..cd837fbfb32 --- /dev/null +++ b/boards/pjrc/teensy4/teensymm.yaml @@ -0,0 +1,25 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: teensymm +name: PJRC TEENSY_MICROMOD +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 768 +flash: 8192 +supported: + - counter + - gpio + - usb_device +testing: + ignore_tags: + - net + - posix +vendor: sparkfun diff --git a/boards/pjrc/teensy4/teensymm_defconfig b/boards/pjrc/teensy4/teensymm_defconfig new file mode 100644 index 00000000000..e73b48be0a3 --- /dev/null +++ b/boards/pjrc/teensy4/teensymm_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_DEVICE_CONFIGURATION_DATA=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000 +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml index d409cbf34b7..a6580f600cf 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml @@ -12,4 +12,5 @@ testing: ignore_tags: - net - bluetooth +ram: 4096 vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml index 0e568f34a79..eb98b653273 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml @@ -13,4 +13,5 @@ testing: ignore_tags: - net - bluetooth +ram: 4096 vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml index 819a8cf9249..580b5805823 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml @@ -12,4 +12,5 @@ testing: ignore_tags: - net - bluetooth +ram: 4096 vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml index 901d15dd34f..e7593464ba1 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml @@ -12,4 +12,5 @@ testing: ignore_tags: - net - bluetooth +ram: 4096 vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml index 928ec24190e..1032fd47b15 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml @@ -12,4 +12,5 @@ testing: ignore_tags: - net - bluetooth +ram: 4096 vendor: snps diff --git a/boards/qemu/nios2/Kconfig b/boards/qemu/nios2/Kconfig deleted file mode 100644 index 22dbe917954..00000000000 --- a/boards/qemu/nios2/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_NIOS2 - select QEMU_TARGET diff --git a/boards/qemu/nios2/Kconfig.defconfig b/boards/qemu/nios2/Kconfig.defconfig deleted file mode 100644 index 81494ff905e..00000000000 --- a/boards/qemu/nios2/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_NIOS2 - -config BUILD_OUTPUT_BIN - default n - -endif diff --git a/boards/qemu/nios2/Kconfig.qemu_nios2 b/boards/qemu/nios2/Kconfig.qemu_nios2 deleted file mode 100644 index 23292f07ffb..00000000000 --- a/boards/qemu/nios2/Kconfig.qemu_nios2 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_NIOS2 - select SOC_QEMU_NIOS2 diff --git a/boards/qemu/nios2/board.cmake b/boards/qemu/nios2/board.cmake deleted file mode 100644 index 9f9bf21124c..00000000000 --- a/boards/qemu/nios2/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} nios2) - -set(QEMU_FLAGS_${ARCH} - -machine altera_10m50_zephyr - -nographic - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/nios2/board.yml b/boards/qemu/nios2/board.yml deleted file mode 100644 index aae11848062..00000000000 --- a/boards/qemu/nios2/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: qemu_nios2 - full_name: QEMU Emulation for Altera Nios-II - vendor: altr - socs: - - name: qemu_nios2 diff --git a/boards/qemu/nios2/doc/index.rst b/boards/qemu/nios2/doc/index.rst deleted file mode 100644 index 235b9b41be4..00000000000 --- a/boards/qemu/nios2/doc/index.rst +++ /dev/null @@ -1,127 +0,0 @@ -.. zephyr:board:: qemu_nios2 - -Overview -******** - -This board configuration will use QEMU to emulate the Altera MAX 10 platform. - -This configuration provides support for an Altera Nios-II CPU and these devices: - -* Internal Interrupt Controller -* Altera Avalon Timer -* NS16550 UART - -.. note:: - This board configuration makes no claims about its suitability for use - with an actual ti_lm3s6965 hardware system, or any other hardware system. - -Hardware -******** -Supported Features -================== - -The following hardware features are supported: - -+--------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+==============+============+======================+ -| IIC | on-chip | Internal interrupt | -| | | controller | -+--------------+------------+----------------------+ -| NS16550 | on-chip | serial port | -| UART | | | -+--------------+------------+----------------------+ -| TIMER | on-chip | system clock | -+--------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 50 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART0. - -If SLIP networking is enabled (see below), an additional serial port will be -used for it. - -Known Problems or Limitations -============================== - -The following platform features are unsupported: - -* Memory protection through optional MPU. However, using a XIP kernel - effectively provides TEXT/RODATA write protection in ROM. -* Writing to the hardware's flash memory -* Serial port in Direct Memory Access (DMA) mode -* Serial Peripheral Interface (SPI) flash -* General-Purpose Input/Output (GPIO) -* Inter-Integrated Circuit (I2C) -* Ethernet - - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Use this configuration to run basic Zephyr applications and kernel tests in the QEMU -emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_nios2 - :goals: run - -This will build an image with the synchronization sample app, boot it using -QEMU, and display the following console output: - -.. code-block:: console - - ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 ***** - threadA: Hello World from arm! - threadB: Hello World from arm! - threadA: Hello World from arm! - threadB: Hello World from arm! - threadA: Hello World from arm! - threadB: Hello World from arm! - threadA: Hello World from arm! - threadB: Hello World from arm! - threadA: Hello World from arm! - threadB: Hello World from arm! - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. - -Networking -========== - -The board supports SLIP networking over an emulated serial port -(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in -:ref:`networking_with_qemu`. - -References -********** - -* `CPU Documentation `_ -* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ -* `Embedded Peripherals IP User Guide `_ -* `MAX 10 FPGA Configuration User Guide `_ -* `MAX 10 FPGA Development Kit User Guide `_ -* `Nios II Command-Line Tools `_ -* `Quartus II Scripting Reference Manual `_ - - -.. _Altera Lite Distribution: http://dl.altera.com/?edition=lite diff --git a/boards/qemu/nios2/qemu_nios2.dts b/boards/qemu/nios2/qemu_nios2.dts deleted file mode 100644 index 4d9f14130b5..00000000000 --- a/boards/qemu/nios2/qemu_nios2.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include - -/ { - model = "qemu_nios2"; - compatible = "qemu,nios2"; - - aliases { - uart-0 = &jtag_uart; - uart-1 = &ns16550_uart; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &ns16550_uart; - zephyr,shell-uart = &ns16550_uart; - }; -}; - -&jtag_uart { - status = "okay"; - current-speed = <115200>; -}; - -&ns16550_uart { - status = "okay"; - current-speed = <115200>; -}; diff --git a/boards/qemu/nios2/qemu_nios2.yaml b/boards/qemu/nios2/qemu_nios2.yaml deleted file mode 100644 index 816c280b5a0..00000000000 --- a/boards/qemu/nios2/qemu_nios2.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_nios2 -name: QEMU Emulation for NIOS II -type: qemu -simulation: - - name: qemu -arch: nios2 -ram: 128 -flash: 128 -toolchain: - - zephyr -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: qemu diff --git a/boards/qemu/nios2/qemu_nios2_defconfig b/boards/qemu/nios2/qemu_nios2_defconfig deleted file mode 100644 index feda1075277..00000000000 --- a/boards/qemu/nios2/qemu_nios2_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_HAS_ALTERA_HAL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_INCLUDE_RESET_VECTOR=n -CONFIG_EXTRA_EXCEPTION_INFO=y -CONFIG_QEMU_ICOUNT_SHIFT=4 diff --git a/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip b/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip index ac31b7857eb..69842cdb183 100644 --- a/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip +++ b/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_QEMU_RISCV32_XIP - select SOC_SIFIVE_FREEDOM_FE310 + select SOC_SIFIVE_FREEDOM_FE310_G002 diff --git a/boards/qemu/riscv32_xip/board.yml b/boards/qemu/riscv32_xip/board.yml index 4c43b4d73c8..17c2d4f1527 100644 --- a/boards/qemu/riscv32_xip/board.yml +++ b/boards/qemu/riscv32_xip/board.yml @@ -3,4 +3,4 @@ board: full_name: QEMU Emulation for RISCV32 XIP vendor: qemu socs: - - name: fe310 + - name: fe310_g002 diff --git a/boards/qemu/rx/Kconfig b/boards/qemu/rx/Kconfig new file mode 100644 index 00000000000..7af558e1bc1 --- /dev/null +++ b/boards/qemu/rx/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RX + select QEMU_TARGET diff --git a/boards/qemu/rx/Kconfig.deconfig b/boards/qemu/rx/Kconfig.deconfig new file mode 100644 index 00000000000..ad7e4d21285 --- /dev/null +++ b/boards/qemu/rx/Kconfig.deconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RX + +config BUILD_OUTPUT_BIN + default n + +# DWT is not properly emulated in QEMU +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE +endchoice + +endif # BOARD_QEMU_RX diff --git a/boards/qemu/rx/Kconfig.qemu_rx b/boards/qemu/rx/Kconfig.qemu_rx new file mode 100644 index 00000000000..625df6b783c --- /dev/null +++ b/boards/qemu/rx/Kconfig.qemu_rx @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RX + select SOC_R5F562N8 diff --git a/boards/qemu/rx/board.cmake b/boards/qemu/rx/board.cmake new file mode 100644 index 00000000000..7f0dd698339 --- /dev/null +++ b/boards/qemu/rx/board.cmake @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_MACH gdbsim-r5f562n8) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine ${QEMU_MACH} + ) + +if(CONFIG_XIP) + set(QEMU_KERNEL_OPTION + -bios ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin + ) +endif() + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/rx/board.yml b/boards/qemu/rx/board.yml new file mode 100644 index 00000000000..2ecd19f7518 --- /dev/null +++ b/boards/qemu/rx/board.yml @@ -0,0 +1,6 @@ +board: + name: qemu_rx + full_name: QEMU Emulation for Renesas RX + vendor: renesas + socs: + - name: r5f562n8 diff --git a/boards/qemu/rx/doc/index.rst b/boards/qemu/rx/doc/index.rst new file mode 100644 index 00000000000..ac38e5906ce --- /dev/null +++ b/boards/qemu/rx/doc/index.rst @@ -0,0 +1,86 @@ +.. zephyr:board:: qemu_rx + +Overview +******** + +This board configuration will use QEMU to emulate the Renesas RXv1 platform. + +This configuration provides support for the R5F562N8 MCU and below devices: + +* On-chip memory (ROM 512KB, RAM 96KB) +* Interrupt Control Unit (ICUa) +* Compare Match Timer x 2CH (CMT0,1) +* Serial Communication Interface x 1CH (SCI0) + +Hardware +******** + +Supported Features +================== + +The following hardware features are supported: + ++----------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++================+============+======================+ +| ICU | on-chip | interrupt controller | ++----------------+------------+----------------------+ +| CMT timer | on-chip | system clock | ++----------------+------------+----------------------+ +| SCI UART | on-chip | serial port | ++----------------+------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 6 MHz generated by the CMT timer. + +Serial Port +----------- + +This board configuration uses a single serial communication channel +on the SCI UART channel 0. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Use this configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_rx + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-3157-gb30f8b6a7327 *** + thread_a: Hello World from cpu 0 on qemu_rx! + thread_b: Hello World from cpu 0 on qemu_rx! + thread_a: Hello World from cpu 0 on qemu_rx! + thread_b: Hello World from cpu 0 on qemu_rx! + thread_a: Hello World from cpu 0 on qemu_rx! + thread_b: Hello World from cpu 0 on qemu_rx! + thread_a: Hello World from cpu 0 on qemu_rx! + thread_b: Hello World from cpu 0 on qemu_rx! + thread_a: Hello World from cpu 0 on qemu_rx! + thread_b: Hello World from cpu 0 on qemu_rx! + + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + + +References +********** + +https://www.qemu.org/ diff --git a/boards/qemu/rx/qemu_rx.dts b/boards/qemu/rx/qemu_rx.dts new file mode 100644 index 00000000000..4b2f7672769 --- /dev/null +++ b/boards/qemu/rx/qemu_rx.dts @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Renesas QEMU"; + compatible = "qemu,rx","renesas,rxv1"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + aliases { + serial0 = &uart0; + }; +}; + +&sci0 { + status = "okay"; + + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + div = <2>; + mul = ; + status = "okay"; +}; + +&cmt { + clock-frequency = <6000000>; + status = "okay"; +}; diff --git a/boards/qemu/rx/qemu_rx.yaml b/boards/qemu/rx/qemu_rx.yaml new file mode 100644 index 00000000000..86c6513f138 --- /dev/null +++ b/boards/qemu/rx/qemu_rx.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: qemu_rx +name: QEMU Emulation for Renesas RX +type: qemu +simulation: + - name: qemu +arch: rx +toolchain: + - cross-compile +supported: + - serial +ram: 96 +flash: 512 diff --git a/boards/qemu/rx/qemu_rx_defconfig b/boards/qemu/rx/qemu_rx_defconfig new file mode 100644 index 00000000000..ebf97f4f755 --- /dev/null +++ b/boards/qemu/rx/qemu_rx_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_QEMU_ICOUNT_SHIFT=5 +CONFIG_QEMU_ICOUNT=y diff --git a/boards/qemu/x86/board.yml b/boards/qemu/x86/board.yml index 7e0fa76a043..cfd84976dae 100644 --- a/boards/qemu/x86/board.yml +++ b/boards/qemu/x86/board.yml @@ -2,6 +2,7 @@ boards: - name: qemu_x86 full_name: QEMU Emulation for X86 + vendor: intel socs: - name: atom variants: @@ -13,11 +14,13 @@ boards: - name: qemu_x86_lakemont full_name: QEMU Emulation for X86 / Lakemont CPU + vendor: intel socs: - name: lakemont - name: qemu_x86_64 full_name: QEMU Emulation for X86 64bit + vendor: intel socs: - name: atom variants: @@ -25,5 +28,6 @@ boards: - name: qemu_x86_tiny full_name: QEMU Emulation for X86 Minimal Configuration + vendor: intel socs: - name: atom diff --git a/boards/qemu/x86/qemu_x86_64.yaml b/boards/qemu/x86/qemu_x86_64.yaml index 3fa3fd18a3c..77641947730 100644 --- a/boards/qemu/x86/qemu_x86_64.yaml +++ b/boards/qemu/x86/qemu_x86_64.yaml @@ -17,4 +17,5 @@ testing: ignore_tags: - net - bluetooth +ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml index c776a903163..221f5665891 100644 --- a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml @@ -13,6 +13,8 @@ testing: only_tags: - kernel - userspace + - llext ignore_tags: - benchmark +ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml index 83a396d06db..5a468d8d6bb 100644 --- a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml +++ b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml @@ -11,6 +11,8 @@ testing: only_tags: - kernel - userspace + - llext ignore_tags: - benchmark +ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nopae.yaml b/boards/qemu/x86/qemu_x86_atom_nopae.yaml index dfb264fb474..b1644407fff 100644 --- a/boards/qemu/x86/qemu_x86_atom_nopae.yaml +++ b/boards/qemu/x86/qemu_x86_atom_nopae.yaml @@ -11,6 +11,8 @@ testing: only_tags: - kernel - userspace + - llext ignore_tags: - benchmark +ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_virt.yaml b/boards/qemu/x86/qemu_x86_atom_virt.yaml index 8794d17df9f..156afae475f 100644 --- a/boards/qemu/x86/qemu_x86_atom_virt.yaml +++ b/boards/qemu/x86/qemu_x86_atom_virt.yaml @@ -11,6 +11,8 @@ testing: only_tags: - kernel - userspace + - llext ignore_tags: - benchmark +ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_xip.yaml b/boards/qemu/x86/qemu_x86_atom_xip.yaml index 6607c68681f..f498803c3de 100644 --- a/boards/qemu/x86/qemu_x86_atom_xip.yaml +++ b/boards/qemu/x86/qemu_x86_atom_xip.yaml @@ -10,4 +10,6 @@ testing: default: true only_tags: - xip + - llext +ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_lakemont.yaml b/boards/qemu/x86/qemu_x86_lakemont.yaml index 3d6103d9404..0a00089884f 100644 --- a/boards/qemu/x86/qemu_x86_lakemont.yaml +++ b/boards/qemu/x86/qemu_x86_lakemont.yaml @@ -13,4 +13,5 @@ testing: - kernel ignore_tags: - benchmark +ram: 3000 vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_tiny.yaml b/boards/qemu/x86/qemu_x86_tiny.yaml index 29197ecd6d8..6699515cdc1 100644 --- a/boards/qemu/x86/qemu_x86_tiny.yaml +++ b/boards/qemu/x86/qemu_x86_tiny.yaml @@ -11,6 +11,8 @@ testing: only_tags: - kernel - userspace + - llext ignore_tags: - benchmark +ram: 256 vendor: qemu diff --git a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml index 9285fa04e9e..32a806f4315 100644 --- a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml +++ b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml @@ -4,6 +4,8 @@ type: qemu simulation: - name: qemu arch: xtensa +toolchain: + - zephyr testing: default: true ignore_tags: diff --git a/boards/rakwireless/rak3172/board.cmake b/boards/rakwireless/rak3172/board.cmake index 8d07af62873..37a3c858d04 100644 --- a/boards/rakwireless/rak3172/board.cmake +++ b/boards/rakwireless/rak3172/board.cmake @@ -4,6 +4,8 @@ board_runner_args(pyocd "--target=stm32wle5ccux") board_runner_args(pyocd "--flash-opt=-O cmsis_dap.limit_packets=1") board_runner_args(jlink "--device=STM32WLE5CC" "--speed=4000" "--reset-after-load") +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/rakwireless/rak3172/rak3172.dts b/boards/rakwireless/rak3172/rak3172.dts index afd16df61c0..7685fa66af0 100644 --- a/boards/rakwireless/rak3172/rak3172.dts +++ b/boards/rakwireless/rak3172/rak3172.dts @@ -6,6 +6,7 @@ /dts-v1/; #include #include +#include / { model = "RAKWireless RAK3172 WisDuo LPWAN Module with a STM32WLE5CC SoC"; @@ -42,20 +43,16 @@ &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, - <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; - status = "okay"; -}; - -&clk_lsi { + <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; status = "okay"; }; &pll { div-m = <1>; - mul-n = <6>; + mul-n = <3>; div-r = <2>; div-q = <2>; - clocks = <&clk_hsi>; + clocks = <&clk_hse>; status = "okay"; }; @@ -98,7 +95,7 @@ &rtc { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>, - <&rcc STM32_SRC_LSI RTC_SEL(2)>; + <&rcc STM32_SRC_LSE RTC_SEL(1)>; status = "okay"; }; @@ -114,26 +111,6 @@ status = "okay"; }; -&clk_lse { - clock-frequency = <32768>; -}; - -&clk_hsi { - status = "okay"; -}; - -&subghzspi { - status = "okay"; - - lora: radio@0 { - status = "okay"; - tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; /* FE_CTRL1 */ - rx-enable-gpios = <&gpiob 8 GPIO_ACTIVE_LOW>; /* FE_CTRL2 */ - power-amplifier-output = "rfo-lp"; - rfo-lp-max-power = <14>; - }; -}; - &flash0 { partitions { compatible = "fixed-partitions"; diff --git a/boards/raspberrypi/rpi_5/rpi_5.dts b/boards/raspberrypi/rpi_5/rpi_5.dts index 3f942d4e6f5..339adba011c 100644 --- a/boards/raspberrypi/rpi_5/rpi_5.dts +++ b/boards/raspberrypi/rpi_5/rpi_5.dts @@ -24,6 +24,7 @@ zephyr,console = &uart10; zephyr,shell-uart = &uart10; zephyr,pcie-controller = &pcie1; + zephyr,entropy = &rng; }; leds { diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst index b82b484f4f2..ea279a93192 100644 --- a/boards/raspberrypi/rpi_pico/doc/index.rst +++ b/boards/raspberrypi/rpi_pico/doc/index.rst @@ -130,20 +130,11 @@ Raspberry Pi Pico's PIO is a programmable chip that can implement a variety of p - :kconfig:option:`CONFIG_LED_STRIP` - :dtcompatible:`worldsemi,ws2812-rpi_pico-pio` -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``rpi_pico`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - System requirements -=================== +******************* Prerequisites for the Pico W ----------------------------- +============================ Building for the Raspberry Pi Pico W requires the AIROC binary blobs provided by Infineon. Run the command below to retrieve those files: @@ -156,26 +147,23 @@ provided by Infineon. Run the command below to retrieve those files: It is recommended running the command above after :file:`west update`. -Debug Probe and Host Tools --------------------------- +.. _rpi_pico_programming_and_debugging: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``rpi_pico`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). Several debugging tools support the Raspberry Pi Pico. The `Raspberry Pi Debug Probe`_ is an easy-to-obtain CMSIS-DAP adapter officially provided by the Raspberry Pi Foundation, making it a convenient choice for debugging ``rpi_pico``. +It can be used with ``openocd`` or ``pyocd``. -It can be used with - -- :ref:`openocd-debug-host-tools` -- :ref:`pyocd-debug-host-tools` - -OpenOCD is the default for ``rpi_pico``. - -- `SEGGER J-Link`_ -- `Black Magic Debug Probe `_ - -can also be used. -These are used with dedicated probes. Flashing ======== @@ -183,20 +171,6 @@ Flashing The ``rpi_pico`` can flash with Zephyr's standard method. See also :ref:`Building, Flashing and Debugging`. -Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: rpi_pico - :goals: build - -.. code-block:: console - - west flash --runner jlink - - -.. _rpi_pico_flashing_using_openocd: - Using OpenOCD ------------- @@ -216,13 +190,14 @@ Here is an example of building and flashing the :zephyr:code-sample:`blinky` app :zephyr-app: samples/basic/blinky :board: rpi_pico :goals: build flash - :gen-args: -DOPENOCD=/usr/local/bin/openocd -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap + :gen-args: -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap + :flash-args: --openocd /usr/local/bin/openocd -Set the CMake option **OPENOCD** to :file:`/usr/local/bin/openocd`. This should work +Set the flash runner option **--openocd** to :file:`/usr/local/bin/openocd`. This should work with the OpenOCD that was installed with the default configuration. This configuration also works with an environment that is set up by the `pico_setup.sh`_ script. -**RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. +In this sample, **RPI_PICO_DEBUG_ADAPTER** specifies which debug adapter is used for debugging. If **RPI_PICO_DEBUG_ADAPTER** was not set, ``cmsis-dap`` is used by default. The ``raspberrypi-swd`` and ``jlink`` are verified to work. @@ -236,7 +211,24 @@ The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from **RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as ``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter. -.. _rpi_pico_flashing_using_uf2: + +Using JLink or other supported tools +------------------------------------ + +You can Flash with a `SEGGER J-Link`_ debug probe as described in +:ref:`Building, Flashing and Debugging `. + +Here is an example of building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: rpi_pico + :goals: build flash + :flash-args: --runner jlink + +You can also use other supported tools, such as `Black Magic Probe`_, +by changing the ``-- runner`` option. + Using UF2 --------- @@ -244,8 +236,15 @@ Using UF2 If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with a UF2 file. By default, building an app for this board will generate a :file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` -button pressed, it will appear on the host as a mass storage device. The -UF2 file should be drag-and-dropped to the device, which will flash the Pico. +button pressed, it will appear on the host as a mass storage device. +Run the following command, or drag-and-drop the uf2 file to the device, +which will flash the Pico. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: rpi_pico + :goals: flash + :flash-args: --runner uf2 Debugging ========= @@ -260,15 +259,12 @@ the `Raspberry Pi Debug Probe`_. :board: rpi_pico :maybe-skip-config: :goals: debug - :gen-args: -DOPENOCD=/usr/local/bin/openocd -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap + :debug-args: --openocd /usr/local/bin/openocd The default debugging tool is ``openocd``. If you use a different tool, specify it with the ``--runner``, such as ``jlink``. -If you use OpenOCD, see also the description about flashing :ref:`rpi_pico_flashing_using_uf2` -for more information. - .. target-notes:: @@ -293,5 +289,5 @@ for more information. .. _SEGGER J-Link: https://www.segger.com/products/debug-probes/j-link/ -.. _Black Magic Debug: +.. _Black Magic Probe: https://black-magic.org/ diff --git a/boards/raspberrypi/rpi_pico2/doc/index.rst b/boards/raspberrypi/rpi_pico2/doc/index.rst index a6ed699a820..612497a0b3c 100644 --- a/boards/raspberrypi/rpi_pico2/doc/index.rst +++ b/boards/raspberrypi/rpi_pico2/doc/index.rst @@ -42,8 +42,16 @@ Programming and Debugging .. zephyr:board-supported-runners:: -As with the Pico 1, the SWD interface can be used to program and debug the -device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . +The overall explanation regarding flashing and debugging is the same as or :zephyr:board:`rpi_pico`. +See :ref:`rpi_pico_programming_and_debugging` in :zephyr:board:`rpi_pico` documentation. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. + +Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: rpi_pico2/rp2350a/m33 + :goals: build flash + :flash-args: --openocd /usr/local/bin/openocd References ********** diff --git a/boards/raytac/an54l15q_db/Kconfig b/boards/raytac/an54l15q_db/Kconfig new file mode 100644 index 00000000000..69aa54f3220 --- /dev/null +++ b/boards/raytac/an54l15q_db/Kconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +# Raytac AN54L15Q-DB board configuration + +if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS + +DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc) + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the flash region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral-specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity) + help + This defines the RAM region size from the TrustZone perspective. + It is used when configuring the TrustZone and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TrustZone without depending + on peripheral specific symbols. + +endif #BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS diff --git a/boards/raytac/an54l15q_db/Kconfig.defconfig b/boards/raytac/an54l15q_db/Kconfig.defconfig new file mode 100644 index 00000000000..82d59ecdbe3 --- /dev/null +++ b/boards/raytac/an54l15q_db/Kconfig.defconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +endif # BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP + +if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS + +config BT_CTLR + default BT + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y + +endif # BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS diff --git a/boards/raytac/an54l15q_db/Kconfig.raytac_an54l15q_db b/boards/raytac/an54l15q_db/Kconfig.raytac_an54l15q_db new file mode 100644 index 00000000000..58f42ef31d9 --- /dev/null +++ b/boards/raytac/an54l15q_db/Kconfig.raytac_an54l15q_db @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_AN54L15Q_DB + select SOC_NRF54L15_CPUAPP if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP || BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS + select SOC_NRF54L15_CPUFLPR if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUFLPR || \ + BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUFLPR_XIP diff --git a/boards/raytac/an54l15q_db/board.cmake b/boards/raytac/an54l15q_db/board.cmake new file mode 100644 index 00000000000..368bcc9d2fe --- /dev/null +++ b/boards/raytac/an54l15q_db/board.cmake @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54L15_CPUAPP) + board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") +elseif (CONFIG_SOC_NRF54L15_CPUFLPR) + board_runner_args(jlink "--device=nRF54L15_RV32") +endif() + +if(BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/raytac/an54l15q_db/board.yml b/boards/raytac/an54l15q_db/board.yml new file mode 100644 index 00000000000..08d0e2398e7 --- /dev/null +++ b/boards/raytac/an54l15q_db/board.yml @@ -0,0 +1,45 @@ +board: + name: raytac_an54l15q_db + full_name: AN54L15Q-DB + vendor: raytac + socs: + - name: nrf54l15 + variants: + - name: xip + cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp +runners: + run_once: + '--recover': + - runners: + - nrfjprog + - nrfutil + run: first + groups: + - boards: + - raytac_an54l15q_db/nrf54l15/cpuapp + - raytac_an54l15q_db/nrf54l15/cpuflpr + - raytac_an54l15q_db/nrf54l15/cpuflpr/xip + '--erase': + - runners: + - nrfjprog + - jlink + - nrfutil + run: first + groups: + - boards: + - raytac_an54l15q_db/nrf54l15/cpuapp + - raytac_an54l15q_db/nrf54l15/cpuflpr + - raytac_an54l15q_db/nrf54l15/cpuflpr/xip + '--reset': + - runners: + - nrfjprog + - jlink + - nrfutil + run: last + groups: + - boards: + - raytac_an54l15q_db/nrf54l15/cpuapp + - raytac_an54l15q_db/nrf54l15/cpuflpr + - raytac_an54l15q_db/nrf54l15/cpuflpr/xip diff --git a/boards/raytac/an54l15q_db/doc/img/raytac_an54l15q_db.webp b/boards/raytac/an54l15q_db/doc/img/raytac_an54l15q_db.webp new file mode 100644 index 00000000000..35ecd0b4e90 Binary files /dev/null and b/boards/raytac/an54l15q_db/doc/img/raytac_an54l15q_db.webp differ diff --git a/boards/raytac/an54l15q_db/doc/index.rst b/boards/raytac/an54l15q_db/doc/index.rst new file mode 100644 index 00000000000..415b8ef51df --- /dev/null +++ b/boards/raytac/an54l15q_db/doc/index.rst @@ -0,0 +1,150 @@ +.. zephyr:board:: raytac_an54l15q_db + +Overview +******** + +The Raytac AN54L15Q-DB demonstration board is a development board based on the Raytac AN54L15Q module. +It uses the Nordic Semiconductor nRF54L15 SoC solution. The idea is to connect all the module's pins +to a 2.54mm pin header. It can easily open the verification module functions and connect with other +peripheral devices and sensor pins, making it a useful tool for early software development. + +.. note:: + You can find more information about the nRF54L15 SoC on the `nRF54L15 website`_. + For the nRF54L15 technical documentation and other resources (such as + SoC Datasheet), see the `nRF54L15 documentation`_ page. + +Hardware +******** + +The Raytac AN54L15Q-DB has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +- Module Demo Board built by AN54L15Q +- Nordic nRF54L15 SoC Solution +- A recommended 3rd-party module by Nordic Semiconductor. +- Intended for Bluetooth specification BT6 +- Intended for FCC, IC, CE, Telec (MIC), KC, SRRC, NCC, RCM, WPC +- 128 MHz ARM® Cortex™-M33 processor with TrustZone® technology +- 128 MHz RISC-V coprocessor with TrustZone® technology +- 1.5MB Flash Memory / 256KB RAM +- RoHS & Reach Compliant. +- 31 GPIO +- Chip Antenna +- Interfaces: SPI, UART, I2C, I2S, PDM, PWM, ADC, and NFC +- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, + ANT+, Zigbee, Thread (802.15.4), and Matter ultra low-power wireless applications. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +LED +--- + +* LED0 (green) = P2.09 +* LED1 (green) = P1.10 +* LED2 (green) = P2.07 +* LED3 (green) = P1.14 + +Push buttons +------------ + +* BUTTON1 = SW0 = P1.13 +* BUTTON2 = SW1 = P1.09 +* BUTTON3 = SW2 = P1.08 +* BUTTON4 = SW3 = P0.04 + +UART +---- +* RX = P1.05 +* TX = P1.04 +* RTS = P1.06 +* CTS = P1.07 + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``raytac_an54l15q_db/nrf54l15/cpuapp`` board can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +.. note:: + The ``raytac_an54l15q_db`` board does not have an on-board J-Link debug IC; + Use the Debug out connector of the nRF5340-DK or nRF54L15-DK to connect to the J1 + or J9 SWD connector, and use SEGGER J-Link OB IF to debug. + +Flashing +======== + +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` +application. + +.. warning:: + + When programming the device, you might get an error similar to the following message:: + + ERROR: The operation attempted is unavailable due to readback protection in + ERROR: your device. Please use --recover to unlock the device. + + This error occurs when readback protection is enabled. + To disable the readback protection, you must *recover* your device. + + Enter the following command to recover the core:: + + west flash --recover + + The ``--recover`` command erases the flash memory and then writes a small binary into + the recovered flash memory. + This binary prevents the readback protection from enabling itself again after a pin + reset or power cycle. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the Raytac AN54L15Q-DB, complete the following steps: + +First, connect the Raytac AN54L15Q-DB's J10 connector to you computer using a USB to TTL +converter. Then run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the USB to TTL converter +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: raytac_an54l15q_db/nrf54l15/cpuapp + :goals: build flash + +References +********** + +.. target-notes:: + +.. _Raytac AN54L15Q-DB website: + https://www.raytac.com/product/ins.php?index_id=139 +.. _Raytac AN54L15Q-DB Specification: + https://www.raytac.com/download/index.php?index_id=60 +.. _Raytac AN54L15Q-DB Schematic: + https://www.raytac.com/upload/catalog_b/8b5e364600a9cc8c53a869733e97f07e.jpg +.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15 +.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_common.dtsi b/boards/raytac/an54l15q_db/raytac_an54l15q_db_common.dtsi new file mode 100644 index 00000000000..447143c6a8a --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_common.dtsi @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Raytac Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "raytac_an54l15q_db_pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + /* + * PWM signal can be exposed on GPIO pin only within same domain. + * There is only one domain which contains both PWM and GPIO: + * PWM20/21/22 and GPIO Port P1. + * Only LEDs connected to P1 can work with PWM, for example LED1. + */ + + pwm_led1: pwm_led_1 { + pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm20_default>; + pinctrl-1 = <&pwm20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +/* Get a node label for wi-fi spi to use in shield files */ +wifi_spi: &spi22 {}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_cpuapp_common.dtsi b/boards/raytac/an54l15q_db/raytac_an54l15q_db_cpuapp_common.dtsi new file mode 100644 index 00000000000..952a8f6d7ae --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_cpuapp_common.dtsi @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2024 Raytac Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include "raytac_an54l15q_db_common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,ieee802154 = &ieee802154; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15500>; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15000>; +}; + +®ulators { + status = "okay"; +}; + +&vregmain { + status = "okay"; + regulator-initial-mode = ; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; + + mx25r64: mx25r6435f@0 { + compatible = "jedec,spi-nor"; + status = "okay"; + reg = <0>; + spi-max-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +&adc { + status = "okay"; +}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.dts b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.dts new file mode 100644 index 00000000000..d9362a6ddb0 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.dts @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2024 Raytac Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "raytac_an54l15q_db_cpuapp_common.dtsi" + +/ { + compatible = "raytac,an54l15q_db_nrf54l15-cpuapp"; + + model = "Raytac AN54L15Q-DB nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(324)>; + }; + + slot0_ns_partition: partition@61000 { + label = "image-0-nonsecure"; + reg = <0x61000 DT_SIZE_K(324)>; + }; + + slot1_partition: partition@b2000 { + label = "image-1"; + reg = <0xb2000 DT_SIZE_K(324)>; + }; + + slot1_ns_partition: partition@103000 { + label = "image-1-nonsecure"; + reg = <0x103000 DT_SIZE_K(324)>; + }; + + /* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */ + storage_partition: partition@15c000 { + label = "storage"; + reg = <0x15c000 DT_SIZE_K(36)>; + }; + }; +}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.yaml new file mode 100644 index 00000000000..4e3b9067475 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp.yaml @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2024 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +identifier: raytac_an54l15q_db/nrf54l15/cpuapp +name: Raytac-AN54L15Q-DB-nRF54l15-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 188 +flash: 324 +supported: + - adc + - counter + - gpio + - i2c + - pwm + - retained_mem + - spi + - watchdog + - i2s diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_defconfig b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_defconfig new file mode 100644 index 00000000000..299496280d2 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2024 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.dts b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.dts new file mode 100644 index 00000000000..db7a01aead8 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.dts @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * Copyright (c) 2024 Raytac Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include +#include "raytac_an54l15q_db_cpuapp_common.dtsi" + +/ { + compatible = "raytac,raytac_an54l15q_db_nrf54l15-cpuapp"; + model = "Raytac AN54L15Q-DB nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_ns_partition; + zephyr,sram = &sram0_ns; + zephyr,entropy = &psa_rng; + }; + + /delete-node/ rng; + + psa_rng: psa-rng { + status = "okay"; + }; +}; + +/ { + /* + * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support + * - Lowest 80 kB SRAM allocated to Secure image (sram0_s). + * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns). + * + * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for + * the FLPR MCU. + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + reg = <0x20000000 DT_SIZE_K(80)>; + }; + + sram0_ns: image_ns@20014000 { + /* Non-Secure image memory */ + reg = <0x20014000 DT_SIZE_K(80)>; + }; + }; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the + * last 96kB are reserved for the FLPR MCU. + * + * This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0000000 DT_SIZE_K(512)>; + }; + + tfm_ps_partition: partition@80000 { + label = "tfm-ps"; + reg = <0x00080000 DT_SIZE_K(16)>; + }; + + tfm_its_partition: partition@84000 { + label = "tfm-its"; + reg = <0x00084000 DT_SIZE_K(16)>; + }; + + tfm_otp_partition: partition@88000 { + label = "tfm-otp"; + reg = <0x00088000 DT_SIZE_K(8)>; + }; + + slot0_ns_partition: partition@8A000 { + label = "image-0-nonsecure"; + reg = <0x0008A000 DT_SIZE_K(844)>; + }; + + storage_partition: partition@15D000 { + label = "storage"; + reg = <0x00015D000 DT_SIZE_K(32)>; + }; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml new file mode 100644 index 00000000000..11ee50ba277 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: raytac_an54l15q_db/nrf54l15/cpuapp/ns +name: Raytac-AN54L15Q-DB-nRF54l15-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +ram: 256 +flash: 1524 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s +vendor: raytac +sysbuild: true diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns_defconfig b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns_defconfig new file mode 100644 index 00000000000..866a03cd868 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +# Disable TFM BL2 since it is not supported +CONFIG_TFM_BL2=n + +# Support for silence logging is not supported at the moment +# Tracked by: NCSDK-31930 +CONFIG_TFM_LOG_LEVEL_SILENCE=n + +# The oscillators are configured as secure and cannot be configured +# from the non secure application directly. This needs to be set +# otherwise nrfx will try to configure them, resulting in a bus +# fault. +CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.dts b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.dts new file mode 100644 index 00000000000..d7c1a0cbbe0 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.dts @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Raytac Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "raytac_an54l15q_db_common.dtsi" + +/ { + model = "Raytac AN54L15Q-DB nRF54L15 FLPR MCU"; + compatible = "raytac,raytac_an54l15q_db_nrf54l15-cpuflpr"; + + chosen { + zephyr,console = &uart30; + zephyr,shell-uart = &uart30; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_rram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&cpuflpr_sram { + status = "okay"; + /* size must be increased due to booting from SRAM */ + reg = <0x20028000 DT_SIZE_K(96)>; + ranges = <0x0 0x20028000 0x18000>; +}; + +&cpuflpr_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(96)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&uart30 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.yaml new file mode 100644 index 00000000000..3a4f07f907e --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +identifier: raytac_an54l15q_db/nrf54l15/cpuflpr +name: Raytac-AN54L15Q-DB-nRF54L15-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 96 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_defconfig b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_defconfig new file mode 100644 index 00000000000..f76cea10065 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.dts b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.dts new file mode 100644 index 00000000000..3e700be42da --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.dts @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Raytac Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "raytac_an54l15q_db_nrf54l15_cpuflpr.dts" + +&cpuflpr_sram { + reg = <0x2002f000 DT_SIZE_K(68)>; + ranges = <0x0 0x2002f000 0x11000>; +}; diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.yaml new file mode 100644 index 00000000000..ee996f4a9a1 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +identifier: raytac_an54l15q_db/nrf54l15/cpuflpr/xip +name: Raytac-AN54L15Q-DB-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 68 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip_defconfig b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip_defconfig new file mode 100644 index 00000000000..883b58986b1 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuflpr_xip_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Execute from RRAM +CONFIG_XIP=y diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_pinctrl.dtsi b/boards/raytac/an54l15q_db/raytac_an54l15q_db_pinctrl.dtsi new file mode 100644 index 00000000000..3f114bd6767 --- /dev/null +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_pinctrl.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart30_default: uart30_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart30_sleep: uart30_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ grtc_default: grtc_default { + group1 { + psels = , + ; + }; + }; + + /omit-if-no-ref/ grtc_sleep: grtc_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/raytac/mdbt53_db_40/Kconfig b/boards/raytac/mdbt53_db_40/Kconfig deleted file mode 100644 index d7591656a26..00000000000 --- a/boards/raytac/mdbt53_db_40/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Ratac MDBT53-DB-40 nRF5340 board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config DOMAIN_CPUNET_BOARD - string - default "raytac_mdbt53_db_40/nrf5340/cpunet" - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "raytac_mdbt53_db_40/nrf5340/cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts index 0db7bc0f933..86e5f8f2013 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts @@ -207,4 +207,4 @@ zephyr_udc0: &usbd { }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts index c5242550baa..18806c9b1cc 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts @@ -57,4 +57,4 @@ }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/raytac/mdbt53v_db_40/Kconfig b/boards/raytac/mdbt53v_db_40/Kconfig deleted file mode 100644 index da05da70267..00000000000 --- a/boards/raytac/mdbt53v_db_40/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Ratac MDBT53V-DB-40 nRF5340 board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config DOMAIN_CPUNET_BOARD - string - default "raytac_mdbt53v_db_40/nrf5340/cpunet" - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "raytac_mdbt53v_db_40/nrf5340/cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts index add880e3518..468243a71d5 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts @@ -160,4 +160,4 @@ }; /* Include default memory partition configuration file */ -#include +#include diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts index c5242550baa..18806c9b1cc 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts @@ -57,4 +57,4 @@ }; /* Include default shared RAM configuration file */ -#include +#include diff --git a/boards/realtek/rts5912_evb/rts5912_evb.dts b/boards/realtek/rts5912_evb/rts5912_evb.dts index f58d75e36da..7f1f476b5c0 100644 --- a/boards/realtek/rts5912_evb/rts5912_evb.dts +++ b/boards/realtek/rts5912_evb/rts5912_evb.dts @@ -71,3 +71,12 @@ pinctrl-names = "default"; pulses-per-round = <2>; }; + +&espi0 { + status = "okay"; + pinctrl-0 = < &espi_alert_gpio003 &espi_cs_gpio004 + &espi_io3_gpio005 &espi_io2_gpio006 + &espi_io1_gpio007 &espi_io0_gpio008 + &espi_clk_gpio009 &espi_reset_gpio020>; + pinctrl-names = "default"; +}; diff --git a/boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig b/boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig index 737b2cdd1b3..3fc1832029c 100644 --- a/boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig @@ -16,3 +16,5 @@ CONFIG_BUILD_OUTPUT_HEX=n CONFIG_I2C=y CONFIG_I2C_CALLBACK=y + +CONFIG_ARM_MPU=y diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig index 9ce790fe46b..cc6884c7bea 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig @@ -9,3 +9,5 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_BUILD_OUTPUT_HEX=n + +CONFIG_ARM_MPU=y diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml index 9a6fd6f7748..8d0e59f9c70 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml @@ -11,4 +11,5 @@ supported: - gpio - uart - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.yaml b/boards/renesas/ek_ra2l1/ek_ra2l1.yaml index 2ab8e436db3..47e0e079bf2 100644 --- a/boards/renesas/ek_ra2l1/ek_ra2l1.yaml +++ b/boards/renesas/ek_ra2l1/ek_ra2l1.yaml @@ -10,6 +10,7 @@ toolchain: supported: - flash - watchdog + - counter vendor: renesas testing: ignore_tags: diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml index 661dcd6c89d..6e1f8a12710 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml @@ -11,4 +11,5 @@ supported: - gpio - uart - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.dts b/boards/renesas/ek_ra4l1/ek_ra4l1.dts index 21c5eb62f80..ec2fca6b8f4 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.dts +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.dts @@ -191,3 +191,16 @@ &wdt { status = "okay"; }; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.yaml b/boards/renesas/ek_ra4l1/ek_ra4l1.yaml index 1c50ba9907c..77368c10346 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.yaml +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.yaml @@ -11,4 +11,5 @@ supported: - gpio - uart - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1.yaml b/boards/renesas/ek_ra4m1/ek_ra4m1.yaml index 1e624c9bda6..af2564df95f 100644 --- a/boards/renesas/ek_ra4m1/ek_ra4m1.yaml +++ b/boards/renesas/ek_ra4m1/ek_ra4m1.yaml @@ -11,4 +11,5 @@ supported: - gpio - uart - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.yaml b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml index 74567cb2432..4b36f431cd1 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.yaml +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml @@ -12,4 +12,5 @@ supported: - uart - usbd - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.yaml b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml index 3035a25af53..5baf4a4bfe6 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.yaml +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml @@ -12,4 +12,5 @@ supported: - uart - usbd - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.yaml b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml index 6d6decc81cd..f986a9f8d44 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1.yaml +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml @@ -11,4 +11,5 @@ supported: - gpio - uart - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml index dc2a982ccc3..ef63f298700 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml @@ -10,4 +10,5 @@ toolchain: supported: - gpio - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml index d2aece1948e..29b29a4efb8 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml @@ -12,4 +12,5 @@ supported: - uart - usbd - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml index a579a97b90d..c5af184f211 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml @@ -11,4 +11,5 @@ supported: - gpio - usbd - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml index c66c24bc725..7ea82509fc2 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml @@ -11,4 +11,5 @@ supported: - gpio - usbd - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml index 77c870f0327..85317151ba3 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml @@ -11,4 +11,5 @@ supported: - gpio - usbd - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml index c3d21e8c3d5..8db264944a3 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml @@ -11,4 +11,5 @@ supported: - gpio - usbd - watchdog + - counter vendor: renesas diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml index 15bb3fca1d6..c4348dcc7f5 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml @@ -13,4 +13,5 @@ supported: - watchdog - usbd - display + - counter vendor: renesas diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml index 97d74ff416a..6c6a7e1976f 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml @@ -12,4 +12,5 @@ supported: - uart - watchdog - usbd + - counter vendor: renesas diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml b/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml index 865a0ee3375..ccd914832ed 100644 --- a/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml +++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml @@ -11,4 +11,5 @@ supported: - gpio - uart - watchdog + - counter vendor: renesas diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml index aaa08aa02e0..ad3884548a9 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml @@ -10,4 +10,5 @@ toolchain: supported: - gpio - watchdog + - counter vendor: renesas diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml index 0abf95dda52..ae8bee39ffb 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml @@ -10,4 +10,5 @@ toolchain: supported: - gpio - watchdog + - counter vendor: renesas diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml index ca61ae119d0..7bb910b764a 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml @@ -12,4 +12,5 @@ supported: - uart - watchdog - usbd + - counter vendor: renesas diff --git a/boards/renesas/rcar_h3ulcb/board.yml b/boards/renesas/rcar_h3ulcb/board.yml index a0e38a44a90..6b2016e7736 100644 --- a/boards/renesas/rcar_h3ulcb/board.yml +++ b/boards/renesas/rcar_h3ulcb/board.yml @@ -1,6 +1,6 @@ board: name: rcar_h3ulcb - full_name: R-CAR H3 ARM CA57 (ARMv8) + full_name: R-Car H3ULCB vendor: renesas socs: - name: r8a77951 diff --git a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg deleted file mode 100644 index 55f8ccde660..00000000000 Binary files a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg and /dev/null differ diff --git a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg deleted file mode 100644 index 3f788baf486..00000000000 Binary files a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg and /dev/null differ diff --git a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg deleted file mode 100644 index 6b37aea51de..00000000000 Binary files a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg and /dev/null differ diff --git a/boards/renesas/rcar_h3ulcb/doc/index.rst b/boards/renesas/rcar_h3ulcb/doc/index.rst new file mode 100644 index 00000000000..44a126bd28e --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/doc/index.rst @@ -0,0 +1,295 @@ +.. zephyr:board:: rcar_h3ulcb + +Overview +******** +R-Car H3ULCB starter kit board is based on the R-Car H3 SoC that features basic +functions for next-generation car navigation systems. +It is composed of a quad Cortex |reg|-A57, a quad Cortex |reg|-A53 cluster and a +dual lockstep Cortex |reg|-R7. + +Zephyr OS support is available for both Cortex |reg|-A cores & Cortex |reg|-R7 core. + +More information about the H3 SoC can be fount at `Renesas R-Car H3 chip`_. + +Hardware +******** + +- H3ULCB features: + + - Storage: + + - 384KB System RAM + - 4/8 GB LPDDR4 + - 64 MB HYPER FLASH (512 MBITS, 160 MHZ, 320 MBYTES/S) + - 16MB QSPI FLASH (128 MBITS,80 MHZ,80 MBYTES/S)1 HEADER QSPI MODULE + - 8/32/64/128 GB EMMC (HS400 240 MBYTES/S) + - MICROSD-CARD SLOT (SDR104 100 MBYTES/S) + - Connectors + + - CN1 COM Express type connector 440pin + - CN2 QSPI Flash module + - CN3 DEBUG JTAG + - CN4 HDMI (HDMI-0) + - CN5 USB 2.0 (USB2.0-1) + - CN6 Push-Pull microSD Card Socket (SDHI-0) + - CN7 Ethernet, Connector, RJ45 + - CN8 LINE Out + - CN9 MIC Input + - CN10 DEBUG SERIAL (not populated) + - CN11 CPLD Programming JTAG + - CN12 DEBUG SERIAL (serial) + - CN13 Main Power Supply input (5VDC) + - CN14 CPU Fan + - Input + + - SW1 Hyper Flash + - SW2 Software Readable DIPSWITCHES (4x) + - SW3 Software Readable Push button + - SW4 Software Readable Push button + - SW5 Software Readable Push button + - SW6 Mode Settings + - SW7 CPLD Reset + - SW8 Power + - SW9 Reset + - Output + + - LED1 HDMI / Hot Plug Sync Detect + - LED4 Software Controllable LED + - LED5 Software Controllable LED + - LED6 Software Controllable LED + - LED9 5V Main Supply + - LED14 Backup LED + - LED15 System Reset + + +Complete list of the H3ULCB board capabilities can be found on the `eLinux H3SK page`_ of the board. + +More information about the board can be found at `Renesas R-Car Starter Kit website`_. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + + It is recommended to disable peripherals used by the R7 core on the Linux host. + +Connections and IOs +=================== + +The H3ULCB Starter Kit can be plugged on a Kingfisher daughter board. + +H3ULCB Board +------------ + +Here are official IOs figures from eLinux for H3ULCB board: + +`H3SK top view`_ + +`H3SK bottom view`_ + +Kingfisher Infotainment daughter board +-------------------------------------- + +When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. + +Here are official IOs figures from eLinux for Kingfisher Infotainment board: + +`Kingfisher top view`_ + +`Kingfisher bottom view`_ + +GPIO +---- + +By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software controllable LED 'LED5' can be used as output. + +UART +---- + +H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. + +Here is information about these serial ports: + ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| Physical Interface | Physical Location | Software Interface | Converter | Further Information | ++====================+===================+====================+===========+======================================+ +| CN12 DEBUG SERIAL | ULCB Board | SCIF2 | FT232RQ | Used by U-BOOT & Linux | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| CN10 DEBUG SERIAL | ULCB Board | SCIF1 | CP2102 | Non-welded | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ + +H3ULCB A53 support is assigning SCIF2 as UART while R7 supports is using SCIF1. In both cases, console are set to 115200 8N1 without hardware flow control by default. + +To access SCIF1 using CN04 UART interface, please follow the following pinout (depending on your Kingfisher board version): + ++--------+----------+----------+ +| Signal | Pin KF03 | Pin KF04 | ++========+==========+==========+ +| RXD | 3 | 4 | ++--------+----------+----------+ +| TXD | 5 | 2 | ++--------+----------+----------+ +| RTS | 4 | 1 | ++--------+----------+----------+ +| CTS | 6 | 3 | ++--------+----------+----------+ +| GND | 9 | 6 | ++--------+----------+----------+ + +CAN +--- + +H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. + ++--------------------+--------------------+--------------+ +| Physical Interface | Software Interface | Transceiver | ++====================+====================+==============+ +| CN17 | CAN0 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ +| CN18 | CAN1 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ + +.. note:: Interfaces are set to 125 kbit/s by default. + +The following table lists CAN physical interfaces pinout: + ++-----+--------+ +| Pin | Signal | ++=====+========+ +| 1 | CANH | ++-----+--------+ +| 2 | CANL | ++-----+--------+ +| 3 | GND | ++-----+--------+ + +I2C +--- + +H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. + +I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. + +Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. + +PWM +--- + +ULCB boards provide one PWM controller with a maximum of 7 channels [0..6]. H3ULCB does provide the pwm0 from test pin CP8 only. + +When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector. + +Programming and Debugging (A53) +******************************* + +Flashing +======== + +At that time, no flashing method is officially supported by this Zephyr port. + +Programming and Debugging (R7) +****************************** + +.. zephyr:board-supported-runners:: + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. + +.. note:: + See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_h3ulcb/r8a77951/r7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb/r8a77951/r7 + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb/r8a77951/r7 + :goals: debug + +You will then get access to a GDB session for debug. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb + +References +********** + +- `Renesas R-Car Starter Kit website`_ +- `Renesas R-Car H3 chip`_ +- `eLinux H3SK page`_ +- `eLinux Kingfisher page`_ + +.. _Renesas R-Car Starter Kit website: + https://www.renesas.com/br/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-m3-starter-kit + +.. _Renesas R-Car H3 chip: + https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support + +.. _eLinux H3SK page: + https://elinux.org/R-Car/Boards/H3SK + +.. _H3SK top view: + https://elinux.org/images/1/1f/R-Car-H3-topview.jpg + +.. _H3SK bottom view: + https://elinux.org/images/c/c2/R-Car-H3-bottomview.jpg + +.. _eLinux Kingfisher page: + https://elinux.org/R-Car/Boards/Kingfisher + +.. _Kingfisher top view: + https://elinux.org/images/0/08/Kfisher_top_specs.png + +.. _Kingfisher bottom view: + https://elinux.org/images/0/06/Kfisher_bot_specs.png diff --git a/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb.jpg similarity index 100% rename from boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg rename to boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb.jpg diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst deleted file mode 100644 index aefe429f5c8..00000000000 --- a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst +++ /dev/null @@ -1,87 +0,0 @@ -.. _rcar_h3ulcb_ca57: - -R-CAR H3 ARM CA57 (ARMv8) -######################### - -Overview -******** -The R-Car H3 is an SOC that features the basic functions for next-generation -car navigation systems. - -Hardware -******** -The R-Car H3 includes: - -* four 1.5-GHz ARM Cortex-A57 MPCore cores; -* four 1.2-GHz ARM Cortex-A53 MPCore cores; -* memory controller for LPDDR4-3200 with 32 bits x 4 channels; -* 2 channels for HDMI1.4b output and 1channel for RGB888 output and 1channel for LVDS; -* 4 channels MIPI-CSI2 Video Input, 2channels digital Video Input; -* serial ATA interface; -* USB3.0 x 2ch and USB2.0 x 3ch interfaces; -* 800-MHz ARM Cortex-R7 core; -* two- and three-dimensional graphics engines; -* video processing units; -* sound processing units; -* MediaLB interface; -* SD card host interface; -* USB3.0 and USB2.0 interfaces; -* PCI Express interface; -* CAN interface; -* EtherAVB. - -Connections and IOs -=================== - -H3ULCB Board ------------- - -Here are official IOs figures from eLinux for H3ULCB board: - -.. figure:: img/rcar_h3ulcb_top.jpg - :align: center - -.. figure:: img/rcar_h3ulcb_bottom.jpg - :align: center - -Supported Features -================== -The Renesas rcar_h3ulcb_ca57 board configuration supports the following -hardware features: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+-----------+------------------------------+--------------------------------+ -| MMC | renesas_rcar_mmc | DMA and SCC | -+-----------+------------------------------+--------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in -:zephyr_file:`boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig` - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. - -References -********** - -- `Renesas R-Car Development Support website`_ -- `eLinux R-Car Starter Kit page`_ - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux R-Car Starter Kit page: - https://elinux.org/R-Car/Boards/H3SK diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst deleted file mode 100644 index f77c16196fa..00000000000 --- a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst +++ /dev/null @@ -1,276 +0,0 @@ -.. _rcar_h3ulcb_boards: - -Renesas R-Car H3ULCB -#################### - -Overview -******** -- The H3 Starter Kit board is designed for evaluating the features and performance of the R-CAR H3 device from Renesas Electronics and it is also used for developing and evaluating application software for these R-CAR H3. - -- The H3 Starter Kit, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, via 440pin connector on bottom side. - -It is possible to order 2 different types of H3 Starter Kit Boards, one with Ethernet connection onboard and one with Ethernet connection on ComExpress. - -.. figure:: img/rcar_h3ulcb_starter_kit.jpg - :align: center - :alt: R-Car starter kit - -.. note:: The H3ULCB board can be plugged on a Renesas Kingfisher Infotainment daughter board through COM Express connector in order to physically access more I/O. CAUTION: In this case, power supply is managed by the daughter board. - -More information about the board can be found at `Renesas R-Car Starter Kit website`_. - -Hardware -******** - -Hardware capabilities for the H3ULCB for can be found on the `eLinux H3SK page`_ of the board. - -.. figure:: img/rcar_h3ulcb_features.jpg - :align: center - :alt: R-Car starter kit features - -.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. - -More information about the SoC that equips the board can be found here: - -- `Renesas R-Car H3 chip`_ - -Supported Features -================== - -Here is the current supported features when running Zephyr Project on the R-Car ULCB CR7: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINMUX | pinmux | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| GPIO | gpio | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+ + + + -| | FT232RQ / CP2102 | serial port-interrupt | -+-----------+------------------------------+--------------------------------+ -| CAN | can | normal mode | -+ + + + -| | TCAN332GDCNT | loopback mode | -+-----------+------------------------------+--------------------------------+ -| I2C | i2c | interrupt driven | -+-----------+------------------------------+--------------------------------+ -| PWM | pwm | All channels | -+-----------+------------------------------+--------------------------------+ - -It's also currently possible to write on the ram console. - -More features will be supported soon. - -Connections and IOs -=================== - -H3ULCB Board ------------- - -Here are official IOs figures from eLinux for H3ULCB board: - -`H3SK top view`_ - -`H3SK bottom view`_ - -Kingfisher Infotainment daughter board --------------------------------------- - -When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. - -Here are official IOs figures from eLinux for Kingfisher Infotainment board: - -`Kingfisher top view`_ - -`Kingfisher bottom view`_ - -GPIO ----- - -By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software controllable LED 'LED5' can be used as output. - -UART ----- - -H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. - -Here is information about these serial ports: - -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| Physical Interface | Physical Location | Software Interface | Converter | Further Information | -+====================+===================+====================+===========+======================================+ -| CN12 DEBUG SERIAL | ULCB Board | SCIF2 | FT232RQ | Used by U-BOOT & Linux | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| CN10 DEBUG SERIAL | ULCB Board | SCIF1 | CP2102 | Non-welded | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ - -.. note:: The Zephyr console output is assigned to SCIF1 (commonly used on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default. - -Here is CN04 UART interface pinout (depending on your Kingfisher board version): - -+--------+----------+----------+ -| Signal | Pin KF03 | Pin KF04 | -+========+==========+==========+ -| RXD | 3 | 4 | -+--------+----------+----------+ -| TXD | 5 | 2 | -+--------+----------+----------+ -| RTS | 4 | 1 | -+--------+----------+----------+ -| CTS | 6 | 3 | -+--------+----------+----------+ -| GND | 9 | 6 | -+--------+----------+----------+ - -CAN ---- - -H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. - -+--------------------+--------------------+--------------+ -| Physical Interface | Software Interface | Transceiver | -+====================+====================+==============+ -| CN17 | CAN0 | TCAN332GDCNT | -+--------------------+--------------------+--------------+ -| CN18 | CAN1 | TCAN332GDCNT | -+--------------------+--------------------+--------------+ - -.. note:: Interfaces are set to 125 kbit/s by default. - -The following table lists CAN physical interfaces pinout: - -+-----+--------+ -| Pin | Signal | -+=====+========+ -| 1 | CANH | -+-----+--------+ -| 2 | CANL | -+-----+--------+ -| 3 | GND | -+-----+--------+ - -I2C ---- - -H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. - -I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. - -Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. - -PWM ---- - -ULCB boards provide one PWM controller with a maximum of 7 channels [0..6]. H3ULCB does provide the pwm0 from test pin CP8 only. - -When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. - -.. note:: - See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_h3ulcb/r8a77951/r7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3ulcb/r8a77951/r7 - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3ulcb - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3ulcb/r8a77951/r7 - :goals: debug - -You will then get access to a GDB session for debug. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3ulcb - -References -********** - -- `Renesas R-Car Starter Kit website`_ -- `Renesas R-Car H3 chip`_ -- `eLinux H3SK page`_ -- `eLinux Kingfisher page`_ - -.. _Renesas R-Car Starter Kit website: - https://www.renesas.com/br/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-m3-starter-kit - -.. _Renesas R-Car H3 chip: - https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support - -.. _eLinux H3SK page: - https://elinux.org/R-Car/Boards/H3SK - -.. _H3SK top view: - https://elinux.org/images/1/1f/R-Car-H3-topview.jpg - -.. _H3SK bottom view: - https://elinux.org/images/c/c2/R-Car-H3-bottomview.jpg - -.. _eLinux Kingfisher page: - https://elinux.org/R-Car/Boards/Kingfisher - -.. _Kingfisher top view: - https://elinux.org/images/0/08/Kfisher_top_specs.png - -.. _Kingfisher bottom view: - https://elinux.org/images/0/06/Kfisher_bot_specs.png - -.. _Install a toolchain: - https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/renesas/rcar_salvator_x/board.yml b/boards/renesas/rcar_salvator_x/board.yml index 11166fb0a2c..c307356ac7d 100644 --- a/boards/renesas/rcar_salvator_x/board.yml +++ b/boards/renesas/rcar_salvator_x/board.yml @@ -1,6 +1,6 @@ board: name: rcar_salvator_x - full_name: R-Car H3 Salvator-X + full_name: R-Car Salvator-X vendor: renesas socs: - name: r8a77951 diff --git a/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg b/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg deleted file mode 100644 index 3f788baf486..00000000000 Binary files a/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg and /dev/null differ diff --git a/boards/renesas/rcar_salvator_x/doc/index.rst b/boards/renesas/rcar_salvator_x/doc/index.rst new file mode 100644 index 00000000000..ae248486db7 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/doc/index.rst @@ -0,0 +1,153 @@ +.. zephyr:board:: rcar_salvator_x + +Overview +******** +- The H3 Salvator-X board is designed for evaluating the features and performance + of the R-CAR H3 device from Renesas Electronics and it is also used for developing + and evaluating application software for these R-CAR H3. + +- The H3 Salvator-X, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, + each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces + like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, + via 440pin connector on bottom side. + +More information about the H3 SoC can be found here: `Renesas R-Car H3 chip`_ + +Hardware +******** + +Hardware capabilities for the H3 Salvator-X for can be found on the `eLinux H3 Salvator-X page`_. + +.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. + +More information about the board can be found at `Renesas R-Car Development Support website`_. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + + It is recommended to disable peripherals used by the R7 core on the Linux host. + +Connections and IOs +=================== + +.. figure:: img/r-car-h3-salvator-x-connections.jpg + :align: center + :alt: R-Car Salvator-X connections + +GPIO +---- + +By running Zephyr on H3 Salvator-X, the software readable push buttons 'SW20', +'SW21', 'SW22' can be used as input, and the software contollable LEDs 'LED4', +'LED5', 'LED6' can be used as output. + +UART +---- + +Salvator-X board is providing two serial ports: + +- one is for A53/A57 processors +- the other one is for CR7 + +Both ports are converted to USB through CP2102 converters and they are exposed +as follows: + ++-----------+-----------+ +| Connector | Processor | ++===========+===========+ +| CN25 | A53/A57 | ++-----------+-----------+ +| CN26 | CR7 | ++-----------+-----------+ + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This +probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected to CN1 on Salvator-X. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN25 and/or CN26 then use the following +settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_salvator_x`` board configuration can be built +in the usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_salvator_x + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_salvator_x + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_salvator_x + :goals: debug + +You will then get access to a GDB session for debug. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_salvator_x + +References +********** + +- `Renesas R-Car H3 chip`_ +- `Renesas R-Car Development Support website`_ +- `eLinux H3 Salvator-X page`_ + +.. _Renesas R-Car H3 chip: + https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux H3 Salvator-X page: + https://elinux.org/R-Car/Boards/Salvator-X + +.. _Install a toolchain: + https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_salvatorx.jpg b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.jpg similarity index 100% rename from boards/renesas/rcar_salvator_x/doc/img/rcar_h3_salvatorx.jpg rename to boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.jpg diff --git a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst deleted file mode 100644 index 3e7b5772944..00000000000 --- a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst +++ /dev/null @@ -1,183 +0,0 @@ -.. _rcar_h3_salvatorx_boards: - -Renesas R-Car H3 Salvator-X -########################### - -Overview -******** -- The H3 Salvator-X board is designed for evaluating the features and performance - of the R-CAR H3 device from Renesas Electronics and it is also used for developing - and evaluating application software for these R-CAR H3. - -- The H3 Salvator-X, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, - each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces - like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, - via 440pin connector on bottom side. - -.. figure:: img/rcar_h3_salvatorx.jpg - :align: center - :alt: R-Car Salvator-X kit - -More information about the board can be found at `Renesas R-Car Development Support website`_. - -Hardware -******** - -Hardware capabilities for the H3 Salvator-X for can be found on the `eLinux H3 Salvator-X page`_ -of the board. - -.. figure:: img/rcar_h3_features.jpg - :align: center - :alt: R-Car Salvator-X features - -.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. - -More information about the SoC that equips the board can be found here: - -- `Renesas R-Car H3 chip`_ - -Supported Features -================== - -Here is the current supported features when running Zephyr Project on the R-Car Salvator-X CR7: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| GPIO | gpio | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+ + + + -| | FT232RQ / CP2102 | serial port-interrupt | -+-----------+------------------------------+--------------------------------+ -| CAN | can | normal mode | -+ + + + -| | TCAN332GDCNT | loopback mode | -+-----------+------------------------------+--------------------------------+ -| I2C | i2c | interrupt driven | -+-----------+------------------------------+--------------------------------+ - -It's also currently possible to write on the ram console. - -Connections and IOs -=================== - -.. figure:: img/r-car-h3-salvator-x-connections.jpg - :align: center - :alt: R-Car Salvator-X connections - -GPIO ----- - -By running Zephyr on H3 Salvator-X, the software readable push buttons 'SW20', -'SW21', 'SW22' can be used as input, and the software contollable LEDs 'LED4', -'LED5', 'LED6' can be used as output. - -UART ----- - -Salvator-X board is providing two serial ports: - -- one is for A53/A57 processors -- the other one is for CR7 - -Both ports are converted to USB through CP2102 converters and they are exposed -as follows: - -+-----------+-----------+ -| Connector | Processor | -+===========+===========+ -| CN25 | A53/A57 | -+-----------+-----------+ -| CN26 | CR7 | -+-----------+-----------+ - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This -probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected to CN1 on Salvator-X. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN25 and/or CN26 then use the following -settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_salvator_x`` board configuration can be built -in the usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_salvator_x - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_salvator_x - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_salvator_x - :goals: debug - -You will then get access to a GDB session for debug. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_salvator_x - -References -********** - -- `Renesas R-Car H3 chip`_ -- `Renesas R-Car Development Support website`_ -- `eLinux H3 Salvator-X page`_ - -.. _Renesas R-Car H3 chip: - https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux H3 Salvator-X page: - https://elinux.org/R-Car/Boards/Salvator-X - -.. _Install a toolchain: - https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/renesas/rcar_salvator_xs/board.yml b/boards/renesas/rcar_salvator_xs/board.yml index 2b8ded23f8a..a6face8931a 100644 --- a/boards/renesas/rcar_salvator_xs/board.yml +++ b/boards/renesas/rcar_salvator_xs/board.yml @@ -1,6 +1,6 @@ board: name: rcar_salvator_xs - full_name: R-CAR Salvator XS M3 ARM CA57 (ARMv8) + full_name: R-Car Salvator-XS vendor: renesas socs: - name: r8a77961 diff --git a/boards/renesas/rcar_salvator_xs/doc/index.rst b/boards/renesas/rcar_salvator_xs/doc/index.rst index 464b4e659d7..60f53324ac6 100644 --- a/boards/renesas/rcar_salvator_xs/doc/index.rst +++ b/boards/renesas/rcar_salvator_xs/doc/index.rst @@ -1,7 +1,4 @@ -.. _rcar_salvator_xs: - -R-CAR Salvator XS M3 ARM CA57 (ARMv8) -##################################### +.. zephyr:board:: rcar_salvator_xs Overview ******** @@ -29,27 +26,12 @@ The R-Car M3-W includes: * CAN interface; * EtherAVB. +Hardware capabilities for the Salvator-XS for can be found on the `eLinux Salvator-XS page`_. + Supported Features ================== -The Renesas rcar_salvator_xs board configuration supports the following -hardware features: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+-----------+------------------------------+--------------------------------+ -| MMC | renesas_rcar_mmc | DMA and SCC | -+-----------+------------------------------+--------------------------------+ - -Other hardware features have not been enabled yet for this board. -The default configuration can be found in -:zephyr_file:`boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig` +.. zephyr:board-supported-hw:: Programming and Debugging ************************* diff --git a/boards/renesas/rcar_salvator_xs/doc/rcar_salvator_xs.jpg b/boards/renesas/rcar_salvator_xs/doc/rcar_salvator_xs.jpg new file mode 100644 index 00000000000..31b725981ff Binary files /dev/null and b/boards/renesas/rcar_salvator_xs/doc/rcar_salvator_xs.jpg differ diff --git a/boards/renesas/rcar_spider_s4/board.yml b/boards/renesas/rcar_spider_s4/board.yml index caf9b8cf5ad..2a4ebdfb1ab 100644 --- a/boards/renesas/rcar_spider_s4/board.yml +++ b/boards/renesas/rcar_spider_s4/board.yml @@ -1,6 +1,6 @@ board: name: rcar_spider_s4 - full_name: R-CAR Spider S4 (ARM64) + full_name: R-Car Spider vendor: renesas socs: - name: r8a779f0 diff --git a/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg b/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg deleted file mode 100644 index 76bda515cfb..00000000000 Binary files a/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg and /dev/null differ diff --git a/boards/renesas/rcar_spider_s4/doc/index.rst b/boards/renesas/rcar_spider_s4/doc/index.rst new file mode 100644 index 00000000000..7edf20bca23 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/doc/index.rst @@ -0,0 +1,265 @@ +.. zephyr:board:: rcar_spider_s4 + +Overview +******** + +R-Car S4 Spider board is based on the R-Car S4 SoC made for Car +Server/Communication Gateway and that is composed of a octo Cortex |reg|-A55, a +dual lockstep Cortex |reg|-R52 and a double dual lockstep G4MH. + +The R-Car S4 SoC enables the launch of Car Server/CoGW with high performance, +high-speed networking, high security and high functional safety levels that are +required as E/E architectures evolve into domains and zones. + +The R-Car S4 solution allows designers to re-use up to 88 percent of software +code developed for 3rd generation R-Car SoCs and RH850 MCU applications. +The software package supports the real-time cores with various drivers and +basic software such as Linux BSP and hypervisors. + +The Renesas R-Car Spider board is the Renesas R-Car S4 reference board and is designed for +evaluating features and performance of this SoC. + +Zephyr OS support is available for both Cortex |reg|-A cores & Cortex |reg|-R52 core. + +More information about the S4 SoC can be fount at `Renesas R-Car S4 chip`_. + +Hardware +******** + +- Spider features: + + - Connectors + + - CPU Board: + + - CN1 JTAG1 + - CN2 JTAG2 + - CN3 EX-SPI (QSPI0) + - CN4 MicroSD Slot (back side) + - CN11 EXIO Connector A (back side) + - CN12 EXIO Connector B (back side) + - CN14 EVT + - CN16 OcuLink (PCIe0,PCIe1) + - CN24 CAN 4pin + - CN20 USB microAB (SCIF0) + - CN21 USB microAB (HSCIF0) + - CN22 SW Board + - CN23 CPLD JTAG + - CN27 FAN + - CN30 Buck3 + - CN31 Buck1 + - CN32 CAN 8pin (back side) + - Breakout Board: + + - CN11 EXIO Connector A + - CN12 EXIO Connector B + - CN13 CAN 0/1 + - CN15 CAN 3/4/5 + - CN18 CAN 6/7/8 + - CN21 CAN 2/9/10/11 + - CN24 CAN 12/13/14/15 + - CN28 LIN0 + - CN29 LIN1 + - CN30 LIN2 + - CN31 LIN3 + - CN32 LIN4 + - CN33 LIN5 + - CN34 LIN6 + - CN35 LIN7 + - CN36 EtherTS + - CN37 MSIOF0 + - CN38 CAN/LIN BOARD + - CN39 GPIO CN_A + - CN40 GPIO + - CN41 I2C + - CN42 HSCIF0 + - CN43 SCIF0 + - CN44 TSN_CN + - CN45 Legacy 12V-in + - CN46 AC Adapter + - CN48 POWER CONTROL + - CN50 Debug Serial + - CN51 FAN + - Input + + - SW1 (SPI Flash Memory / EX-SPI connector) + - SW2 (Hyper Flash Memory / SPI Flash Memory) + - SW3 (MicroSD Card Slot / eMMC Memory) + - SW4 (PRESETn) + - SW6 (Interface Voltage Setting for MMC/JTAG2) + - SW8 Mode Setting + - SW10 (Software Switch) + - SW11 (Board Power-Supply Circuit Control) + - SW12 (AURORES#) + - SW13 (CANFD0 RX) + - SW14 (CANFD0 TX) + - SW15 (System Reset Switch) + - Output + + - LED7 Software Controllable LED + - LED8 Software Controllable LED + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + + It is recommended to disable peripherals used by the R52 core on the Linux host. + +Connections and IOs +=================== + +The Spider board consists of a CPU board plugged on top of a Breakout board. + +Here are the official IOs figures from eLinux for S4 board: + +`S4 Spider CPU board IOs`_ + +`S4 Spider breakout board IOs`_ + +GPIO +---- + +By running Zephyr on S4 Spider, the software controllable LED 'LED8' can be used as output. + +UART +---- + +Here is information about both serial ports provided on the S4 Spider board : + ++--------------------+----------+--------------------+-------------+------------------------+ +| Physical Interface | Location | Software Interface | Converter | Further Information | ++====================+==========+====================+=============+========================+ +| CN20 USB Port | CPU Board| SCIF0/HSCIF1 | FT232HQ | Default Zephyr serial | ++--------------------+----------+--------------------+-------------+------------------------+ +| CN21 USB Port | CPU Board| SCIF3/HSCIF0 | FT2232H-56Q | Used by U-BOOT & Linux | ++--------------------+----------+--------------------+-------------+------------------------+ + +.. note:: + The Zephyr console output is assigned to SCIF0 (CN20 USB Port) with settings: + 115200 8N1 without hardware flow control by default. + +I2C +--- + +I2C is mainly used to manage and power-on some onboard chips on the S4 Spider board. + +Embedded I2C devices and I/O expanders are not yet supported. +The current I2C support therefore does not make any devices available to the user at this time. + +Programming and Debugging (A55) +******************************* + +At that time, no direct flashing method is officially supported by this Zephyr port. +However, it is possible to load the Zephyr binary using U-Boot commands. + +One of the ways to load Zephyr is shown below. + +.. code-block:: console + + tftp 0x48000000 + booti 0x48000000 + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_spider_s4/r8a779f0/a55 + :goals: build + +Programming and Debugging (R52) +******************************* + +.. zephyr:board-supported-runners:: + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +| The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. +| This probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected with a "Coresight 20 pins" +adapter to CN1 connector on Spider board. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN20 USB port of your Spider board. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_spider_s4/r8a779f0/r52`` board configuration can be built in the +usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_spider_s4/r8a779f0/r52 + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.3.0-rc2 *** + Hello World! rcar_spider_s4 + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_spider_s4/r8a779f0/r52 + :goals: debug + +You will then get access to a GDB session for debugging. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v3.3.0-rc2 *** + Hello World! rcar_spider_s4 + + +References +********** + +- `Renesas R-Car S4 Spider`_ +- `Renesas R-Car S4 chip`_ +- `eLinux S4 Spider`_ + +.. _Renesas R-Car S4 Spider: + https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/rtp8a779f0askb0sp2s-r-car-s4-reference-boardspider + +.. _Renesas R-Car S4 chip: + https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-s4-automotive-system-chip-soc-car-servercommunication-gateway + +.. _eLinux S4 Spider: + https://elinux.org/R-Car/Boards/Spider + +.. _S4 Spider CPU board IOs: + https://elinux.org/images/6/6d/Rcar_s4_spider_cpu_board.jpg + +.. _S4 Spider breakout board IOs: + https://elinux.org/images/2/29/Rcar_s4_spider_breakout_board.jpg diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst deleted file mode 100644 index b66975af164..00000000000 --- a/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst +++ /dev/null @@ -1,83 +0,0 @@ -.. _rcar_spider_a55: - -R-CAR Spider S4 (ARM64) -####################### - -Overview -******** -R-Car S4 enables to launch Car Server/CoGW with high performance, high-speed networking, -high security and high functional safety levels that are required as E/E architectures -evolve into domains and zones. The R-Car S4 solution allows designers to re-use up to 88 -percent of software code developed for 3rd generation R-Car SoCs and RH850 MCU applications. -The software package supports the real-time cores with various drivers and basic software -such as Linux BSP and hypervisors. - -Hardware -******** -The R-Car S4 includes: - -* eight 1.2GHz Arm Cortex-A55 cores, 2 cores x 4 clusters; -* 1.0 GHz Arm Cortex-R52 core (hardware Lock step is supported); -* two 400MHz G4MH cores (hardware Lock step is supported); -* memory controller for LPDDR4X-3200 with 32bit bus (16bit x 1ch + 16bit x 1ch) with ECC; -* SD card host interface / eMMC; -* UFS 3.0 x 1 channel; -* PCI Express Gen4.0 interface (Dual lane x 2ch); -* ICUMX; -* ICUMH; -* SHIP-S x 3 channels; -* AES Accerator x 8 channels; -* CAN FD interface x 16 channels; -* R-Switch2 (Ether); -* 100base EtherAVB x 1 channel; -* Gbit-EtherTSN x 3 channels; -* 1 unit FlexRay (A,B 2ch) interface. - -Supported Features -================== -The Renesas ``rcar_spider_s4/r8a779f0/a55`` board configuration supports the following -hardware features: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| UART | serial | interrupt-driven/polling | -+-----------+------------------------------+--------------------------------+ - -Other hardware features have not been enabled yet for this board. - -Programming and Debugging -************************* - -The onboard flash is not supported by Zephyr at this time. However, it is possible to -load the Zephyr binary using U-Boot commands. - -One of the ways to load Zephyr is shown below. - -.. code-block:: console - - tftp 0x48000000 - booti 0x48000000 - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_spider_s4/r8a779f0/a55 - :goals: build - -References -********** - -- `Renesas R-Car Development Support website`_ -- `eLinux Spider page`_ - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux Spider page: - https://elinux.org/R-Car/Boards/Spider diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst deleted file mode 100644 index 9c7be4d8f99..00000000000 --- a/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst +++ /dev/null @@ -1,200 +0,0 @@ -.. _rcar_spider_boards: - -Renesas R-Car Spider -#################### - -Overview -******** - -| R-Car S4 enables the launch of Car Server/CoGW with high performance, high-speed networking, -| high security and high functional safety levels that are required as E/E architectures -| evolve into domains and zones. - -| The R-Car S4 solution allows designers to re-use up to 88 percent of software code developed -| for 3rd generation R-Car SoCs and RH850 MCU applications.\ -| The software package supports the real-time cores with various drivers and basic software -| such as Linux BSP and hypervisors. - -The Renesas R-Car Spider board is the Renesas R-Car S4 reference board and is designed for -evaluating features and performance of this SoC. - -.. figure:: img/rcar_s4_spider_full.jpg - :align: center - :alt: R-Car S4 Spider - -More information about the board can be found at `Renesas R-Car S4 Spider`_ website. - -Hardware -******** - -Hardware capabilities for the S4 Spider board can be found on the `eLinux S4 Spider`_ page. - -.. figure:: img/rcar_s4_block_diagram.jpg - :align: center - :alt: R-Car S4 Spider block diagram - -.. note:: We support Zephyr running on the CR52 processor that is provided for RTOS purpose. - -More information about the SoC that equips the board can be found here: - -- `Renesas R-Car S4 chip`_ - -Supported Features -================== - -Here are the current supported features when running Zephyr Project on the R-Car S4 Spider CR52: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINMUX | pinmux | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| GPIO | gpio | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+ + + + -| | FT232RQ | serial port-interrupt | -+-----------+------------------------------+--------------------------------+ -| I2C | i2c | interrupt driven | -+-----------+------------------------------+--------------------------------+ -| PWM | pwm | All channels | -+-----------+------------------------------+--------------------------------+ - -It is also currently possible to write on the ram console. - -More features will be supported soon. - -Connections and IOs -=================== - -| The "Spider board" consists of a CPU board and a Breakout board. -| The CPU board is stuck on top of the Breakout board. - -Here are the official IOs figures from eLinux for S4 board: - -`S4 Spider CPU board IOs`_ - -`S4 Spider breakout board IOs`_ - -GPIO ----- - -By running Zephyr on S4 Spider, the software controllable LED 'LED8' can be used as output. - -UART ----- - -Here is information about both serial ports provided on the S4 Spider board : - -+--------------------+----------+--------------------+-------------+------------------------+ -| Physical Interface | Location | Software Interface | Converter | Further Information | -+====================+==========+====================+=============+========================+ -| CN20 USB Port | CPU Board| SCIF0/HSCIF1 | FT232HQ | Default Zephyr serial | -+--------------------+----------+--------------------+-------------+------------------------+ -| CN21 USB Port | CPU Board| SCIF3/HSCIF0 | FT2232H-56Q | Used by U-BOOT & Linux | -+--------------------+----------+--------------------+-------------+------------------------+ - -.. note:: - The Zephyr console output is assigned to SCIF0 (CN20 USB Port) with settings: - 115200 8N1 without hardware flow control by default. - -I2C ---- - -I2C is mainly used to manage and power-on some onboard chips on the S4 Spider board. - -Embedded I2C devices and I/O expanders are not yet supported. -The current I2C support therefore does not make any devices available to the user at this time. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -| The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. -| This probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected with a "Coresight 20 pins" -adapter to CN1 connector on Spider board. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN20 USB port of your Spider board. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_spider_s4/r8a779f0/r52`` board configuration can be built in the -usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_spider_s4/r8a779f0/r52 - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v3.3.0-rc2 *** - Hello World! rcar_spider_s4 - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_spider_s4/r8a779f0/r52 - :goals: debug - -You will then get access to a GDB session for debugging. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v3.3.0-rc2 *** - Hello World! rcar_spider_s4 - -References -********** - -- `Renesas R-Car S4 Spider`_ -- `Renesas R-Car S4 chip`_ -- `eLinux S4 Spider`_ - -.. _Renesas R-Car S4 Spider: - https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/rtp8a779f0askb0sp2s-r-car-s4-reference-boardspider - -.. _Renesas R-Car S4 chip: - https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-s4-automotive-system-chip-soc-car-servercommunication-gateway - -.. _eLinux S4 Spider: - https://elinux.org/R-Car/Boards/Spider - -.. _S4 Spider CPU board IOs: - https://elinux.org/images/6/6d/Rcar_s4_spider_cpu_board.jpg - -.. _S4 Spider breakout board IOs: - https://elinux.org/images/2/29/Rcar_s4_spider_breakout_board.jpg diff --git a/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_spider_full.jpg b/boards/renesas/rcar_spider_s4/doc/rcar_spider_s4.jpg similarity index 100% rename from boards/renesas/rcar_spider_s4/doc/img/rcar_s4_spider_full.jpg rename to boards/renesas/rcar_spider_s4/doc/rcar_spider_s4.jpg diff --git a/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 b/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 new file mode 100644 index 00000000000..3587994f266 --- /dev/null +++ b/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RSK_RX130 + select SOC_R5F513083XFB diff --git a/boards/renesas/rsk_rx130/board.cmake b/boards/renesas/rsk_rx130/board.cmake new file mode 100644 index 00000000000..0fb228f3dd8 --- /dev/null +++ b/boards/renesas/rsk_rx130/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" +board_runner_args(jlink "--device=R5F51308" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rsk_rx130/board.yml b/boards/renesas/rsk_rx130/board.yml new file mode 100644 index 00000000000..90573aed223 --- /dev/null +++ b/boards/renesas/rsk_rx130/board.yml @@ -0,0 +1,13 @@ +board: + name: rsk_rx130 + full_name: Renesas Starter Kit for RX130 + vendor: renesas + revision: + format: custom + default: 512kb + exact: true + revisions: + - name: 512kb + - name: 128kb + socs: + - name: r5f513083xfb diff --git a/boards/renesas/rsk_rx130/doc/index.rst b/boards/renesas/rsk_rx130/doc/index.rst new file mode 100644 index 00000000000..c76d4b9bcb8 --- /dev/null +++ b/boards/renesas/rsk_rx130/doc/index.rst @@ -0,0 +1,149 @@ +.. zephyr:board:: rsk_rx130 + +Overview +******** + +The Renesas Starter Kit for RX130-512KB is the perfect starter kit for +developers who are new to the RX130 (Program Flash 512KB, Pin Count 100-pin), +which operates at up to 32 MHz and is based on the RXv1 core architecture, +making it suitable for various embedded applications + +**MCU Native Pin Access** + +The RSKRX130-512KB includes: + +- 32-MHz, 32-bit RX MCUs in 100 pins LFQFP package, Micon Pin Headers +- Direct MCU pin access through standard headers for easy peripheral integration +- Internal high-speed oscillator and low-speed on-chip oscillators +- Three low power consumption modes + +**System Control and Debugging** + +- USB Full-Speed Device (mini-B connector) for communication and power + +- Power source options: + + - USB-powered (debug port) + - External power supply via standard input + +- Debugging support: + + - Via Jlink debugger with RX adapter boards. + +- User LEDs and buttons: + + - Four User LEDs (red x2, yellow, green) + - Power LED (green) indicating availability of regulated power + - One Reset button, three User buttons + +- Ecosystems expansions: + + - Two Digilent Pmod (LCD and Spare) connectors + - 2Kbit I2C EEPROM + +**Special Feature Access** + +- IEC60730 compliance +- Capacitive touch sensing unit +- LCD drive capability for displaying data or status in real-time applications + +Hardware +******** +Detailed hardware features can be found at: + +- RX130 MCU: `RX130 Group User's Manual Hardware`_ +- RSK-RX130-512KB: `RSK_RX130_512KB - User's Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``rsk_rx130@512kb`` board target configuration can be +built, flashed, and debugged as below. + +Currently, the Zephyr SDK hasn't added support for RX builds yet, so the GCC for RX toolchain is required and build system need to be set to use "cross-compile". + + - Download and install GCC for RX v8.3.0.202405 toolchain: + + https://llvm-gcc-renesas.com/rx-download-toolchains/ + + - Set env variable: + + .. code-block:: console + + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + export CROSS_COMPILE=/bin/rx-elf- + + - Build the Blinky Sample for RSK-RX130-512KB: + + .. code-block:: console + + cd ~/zephyrproject/zephyr + west build -p always -b rsk_rx130@512kb samples/basic/blinky + +Flashing +======== + +Program can be flashed to RSKRX130-512KB via Jlink with RX adapter boards. + +To flash the program to board + + 1. Connect from board's debug connector port to host PC using Jlink debugger. + + 2. Execute west command + + .. code-block:: console + + west flash + +Debugging +========= + +You can use `Renesas Debug extension`_ on Visual Studio code for a visual debug interface. +The configuration for launch.json is as below. + +.. code-block:: json + + { + "version": "0.2.0", + "configurations": [ + { + "type": "renesas-hardware", + "request": "launch", + "name": "Renesas GDB Hardware Debugging", + "target": { + "deviceFamily": "RX", + "device": "R5F51308", + "debuggerType": "SEGGERJLINKRX", + } + } + ] + } + + +References +********** + +- `RSK_RX130_512KB Website`_ +- `RX130 MCU group Website`_ + +.. _RSK_RX130_512KB Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx130-512kb-starter-kit-renesas-starter-kit-rx130-512kb + +.. _RX130 MCU group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx130-cost-optimized-high-performance-32-bit-microcontroller-enhanced-touch-key-function-and-5v-operation + +.. _RSK_RX130_512KB - User's Manual: + https://www.renesas.com/en/document/mat/renesas-starter-kit-rx130-512kb-users-manual-rev100 + +.. _RX130 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/rx130-group-users-manual-hardware-rev300 + +.. _Renesas Debug extension: + https://marketplace.visualstudio.com/items?itemName=RenesasElectronicsCorporation.renesas-debug diff --git a/boards/renesas/rsk_rx130/doc/rsk_rx130.webp b/boards/renesas/rsk_rx130/doc/rsk_rx130.webp new file mode 100644 index 00000000000..e112958c0f0 Binary files /dev/null and b/boards/renesas/rsk_rx130/doc/rsk_rx130.webp differ diff --git a/boards/renesas/rsk_rx130/doc/rx130_block_diagram.webp b/boards/renesas/rsk_rx130/doc/rx130_block_diagram.webp new file mode 100644 index 00000000000..563d8284917 Binary files /dev/null and b/boards/renesas/rsk_rx130/doc/rx130_block_diagram.webp differ diff --git a/boards/renesas/rsk_rx130/revision.cmake b/boards/renesas/rsk_rx130/revision.cmake new file mode 100644 index 00000000000..f9ba58ee9af --- /dev/null +++ b/boards/renesas/rsk_rx130/revision.cmake @@ -0,0 +1,8 @@ +set(RX130_REVISIONS "512kb" "128kb") +if (NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "RX130_REVISIONS") +else() + if (NOT BOARD_REVISION IN_LIST RX130_REVISIONS) + message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for Legend. Accepted revisions: ${RX130_REVISIONS}") + endif() +endif() \ No newline at end of file diff --git a/boards/renesas/rsk_rx130/rsk_rx130.dts b/boards/renesas/rsk_rx130/rsk_rx130.dts new file mode 100644 index 00000000000..1ca2ac91d81 --- /dev/null +++ b/boards/renesas/rsk_rx130/rsk_rx130.dts @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "rsk_rx130_512kb-pinctrl.dtsi" + +/ { + model = "Renesas RSK+RX130-512KB KIT"; + compatible = "renesas,rsk_rx130_512kb","renesas,rxv1"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioportd 3 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led3: led3 { + gpios = <&ioporte 6 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led3; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + div = <2>; + mul = ; + status = "okay"; +}; + +&cmt { + clock-frequency = <4000000>; + status = "okay"; +}; + +&ioportd { + status = "okay"; +}; + +&ioporte { + status = "okay"; +}; + +&sci1 { + pinctrl-0 = <&sci1_default>; + pinctrl-names = "default"; + status = "okay"; + + uart1: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi b/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi new file mode 100644 index 00000000000..8b4006931bc --- /dev/null +++ b/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci1_default: sci1_default { + group1 { + psels = , /* TX */ + ; /* RX */ + }; + }; +}; diff --git a/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml b/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml new file mode 100644 index 00000000000..49890d8e2fb --- /dev/null +++ b/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: rsk_rx130@512kb +name: Renesas Starter Kit+ RX130-512KB +type: mcu +arch: rx +toolchain: + - cross-compile +supported: + - gpio + - serial + - timer +ram: 48 +flash: 512 diff --git a/boards/renesas/rsk_rx130/rsk_rx130_defconfig b/boards/renesas/rsk_rx130/rsk_rx130_defconfig new file mode 100644 index 00000000000..95b9befa6dc --- /dev/null +++ b/boards/renesas/rsk_rx130/rsk_rx130_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/rzg3s_smarc/doc/index.rst b/boards/renesas/rzg3s_smarc/doc/index.rst index d69f9686e2c..2f2eeeab7f2 100644 --- a/boards/renesas/rzg3s_smarc/doc/index.rst +++ b/boards/renesas/rzg3s_smarc/doc/index.rst @@ -58,40 +58,7 @@ Please see :zephyr:code-sample:`rz-openamp-linux-zephyr` sample for reference. Supported Features ================== -The ``rzg3s_smarc/r9a08g045s33gbg/cm33`` board target supports the ARM Cortex-M33 System Core without FPU -and the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| GTM | on-chip | counter | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| INTC | on-chip | external interrupt controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock control | -+-----------+------------+-------------------------------------+ -| MHU | on-chip | mbox | -+-----------+------------+-------------------------------------+ - -Other hardware features are currently not supported by the port. +.. zephyr:board-supported-hw:: Programming and Debugging ************************* diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi index 72a243947cd..a5d105ac29c 100644 --- a/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi @@ -55,4 +55,27 @@ pinmux = ; /* GTIOCA */ }; }; + + /omit-if-no-ref/ can0_pins: can0 { + can0-pinmux { + pinmux = , /* TX */ + ; /* RX */ + }; + }; + + /omit-if-no-ref/ can1_pins: can1 { + can1-pinmux { + pinmux = , /* TX */ + ; /* RX */ + }; + }; + + /omit-if-no-ref/ spi0_pins: spi0 { + spi0-pinmux { + pinmux = , /* CK */ + , /* MOSI */ + , /* MISO */ + ; /* SSL */ + }; + }; }; diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts index 1f2bd49c9b9..5440eeaa5e4 100644 --- a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts @@ -22,6 +22,7 @@ zephyr,flash = &spi_flash; zephyr,console = &scif1; zephyr,shell-uart = &scif1; + zephyr,canbus = &canfd0; }; aliases { @@ -74,6 +75,19 @@ reg = <0x80200000 DT_SIZE_K(256)>; }; + transceiver0: can-phy0 { + compatible = "can-transceiver-gpio"; + standby-gpios = <&gpio13 0 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + #phy-cells = <0>; + }; + + transceiver1: can-phy1 { + compatible = "can-transceiver-gpio"; + standby-gpios = <&gpio13 1 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + #phy-cells = <0>; + }; }; &scif1 { @@ -83,14 +97,36 @@ status = "okay"; }; -&gpio0{ +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; status = "okay"; }; -&gpio18{ +&gpio0 { + status = "okay"; +}; + +&gpio13{ + status = "okay"; +}; + +&gpio18 { status = "okay"; }; &adc { status = "okay"; }; + +&canfd_global { + status = "okay"; +}; + +&canfd0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; + rx-max-filters = <32>; + phys = <&transceiver0>; +}; diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml index ad2a7687a93..cf2b6a3e8d4 100644 --- a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml @@ -13,3 +13,5 @@ supported: - gpio - counter - pwm + - spi + - can diff --git a/boards/sc/scobc_module1/board.yml b/boards/sc/scobc_module1/board.yml index 2ffbcc51e54..02c931595cb 100644 --- a/boards/sc/scobc_module1/board.yml +++ b/boards/sc/scobc_module1/board.yml @@ -1,6 +1,6 @@ board: name: scobc_module1 full_name: OBC module 1 - vendor: spacecubics + vendor: sc socs: - name: designstart_fpga_cortex_m3 diff --git a/boards/seeed/xiao_mg24/xiao_mg24.dts b/boards/seeed/xiao_mg24/xiao_mg24.dts index 24a2cc570ea..86181585bcb 100644 --- a/boards/seeed/xiao_mg24/xiao_mg24.dts +++ b/boards/seeed/xiao_mg24/xiao_mg24.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "xiao_mg24-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" @@ -14,13 +14,13 @@ compatible = "seeed,xiao_mg24", "silabs,efr32mg24"; chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; zephyr,console = &usart0; + zephyr,flash = &flash0; zephyr,shell-uart = &usart0; - zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci = &bt_hci_silabs; + zephyr,uart-pipe = &usart0; }; /* These aliases are provided for compatibility with samples */ @@ -48,25 +48,25 @@ }; &hfxo { - status = "okay"; ctune = <95>; precision = <50>; + status = "okay"; }; &lfxo { - status = "okay"; ctune = <44>; precision = <50>; + status = "okay"; }; &hfrcodpll { clock-frequency = ; clocks = <&hfxo>; - dpll-n = <3839>; - dpll-m = <1919>; + dpll-autorecover; dpll-edge = "fall"; dpll-lock = "phase"; - dpll-autorecover; + dpll-m = <1919>; + dpll-n = <3839>; }; &em23grpaclk { @@ -98,19 +98,19 @@ &eusart0 { compatible = "silabs,eusart-uart"; + current-speed = <115200>; pinctrl-0 = <&eusart0_default>; pinctrl-names = "default"; - current-speed = <115200>; }; &eusart1 { compatible = "silabs,eusart-spi"; - pinctrl-0 = <&eusart1_default>; - pinctrl-names = "default"; - cs-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; - clock-frequency = <4000000>; #address-cells = <1>; #size-cells = <0>; + clock-frequency = <4000000>; + cs-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; }; &i2c0 { @@ -145,7 +145,6 @@ &gpioc { status = "okay"; - }; &gpiod { @@ -172,27 +171,27 @@ /* Reserve 48 kB for the bootloader */ boot_partition: partition@0 { - label = "mcuboot"; reg = <0x0 DT_SIZE_K(48)>; + label = "mcuboot"; read-only; }; /* Reserve 720 kB for the application in slot 0 */ slot0_partition: partition@c000 { - label = "image-0"; reg = <0x0000c000 0x000B8000>; + label = "image-0"; }; /* Reserve 720 kB for the application in slot 1 */ slot1_partition: partition@C4000 { - label = "image-1"; reg = <0x000C0000 0x000B8000>; + label = "image-1"; }; /* Set 16 kB of storage at the end of the 1536 kB of flash */ storage_partition: partition@17c000 { - label = "storage"; reg = <0x0017c000 DT_SIZE_K(16)>; + label = "storage"; }; }; }; diff --git a/boards/segger/ip_k66f/ip_k66f.yaml b/boards/segger/ip_k66f/ip_k66f.yaml index 0ce51cd967d..19455195664 100644 --- a/boards/segger/ip_k66f/ip_k66f.yaml +++ b/boards/segger/ip_k66f/ip_k66f.yaml @@ -14,4 +14,3 @@ supported: - netif:eth ram: 256 flash: 2048 -vendor: nxp diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120-pinctrl.dtsi b/boards/sensry/ganymed_bob/ganymed_bob_sy120-pinctrl.dtsi index 97649fe985f..45b41f9ede3 100644 --- a/boards/sensry/ganymed_bob/ganymed_bob_sy120-pinctrl.dtsi +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120-pinctrl.dtsi @@ -114,26 +114,32 @@ /omit-if-no-ref/ rgmii_tx_ctl: rgmii_tx_ctl { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_tx_clk: rgmii_tx_clk { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_txd0: rgmii_txd0 { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_txd1: rgmii_txd1 { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_txd2: rgmii_txd2 { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_txd3: rgmii_txd3 { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_rxd0: rgmii_rxd0 { diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120-pinctrl.dtsi b/boards/sensry/ganymed_sk/ganymed_sk_sy120-pinctrl.dtsi index 09a8fa16f88..efed873377c 100644 --- a/boards/sensry/ganymed_sk/ganymed_sk_sy120-pinctrl.dtsi +++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120-pinctrl.dtsi @@ -114,26 +114,32 @@ /omit-if-no-ref/ rgmii_tx_ctl: rgmii_tx_ctl { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_tx_clk: rgmii_tx_clk { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_txd0: rgmii_txd0 { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_txd1: rgmii_txd1 { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_txd2: rgmii_txd2 { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_txd3: rgmii_txd3 { pinmux = ; + slew-rate = <3>; }; /omit-if-no-ref/ rgmii_rxd0: rgmii_rxd0 { diff --git a/boards/shields/abrobot_esp32c3_oled/shield.yml b/boards/shields/abrobot_esp32c3_oled/shield.yml new file mode 100644 index 00000000000..ce4db2f3b0e --- /dev/null +++ b/boards/shields/abrobot_esp32c3_oled/shield.yml @@ -0,0 +1,6 @@ +shield: + name: abrobot_sh1106_72x40 + full_name: ABRobot ESP32C3 OLED Shield + vendor: others + supported_features: + - display diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/shield.yml b/boards/shields/adafruit_2_8_tft_touch_v2/shield.yml new file mode 100644 index 00000000000..5067bb7a997 --- /dev/null +++ b/boards/shields/adafruit_2_8_tft_touch_v2/shield.yml @@ -0,0 +1,16 @@ +shields: + - name: adafruit_2_8_tft_touch_v2 + full_name: Adafruit 2.8" TFT Touch Shield V2 (Uno) + vendor: adafruit + supported_features: + - display + - input + - sdhc + + - name: adafruit_2_8_tft_touch_v2_nano + full_name: Adafruit 2.8" TFT Touch Shield V2 (Nano) + vendor: adafruit + supported_features: + - display + - input + - sdhc diff --git a/boards/shields/adafruit_adalogger_featherwing/shield.yml b/boards/shields/adafruit_adalogger_featherwing/shield.yml new file mode 100644 index 00000000000..5bad1a45281 --- /dev/null +++ b/boards/shields/adafruit_adalogger_featherwing/shield.yml @@ -0,0 +1,7 @@ +shield: + name: adafruit_adalogger_featherwing + full_name: Adafruit Adalogger FeatherWing + vendor: adafruit + supported_features: + - sdhc + - rtc diff --git a/boards/shields/adafruit_aw9523/shield.yml b/boards/shields/adafruit_aw9523/shield.yml new file mode 100644 index 00000000000..db9dd1d3158 --- /dev/null +++ b/boards/shields/adafruit_aw9523/shield.yml @@ -0,0 +1,7 @@ +shield: + name: adafruit_aw9523 + full_name: Adafruit AW9523 GPIO Expander and LED Driver + vendor: adafruit + supported_features: + - mfd + - gpio diff --git a/boards/shields/adafruit_data_logger/shield.yml b/boards/shields/adafruit_data_logger/shield.yml new file mode 100644 index 00000000000..fe7f6ad7fb4 --- /dev/null +++ b/boards/shields/adafruit_data_logger/shield.yml @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024, Nordic Semiconductor ASA + +shield: + name: adafruit_data_logger + full_name: Adafruit Data Logger Shield + vendor: adafruit + supported_features: + - rtc + - sdhc diff --git a/boards/shields/adafruit_neopixel_grid_bff/shield.yml b/boards/shields/adafruit_neopixel_grid_bff/shield.yml new file mode 100644 index 00000000000..cad7e55d105 --- /dev/null +++ b/boards/shields/adafruit_neopixel_grid_bff/shield.yml @@ -0,0 +1,13 @@ +shields: + - name: adafruit_neopixel_grid_bff + full_name: Adafruit NeoPixel Grid BFF + vendor: adafruit + supported_features: + - led_strip + + - name: adafruit_neopixel_grid_bff_display + full_name: Adafruit NeoPixel Grid BFF (with display matrix) + vendor: adafruit + supported_features: + - led_strip + - display diff --git a/boards/shields/adafruit_pca9685/shield.yml b/boards/shields/adafruit_pca9685/shield.yml new file mode 100644 index 00000000000..df816cabfc1 --- /dev/null +++ b/boards/shields/adafruit_pca9685/shield.yml @@ -0,0 +1,6 @@ +shield: + name: adafruit_pca9685 + full_name: Adafruit PCA9685 PWM Shield + vendor: adafruit + supported_features: + - pwm diff --git a/boards/shields/adafruit_winc1500/shield.yml b/boards/shields/adafruit_winc1500/shield.yml new file mode 100644 index 00000000000..0228c1425b0 --- /dev/null +++ b/boards/shields/adafruit_winc1500/shield.yml @@ -0,0 +1,6 @@ +shield: + name: adafruit_winc1500 + full_name: Adafruit WINC1500 WiFi Shield + vendor: adafruit + supported_features: + - wifi diff --git a/boards/shields/amg88xx/doc/AMG88XX_panasonic_grid_eye_evaluation_kit.png b/boards/shields/amg88xx/doc/amg88xx_eval_kit.png similarity index 100% rename from boards/shields/amg88xx/doc/AMG88XX_panasonic_grid_eye_evaluation_kit.png rename to boards/shields/amg88xx/doc/amg88xx_eval_kit.png diff --git a/boards/shields/amg88xx/doc/AMG88XX_panasonic_grid_eye_evaluation_shield.png b/boards/shields/amg88xx/doc/amg88xx_grid_eye_eval_shield.png similarity index 100% rename from boards/shields/amg88xx/doc/AMG88XX_panasonic_grid_eye_evaluation_shield.png rename to boards/shields/amg88xx/doc/amg88xx_grid_eye_eval_shield.png diff --git a/boards/shields/amg88xx/doc/index.rst b/boards/shields/amg88xx/doc/index.rst index 166b64dd5e2..a307c3e00ea 100644 --- a/boards/shields/amg88xx/doc/index.rst +++ b/boards/shields/amg88xx/doc/index.rst @@ -24,7 +24,7 @@ For sensor evaluation and rapid prototyping multiple shields are available: - `Panasonic Grid-EYE Evaluation Shield`_ - .. figure:: AMG88XX_panasonic_grid_eye_evaluation_shield.png + .. figure:: amg88xx_grid_eye_eval_shield.png :width: 300px :align: center :alt: Panasonic Grid-EYE Evaluation Shield @@ -45,7 +45,7 @@ also could be used as an Arduino shield. - Panasonic Grid-EYE Evaluation Kit - .. figure:: AMG88XX_panasonic_grid_eye_evaluation_kit.png + .. figure:: amg88xx_eval_kit.png :width: 250px :align: center :alt: Panasonic Grid-EYE Evaluation Kit (deprecated) diff --git a/boards/shields/amg88xx/shield.yml b/boards/shields/amg88xx/shield.yml new file mode 100644 index 00000000000..ac2d621a0c6 --- /dev/null +++ b/boards/shields/amg88xx/shield.yml @@ -0,0 +1,12 @@ +shields: + - name: amg88xx_grid_eye_eval_shield + full_name: Panasonic Grid-EYE Evaluation Shield + vendor: panasonic + supported_features: + - sensor + + - name: amg88xx_eval_kit + full_name: Panasonic Grid-EYE Evaluation Kit + vendor: panasonic + supported_features: + - sensor diff --git a/boards/shields/arceli_eth_w5500/shield.yml b/boards/shields/arceli_eth_w5500/shield.yml new file mode 100644 index 00000000000..16083e97559 --- /dev/null +++ b/boards/shields/arceli_eth_w5500/shield.yml @@ -0,0 +1,6 @@ +shield: + name: arceli_eth_w5500 + full_name: Arceli ETH W5500 Shield + vendor: wiznet + supported_features: + - ethernet diff --git a/boards/shields/arduino_giga_display_shield/giga_display_shield.overlay b/boards/shields/arduino_giga_display_shield/arduino_giga_display_shield.overlay similarity index 100% rename from boards/shields/arduino_giga_display_shield/giga_display_shield.overlay rename to boards/shields/arduino_giga_display_shield/arduino_giga_display_shield.overlay diff --git a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf index 881770e9f68..27961f09f2f 100644 --- a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf +++ b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf @@ -6,4 +6,3 @@ CONFIG_STM32_LTDC_RGB565=y CONFIG_DISPLAY_INIT_PRIORITY=87 CONFIG_STM32_LTDC_DISABLE_FMC_BANK1=y CONFIG_INPUT_GT911_INTERRUPT=y -CONFIG_STM32_LTDC_FB_USE_SHARED_MULTI_HEAP=y diff --git a/boards/shields/arduino_giga_display_shield/doc/index.rst b/boards/shields/arduino_giga_display_shield/doc/index.rst index b2834b23520..6ef0cc47e04 100644 --- a/boards/shields/arduino_giga_display_shield/doc/index.rst +++ b/boards/shields/arduino_giga_display_shield/doc/index.rst @@ -40,7 +40,7 @@ for projects utilizing this shield. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: arduino_giga_r1_wifi + :board: arduino_giga_r1/stm32h747xx/m7 :shield: arduino_giga_display_shield :goals: build diff --git a/boards/shields/arduino_giga_display_shield/shield.yml b/boards/shields/arduino_giga_display_shield/shield.yml new file mode 100644 index 00000000000..22a83668222 --- /dev/null +++ b/boards/shields/arduino_giga_display_shield/shield.yml @@ -0,0 +1,6 @@ +shield: + name: arduino_giga_display_shield + full_name: Arduino GIGA Display Shield + vendor: arduino + supported_features: + - display diff --git a/boards/shields/arduino_modulino_buttons/Kconfig.shield b/boards/shields/arduino_modulino_buttons/Kconfig.shield new file mode 100644 index 00000000000..1389b0d5036 --- /dev/null +++ b/boards/shields/arduino_modulino_buttons/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2025 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ARDUINO_MODULINO_BUTTONS + def_bool $(shields_list_contains,arduino_modulino_buttons) diff --git a/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay b/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay new file mode 100644 index 00000000000..96c84cbfb43 --- /dev/null +++ b/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay @@ -0,0 +1,27 @@ +/* + * Copyright 2025 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&qwiic_i2c { + modulino-buttons@3e { + compatible = "i2c-device"; + reg = <0x3e>; + + modulino_buttons: modulino-buttons { + compatible = "arduino,modulino-buttons"; + zephyr,codes = , + , + ; + }; + + modulino_leds: modulino-leds { + compatible = "arduino,modulino-buttons-leds"; + }; + }; + +}; diff --git a/boards/shields/arduino_modulino_buttons/doc/img/arduino_modulino_buttons.webp b/boards/shields/arduino_modulino_buttons/doc/img/arduino_modulino_buttons.webp new file mode 100644 index 00000000000..c003d3358a5 Binary files /dev/null and b/boards/shields/arduino_modulino_buttons/doc/img/arduino_modulino_buttons.webp differ diff --git a/boards/shields/arduino_modulino_buttons/doc/index.rst b/boards/shields/arduino_modulino_buttons/doc/index.rst new file mode 100644 index 00000000000..3d5f428b1d9 --- /dev/null +++ b/boards/shields/arduino_modulino_buttons/doc/index.rst @@ -0,0 +1,30 @@ +.. _arduino_modulino_buttons: + +Arduino Modulino Buttons +######################## + +Overview +******** + +The Arduino Modulino Buttons is a QWIIC compatible module with three buttons +and three LEDs. + + +.. image:: img/arduino_modulino_buttons.webp + :align: center + :alt: Arduino Modulino Buttons module + +Programming +*********** + +Set ``--shield arduino_modulino_buttons`` when you invoke ``west build``, the +buttons will be available through the input subsystem and the LEDs through the +LED subsystem. + +For example, + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/input + :board: arduino_uno_r4@wifi + :shield: arduino_modulino_buttons + :goals: build diff --git a/boards/shields/arduino_modulino_buttons/shield.yml b/boards/shields/arduino_modulino_buttons/shield.yml new file mode 100644 index 00000000000..6fca86f2065 --- /dev/null +++ b/boards/shields/arduino_modulino_buttons/shield.yml @@ -0,0 +1,7 @@ +shield: + name: arduino_modulino_buttons + full_name: Arduino Modulino Buttons + vendor: arduino + supported_features: + - input + - led diff --git a/boards/shields/arduino_modulino_smartleds/Kconfig.shield b/boards/shields/arduino_modulino_smartleds/Kconfig.shield new file mode 100644 index 00000000000..8ae10346405 --- /dev/null +++ b/boards/shields/arduino_modulino_smartleds/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2025 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ARDUINO_MODULINO_SMARTLEDS + def_bool $(shields_list_contains,arduino_modulino_smartleds) diff --git a/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay b/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay new file mode 100644 index 00000000000..8873c1312bb --- /dev/null +++ b/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay @@ -0,0 +1,24 @@ +/* + * Copyright 2025 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + led-strip = &modulino_smartleds; + }; +}; + +&qwiic_i2c { + modulino_smartleds: modulino-smartleds@36 { + compatible = "arduino,modulino-smartleds"; + reg = <0x36>; + chain-length = <8>; + color-mapping = ; + }; +}; diff --git a/boards/shields/arduino_modulino_smartleds/doc/img/arduino_modulino_smartleds.webp b/boards/shields/arduino_modulino_smartleds/doc/img/arduino_modulino_smartleds.webp new file mode 100644 index 00000000000..7e5d6c5a54b Binary files /dev/null and b/boards/shields/arduino_modulino_smartleds/doc/img/arduino_modulino_smartleds.webp differ diff --git a/boards/shields/arduino_modulino_smartleds/doc/index.rst b/boards/shields/arduino_modulino_smartleds/doc/index.rst new file mode 100644 index 00000000000..f0f70ac4d3d --- /dev/null +++ b/boards/shields/arduino_modulino_smartleds/doc/index.rst @@ -0,0 +1,29 @@ +.. _arduino_modulino_smartleds: + +Arduino Modulino smart LEDs +########################### + +Overview +******** + +The Arduino Modulino smart LEDs is a QWIIC compatible module with 8 addressable +LEDs. + + +.. image:: img/arduino_modulino_smartleds.webp + :align: center + :alt: Arduino Modulino Smart LEDs + +Programming +*********** + +Set ``--shield arduino_modulino_smartleds`` when you invoke ``west build``, the +leds will be available through the LED strip subsystem. + +For example, + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip + :board: arduino_uno_r4@wifi + :shield: arduino_modulino_smartleds + :goals: build diff --git a/boards/shields/arduino_modulino_smartleds/shield.yml b/boards/shields/arduino_modulino_smartleds/shield.yml new file mode 100644 index 00000000000..bbae23420d4 --- /dev/null +++ b/boards/shields/arduino_modulino_smartleds/shield.yml @@ -0,0 +1,6 @@ +shield: + name: arduino_modulino_smartleds + full_name: Arduino Modulino SmartLEDs + vendor: arduino + supported_features: + - led_strip diff --git a/boards/shields/arduino_uno_click/shield.yml b/boards/shields/arduino_uno_click/shield.yml new file mode 100644 index 00000000000..311b36ff122 --- /dev/null +++ b/boards/shields/arduino_uno_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: arduino_uno_click + full_name: Arduino UNO Click + vendor: arduino + supported_features: + - gpio diff --git a/boards/shields/atmel_rf2xx/shield.yml b/boards/shields/atmel_rf2xx/shield.yml new file mode 100644 index 00000000000..ed706b102d0 --- /dev/null +++ b/boards/shields/atmel_rf2xx/shield.yml @@ -0,0 +1,34 @@ +shields: + - name: atmel_rf2xx + full_name: Atmel AT86RF2XX Transceiver + vendor: atmel + + - name: atmel_rf2xx_arduino + full_name: Atmel AT86RF2XX Transceiver for Arduino + vendor: atmel + supported_features: + - ieee802154 + + - name: atmel_rf2xx_legacy + full_name: Atmel AT86RF2XX Transceiver for Atmel Xplained (legacy) + vendor: atmel + supported_features: + - ieee802154 + + - name: atmel_rf2xx_mikrobus + full_name: Atmel AT86RF2XX Transceiver for MikroBUS + vendor: atmel + supported_features: + - ieee802154 + + - name: atmel_rf2xx_xplained + full_name: Atmel AT86RF2XX Transceiver for Atmel Xplained + vendor: atmel + supported_features: + - ieee802154 + + - name: atmel_rf2xx_xpro + full_name: Atmel AT86RF2XX Transceiver for Atmel Xplained Pro + vendor: atmel + supported_features: + - ieee802154 diff --git a/boards/shields/boostxl_ulpsense/shield.yml b/boards/shields/boostxl_ulpsense/shield.yml new file mode 100644 index 00000000000..b4c5b5ca8fa --- /dev/null +++ b/boards/shields/boostxl_ulpsense/shield.yml @@ -0,0 +1,6 @@ +shield: + name: boostxl_ulpsense + full_name: BOOSTXL-ULPSENSE + vendor: ti + supported_features: + - sensor diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/shield.yml b/boards/shields/buydisplay_2_8_tft_touch_arduino/shield.yml new file mode 100644 index 00000000000..af1039a4cff --- /dev/null +++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/shield.yml @@ -0,0 +1,7 @@ +shield: + name: buydisplay_2_8_tft_touch_arduino + full_name: BuyDisplay 2.8" TFT Touch Shield + vendor: gooddisplay + supported_features: + - input + - display diff --git a/boards/shields/buydisplay_3_5_tft_touch_arduino/shield.yml b/boards/shields/buydisplay_3_5_tft_touch_arduino/shield.yml new file mode 100644 index 00000000000..b901de44537 --- /dev/null +++ b/boards/shields/buydisplay_3_5_tft_touch_arduino/shield.yml @@ -0,0 +1,7 @@ +shield: + name: buydisplay_3_5_tft_touch_arduino + full_name: BuyDisplay 3.5" TFT Touch Shield + vendor: gooddisplay + supported_features: + - input + - display diff --git a/boards/shields/dac80508_evm/shield.yml b/boards/shields/dac80508_evm/shield.yml new file mode 100644 index 00000000000..ee0aba3948b --- /dev/null +++ b/boards/shields/dac80508_evm/shield.yml @@ -0,0 +1,6 @@ +shields: + - name: dac80508_evm + full_name: DAC80508 Evaluation Module + vendor: ti + supported_features: + - dac diff --git a/boards/shields/dvp_20pin_ov7670/Kconfig.shield b/boards/shields/dvp_20pin_ov7670/Kconfig.shield new file mode 100644 index 00000000000..f063d3d731e --- /dev/null +++ b/boards/shields/dvp_20pin_ov7670/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2025 tinyVision.ai Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_DVP_20PIN_OV7670 + def_bool $(shields_list_contains,dvp_20pin_ov7670) diff --git a/boards/shields/dvp_20pin_ov7670/doc/index.rst b/boards/shields/dvp_20pin_ov7670/doc/index.rst new file mode 100644 index 00000000000..88e0d1bf28d --- /dev/null +++ b/boards/shields/dvp_20pin_ov7670/doc/index.rst @@ -0,0 +1,81 @@ +.. _dvp_20pin_ov7670: + +DVP 20-pin OV7670 Camera Module +############################### + +Overview +******** + +This series of shields supports the camera modules which use a 18-pin connector compatible with +the :dtcompatible:`arducam,dvp-20pin-connector` to connect a devkit to an OV7670 image sensor via +DVP (Digital Video Port), also known as "parallel interface". + +Only 18 pins out of the 20-pin connector are present. + +It was originally produced by `Arducam`_ but is discontinuited, and now `Olimex`_ provides it. + +Pins assignment +=============== + ++-----+--------------+-----+--------------+ +| Pin | Function | Pin | Function | ++=====+==============+=====+==============+ +| 1 | 3V3 | 2 | GND | ++-----+--------------+-----+--------------+ +| 3 | SCL | 4 | SDA | ++-----+--------------+-----+--------------+ +| 5 | VS | 6 | HS | ++-----+--------------+-----+--------------+ +| 7 | PCLK | 8 | XCLK | ++-----+--------------+-----+--------------+ +| 9 | D7 | 10 | D6 | ++-----+--------------+-----+--------------+ +| 11 | D5 | 12 | D4 | ++-----+--------------+-----+--------------+ +| 13 | D3 | 14 | D2 | ++-----+--------------+-----+--------------+ +| 15 | D1 | 16 | D0 | ++-----+--------------+-----+--------------+ +| 17 | POWER_EN | 18 | POWER_DOWN | ++-----+--------------+-----+--------------+ + +Requirements +************ + +This shield can be used with any board that provides an 18 or 20-pin header spread over two rows +of 9 or 10 pins each with the above pinout, such as the `arduino Giga R1`_, `NXP FRDM-MCXN947`_, +ST boards with the `ST-CAMS-OMV`_ adapter, or any other board with a compatible connector. + +Alternatively, it is possible to use jumper wires to connect the module to any devkit that +exposes their camera parallel port to pin headers. + +Programming +*********** + +Set ``--shield dvp_20pin_ov7670`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/video/capture + :board: frdm_mcxn947 + :shield: dvp_20pin_ov7670 + :goals: build + +References +********** + +.. target-notes:: + +.. _ST-CAMS-OMV: + https://www.st.com/en/evaluation-tools/b-cams-omv.html + +.. _Arducam: + https://docs.arducam.com/DVP-Camera-Module/Arduino-GIGA/Arduino-GIGA/Quick-Start-Guide/ + +.. _Arduino Giga R1: + https://docs.arduino.cc/tutorials/giga-r1-wifi/giga-camera/ + +.. _NXP FRDM-MCXN947: + https://www.nxp.com/docs/en/application-note/AN14191.pdf + +.. _Olimex: + https://www.olimex.com/Products/Components/Camera/CAMERA-OV7670/ diff --git a/boards/shields/dvp_20pin_ov7670/dvp_20pin_ov7670.overlay b/boards/shields/dvp_20pin_ov7670/dvp_20pin_ov7670.overlay new file mode 100644 index 00000000000..234c33c2d5f --- /dev/null +++ b/boards/shields/dvp_20pin_ov7670/dvp_20pin_ov7670.overlay @@ -0,0 +1,37 @@ +/* + * Copyright 2024 NXP + * Copyright 2025 tinyVision.ai Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,camera = &dvp_20pin_interface; + }; +}; + +&dvp_20pin_i2c { + ov7670: ov7670@21 { + compatible = "ovti,ov7670"; + reg = <0x21>; + reset-gpios = <&dvp_20pin_connector DVP_20PIN_PEN GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&dvp_20pin_connector DVP_20PIN_PDN GPIO_ACTIVE_HIGH>; + + port { + ov7670_ep_out: endpoint { + remote-endpoint-label = "dvp_20pin_ep_in"; + }; + }; + }; +}; + +&dvp_20pin_interface { + status = "okay"; + + port { + dvp_20pin_ep_in: endpoint { + remote-endpoint-label = "ov7670_ep_out"; + }; + }; +}; diff --git a/boards/shields/dvp_20pin_ov7670/shield.yml b/boards/shields/dvp_20pin_ov7670/shield.yml new file mode 100644 index 00000000000..23d88ef7dc4 --- /dev/null +++ b/boards/shields/dvp_20pin_ov7670/shield.yml @@ -0,0 +1,6 @@ +shield: + name: dvp_20pin_ov7670 + full_name: DVP 20-pin OV7670 Camera Shield + vendor: ovti + supported_features: + - video diff --git a/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield b/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield index 187fbec05cb..ebcc4f73c02 100644 --- a/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield +++ b/boards/shields/dvp_fpc24_mt9m114/Kconfig.shield @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config SHIELD_DVP_FPC24_MT9M114 - def_bool $(shields_list_contains,DVP_FPC24_MT9M114) + def_bool $(shields_list_contains,dvp_fpc24_mt9m114) diff --git a/boards/shields/dvp_fpc24_mt9m114/shield.yml b/boards/shields/dvp_fpc24_mt9m114/shield.yml new file mode 100644 index 00000000000..9757add7dbb --- /dev/null +++ b/boards/shields/dvp_fpc24_mt9m114/shield.yml @@ -0,0 +1,6 @@ +shield: + name: dvp_fpc24_mt9m114 + full_name: DVP FPC-24 MT9M114 Camera Module + vendor: aptina + supported_features: + - video diff --git a/boards/shields/esp_8266/shield.yml b/boards/shields/esp_8266/shield.yml new file mode 100644 index 00000000000..109f1492447 --- /dev/null +++ b/boards/shields/esp_8266/shield.yml @@ -0,0 +1,18 @@ +shields: + - name: esp_8266 + full_name: ESP-8266 Module + vendor: espressif + supported_features: + - wifi + + - name: esp_8266_arduino + full_name: ESP-8266 Module (Arduino) + vendor: espressif + supported_features: + - wifi + + - name: esp_8266_mikrobus + full_name: ESP-8266 Module (MikroBus) + vendor: espressif + supported_features: + - wifi diff --git a/boards/shields/eval_ad4052_ardz/doc/eval_ad4052_ardz.webp b/boards/shields/eval_ad4052_ardz/doc/eval_ad4052_ardz.webp new file mode 100644 index 00000000000..27a9fe4f7d9 Binary files /dev/null and b/boards/shields/eval_ad4052_ardz/doc/eval_ad4052_ardz.webp differ diff --git a/boards/shields/eval_ad4052_ardz/shield.yml b/boards/shields/eval_ad4052_ardz/shield.yml new file mode 100644 index 00000000000..69c46837bc3 --- /dev/null +++ b/boards/shields/eval_ad4052_ardz/shield.yml @@ -0,0 +1,6 @@ +shield: + name: eval_ad4052_ardz + full_name: AD4052 Evaluation Shield + vendor: adi + supported_features: + - adc diff --git a/boards/shields/eval_adxl362_ardz/doc/eval_adxl362_ardz.webp b/boards/shields/eval_adxl362_ardz/doc/eval_adxl362_ardz.webp new file mode 100644 index 00000000000..1a941d26e65 Binary files /dev/null and b/boards/shields/eval_adxl362_ardz/doc/eval_adxl362_ardz.webp differ diff --git a/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay b/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay index d5b63252656..777730ccf7e 100644 --- a/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay +++ b/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + &arduino_spi { status = "okay"; @@ -12,6 +14,8 @@ reg = <0x0>; spi-max-frequency = ; int1-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; + fifo-mode = ; + fifo-watermark = <0x80>; status = "okay"; }; }; diff --git a/boards/shields/eval_adxl362_ardz/shield.yml b/boards/shields/eval_adxl362_ardz/shield.yml new file mode 100644 index 00000000000..3724616c056 --- /dev/null +++ b/boards/shields/eval_adxl362_ardz/shield.yml @@ -0,0 +1,6 @@ +shield: + name: eval_adxl362_ardz + full_name: ADXL362 Evaluation Shield + vendor: adi + supported_features: + - sensor diff --git a/boards/shields/eval_adxl367_ardz/Kconfig.shield b/boards/shields/eval_adxl367_ardz/Kconfig.shield new file mode 100644 index 00000000000..dbccde37566 --- /dev/null +++ b/boards/shields/eval_adxl367_ardz/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_EVAL_ADXL367_ARDZ + def_bool $(shields_list_contains,eval_adxl367_ardz) diff --git a/boards/shields/eval_adxl367_ardz/doc/eval_adxl367_ardz.webp b/boards/shields/eval_adxl367_ardz/doc/eval_adxl367_ardz.webp new file mode 100644 index 00000000000..8f3e5beeaa1 Binary files /dev/null and b/boards/shields/eval_adxl367_ardz/doc/eval_adxl367_ardz.webp differ diff --git a/boards/shields/eval_adxl367_ardz/doc/index.rst b/boards/shields/eval_adxl367_ardz/doc/index.rst new file mode 100644 index 00000000000..e144b28ecfe --- /dev/null +++ b/boards/shields/eval_adxl367_ardz/doc/index.rst @@ -0,0 +1,40 @@ +.. _eval_adxl367_ardz: + +EVAL-ADXL367-ARDZ +################# + +Overview +******** + +The EVAL-ADXL367-ARDZ is a 3-axis digital accelerometer Arduino shield powered +by the Analog Devices ADXL367. + +Programming +*********** + +Set ``--shield eval_adxl367_ardz`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: apard32690/max32690/m4 + :shield: eval_adxl367_ardz + :goals: build + +Requirements +************ + +This shield can only be used with a board which provides a configuration for +Arduino connectors and defines node aliases for SPI and GPIO interfaces (see +:ref:`shields` for more details). + +References +********** + +- `ADXL367 product page`_ +- `ADXL367 data sheet`_ + +.. _ADXL367 product page: + https://www.analog.com/en/products/adxl367.html + +.. _ADXL367 data sheet: + https://www.analog.com/media/en/technical-documentation/data-sheets/adxl367.pdf diff --git a/boards/shields/eval_adxl367_ardz/eval_adxl367_ardz.overlay b/boards/shields/eval_adxl367_ardz/eval_adxl367_ardz.overlay new file mode 100644 index 00000000000..98ab6236991 --- /dev/null +++ b/boards/shields/eval_adxl367_ardz/eval_adxl367_ardz.overlay @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + accel0 = &adxl367_eval_adxl367_ardz; + }; +}; + +&arduino_spi { + status = "okay"; + + adxl367_eval_adxl367_ardz: adxl367@0 { + compatible = "adi,adxl367"; + reg = <0x0>; + spi-max-frequency = ; + int1-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; + fifo-mode = ; + status = "okay"; + }; +}; diff --git a/boards/shields/eval_adxl367_ardz/shield.yml b/boards/shields/eval_adxl367_ardz/shield.yml new file mode 100644 index 00000000000..3bea673c1f4 --- /dev/null +++ b/boards/shields/eval_adxl367_ardz/shield.yml @@ -0,0 +1,6 @@ +shield: + name: eval_adxl367_ardz + full_name: ADXL367 Evaluation Shield + vendor: adi + supported_features: + - sensor diff --git a/boards/shields/eval_adxl372_ardz/doc/eval_adxl372_ardz.webp b/boards/shields/eval_adxl372_ardz/doc/eval_adxl372_ardz.webp new file mode 100644 index 00000000000..8f3e5beeaa1 Binary files /dev/null and b/boards/shields/eval_adxl372_ardz/doc/eval_adxl372_ardz.webp differ diff --git a/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay b/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay index 349374a7c7a..a7579e16c71 100644 --- a/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay +++ b/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay @@ -4,6 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + + &arduino_spi { status = "okay"; @@ -12,6 +15,8 @@ reg = <0x0>; spi-max-frequency = ; int1-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; + fifo-mode = ; + fifo-watermark = <0x80>; status = "okay"; }; }; diff --git a/boards/shields/eval_adxl372_ardz/shield.yml b/boards/shields/eval_adxl372_ardz/shield.yml new file mode 100644 index 00000000000..a2087b5d93d --- /dev/null +++ b/boards/shields/eval_adxl372_ardz/shield.yml @@ -0,0 +1,6 @@ +shield: + name: eval_adxl372_ardz + full_name: ADXL372 Evaluation Shield + vendor: adi + supported_features: + - sensor diff --git a/boards/shields/frdm_cr20a/shield.yml b/boards/shields/frdm_cr20a/shield.yml new file mode 100644 index 00000000000..182db924f08 --- /dev/null +++ b/boards/shields/frdm_cr20a/shield.yml @@ -0,0 +1,6 @@ +shield: + name: frdm_cr20a + full_name: FRDM-CR20A + vendor: nxp + supported_features: + - ieee802154 diff --git a/boards/shields/frdm_kw41z/shield.yml b/boards/shields/frdm_kw41z/shield.yml new file mode 100644 index 00000000000..ecc2bbf5658 --- /dev/null +++ b/boards/shields/frdm_kw41z/shield.yml @@ -0,0 +1,6 @@ +shield: + name: frdm_kw41z + full_name: FRDM-KW41Z + vendor: nxp + supported_features: + - bluetooth diff --git a/boards/shields/frdm_stbc_agm01/shield.yml b/boards/shields/frdm_stbc_agm01/shield.yml new file mode 100644 index 00000000000..ac51a2b72fd --- /dev/null +++ b/boards/shields/frdm_stbc_agm01/shield.yml @@ -0,0 +1,6 @@ +shield: + name: frdm_stbc_agm01 + full_name: FRDM-ST BC-AGM01 + vendor: nxp + supported_features: + - sensor diff --git a/boards/shields/ftdi_vm800c/shield.yml b/boards/shields/ftdi_vm800c/shield.yml new file mode 100644 index 00000000000..aa4d8411f45 --- /dev/null +++ b/boards/shields/ftdi_vm800c/shield.yml @@ -0,0 +1,6 @@ +shield: + name: ftdi_vm800c + full_name: FTDI VM800C Display Shield + vendor: ftdi + supported_features: + - display diff --git a/boards/shields/g1120b0mipi/shield.yml b/boards/shields/g1120b0mipi/shield.yml new file mode 100644 index 00000000000..dd22248e89b --- /dev/null +++ b/boards/shields/g1120b0mipi/shield.yml @@ -0,0 +1,6 @@ +shield: + name: g1120b0mipi + full_name: G1120B0 MIPI Display Shield + vendor: boe + supported_features: + - display diff --git a/boards/shields/index.rst b/boards/shields/index.rst new file mode 100644 index 00000000000..a2bfea271ce --- /dev/null +++ b/boards/shields/index.rst @@ -0,0 +1,8 @@ +Shields +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/shields/inventek_eswifi/shield.yml b/boards/shields/inventek_eswifi/shield.yml new file mode 100644 index 00000000000..beb9e6130f3 --- /dev/null +++ b/boards/shields/inventek_eswifi/shield.yml @@ -0,0 +1,16 @@ +shields: + - name: inventek_eswifi + full_name: Inventek es-WIFI Shield (generic) + vendor: inventek + + - name: inventek_eswifi_arduino_spi + full_name: Inventek es-WIFI Shield (SPI) + vendor: inventek + supported_features: + - wifi + + - name: inventek_eswifi_arduino_uart + full_name: Inventek es-WIFI Mini Shield (UART) + vendor: inventek + supported_features: + - wifi diff --git a/boards/shields/lcd_par_s035/shield.yml b/boards/shields/lcd_par_s035/shield.yml new file mode 100644 index 00000000000..ea1ae5603a0 --- /dev/null +++ b/boards/shields/lcd_par_s035/shield.yml @@ -0,0 +1,14 @@ +shields: + - name: lcd_par_s035_8080 + full_name: NXP LCD_PAR_S035 TFT LCD Module (Parallel) + vendor: nxp + supported_features: + - input + - display + + - name: lcd_par_s035_spi + full_name: NXP LCD_PAR_S035 TFT LCD Module (SPI) + vendor: nxp + supported_features: + - input + - display diff --git a/boards/shields/link_board_eth/shield.yml b/boards/shields/link_board_eth/shield.yml new file mode 100644 index 00000000000..762f8d6b063 --- /dev/null +++ b/boards/shields/link_board_eth/shield.yml @@ -0,0 +1,6 @@ +shield: + name: link_board_eth + full_name: link board ETH + vendor: phytec + supported_features: + - ethernet diff --git a/boards/shields/lmp90100_evb/shield.yml b/boards/shields/lmp90100_evb/shield.yml new file mode 100644 index 00000000000..08b7cef8ee0 --- /dev/null +++ b/boards/shields/lmp90100_evb/shield.yml @@ -0,0 +1,7 @@ +shield: + name: lmp90100_evb + full_name: LMP90100 Sensor AFE Evaluation Board + vendor: ti + supported_features: + - adc + - mtd diff --git a/boards/shields/ls0xx_generic/shield.yml b/boards/shields/ls0xx_generic/shield.yml new file mode 100644 index 00000000000..2556a30cc8a --- /dev/null +++ b/boards/shields/ls0xx_generic/shield.yml @@ -0,0 +1,6 @@ +shield: + name: ls013b7dh03 + full_name: Sharp memory display generic shield + vendor: sharp + supported_features: + - display diff --git a/boards/shields/m5stack_cardputer/shield.yml b/boards/shields/m5stack_cardputer/shield.yml new file mode 100644 index 00000000000..5da69b4e890 --- /dev/null +++ b/boards/shields/m5stack_cardputer/shield.yml @@ -0,0 +1,7 @@ +shield: + name: m5stack_cardputer + full_name: M5Stack Cardputer + vendor: m5stack + supported_features: + - display + - sdhc diff --git a/boards/shields/m5stack_core2_ext/shield.yml b/boards/shields/m5stack_core2_ext/shield.yml new file mode 100644 index 00000000000..16fce341d38 --- /dev/null +++ b/boards/shields/m5stack_core2_ext/shield.yml @@ -0,0 +1,6 @@ +shield: + name: m5stack_core2_ext + full_name: M5Stack-Core2 base shield + vendor: m5stack + supported_features: + - sensor diff --git a/boards/shields/max3421e/shield.yml b/boards/shields/max3421e/shield.yml new file mode 100644 index 00000000000..4a65f5c7913 --- /dev/null +++ b/boards/shields/max3421e/shield.yml @@ -0,0 +1,6 @@ +shields: + - name: sparkfun_max3421e + full_name: SparkFun USB Host Shield + vendor: sparkfun + supported_features: + - usb diff --git a/boards/shields/max7219/shield.yml b/boards/shields/max7219/shield.yml new file mode 100644 index 00000000000..c30d60b0b3b --- /dev/null +++ b/boards/shields/max7219/shield.yml @@ -0,0 +1,6 @@ +shields: + - name: max7219_8x8 + full_name: MAX7219 8x8 Display shield + vendor: others + supported_features: + - display diff --git a/boards/shields/mcp2515/shield.yml b/boards/shields/mcp2515/shield.yml new file mode 100644 index 00000000000..e5fca9355fc --- /dev/null +++ b/boards/shields/mcp2515/shield.yml @@ -0,0 +1,18 @@ +shields: + - name: adafruit_can_picowbell + full_name: PiCowbell CAN Bus for Pico + vendor: adafruit + supported_features: + - can + + - name: dfrobot_can_bus_v2_0 + full_name: CAN-BUS Shield V2 + vendor: dfrobot + supported_features: + - can + + - name: keyestudio_can_bus_ks0411 + full_name: Keyestudio CAN-BUS Shield + vendor: others + supported_features: + - can diff --git a/boards/shields/mikroe_accel13_click/shield.yml b/boards/shields/mikroe_accel13_click/shield.yml new file mode 100644 index 00000000000..4e877d2c7a7 --- /dev/null +++ b/boards/shields/mikroe_accel13_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_accel13_click + full_name: ACCEL 13 Click + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_adc_click/shield.yml b/boards/shields/mikroe_adc_click/shield.yml new file mode 100644 index 00000000000..90109123009 --- /dev/null +++ b/boards/shields/mikroe_adc_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_adc_click + full_name: ADC Click + vendor: mikroe + supported_features: + - adc diff --git a/boards/shields/mikroe_ble_tiny_click/shield.yml b/boards/shields/mikroe_ble_tiny_click/shield.yml new file mode 100644 index 00000000000..20e50770216 --- /dev/null +++ b/boards/shields/mikroe_ble_tiny_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_ble_tiny_click + full_name: BLE TINY Click + vendor: mikroe + supported_features: + - bluetooth diff --git a/boards/shields/mikroe_eth3_click/shield.yml b/boards/shields/mikroe_eth3_click/shield.yml new file mode 100644 index 00000000000..47ef8b04c73 --- /dev/null +++ b/boards/shields/mikroe_eth3_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_eth3_click + full_name: ETH3 Click + vendor: mikroe + supported_features: + - ethernet diff --git a/boards/shields/mikroe_eth_click/shield.yml b/boards/shields/mikroe_eth_click/shield.yml new file mode 100644 index 00000000000..2034b5612b7 --- /dev/null +++ b/boards/shields/mikroe_eth_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_eth_click + full_name: ETH Click + vendor: mikroe + supported_features: + - ethernet diff --git a/boards/shields/mikroe_lte_iot10_click/Kconfig.defconfig b/boards/shields/mikroe_lte_iot10_click/Kconfig.defconfig new file mode 100644 index 00000000000..580faa75d33 --- /dev/null +++ b/boards/shields/mikroe_lte_iot10_click/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Benjamin Cabé +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_MIKROE_LTE_IOT10_CLICK + +if MODEM_CELLULAR + +# Using regulator-fixed driver to pull RTS low and effectively disable flow control since it can't +# really be setup in a generic way when using shields. +config REGULATOR + default y + +endif # MODEM_CELLULAR + +endif # SHIELD_MIKROE_LTE_IOT10_CLICK diff --git a/boards/shields/mikroe_lte_iot10_click/Kconfig.shield b/boards/shields/mikroe_lte_iot10_click/Kconfig.shield new file mode 100644 index 00000000000..b685be96c91 --- /dev/null +++ b/boards/shields/mikroe_lte_iot10_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Benjamin Cabé +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_LTE_IOT10_CLICK + def_bool $(shields_list_contains,mikroe_lte_iot10_click) diff --git a/boards/shields/mikroe_lte_iot10_click/doc/index.rst b/boards/shields/mikroe_lte_iot10_click/doc/index.rst new file mode 100644 index 00000000000..5fc87969e8a --- /dev/null +++ b/boards/shields/mikroe_lte_iot10_click/doc/index.rst @@ -0,0 +1,55 @@ +.. _mikroe_lte_iot10_click_shield: + +MikroElektronika LTE IoT 10 Click +################################# + +Overview +******** + +The MikroElektronika LTE IoT 10 Click is a compact add-on board that provides reliable LTE-M and +NB-IoT connectivity for industrial and commercial IoT applications. + +This board features the Monarch 2 GM02S, a dual-mode LTE-M/NB-IoT module from Sequans (based on +Sequans SQN3430 Chipset), offering global band support from 617MHz to 2.2GHz. + +.. figure:: mikroe_lte_iot10_click.webp + :align: center + :alt: MikroElektronika LTE IoT 10 Click + + MikroElektronika LTE IoT 10 Click (Credit: MikroElektronika) + +Requirements +************ + +This shield can only be used with a development board that provides a configuration for mikroBUS +connectors and defines a ``mikrobus_serial`` node alias for the mikroBUS UART interface +(see :ref:`shields` for more details). + +For more information about the GM02S module and the LTE IoT 10 Click, you may refer to the following +documentation: + +- `GM02S Datasheet`_ +- `LTE IoT 10 Click`_ + +Programming +*********** + +Set ``--shield mikroe_lte_iot10_click`` when you invoke ``west build``. Here is an example with the +:zephyr:code-sample:`cellular-modem` code sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/net/cellular_modem + :board: ek_ra6m4 + :shield: mikroe_lte_iot10_click + :goals: build + +References +********** + +.. target-notes:: + +.. _GM02S Datasheet: + https://www.sequans.com/products-solutions/gm02s/ + +.. _LTE IoT 10 Click: + https://www.mikroe.com/lte-iot-10-click diff --git a/boards/shields/mikroe_lte_iot10_click/doc/mikroe_lte_iot10_click.webp b/boards/shields/mikroe_lte_iot10_click/doc/mikroe_lte_iot10_click.webp new file mode 100644 index 00000000000..c145040f636 Binary files /dev/null and b/boards/shields/mikroe_lte_iot10_click/doc/mikroe_lte_iot10_click.webp differ diff --git a/boards/shields/mikroe_lte_iot10_click/mikroe_lte_iot10_click.overlay b/boards/shields/mikroe_lte_iot10_click/mikroe_lte_iot10_click.overlay new file mode 100644 index 00000000000..0ca4040a381 --- /dev/null +++ b/boards/shields/mikroe_lte_iot10_click/mikroe_lte_iot10_click.overlay @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Benjamin Cabé + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + modem = &modem; + modem-uart = &mikrobus_serial; + }; + + en_rts { + compatible = "regulator-fixed"; + regulator-name = "enable-rts"; + enable-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; +}; + +&mikrobus_serial { + status = "okay"; + current-speed = <115200>; + modem: modem { + status = "okay"; + compatible = "sqn,gm02s"; + mdm-wake-gpios = <&mikrobus_header 0 (GPIO_OPEN_SOURCE | GPIO_ACTIVE_HIGH)>; + mdm-reset-gpios = <&mikrobus_header 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + }; +}; diff --git a/boards/shields/mikroe_lte_iot10_click/shield.yml b/boards/shields/mikroe_lte_iot10_click/shield.yml new file mode 100644 index 00000000000..9b373fc451e --- /dev/null +++ b/boards/shields/mikroe_lte_iot10_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_lte_iot10_click + full_name: LTE IoT 10 Click + vendor: mikroe + supported_features: + - modem diff --git a/boards/shields/mikroe_mcp2518fd_click/shield.yml b/boards/shields/mikroe_mcp2518fd_click/shield.yml new file mode 100644 index 00000000000..817ea25ca7f --- /dev/null +++ b/boards/shields/mikroe_mcp2518fd_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_mcp2518fd_click + full_name: MikroElektronika MCP2518FD Click shield + vendor: mikroe + supported_features: + - can diff --git a/boards/shields/mikroe_weather_click/shield.yml b/boards/shields/mikroe_weather_click/shield.yml new file mode 100644 index 00000000000..f565c1f1c96 --- /dev/null +++ b/boards/shields/mikroe_weather_click/shield.yml @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024, Nordic Semiconductor ASA + +shields: + - name: mikroe_weather_click_i2c + full_name: Weather Click (I2C) + vendor: mikroe + supported_features: + - sensor + + - name: mikroe_weather_click_spi + full_name: Weather Click (SPI) + vendor: mikroe + supported_features: + - sensor diff --git a/boards/shields/mikroe_wifi_bt_click/shield.yml b/boards/shields/mikroe_wifi_bt_click/shield.yml new file mode 100644 index 00000000000..65628b9addf --- /dev/null +++ b/boards/shields/mikroe_wifi_bt_click/shield.yml @@ -0,0 +1,12 @@ +shields: + - name: mikroe_wifi_bt_click_arduino + full_name: WIFI BLE Click (Arduino) + vendor: mikroe + supported_features: + - wifi + + - name: mikroe_wifi_bt_click_mikrobus + full_name: WIFI BLE Click (MikroBus) + vendor: mikroe + supported_features: + - wifi diff --git a/boards/shields/npm1100_ek/shield.yml b/boards/shields/npm1100_ek/shield.yml new file mode 100644 index 00000000000..de2c85cd344 --- /dev/null +++ b/boards/shields/npm1100_ek/shield.yml @@ -0,0 +1,6 @@ +shield: + name: npm1100_ek + full_name: nPM1100 EK + vendor: nordic + supported_features: + - regulator diff --git a/boards/shields/npm1300_ek/shield.yml b/boards/shields/npm1300_ek/shield.yml new file mode 100644 index 00000000000..8714c000881 --- /dev/null +++ b/boards/shields/npm1300_ek/shield.yml @@ -0,0 +1,11 @@ +shield: + name: npm1300_ek + full_name: nPM1300 EK + vendor: nordic + supported_features: + - mfd + - input + - gpio + - led + - regulator + - sensor diff --git a/boards/shields/npm2100_ek/Kconfig.shield b/boards/shields/npm2100_ek/Kconfig.shield new file mode 100644 index 00000000000..cbd8fff0a1c --- /dev/null +++ b/boards/shields/npm2100_ek/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_NPM2100_EK + def_bool $(shields_list_contains,npm2100_ek) diff --git a/boards/shields/npm2100_ek/doc/index.rst b/boards/shields/npm2100_ek/doc/index.rst new file mode 100644 index 00000000000..0edf2a8da21 --- /dev/null +++ b/boards/shields/npm2100_ek/doc/index.rst @@ -0,0 +1,30 @@ +.. _npm2100_ek: + +nPM2100 EK +########## + +Overview +******** + +The nPM2100 EK lets you test different functions and features of the nPM2100 +Power Management Integrated Circuit (PMIC). + +Requirements +************ + +The nPM2100 EK board is not a direct fit into an Arduino connector. However, +the Zephyr shield must be connected to the Arduino shield connectors. That is, +you need to connect the I2C lines to the ``arduino_i2c`` bus. This allows to +use the shield with any host board that supports the Arduino connector. + +Usage +***** + +To use the shield in any application, build it with the following command: + +.. zephyr-app-commands:: + :board: your_board + :shield: npm2100_ek + :goals: build + +For a comprehensive sample, refer to :zephyr:code-sample:`npm2100_ek`. diff --git a/boards/shields/npm2100_ek/npm2100_ek.overlay b/boards/shields/npm2100_ek/npm2100_ek.overlay new file mode 100644 index 00000000000..5db980a9afc --- /dev/null +++ b/boards/shields/npm2100_ek/npm2100_ek.overlay @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2025 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&arduino_i2c { + npm2100_pmic: pmic@74 { + compatible = "nordic,npm2100"; + reg = <0x74>; + + npm2100_gpio: gpio-controller { + compatible = "nordic,npm2100-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + }; + + npm2100_regulators: regulators { + compatible = "nordic,npm2100-regulator"; + + /* limits are set to min/max allowed values */ + npm2100_boost: BOOST { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + npm2100_ldosw: LDOSW { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3000000>; + }; + }; + + npm2100_wdt: watchdog { + compatible = "nordic,npm2100-wdt"; + }; + + npm2100_vbat: vbat { + compatible = "nordic,npm2100-vbat"; + }; + + npm2100_buttons: buttons { + compatible = "gpio-keys"; + + pmic_button0: pmic_button_0 { + gpios = <&npm2100_gpio 0 GPIO_ACTIVE_LOW>; + label = "Pmic button switch 0"; + zephyr,code = ; + }; + + pmic_button1: pmic_button_1 { + gpios = <&npm2100_gpio 1 GPIO_ACTIVE_LOW>; + label = "Pmic button switch 1"; + zephyr,code = ; + }; + }; + }; +}; diff --git a/boards/shields/npm2100_ek/shield.yml b/boards/shields/npm2100_ek/shield.yml new file mode 100644 index 00000000000..aa40f377850 --- /dev/null +++ b/boards/shields/npm2100_ek/shield.yml @@ -0,0 +1,12 @@ +shield: + name: npm2100_ek + full_name: nPM2100 EK + vendor: nordic + supported_features: + - mfd + - input + - gpio + - led + - regulator + - sensor + - watchdog diff --git a/boards/shields/npm6001_ek/shield.yml b/boards/shields/npm6001_ek/shield.yml new file mode 100644 index 00000000000..5ddef6d5767 --- /dev/null +++ b/boards/shields/npm6001_ek/shield.yml @@ -0,0 +1,9 @@ +shield: + name: npm6001_ek + full_name: nPM6001 EK + vendor: nordic + supported_features: + - mfd + - gpio + - watchdog + - regulator diff --git a/boards/shields/nrf7002eb/doc/index.rst b/boards/shields/nrf7002eb/doc/index.rst index 06f9f4d828d..85079cdefef 100644 --- a/boards/shields/nrf7002eb/doc/index.rst +++ b/boards/shields/nrf7002eb/doc/index.rst @@ -44,7 +44,7 @@ Usage The shield can be used in any application by setting ``--shield nrf7002eb`` when invoking ``west build``. Shield Variants -############### +*************** The nRF7002 EB has a variant which includes the COEX pins. These pins are not be routed to the edge-connector on some boards, like earlier revisions of the Thingy53 than v1.0.0. @@ -53,7 +53,7 @@ edge-connector on some boards, like earlier revisions of the Thingy53 than v1.0. - ``nrf7002eb_coex``: Variant which includes the COEX pins. SR Co-existence -############### +*************** The nRF7002 EB supports SR co-existence provided the host board supports it. The SR co-existence pins are connected to the host board's GPIO pins. diff --git a/boards/shields/nrf7002eb/shield.yml b/boards/shields/nrf7002eb/shield.yml new file mode 100644 index 00000000000..43ab36ad995 --- /dev/null +++ b/boards/shields/nrf7002eb/shield.yml @@ -0,0 +1,12 @@ +shields: + - name: nrf7002eb + full_name: nRF7002 Evaluation Board Shield + vendor: nordic + supported_features: + - wifi + + - name: nrf7002eb_coex + full_name: nRF7002 Evaluation Board Shield (SR Co-Existence) + vendor: nordic + supported_features: + - wifi diff --git a/boards/shields/nrf7002ek/doc/index.rst b/boards/shields/nrf7002ek/doc/index.rst index cfe08750f57..2c55e34c1d8 100644 --- a/boards/shields/nrf7002ek/doc/index.rst +++ b/boards/shields/nrf7002ek/doc/index.rst @@ -44,7 +44,7 @@ Usage The shield can be used in any application by setting ``--shield nrf7002ek`` when invoking ``west build``. SR Co-existence -############### +*************** The nRF7002 EK supports SR co-existence provided the host board supports it. The SR co-existence pins are connected to the host board's GPIO pins. The interface is selected by setting @@ -56,7 +56,7 @@ Two Kconfig options are available to enable SR co-existence: - :kconfig:option:`CONFIG_NRF70_SR_COEX_RF_SWITCH`: Control SR side RF switch. Shield Variants -############### +*************** The nRF7002 EK is available in four variants: diff --git a/boards/shields/nrf7002ek/shield.yml b/boards/shields/nrf7002ek/shield.yml new file mode 100644 index 00000000000..f33c8c885bd --- /dev/null +++ b/boards/shields/nrf7002ek/shield.yml @@ -0,0 +1,24 @@ +shields: + - name: nrf7002ek + full_name: nRF7002 Evaluation Kit Shield + vendor: nordic + supported_features: + - wifi + + - name: nrf7002ek_nrf7000 + full_name: nRF7002 Evaluation Kit Shield (nRF7000) + vendor: nordic + supported_features: + - wifi + + - name: nrf7002ek_nrf7001 + full_name: nRF7002 Evaluation Kit Shield (nRF7001) + vendor: nordic + supported_features: + - wifi + + - name: nrf7002ek_coex + full_name: nRF7002 Evaluation Kit Shield (SR Co-Existence) + vendor: nordic + supported_features: + - wifi diff --git a/boards/shields/nxp_btb44_ov5640/shield.yml b/boards/shields/nxp_btb44_ov5640/shield.yml new file mode 100644 index 00000000000..902d26edc89 --- /dev/null +++ b/boards/shields/nxp_btb44_ov5640/shield.yml @@ -0,0 +1,6 @@ +shield: + name: nxp_btb44_ov5640 + full_name: NXP BTB44 OV5640 Camera Module + vendor: nxp + supported_features: + - video diff --git a/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig b/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig new file mode 100644 index 00000000000..79692b8f2e2 --- /dev/null +++ b/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig @@ -0,0 +1,91 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_NXP_M2_1XK_WIFI_BT + +if BT + +choice BT_NXP_MODULE + default BT_NXP_IW416 +endchoice + +endif # BT + +if WIFI + +config WIFI_NXP + default y + +choice NXP_WIFI_PART + default NXP_IW416 +endchoice + +choice NXP_IW416_MODULE + default NXP_IW416_MURATA_1XK_M2 +endchoice + +endif # WIFI + +endif # SHIELD_NXP_M2_1XK_WIFI_BT + +if SHIELD_NXP_M2_2EL_WIFI_BT + +if BT + +choice BT_NXP_MODULE + default BT_NXP_NW612 +endchoice + +endif # BT + +if WIFI + +config WIFI_NXP + default y + +choice NXP_WIFI_PART + default NXP_IW61X +endchoice + +choice NXP_IW61X_MODULE + default NXP_IW612_MURATA_2EL_M2 +endchoice + +endif # WIFI + +endif # SHIELD_NXP_M2_2EL_WIFI_BT + +if (BT_NXP_IW416) || (BT_NXP_NW612) || (NXP_IW416) || (NXP_IW61X) + +if BT + +config SYSTEM_WORKQUEUE_STACK_SIZE + default 2048 + +config BT_LONG_WQ_STACK_SIZE + default 2560 + +config MAIN_STACK_SIZE + default 2560 + +if SHELL + +config SHELL_STACK_SIZE + default 4096 + +endif # SHELL + +endif # BT + +if WIFI_NXP + +if SHELL + +config NXP_WIFI_SHELL + default y + +endif # SHELL + +endif # WIFI_NXP + +endif diff --git a/boards/shields/nxp_m2_wifi_bt/Kconfig.shield b/boards/shields/nxp_m2_wifi_bt/Kconfig.shield new file mode 100644 index 00000000000..d61c97955ef --- /dev/null +++ b/boards/shields/nxp_m2_wifi_bt/Kconfig.shield @@ -0,0 +1,8 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_NXP_M2_1XK_WIFI_BT + def_bool $(shields_list_contains,nxp_m2_1xk_wifi_bt) + +config SHIELD_NXP_M2_2EL_WIFI_BT + def_bool $(shields_list_contains,nxp_m2_2el_wifi_bt) diff --git a/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1040_evk_mimxrt1042.overlay b/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1040_evk_mimxrt1042.overlay new file mode 100644 index 00000000000..7a5a33dda76 --- /dev/null +++ b/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1040_evk_mimxrt1042.overlay @@ -0,0 +1,26 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&m2_hci_bt_uart { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-1; + /delete-property/ pinctrl-2; + /delete-property/ pinctrl-names; + pinctrl-0 = <&pinmux_lpuart3_flowcontrol>; + pinctrl-1 = <&pinmux_lpuart3_sleep>; + pinctrl-names = "default", "sleep"; + + bt_hci_uart: bt_hci_uart { + m2_bt_module: m2_bt_module { + sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&m2_wifi_sdio { + /* TODO: Unsupported; Fix pinctrl */ +}; diff --git a/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay new file mode 100644 index 00000000000..3c9276102f2 --- /dev/null +++ b/boards/shields/nxp_m2_wifi_bt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay @@ -0,0 +1,90 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,uart-pipe = &lpuart1; + }; +}; + +&m2_hci_bt_uart { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-1; + /delete-property/ pinctrl-2; + /delete-property/ pinctrl-names; + pinctrl-0 = <&pinmux_lpuart3_flow_control>; + pinctrl-1 = <&pinmux_lpuart3_sleep>; + pinctrl-names = "default", "sleep"; + + bt_hci_uart: bt_hci_uart { + m2_bt_module: m2_bt_module { + sdio-reset-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + w-disable-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&m2_wifi_sdio { + /* Use dat3 detection method */ + detect-dat3; + pinctrl-4 = <&pinmux_usdhc1_dat3_nopull>; + pinctrl-names = "default", "slow", "med", "fast", "nopull"; +}; + +&pinctrl { + /* removes pull on dat3 for card detect */ + pinmux_usdhc1_dat3_nopull: pinmux_usdhc1_dat3_nopull { + + group0 { + pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>; + bias-disable; + drive-strength = "r0"; + input-schmitt-enable; + slew-rate = "fast"; + nxp,speed = "100-mhz"; + }; + + group1 { + pinmux = <&iomuxc_gpio_b1_12_gpio2_io28>, + <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>, + <&iomuxc_gpio_sd_b0_02_usdhc1_data0>, + <&iomuxc_gpio_sd_b0_03_usdhc1_data1>, + <&iomuxc_gpio_sd_b0_04_usdhc1_data2>; + drive-strength = "r0"; + input-schmitt-enable; + bias-pull-up; + bias-pull-up-value = "47k"; + slew-rate = "fast"; + nxp,speed = "100-mhz"; + }; + + group2 { + pinmux = <&iomuxc_gpio_b1_14_usdhc1_vselect>; + drive-strength = "r0-4"; + input-schmitt-enable; + bias-pull-up; + bias-pull-up-value = "47k"; + slew-rate = "fast"; + nxp,speed = "100-mhz"; + }; + + group3 { + pinmux = <&iomuxc_gpio_ad_b0_05_gpio1_io05>; + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + + group4 { + pinmux = <&iomuxc_gpio_sd_b0_05_usdhc1_data3>; + bias-disable; + drive-strength = "r0"; + slew-rate = "fast"; + nxp,speed = "100-mhz"; + input-schmitt-enable; + }; + }; +}; diff --git a/boards/shields/nxp_m2_wifi_bt/doc/index.rst b/boards/shields/nxp_m2_wifi_bt/doc/index.rst new file mode 100644 index 00000000000..19c3355faf1 --- /dev/null +++ b/boards/shields/nxp_m2_wifi_bt/doc/index.rst @@ -0,0 +1,72 @@ +.. _nxp_m2_wifi_bt: + +NXP M.2 Wi-Fi and BT Shield +########################### + +Overview +******** + +This Zephyr shield is tested with the following M.2 modules and hardware for Wi-Fi and Bluetooth applications: + +- Embedded Artist 1XK module - uses Murata 1XK radio module with NXP IW416 chipset +- Embedded Artist 2EL module - uses Murata 2EL radio module with NXP IW612 chipset + +More information about supported chipsets, radio modules and M.2 modules can be found in below links, + +- `IW612 NXP Chipset `_ +- `IW416 NXP Chipset `_ +- `2EL Murata Radio Module `_ +- `1XK Murata Radio Module `_ +- `1XK Embedded Artist Module `_ +- `2EL Embedded Artist Module `_ + +Requirements +************ + +To use the shield, below requirements needs to be satisfied. + +- M.2 module with BT HCI UART and SDIO Interface with NXP IW416 or IW612 SoC support. +- Host platform shall have compatible M.2 interface slot. +- For Coex (Wi-Fi + BT), UART driver that supports UART RTS line control to wakeup BT CPU from sleep. +- To use default Bluetooth-Shell app it needs ~490KB flash & ~130KB RAM memory. +- To use default Wi-Fi-Shell app it needs ~1MB flash & ~1.2MB RAM memory. + +Integration Platform +******************** + +This shield works with below host platform, + +- :zephyr:board:`mimxrt1060_evk` Rev-C. + +Fetch Binary Blobs +****************** + +To support Bluetooth or Wi-Fi, nxp_m2_wifi_bt requires fetching binary blobs, +using the following command: + +.. code-block:: console + + west blobs fetch hal_nxp + +Programming +*********** + +Below are the supported shields to be used with ``--shield