Nrfx none pull in nrf54lm20dk

boards/nordic/nrf54lm20dk/Kconfig.defconfig

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+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP

boards/nordic/nrf54lm20dk/Kconfig.nrf54lm20dk

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+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NRF54LM20DK
+	select SOC_NRF54LM20A_ENGA_CPUAPP if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP
+	select SOC_NRF54LM20A_ENGA_CPUFLPR if BOARD_NRF54LM20DK_NRF54LM20A_CPUFLPR

boards/nordic/nrf54lm20dk/board.cmake

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+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP)
+  board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+elseif(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR)
+  board_runner_args(jlink "--speed=4000")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nordic/nrf54lm20dk/board.yml

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+board:
+  name: nrf54lm20dk
+  full_name: nRF54LM20 DK
+  vendor: nordic
+  socs:
+  - name: nrf54lm20a
+    variants:
+    - name: xip
+      cpucluster: cpuflpr
+runners:
+  run_once:
+    '--recover':
+    - runners:
+      - nrfjprog
+      - nrfutil
+      run: first
+      groups:
+      - boards:
+        - nrf54lm20dk/nrf54lm20a/cpuapp
+        - nrf54lm20dk/nrf54lm20a/cpuflpr
+        - nrf54lm20dk/nrf54lm20a/cpuflpr/xip
+    '--erase':
+    - runners:
+      - nrfjprog
+      - jlink
+      - nrfutil
+      run: first
+      groups:
+      - boards:
+        - nrf54lm20dk/nrf54lm20a/cpuapp
+        - nrf54lm20dk/nrf54lm20a/cpuflpr
+        - nrf54lm20dk/nrf54lm20a/cpuflpr/xip
+    '--reset':
+    - runners:
+      - nrfjprog
+      - jlink
+      - nrfutil
+      run: last
+      groups:
+      - boards:
+        - nrf54lm20dk/nrf54lm20a/cpuapp
+        - nrf54lm20dk/nrf54lm20a/cpuflpr
+        - nrf54lm20dk/nrf54lm20a/cpuflpr/xip

boards/nordic/nrf54lm20dk/doc/index.rst

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+.. zephyr:board:: nrf54lm20dk
+
+Overview
+********
+
+The nRF54LM20 Development Kit hardware provides support for the Nordic Semiconductor
+nRF54LM20A Arm Cortex-M33 CPU and the following devices:
+
+* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
+* CLOCK
+* RRAM
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
+* MEMCONF
+* :abbr:`MPU (Memory Protection Unit)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`PWM (Pulse Width Modulation)`
+* :abbr:`GRTC (Global real-time counter)`
+* Segger RTT (RTT Console)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+Hardware
+********
+
+nRF54LM20 DK has two crystal oscillators:
+
+* High-frequency 32 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+The crystal oscillators can be configured to use either
+internal or external capacitors.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``nrf54lm20dk/nrf54lm20a/cpuapp`` board target can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Applications for the ``nrf54lm20dk/nrf54lm20a/cpuflpr`` board target need
+to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+   west build -p -b nrf54lm20dk/nrf54lm20a/cpuflpr --sysbuild
+
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
+application.
+
+.. warning::
+
+   When programming the device, you might get an error similar to the following message::
+
+    ERROR: The operation attempted is unavailable due to readback protection in
+    ERROR: your device. Please use --recover to unlock the device.
+
+   This error occurs when readback protection is enabled.
+   To disable the readback protection, you must *recover* your device.
+
+   Enter the following command to recover the core::
+
+    west flash --recover
+
+   The ``--recover`` command erases the flash memory and then writes a small binary into
+   the recovered flash memory.
+   This binary prevents the readback protection from enabling itself again after a pin
+   reset or power cycle.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the nRF54LM20 DK, complete the following steps:
+
+First, connect the nRF54LM20 DK to you computer using the IMCU USB port on the DK.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nrf54lm20dk/nrf54lm20a/cpuapp
+   :goals: build flash
+
+Testing the LEDs and buttons in the nRF54LM20 DK
+************************************************
+
+Test the nRF54LM20 DK with a :zephyr:code-sample:`blinky` sample.

boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi

@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include <nordic/nrf54lm20a_enga_cpuapp.dtsi>
+#include "nrf54lm20dk_nrf54lm20a-common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,bt-mon-uart = &uart20;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,bt-hci = &bt_hci_sdc;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&hfpll {
+	clock-frequency = <DT_FREQ_M(128)>;
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <17000>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&vregmain {
+	status = "okay";
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(449)>;
+		};
+
+		slot0_ns_partition: partition@80400 {
+			label = "image-0-nonsecure";
+			reg = <0x80400 DT_SIZE_K(449)>;
+		};
+
+		slot1_partition: partition@f0800 {
+			label = "image-1";
+			reg = <0xf0800 DT_SIZE_K(449)>;
+		};
+
+		slot1_ns_partition: partition@160c00 {
+			label = "image-1-nonsecure";
+			reg = <0x160c00 DT_SIZE_K(449)>;
+		};
+
+		storage_partition: partition@1d1000 {
+			label = "storage";
+			reg = <0x1d1000 DT_SIZE_K(36)>;
+		};
+	};
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&nfct {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&bt_hci_controller {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+zephyr_udc0: &usbhs {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	mx25r64: mx25r6435f@0 {
+		compatible = "jedec,spi-nor";
+		status = "disabled";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+		jedec-id = [c2 28 17];
+		sfdp-bfp = [
+			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
+			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
+			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
+			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
+		];
+		size = <67108864>;
+		has-dpd;
+		t-enter-dpd = <10000>;
+		t-exit-dpd = <35000>;
+	};
+};