diff --git a/.clang-format b/.clang-format index 11054457bc3..e0982b801ca 100644 --- a/.clang-format +++ b/.clang-format @@ -82,6 +82,7 @@ ForEachMacros: - 'HTTP_SERVICE_FOREACH_RESOURCE' - 'I3C_BUS_FOR_EACH_I3CDEV' - 'I3C_BUS_FOR_EACH_I2CDEV' + - 'MIN_HEAP_FOREACH' IfMacros: - 'CHECKIF' # Disabled for now, see bug https://github.com/zephyrproject-rtos/zephyr/issues/48520 diff --git a/.github/ISSUE_TEMPLATE/002_enhancement.md b/.github/ISSUE_TEMPLATE/002_enhancement.md deleted file mode 100644 index 36dd018047d..00000000000 --- a/.github/ISSUE_TEMPLATE/002_enhancement.md +++ /dev/null @@ -1,28 +0,0 @@ ---- -name: Enhancement -about: Suggest enhancements to existing features -title: '' -labels: Enhancement -assignees: '' - ---- - -**Is your enhancement proposal related to a problem? Please describe.** - - -**Describe the solution you'd like** - - -**Describe alternatives you've considered** - - -**Additional context** - diff --git a/.github/ISSUE_TEMPLATE/002_enhancement.yml b/.github/ISSUE_TEMPLATE/002_enhancement.yml new file mode 100644 index 00000000000..3c2c12b8dce --- /dev/null +++ b/.github/ISSUE_TEMPLATE/002_enhancement.yml @@ -0,0 +1,42 @@ +name: Enhancement +description: Submit an Enhancement +labels: ["Enhancement"] +type: "Enhancement" +assignees: [] +body: + - type: markdown + attributes: + value: | + Thanks for taking the time to fill out this enhancement proposal. + - type: textarea + id: description + attributes: + label: Summary + description: | + Is your enhancement proposal related to a problem? Please describe. + placeholder: | + A clear and concise description of what the problem is. + validations: + required: true + - type: textarea + id: solution + attributes: + label: Describe the solution you'd like + description: | + Describe the solution you'd like + placeholder: | + A clear and concise description of what you want to happen. + validations: + required: true + - type: textarea + id: alternatives + attributes: + label: Alternatives + description: Describe alternatives you've considered + placeholder: | + A clear and concise description of any alternative solutions or features you've considered. + - type: textarea + id: context + attributes: + label: Additional Context + description: Add any other context or graphics (drag-and-drop an image) about the enhancement here. diff --git a/.github/ISSUE_TEMPLATE/003_rfc-proposal.md b/.github/ISSUE_TEMPLATE/003_rfc-proposal.md deleted file mode 100644 index 9cea2d2dac2..00000000000 --- a/.github/ISSUE_TEMPLATE/003_rfc-proposal.md +++ /dev/null @@ -1,60 +0,0 @@ ---- -name: RFC / Proposal -about: Submit an RFC / Proposal -title: '' -labels: RFC -assignees: '' - ---- - -## Introduction - - - -### Problem description - - -### Proposed change - - -## Detailed RFC - - -### Proposed change (Detailed) - - -### Dependencies - - -### Concerns and Unresolved Questions - - -## Alternatives - diff --git a/.github/ISSUE_TEMPLATE/003_rfc-proposal.yml b/.github/ISSUE_TEMPLATE/003_rfc-proposal.yml new file mode 100644 index 00000000000..7ef0ca16e14 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/003_rfc-proposal.yml @@ -0,0 +1,75 @@ +name: RFC / Proposal +description: Submit a Proposal (RFC) +labels: ["RFC"] +type: RFC +assignees: [] +body: + - type: markdown + attributes: + value: | + ## Introduction + + This section targets end users, TSC members, maintainers and anyone else + that might need a quick explanation of your proposed change. + + - type: textarea + id: problem-description + attributes: + label: Problem Description + description: Why do we want this change and what problem are we trying to address? + placeholder: Explain the problem or limitation this RFC is meant to resolve. + validations: + required: true + + - type: textarea + id: proposed-change-summary + attributes: + label: Proposed Change (Summary) + description: A high-level summary of the proposed change. + placeholder: Brief summary of what will change if this RFC is implemented. + validations: + required: true + + - type: markdown + attributes: + value: | + ## Detailed RFC + + This section targets the development team. Upon reading it, each engineer + should understand what must be done to implement the proposed feature. + + - type: textarea + id: detailed-change + attributes: + label: Proposed Change (Detailed) + description: Describe the change in as much detail as possible. Include context or background info, and reuse of existing components if applicable. + placeholder: Explain exactly what you’re planning to change and how. + validations: + required: true + + - type: textarea + id: dependencies + attributes: + label: Dependencies + description: Highlight how this change may affect the rest of the project or other teams/components. + placeholder: List components, modules, or teams affected. + validations: + required: false + + - type: textarea + id: concerns + attributes: + label: Concerns and Unresolved Questions + description: List any concerns, unknowns, or unresolved questions related to this proposal. + placeholder: Any areas of uncertainty? + validations: + required: false + + - type: textarea + id: alternatives + attributes: + label: Alternatives Considered + description: What alternative solutions were considered? Why was this proposal chosen? + placeholder: List alternatives and explain the rationale behind your choice. + validations: + required: false diff --git a/.github/ISSUE_TEMPLATE/004_feature_request.md b/.github/ISSUE_TEMPLATE/004_feature_request.md deleted file mode 100644 index 63aa536c8f5..00000000000 --- a/.github/ISSUE_TEMPLATE/004_feature_request.md +++ /dev/null @@ -1,28 +0,0 @@ ---- -name: Feature request -about: Suggest an idea for this project -title: '' -labels: Feature Request -assignees: '' - ---- - -**Is your feature request related to a problem? Please describe.** - - -**Describe the solution you'd like** - - -**Describe alternatives you've considered** - - -**Additional context** - diff --git a/.github/ISSUE_TEMPLATE/004_feature_request.yml b/.github/ISSUE_TEMPLATE/004_feature_request.yml new file mode 100644 index 00000000000..e085f08ed77 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/004_feature_request.yml @@ -0,0 +1,29 @@ +name: Feature Request +description: Suggest a new feature or enhancement +labels: ["Feature Request"] +type: Feature +assignees: [] +body: + - type: textarea + id: problem + attributes: + label: Is your feature request related to a problem? Please describe. + description: A clear and concise description of what the problem is. + placeholder: e.g., I'm frustrated when I need to do X manually because Y is missing. + validations: + required: true + + - type: textarea + id: solution + attributes: + label: Describe the solution you'd like + description: A clear and concise description of what you want to happen. + placeholder: e.g., It would be great if the system could automatically handle X by doing Y. + validations: + required: true + + - type: textarea + id: alternatives + attributes: + label: Describe alternatives you've considered + description: Include any alternative solutions or features diff --git a/.github/ISSUE_TEMPLATE/006_nomination.md b/.github/ISSUE_TEMPLATE/006_nomination.md deleted file mode 100644 index 832fb7b8296..00000000000 --- a/.github/ISSUE_TEMPLATE/006_nomination.md +++ /dev/null @@ -1,42 +0,0 @@ ---- -name: Contributor Nomination -about: Nominate a GitHub user for additional rights on the Zephyr Project -title: '' -labels: Role Nomination -assignees: '' - ---- - -# Background - -The [TSC Project Roles] defines the main roles for the Zephyr Project, including -Maintainer, Collaborator, and Contributor. - -By default anyone that contributes code or documentation is a Contributor, but -with the lowest [GitHub Permission Level] of Read. For example, Contributors -with Read permission do not have the permission to add reviewers to a pull -request. - -Use this template to nominate a GitHub user for the Contributor role with -Triage permission level, which allows the user to add reviewers to a pull -request and be added as a reviewer by other users. - -# Nomination - -## GitHub User - -Provide the following information about the GitHub user: - -1. Full Name -1. GitHub username -1. Organization (optional) - -## Supporting Documents - -Add links to 3-5 GitHub pull requests, in the Zephyr project, authored or -reviewed by the GitHub user that demonstrate the user's dedication to the -Zephyr project. - - -[TSC Project Roles]: -[GitHub Permission Level]: diff --git a/.github/ISSUE_TEMPLATE/006_nomination.yml b/.github/ISSUE_TEMPLATE/006_nomination.yml new file mode 100644 index 00000000000..fd2914cf2f4 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/006_nomination.yml @@ -0,0 +1,57 @@ +name: Contributor Nomination +description: Nominate a GitHub user for the Contributor role with triage permissions +labels: [Role Nomination] +assignees: ['nashif'] +body: + - type: markdown + attributes: + value: | + ## Background + + The [TSC Project Roles](https://docs.zephyrproject.org/latest/project/project_roles.html) defines the main roles for the Zephyr Project, including Maintainer, Collaborator, and Contributor. + + By default, anyone who contributes code or documentation is a Contributor, but with the lowest [GitHub Permission Level](https://docs.github.com/en/organizations/managing-access-to-your-organizations-repositories/repository-roles-for-an-organization) of **Read**. + + Use this form to nominate a user for the **Contributor** role with **Triage** permission, which allows the user to: + - Add reviewers to pull requests + - Be added as a reviewer by others + + - type: input + id: full-name + attributes: + label: Full Name + description: Full name of the nominated contributor. + placeholder: e.g., Jane Doe + validations: + required: true + + - type: input + id: github-username + attributes: + label: GitHub Username + description: GitHub handle of the nominated contributor. + placeholder: e.g., @janedoe + validations: + required: true + + - type: input + id: organization + attributes: + label: Organization + description: Organization the nominee is affiliated with (optional). + placeholder: e.g., Acme Corp + validations: + required: false + + - type: textarea + id: supporting-documents + attributes: + label: Supporting Documents + description: Provide links to 3–5 pull requests authored or reviewed by the nominee that demonstrate their dedication to the Zephyr project. + placeholder: | + e.g., + - https://github.com/zephyrproject-rtos/zephyr/pull/12345 + - https://github.com/zephyrproject-rtos/zephyr/pull/23456 + - https://github.com/zephyrproject-rtos/zephyr/pull/34567 + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/007_ext-source.md b/.github/ISSUE_TEMPLATE/007_ext-source.md deleted file mode 100644 index 2b6eb4cebb9..00000000000 --- a/.github/ISSUE_TEMPLATE/007_ext-source.md +++ /dev/null @@ -1,77 +0,0 @@ ---- -name: External Source Code -about: Submit a proposal to integrate external source code -title: '' -labels: TSC -assignees: '' - ---- - -## Origin - -Name of project hosting the original open source code -Provide a link to the source - -## Purpose - -Brief description of what this software does - -## Mode of integration - -Describe whether you'd like to integrate this external component in the main tree -or as a module, and why. If the mode of integration is a module, suggest a -repository name for the module - -## Maintainership - -List the person(s) that will be maintaining the integration of this external code -for the foreseeable future. Please use GitHub IDs to identify them. You can -choose to identify a single maintainer only or add collaborators as well - -## Pull Request - -Pull request (if any) with the actual implementation of the integration, be it -in the main tree or as a module (pointing to your own fork for now). Make sure -the PR is correctly labeled as "DNM" - -## Description - -Long description that will help reviewers discuss suitability of the -component to solve the problem at hand (there may be a better options -available.) - -What is its primary functionality (e.g., SQLLite is a lightweight -database)? - -What problem are you trying to solve? (e.g., a state store is -required to maintain ...) - -Why is this the right component to solve it (e.g., SQLite is small, -easy to use, and has a very liberal license.) - -## Security - -Does this component include any cryptographic functionality? -If so, please describe the cryptographic algorithms and protocols used. - -How does this component handle security vulnerabilities and updates? -Are there any known vulnerabilities in this component? If so, please -provide details and references to any CVEs or security advisories. - -## Dependencies - -What other components does this package depend on? - -Will the Zephyr project have a direct dependency on the component, or -will it be included via an abstraction layer with this component as a -replaceable implementation? - -## Revision - -Version or SHA you would like to integrate initially - -## License - -Please use an SPDX identifier (https://spdx.org/licenses/), such as -``BSD-3-Clause`` - diff --git a/.github/ISSUE_TEMPLATE/007_ext-source.yml b/.github/ISSUE_TEMPLATE/007_ext-source.yml new file mode 100644 index 00000000000..741be93e184 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/007_ext-source.yml @@ -0,0 +1,106 @@ +name: External Component Integration +description: Propose integration of an external open source component +labels: ["TSC"] +assignees: [] +body: + - type: textarea + id: origin + attributes: + label: Origin + description: Name of project hosting the original open source code. Provide a link to the source. + placeholder: e.g., SQLite - https://sqlite.org + validations: + required: true + + - type: textarea + id: purpose + attributes: + label: Purpose + description: Brief description of what this software does. + placeholder: | + e.g., A small, fast, self-contained SQL database engine. + validations: + required: true + + - type: textarea + id: integration-mode + attributes: + label: Mode of Integration + description: Should this be integrated in the main tree or as a module? Explain your choice and suggest a module repo name if applicable. + placeholder: | + e.g., As a module - proposed repo name: zephyr-sqlite + validations: + required: true + + - type: textarea + id: maintainership + attributes: + label: Maintainership + description: List maintainers (GitHub IDs) for this integration. Include at least one primary maintainer. + placeholder: | + e.g., @username1 (primary), @username2 (collaborator) + validations: + required: true + + - type: input + id: pull-request + attributes: + label: Pull Request + description: Link to the pull request (if any) for this integration. Must be labeled "DNM" (Do Not Merge). + placeholder: | + e.g., https://github.com/zephyrproject-rtos/zephyr/pull/12345 + validations: + required: false + + - type: textarea + id: description + attributes: + label: Description + description: Long-form description to justify suitability of this component. + placeholder: | + - What is its primary functionality? + - What problem does it solve? + - Why is this the right component? + validations: + required: true + + - type: textarea + id: security + attributes: + label: Security + description: Security-related aspects of this component, including cryptographic functions and known vulnerabilities. + placeholder: | + - Does it use cryptography? + - How are vulnerabilities handled? + - Any known CVEs? + validations: + required: false + + - type: textarea + id: dependencies + attributes: + label: Dependencies + description: What does this component depend on, and how will it be integrated (directly or via abstraction)? + placeholder: | + - Other external packages? + - Direct or abstracted use in Zephyr? + validations: + required: false + + - type: input + id: revision + attributes: + label: Version or SHA + description: Which version or specific commit should be initially integrated? + placeholder: e.g., v3.45.0 or 79cc94d + validations: + required: true + + - type: input + id: license + attributes: + label: License (SPDX) + description: Provide the license using a valid SPDX identifier (e.g., BSD-3-Clause). + placeholder: e.g., MIT or BSD-3-Clause + validations: + required: true diff --git a/.github/SECURITY.md b/.github/SECURITY.md index ffbaf1a6b62..cd4e9d62f95 100644 --- a/.github/SECURITY.md +++ b/.github/SECURITY.md @@ -8,11 +8,11 @@ updates: - The most recent release, and the release prior to that. - Active LTS releases. -At this time, with the latest release of v4.0, the supported +At this time, with the latest release of v4.2, the supported versions are: - - v4.1: Current release - - v4.0: Prior release + - v4.2: Current release + - v4.1: Prior release - v3.7: Current LTS ## Reporting process diff --git a/.github/workflows/assigner.yml b/.github/workflows/assigner.yml index b4edf9c02a6..a986067d5f8 100644 --- a/.github/workflows/assigner.yml +++ b/.github/workflows/assigner.yml @@ -44,7 +44,7 @@ jobs: - name: Run assignment script env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + GITHUB_TOKEN: ${{ secrets.ZB_PR_ASSIGNER_GITHUB_TOKEN }} run: | FLAGS="-v" FLAGS+=" -o ${{ github.event.repository.owner.login }}" diff --git a/.github/workflows/bsim-tests-publish.yaml b/.github/workflows/bsim-tests-publish.yaml index 4e9ed86b082..83aa87dcbbf 100644 --- a/.github/workflows/bsim-tests-publish.yaml +++ b/.github/workflows/bsim-tests-publish.yaml @@ -19,12 +19,12 @@ jobs: steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9 + uses: dawidd6/action-download-artifact@ac66b43f0e6a346234dd65d4d0c8fbb31cb316e5 # v11 with: run_id: ${{ github.event.workflow_run.id }} - name: Publish BabbleSim Test Results - uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0 with: check_name: BabbleSim Test Results comment_mode: off diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 81473f734e7..9bfb923e397 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -10,7 +10,7 @@ on: - "tests/bsim/**" - "boards/nordic/nrf5*/*dt*" - "dts/*/nordic/**" - - "tests/bluetooth/common/testlib/**" + - "tests/bluetooth/**" - "samples/bluetooth/**" - "boards/native/**" - "soc/native/**" @@ -42,7 +42,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 options: '--entrypoint /bin/bash' env: ZEPHYR_TOOLCHAIN_VARIANT: zephyr @@ -123,7 +123,7 @@ jobs: files: | samples/bluetooth/ subsys/bluetooth/ - tests/bluetooth/common/testlib/ + tests/bluetooth/ tests/bsim/bluetooth/ - name: Check if Networking files changed @@ -193,7 +193,7 @@ jobs: junit.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0 with: check_name: Bsim Test Results files: "junit.xml" diff --git a/.github/workflows/bug_snapshot.yaml b/.github/workflows/bug_snapshot.yaml index befa8cdb8bf..3959b5fccc8 100644 --- a/.github/workflows/bug_snapshot.yaml +++ b/.github/workflows/bug_snapshot.yaml @@ -10,8 +10,8 @@ on: workflow_dispatch: branches: [main] schedule: - # Run daily at 14:05 - - cron: '5 14 * * *' + # Run daily at 00:05 + - cron: '5 00 * * *' permissions: contents: read @@ -52,7 +52,7 @@ jobs: echo "BUGS_PICKLE_PATH=${BUGS_PICKLE_PATH}" >> ${GITHUB_ENV} - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 + uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index 04bc190fd13..d61f52bbce4 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -18,7 +18,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -109,7 +109,7 @@ jobs: export ZEPHYR_BASE=${PWD} export ZEPHYR_TOOLCHAIN_VARIANT=llvm - ./scripts/twister -p native_sim --no-detailed-test-id --force-color --inline-logs -M -N -v --retry-failed 2 \ + ./scripts/twister -p native_sim --force-color --inline-logs -M -N -v --retry-failed 2 \ -T tests --subset ${{matrix.subset}}/2 -j 16 - name: Print ccache stats @@ -172,7 +172,7 @@ jobs: junit-clang.html - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0 if: always() with: check_name: Unit Test Results diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 0a048b95f28..bc5dd7e758d 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -17,7 +17,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -232,7 +232,7 @@ jobs: - name: Upload coverage to Codecov if: always() - uses: codecov/codecov-action@ad3126e916f78f00edff4ed0317cf185271ccc2d # v5.4.2 + uses: codecov/codecov-action@18283e04ce6e62d37312384ff67231eb8fd56d24 # v5.4.3 with: env_vars: OS,PYTHON fail_ci_if_error: false diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index 869467e030a..ac0d73c8d60 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -7,7 +7,7 @@ on: - v*-branch - collab-* schedule: - - cron: '34 16 * * 3' + - cron: '34 16 * * 6' pull_request: branches: - main @@ -39,7 +39,7 @@ jobs: uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Initialize CodeQL - uses: github/codeql-action/init@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 + uses: github/codeql-action/init@181d5eefc20863364f96762470ba6f862bdef56b # v3.29.2 with: languages: ${{ matrix.language }} build-mode: ${{ matrix.build-mode }} @@ -53,6 +53,6 @@ jobs: exit 0 - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 + uses: github/codeql-action/analyze@181d5eefc20863364f96762470ba6f862bdef56b # v3.29.2 with: category: "/language:${{matrix.language}}" diff --git a/.github/workflows/daily_test_version.yml b/.github/workflows/daily_test_version.yml index 4b89661a8af..2b601869964 100644 --- a/.github/workflows/daily_test_version.yml +++ b/.github/workflows/daily_test_version.yml @@ -20,7 +20,7 @@ jobs: steps: - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 + uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index bc147ee3817..29dc9913d9a 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -15,8 +15,8 @@ permissions: contents: read env: - DOXYGEN_VERSION: 1.12.0 - DOXYGEN_MD5SUM: fd96a5defa535dfe2e987b46540844a4 + DOXYGEN_VERSION: 1.14.0 + DOXYGEN_MD5SUM: e761a5097ae20ecccfd02041925f102a JOB_COUNT: 4 jobs: @@ -108,7 +108,7 @@ jobs: cache-dependency-path: doc/requirements.txt - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + uses: zephyrproject-rtos/action-zephyr-setup@b2453c72966ee67b1433be22b250348d48283286 # v1.0.7 with: app-path: zephyr toolchains: 'all' @@ -226,7 +226,7 @@ jobs: echo "/opt/doxygen-${DOXYGEN_VERSION}/bin" >> $GITHUB_PATH - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + uses: zephyrproject-rtos/action-zephyr-setup@b2453c72966ee67b1433be22b250348d48283286 # v1.0.7 with: app-path: zephyr toolchains: 'arm-zephyr-eabi' diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index 9552d72b3d9..710d9ec1ceb 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -25,7 +25,7 @@ jobs: steps: - name: Download artifacts id: download-artifacts - uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9 + uses: dawidd6/action-download-artifact@ac66b43f0e6a346234dd65d4d0c8fbb31cb316e5 # v11 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} @@ -66,7 +66,7 @@ jobs: - name: Configure AWS Credentials if: steps.download-artifacts.outputs.found_artifact == 'true' - uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 + uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_PR_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/doc-publish.yml b/.github/workflows/doc-publish.yml index 89afeb4ed1b..a435f7ef5d0 100644 --- a/.github/workflows/doc-publish.yml +++ b/.github/workflows/doc-publish.yml @@ -27,7 +27,7 @@ jobs: steps: - name: Download artifacts - uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9 + uses: dawidd6/action-download-artifact@ac66b43f0e6a346234dd65d4d0c8fbb31cb316e5 # v11 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} @@ -40,7 +40,7 @@ jobs: fi - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 + uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 with: aws-access-key-id: ${{ vars.AWS_DOCS_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_DOCS_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index 1e4eeaa76b4..c10dea7101f 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -1,9 +1,8 @@ name: Footprint Tracking -# Run every 12 hours and on tags on: schedule: - - cron: '50 1/12 * * *' + - cron: '50 00 * * *' push: paths: - 'VERSION' @@ -29,7 +28,7 @@ jobs: group: zephyr-runner-v2-linux-x64-4xlarge if: github.repository_owner == 'zephyrproject-rtos' container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 options: '--entrypoint /bin/bash' defaults: run: @@ -90,7 +89,7 @@ jobs: west update 2>&1 1> west.update.log || west update 2>&1 1> west.update2.log - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 + uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index 27166aa993a..77612ecd7ad 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -56,13 +56,13 @@ jobs: - name: Set up Python uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 with: - python-version: 3.11 + python-version: 3.12 - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + uses: zephyrproject-rtos/action-zephyr-setup@b2453c72966ee67b1433be22b250348d48283286 # v1.0.7 with: app-path: zephyr - toolchains: aarch64-zephyr-elf:arc-zephyr-elf:arc64-zephyr-elf:arm-zephyr-eabi:mips-zephyr-elf:riscv64-zephyr-elf:sparc-zephyr-elf:x86_64-zephyr-elf:xtensa-dc233c_zephyr-elf:xtensa-sample_controller32_zephyr-elf + toolchains: aarch64-zephyr-elf:arc-zephyr-elf:arc64-zephyr-elf:arm-zephyr-eabi:mips-zephyr-elf:riscv64-zephyr-elf:sparc-zephyr-elf:x86_64-zephyr-elf:xtensa-dc233c_zephyr-elf:xtensa-sample_controller32_zephyr-elf:rx-zephyr-elf - name: Build firmware working-directory: zephyr diff --git a/.github/workflows/issue_count.yml b/.github/workflows/issue_count.yml index 0ab24ef5f64..2e5b11f11e9 100644 --- a/.github/workflows/issue_count.yml +++ b/.github/workflows/issue_count.yml @@ -2,7 +2,7 @@ name: Issue Tracker on: schedule: - - cron: '*/10 * * * *' + - cron: '10 1/4 * * *' permissions: contents: read @@ -45,7 +45,7 @@ jobs: path: ${{ env.OUTPUT_FILE_NAME }} - name: Configure AWS Credentials - uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0 + uses: aws-actions/configure-aws-credentials@b47578312673ae6fa5b5096b330d9fbac3d116df # v4.2.1 with: aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }} aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }} diff --git a/.github/workflows/maintainer_check.yml b/.github/workflows/maintainer_check.yml new file mode 100644 index 00000000000..dee115e8ced --- /dev/null +++ b/.github/workflows/maintainer_check.yml @@ -0,0 +1,43 @@ +name: Maintainer file check + +on: + pull_request_target: + branches: + - main + paths: + - MAINTAINERS.yml + +permissions: + contents: read + +jobs: + assignment: + name: Check MAINTAINERS.yml changes + runs-on: ubuntu-24.04 + + steps: + - name: Check out source code + uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 + + - name: Set up Python + uses: actions/setup-python@a26af69be951a213d495a4c3e4e4022e16d87065 # v5.6.0 + with: + python-version: 3.12 + cache: pip + cache-dependency-path: scripts/requirements-actions.txt + + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + + - name: Fetch MAINTAINERS.yml from mainline + run: | + git fetch origin main + git show origin/main:MAINTAINERS.yml > mainline_MAINTAINERS.yml + + - name: Check maintainer file changes + env: + GITHUB_TOKEN: ${{ secrets.ZB_PR_ASSIGNER_GITHUB_TOKEN }} + run: | + python ./scripts/ci/check_maintainer_changes.py \ + --repo zephyrproject-rtos/zephyr mainline_MAINTAINERS.yml MAINTAINERS.yml diff --git a/.github/workflows/pinned-gh-actions.yml b/.github/workflows/pinned-gh-actions.yml index c89eb7464f7..e7f51a3316e 100644 --- a/.github/workflows/pinned-gh-actions.yml +++ b/.github/workflows/pinned-gh-actions.yml @@ -16,4 +16,4 @@ jobs: - name: Checkout code uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2 - name: Ensure SHA pinned actions - uses: zgosalvez/github-actions-ensure-sha-pinned-actions@2d6823da4039243036c86d76f503c84e2ded2517 # v3.0.24 + uses: zgosalvez/github-actions-ensure-sha-pinned-actions@fc87bb5b5a97953d987372e74478de634726b3e5 # v3.0.25 diff --git a/.github/workflows/pr_metadata_check.yml b/.github/workflows/pr_metadata_check.yml index 91c997279df..3e862321e96 100644 --- a/.github/workflows/pr_metadata_check.yml +++ b/.github/workflows/pr_metadata_check.yml @@ -33,15 +33,7 @@ jobs: pip install -r scripts/requirements-actions.txt --require-hashes - name: Run the check script + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | - ./scripts/ci/do_not_merge.py -p "${{ github.event.pull_request.number }}" - - empty_pr_description: - if: ${{ github.event.pull_request.body == '' }} - name: PR Description - runs-on: ubuntu-24.04 - steps: - - name: Check for PR description - run: | - echo "Pull request description cannot be empty." - exit 1 + python -u scripts/ci/do_not_merge.py -p "${{ github.event.pull_request.number }}" diff --git a/.github/workflows/scorecards.yml b/.github/workflows/scorecards.yml index 3d4471e70a5..b7527d0b50c 100644 --- a/.github/workflows/scorecards.yml +++ b/.github/workflows/scorecards.yml @@ -34,7 +34,7 @@ jobs: persist-credentials: false - name: "Run analysis" - uses: ossf/scorecard-action@f49aabe0b5af0936a0987cfb85d86b75731b0186 # v2.4.1 + uses: ossf/scorecard-action@05b42c624433fc40578a4040d5cf5e36ddca8cde # v2.4.2 with: results_file: results.sarif results_format: sarif @@ -56,6 +56,6 @@ jobs: # Upload the results to GitHub's code scanning dashboard (optional). # Commenting out will disable upload of results to your repo's Code Scanning dashboard - name: "Upload to code-scanning" - uses: github/codeql-action/upload-sarif@60168efe1c415ce0f5521ea06d5c2062adbeed1b # v3.28.17 + uses: github/codeql-action/upload-sarif@181d5eefc20863364f96762470ba6f862bdef56b # v3.29.2 with: sarif_file: results.sarif diff --git a/.github/workflows/twister-publish.yaml b/.github/workflows/twister-publish.yaml index 8c700a81f38..d080409645b 100644 --- a/.github/workflows/twister-publish.yaml +++ b/.github/workflows/twister-publish.yaml @@ -39,7 +39,7 @@ jobs: - name: Download Artifacts id: download-artifacts - uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9 + uses: dawidd6/action-download-artifact@ac66b43f0e6a346234dd65d4d0c8fbb31cb316e5 # v11 with: path: artifacts workflow: twister.yml diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index b8ddd8e82ca..d5f214be9fb 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -65,7 +65,7 @@ jobs: - name: Setup Zephyr project if: github.event_name == 'pull_request' - uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + uses: zephyrproject-rtos/action-zephyr-setup@b2453c72966ee67b1433be22b250348d48283286 # v1.0.7 with: app-path: zephyr toolchains: all @@ -89,7 +89,7 @@ jobs: run: | export ZEPHYR_BASE=${PWD} export ZEPHYR_TOOLCHAIN_VARIANT=zephyr - python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --no-detailed-test-id --pull-request -t $TESTS_PER_BUILDER + python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request -t $TESTS_PER_BUILDER if [ -s .testplan ]; then cat .testplan >> $GITHUB_ENV else @@ -127,7 +127,7 @@ jobs: needs: twister-build-prep if: needs.twister-build-prep.outputs.size != 0 container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.0.20250523 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.1.20250624 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -142,7 +142,7 @@ jobs: CCACHE_IGNOREOPTIONS: '-specs=* --specs=*' BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components - TWISTER_COMMON: ' --test-config tests/test_config_ci.yaml --no-detailed-test-id --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 ' + TWISTER_COMMON: ' --test-config tests/test_config_ci.yaml --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 ' WEEKLY_OPTIONS: ' -M --build-only --all --show-footprint --report-filtered -j 32' PR_OPTIONS: ' --clobber-output --integration -j 16' PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered -j 16' @@ -210,6 +210,11 @@ jobs: echo "github.base_ref: ${{ github.base_ref }}" echo "github.ref_name: ${{ github.ref_name }}" + - name: Install Python packages + run: | + pip install -r scripts/requirements-actions.txt --require-hashes + west packages pip --install + - name: Set up ccache run: | mkdir -p ${CCACHE_DIR} @@ -248,7 +253,7 @@ jobs: rm -f testplan.json export ZEPHYR_BASE=${PWD} export ZEPHYR_TOOLCHAIN_VARIANT=zephyr - python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request --no-detailed-test-id + python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request ./scripts/twister --subset ${{matrix.subset}}/${{ strategy.job-total }} --load-tests testplan.json ${TWISTER_COMMON} ${PR_OPTIONS} if [ "${{matrix.subset}}" = "1" -a ${{needs.twister-build-prep.outputs.fullrun}} = 'True' ]; then ./scripts/zephyr_module.py --twister-out module_tests.args @@ -356,7 +361,7 @@ jobs: junit.xml - name: Publish Unit Test Results - uses: EnricoMi/publish-unit-test-result-action@afb2984f4d89672b2f9d9c13ae23d53779671984 # v2.19.0 + uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0 with: check_name: Unit Test Results files: "**/twister.xml" diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index 6cc922adb61..5590016e922 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -45,7 +45,7 @@ jobs: cache-dependency-path: scripts/requirements-actions.txt - name: Setup Zephyr project - uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6 + uses: zephyrproject-rtos/action-zephyr-setup@b2453c72966ee67b1433be22b250348d48283286 # v1.0.7 with: app-path: zephyr toolchains: all @@ -134,7 +134,7 @@ jobs: EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" fi BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --create-rom-ram-report --footprint-report ROM --enable-size-report --footprint-from-buildlog $BASIC_FLAGS + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --create-rom-ram-report --footprint-report ROM --enable-size-report --footprint-from-buildlog $BASIC_FLAGS --detailed-test-id - name: Build firmware No. 7 - list tags working-directory: zephyr @@ -146,7 +146,7 @@ jobs: EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" fi BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --list-tags $BASIC_FLAGS + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --list-tags $BASIC_FLAGS --detailed-test-id - name: Build firmware No. 8 - list tests working-directory: zephyr @@ -170,7 +170,7 @@ jobs: EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" fi BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --report-dir . --report-name test_name --report-suffix suffix --report-summary 0 --report-all-options --report-filtered $BASIC_FLAGS + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --report-dir . --report-name test_name --report-suffix suffix --report-summary 0 --report-all-options --report-filtered $BASIC_FLAGS --detailed-test-id - name: Build firmware No. 10 - force platform and toolchain, log level, timestamps, logfile working-directory: zephyr @@ -182,5 +182,5 @@ jobs: EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out" fi BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS" - ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --force-platform --platform qemu_x86 --force-toolchain --log-level WARNING --log-file log.file $BASIC_FLAGS + ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --force-platform --platform qemu_x86 --force-toolchain --log-level WARNING --log-file log.file $BASIC_FLAGS --detailed-test-id rm log.file diff --git a/.gitignore b/.gitignore index aab3981f52f..b57bdc85372 100644 --- a/.gitignore +++ b/.gitignore @@ -102,6 +102,7 @@ MaintainersFormat.txt ModulesMaintainers.txt Nits.txt Pylint.txt +PythonCompat.txt Ruff.txt SphinxLint.txt SysbuildKconfig.txt @@ -109,3 +110,4 @@ SysbuildKconfigBasic.txt SysbuildKconfigBasicNoModules.txt TextEncoding.txt YAMLLint.txt +ZephyrModuleFile.txt diff --git a/.gitlint b/.gitlint index 16e9bdca9aa..f837a21c57a 100644 --- a/.gitlint +++ b/.gitlint @@ -1,6 +1,7 @@ # All these sections are optional, edit this file as you like. # Zephyr-specific defaults are located in scripts/gitlint/zephyr_commit_rules.py [general] +regex-style-search=true ignore=title-trailing-punctuation, T3, title-max-length, T1, body-hard-tab, B3, B1 # verbosity should be a value between 1 and 3, the commandline -v flags take precedence over this verbosity = 3 diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml index e7d51e2294f..2af90ce1fdd 100644 --- a/.ruff-excludes.toml +++ b/.ruff-excludes.toml @@ -568,64 +568,6 @@ "UP036", # https://docs.astral.sh/ruff/rules/outdated-version-block "UP038", # https://docs.astral.sh/ruff/rules/non-pep604-isinstance ] -"./scripts/list_boards.py" = [ - "E731", # https://docs.astral.sh/ruff/rules/lambda-assignment - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if - "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation-union - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes - "UP032", # https://docs.astral.sh/ruff/rules/f-string - "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import -] -"./scripts/list_hardware.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes - "UP032", # https://docs.astral.sh/ruff/rules/f-string - "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import -] -"./scripts/logging/dictionary/database_gen.py" = [ - "E713", # https://docs.astral.sh/ruff/rules/not-in-test - "E741", # https://docs.astral.sh/ruff/rules/ambiguous-variable-name - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if - "SIM103", # https://docs.astral.sh/ruff/rules/needless-bool - "SIM113", # https://docs.astral.sh/ruff/rules/enumerate-for-loop - "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler -] -"./scripts/logging/dictionary/dictionary_parser/data_types.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses -] -"./scripts/logging/dictionary/dictionary_parser/log_database.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "SIM103", # https://docs.astral.sh/ruff/rules/needless-bool - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes - "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses -] -"./scripts/logging/dictionary/dictionary_parser/log_parser.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] -"./scripts/logging/dictionary/dictionary_parser/log_parser_v1.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports - "UP030", # https://docs.astral.sh/ruff/rules/format-literals - "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting - "UP032", # https://docs.astral.sh/ruff/rules/f-string -] -"./scripts/logging/dictionary/dictionary_parser/log_parser_v3.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] -"./scripts/logging/dictionary/dictionary_parser/mipi_syst.py" = [ - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] -"./scripts/logging/dictionary/dictionary_parser/utils.py" = [ - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] -"./scripts/logging/dictionary/log_parser.py" = [ - "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler - "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes -] "./scripts/make_bugs_pickle.py" = [ "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import @@ -1117,10 +1059,6 @@ "UP008", # https://docs.astral.sh/ruff/rules/super-call-with-parameters "UP032", # https://docs.astral.sh/ruff/rules/f-string ] -"./scripts/west_commands/spdx.py" = [ - "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders - "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports -] "./scripts/west_commands/tests/conftest.py" = [ "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports ] diff --git a/CMakeLists.txt b/CMakeLists.txt index 3157813d65c..f7383e0bd58 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -214,24 +214,53 @@ endif() # 1) Using EXTRA_CFLAGS which is applied regardless of kconfig choice, or # 2) Rely on override support being implemented by your toolchain_cc_optimize_*() # -get_property(OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG TARGET compiler PROPERTY no_optimization) -get_property(OPTIMIZE_FOR_DEBUG_FLAG TARGET compiler PROPERTY optimization_debug) -get_property(OPTIMIZE_FOR_SPEED_FLAG TARGET compiler PROPERTY optimization_speed) -get_property(OPTIMIZE_FOR_SIZE_FLAG TARGET compiler PROPERTY optimization_size) -get_property(OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG TARGET compiler PROPERTY optimization_size_aggressive) +get_property(COMPILER_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG TARGET compiler PROPERTY no_optimization) +get_property(COMPILER_OPTIMIZE_FOR_DEBUG_FLAG TARGET compiler PROPERTY optimization_debug) +get_property(COMPILER_OPTIMIZE_FOR_SPEED_FLAG TARGET compiler PROPERTY optimization_speed) +get_property(COMPILER_OPTIMIZE_FOR_SIZE_FLAG TARGET compiler PROPERTY optimization_size) +get_property(COMPILER_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG TARGET compiler PROPERTY optimization_size_aggressive) + +get_property(ASM_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG TARGET asm PROPERTY no_optimization) +get_property(ASM_OPTIMIZE_FOR_DEBUG_FLAG TARGET asm PROPERTY optimization_debug) +get_property(ASM_OPTIMIZE_FOR_SPEED_FLAG TARGET asm PROPERTY optimization_speed) +get_property(ASM_OPTIMIZE_FOR_SIZE_FLAG TARGET asm PROPERTY optimization_size) +get_property(ASM_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG TARGET asm PROPERTY optimization_size_aggressive) + +# Let the assembler inherit the optimization flags of the compiler if it is +# not set explicitly. +if(NOT ASM_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG) + set(ASM_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG ${COMPILER_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG}) +endif() +if(NOT ASM_OPTIMIZE_FOR_DEBUG_FLAG) + set(ASM_OPTIMIZE_FOR_DEBUG_FLAG ${COMPILER_OPTIMIZE_FOR_DEBUG_FLAG}) +endif() +if(NOT ASM_OPTIMIZE_FOR_SPEED_FLAG) + set(ASM_OPTIMIZE_FOR_SPEED_FLAG ${COMPILER_OPTIMIZE_FOR_SPEED_FLAG}) +endif() +if(NOT ASM_OPTIMIZE_FOR_SIZE_FLAG) + set(ASM_OPTIMIZE_FOR_SIZE_FLAG ${COMPILER_OPTIMIZE_FOR_SIZE_FLAG}) +endif() +if(NOT ASM_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG) + set(ASM_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG ${COMPILER_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG}) +endif() # From kconfig choice, pick the actual OPTIMIZATION_FLAG to use. # Kconfig choice ensures only one of these CONFIG_*_OPTIMIZATIONS is set. if(CONFIG_NO_OPTIMIZATIONS) - set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG}) + set(COMPILER_OPTIMIZATION_FLAG ${COMPILER_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG}) + set(ASM_OPTIMIZATION_FLAG ${ASM_OPTIMIZE_FOR_NO_OPTIMIZATIONS_FLAG}) elseif(CONFIG_DEBUG_OPTIMIZATIONS) - set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_DEBUG_FLAG}) + set(COMPILER_OPTIMIZATION_FLAG ${COMPILER_OPTIMIZE_FOR_DEBUG_FLAG}) + set(ASM_OPTIMIZATION_FLAG ${ASM_OPTIMIZE_FOR_DEBUG_FLAG}) elseif(CONFIG_SPEED_OPTIMIZATIONS) - set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_SPEED_FLAG}) + set(COMPILER_OPTIMIZATION_FLAG ${COMPILER_OPTIMIZE_FOR_SPEED_FLAG}) + set(ASM_OPTIMIZATION_FLAG ${ASM_OPTIMIZE_FOR_SPEED_FLAG}) elseif(CONFIG_SIZE_OPTIMIZATIONS) - set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_SIZE_FLAG}) # Default in kconfig + set(COMPILER_OPTIMIZATION_FLAG ${COMPILER_OPTIMIZE_FOR_SIZE_FLAG}) # Default in kconfig + set(ASM_OPTIMIZATION_FLAG ${ASM_OPTIMIZE_FOR_SIZE_FLAG}) elseif(CONFIG_SIZE_OPTIMIZATIONS_AGGRESSIVE) - set(OPTIMIZATION_FLAG ${OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG}) + set(COMPILER_OPTIMIZATION_FLAG ${COMPILER_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG}) + set(ASM_OPTIMIZATION_FLAG ${ASM_OPTIMIZE_FOR_SIZE_AGGRESSIVE_FLAG}) else() message(FATAL_ERROR "Unreachable code. Expected optimization level to have been chosen. See Kconfig.zephyr") @@ -245,8 +274,9 @@ SOC_* symbol.") endif() # Apply the final optimization flag(s) -zephyr_compile_options($<$:${OPTIMIZATION_FLAG}>) -zephyr_compile_options($<$:${OPTIMIZATION_FLAG}>) +zephyr_compile_options($<$:${ASM_OPTIMIZATION_FLAG}>) +zephyr_compile_options($<$:${COMPILER_OPTIMIZATION_FLAG}>) +zephyr_compile_options($<$:${COMPILER_OPTIMIZATION_FLAG}>) if(CONFIG_LTO) zephyr_compile_options($) @@ -301,6 +331,9 @@ if(CONFIG_CPP) elseif(CONFIG_STD_CPP2B) set(STD_CPP_DIALECT_FLAGS $) list(APPEND CMAKE_CXX_COMPILE_FEATURES ${compile_features_cpp20}) + elseif(CONFIG_STD_CPP23) + set(STD_CPP_DIALECT_FLAGS $) + list(APPEND CMAKE_CXX_COMPILE_FEATURES ${compile_features_cpp23}) else() message(FATAL_ERROR "Unreachable code. Expected C++ standard to have been chosen. See Kconfig.zephyr.") @@ -951,10 +984,14 @@ add_custom_target(${DEVICE_API_LD_TARGET} zephyr_linker_include_generated(CMAKE ${DEVICE_API_LINKER_SECTIONS_CMAKE}) -# Add a pseudo-target that is up-to-date when all generated headers -# are up-to-date. +# Create an interface library which collects the dependencies to Zephyr +# generated headers. Libraries containing files that include these headers can +# use add_dependencies or target_link_libraries against this target to ensure +# that generated headers are up-to-date before the libraries are built. This +# ordering dependency can be propagated to these libraries' dependenents via +# the PUBLIC or INTERFACE option of target_link_libraries. -add_custom_target(zephyr_generated_headers) +add_library(zephyr_generated_headers INTERFACE) add_dependencies(zephyr_generated_headers offsets_h version_h ) @@ -1051,8 +1088,10 @@ if(CONFIG_LLEXT) # Weak definitions for these must be added at the end of the link order # to avoid shadowing actual implementations. add_library(syscall_weakdefs syscall_weakdefs_llext.c) - add_dependencies(syscall_weakdefs zephyr_generated_headers) - target_link_libraries(syscall_weakdefs zephyr_interface) + target_link_libraries(syscall_weakdefs + zephyr_generated_headers + zephyr_interface + ) list(APPEND NO_WHOLE_ARCHIVE_LIBS syscall_weakdefs) endif() @@ -1701,8 +1740,12 @@ list(APPEND list(APPEND post_build_byproducts ${KERNEL_MAP_NAME}) # Use ';' as separator to get proper space in resulting command. -set(gap_fill_prop "$") -set(gap_fill "$<$:${gap_fill_prop}${CONFIG_BUILD_GAP_FILL_PATTERN}>") +# Ignore gapfill for RX target as some RX toolchains generate wrong output image when running +# gapfill for binary format. +if(NOT CONFIG_RX) + set(gap_fill_prop "$") + set(gap_fill "$<$:${gap_fill_prop}${CONFIG_BUILD_GAP_FILL_PATTERN}>") +endif() if(CONFIG_OUTPUT_PRINT_MEMORY_USAGE) target_link_libraries(${logical_target_for_zephyr_elf} $) @@ -1905,11 +1948,14 @@ if(CONFIG_BUILD_OUTPUT_S19) endif() if(CONFIG_OUTPUT_DISASSEMBLY) -if(CONFIG_OUTPUT_DISASSEMBLE_ALL) + if(CONFIG_OUTPUT_DISASSEMBLE_ALL) set(disassembly_type "$") - elseif (CONFIG_OUTPUT_DISASSEMBLY_WITH_SOURCE) + elseif(CONFIG_OUTPUT_DISASSEMBLY_WITH_SOURCE) set(disassembly_type "$") endif() + if(CONFIG_OUTPUT_DISASSEMBLY_NO_ALIASES) + list(APPEND disassembly_type "$") + endif() list(APPEND post_build_commands COMMAND $ @@ -1984,32 +2030,20 @@ if(CONFIG_BUILD_OUTPUT_COMPRESS_DEBUG_SECTIONS) endif() if(CONFIG_BUILD_OUTPUT_EXE) - if (NOT CONFIG_NATIVE_LIBRARY) - list(APPEND - post_build_commands - COMMAND - ${CMAKE_COMMAND} -E copy ${KERNEL_ELF_NAME} ${KERNEL_EXE_NAME} - ) - list(APPEND - post_build_byproducts - ${KERNEL_EXE_NAME} - ) - else() - if(CMAKE_GENERATOR STREQUAL "Unix Makefiles") - set(MAKE "${CMAKE_MAKE_PROGRAM}" CACHE FILEPATH "cmake defined make") - endif() - find_program(MAKE make REQUIRED) - add_custom_target(native_runner_executable - ALL - COMMENT "Building native simulator runner, and linking final executable" - COMMAND - ${MAKE} -f ${ZEPHYR_BASE}/scripts/native_simulator/Makefile all --warn-undefined-variables - -r NSI_CONFIG_FILE=${APPLICATION_BINARY_DIR}/zephyr/NSI/nsi_config - # nsi_config is created by the board cmake file - DEPENDS ${logical_target_for_zephyr_elf} - BYPRODUCTS ${KERNEL_EXE_NAME} - ) + if(CMAKE_GENERATOR STREQUAL "Unix Makefiles") + set(MAKE "${CMAKE_MAKE_PROGRAM}" CACHE FILEPATH "cmake defined make") endif() + find_program(MAKE make REQUIRED) + add_custom_target(native_runner_executable + ALL + COMMENT "Building native simulator runner, and linking final executable" + COMMAND + ${MAKE} -f ${ZEPHYR_BASE}/scripts/native_simulator/Makefile all --warn-undefined-variables + -r NSI_CONFIG_FILE=${APPLICATION_BINARY_DIR}/zephyr/NSI/nsi_config + # nsi_config is created by the board cmake file + DEPENDS ${logical_target_for_zephyr_elf} + BYPRODUCTS ${KERNEL_EXE_NAME} + ) set(BYPRODUCT_KERNEL_EXE_NAME "${PROJECT_BINARY_DIR}/${KERNEL_EXE_NAME}" CACHE FILEPATH "Kernel exe file" FORCE) endif() diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 4993e56c8b2..7391d570766 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -460,17 +460,6 @@ config NATIVE_BUILD Zephyr will be built targeting the host system for debug and development purposes. -config NATIVE_APPLICATION - bool - default y if ARCH_POSIX - depends on !NATIVE_LIBRARY - select NATIVE_BUILD - select DEPRECATED - help - Build as a native application that can run on the host and using - resources and libraries provided by the host. This option is deprecated - and will be removed in Zephyr v4.3 - config NATIVE_LIBRARY bool select NATIVE_BUILD @@ -507,7 +496,7 @@ config SIZE_OPTIMIZATIONS config SIZE_OPTIMIZATIONS_AGGRESSIVE bool "Aggressively optimize for size" help - Compiler optimizations wil be set to -Oz independently of other + Compiler optimizations will be set to -Oz independently of other options. config SPEED_OPTIMIZATIONS @@ -697,6 +686,13 @@ config OUTPUT_DISASSEMBLY_WITH_SOURCE the .lst file that can vary across platforms because of reasons such as having ".." include paths. +config OUTPUT_DISASSEMBLY_NO_ALIASES + bool "Disassemble with raw instruction mnemonics" + depends on OUTPUT_DISASSEMBLY + help + The .lst file will contain raw instruction mnemonic instead of + pseudo instructions. + config OUTPUT_PRINT_MEMORY_USAGE bool "Print memory usage to stdout" default y diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 77296a734a6..0514024f169 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -111,6 +111,7 @@ # Areas are sorted by name +# zephyr-keep-sorted-start strip(":) nofold ACPI: status: maintained maintainers: @@ -126,32 +127,37 @@ ACPI: tests: - acpi -Aesc Platform: - status: maintained - maintainers: - - dnltz - files: - - soc/aesc/ - - dts/riscv/aesc/ - - boards/aesc/ - files-regex: - - ^drivers/.*aesc(\.c)?$ - labels: - - "area: Aesc Silicon Platform" - -Antmicro platforms: +ADI Platforms: status: maintained maintainers: - - fkokosinski - - tgorochowik + - MaureenHelm collaborators: - - kgugala + - ozersa + - ttmut + - yasinustunerg + - galak + - microbuilder files: - - boards/antmicro/ - - soc/antmicro/ - - dts/arm/antmicro/ + - boards/adi/ + - boards/shields/eval*ardz/ + - boards/shields/pmod_acl/ + - drivers/*/*max* + - drivers/*/*max*/ + - drivers/dac/dac_ltc* + - drivers/ethernet/eth_adin* + - drivers/ethernet/phy/phy_adin* + - drivers/mdio/mdio_adin* + - drivers/sensor/adi/ + - drivers/stepper/adi_tmc/ + - dts/arm/adi/ + - dts/bindings/*/adi,* + - dts/bindings/*/lltc,* + - dts/bindings/*/maxim,* + - soc/adi/ + files-regex: + - ^drivers/(adc|dac|gpio|mfd|regulator)/.*adp?\d+ labels: - - "platform: Antmicro" + - "platform: ADI" ARC arch: status: maintained @@ -175,15 +181,40 @@ ARC arch: tests: - arch.arc -Arduino Platforms: +ARM Platforms: status: maintained maintainers: - - pillo79 + - wearyzen collaborators: - - facchinm + - ithinuel files: - - boards/arduino/ - - drivers/*/*modulino* + - boards/arm/mps*/ + - boards/arm/v2m_*/ + - boards/arm/fvp_base*/ + - soc/arm/mps*/ + - soc/arm/musca/ + - soc/arm/beetle/ + - soc/arm/designstart/ + - soc/arm/fvp_aemv8*/ + - dts/arm/armv*.dtsi + - dts/bindings/arm/arm*.yaml + - drivers/interrupt_controller/intc_gic* + labels: + - "platform: ARM" + +ARM SiP SVC: + status: odd fixes + files: + - subsys/sip_svc/ + - tests/subsys/sip_svc/ + - include/zephyr/sip_svc/ + - include/zephyr/drivers/sip_svc/ + - drivers/sip_svc/ + - samples/subsys/sip_svc/ + labels: + - "area: ARM SiP SVC" + tests: + - sip_svc ARM arch: status: maintained @@ -232,27 +263,6 @@ ARM64 arch: tests: - arch.arm64 -ARM Platforms: - status: maintained - maintainers: - - wearyzen - collaborators: - - ithinuel - files: - - boards/arm/mps*/ - - boards/arm/v2m_*/ - - boards/arm/fvp_base*/ - - soc/arm/mps*/ - - soc/arm/musca/ - - soc/arm/beetle/ - - soc/arm/designstart/ - - soc/arm/fvp_aemv8*/ - - dts/arm/armv*.dtsi - - dts/bindings/arm/arm*.yaml - - drivers/interrupt_controller/intc_gic* - labels: - - "platform: ARM" - ASPEED Platforms: status: odd fixes files: @@ -263,29 +273,18 @@ ASPEED Platforms: labels: - "platform: ASPEED" -ARM SiP SVC: - status: odd fixes - files: - - subsys/sip_svc/ - - tests/subsys/sip_svc/ - - include/zephyr/sip_svc/ - - include/zephyr/drivers/sip_svc/ - - drivers/sip_svc/ - labels: - - "area: ARM SiP SVC" - tests: - - sip_svc - -MIPS arch: - status: odd fixes +Aesc Platform: + status: maintained + maintainers: + - dnltz files: - - arch/mips/ - - include/zephyr/arch/mips/ - - boards/qemu/malta/ + - soc/aesc/ + - dts/riscv/aesc/ + - boards/aesc/ + files-regex: + - ^drivers/.*aesc(\.c)?$ labels: - - "area: MIPS" - tests: - - arch.mips + - "area: Aesc Silicon Platform" Ambiq Platforms: status: maintained @@ -320,6 +319,60 @@ AndesTech Platforms: labels: - "platform: Andes Technology" +Antmicro platforms: + status: maintained + maintainers: + - fkokosinski + - tgorochowik + collaborators: + - kgugala + files: + - boards/antmicro/ + - soc/antmicro/ + - dts/arm/antmicro/ + labels: + - "platform: Antmicro" + +Arduino Platforms: + status: maintained + maintainers: + - pillo79 + collaborators: + - facchinm + files: + - boards/arduino/ + - boards/shields/arduino_*/ + - drivers/*/*modulino* + +Base OS: + status: maintained + maintainers: + - andyross + - nashif + collaborators: + - dcpleung + - peter-mitsis + files: + - include/zephyr/sys/ + - lib/os/ + - tests/misc/print_format/ + - tests/lib/p4workq/ + - tests/lib/fdtable/ + files-exclude: + - include/zephyr/sys/cbprintf* + - tests/unit/cbprintf/ + - tests/lib/cbprintf_*/ + - lib/os/cbprintf* + - lib/os/Kconfig.cbprintf + - include/zephyr/sys/mem_manage.h + - include/zephyr/sys/mpsc_pbuf.h + - include/zephyr/sys/mpsc_packet.h + - lib/os/mpsc_pbuf.c + labels: + - "area: Base OS" + tests: + - printk + BeagleBoard Platforms: status: maintained maintainers: @@ -361,27 +414,63 @@ Binary Descriptors: tests: - bindesc -Bluetooth HCI: +Bluetooth Audio: status: maintained maintainers: - - jhedberg - - alwa-nordic - collaborators: - - hermabe - Thalley + collaborators: + - jhedberg - sjanc - - theob-pro - - HoZHel - - cvinayak + - asbjornsabo + - fredrikdanebjer + - larsgk + - pin-zephyr + - niym-ot + - jthm-ot + - babrsn files: - - include/zephyr/drivers/bluetooth/ - - include/zephyr/drivers/bluetooth.h - - drivers/bluetooth/ - - samples/bluetooth/hci_*/ - - tests/bsim/bluetooth/hci_uart/ - - dts/bindings/bluetooth/ + - subsys/bluetooth/audio/ + - include/zephyr/bluetooth/audio/ + - tests/bluetooth/audio/ + - tests/bsim/bluetooth/audio/ + - tests/bsim/bluetooth/audio_samples/ + - tests/bsim/bluetooth/tester/src/audio/ + - tests/bluetooth/shell/audio.conf + - tests/bluetooth/tester/overlay-le-audio.conf + - tests/bluetooth/tester/overlay-bt_ll_sw_split.conf + - tests/bluetooth/tester/src/audio/ + - doc/connectivity/bluetooth/api/audio/ + - doc/connectivity/bluetooth/shell/audio/ + - samples/bluetooth/bap*/ + - samples/bluetooth/cap*/ + - samples/bluetooth/ccp*/ + - samples/bluetooth/hap*/ + - samples/bluetooth/pbp*/ + - samples/bluetooth/tmap*/ labels: - - "area: Bluetooth HCI" + - "area: Bluetooth Audio" + - "area: Bluetooth" + tests: + - bluetooth.audio + +Bluetooth Classic: + status: maintained + maintainers: + - lylezhu2012 + collaborators: + - jhedberg + - MarkWangChinese + - gzh-terry + - makeshi + files: + - doc/connectivity/bluetooth/shell/classic/a2dp.rst + - subsys/bluetooth/common/ + - subsys/bluetooth/host/classic/ + - include/zephyr/bluetooth/classic/ + - tests/bluetooth/classic/ + - samples/bluetooth/classic/ + labels: + - "area: Bluetooth Classic" - "area: Bluetooth" tests: - bluetooth @@ -413,19 +502,46 @@ Bluetooth Controller: tests: - bluetooth.controller -Bluetooth Host: +Bluetooth HCI: status: maintained maintainers: - jhedberg - alwa-nordic collaborators: - hermabe - - rugeGerritsen - - sjanc - Thalley - - theob-pro + - sjanc + - HoZHel - cvinayak - files: + - PavelVPV + - HaavardRei + files: + - include/zephyr/drivers/bluetooth/ + - include/zephyr/drivers/bluetooth.h + - drivers/bluetooth/ + - samples/bluetooth/hci_*/ + - tests/bsim/bluetooth/hci_uart/ + - dts/bindings/bluetooth/ + labels: + - "area: Bluetooth HCI" + - "area: Bluetooth" + tests: + - bluetooth + +Bluetooth Host: + status: maintained + maintainers: + - jhedberg + - alwa-nordic + collaborators: + - hermabe + - rugeGerritsen + - sjanc + - Thalley + - cvinayak + - PavelVPV + - HaavardRei + files: - doc/connectivity/bluetooth/ - include/zephyr/bluetooth/ - samples/bluetooth/ @@ -464,6 +580,7 @@ Bluetooth Host: - samples/bluetooth/tmap*/ - samples/bluetooth/iso_*/ - samples/bluetooth/mesh*/ + - samples/bluetooth/classic/ - subsys/bluetooth/host/iso.c - subsys/bluetooth/host/iso_internal.h - subsys/bluetooth/host/shell/iso.c @@ -480,10 +597,32 @@ Bluetooth Host: - tests/bsim/bluetooth/hci_uart/ - tests/bsim/bluetooth/ll/ - tests/bsim/bluetooth/mesh/ + - tests/bsim/bluetooth/tester/src/audio/ labels: - "area: Bluetooth Host" - "area: Bluetooth" +Bluetooth ISO: + status: maintained + maintainers: + - Thalley + collaborators: + - jhedberg + - rugeGerritsen + - cvinayak + files: + - include/zephyr/bluetooth/iso.h + - doc/connectivity/bluetooth/shell/host/iso.rst + - samples/bluetooth/iso_*/ + - subsys/bluetooth/host/iso.c + - subsys/bluetooth/host/iso_internal.h + - subsys/bluetooth/host/shell/iso.c + labels: + - "area: Bluetooth ISO" + - "area: Bluetooth" + tests: + - bluetooth + Bluetooth Mesh: status: maintained maintainers: @@ -512,104 +651,37 @@ Bluetooth Mesh: tests: - bluetooth.mesh -Bluetooth Audio: +Bluetooth Qualification: status: maintained maintainers: - - Thalley - collaborators: - - jhedberg - - Casper-Bonde-Bose - - MariuszSkamra - sjanc - - asbjornsabo - - fredrikdanebjer - - larsgk - - pin-zephyr - - niym-ot - - jthm-ot - - babrsn - files: - - subsys/bluetooth/audio/ - - include/zephyr/bluetooth/audio/ - - tests/bluetooth/audio/ - - tests/bsim/bluetooth/audio/ - - tests/bsim/bluetooth/audio_samples/ - - tests/bluetooth/shell/audio.conf - - tests/bluetooth/tester/overlay-le-audio.conf - - tests/bluetooth/tester/overlay-bt_ll_sw_split.conf - - tests/bluetooth/tester/src/audio/ - - doc/connectivity/bluetooth/api/audio/ - - doc/connectivity/bluetooth/shell/audio/ - - samples/bluetooth/bap*/ - - samples/bluetooth/cap*/ - - samples/bluetooth/ccp*/ - - samples/bluetooth/hap*/ - - samples/bluetooth/pbp*/ - - samples/bluetooth/tmap*/ - labels: - - "area: Bluetooth Audio" - - "area: Bluetooth" - tests: - - bluetooth.audio - -Bluetooth Classic: - status: maintained - maintainers: - - lylezhu2012 collaborators: - - jhedberg - - MarkWangChinese - - gzh-terry - - makeshi - files: - - doc/connectivity/bluetooth/shell/classic/a2dp.rst - - subsys/bluetooth/common/ - - subsys/bluetooth/host/classic/ - - include/zephyr/bluetooth/classic/ - - tests/bluetooth/classic/ - labels: - - "area: Bluetooth Classic" - - "area: Bluetooth" - tests: - - bluetooth - -Bluetooth ISO: - status: maintained - maintainers: - Thalley - collaborators: - jhedberg - - rugeGerritsen - - cvinayak files: - - include/zephyr/bluetooth/iso.h - - doc/connectivity/bluetooth/shell/host/iso.rst - - samples/bluetooth/iso_*/ - - subsys/bluetooth/host/iso.c - - subsys/bluetooth/host/iso_internal.h - - subsys/bluetooth/host/shell/iso.c + - doc/connectivity/bluetooth/autopts/ + - tests/bluetooth/qualification/ + - tests/bluetooth/tester/ labels: - - "area: Bluetooth ISO" + - "area: Bluetooth Qualification" - "area: Bluetooth" tests: - bluetooth -Bluetooth Qualification: +Board/SoC configuration: status: maintained maintainers: - - sjanc + - tejlmand collaborators: - - Thalley - - jhedberg + - galak + - nashif + - nordicjm + - "57300" files: - - doc/connectivity/bluetooth/autopts/ - - tests/bluetooth/qualification/ - - tests/bluetooth/tester/ + - soc/Kconfig* + - boards/Kconfig* labels: - - "area: Bluetooth Qualification" - - "area: Bluetooth" - tests: - - bluetooth + - "area: Board/SoC configuration" Bootloaders: status: odd fixes @@ -620,6 +692,27 @@ Bootloaders: tests: - bootloader +Bouffalolab Platforms: + status: maintained + maintainers: + - nandojve + - VynDragon + files: + - boards/bflb/ + - drivers/*/*bflb* + - dts/riscv/bflb/ + - dts/bindings/*/bflb,* + - soc/bflb/ + labels: + - "platform: Bouffalo Lab" + +Broadcom Platforms: + status: odd fixes + files: + - dts/*/broadcom/ + - soc/brcm/ + - boards/brcm/ + Build system: status: maintained maintainers: @@ -645,25 +738,31 @@ Build system: - scripts/list_boards.py - scripts/list_hardware.py - scripts/schemas/*-schema.yml + - tests/misc/test_build/ + - tests/application_development/ + - samples/application_development/ labels: - "area: Build System" tests: - buildsystem -Board/SoC configuration: +C library: status: maintained maintainers: - - tejlmand + - stephanosio collaborators: - - galak + - aescolar - nashif - - nordicjm - - "57300" + - keith-packard + - cfriedt files: - - soc/Kconfig* - - boards/Kconfig* + - lib/libc/ + - tests/lib/c_lib/ + - tests/lib/newlib/ labels: - - "area: Board/SoC configuration" + - "area: C Library" + tests: + - libraries.libc "C++": status: maintained @@ -681,41 +780,6 @@ Board/SoC configuration: tests: - cpp -Cache: - status: maintained - maintainers: - - carlocaione - collaborators: - - nashif - files: - - include/zephyr/drivers/cache.h - - include/zephyr/cache.h - - doc/hardware/cache/index.rst - - drivers/cache/ - - tests/kernel/cache/ - labels: - - "area: Cache" - tests: - - kernel.cache - -C library: - status: maintained - maintainers: - - stephanosio - collaborators: - - aescolar - - nashif - - keith-packard - - cfriedt - files: - - lib/libc/ - - tests/lib/c_lib/ - - tests/lib/newlib/ - labels: - - "area: C Library" - tests: - - libraries.libc - CMSIS API layer: status: odd fixes collaborators: @@ -733,39 +797,6 @@ CMSIS API layer: - portability.cmsis_rtos_v1 - portability.cmsis_rtos_v2 -DAP: - status: maintained - maintainers: - - jfischer-no - collaborators: - - maxd-nordic - files: - - include/zephyr/drivers/swdp.h - - drivers/dp/ - - subsys/dap/ - - samples/subsys/dap/ - description: >- - Debug Access Port controller - labels: - - "area: dap" - -DSP subsystem: - status: maintained - maintainers: - - stephanosio - - yperess - files: - - subsys/dsp/ - - tests/subsys/dsp/ - - include/zephyr/dsp/dsp.h - - include/zephyr/dsp/types.h - - include/zephyr/dsp/ - - doc/services/dsp/ - labels: - - "area: DSP" - tests: - - zdsp - CMSIS-DSP integration: status: maintained maintainers: @@ -777,6 +808,7 @@ CMSIS-DSP integration: - modules/cmsis-dsp/ - tests/benchmarks/cmsis_dsp/ - tests/lib/cmsis_dsp/ + - samples/modules/cmsis_dsp/ labels: - "area: CMSIS-DSP" tests: @@ -797,10 +829,27 @@ CMSIS-NN integration: tests: - libraries.cmsis_nn -Coding Guidelines: +Cache: status: maintained maintainers: - - keith-zephyr + - carlocaione + collaborators: + - nashif + files: + - include/zephyr/drivers/cache.h + - include/zephyr/cache.h + - doc/hardware/cache/index.rst + - drivers/cache/ + - tests/kernel/cache/ + labels: + - "area: Cache" + tests: + - kernel.cache + +Coding Guidelines: + status: maintained + maintainers: + - keith-zephyr collaborators: - nashif - carlescufi @@ -839,6 +888,7 @@ Common Architecture Interface: - include/zephyr/arch/common/ - tests/arch/common/ - doc/hardware/porting/arch.rst + - doc/hardware/arch/ labels: - "area: Architectures" tests: @@ -854,6 +904,72 @@ Console: tests: - sample.console +Continuous Integration: + status: maintained + maintainers: + - stephanosio + - nashif + collaborators: + - fabiobaltieri + - kartben + files: + - .github/ + - scripts/requirements-actions.* + - scripts/ci/ + - scripts/make_bugs_pickle.py + - .checkpatch.conf + - scripts/gitlint/ + - scripts/set_assignees.py + labels: + - "area: Continuous Integration" + +DAP: + status: maintained + maintainers: + - jfischer-no + collaborators: + - maxd-nordic + files: + - include/zephyr/drivers/swdp.h + - drivers/dp/ + - subsys/dap/ + - samples/subsys/dap/ + description: >- + Debug Access Port controller + labels: + - "area: dap" + +DFU: + status: maintained + maintainers: + - de-nordic + - nordicjm + files: + - include/zephyr/dfu/ + - subsys/dfu/ + - tests/subsys/dfu/ + labels: + - "area: DFU" + tests: + - dfu + +DSP subsystem: + status: maintained + maintainers: + - stephanosio + - yperess + files: + - subsys/dsp/ + - tests/subsys/dsp/ + - include/zephyr/dsp/dsp.h + - include/zephyr/dsp/types.h + - include/zephyr/dsp/ + - doc/services/dsp/ + labels: + - "area: DSP" + tests: + - zdsp + Debug: status: maintained maintainers: @@ -871,13 +987,12 @@ Debug: - doc/services/profiling/perf.rst - samples/subsys/profiling/perf/ - scripts/profiling/stackcollapse.py - - subsys/profiling/perf/ + - subsys/profiling/ labels: - "area: Debugging" tests: - debug - "Debug: Symtab": status: maintained maintainers: @@ -903,6 +1018,7 @@ Demand Paging: files: - subsys/demand_paging/ - tests/kernel/mem_protect/demand_paging/ + - samples/subsys/demand_paging/ tests: - kernel.demand_paging @@ -926,20 +1042,6 @@ Device Driver Model: - kernel.device - init -DFU: - status: maintained - maintainers: - - de-nordic - - nordicjm - files: - - include/zephyr/dfu/ - - subsys/dfu/ - - tests/subsys/dfu/ - labels: - - "area: DFU" - tests: - - dfu - Devicetree: status: maintained maintainers: @@ -1011,7 +1113,9 @@ Display drivers: - samples/subsys/display/ - tests/subsys/display/ - doc/hardware/peripherals/display/ - - tests/drivers/*/display/ + - tests/drivers/display/ + - tests/drivers/build_all/display/ + - samples/drivers/display/ labels: - "area: Display" tests: @@ -1068,22 +1172,9 @@ Documentation Infrastructure: labels: - "area: Documentation Infrastructure" -Release Notes: - status: maintained - maintainers: - - danieldegrasse - - dkalowsk - collaborators: - - kartben - files: - - doc/releases/migration-guide-* - - doc/releases/release-notes-* - labels: - - "Release Notes" - "Drivers: ADC": - status: maintained - maintainers: + status: odd fixes + collaborators: - anangl files: - drivers/adc/ @@ -1110,24 +1201,12 @@ Release Notes: - drivers/audio/ - include/zephyr/audio/ - doc/hardware/peripherals/audio/ + - samples/drivers/audio/ + - tests/drivers/build_all/audio/ + - tests/drivers/audio/ labels: - "area: Audio" -"Drivers: bbram": - status: maintained - maintainers: - - yperess - files: - - tests/drivers/bbram/ - - tests/drivers/build_all/bbram/ - - drivers/bbram/ - - include/zephyr/drivers/bbram.h - - doc/hardware/peripherals/bbram.rst - labels: - - "area: Battery Backed RAM (bbram)" - tests: - - drivers.bbram - "Drivers: Aux display": status: maintained maintainers: @@ -1139,6 +1218,9 @@ Release Notes: - drivers/auxdisplay/* - dts/bindings/auxdisplay/* - doc/hardware/peripherals/auxdisplay.rst + - samples/drivers/auxdisplay/ + - tests/drivers/build_all/auxdisplay/ + - samples/drivers/auxdisplay_*/ labels: - "area: Aux display" tests: @@ -1172,6 +1254,7 @@ Release Notes: - samples/net/sockets/can/ - samples/subsys/canbus/ - scripts/west_commands/runners/canopen_program.py + - snippets/socketcan-native-sim/ - subsys/canbus/ - subsys/net/l2/canbus/ - tests/drivers/build_all/can/ @@ -1216,6 +1299,7 @@ Release Notes: - tests/drivers/clock_control/ - include/zephyr/drivers/clock_control/ - doc/hardware/peripherals/clock_control.rst + - samples/drivers/clock_control_*/ labels: - "area: Clock control" tests: @@ -1337,19 +1421,6 @@ Release Notes: labels: - "area: DAI" -"Drivers: Devmux": - status: maintained - maintainers: - - cfriedt - files: - - drivers/misc/devmux/ - - include/zephyr/drivers/misc/devmux/ - - tests/drivers/console_switching/ - labels: - - "area: Devmux" - tests: - - drivers.devmux - "Drivers: DMA": status: maintained maintainers: @@ -1368,6 +1439,31 @@ Release Notes: tests: - drivers.dma +"Drivers: Debug": + status: maintained + maintainers: + - asmellby + collaborators: + - nordic-krch + files: + - drivers/debug/ + - dts/bindings/debug/ + labels: + - "area: Debugging" + +"Drivers: Devmux": + status: maintained + maintainers: + - cfriedt + files: + - drivers/misc/devmux/ + - include/zephyr/drivers/misc/devmux/ + - tests/drivers/console_switching/ + labels: + - "area: Devmux" + tests: + - drivers.devmux + "Drivers: EDAC": status: maintained maintainers: @@ -1379,6 +1475,7 @@ Release Notes: - samples/subsys/edac/ - tests/subsys/edac/ - doc/hardware/peripherals/edac/ + - include/zephyr/drivers/edac/ labels: - "area: EDAC" tests: @@ -1402,22 +1499,6 @@ Release Notes: tests: - drivers.eeprom -"Drivers: Entropy": - status: maintained - maintainers: - - ceolin - collaborators: - - tomi-font - files: - - drivers/entropy/ - - include/zephyr/drivers/entropy.h - - tests/drivers/entropy/ - - doc/hardware/peripherals/entropy.rst - labels: - - "area: Crypto / RNG" - tests: - - drivers.entropy - "Drivers: ESPI": status: maintained maintainers: @@ -1440,6 +1521,22 @@ Release Notes: - sample.drivers.espi - drivers.espi +"Drivers: Entropy": + status: maintained + maintainers: + - ceolin + collaborators: + - tomi-font + files: + - drivers/entropy/ + - include/zephyr/drivers/entropy.h + - tests/drivers/entropy/ + - doc/hardware/peripherals/entropy.rst + labels: + - "area: Crypto / RNG" + tests: + - drivers.entropy + "Drivers: Ethernet": status: maintained maintainers: @@ -1457,12 +1554,33 @@ Release Notes: - tests/drivers/ethernet/ - include/zephyr/drivers/ethernet/ - include/zephyr/net/phy.h + - include/zephyr/net/mii.h - include/zephyr/net/ethernet.h + - samples/drivers/ethernet/ labels: - "area: Ethernet" tests: - net.ethernet +"Drivers: FPGA": + status: maintained + maintainers: + - cfriedt + collaborators: + - tgorochowik + - fkokosinski + - msierszulski + files: + - drivers/fpga/ + - dts/bindings/fpga/ + - include/zephyr/drivers/fpga.h + - samples/drivers/fpga/ + - tests/drivers/build_all/fpga/ + labels: + - "area: FPGA" + tests: + - drivers.fpga + "Drivers: Flash": status: maintained maintainers: @@ -1481,65 +1599,32 @@ Release Notes: - include/zephyr/drivers/flash/ - tests/drivers/flash_simulator/ - tests/drivers/build_all/flash/ + - tests/drivers/flash_api/ labels: - "area: Flash" tests: - drivers.flash -"Drivers: FPGA": - status: maintained - maintainers: - - cfriedt - collaborators: - - tgorochowik - - fkokosinski - - msierszulski - files: - - drivers/fpga/ - - dts/bindings/fpga/ - - include/zephyr/drivers/fpga.h - - samples/drivers/fpga/ - - tests/drivers/build_all/fpga/ - labels: - - "area: FPGA" - tests: - - drivers.fpga - "Drivers: Fuel Gauge": status: maintained maintainers: - aaronemassey - teburd + collaborators: + - DBS06 files: - drivers/fuel_gauge/ - dts/bindings/fuel-gauge/ - include/zephyr/drivers/fuel_gauge.h - tests/drivers/fuel_gauge/ - doc/hardware/peripherals/fuel_gauge.rst + - samples/drivers/fuel_gauge/ + - tests/drivers/build_all/fuel_gauge/ labels: - "area: Fuel Gauge" tests: - drivers.fuel_gauge -"Drivers: GPIO": - status: odd fixes - collaborators: - - henrikbrixandersen - - mnkp - files: - - doc/hardware/peripherals/gpio.rst - - drivers/gpio/ - - dts/bindings/gpio/ - - include/zephyr/drivers/gpio/ - - include/zephyr/drivers/gpio.h - - include/zephyr/dt-bindings/gpio/ - - tests/drivers/gpio/ - - tests/drivers/build_all/gpio/ - labels: - - "area: GPIO" - tests: - - drivers.gpio - "Drivers: GNSS": status: maintained maintainers: @@ -1547,36 +1632,45 @@ Release Notes: collaborators: - tomi-font - fabiobaltieri + - ubieda files: - doc/hardware/peripherals/gnss.rst - drivers/gnss/ - include/zephyr/data/navigation.h - include/zephyr/drivers/gnss.h - include/zephyr/drivers/gnss/ + - include/zephyr/gnss/ - dts/bindings/gnss/ - include/zephyr/dt-bindings/gnss/ - tests/drivers/build_all/gnss/ - tests/drivers/gnss/ + - tests/subsys/gnss/ + - samples/drivers/gnss/ + - subsys/gnss/ labels: - "area: GNSS" tests: - drivers.gnss + - gnss -"Drivers: Haptics": - status: maintained - maintainers: - - rriveramcrus +"Drivers: GPIO": + status: odd fixes + collaborators: + - henrikbrixandersen + - mnkp files: - - drivers/haptics/ - - dts/bindings/haptics/ - - include/zephyr/drivers/haptics.h - - doc/hardware/peripherals/haptics.rst - - tests/drivers/build_all/haptics/ - - samples/drivers/haptics/ + - doc/hardware/peripherals/gpio.rst + - drivers/gpio/ + - dts/bindings/gpio/ + - include/zephyr/drivers/gpio/ + - include/zephyr/drivers/gpio.h + - include/zephyr/dt-bindings/gpio/ + - tests/drivers/gpio/ + - tests/drivers/build_all/gpio/ labels: - - "area: Haptics" + - "area: GPIO" tests: - - drivers.haptics + - drivers.gpio "Drivers: HW Info": status: maintained @@ -1593,6 +1687,22 @@ Release Notes: tests: - drivers.hwinfo +"Drivers: Haptics": + status: maintained + maintainers: + - rriveramcrus + files: + - drivers/haptics/ + - dts/bindings/haptics/ + - include/zephyr/drivers/haptics.h + - doc/hardware/peripherals/haptics.rst + - tests/drivers/build_all/haptics/ + - samples/drivers/haptics/ + labels: + - "area: Haptics" + tests: + - drivers.haptics + "Drivers: Hardware Spinlock": status: odd fixes files: @@ -1673,122 +1783,6 @@ Release Notes: tests: - drivers.ieee802154 -"Drivers: Mbox": - status: maintained - maintainers: - - carlocaione - collaborators: - - wearyzen - - ithinuel - files: - - include/zephyr/drivers/mbox.h - - drivers/mbox/ - - samples/drivers/mbox/ - - dts/bindings/mbox/ - - doc/hardware/peripherals/mbox.rst - labels: - - "area: mbox" - tests: - - sample.drivers.mbox - -"Drivers: MEMC": - status: odd fixes - files: - - drivers/memc/ - - samples/drivers/memc/ - - tests/drivers/memc/ - - include/zephyr/dt-bindings/memory-controller/ - - dts/bindings/memory-controllers/ - labels: - - "area: MEMC" - tests: - - samples.drivers.memc - - drivers.memc - -"Drivers: MDIO": - status: maintained - maintainers: - - maass-hamburg - collaborators: - - decsny - files: - - doc/hardware/peripherals/mdio.rst - - drivers/mdio/ - - include/zephyr/drivers/mdio.h - - include/zephyr/net/mdio.h - - tests/drivers/build_all/mdio/ - - dts/bindings/mdio/ - labels: - - "area: MDIO" - tests: - - drivers.mdio - -"Drivers: MIPI-DSI": - status: odd fixes - files: - - drivers/mipi_dsi/ - - doc/hardware/peripherals/mipi_dsi.rst - - include/zephyr/drivers/mipi_dsi.h - - include/zephyr/drivers/mipi_dsi/ - - tests/drivers/mipi_dsi/ - - include/zephyr/dt-bindings/mipi_dsi/ - - dts/bindings/mipi-dsi/ - labels: - - "area: MIPI-DSI" - tests: - - drivers.mipi_dsi - -"Drivers: MSPI": - status: maintained - maintainers: - - swift-tk - files: - - drivers/mspi/ - - drivers/memc/*mspi* - - drivers/flash/*mspi* - - include/zephyr/drivers/mspi.h - - include/zephyr/drivers/mspi/ - - samples/drivers/mspi/ - - tests/drivers/mspi/ - - doc/hardware/peripherals/mspi.rst - - dts/bindings/mspi/ - - dts/bindings/mtd/mspi* - labels: - - "area: MSPI" - tests: - - drivers.mspi - -"Drivers: Reset": - status: odd fixes - collaborators: - - decsny - files: - - drivers/reset/ - - include/zephyr/drivers/reset.h - - dts/bindings/reset/ - - include/zephyr/dt-bindings/reset/ - -"Interrupt Handling": - status: odd fixes - collaborators: - - ycsin - - dcpleung - - nashif - files: - - drivers/interrupt_controller/ - - dts/bindings/interrupt-controller/ - - include/zephyr/drivers/interrupt_controller/ - - include/zephyr/dt-bindings/interrupt-controller/ - - include/zephyr/irq* - - include/zephyr/sw_isr_table.h - - include/zephyr/shared_irq.h - - tests/drivers/interrupt_controller/ - - tests/drivers/build_all/interrupt_controller/ - labels: - - "area: Interrupt Controller" - tests: - - drivers.interrupt_controller - "Drivers: IPM": status: odd fixes collaborators: @@ -1812,6 +1806,8 @@ Release Notes: maintainers: - Mani-Sadhasivam - simonguinot + collaborators: + - jeppenodgaard files: - drivers/led/ - include/zephyr/drivers/led/ @@ -1834,17 +1830,51 @@ Release Notes: collaborators: - soburi - thedjnK + - jeppenodgaard files: - drivers/led_strip/ - dts/bindings/led_strip/ - include/zephyr/drivers/led_strip.h - tests/drivers/build_all/led_strip/ - include/zephyr/drivers/led_strip/ + - samples/drivers/led/led_strip/ labels: - "area: LED" tests: - drivers.led_strip +"Drivers: MDIO": + status: maintained + maintainers: + - maass-hamburg + collaborators: + - decsny + files: + - doc/hardware/peripherals/mdio.rst + - drivers/mdio/ + - include/zephyr/drivers/mdio.h + - include/zephyr/net/mdio.h + - tests/drivers/build_all/mdio/ + - dts/bindings/mdio/ + labels: + - "area: MDIO" + tests: + - drivers.mdio + +"Drivers: MEMC": + status: odd fixes + files: + - drivers/memc/ + - samples/drivers/memc/ + - tests/drivers/memc/ + - include/zephyr/dt-bindings/memory-controller/ + - dts/bindings/memory-controllers/ + labels: + - "area: MEMC" + tests: + - samples.drivers.memc + - drivers.memc + "Drivers: MFD": status: odd fixes collaborators: @@ -1861,74 +1891,102 @@ Release Notes: tests: - drivers.mfd -"Drivers: Modem": +"Drivers: MIPI DBI": status: maintained maintainers: - - rerickson1 + - danieldegrasse files: - - drivers/modem/ - - tests/drivers/build_all/modem/ - - dts/bindings/modem/ - - include/zephyr/drivers/modem/ + - drivers/mipi_dbi/ + - dts/bindings/mipi-dbi/ + - include/zephyr/dt-bindings/mipi_dbi/ labels: - - "area: Modem Drivers" + - "area: Display Controller" + +"Drivers: MIPI-DSI": + status: odd fixes + files: + - drivers/mipi_dsi/ + - doc/hardware/peripherals/mipi_dsi.rst + - include/zephyr/drivers/mipi_dsi.h + - include/zephyr/drivers/mipi_dsi/ + - tests/drivers/mipi_dsi/ + - include/zephyr/dt-bindings/mipi_dsi/ + - dts/bindings/mipi-dsi/ + labels: + - "area: MIPI-DSI" tests: - - drivers.modem + - drivers.mipi_dsi -"Drivers: Regulators": +"Drivers: MSPI": status: maintained maintainers: - - nordic-auko - - seov-nordic - collaborators: - - danieldegrasse - - aasinclair + - swift-tk files: - - drivers/regulator/ - - include/zephyr/drivers/regulator/ - - include/zephyr/drivers/regulator.h - - include/zephyr/dt-bindings/regulator/ - - tests/drivers/regulator/ - - tests/drivers/build_all/regulator/ - - doc/hardware/peripherals/regulators.rst - - dts/bindings/regulator/ + - drivers/mspi/ + - drivers/memc/*mspi* + - drivers/flash/*mspi* + - include/zephyr/drivers/mspi.h + - include/zephyr/drivers/mspi/ + - samples/drivers/mspi/ + - tests/drivers/mspi/ + - doc/hardware/peripherals/mspi.rst + - dts/bindings/mspi/ + - dts/bindings/mtd/mspi* labels: - - "area: Regulators" + - "area: MSPI" tests: - - drivers.regulator + - drivers.mspi -"Drivers: Retained Memory": +"Drivers: Mbox": status: maintained maintainers: - - nordicjm - files: - - drivers/retained_mem/ - - dts/bindings/retained_mem/ - - include/zephyr/drivers/retained_mem.h - - tests/drivers/retained_mem/ - - doc/hardware/peripherals/retained_mem.rst - - dts/bindings/retained_mem/ + - carlocaione + collaborators: + - wearyzen + - ithinuel + files: + - include/zephyr/drivers/mbox.h + - drivers/mbox/ + - samples/drivers/mbox/ + - dts/bindings/mbox/ + - doc/hardware/peripherals/mbox.rst + - tests/drivers/mbox/ + - samples/drivers/mbox_data/ labels: - - "area: Retained Memory" + - "area: mbox" tests: - - drivers.retained_mem + - sample.drivers.mbox -"Drivers: RTC": +"Drivers: Memory Management": status: maintained maintainers: - - bjarki-andreasen + - dcpleung + collaborators: + - ceolin + - edersondisouza + - jxstelter files: - - drivers/rtc/ - - include/zephyr/drivers/rtc/ - - tests/drivers/rtc/ - - doc/hardware/peripherals/rtc.rst - - include/zephyr/drivers/rtc.h - - tests/drivers/build_all/rtc/ - - dts/bindings/rtc/ + - include/zephyr/drivers/mm/ + - drivers/mm/ + - tests/boards/intel_adsp/mm/ + - dts/bindings/mm/ labels: - - "area: RTC" + - "area: Memory Management" + +"Drivers: Modem": + status: maintained + maintainers: + - rerickson1 + files: + - drivers/modem/ + - tests/drivers/build_all/modem/ + - dts/bindings/modem/ + - include/zephyr/drivers/modem/ + - tests/drivers/modem/ + labels: + - "area: Modem Drivers" tests: - - drivers.rtc + - drivers.modem "Drivers: PCI": status: maintained @@ -1960,22 +2018,21 @@ Release Notes: tests: - samples.drivers.peci -"Drivers: Pin Control": - status: odd fixes +"Drivers: PM CPU ops": + status: maintained + maintainers: + - carlocaione collaborators: - - gmarull + - gdengi + - nbalabak files: - - doc/hardware/pinctrl/ - - include/zephyr/drivers/pinctrl/ - - include/zephyr/drivers/pinctrl.h - - drivers/pinctrl/ - - tests/drivers/pinctrl/ - - dts/bindings/pinctrl/ - - include/zephyr/dt-bindings/pinctrl/ + - drivers/pm_cpu_ops/ + - include/zephyr/drivers/pm_cpu_ops/ + - include/zephyr/drivers/pm_cpu_ops.h + - include/zephyr/arch/arm64/arm-smccc.h + - dts/bindings/pm_cpu_ops/ labels: - - "area: Pinctrl" - tests: - - drivers.pinctrl + - "area: PM CPU ops" "Drivers: PS2": status: odd fixes @@ -1990,37 +2047,39 @@ Release Notes: tests: - sample.drivers.espi.ps2 -"Drivers: PTP Clock": +"Drivers: PSI5": status: maintained maintainers: - - yangbolu1991 + - manuargue + - Dat-NguyenDuy + collaborators: + - congnguyenhuu files: - - drivers/ptp_clock/ - - include/zephyr/drivers/ptp_clock.h + - drivers/psi5/ + - include/zephyr/drivers/psi5/ + - dts/bindings/psi5/ + - doc/hardware/peripherals/psi5.rst + - tests/drivers/psi5/ + - samples/drivers/psi5/ labels: - - "area: Clocks" + - "area: PSI5" + tests: + - drivers.psi5 -"Drivers: PM CPU ops": +"Drivers: PTP Clock": status: maintained maintainers: - - carlocaione - collaborators: - - gdengi - - nbalabak + - yangbolu1991 files: - - drivers/pm_cpu_ops/ - - include/zephyr/drivers/pm_cpu_ops/ - - include/zephyr/drivers/pm_cpu_ops.h - - include/zephyr/arch/arm64/arm-smccc.h - - dts/bindings/pm_cpu_ops/ + - drivers/ptp_clock/ + - include/zephyr/drivers/ptp_clock.h labels: - - "area: PM CPU ops" + - "area: Clocks" "Drivers: PWM": - status: maintained - maintainers: - - anangl + status: odd fixes collaborators: + - anangl - henrikbrixandersen files: - drivers/pwm/ @@ -2032,11 +2091,96 @@ Release Notes: - tests/drivers/build_all/pwm/ - include/zephyr/drivers/pwm.h - include/zephyr/drivers/pwm/ + - samples/basic/blinky_pwm/ labels: - "area: PWM" tests: - drivers.pwm +"Drivers: Pin Control": + status: odd fixes + collaborators: + - gmarull + files: + - doc/hardware/pinctrl/ + - include/zephyr/drivers/pinctrl/ + - include/zephyr/drivers/pinctrl.h + - drivers/pinctrl/ + - tests/drivers/pinctrl/ + - dts/bindings/pinctrl/ + - include/zephyr/dt-bindings/pinctrl/ + labels: + - "area: Pinctrl" + tests: + - drivers.pinctrl + +"Drivers: RTC": + status: maintained + maintainers: + - bjarki-andreasen + files: + - drivers/rtc/ + - include/zephyr/drivers/rtc/ + - tests/drivers/rtc/ + - doc/hardware/peripherals/rtc.rst + - include/zephyr/drivers/rtc.h + - tests/drivers/build_all/rtc/ + - dts/bindings/rtc/ + - samples/drivers/rtc/ + labels: + - "area: RTC" + tests: + - drivers.rtc + +"Drivers: Regulators": + status: maintained + maintainers: + - nordic-auko + - seov-nordic + collaborators: + - danieldegrasse + - aasinclair + files: + - drivers/regulator/ + - include/zephyr/drivers/regulator/ + - include/zephyr/drivers/regulator.h + - include/zephyr/dt-bindings/regulator/ + - tests/drivers/regulator/ + - tests/drivers/build_all/regulator/ + - doc/hardware/peripherals/regulators.rst + - dts/bindings/regulator/ + labels: + - "area: Regulators" + tests: + - drivers.regulator + +"Drivers: Reset": + status: odd fixes + collaborators: + - decsny + files: + - drivers/reset/ + - include/zephyr/drivers/reset.h + - dts/bindings/reset/ + - include/zephyr/dt-bindings/reset/ + - tests/drivers/reset/ + +"Drivers: Retained Memory": + status: maintained + maintainers: + - nordicjm + files: + - drivers/retained_mem/ + - dts/bindings/retained_mem/ + - include/zephyr/drivers/retained_mem.h + - tests/drivers/retained_mem/ + - doc/hardware/peripherals/retained_mem.rst + - dts/bindings/retained_mem/ + labels: + - "area: Retained Memory" + tests: + - drivers.retained_mem + "Drivers: SDHC": status: maintained maintainers: @@ -2052,53 +2196,24 @@ Release Notes: tests: - drivers.sdhc -"Drivers: Serial/UART": - status: maintained - maintainers: - - dcpleung - files: - - drivers/serial/ - - include/zephyr/drivers/uart.h - - include/zephyr/drivers/uart/ - - dts/bindings/serial/ - - samples/drivers/uart/ - - tests/drivers/uart/ - - tests/drivers/build_all/uart/ - - doc/hardware/peripherals/uart.rst - - include/zephyr/drivers/serial/ - - include/zephyr/drivers/uart_pipe.h - labels: - - "area: UART" - tests: - - drivers.uart - -"Drivers: Sensors": +"Drivers: SENT": status: maintained maintainers: - - MaureenHelm + - manuargue + - Dat-NguyenDuy collaborators: - - avisconti - - teburd - - yperess - - tristan-google - - ubieda - - jeppenodgaard - - asemjonovs + - congnguyenhuu files: - - drivers/sensor/ - - include/zephyr/drivers/sensor.h - - include/zephyr/drivers/sensor_data_types.h - - samples/sensor/ - - tests/drivers/sensor/ - - dts/bindings/sensor/ - - include/zephyr/drivers/sensor/ - - include/zephyr/dt-bindings/sensor/ - - doc/hardware/peripherals/sensor/ - - tests/drivers/build_all/sensor/ + - drivers/sent/ + - include/zephyr/drivers/sent/ + - dts/bindings/sent/ + - doc/hardware/peripherals/sent.rst + - tests/drivers/sent/ + - samples/drivers/sent/ labels: - - "area: Sensors" + - "area: SENT" tests: - - drivers.sensor + - drivers.sent "Drivers: SMBus": status: maintained @@ -2122,6 +2237,7 @@ Release Notes: - tbursztyka collaborators: - teburd + - decsny files: - drivers/spi/ - include/zephyr/drivers/spi.h @@ -2129,24 +2245,75 @@ Release Notes: - dts/bindings/spi/ - include/zephyr/dt-bindings/spi/ - doc/hardware/peripherals/spi.rst + - tests/drivers/build_all/spi/ + - samples/drivers/spi_*/ labels: - "area: SPI" tests: - drivers.spi -"Drivers: Stepper": +"Drivers: Sensors": status: maintained maintainers: - - jilaypandya + - MaureenHelm collaborators: - - bjarki-andreasen - - dipakgmx - - fabiobaltieri - - faxe1008 - - jbehrensnx + - avisconti + - teburd + - yperess + - tristan-google + - ubieda + - jeppenodgaard + - asemjonovs files: - - drivers/stepper/ - - include/zephyr/drivers/stepper/ + - drivers/sensor/ + - include/zephyr/drivers/sensor.h + - include/zephyr/drivers/sensor_data_types.h + - samples/sensor/ + - tests/drivers/sensor/ + - dts/bindings/sensor/ + - include/zephyr/drivers/sensor/ + - include/zephyr/dt-bindings/sensor/ + - doc/hardware/peripherals/sensor/ + - tests/drivers/build_all/sensor/ + - include/zephyr/drivers/sensor_* + labels: + - "area: Sensors" + tests: + - drivers.sensor + +"Drivers: Serial/UART": + status: maintained + maintainers: + - dcpleung + files: + - drivers/serial/ + - include/zephyr/drivers/uart.h + - include/zephyr/drivers/uart/ + - dts/bindings/serial/ + - samples/drivers/uart/ + - tests/drivers/uart/ + - tests/drivers/build_all/uart/ + - doc/hardware/peripherals/uart.rst + - include/zephyr/drivers/serial/ + - include/zephyr/drivers/uart_pipe.h + labels: + - "area: UART" + tests: + - drivers.uart + +"Drivers: Stepper": + status: maintained + maintainers: + - jilaypandya + collaborators: + - bjarki-andreasen + - dipakgmx + - fabiobaltieri + - faxe1008 + - jbehrensnx + files: + - drivers/stepper/ + - include/zephyr/drivers/stepper/ - include/zephyr/drivers/stepper.h - dts/bindings/stepper/ - doc/hardware/peripherals/stepper.rst @@ -2158,6 +2325,17 @@ Release Notes: tests: - drivers.stepper +"Drivers: Syscon": + status: maintained + maintainers: + - carlocaione + files: + - include/zephyr/drivers/syscon.h + - drivers/syscon/ + - tests/drivers/syscon/ + tests: + - drivers.syscon + "Drivers: System timer": status: maintained maintainers: @@ -2172,6 +2350,36 @@ Release Notes: labels: - "area: Timer" +"Drivers: Time Aware GPIO": + status: maintained + maintainers: + - akanisetti + files: + - doc/hardware/peripherals/tgpio.rst + - drivers/misc/timeaware_gpio/ + - include/zephyr/drivers/misc/timeaware_gpio/ + - samples/drivers/misc/timeaware_gpio/ + labels: + - "area: Time Aware GPIO" + tests: + - sample.drivers.misc.timeaware_gpio + +"Drivers: VIRTIO": + status: maintained + maintainers: + - fkokosinski + - tgorochowik + collaborators: + - kgugala + files: + - drivers/virtio/ + - dts/bindings/virtio/ + - include/zephyr/drivers/virtio.h + - include/zephyr/drivers/virtio/ + - tests/drivers/build_all/virtio/ + labels: + - "area: VIRTIO" + "Drivers: Video": status: maintained maintainers: @@ -2188,24 +2396,26 @@ Release Notes: - tests/drivers/*/video/ - dts/bindings/video/ - samples/drivers/video/ + - tests/drivers/video/ labels: - "area: Video" tests: - drivers.video -"Drivers: VIRTIO": - status: maintained - maintainers: - - fkokosinski - - tgorochowik - collaborators: - - kgugala +"Drivers: Virtualization": + status: odd fixes files: - - drivers/virtio/ - - dts/bindings/virtio/ - - include/zephyr/virtio/ + - drivers/virtualization/ + - tests/drivers/virtualization/ + - dts/bindings/virtualization/ + - include/zephyr/drivers/virtualization/ + - doc/services/virtualization/ + - include/zephyr/drivers/virtualization/ivshmem.h + - samples/drivers/virtualization/ labels: - - "area: VIRTIO" + - "area: Virtualization" + tests: + - drivers.virtualization "Drivers: W1": status: maintained @@ -2257,18 +2467,7 @@ Release Notes: files: - drivers/wifi/ - dts/bindings/wifi/ - labels: - - "area: Wi-Fi" - -"Drivers: Wi-Fi es-WiFi": - status: odd fixes - collaborators: - - loicpoulain - files: - - drivers/wifi/eswifi/ - description: >- - Inventek es-WiFi - + - tests/drivers/build_all/wifi/ labels: - "area: Wi-Fi" @@ -2295,46 +2494,45 @@ Release Notes: labels: - "area: Wi-Fi" -"Drivers: Memory Management": - status: maintained - maintainers: - - dcpleung +"Drivers: Wi-Fi es-WiFi": + status: odd fixes collaborators: - - ceolin - - edersondisouza - - jxstelter + - loicpoulain files: - - include/zephyr/drivers/mm/ - - drivers/mm/ - - tests/boards/intel_adsp/mm/ - - dts/bindings/mm/ + - drivers/wifi/eswifi/ + description: >- + Inventek es-WiFi labels: - - "area: Memory Management" + - "area: Wi-Fi" -"Drivers: MIPI DBI": +"Drivers: Wurth Elektronik Sensors": status: maintained maintainers: - - danieldegrasse + - mah-eiSmart + - wm-eisos files: - - drivers/mipi_dbi/ - - dts/bindings/mipi-dbi/ - - include/zephyr/dt-bindings/mipi_dbi/ + - drivers/sensor/wsen/ labels: - - "area: Display Controller" + - "area: Sensors" + tests: + - drivers.sensors + description: >- + Drivers of Wurth Elektronik sensors. -"Drivers: Virtualization": - status: odd fixes +"Drivers: bbram": + status: maintained + maintainers: + - yperess files: - - drivers/virtualization/ - - tests/drivers/virtualization/ - - dts/bindings/virtualization/ - - include/zephyr/drivers/virtualization/ - - doc/services/virtualization/ - - include/zephyr/drivers/virtualization/ivshmem.h + - tests/drivers/bbram/ + - tests/drivers/build_all/bbram/ + - drivers/bbram/ + - include/zephyr/drivers/bbram.h + - doc/hardware/peripherals/bbram.rst labels: - - "area: Virtualization" + - "area: Battery Backed RAM (bbram)" tests: - - drivers.virtualization + - drivers.bbram EC Host Commands: status: maintained @@ -2349,22 +2547,73 @@ EC Host Commands: tests: - mgmt.ec_host_cmd -Xen Platform: +Emulation: status: maintained maintainers: - - firscity + - yperess collaborators: - - lorc - - luca-fancellu + - aaronemassey + - jeremybettis + - alevkoy + - asemjonovs + - tristan-google files: - - include/zephyr/xen/ - - drivers/xen/ - - arch/arm64/core/xen/ - - soc/xen/ - - boards/xen/ - - dts/bindings/xen/ + - subsys/emul/ + - include/zephyr/drivers/emul_* + - include/zephyr/drivers/emul.h + - include/zephyr/drivers/espi_emul.h + - include/zephyr/drivers/i2c_emul.h + - include/zephyr/drivers/spi_emul.h + - tests/subsys/emul/ + - doc/hardware/emulator/ labels: - - "area: Xen Platform" + - "area: HW Emulation" + tests: + - emul + +Enclustra Platforms: + status: maintained + maintainers: + - fkokosinski + collaborators: + - tgorochowik + files: + - boards/enclustra/ + labels: + - "platform: Enclustra" + +Espressif Platforms: + status: maintained + maintainers: + - sylvioalves + collaborators: + - LucasTambor + - marekmatej + - uLipe + - raffarost + - wmrsouza + files: + - drivers/*/*esp32*.c + - boards/espressif/ + - soc/espressif/ + - dts/*/espressif/ + - dts/bindings/*/*esp32* + - samples/boards/espressif/ + - tests/boards/espressif/ + - drivers/*/*esp32*/ + labels: + - "platform: ESP32" + +Ezurio platforms: + status: maintained + maintainers: + - rerickson1 + collaborators: + - greg-leach + files: + - boards/ezurio/ + labels: + - "platform: Ezurio" Filesystems: status: maintained @@ -2403,19 +2652,63 @@ Formatted Output: - utilities.prf - libraries.cbprintf -Google Platforms: +GD32 Platforms: status: maintained maintainers: - - fabiobaltieri - - keith-zephyr + - nandojve collaborators: - - duda-patryk + - soburi + - cameled files: - - boards/google/ - - samples/boards/google/ - -Hash Utilities: - status: maintained + - boards/gd/ + - drivers/*/*gd32* + - dts/*/gd/ + - dts/bindings/*/*gd32* + - scripts/west_commands/*/*gd32* + - soc/gd/gd32/ + labels: + - "platform: GD32" + description: >- + GigaDevice GD32 SOCs, dts files and related drivers. Starter and eval + boards. + +Gaisler Platforms: + status: odd fixes + collaborators: + - tbr-tt + files: + - dts/sparc/gaisler/ + - soc/gaisler/ + - boards/gaisler/ + labels: + - "area: SPARC" + +Gardena Platforms: + status: maintained + maintainers: + - rettichschnidi + collaborators: + - M1cha + files: + - boards/gardena/ + labels: + - "platform: Gardena" + description: >- + Gardena board(s). + +Google Platforms: + status: maintained + maintainers: + - fabiobaltieri + - keith-zephyr + collaborators: + - duda-patryk + files: + - boards/google/ + - samples/boards/google/ + +Hash Utilities: + status: maintained maintainers: - cfriedt files: @@ -2431,6 +2724,88 @@ Hash Utilities: - libraries.hash_function - libraries.hash_map +Heap Management: + status: maintained + maintainers: + - npitre + - andyross + files: + - tests/lib/shared_multi_heap/ + - lib/heap/ + - tests/lib/heap/ + - tests/lib/heap_align/ + - tests/lib/multi_heap/ + - include/zephyr/multi_heap/ + +IPC: + status: maintained + maintainers: + - doki-nordic + collaborators: + - carlocaione + - arnopo + files: + - include/zephyr/ipc/ + - samples/subsys/ipc/ + - subsys/ipc/ + - tests/subsys/ipc/ + - doc/services/ipc/ + - dts/bindings/ipc/ + - include/zephyr/dt-bindings/ipc_service/ + description: >- + Inter-Processor Communication + labels: + - "area: IPC" + tests: + - ipc + +ITE Platforms: + status: maintained + maintainers: + - Dino-Li + - GTLin08 + - RuibinChang + - Chenhongren + collaborators: + - jackrosenthal + - keith-zephyr + - fabiobaltieri + files: + - boards/ite/ + - drivers/sensor/ite/ + - drivers/usb/udc/*it82xx2*.c + - drivers/usb/device/*it82xx2*.c + - drivers/*/*it51xxx*.c + - drivers/*/*it8xxx2*.c + - drivers/*/*_ite_* + - dts/bindings/*/ite* + - dts/riscv/ite/ + - soc/ite/ + labels: + - "platform: ITE" + +Infineon Platforms: + status: maintained + maintainers: + - sreeramIfx + collaborators: + - mcatee-infineon + - talih0 + files: + - boards/cypress/ + - boards/infineon/ + - drivers/*/*ifx_cat1* + - drivers/*/*xmc* + - drivers/sensor/infineon/ + - dts/arm/infineon/ + - dts/bindings/*/*infineon* + - soc/infineon/ + labels: + - "platform: Infineon" + description: >- + Infineon SOCs, dts files and related drivers. Infineon Proto, Pioneer, Eval and Relax + boards. + Input: status: maintained maintainers: @@ -2454,27 +2829,109 @@ Input: - drivers.input - input -IPC: +Intel Platforms (Agilex): status: maintained maintainers: - - doki-nordic + - gdengi collaborators: - - carlocaione - - arnopo + - nbalabak + - teikheng files: - - include/zephyr/ipc/ - - samples/subsys/ipc/ - - subsys/ipc/ - - tests/subsys/ipc/ - - doc/services/ipc/ - - dts/bindings/ipc/ - - include/zephyr/dt-bindings/ipc_service/ - description: >- - Inter-Processor Communication + - boards/intel/socfpga/ + - soc/intel/intel_socfpga/ + - dts/arm64/intel/ + - dts/bindings/*/intel,agilex* + - dts/arm/intel_socfpga_std/ labels: - - "area: IPC" + - "platform: Intel SoC FPGA Agilex" + +Intel Platforms (ISH): + status: maintained + maintainers: + - kwd-doodling + collaborators: + - teburd + - likongintel + - nashif + files: + - boards/intel/ish/ + - soc/intel/intel_ish/ + - dts/x86/intel/intel_ish* + - dts/bindings/*/intel,sedi* + - drivers/*/*sedi* + labels: + - "platform: Intel ISH" + +Intel Platforms (X86): + status: maintained + maintainers: + - edersondisouza + collaborators: + - najumon1980 + - teburd + - dcpleung + - ceolin + files: + - boards/intel/adl/ + - boards/intel/ehl/ + - boards/intel/rpl/ + - dts/x86/intel/ + - soc/intel/atom/ + - soc/intel/lakemont/ + - soc/intel/*_lake/ + - drivers/timer/Kconfig.x86 + - drivers/timer/hpet.c + - drivers/timer/apic* + labels: + - "platform: X86" + - "platform: Intel" + +Intel Platforms (Xtensa): + status: maintained + maintainers: + - dcpleung + collaborators: + - andyross + - lyakh + - lgirdwood + - kv2019i + - ceolin + - tmleman + - softwarecki + - jxstelter + - marcinszkudlinski + - nashif + files: + - boards/intel/adsp/ + - soc/intel/intel_adsp/ + - dts/xtensa/intel/ + - tests/boards/intel_adsp/ + - samples/boards/intel/adsp/ + - dts/bindings/*/intel,adsp* + - scripts/west_commands/runners/intel_adsp.py + labels: + - "platform: Intel ADSP" + +"Interrupt Handling": + status: odd fixes + collaborators: + - ycsin + - dcpleung + - nashif + files: + - drivers/interrupt_controller/ + - dts/bindings/interrupt-controller/ + - include/zephyr/drivers/interrupt_controller/ + - include/zephyr/dt-bindings/interrupt-controller/ + - include/zephyr/irq* + - include/zephyr/sw_isr_table.h + - include/zephyr/shared_irq.h + - tests/drivers/interrupt_controller/ + - tests/drivers/build_all/interrupt_controller/ + labels: + - "area: Interrupt Controller" tests: - - ipc + - drivers.interrupt_controller JSON Web Token: status: maintained @@ -2510,8 +2967,7 @@ Kconfig: labels: - "area: Kconfig" description: >- - See https://docs.zephyrproject.org/latest/build/kconfig/index.html and - https://docs.zephyrproject.org/latest/hardware/porting/board_porting.html#default-board-configuration + See https://docs.zephyrproject.org/latest/build/kconfig/index.html tests: - kconfig @@ -2545,113 +3001,25 @@ Kernel: tests: - kernel -Utilities: +"Linkable Loadable Extensions": status: maintained maintainers: - - andyross - - nashif + - teburd collaborators: - - dcpleung - - peter-mitsis + - lyakh + - pillo79 files: - - lib/crc/ - - lib/utils/ - - tests/unit/timeutil/ - - tests/unit/time_units/ - - tests/unit/rbtree/ - - tests/unit/math_extras/ - - tests/unit/crc/ - - tests/unit/base64/ - - tests/unit/math_extras/ - - tests/unit/list/ - - tests/unit/intmath/ - - tests/unit/pot/ - - tests/lib/time/ - - tests/lib/onoff/ - - tests/lib/sys_util/ - - tests/lib/sprintf/ - - tests/lib/ringbuffer/ - - tests/lib/notify/ - - tests/lib/linear_range/ - labels: - - "area: Utilities" - tests: - - utilities - - libraries.ring_buffer - - libraries.linear_range - -Base OS: - status: maintained - maintainers: - - andyross - - nashif - collaborators: - - dcpleung - - peter-mitsis - files: - - include/zephyr/sys/ - - lib/os/ - - tests/misc/print_format/ - - tests/lib/p4workq/ - - tests/lib/fdtable/ - files-exclude: - - include/zephyr/sys/cbprintf* - - tests/unit/cbprintf/ - - tests/lib/cbprintf_*/ - - lib/os/cbprintf* - - lib/os/Kconfig.cbprintf - - include/zephyr/sys/mem_manage.h - - include/zephyr/sys/mpsc_pbuf.h - - include/zephyr/sys/mpsc_packet.h - - lib/os/mpsc_pbuf.c + - cmake/llext-edk.cmake + - samples/subsys/llext/ + - include/zephyr/llext/ + - tests/misc/llext-edk/ + - tests/subsys/llext/ + - subsys/llext/ + - doc/services/llext/ labels: - - "area: Base OS" - tests: - - printk - -Heap Management: - status: maintained - maintainers: - - npitre - - andyross - files: - - tests/lib/shared_multi_heap/ - - lib/heap/ - - tests/lib/heap/ - - tests/lib/heap_align/ - - tests/lib/multi_heap/ - - include/zephyr/multi_heap/ - -Memory Management: - status: maintained - maintainers: - - carlocaione - - dcpleung - files: - - subsys/mem_mgmt/ - - lib/mem_blocks/ - - tests/subsys/mem_mgmt/ - - include/zephyr/mem_mgmt/mem_attr_heap.h - - tests/lib/mem_alloc/ - - tests/lib/mem_blocks/ - - doc/services/mem_mgmt/ - - include/zephyr/mem_mgmt/mem_attr.h - - include/zephyr/dt-bindings/memory-attr/ - - tests/lib/mem_blocks_stats/ - - tests/drivers/mm/ + - "area: llext" tests: - - mem_mgmt - -Ezurio platforms: - status: maintained - maintainers: - - rerickson1 - collaborators: - - greg-leach - files: - - boards/ezurio/ - labels: - - "platform: Ezurio" + - llext Linker Scripts: status: maintained @@ -2661,11 +3029,34 @@ Linker Scripts: - include/zephyr/linker/ - tests/misc/iterable_sections/ - tests/application_development/code_relocation/ + - samples/application_development/code_relocation_nocopy/ labels: - "area: Linker Scripts" tests: - linker +LiteX Platforms: + status: maintained + maintainers: + - tgorochowik + - kgugala + - fkokosinski + collaborators: + - mateusz-holenko + - maass-hamburg + files: + - boards/enjoydigital/litex_vexriscv/ + - drivers/*/*litex* + - drivers/*/Kconfig.litex + - dts/bindings/*/litex* + - dts/riscv/riscv32-litex-vexriscv.dtsi + - include/zephyr/drivers/*/*litex* + - samples/boards/enjoydigital/litex/ + - samples/drivers/*litex/ + - soc/litex/ + labels: + - "platform: LiteX" + Little FS: status: odd fixes files: @@ -2679,30 +3070,6 @@ Little FS: tests: - filesystem.littlefs -Logging: - status: maintained - maintainers: - - nordic-krch - collaborators: - - dcpleung - files: - - include/zephyr/logging/ - - include/zephyr/sys/mpsc_pbuf.h - - include/zephyr/sys/mpsc_packet.h - - lib/os/mpsc_pbuf.c - - doc/kernel/data_structures/mpsc_pbuf.rst - - tests/lib/mpsc_pbuf/ - - samples/subsys/logging/ - - subsys/logging/ - - tests/subsys/logging/ - - scripts/logging/ - - doc/services/logging/ - - tests/lib/spsc_pbuf/ - labels: - - "area: Logging" - tests: - - logging - LoRa and LoRaWAN: status: maintained maintainers: @@ -2721,12 +3088,38 @@ LoRa and LoRaWAN: - include/zephyr/dt-bindings/lora/ - dts/bindings/lora/ - doc/connectivity/lora_lorawan/index.rst + - tests/subsys/lorawan/ + - tests/drivers/build_all/lora/ labels: - "area: LoRa" tests: - sample.driver.lora - lorawan +Logging: + status: maintained + maintainers: + - nordic-krch + collaborators: + - dcpleung + files: + - include/zephyr/logging/ + - include/zephyr/sys/mpsc_pbuf.h + - include/zephyr/sys/mpsc_packet.h + - lib/os/mpsc_pbuf.c + - doc/kernel/data_structures/mpsc_pbuf.rst + - tests/lib/mpsc_pbuf/ + - samples/subsys/logging/ + - subsys/logging/ + - tests/subsys/logging/ + - scripts/logging/ + - doc/services/logging/ + - tests/lib/spsc_pbuf/ + labels: + - "area: Logging" + tests: + - logging + MAINTAINERS file: status: maintained maintainers: @@ -2759,6 +3152,88 @@ MCU Manager: tests: - mgmt.mcumgr +MIPS arch: + status: odd fixes + files: + - arch/mips/ + - include/zephyr/arch/mips/ + - boards/qemu/malta/ + labels: + - "area: MIPS" + tests: + - arch.mips + +Memory Management: + status: maintained + maintainers: + - carlocaione + - dcpleung + files: + - subsys/mem_mgmt/ + - lib/mem_blocks/ + - tests/subsys/mem_mgmt/ + - include/zephyr/mem_mgmt/mem_attr_heap.h + - tests/lib/mem_alloc/ + - tests/lib/mem_blocks/ + - doc/services/mem_mgmt/ + - include/zephyr/mem_mgmt/mem_attr.h + - include/zephyr/dt-bindings/memory-attr/ + - tests/lib/mem_blocks_stats/ + - tests/drivers/mm/ + tests: + - mem_mgmt + +Microchip MEC Platforms: + status: maintained + maintainers: + - jvasanth1 + collaborators: + - VenkatKotakonda + - albertofloyd + files: + - boards/microchip/mec*/ + - dts/arm/microchip/ + - soc/microchip/mec/ + - drivers/*/*mchp*.c + - tests/boards/mec15xxevb_assy6853/ + - tests/boards/mec172xevb_assy6906/ + - dts/bindings/*/microchip,mec* + - dts/bindings/*/microchip,xec* + - samples/boards/microchip/ + labels: + - "platform: Microchip MEC" + +Microchip RISC-V Platforms: + status: maintained + maintainers: + - fkokosinski + - kgugala + - tgorochowik + files: + - boards/microchip/m2gl025_miv/ + - boards/microchip/mpfs_icicle/ + - dts/riscv/microchip/ + - soc/microchip/miv/ + labels: + - "platform: Microchip RISC-V" + +Microchip SAM Platforms: + status: maintained + maintainers: + - nandojve + collaborators: + - pdgendt + - mnkp + - stephanosio + files: + - boards/atmel/ + - dts/arm/atmel/ + - soc/atmel/ + - drivers/*/*sam*.c + - dts/bindings/*/atmel,* + labels: + - "platform: Microchip SAM" + Modbus: status: maintained maintainers: @@ -2807,50 +3282,198 @@ NEORV32 platform: tests: - boards.neorv32 -OSDP: +NXP Platform Drivers: status: maintained maintainers: - - sidcha + - dleach02 + - mmahadevan108 collaborators: - - adakus - - r2r0 - files: - - subsys/mgmt/osdp/ - - include/zephyr/mgmt/osdp.h - - samples/subsys/mgmt/osdp/ + - decsny + - manuargue + - dbaluta + - Raymond0225 + files-regex: + - ^drivers/.*nxp.* + - ^drivers/.*mcux.* + files: + - drivers/*/*imx* + - drivers/*/*lpc*.c + - drivers/*/*mcux*.c + - drivers/*/*.mcux + - drivers/*/*.nxp + - drivers/*/*nxp* + - drivers/*/*/*kinetis* + - drivers/misc/*/nxp* + - include/zephyr/dt-bindings/*/*nxp* + - include/zephyr/dt-bindings/*/*mcux* + - include/zephyr/dt-bindings/inputmux/ + - include/zephyr/dt-bindings/rdc/ + - include/zephyr/drivers/*/*nxp* + - include/zephyr/drivers/*/*nxp*/ + - include/zephyr/drivers/*/*mcux* + - arch/arm/core/mpu/nxp_mpu.c + - dts/bindings/*/nxp* + files-exclude: + - drivers/wifi/ + - drivers/bluetooth/ + - drivers/usb/ + files-regex-exclude: + - .*s32.* labels: - - "area: OSDP" - tests: - - sample.mgmt.osdp + - "platform: NXP Drivers" + description: NXP Drivers -hawkBit: +NXP Platform MCUX USB: status: maintained maintainers: - - maass-hamburg + - mmahadevan108 + - MarkWangChinese files: - - subsys/mgmt/hawkbit/ - - include/zephyr/mgmt/hawkbit/ - - include/zephyr/mgmt/hawkbit.h - - samples/subsys/mgmt/hawkbit/ + - drivers/usb/*/*mcux* + - boards/nxp/usb_kw24d512/ labels: - - "area: hawkBit" - tests: - - sample.net.hawkbit + - "platform: NXP Drivers" + description: NXP MCUX USB shim drivers -"mgmt: updatehub": +NXP Platform Wireless: status: maintained maintainers: - - nandojve + - dleach02 + collaborators: + - MaochenWang1 + - axelnxp + - George-Stefan files: - - subsys/mgmt/updatehub/ - - include/zephyr/mgmt/updatehub.h - - samples/subsys/mgmt/updatehub/ + - boards/nxp/*mcxw*/ + - boards/nxp/*rw*/ + - drivers/*/*mcxw*.c + - drivers/bluetooth/hci/*nxp* + - drivers/hdlc_rcp_if/*nxp* + - drivers/ieee802154/ieee802154_kw41z.c + - drivers/wifi/nxp/ + - samples/bluetooth/**/*rw* + - samples/net/**/*mcxw* + - samples/net/**/*nxp* + - samples/net/**/*rw* + - soc/nxp/mcx/mcxw/ + - soc/nxp/rw/ labels: - - "area: updatehub" - description: >- - UpdateHub embedded Firmware Over-The-Air (FOTA) upgrade agent - tests: - - sample.net.updatehub + - "platform: NXP Drivers" + +NXP Platforms (MCU): + status: maintained + maintainers: + - dleach02 + - mmahadevan108 + collaborators: + - DerekSnell + - EmilioCBen + - decsny + - butok + files: + - boards/nxp/mimxrt*/ + - boards/nxp/frdm*/ + - boards/nxp/lpcxpress*/ + - boards/nxp/twr_*/ + - boards/nxp/*rw*/ + - boards/nxp/hexiwear/ + - boards/nxp/common/ + - boards/nxp/* + - soc/nxp/common/ + - soc/nxp/imxrt/ + - soc/nxp/kinetis/ + - soc/nxp/lpc/ + - soc/nxp/rw/ + - soc/nxp/mcx/ + - dts/arm/nxp/ + - samples/boards/nxp*/ + files-exclude: + - dts/arm/nxp/nxp_imx* + files-regex-exclude: + - .*s32.* + labels: + - "platform: NXP" + description: NXP MCU Platforms supported by MCUXpresso suite + +NXP Platforms (MPU): + status: maintained + maintainers: + - JiafeiPan + collaborators: + - dleach02 + - dbaluta + - iuliana-prodan + - yangbolu1991 + - Zhiqiang-Hou + files: + - dts/arm64/nxp/ + - dts/arm/nxp/nxp_imx* + - soc/nxp/imx/ + - soc/nxp/layerscape/ + - boards/nxp/ls1046ardb/ + files-regex: + - boards/nxp/m?imx[^(rt)].*/ + labels: + - "platform: NXP MPU" + description: NXP MPU platforms + +NXP Platforms (Robotics Products): + status: maintained + maintainers: + - bperseghetti + - PetervdPerk-NXP + collaborators: + - manuargue + files: + - boards/nxp/vmu*/ + - boards/nxp/rddrone_fmuk66/ + - boards/nxp/mr_canhubk3/ + - boards/nxp/ucans32k1sic/ + labels: + - "platform: NXP Robotics" + description: NXP Robotics Module Platform Products + +NXP Platforms (S32): + status: maintained + maintainers: + - manuargue + collaborators: + - Dat-NguyenDuy + - congnguyenhuu + files: + - boards/nxp/*s32*/ + - boards/common/*nxp_s32* + - soc/nxp/s32/ + - drivers/*/*nxp_s32* + - drivers/misc/*nxp_s32*/ + - dts/bindings/*/nxp,s32* + - dts/arm/nxp/*s32* + - samples/boards/nxp/s32/ + - include/zephyr/dt-bindings/*/nxp-s32* + - include/zephyr/dt-bindings/*/nxp_s32* + - include/zephyr/drivers/*/*nxp_s32* + files-exclude: + - boards/nxp/ucans32k1sic/ + labels: + - "platform: NXP S32" + description: NXP S32 platforms and S32-specific drivers + +NXP Platforms (Xtensa): + status: maintained + maintainers: + - dbaluta + collaborators: + - iuliana-prodan + files: + - soc/nxp/imx/*/adsp/ + - soc/nxp/imxrt/imxrt5xx/f1/ + - soc/nxp/imxrt/imxrt7xx/hifi1/ + - soc/nxp/imxrt/*/hifi4/ + - soc/nxp/imxrt/imxrt[567]xx/CMakeLists.txt + - soc/nxp/imxrt/imxrt[567]xx/Kconfig* + labels: + - "platform: NXP Xtensa" + description: NXP Xtensa platforms Native_sim and POSIX arch: status: maintained @@ -2899,6 +3522,7 @@ Networking: files-exclude: - doc/connectivity/networking/api/gptp.rst - doc/connectivity/networking/api/ieee802154.rst + - doc/connectivity/networking/api/ocpp.rst - doc/connectivity/networking/api/ptp.rst - doc/connectivity/networking/api/wifi.rst - doc/connectivity/networking/api/http*.rst @@ -2912,6 +3536,7 @@ Networking: - samples/net/sockets/coap_*/ - samples/net/sockets/*http*/ - samples/net/lwm2m_client/ + - samples/net/ocpp/ - samples/net/wifi/ - samples/net/dhcpv4_client/ - subsys/net/l2/ethernet/gptp/ @@ -2921,11 +3546,13 @@ Networking: - subsys/net/lib/config/ieee802154* - subsys/net/lib/http/ - subsys/net/lib/lwm2m/ + - subsys/net/lib/ocpp/ - subsys/net/lib/ptp/ - subsys/net/lib/tls_credentials/ - subsys/net/lib/dhcpv4/ - tests/net/dhcpv4/ - tests/net/ieee802154/ + - tests/net/lib/ocpp/ - tests/net/lib/http*/ - tests/net/wifi/ labels: @@ -2933,21 +3560,6 @@ Networking: tests: - net -"Networking: BSD sockets": - status: maintained - maintainers: - - rlubos - - jukkar - files: - - samples/net/sockets/ - - subsys/net/lib/sockets/ - - tests/net/socket/ - labels: - - "area: Networking" - - "area: Sockets" - tests: - - net.socket - "Networking Buffers": status: maintained maintainers: @@ -2965,23 +3577,20 @@ Networking: tests: - libraries.net_buf -"Networking: Connection Manager": +"Networking: BSD sockets": status: maintained maintainers: - rlubos - collaborators: - - glarsennordic - jukkar files: - - include/zephyr/net/conn_mgr*.h - - subsys/net/conn_mgr/ - - tests/net/conn_mgr_monitor/ - - tests/net/conn_mgr_conn/ - - doc/connectivity/networking/conn_mgr/ + - samples/net/sockets/ + - subsys/net/lib/sockets/ + - tests/net/socket/ labels: - "area: Networking" + - "area: Sockets" tests: - - net.conn_mgr + - net.socket "Networking: CoAP": status: maintained @@ -2998,6 +3607,24 @@ Networking: tests: - net.coap +"Networking: Connection Manager": + status: maintained + maintainers: + - rlubos + collaborators: + - glarsennordic + - jukkar + files: + - include/zephyr/net/conn_mgr*.h + - subsys/net/conn_mgr/ + - tests/net/conn_mgr_monitor/ + - tests/net/conn_mgr_conn/ + - doc/connectivity/networking/conn_mgr/ + labels: + - "area: Networking" + tests: + - net.conn_mgr + "Networking: DHCPv4": status: maintained maintainers: @@ -3016,19 +3643,24 @@ Networking: - net.dhcpv4_client - net.dhcpv4_server -"Networking: gPTP": +"Networking: HTTP": status: maintained maintainers: - jukkar + - rlubos + collaborators: + - matt-rodgers files: - - doc/connectivity/networking/api/gptp.rst - - include/zephyr/net/gptp.h - - samples/net/gptp/ - - subsys/net/l2/ethernet/gptp/ + - doc/connectivity/networking/api/http*.rst + - include/zephyr/net/http/ + - subsys/net/lib/http/ + - samples/net/sockets/*http*/ + - tests/net/lib/http*/ labels: - "area: Networking" + - "area: HTTP" tests: - - sample.net.gptp + - net.http "Networking: LWM2M": status: maintained @@ -3076,20 +3708,6 @@ Networking: tests: - net.mqtt_sn -"Networking: PTP": - status: maintained - maintainers: - - awojasinski - files: - - doc/connectivity/networking/api/ptp.rst - - include/zephyr/net/ptp.h - - subsys/net/lib/ptp/ - - samples/net/ptp/ - labels: - - "area: PTP" - tests: - - sample.net.ptp - "Networking: Native IEEE 802.15.4": status: odd fixes collaborators: @@ -3106,6 +3724,17 @@ Networking: tests: - net.ieee802154 +"Networking: OCPP": + status: maintained + maintainers: + - ssekar15 + files: + - samples/net/ocpp/ + - subsys/net/lib/ocpp/ + - tests/net/lib/ocpp/ + labels: + - "area: OCPP" + "Networking: OpenThread": status: maintained maintainers: @@ -3126,6 +3755,20 @@ Networking: tests: - openthread +"Networking: PTP": + status: maintained + maintainers: + - awojasinski + files: + - doc/connectivity/networking/api/ptp.rst + - include/zephyr/net/ptp.h + - subsys/net/lib/ptp/ + - samples/net/ptp/ + labels: + - "area: PTP" + tests: + - sample.net.ptp + "Networking: Wi-Fi": status: maintained maintainers: @@ -3146,50 +3789,111 @@ Networking: tests: - net.wifi -"Networking: HTTP": +"Networking: gPTP": status: maintained maintainers: - jukkar - - rlubos - collaborators: - - mrodgers-witekio files: - - doc/connectivity/networking/api/http*.rst - - include/zephyr/net/http/ - - subsys/net/lib/http/ - - samples/net/sockets/*http*/ - - tests/net/lib/http*/ + - doc/connectivity/networking/api/gptp.rst + - include/zephyr/net/gptp.h + - samples/net/gptp/ + - subsys/net/l2/ethernet/gptp/ labels: - "area: Networking" - - "area: HTTP" tests: - - net.http + - sample.net.gptp -nRF BSIM: +Nuvoton NPCM Platforms: status: maintained maintainers: - - aescolar + - maxdog988 + - warp5tw + - jc849 files: - - boards/native/nrf_bsim/ - - tests/boards/nrf52_bsim/ - - tests/bsim/ - - doc/develop/test/bsim.rst - - .github/workflows/bsim-tests* - files-regex-exclude: - - tests\/bsim\/.*\/.*\.([ch]|conf) - - tests\/bsim\/.*\/(CMakeLists|Kconfig).* + - soc/nuvoton/npcm/ + - boards/nuvoton/npcm*/ + - dts/arm/nuvoton/ + - drivers/*/*_npcm* + - include/zephyr/dt-bindings/*/npcm_* labels: - - "platform: nRF BSIM" + - "platform: Nuvoton NPCM" + +Nuvoton NPCX Platforms: + status: maintained + maintainers: + - MulinChao + - ChiHuaL + collaborators: + - TomChang19 + - alvsun + - sjg20 + - keith-zephyr + - jackrosenthal + - fabiobaltieri + files: + - soc/nuvoton/npcx/ + - boards/nuvoton/npcx*/ + - dts/arm/nuvoton/ + - dts/bindings/*/*npcx* + - drivers/*/*_npcx*.c + labels: + - "platform: Nuvoton NPCX" + +Nuvoton Numicro Numaker Platforms: + status: maintained + maintainers: + - cyliangtw + collaborators: + - ssekar15 + files: + - soc/nuvoton/numaker/ + - soc/nuvoton/numicro/ + - boards/nuvoton/numaker*/ + - dts/arm/nuvoton/ + - dts/bindings/*/*numicro* + - dts/bindings/*/*numaker* + - drivers/*/*_numicro* + - drivers/*/*_numaker* + labels: + - "platform: Nuvoton Numicro Numaker" + +OSDP: + status: maintained + maintainers: + - sidcha + collaborators: + - adakus + - r2r0 + files: + - subsys/mgmt/osdp/ + - include/zephyr/mgmt/osdp.h + - samples/subsys/mgmt/osdp/ + labels: + - "area: OSDP" tests: - - boards.nrf52_bsim + - sample.mgmt.osdp + +Octavo Systems Platforms: + status: maintained + maintainers: + - fkokosinski + - tgorochowik + collaborators: + - kgugala + files: + - boards/oct/ + - soc/oct/ + labels: + - "platform: Octavo Systems" Open AMP: status: maintained maintainers: - carlocaione + - iuliana-prodan collaborators: - uLipe - - iuliana-prodan + - arnopo files: - lib/open-amp/ - samples/subsys/ipc/openamp/ @@ -3200,6 +3904,21 @@ Open AMP: tests: - sample.ipc.openamp +OpenTitan Platforms: + status: maintained + maintainers: + - snematbakhsh + files: + - boards/lowrisc/opentitan_earlgrey/ + - drivers/*/*opentitan* + - dts/bindings/*/*opentitan* + - dts/riscv/lowrisc/*opentitan* + - soc/lowrisc/opentitan/ + labels: + - "platform: OpenTitan" + description: >- + OpenTitan boards, SOCs, dts files and related drivers. + PHYTEC Platforms: status: maintained maintainers: @@ -3245,6 +3964,24 @@ POSIX API layer: - libraries.fdtable - portability.posix +Panasonic Platforms: + status: maintained + maintainers: + - pideu-sj + files: + - boards/panasonic/ + labels: + - "platform: Panasonic" + +Peregrine Platforms: + status: maintained + maintainers: + - nandojve + files: + - boards/peregrine/ + labels: + - "platform: Peregrine" + Power management: status: maintained maintainers: @@ -3264,6 +4001,7 @@ Power management: - drivers/power_domain/ - dts/bindings/power/ - include/zephyr/dt-bindings/power/ + - tests/drivers/build_all/power_domain/ labels: - "area: Power Management" tests: @@ -3291,6 +4029,7 @@ RISCV arch: - npitre - ycsin - VynDragon + - masz-nordic files: - arch/riscv/ - boards/enjoydigital/litex_vexriscv/ @@ -3314,774 +4053,80 @@ RISCV arch: tests: - arch.riscv -Retention: +RTIO: status: maintained maintainers: - - nordicjm + - teburd + collaborators: + - yperess + - ubieda files: - - dts/bindings/retention/ - - include/zephyr/retention/ - - subsys/retention/ - - doc/services/retention/ + - samples/subsys/rtio/ + - include/zephyr/rtio/ + - tests/subsys/rtio/ + - subsys/rtio/ + - doc/services/rtio/ labels: - - "area: Retention" + - "area: RTIO" + tests: + - rtio -Samples: +RX arch: status: maintained maintainers: - - kartben - collaborators: - - nashif + - duynguyenxa files: - - samples/ + - arch/rx/ + - include/zephyr/arch/rx/ + - dts/rx/ + - boards/qemu/rx/ + - soc/renesas/rx/ + - tests/arch/rx/ + - include/zephyr/drivers/misc/renesas_rx_external_interrupt/ labels: - - "area: Samples" + - "area: RX" + tests: + - arch.rx -Sensor Subsystem: +Random: status: maintained maintainers: - - lixuzha - - ghu0510 - - yperess + - ceolin collaborators: - - qianruh - files: - - dts/bindings/sensor/zephyr,sensing.yaml - - dts/bindings/sensor/zephyr,sensing*.yaml - - include/zephyr/sensing/ - - doc/services/sensing/ - - subsys/sensing/ - - samples/subsys/sensing/ - - tests/subsys/sensing/ - labels: - - "area: Sensor Subsystem" - tests: - - sample.sensing - - sensing.api - -Stats: - status: odd fixes + - tomi-font files: - - subsys/stats/ - - include/zephyr/stats/stats.h + - subsys/random/ + - include/zephyr/random/ + - tests/subsys/random/ labels: - - "area: Stats" + - "area: Random" -Twister: +Raspberry Pi Pico Platforms: status: maintained maintainers: - - nashif + - soburi collaborators: - - PerMac - - hakehuang - - golowanow - - gchwier - - LukaszMrugala - - KamilxPaszkiet + - yonsch + - threeeights + - ajf58 files: - - scripts/twister - - scripts/schemas/twister/ - - scripts/pylib/twister/ - - scripts/tests/twister/ - - scripts/tests/twister_blackbox/ - - doc/develop/test/twister.rst - - scripts/pylib/pytest-twister-harness/ - - doc/develop/test/pytest.rst - - tests/test_config.yaml - - scripts/utils/twister_to_list.py - - tests/robot/common.robot - labels: - - "area: Twister" - -Settings: - status: odd fixes - files: - - include/zephyr/settings/ - - subsys/settings/ - - tests/subsys/settings/ - - samples/subsys/settings/ - - doc/services/storage/settings/ - labels: - - "area: Settings" - tests: - - settings - -Shell: - status: maintained - maintainers: - - jakub-uC - collaborators: - - carlescufi - files: - - include/zephyr/shell/ - - samples/subsys/shell/ - - subsys/shell/ - - tests/subsys/shell/ - - doc/services/shell/ - labels: - - "area: Shell" - tests: - - shell - -Shields: - status: maintained - maintainers: - - kartben - collaborators: - - avisconti - - jfischer-no - - erwango - files: - - boards/shields/ - - doc/hardware/porting/shields.rst - - samples/shields/ - labels: - - "area: Shields" - tests: - - sample.shields - -SPARC arch: - status: odd fixes - collaborators: - - tbr-tt - files: - - arch/sparc/ - - include/zephyr/arch/sparc/ - - dts/sparc/ - - boards/qemu/leon3/ - labels: - - "area: SPARC" - -Gaisler Platforms: - status: odd fixes - collaborators: - - tbr-tt - files: - - dts/sparc/gaisler/ - - soc/gaisler/ - - boards/gaisler/ - labels: - - "area: SPARC" - -State machine framework: - status: maintained - maintainers: - - sambhurst - collaborators: - - keith-zephyr - - glenn-andrews - files: - - doc/services/smf/ - - include/zephyr/smf.h - - lib/smf/ - - tests/lib/smf/ - - samples/subsys/smf/ - labels: - - "area: State Machine Framework" - tests: - - libraries.smf - -ADI Platforms: - status: maintained - maintainers: - - MaureenHelm - collaborators: - - ozersa - - ttmut - - yasinustunerg - - galak - - microbuilder - files: - - boards/adi/ - - boards/shields/eval*ardz/ - - boards/shields/pmod_acl/ - - drivers/*/*max* - - drivers/*/*max*/ - - drivers/dac/dac_ltc* - - drivers/ethernet/eth_adin* - - drivers/ethernet/phy/phy_adin* - - drivers/mdio/mdio_adin* - - drivers/sensor/adi/ - - drivers/stepper/adi_tmc/ - - dts/arm/adi/ - - dts/bindings/*/adi,* - - dts/bindings/*/lltc,* - - dts/bindings/*/maxim,* - - soc/adi/ - files-regex: - - ^drivers/(adc|dac|gpio|mfd|regulator)/.*adp?\d+ - labels: - - "platform: ADI" - -Bouffalolab Platforms: - status: maintained - maintainers: - - nandojve - - VynDragon - files: - - boards/bflb/ - - drivers/*/*bflb* - - dts/riscv/bflb/ - - dts/bindings/*/bflb,* - - soc/bflb/ - labels: - - "platform: bouffalolab" - -Broadcom Platforms: - status: odd fixes - files: - - dts/*/broadcom/ - - soc/brcm/ - - boards/brcm/ - -GD32 Platforms: - status: maintained - maintainers: - - nandojve - collaborators: - - soburi - - cameled - files: - - boards/gd/ - - drivers/*/*gd32* - - dts/*/gd/ - - dts/bindings/*/*gd32* - - scripts/west_commands/*/*gd32* - - soc/gd/gd32/ - labels: - - "platform: GD32" - description: >- - GigaDevice GD32 SOCs, dts files and related drivers. Starter and eval - boards. - -Synopsys Platforms: - status: maintained - maintainers: - - ruuddw - - evgeniy-paltsev - collaborators: - - abrodkin - files: - - soc/snps/ - - boards/snps/ - - boards/qemu/arc/ - - samples/boards/arc_secure_services/ - - scripts/west_commands/runners/mdb.py - - scripts/west_commands/tests/test_mdb.py - - scripts/west_commands/runners/nsim.py - - cmake/emu/nsim.cmake - - drivers/serial/uart_hostlink.c - - drivers/serial/Kconfig.hostlink - labels: - - "platform: Synopsys" - -Nuvoton NPCX Platforms: - status: maintained - maintainers: - - MulinChao - - ChiHuaL - collaborators: - - TomChang19 - - alvsun - - sjg20 - - keith-zephyr - - jackrosenthal - - fabiobaltieri - files: - - soc/nuvoton/npcx/ - - boards/nuvoton/npcx*/ - - dts/arm/nuvoton/ - - dts/bindings/*/*npcx* - - drivers/*/*_npcx*.c - labels: - - "platform: Nuvoton NPCX" - -Nuvoton Numicro Numaker Platforms: - status: maintained - maintainers: - - cyliangtw - collaborators: - - ssekar15 - files: - - soc/nuvoton/numaker/ - - soc/nuvoton/numicro/ - - boards/nuvoton/numaker*/ - - dts/arm/nuvoton/ - - dts/bindings/*/*numicro* - - dts/bindings/*/*numaker* - - drivers/*/*_numicro* - - drivers/*/*_numaker* - labels: - - "platform: Nuvoton Numicro Numaker" - -Nuvoton NPCM Platforms: - status: maintained - maintainers: - - maxdog988 - - warp5tw - - jc849 - files: - - soc/nuvoton/npcm/ - - boards/nuvoton/npcm*/ - - dts/arm/nuvoton/ - - drivers/*/*_npcm* - - include/zephyr/dt-bindings/*/npcm_* - labels: - - "platform: Nuvoton NPCM" - -Raspberry Pi Pico Platforms: - status: maintained - maintainers: - - soburi - collaborators: - - yonsch - - threeeights - - ajf58 - files: - - boards/raspberrypi/rpi_pico*/ - - boards/adafruit/kb2040/ - - boards/adafruit/macropad_rp2040/ - - boards/adafruit/qt_py_rp2040/ - - boards/pimoroni/pico_plus2/ - - boards/seeed/xiao_rp2040/ - - boards/sparkfun/pro_micro_rp2040/ - - boards/waveshare/rp2040_zero/ - - boards/wiznet/w5500_evb_pico*/ - - dts/arm/raspberrypi/rpi_pico/ - - dts/bindings/*/raspberrypi,pico* - - drivers/*/*rpi_pico - - drivers/*/*rpi_pico*/ - - drivers/*/*rpi_pico*.c - - soc/raspberrypi/ - labels: - - "platform: Raspberry Pi Pico" - -Silabs Platforms: - status: maintained - maintainers: - - jhedberg - - asmellby - collaborators: - - jerome-pouiller - - Martinhoff-maker - files: - - soc/silabs/ - - boards/silabs/ - - dts/arm/silabs/ - - dts/bindings/*/silabs* - - drivers/*/*gecko* - - drivers/*/*silabs* - - drivers/*/*siwx91x* - - drivers/*/*/*silabs* - - drivers/*/*/*siwx91x* - - tests/boards/silabs/ - labels: - - "platform: Silabs" - -Silabs SiM3U Platforms: - status: maintained - maintainers: - - rettichschnidi - collaborators: - - M1cha - - asmellby - - jerome-pouiller - - jhedberg - files: - - boards/silabs/dev_kits/sim3u1xx_dk/ - - drivers/*/*_si32* - - drivers/*/Kconfig.si32 - - dts/arm/silabs/sim3u* - - dts/bindings/*/*silabs,si32* - - include/zephyr/dt-bindings/pinctrl/*si32* - - soc/silabs/silabs_sim3/ - labels: - - "platform: Silabs SiM3U" - description: >- - SiM3U SoCs, dts files, and related drivers. Boards based on SiM3U SoCs. - -Gardena Platforms: - status: maintained - maintainers: - - rettichschnidi - collaborators: - - M1cha - files: - - boards/gardena/ - labels: - - "platform: Gardena" - description: >- - Gardena board(s). - -Intel Platforms (X86): - status: maintained - maintainers: - - edersondisouza - collaborators: - - najumon1980 - - teburd - - dcpleung - - ceolin - files: - - boards/intel/adl/ - - boards/intel/ehl/ - - boards/intel/rpl/ - - dts/x86/intel/ - - soc/intel/atom/ - - soc/intel/lakemont/ - - soc/intel/*_lake/ - - drivers/timer/Kconfig.x86 - - drivers/timer/hpet.c - - drivers/timer/apic* - labels: - - "platform: X86" - -Intel Platforms (Xtensa): - status: maintained - maintainers: - - dcpleung - collaborators: - - andyross - - lyakh - - lgirdwood - - kv2019i - - ceolin - - tmleman - - softwarecki - - jxstelter - - marcinszkudlinski - - nashif - files: - - boards/intel/adsp/ - - soc/intel/intel_adsp/ - - dts/xtensa/intel/ - - tests/boards/intel_adsp/ - - samples/boards/intel/adsp/ - - dts/bindings/*/intel,adsp* - - scripts/west_commands/runners/intel_adsp.py - labels: - - "platform: Intel ADSP" - -Intel Platforms (ISH): - status: maintained - maintainers: - - kwd-doodling - collaborators: - - teburd - - likongintel - - nashif - files: - - boards/intel/ish/ - - soc/intel/intel_ish/ - - dts/x86/intel/intel_ish* - - dts/bindings/*/intel,sedi* - - drivers/*/*sedi* - labels: - - "platform: Intel ISH" - -Intel Platforms (Agilex): - status: maintained - maintainers: - - gdengi - collaborators: - - nbalabak - - teikheng - files: - - boards/intel/socfpga/ - - soc/intel/intel_socfpga/ - - dts/arm64/intel/ - - dts/bindings/*/intel,agilex* - - dts/arm/intel_socfpga_std/ - labels: - - "platform: Intel SoC FPGA Agilex" - -NXP Platform Drivers: - status: maintained - maintainers: - - dleach02 - - mmahadevan108 - collaborators: - - decsny - - manuargue - - dbaluta - - Raymond0225 - files-regex: - - ^drivers/.*nxp.* - - ^drivers/.*mcux.* - files: - - drivers/*/*imx* - - drivers/*/*lpc*.c - - drivers/*/*mcux*.c - - drivers/*/*.mcux - - drivers/*/*.nxp - - drivers/*/*nxp* - - drivers/*/*/*kinetis* - - drivers/misc/*/nxp* - - include/zephyr/dt-bindings/*/*nxp* - - include/zephyr/dt-bindings/*/*mcux* - - include/zephyr/dt-bindings/inputmux/ - - include/zephyr/dt-bindings/rdc/ - - include/zephyr/drivers/*/*nxp* - - include/zephyr/drivers/*/*nxp*/ - - include/zephyr/drivers/*/*mcux* - - arch/arm/core/mpu/nxp_mpu.c - - dts/bindings/*/nxp* - files-exclude: - - drivers/wifi/ - - drivers/bluetooth/ - - drivers/usb/ - files-regex-exclude: - - .*s32.* - labels: - - "platform: NXP Drivers" - description: NXP Drivers - -NXP Platform Wireless: - status: maintained - maintainers: - - dleach02 - collaborators: - - MaochenWang1 - - axelnxp - - George-Stefan - files: - - drivers/wifi/nxp/ - - drivers/bluetooth/hci/*nxp* - - drivers/ieee802154/ieee802154_kw41z.c - - drivers/*/*mcxw*.c - labels: - - "platform: NXP Drivers" - -NXP Platform MCUX USB: - status: maintained - maintainers: - - mmahadevan108 - - MarkWangChinese - files: - - drivers/usb/*/*mcux* - - boards/nxp/usb_kw24d512/ - labels: - - "platform: NXP Drivers" - description: NXP MCUX USB shim drivers - -NXP Platforms (MCU): - status: maintained - maintainers: - - dleach02 - - mmahadevan108 - collaborators: - - DerekSnell - - EmilioCBen - - decsny - - butok - files: - - boards/nxp/mimxrt*/ - - boards/nxp/frdm*/ - - boards/nxp/lpcxpress*/ - - boards/nxp/twr_*/ - - boards/nxp/*rw*/ - - boards/nxp/hexiwear/ - - boards/nxp/common/ - - boards/nxp/* - - soc/nxp/common/ - - soc/nxp/imxrt/ - - soc/nxp/kinetis/ - - soc/nxp/lpc/ - - soc/nxp/rw/ - - soc/nxp/mcx/ - - dts/arm/nxp/ - - samples/boards/nxp*/ - files-exclude: - - dts/arm/nxp/nxp_imx* - files-regex-exclude: - - .*s32.* - labels: - - "platform: NXP" - description: NXP MCU Platforms supported by MCUXpresso suite - -NXP Platforms (S32): - status: maintained - maintainers: - - manuargue - collaborators: - - Dat-NguyenDuy - - congnguyenhuu - files: - - boards/nxp/*s32*/ - - boards/common/*nxp_s32* - - soc/nxp/s32/ - - drivers/*/*nxp_s32* - - drivers/misc/*nxp_s32*/ - - dts/bindings/*/nxp,s32* - - dts/arm/nxp/*s32* - - samples/boards/nxp/s32/ - - include/zephyr/dt-bindings/*/nxp-s32* - - include/zephyr/dt-bindings/*/nxp_s32* - - include/zephyr/drivers/*/*nxp_s32* - files-exclude: - - boards/nxp/ucans32k1sic/ - labels: - - "platform: NXP S32" - description: NXP S32 platforms and S32-specific drivers - -NXP Platforms (MPU): - status: maintained - maintainers: - - JiafeiPan - collaborators: - - dleach02 - - dbaluta - - iuliana-prodan - - yangbolu1991 - - Zhiqiang-Hou - files: - - dts/arm64/nxp/ - - dts/arm/nxp/nxp_imx* - - soc/nxp/imx/ - - soc/nxp/layerscape/ - - boards/nxp/ls1046ardb/ - files-regex: - - boards/nxp/m?imx[^(rt)].*/ - labels: - - "platform: NXP MPU" - description: NXP MPU platforms - -NXP Platforms (Xtensa): - status: maintained - maintainers: - - dbaluta - collaborators: - - iuliana-prodan - files: - - soc/nxp/imx/*/adsp/ - - soc/nxp/imxrt/imxrt5xx/f1/ - labels: - - "platform: NXP Xtensa" - description: NXP Xtensa platforms - -NXP Platforms (Robotics Products): - status: maintained - maintainers: - - bperseghetti - - PetervdPerk-NXP - collaborators: - - manuargue - files: - - boards/nxp/vmu*/ - - boards/nxp/rddrone_fmuk66/ - - boards/nxp/mr_canhubk3/ - - boards/nxp/ucans32k1sic/ - labels: - - "platform: NXP Robotics" - description: NXP Robotics Module Platform Products - -Microchip MEC Platforms: - status: maintained - maintainers: - - jvasanth1 - collaborators: - - VenkatKotakonda - - albertofloyd - files: - - boards/microchip/mec*/ - - dts/arm/microchip/ - - soc/microchip/mec/ - - drivers/*/*mchp*.c - - tests/boards/mec15xxevb_assy6853/ - - tests/boards/mec172xevb_assy6906/ - - dts/bindings/*/microchip,mec* - - dts/bindings/*/microchip,xec* - labels: - - "platform: Microchip MEC" - -Microchip RISC-V Platforms: - status: maintained - maintainers: - - fkokosinski - - kgugala - - tgorochowik - files: - - boards/microchip/m2gl025_miv/ - - boards/microchip/mpfs_icicle/ - - dts/riscv/microchip/ - - soc/microchip/miv/ - labels: - - "platform: Microchip RISC-V" - -Microchip SAM Platforms: - status: maintained - maintainers: - - nandojve - collaborators: - - attie-argentum - - pdgendt - - mnkp - - stephanosio - files: - - boards/atmel/ - - dts/arm/atmel/ - - soc/atmel/ - - drivers/*/*sam*.c - - dts/bindings/*/atmel,* - labels: - - "platform: Microchip SAM" - -nRF Platforms: - status: maintained - maintainers: - - anangl - - masz-nordic - collaborators: - - jaz1-nordic - - kl-cruz - - magp-nordic - - nika-nordic - files: - - boards/nordic/ - - drivers/*/*nrf*.c - - drivers/*/*nrf*/ - - drivers/*/*nordic*/ - - soc/nordic/ - - samples/boards/nordic/ - - dts/*/nordic/ - - dts/bindings/*/nordic,* - - include/zephyr/drivers/*/*nrf*.h - - include/zephyr/drivers/*/*nrf*/ - - include/zephyr/dt-bindings/*/nordic*.h - - include/zephyr/dt-bindings/*/nrf*.h - - tests/drivers/*/*nrf*/ - - snippets/nordic*/ - - tests/boards/nrf/ - labels: - - "platform: nRF" - -Octavo Systems Platforms: - status: maintained - maintainers: - - fkokosinski - - tgorochowik - collaborators: - - kgugala - files: - - boards/oct/ - - soc/oct/ - labels: - - "platform: Octavo Systems" - -OpenTitan Platforms: - status: maintained - maintainers: - - snematbakhsh - files: - - boards/lowrisc/opentitan_earlgrey/ - - drivers/*/*opentitan* - - dts/bindings/*/*opentitan* - - dts/riscv/lowrisc/*opentitan* - - soc/lowrisc/opentitan/ + - boards/raspberrypi/rpi_pico*/ + - boards/adafruit/kb2040/ + - boards/adafruit/macropad_rp2040/ + - boards/adafruit/qt_py_rp2040/ + - boards/pimoroni/pico_plus2/ + - boards/seeed/xiao_rp2040/ + - boards/sparkfun/pro_micro_rp2040/ + - boards/waveshare/rp2040_zero/ + - boards/wiznet/w5500_evb_pico*/ + - dts/arm/raspberrypi/rpi_pico/ + - dts/bindings/*/raspberrypi,pico* + - drivers/*/*rpi_pico + - drivers/*/*rpi_pico*/ + - drivers/*/*rpi_pico*.c + - soc/raspberrypi/ labels: - - "platform: OpenTitan" - description: >- - OpenTitan boards, SOCs, dts files and related drivers. + - "platform: Raspberry Pi Pico" Realtek EC Platforms: status: maintained @@ -4096,26 +4141,41 @@ Realtek EC Platforms: labels: - "platform: Realtek EC" -Renesas SmartBond Platforms: +Release Notes: status: maintained maintainers: - - ioannis-karachalios - - andrzej-kaczmarek - - blauret + - cfriedt + - jhedberg collaborators: - - ydamigos + - kartben files: - - boards/renesas/da14*/ - - drivers/*/*smartbond* - - drivers/pinctrl/renesas/smartbond/ - - dts/arm/renesas/smartbond/ - - dts/bindings/*/renesas,smartbond* - - soc/renesas/smartbond/ + - doc/releases/migration-guide-* + - doc/releases/release-notes-* labels: - - "platform: Renesas SmartBond" + - "Release Notes" + +Renesas R-Car Platforms: + status: maintained + maintainers: + - aaillet + - lorc + collaborators: + - xakep-amatop + files: + - boards/renesas/rcar_*/ + - drivers/*/*rcar* + - drivers/clock_control/*cpg_mssr* + - drivers/pinctrl/renesas/rcar/ + - dts/arm/renesas/rcar/ + - dts/arm64/renesas/ + - dts/bindings/*/*rcar* + - soc/renesas/rcar/ + labels: + - "platform: Renesas R-Car" description: >- - Renesas SmartBond SOCs, dts files, and related drivers. Renesas boards based - on SmartBond SoCs. + Renesas R-Car SOCs, dts files (Cortex-R and Cortex-A sides). + Renesas boards based on R-Car SOCs (Cortex-R and Cortex-A sides). + Renesas R-Car related drivers. Renesas RA Platforms: status: maintained @@ -4135,6 +4195,8 @@ Renesas RA Platforms: - dts/bindings/*/*renesas,ra* - soc/renesas/ra/ - samples/boards/renesas/ + - tests/boards/renesas/ + - include/zephyr/drivers/misc/renesas_ra_external_interrupt/ labels: - "platform: Renesas RA" description: >- @@ -4158,33 +4220,69 @@ Renesas RZ Platforms: - dts/bindings/*/*renesas,rz* - soc/renesas/rz/ labels: - - "platforms: Renesas RZ" - description: >- - Renesas RZ SOCs, dts files, and related drivers. Renesas boards based - on RZ SoCs. + - "platforms: Renesas RZ" + description: >- + Renesas RZ SOCs, dts files, and related drivers. Renesas boards based + on RZ SoCs. + +Renesas SmartBond Platforms: + status: maintained + maintainers: + - ioannis-karachalios + - andrzej-kaczmarek + - blauret + collaborators: + - ydamigos + files: + - boards/renesas/da14*/ + - drivers/*/*smartbond* + - drivers/pinctrl/renesas/smartbond/ + - dts/arm/renesas/smartbond/ + - dts/bindings/*/renesas,smartbond* + - soc/renesas/smartbond/ + labels: + - "platform: Renesas SmartBond" + description: >- + Renesas SmartBond SOCs, dts files, and related drivers. Renesas boards based + on SmartBond SoCs. + +Retention: + status: maintained + maintainers: + - nordicjm + files: + - dts/bindings/retention/ + - include/zephyr/retention/ + - subsys/retention/ + - doc/services/retention/ + labels: + - "area: Retention" + +SPARC arch: + status: odd fixes + collaborators: + - tbr-tt + files: + - arch/sparc/ + - include/zephyr/arch/sparc/ + - dts/sparc/ + - boards/qemu/leon3/ + labels: + - "area: SPARC" -Renesas R-Car Platforms: +SPDX Tooling: status: maintained maintainers: - - aaillet - - lorc + - kartben collaborators: - - xakep-amatop + - pdgendt + - swinslow files: - - boards/renesas/rcar_*/ - - drivers/*/*rcar* - - drivers/clock_control/*cpg_mssr* - - drivers/pinctrl/renesas/rcar/ - - dts/arm/renesas/rcar/ - - dts/arm64/renesas/ - - dts/bindings/*/*rcar* - - soc/renesas/rcar/ + - scripts/west_commands/spdx.py + - scripts/west_commands/zspdx/ + - tests/application_development/software_bill_of_materials/ labels: - - "platform: Renesas R-Car" - description: >- - Renesas R-Car SOCs, dts files (Cortex-R and Cortex-A sides). - Renesas boards based on R-Car SOCs (Cortex-R and Cortex-A sides). - Renesas R-Car related drivers. + - "area: SPDX Tooling" STM32 Platforms: status: maintained @@ -4240,238 +4338,192 @@ STM32 Wireless Platforms: STM32WB SOCs, dts files and related drivers. STM32WB development boards and ST bluetooth shields. -Enclustra Platforms: - status: maintained - maintainers: - - fkokosinski - collaborators: - - tgorochowik - files: - - boards/enclustra/ - labels: - - "platform: Enclustra" - -Espressif Platforms: +Samples: status: maintained maintainers: - - sylvioalves + - kartben collaborators: - - LucasTambor - - marekmatej - - uLipe - - raffarost - - wmrsouza + - nashif files: - - drivers/*/*esp32*.c - - boards/espressif/ - - soc/espressif/ - - dts/*/espressif/ - - dts/bindings/*/*esp32* - - samples/boards/espressif/ - - tests/boards/espressif/ - - drivers/*/*esp32*/ + - samples/sample_definition_and_criteria.rst + - samples/ labels: - - "platform: ESP32" + - "area: Samples" -ITE Platforms: +Secure storage: status: maintained maintainers: - - Dino-Li - - GTLin08 - - RuibinChang - collaborators: - - jackrosenthal - - keith-zephyr - - brockus-zephyr - - sjg20 + - tomi-font files: - - boards/ite/ - - drivers/sensor/ite/ - - drivers/*/*it8xxx2*.c - - drivers/*/*_ite_* - - dts/bindings/*/ite* - - dts/riscv/ite/ - - soc/ite/ + - subsys/secure_storage/ + - include/zephyr/psa/ + - samples/psa/ + - doc/services/storage/secure_storage/index.rst + - tests/subsys/secure_storage/ labels: - - "platform: ITE" + - "area: Secure storage" + tests: + - psa.secure_storage -TI MSPM0 Platforms: - status: maintained - maintainers: - - ssekar15 +Seeed Studio Platforms: + status: odd fixes files: - - soc/ti/mspm0/ - - boards/ti/lp_mspm0g3507/ - - dts/arm/ti/mspm0/ - - dts/bindings/*/*mspm0* - - drivers/*/*_mspm0* - - modules/Kconfig.mspm0 + - boards/seeed/ + - boards/shields/seeed_*/ labels: - - "platform: Texas Instruments MSPM0" + - "platform: Seeed Studio" -TI SimpleLink Platforms: +Sensor Subsystem: status: maintained maintainers: - - vaishnavachath + - lixuzha + - ghu0510 + - yperess collaborators: - - vanti + - qianruh files: - - boards/ti/cc*/ - - boards/ti/msp*/ - - drivers/*/*cc13* - - drivers/*/*cc25* - - drivers/*/*cc26* - - drivers/*/*cc32* - - dts/arm/ti/cc* - - dts/bindings/*/ti,* - - soc/ti/simplelink/ - - dts/bindings/*/ti,* - - modules/Kconfig.simplelink + - dts/bindings/sensor/zephyr,sensing.yaml + - dts/bindings/sensor/zephyr,sensing*.yaml + - include/zephyr/sensing/ + - doc/services/sensing/ + - subsys/sensing/ + - samples/subsys/sensing/ + - tests/subsys/sensing/ labels: - - "platform: TI SimpleLink" + - "area: Sensor Subsystem" + tests: + - sample.sensing + - sensing.api -TI K3 Platforms: +Sensry Platforms: status: maintained maintainers: - - vaishnavachath - collaborators: - - gramsay0 - - dnltz - - glneo - files: - - boards/ti/*am62*/ - - drivers/*/*davinci* - - drivers/*/*omap* - - drivers/*/*ti_k3* - - dts/arm/ti/am6* - - dts/arm/ti/j7* - - dts/bindings/*/ti,k3* - - soc/ti/k3/ - labels: - - "platform: TI K3" - -TI Platforms: - status: odd fixes + - tswaehn files: - - soc/ti/lm3s6965/ - - dts/arm/ti/lm3s6965.dtsi + - boards/sensry/ + files-regex: + - .*sy1xx.* labels: - - "platform: TI" + - "platform: sensry" -Xilinx Platforms: +Settings: status: odd fixes - collaborators: - - henrikbrixandersen - - ibirnbaum - - michalsimek files: - - boards/amd/ - - drivers/*/*xilinx* - - drivers/*/*xlnx* - - drivers/*/*zynq* - - dts/*/xilinx/ - - dts/bindings/*/*xlnx* - - include/zephyr/*/*/*xlnx* - - soc/xlnx/ + - include/zephyr/settings/ + - subsys/settings/ + - tests/subsys/settings/ + - samples/subsys/settings/ + - doc/services/storage/settings/ + - tests/subsys/settings_commit_prio/ labels: - - "platform: Xilinx" + - "area: Settings" + tests: + - settings -Infineon Platforms: +Shell: status: maintained maintainers: - - ifyall + - jakub-uC collaborators: - - npal-cy - - talih0 + - carlescufi files: - - boards/cypress/ - - boards/infineon/ - - drivers/*/*ifx_cat1* - - drivers/*/*xmc* - - drivers/sensor/infineon/ - - dts/arm/infineon/ - - dts/bindings/*/*infineon* - - soc/infineon/ + - include/zephyr/shell/ + - samples/subsys/shell/ + - subsys/shell/ + - tests/subsys/shell/ + - doc/services/shell/ labels: - - "platform: Infineon" - description: >- - Infineon SOCs, dts files and related drivers. Infineon Proto, Pioneer, Eval and Relax - boards. + - "area: Shell" + tests: + - shell -LiteX Platforms: +Shields: status: maintained maintainers: - - tgorochowik - - kgugala - - fkokosinski + - kartben collaborators: - - mateusz-holenko - - maass-hamburg + - avisconti + - jfischer-no + - erwango files: - - boards/enjoydigital/litex_vexriscv/ - - drivers/*/*litex* - - drivers/*/Kconfig.litex - - dts/bindings/*/litex* - - dts/riscv/riscv32-litex-vexriscv.dtsi - - include/zephyr/drivers/*/*litex* - - samples/boards/enjoydigital/litex/ - - samples/drivers/*litex/ - - soc/litex/ + - boards/shields/ + - doc/hardware/porting/shields.rst + - samples/shields/ labels: - - "platform: LiteX" + - "area: Shields" + tests: + - sample.shields -Panasonic Platforms: +Silabs Platforms: status: maintained maintainers: - - pideu-sj + - jhedberg + - asmellby + collaborators: + - jerome-pouiller + - Martinhoff-maker files: - - boards/panasonic/ + - soc/silabs/ + - boards/silabs/ + - dts/arm/silabs/ + - dts/bindings/*/silabs* + - drivers/*/*gecko* + - drivers/*/*silabs* + - drivers/*/*siwx91x* + - drivers/*/*/*silabs* + - drivers/*/*/*siwx91x* + - tests/boards/silabs/ + - snippets/*silabs*/ labels: - - "platform: Panasonic" + - "platform: Silabs" -RTIO: +Silabs SiM3U Platforms: status: maintained maintainers: - - teburd + - rettichschnidi collaborators: - - yperess - - ubieda + - M1cha + - asmellby + - jerome-pouiller + - jhedberg files: - - samples/subsys/rtio/ - - include/zephyr/rtio/ - - tests/subsys/rtio/ - - subsys/rtio/ - - doc/services/rtio/ + - boards/silabs/dev_kits/sim3u1xx_dk/ + - drivers/*/*_si32* + - drivers/*/Kconfig.si32 + - dts/arm/silabs/sim3u* + - dts/bindings/*/*silabs,si32* + - include/zephyr/dt-bindings/pinctrl/*si32* + - soc/silabs/silabs_sim3/ labels: - - "area: RTIO" - tests: - - rtio + - "platform: Silabs SiM3U" + description: >- + SiM3U SoCs, dts files, and related drivers. Boards based on SiM3U SoCs. -Secure storage: +State machine framework: status: maintained maintainers: - - tomi-font + - sambhurst + collaborators: + - keith-zephyr + - glenn-andrews files: - - subsys/secure_storage/ - - include/zephyr/psa/ - - samples/psa/ - - doc/services/storage/secure_storage/index.rst - - tests/subsys/secure_storage/ + - doc/services/smf/ + - include/zephyr/smf.h + - lib/smf/ + - tests/lib/smf/ + - samples/subsys/smf/ labels: - - "area: Secure storage" + - "area: State Machine Framework" tests: - - psa.secure_storage + - libraries.smf -Sensry Platforms: - status: maintained - maintainers: - - tswaehn +Stats: + status: odd fixes files: - - boards/sensry/ - files-regex: - - .*sy1xx.* + - subsys/stats/ + - include/zephyr/stats/stats.h labels: - - "platform: sensry" + - "area: Stats" Storage: status: odd fixes @@ -4496,6 +4548,27 @@ Storage ZMS: - tests/subsys/fs/zms/ - doc/services/storage/zms/zms.rst +Synopsys Platforms: + status: maintained + maintainers: + - ruuddw + - evgeniy-paltsev + collaborators: + - abrodkin + files: + - soc/snps/ + - boards/snps/ + - boards/qemu/arc/ + - samples/boards/arc_secure_services/ + - scripts/west_commands/runners/mdb.py + - scripts/west_commands/tests/test_mdb.py + - scripts/west_commands/runners/nsim.py + - cmake/emu/nsim.cmake + - drivers/serial/uart_hostlink.c + - drivers/serial/Kconfig.hostlink + labels: + - "platform: Synopsys" + Sysbuild: status: maintained maintainers: @@ -4512,31 +4585,6 @@ Sysbuild: tests: - sample.sysbuild -Task Watchdog: - status: maintained - maintainers: - - martinjaeger - files: - - include/zephyr/task_wdt/ - - samples/subsys/task_wdt/ - - subsys/task_wdt/ - - doc/services/task_wdt/index.rst - labels: - - "area: Task Watchdog" - tests: - - sample.task_wdt - -"Drivers: Syscon": - status: maintained - maintainers: - - carlocaione - files: - - include/zephyr/drivers/syscon.h - - drivers/syscon/ - - tests/drivers/syscon/ - tests: - - drivers.syscon - TDK Sensors: status: maintained maintainers: @@ -4554,35 +4602,118 @@ TDK Sensors: tests: - drivers.sensors -"Drivers: Time Aware GPIO": +TI K3 Platforms: status: maintained maintainers: - - akanisetti + - vaishnavachath + collaborators: + - gramsay0 + - dnltz + - glneo files: - - doc/hardware/peripherals/tgpio.rst - - drivers/misc/timeaware_gpio/ - - include/zephyr/drivers/misc/timeaware_gpio/ - - samples/drivers/misc/timeaware_gpio/ + - boards/ti/*am62*/ + - drivers/*/*davinci* + - drivers/*/*omap* + - drivers/*/*ti_k3* + - dts/arm/ti/am6* + - dts/arm/ti/j7* + - dts/bindings/*/ti,k3* + - soc/ti/k3/ labels: - - "area: Time Aware GPIO" + - "platform: TI K3" + +TI MSPM0 Platforms: + status: maintained + maintainers: + - ssekar15 + files: + - soc/ti/mspm0/ + - boards/ti/lp_mspm0g3507/ + - dts/arm/ti/mspm0/ + - dts/bindings/*/*mspm0* + - drivers/*/*_mspm0* + - modules/Kconfig.mspm0 + labels: + - "platform: Texas Instruments MSPM0" + +TI Platforms: + status: odd fixes + files: + - soc/ti/lm3s6965/ + - dts/arm/ti/lm3s6965.dtsi + labels: + - "platform: TI" + +TI SimpleLink Platforms: + status: maintained + maintainers: + - vaishnavachath + collaborators: + - vanti + files: + - boards/ti/cc*/ + - boards/ti/msp*/ + - drivers/*/*cc13* + - drivers/*/*cc25* + - drivers/*/*cc26* + - drivers/*/*cc32* + - dts/arm/ti/cc* + - dts/bindings/*/ti,* + - soc/ti/simplelink/ + - dts/bindings/*/ti,* + - modules/Kconfig.simplelink + labels: + - "platform: TI SimpleLink" + +Task Watchdog: + status: maintained + maintainers: + - martinjaeger + files: + - include/zephyr/task_wdt/ + - samples/subsys/task_wdt/ + - subsys/task_wdt/ + - doc/services/task_wdt/index.rst + labels: + - "area: Task Watchdog" tests: - - sample.drivers.misc.timeaware_gpio + - sample.task_wdt -"Toolchain Integration": +Test Framework (Ztest): status: maintained maintainers: - - tejlmand + - nashif collaborators: - - stephanosio + - aaronemassey + - jeremybettis + - yperess + - asemjonovs files: - - cmake/bintools/ - - cmake/compiler/ - - cmake/linker/ - - cmake/toolchain/ - - include/zephyr/toolchain/ - - include/zephyr/toolchain.h + - subsys/testsuite/ + - tests/ztest/ + - tests/unit/util/ + - tests/subsys/testsuite/ + - samples/subsys/testsuite/ + - doc/develop/test/ labels: - - "area: Toolchains" + - "area: Testsuite" + tests: + - testing + +Testing with Renode: + # This area is to be converted to a subarea + status: odd fixes + collaborators: + - mateusz-holenko + - fkokosinski + files: + - cmake/emu/renode.cmake + - soc/renode/ + - boards/renode/ + - boards/*/*/support/*.repl + - boards/*/*/support/*.resc + labels: + - "area: Renode" "Toolchain ARC MWDT": status: maintained @@ -4597,18 +4728,6 @@ TDK Sensors: labels: - "area: Toolchains" -"Toolchain arm compiler 6": - status: maintained - maintainers: - - tejlmand - files: - - cmake/*/armclang/ - - cmake/linker/armlink/ - - include/zephyr/toolchain/armclang.h - - lib/libc/armstdc/* - labels: - - "area: Toolchains" - "Toolchain IAR": status: maintained maintainers: @@ -4624,6 +4743,34 @@ TDK Sensors: labels: - "area: Toolchains" +"Toolchain Integration": + status: maintained + maintainers: + - tejlmand + collaborators: + - stephanosio + files: + - cmake/bintools/ + - cmake/compiler/ + - cmake/linker/ + - cmake/toolchain/ + - include/zephyr/toolchain/ + - include/zephyr/toolchain.h + labels: + - "area: Toolchains" + +"Toolchain arm compiler 6": + status: maintained + maintainers: + - tejlmand + files: + - cmake/*/armclang/ + - cmake/linker/armlink/ + - include/zephyr/toolchain/armclang.h + - lib/libc/armstdc/* + labels: + - "area: Toolchains" + "Toolchain oneApi": status: maintained maintainers: @@ -4653,6 +4800,33 @@ Tracing: tests: - tracing +Twister: + status: maintained + maintainers: + - nashif + collaborators: + - PerMac + - hakehuang + - golowanow + - gchwier + - LukaszMrugala + - KamilxPaszkiet + files: + - scripts/twister + - scripts/schemas/twister/ + - scripts/pylib/twister/ + - scripts/tests/twister/ + - scripts/tests/twister_blackbox/ + - doc/develop/test/twister.rst + - scripts/pylib/pytest-twister-harness/ + - doc/develop/test/pytest.rst + - tests/test_config.yaml + - scripts/utils/twister_to_list.py + - tests/robot/common.robot + - scripts/pylib/*-twister-harness/ + labels: + - "area: Twister" + USB: status: maintained maintainers: @@ -4730,6 +4904,40 @@ Userspace: tests: - kernel.memory_protection +Utilities: + status: maintained + maintainers: + - andyross + - nashif + collaborators: + - dcpleung + - peter-mitsis + files: + - lib/crc/ + - lib/utils/ + - tests/unit/timeutil/ + - tests/unit/time_units/ + - tests/unit/rbtree/ + - tests/unit/math_extras/ + - tests/unit/crc/ + - tests/unit/base64/ + - tests/unit/math_extras/ + - tests/unit/list/ + - tests/unit/intmath/ + - tests/unit/pot/ + - tests/lib/onoff/ + - tests/lib/sys_util/ + - tests/lib/sprintf/ + - tests/lib/ringbuffer/ + - tests/lib/notify/ + - tests/lib/linear_range/ + labels: + - "area: Utilities" + tests: + - utilities + - libraries.ring_buffer + - libraries.linear_range + VFS: status: maintained maintainers: @@ -4739,12 +4947,27 @@ VFS: - tests/subsys/fs/fat_fs_api/ description: >- VFS implementation - labels: - "area: File System" tests: - filesystem +WCH Platforms: + status: maintained + maintainers: + - nzmichaelh + - kholia + collaborators: + - VynDragon + files: + - boards/wch/ + - dts/riscv/wch/ + - soc/wch/ + - drivers/*/*wch* + - dts/bindings/*/wch,* + labels: + - "platform: WinChipHead" + West: status: maintained maintainers: @@ -4753,6 +4976,7 @@ West: - mbolivar - carlescufi - swinslow + - marc-hb files: - scripts/west-commands.yml - scripts/west_commands/ @@ -4770,7 +4994,7 @@ West: labels: - "area: ACPI" -"West project: bsim": +"West project: babblesim_base": status: maintained maintainers: - aescolar @@ -4778,7 +5002,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_base": +"West project: babblesim_ext_2G4_channel_NtNcable": status: maintained maintainers: - aescolar @@ -4786,7 +5010,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_2G4_libPhyComv1": +"West project: babblesim_ext_2G4_channel_multiatt": status: maintained maintainers: - aescolar @@ -4794,7 +5018,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_2G4_phy_v1": +"West project: babblesim_ext_2G4_device_WLAN_actmod": status: maintained maintainers: - aescolar @@ -4802,7 +5026,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_2G4_channel_NtNcable": +"West project: babblesim_ext_2G4_device_burst_interferer": status: maintained maintainers: - aescolar @@ -4810,7 +5034,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_2G4_channel_multiatt": +"West project: babblesim_ext_2G4_device_playback": status: maintained maintainers: - aescolar @@ -4818,7 +5042,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_2G4_modem_magic": +"West project: babblesim_ext_2G4_libPhyComv1": status: maintained maintainers: - aescolar @@ -4834,7 +5058,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_2G4_device_burst_interferer": +"West project: babblesim_ext_2G4_modem_magic": status: maintained maintainers: - aescolar @@ -4842,7 +5066,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_2G4_device_WLAN_actmod": +"West project: babblesim_ext_2G4_phy_v1": status: maintained maintainers: - aescolar @@ -4850,7 +5074,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_2G4_device_playback": +"West project: babblesim_ext_libCryptov1": status: maintained maintainers: - aescolar @@ -4858,7 +5082,7 @@ West: labels: - "platform: nRF BSIM" -"West project: babblesim_ext_libCryptov1": +"West project: bsim": status: maintained maintainers: - aescolar @@ -5009,10 +5233,10 @@ West: "West project: hal_cypress": status: maintained maintainers: - - ifyall + - sreeramIfx collaborators: - nashif - - npal-cy + - mcatee-infineon files: - modules/Kconfig.cypress labels: @@ -5025,6 +5249,8 @@ West: collaborators: - LucasTambor - marekmatej + - raffarost + - wmrsouza files: - modules/Kconfig.esp32 labels: @@ -5037,6 +5263,7 @@ West: - wearyzen collaborators: - ithinuel + - ccli8 files: - drivers/misc/ethos_u/ - modules/hal_ethos_u/ @@ -5057,21 +5284,35 @@ West: "West project: hal_infineon": status: maintained maintainers: - - ifyall + - sreeramIfx collaborators: - parthitce - talih0 - - npal-cy + - mcatee-infineon files: - modules/Kconfig.infineon - modules/hal_infineon/ labels: - "platform: Infineon" +"West project: hal_intel": + status: maintained + maintainers: + - kwd-doodling + collaborators: + - teburd + - likongintel + files: + - modules/Kconfig.intel + labels: + - "platform: Intel ISH" + "West project: hal_microchip": status: maintained maintainers: - jvasanth1 + - AzharMCHP + - scottwcpg collaborators: - VenkatKotakonda - albertofloyd @@ -5085,9 +5326,16 @@ West: status: maintained maintainers: - anangl + - nika-nordic + - masz-nordic collaborators: - hubertmis - nordic-krch + - kl-cruz + - magp-nordic + - jaz1-nordic + - mif1-nordic + - adamkondraciuk files: - modules/hal_nordic/ labels: @@ -5096,6 +5344,9 @@ West: "West project: hal_nuvoton": status: maintained maintainers: + - cyliangtw + - ccli8 + collaborators: - ssekar15 files: - modules/Kconfig.nuvoton @@ -5107,11 +5358,16 @@ West: maintainers: - dleach02 - mmahadevan108 - collaborators: - decsny + collaborators: - manuargue - PetervdPerk-NXP - bperseghetti + - JiafeiPan + - ZhaoxiangJin + - EmilioCBen + - MaochenWang1 + - axelnxp files: - modules/hal_nxp/ labels: @@ -5247,6 +5503,7 @@ West: status: maintained maintainers: - mah-eiSmart + - wm-eisos files: - modules/Kconfig.wurthelektronik @@ -5262,25 +5519,32 @@ West: labels: - "area: Xtensa" -"West project: hal_intel": +"West project: hostap": status: maintained maintainers: - - kwd-doodling + - krish2718 + - jukkar collaborators: - - teburd - - likongintel + - MaochenWang1 files: - - modules/Kconfig.intel + - modules/hostap/ labels: - - "platform: Intel" + - "area: Wi-Fi" + tests: + - net.wifi -"West project: zephyr-lang-rust": +"West project: liblc3": status: maintained maintainers: - - d3zd3z - files: [] + - Casper-Bonde-Bose + - MariuszSkamra + collaborators: + - thalley + - asbjornsabo + files: + - modules/liblc3/ labels: - - "area: Rust" + - "area: Audio" "West project: libmctp": status: maintained @@ -5303,19 +5567,6 @@ West: labels: - "area: AMP" -"West project: liblc3": - status: maintained - maintainers: - - Casper-Bonde-Bose - - MariuszSkamra - collaborators: - - thalley - - asbjornsabo - files: - - modules/liblc3/ - labels: - - "area: Audio" - "West project: littlefs": status: odd fixes files: @@ -5344,6 +5595,7 @@ West: - modules/lvgl/ - tests/lib/gui/lvgl/ - include/zephyr/dt-bindings/lvgl/ + - samples/modules/lvgl/ labels: - "area: LVGL" @@ -5426,8 +5678,7 @@ West: maintainers: - aescolar collaborators: - - wopu-ot - - thoh-ot + - rugeGerritsen files: [] labels: - "area: native port" @@ -5494,6 +5745,18 @@ West: - "area: C Library" - "area: picolibc" +"West project: psa-arch-tests": + status: maintained + maintainers: + - d3zd3z + collaborators: + - Vge0rge + - wearyzen + - ithinuel + files: [] + labels: + - "area: TF-M" + "West project: segger": status: odd fixes collaborators: @@ -5517,6 +5780,18 @@ West: labels: - "area: Audio" +"West project: tf-m-tests": + status: maintained + maintainers: + - d3zd3z + collaborators: + - Vge0rge + - wearyzen + - ithinuel + files: [] + labels: + - "area: TF-M" + "West project: tflite-micro": status: maintained maintainers: @@ -5543,45 +5818,6 @@ West: tests: - thrift -"West project: tinycrypt": - status: odd fixes - files: - - modules/Kconfig.tinycrypt - labels: - - "area: Crypto / RNG" - -"West project: trusted-firmware-m": - status: maintained - maintainers: - - d3zd3z - collaborators: - - Vge0rge - - wearyzen - - valeriosetti - - tomi-font - - ithinuel - files: - - modules/trusted-firmware-m/ - - samples/tfm_integration/ - - doc/services/tfm/ - labels: - - "area: TF-M" - tests: - - trusted-firmware-m - - psa.secure_storage - -"West project: tf-m-tests": - status: maintained - maintainers: - - d3zd3z - collaborators: - - Vge0rge - - wearyzen - - ithinuel - files: [] - labels: - - "area: TF-M" - "West project: trusted-firmware-a": status: maintained maintainers: @@ -5596,17 +5832,25 @@ West: labels: - "area: TF-A" -"West project: psa-arch-tests": +"West project: trusted-firmware-m": status: maintained maintainers: - d3zd3z collaborators: - Vge0rge - wearyzen + - valeriosetti + - tomi-font - ithinuel - files: [] + files: + - modules/trusted-firmware-m/ + - samples/tfm_integration/ + - doc/services/tfm/ labels: - "area: TF-M" + tests: + - trusted-firmware-m + - psa.secure_storage "West project: uoscore-uedhoc": status: maintained @@ -5629,25 +5873,68 @@ West: labels: - "area: CBOR" +"West project: zephyr-lang-rust": + status: maintained + maintainers: + - d3zd3z + files: [] + labels: + - "area: Rust" + "West project: zscilib": status: maintained maintainers: - microbuilder files: [] -"West project: hostap": +Wurth Elektronik Platforms: status: maintained maintainers: - - krish2718 - - jukkar + - mah-eiSmart + - wm-eisos + files: + - boards/we/ + - dts/arm/we/ + labels: + - "platform: WE" + description: >- + Wurth Elektronik radio modules, development boards, and SoCs. + +Xen Platform: + status: maintained + maintainers: + - firscity collaborators: - - MaochenWang1 + - lorc + - luca-fancellu files: - - modules/hostap/ + - include/zephyr/xen/ + - drivers/xen/ + - arch/arm64/core/xen/ + - soc/xen/ + - boards/xen/ + - dts/bindings/xen/ + - snippets/xen_dom0/ labels: - - "area: Wi-Fi" - tests: - - net.wifi + - "area: Xen Platform" + +Xilinx Platforms: + status: odd fixes + collaborators: + - henrikbrixandersen + - ibirnbaum + - michalsimek + files: + - boards/amd/ + - drivers/*/*xilinx* + - drivers/*/*xlnx* + - drivers/*/*zynq* + - dts/*/xilinx/ + - dts/bindings/*/*xlnx* + - include/zephyr/*/*/*xlnx* + - soc/xlnx/ + labels: + - "platform: Xilinx" Xtensa arch: status: maintained @@ -5666,146 +5953,119 @@ Xtensa arch: - soc/cdns/dc233c/ - soc/cdns/xtensa_sample_controller/ - tests/arch/xtensa/ + - doc/hardware/arch/xtensa.rst labels: - "area: Xtensa" -x86 arch: - status: maintained - maintainers: - - edersondisouza - collaborators: - - andyross - - dcpleung - - ceolin - - laurenmurphyx64 - - najumon1980 - - nashif - files: - - arch/x86/ - - include/zephyr/arch/x86/ - - tests/arch/x86/ - - drivers/interrupt_controller/*intel* - - drivers/interrupt_controller/*ioapic* - - drivers/interrupt_controller/*loapic* - - doc/hardware/arch/x86.rst - labels: - - "area: X86" - -Continuous Integration: +hawkBit: status: maintained maintainers: - - stephanosio - - nashif - collaborators: - - fabiobaltieri - - kartben + - maass-hamburg files: - - .github/ - - scripts/requirements-actions.* - - scripts/ci/ - - scripts/make_bugs_pickle.py - - .checkpatch.conf - - scripts/gitlint/ - - scripts/set_assignees.py + - subsys/mgmt/hawkbit/ + - include/zephyr/mgmt/hawkbit/ + - include/zephyr/mgmt/hawkbit.h + - samples/subsys/mgmt/hawkbit/ labels: - - "area: Continuous Integration" + - "area: hawkBit" + tests: + - sample.net.hawkbit -Test Framework (Ztest): +"mgmt: updatehub": status: maintained maintainers: - - nashif - collaborators: - - aaronemassey - - jeremybettis - - yperess - - asemjonovs + - nandojve files: - - subsys/testsuite/ - - tests/ztest/ - - tests/unit/util/ - - tests/subsys/testsuite/ - - samples/subsys/testsuite/ - - doc/develop/test/ + - subsys/mgmt/updatehub/ + - include/zephyr/mgmt/updatehub.h + - samples/subsys/mgmt/updatehub/ labels: - - "area: Testsuite" + - "area: updatehub" + description: >- + UpdateHub embedded Firmware Over-The-Air (FOTA) upgrade agent tests: - - testing + - sample.net.updatehub -Emulation: +nRF BSIM: status: maintained maintainers: - - yperess - collaborators: - - aaronemassey - - jeremybettis - - alevkoy - - asemjonovs - - tristan-google + - aescolar files: - - subsys/emul/ - - include/zephyr/drivers/emul_* - - include/zephyr/drivers/emul.h - - include/zephyr/drivers/espi_emul.h - - include/zephyr/drivers/i2c_emul.h - - include/zephyr/drivers/spi_emul.h - - tests/subsys/emul/ - - doc/hardware/emulator/ + - boards/native/nrf_bsim/ + - tests/boards/nrf52_bsim/ + - tests/bsim/ + - doc/develop/test/bsim.rst + - .github/workflows/bsim-tests* + files-regex-exclude: + - tests\/bsim\/.*\/.*\.([ch]|conf) + - tests\/bsim\/.*\/(CMakeLists|Kconfig).* labels: - - "area: HW Emulation" + - "platform: nRF BSIM" tests: - - emul + - boards.nrf52_bsim -Random: +nRF Platforms: status: maintained maintainers: - - ceolin + - anangl + - masz-nordic collaborators: - - tomi-font + - jaz1-nordic + - kl-cruz + - magp-nordic + - nika-nordic files: - - subsys/random/ - - include/zephyr/random/ + - boards/nordic/ + - drivers/*/*nrf*.c + - drivers/*/*nrf*/ + - drivers/*/*nordic*/ + - soc/nordic/ + - samples/boards/nordic/ + - dts/*/nordic/ + - dts/bindings/*/nordic,* + - include/zephyr/drivers/*/*nrf*.h + - include/zephyr/drivers/*/*nrf*/ + - include/zephyr/dt-bindings/*/nordic*.h + - include/zephyr/dt-bindings/*/nrf*.h + - tests/drivers/*/*nrf*/ + - snippets/nordic*/ + - tests/boards/nrf/ + files-exclude: + - drivers/wifi/nrf_wifi/ + - dts/bindings/wifi/ labels: - - "area: Random" + - "platform: nRF" -Peregrine Platforms: +u-blox Platforms: status: maintained maintainers: - - nandojve + - 3rang files: - - boards/peregrine/ + - boards/u-blox/ labels: - - "platform: Peregrine" + - "platform: u-blox" -WCH Platforms: +x86 arch: status: maintained maintainers: - - nzmichaelh - - kholia - collaborators: - - VynDragon - files: - - boards/wch/ - - dts/riscv/wch/ - - soc/wch/ - - drivers/*/*wch* - - dts/bindings/*/wch,* - labels: - - "platform: WinChipHead" - -# This area is to be converted to a subarea -Testing with Renode: - status: odd fixes + - edersondisouza collaborators: - - mateusz-holenko - - fkokosinski + - andyross + - dcpleung + - ceolin + - laurenmurphyx64 + - najumon1980 + - nashif files: - - cmake/emu/renode.cmake - - soc/renode/ - - boards/renode/ - - boards/*/*/support/*.repl - - boards/*/*/support/*.resc + - arch/x86/ + - include/zephyr/arch/x86/ + - tests/arch/x86/ + - drivers/interrupt_controller/*intel* + - drivers/interrupt_controller/*ioapic* + - drivers/interrupt_controller/*loapic* + - doc/hardware/arch/x86.rst labels: - - "area: Renode" + - "area: X86" zbus: status: maintained @@ -5821,39 +6081,4 @@ zbus: - "area: zbus" tests: - message_bus.zbus - -"Linkable Loadable Extensions": - status: maintained - maintainers: - - teburd - collaborators: - - lyakh - - pillo79 - files: - - cmake/llext-edk.cmake - - samples/subsys/llext/ - - include/zephyr/llext/ - - tests/misc/llext-edk/ - - tests/subsys/llext/ - - subsys/llext/ - - doc/services/llext/ - labels: - - "area: llext" - tests: - - llext - -RX arch: - status: maintained - maintainers: - - duynguyenxa - files: - - arch/rx/ - - include/zephyr/arch/rx/ - - dts/rx/ - - boards/qemu/rx/ - - soc/renesas/rx/ - - tests/arch/rx/ - labels: - - "area: RX" - tests: - - arch.rx +# zephyr-keep-sorted-stop diff --git a/SDK_VERSION b/SDK_VERSION index 7cca7711a0d..c3d16c1646b 100644 --- a/SDK_VERSION +++ b/SDK_VERSION @@ -1 +1 @@ -0.17.1 +0.17.2 diff --git a/VERSION b/VERSION index 9749142466b..5b7b1a7378a 100644 --- a/VERSION +++ b/VERSION @@ -1,5 +1,5 @@ VERSION_MAJOR = 4 -VERSION_MINOR = 1 +VERSION_MINOR = 2 PATCHLEVEL = 99 VERSION_TWEAK = 0 EXTRAVERSION = diff --git a/arch/Kconfig b/arch/Kconfig index 646b83c9d65..a179cc63b08 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -107,6 +107,8 @@ config X86 config RISCV bool select ARCH_IS_SET + select ATOMIC_OPERATIONS_C if !RISCV_ISA_EXT_A + select ATOMIC_OPERATIONS_BUILTIN if RISCV_ISA_EXT_A select ARCH_SUPPORTS_COREDUMP select ARCH_SUPPORTS_COREDUMP_PRIV_STACKS select ARCH_SUPPORTS_ROM_START if !SOC_FAMILY_ESPRESSIF_ESP32 @@ -314,6 +316,16 @@ config USERSPACE privileged mode or handling a system call; to ensure these are always caught, enable CONFIG_HW_STACK_PROTECTION. +config NOINIT_SNIPPET_FIRST + bool "Place the no-init linker script snippet first" + help + By default the include/zephyr/linker/common-noinit.ld file inserts the + snippets-noinit.ld file at the end of the section. There are times when + the directives in the snippets-noinit.ld file apply to the other directives + in this file. And in that case the include statement for the snippets-noinit.ld + file needs to come at the start of the section. This configuration option + allows that to happen. + config PRIVILEGED_STACK_SIZE int "Size of privileged stack" default 2048 if EMUL @@ -440,15 +452,21 @@ config ARCH_STACKWALK_MAX_FRAMES menu "Interrupt Configuration" +config TOOLCHAIN_SUPPORTS_ISR_TABLES_LOCAL_DECLARATION + bool + help + Hidden option to signal that toolchain supports local declaration of + interrupt tables. + config ISR_TABLES_LOCAL_DECLARATION_SUPPORTED bool default y # Userspace is currently not supported depends on !USERSPACE # List of currently supported architectures - depends on ARM || ARM64 + depends on ARM || ARM64 || RISCV # List of currently supported toolchains - depends on "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" || "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "gnuarmemb" + depends on "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" || "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "gnuarmemb" || "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "llvm" || TOOLCHAIN_SUPPORTS_ISR_TABLES_LOCAL_DECLARATION config ISR_TABLES_LOCAL_DECLARATION bool "ISR tables created locally and placed by linker" @@ -464,6 +482,7 @@ config ISR_TABLES_LOCAL_DECLARATION config DYNAMIC_INTERRUPTS bool "Installation of IRQs at runtime" + select SRAM_SW_ISR_TABLE help Enable installation of interrupts at runtime, which will move some interrupt-related data structures to RAM instead of ROM, and @@ -590,6 +609,12 @@ config SRAM_VECTOR_TABLE When XiP is enabled, this option will result in the vector table being relocated from Flash to SRAM. +config SRAM_SW_ISR_TABLE + bool "Place the software ISR table in SRAM instead of flash" + help + The option specifies that the software interrupts vector table will be + placed inside SRAM instead of the flash. + config IRQ_OFFLOAD_NESTED bool "irq_offload() supports nested IRQs" depends on IRQ_OFFLOAD @@ -1173,3 +1198,9 @@ config ARCH_HAS_CUSTOM_CURRENT_IMPL help Select when architecture implements arch_current_thread() & arch_current_thread_set(). + +config ARCH_IPI_LAZY_COPROCESSORS_SAVE + bool + help + Select when the architecture has multi-CPU lazy context switching + of coprocessor registers. diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index d44ca272b11..d050acc69d5 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -258,10 +258,10 @@ config ARC_CURRENT_THREAD_USE_NO_TLS select CURRENT_THREAD_USE_NO_TLS default y if (RGF_NUM_BANKS > 1) || ("$(ZEPHYR_TOOLCHAIN_VARIANT)" = "arcmwdt") help - Disable current Thread Local Storage for ARC. For cores with more then one - RGF_NUM_BANKS the parameter is disabled by-default because banks syncronization + Disable current Thread Local Storage for ARC. For cores with more than one + RGF_NUM_BANKS the parameter is disabled by-default because banks synchronization requires significant time, and it slows down performance. - ARCMWDT works with tls pointer in different way then GCC. Optimized access to + ARCMWDT works with TLS pointer in different way then GCC. Optimized access to TLS pointer via the _current symbol does not provide significant advantages in case of MetaWare. @@ -274,7 +274,7 @@ config GEN_IRQ_START_VECTOR config HARVARD bool "Harvard Architecture" help - The ARC CPU can be configured to have two busses; + The ARC CPU can be configured to have two buses; one for instruction fetching and another that serves as a data bus. config CODE_DENSITY @@ -370,6 +370,28 @@ endmenu config DCACHE_LINE_SIZE default 32 +config ARC_DCACHE_REGION_OPERATIONS + bool "DCACHE region operations" + depends on CACHE_MANAGEMENT && DCACHE + default n + help + Perform L1 data cache management operations by regions rather than line by line in a loop, + improves performance of cache management operations. + +config ARC_SLC + bool "System level cache" + depends on CACHE_MANAGEMENT && DCACHE && (CPU_HS4X || CPU_HS3X) + default n + help + This option enables System Level Cache, and adds SLC support to the data cache management operations. + +config ARC_SLC_LINE_SIZE + int "SLC line size" + depends on ARC_SLC + default 128 + help + Size in bytes of a CPU system level cache line. + config ARC_EXCEPTION_STACK_SIZE int "ARC exception handling stack size" default 768 if !64BIT @@ -389,6 +411,11 @@ config ARC_EARLY_SOC_INIT (before C runtime initialization). Setup code is called in form of soc_early_asm_init_percpu assembler macro. +# ARC vector table must be aligned to 1KiB boundary, and will be at the +# start of the ROM region. +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + config MAIN_STACK_SIZE default 4096 if 64BIT diff --git a/arch/arc/core/cache.c b/arch/arc/core/cache.c index 2688d5b03eb..915d38cd329 100644 --- a/arch/arc/core/cache.c +++ b/arch/arc/core/cache.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2016 Synopsys, Inc. All rights reserved. + * Copyright (c) 2025 GSI Technology, All rights reserved. * * SPDX-License-Identifier: Apache-2.0 */ @@ -29,16 +30,34 @@ size_t sys_cache_line_size; #endif -#define DC_CTRL_DC_ENABLE 0x0 /* enable d-cache */ -#define DC_CTRL_DC_DISABLE 0x1 /* disable d-cache */ -#define DC_CTRL_INVALID_ONLY 0x0 /* invalid d-cache only */ -#define DC_CTRL_INVALID_FLUSH 0x40 /* invalid and flush d-cache */ -#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /* locked d-cache can be flushed */ -#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /* locked d-cache cannot be flushed */ -#define DC_CTRL_FLUSH_STATUS 0x100/* flush status */ -#define DC_CTRL_DIRECT_ACCESS 0x0 /* direct access mode */ -#define DC_CTRL_INDIRECT_ACCESS 0x20 /* indirect access mode */ -#define DC_CTRL_OP_SUCCEEDED 0x4 /* d-cache operation succeeded */ +#define DC_CTRL_DC_ENABLE 0x0 /* enable d-cache */ +#define DC_CTRL_DC_DISABLE 0x1 /* disable d-cache */ +#define DC_CTRL_INVALID_ONLY 0x0 /* invalid d-cache only */ +#define DC_CTRL_INVALID_FLUSH 0x40 /* invalid and flush d-cache */ +#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /* locked d-cache can be flushed */ +#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /* locked d-cache cannot be flushed */ +#define DC_CTRL_FLUSH_STATUS 0x100 /* flush status */ +#define DC_CTRL_DIRECT_ACCESS 0x0 /* direct access mode */ +#define DC_CTRL_INDIRECT_ACCESS 0x20 /* indirect access mode */ +#define DC_CTRL_OP_SUCCEEDED 0x4 /* d-cache operation succeeded */ +#define DC_CTRL_INVALIDATE_MODE 0x40 /* d-cache invalidate mode bit */ +#define DC_CTRL_REGION_OP 0xe00 /* d-cache region operation */ + +#define MMU_BUILD_PHYSICAL_ADDR_EXTENSION 0x1000 /* physical address extension enable mask */ + +#define SLC_CTRL_DISABLE 0x1 /* SLC disable */ +#define SLC_CTRL_INVALIDATE_MODE 0x40 /* SLC invalidate mode */ +#define SLC_CTRL_BUSY_STATUS 0x100 /* SLC busy status */ +#define SLC_CTRL_REGION_OP 0xe00 /* SLC region operation */ + +#if defined(CONFIG_ARC_SLC) +/* + * spinlock is used for SLC access because depending on HW configuration, the SLC might be shared + * between the cores, and in this case, only one core is allowed to access the SLC register + * interface at a time. + */ +static struct k_spinlock slc_lock; +#endif static bool dcache_available(void) { @@ -55,9 +74,189 @@ static void dcache_dc_ctrl(uint32_t dcache_en_mask) } } +static bool pae_exists(void) +{ + uint32_t bcr = z_arc_v2_aux_reg_read(_ARC_V2_MMU_BUILD); + + return 1 == FIELD_GET(MMU_BUILD_PHYSICAL_ADDR_EXTENSION, bcr); +} + +#if defined(CONFIG_ARC_SLC) +static void slc_enable(void) +{ + uint32_t val = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + + val &= ~SLC_CTRL_DISABLE; + z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, val); +} + +static void slc_high_addr_init(void) +{ + z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_END1, 0); + z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_START1, 0); +} + +static void slc_flush_region(void *start_addr_ptr, size_t size) +{ + uintptr_t start_addr = (uintptr_t)start_addr_ptr; + uintptr_t end_addr; + uint32_t ctrl; + + K_SPINLOCK(&slc_lock) { + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + + ctrl &= ~SLC_CTRL_REGION_OP; + + z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl); + + /* + * END needs to be setup before START (latter triggers the operation) + * END can't be same as START, so add (l2_line_sz - 1) to sz + */ + end_addr = start_addr + size + CONFIG_ARC_SLC_LINE_SIZE - 1; + + z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_END, end_addr); + /* Align start address to cache line size, see STAR 5103816 */ + z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_START, + start_addr & ~(CONFIG_ARC_SLC_LINE_SIZE - 1)); + + /* Make sure "busy" bit reports correct status, see STAR 9001165532 */ + z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) { + /* Do Nothing */ + } + } +} + +static void slc_invalidate_region(void *start_addr_ptr, size_t size) +{ + uintptr_t start_addr = (uintptr_t)start_addr_ptr; + uintptr_t end_addr; + uint32_t ctrl; + + K_SPINLOCK(&slc_lock) { + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + + ctrl &= ~SLC_CTRL_INVALIDATE_MODE; + + ctrl &= ~SLC_CTRL_REGION_OP; + ctrl |= FIELD_PREP(SLC_CTRL_REGION_OP, 0x1); + + z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl); + + /* + * END needs to be setup before START (latter triggers the operation) + * END can't be same as START, so add (l2_line_sz - 1) to sz + */ + end_addr = start_addr + size + CONFIG_ARC_SLC_LINE_SIZE - 1; + + z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_END, end_addr); + /* Align start address to cache line size, see STAR 5103816 */ + z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_START, + start_addr & ~(CONFIG_ARC_SLC_LINE_SIZE - 1)); + + /* Make sure "busy" bit reports correct status, see STAR 9001165532 */ + z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) { + /* Do Nothing */ + } + } +} + +static void slc_flush_and_invalidate_region(void *start_addr_ptr, size_t size) +{ + uintptr_t start_addr = (uintptr_t)start_addr_ptr; + uintptr_t end_addr; + uint32_t ctrl; + + K_SPINLOCK(&slc_lock) { + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + + ctrl |= SLC_CTRL_INVALIDATE_MODE; + + ctrl &= ~SLC_CTRL_REGION_OP; + ctrl |= FIELD_PREP(SLC_CTRL_REGION_OP, 0x1); + + z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl); + + /* + * END needs to be setup before START (latter triggers the operation) + * END can't be same as START, so add (l2_line_sz - 1) to sz + */ + end_addr = start_addr + size + CONFIG_ARC_SLC_LINE_SIZE - 1; + + z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_END, end_addr); + /* Align start address to cache line size, see STAR 5103816 */ + z_arc_v2_aux_reg_write(_ARC_V2_SLC_RGN_START, + start_addr & ~(CONFIG_ARC_SLC_LINE_SIZE - 1)); + + /* Make sure "busy" bit reports correct status, see STAR 9001165532 */ + z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) { + /* Do Nothing */ + } + } +} + +static void slc_flush_all(void) +{ + K_SPINLOCK(&slc_lock) { + z_arc_v2_aux_reg_write(_ARC_V2_SLC_FLUSH, 0x1); + + /* Make sure "busy" bit reports correct status, see STAR 9001165532 */ + z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) { + /* Do Nothing */ + } + } +} + +static void slc_invalidate_all(void) +{ + uint32_t ctrl; + + K_SPINLOCK(&slc_lock) { + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + ctrl &= ~SLC_CTRL_INVALIDATE_MODE; + z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl); + + z_arc_v2_aux_reg_write(_ARC_V2_SLC_INVALIDATE, 0x1); + + /* Make sure "busy" bit reports correct status, see STAR 9001165532 */ + z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) { + /* Do Nothing */ + } + } +} + +static void slc_flush_and_invalidate_all(void) +{ + uint32_t ctrl; + + K_SPINLOCK(&slc_lock) { + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + ctrl |= SLC_CTRL_INVALIDATE_MODE; + z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, ctrl); + + z_arc_v2_aux_reg_write(_ARC_V2_SLC_INVALIDATE, 0x1); + + /* Make sure "busy" bit reports correct status, see STAR 9001165532 */ + z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); + while (z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL) & SLC_CTRL_BUSY_STATUS) { + /* Do Nothing */ + } + } +} +#endif /* CONFIG_ARC_SLC */ + void arch_dcache_enable(void) { dcache_dc_ctrl(DC_CTRL_DC_ENABLE); + +#if defined(CONFIG_ARC_SLC) + slc_enable(); +#endif } void arch_dcache_disable(void) @@ -65,17 +264,107 @@ void arch_dcache_disable(void) /* nothing */ } -int arch_dcache_flush_range(void *start_addr_ptr, size_t size) +#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS) +static void dcache_high_addr_init(void) +{ + z_arc_v2_aux_reg_write(_ARC_V2_DC_PTAG_HI, 0); +} + +static void dcache_flush_region(void *start_addr_ptr, size_t size) { size_t line_size = sys_cache_data_line_size_get(); uintptr_t start_addr = (uintptr_t)start_addr_ptr; uintptr_t end_addr; + uint32_t ctrl; unsigned int key; - if (!dcache_available() || (size == 0U) || line_size == 0U) { - return -ENOTSUP; + key = arch_irq_lock(); /* --enter critical section-- */ + + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL); + + ctrl &= ~DC_CTRL_REGION_OP; + + z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl); + + end_addr = start_addr + size + line_size - 1; + + z_arc_v2_aux_reg_write(_ARC_V2_DC_ENDR, end_addr); + z_arc_v2_aux_reg_write(_ARC_V2_DC_STARTR, start_addr); + + while (z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { + /* Do nothing */ + } + + arch_irq_unlock(key); /* --exit critical section-- */ +} + +static void dcache_invalidate_region(void *start_addr_ptr, size_t size) +{ + size_t line_size = sys_cache_data_line_size_get(); + uintptr_t start_addr = (uintptr_t)start_addr_ptr; + uintptr_t end_addr; + uint32_t ctrl; + unsigned int key; + + key = arch_irq_lock(); /* --enter critical section-- */ + + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL); + + ctrl &= ~DC_CTRL_INVALIDATE_MODE; + + ctrl &= ~DC_CTRL_REGION_OP; + ctrl |= FIELD_PREP(DC_CTRL_REGION_OP, 0x1); + + z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl); + + end_addr = start_addr + size + line_size - 1; + + z_arc_v2_aux_reg_write(_ARC_V2_DC_ENDR, end_addr); + z_arc_v2_aux_reg_write(_ARC_V2_DC_STARTR, start_addr); + + arch_irq_unlock(key); /* --exit critical section-- */ +} + +static void dcache_flush_and_invalidate_region(void *start_addr_ptr, size_t size) +{ + size_t line_size = sys_cache_data_line_size_get(); + uintptr_t start_addr = (uintptr_t)start_addr_ptr; + uintptr_t end_addr; + uint32_t ctrl; + unsigned int key; + + key = arch_irq_lock(); /* --enter critical section-- */ + + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL); + + ctrl |= DC_CTRL_INVALIDATE_MODE; + + ctrl &= ~DC_CTRL_REGION_OP; + ctrl |= FIELD_PREP(DC_CTRL_REGION_OP, 0x1); + + z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl); + + end_addr = start_addr + size + line_size - 1; + + z_arc_v2_aux_reg_write(_ARC_V2_DC_ENDR, end_addr); + z_arc_v2_aux_reg_write(_ARC_V2_DC_STARTR, start_addr); + + while (z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { + /* Do nothing */ } + arch_irq_unlock(key); /* --exit critical section-- */ +} + +#else /* CONFIG_ARC_DCACHE_REGION_OPERATIONS */ + +static void dcache_flush_lines(void *start_addr_ptr, size_t size) +{ + size_t line_size = sys_cache_data_line_size_get(); + uintptr_t start_addr = (uintptr_t)start_addr_ptr; + uintptr_t end_addr; + unsigned int key; + end_addr = start_addr + size; start_addr = ROUND_DOWN(start_addr, line_size); @@ -98,25 +387,52 @@ int arch_dcache_flush_range(void *start_addr_ptr, size_t size) } while (start_addr < end_addr); arch_irq_unlock(key); /* --exit critical section-- */ +} - return 0; +static void dcache_invalidate_lines(void *start_addr_ptr, size_t size) +{ + size_t line_size = sys_cache_data_line_size_get(); + uintptr_t start_addr = (uintptr_t)start_addr_ptr; + uintptr_t end_addr; + unsigned int key; + uint32_t ctrl; + + end_addr = start_addr + size; + start_addr = ROUND_DOWN(start_addr, line_size); + + key = arch_irq_lock(); /* -enter critical section- */ + + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL); + ctrl &= ~DC_CTRL_INVALIDATE_MODE; + z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl); + + do { + z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDL, start_addr); + __builtin_arc_nop(); + __builtin_arc_nop(); + __builtin_arc_nop(); + start_addr += line_size; + } while (start_addr < end_addr); + irq_unlock(key); /* -exit critical section- */ } -int arch_dcache_invd_range(void *start_addr_ptr, size_t size) +static void dcache_flush_and_invalidate_lines(void *start_addr_ptr, size_t size) { size_t line_size = sys_cache_data_line_size_get(); uintptr_t start_addr = (uintptr_t)start_addr_ptr; uintptr_t end_addr; unsigned int key; + uint32_t ctrl; - if (!dcache_available() || (size == 0U) || line_size == 0U) { - return -ENOTSUP; - } end_addr = start_addr + size; start_addr = ROUND_DOWN(start_addr, line_size); key = arch_irq_lock(); /* -enter critical section- */ + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL); + ctrl |= DC_CTRL_INVALIDATE_MODE; + z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl); + do { z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDL, start_addr); __builtin_arc_nop(); @@ -125,28 +441,155 @@ int arch_dcache_invd_range(void *start_addr_ptr, size_t size) start_addr += line_size; } while (start_addr < end_addr); irq_unlock(key); /* -exit critical section- */ +} + +#endif /* CONFIG_ARC_DCACHE_REGION_OPERATIONS */ + +int arch_dcache_flush_range(void *start_addr_ptr, size_t size) +{ + size_t line_size = sys_cache_data_line_size_get(); + + if (!dcache_available() || (size == 0U) || line_size == 0U) { + return -ENOTSUP; + } + +#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS) + dcache_flush_region(start_addr_ptr, size); +#else + dcache_flush_lines(start_addr_ptr, size); +#endif + +#if defined(CONFIG_ARC_SLC) + slc_flush_region(start_addr_ptr, size); +#endif + + return 0; +} + +int arch_dcache_invd_range(void *start_addr_ptr, size_t size) +{ + size_t line_size = sys_cache_data_line_size_get(); + + if (!dcache_available() || (size == 0U) || line_size == 0U) { + return -ENOTSUP; + } + +#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS) + dcache_invalidate_region(start_addr_ptr, size); +#else + dcache_invalidate_lines(start_addr_ptr, size); +#endif + +#if defined(CONFIG_ARC_SLC) + slc_invalidate_region(start_addr_ptr, size); +#endif return 0; } int arch_dcache_flush_and_invd_range(void *start_addr_ptr, size_t size) { - return -ENOTSUP; + size_t line_size = sys_cache_data_line_size_get(); + + if (!dcache_available() || (size == 0U) || line_size == 0U) { + return -ENOTSUP; + } + +#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS) + dcache_flush_and_invalidate_region(start_addr_ptr, size); +#else + dcache_flush_and_invalidate_lines(start_addr_ptr, size); +#endif + +#if defined(CONFIG_ARC_SLC) + slc_flush_and_invalidate_region(start_addr_ptr, size); +#endif + + return 0; } int arch_dcache_flush_all(void) { - return -ENOTSUP; + size_t line_size = sys_cache_data_line_size_get(); + unsigned int key; + + if (!dcache_available() || line_size == 0U) { + return -ENOTSUP; + } + + key = irq_lock(); + + z_arc_v2_aux_reg_write(_ARC_V2_DC_FLSH, 0x1); + + while (z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { + /* Do nothing */ + } + + irq_unlock(key); + +#if defined(CONFIG_ARC_SLC) + slc_flush_all(); +#endif + + return 0; } int arch_dcache_invd_all(void) { - return -ENOTSUP; + size_t line_size = sys_cache_data_line_size_get(); + unsigned int key; + uint32_t ctrl; + + if (!dcache_available() || line_size == 0U) { + return -ENOTSUP; + } + + key = irq_lock(); + + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL); + ctrl &= ~DC_CTRL_INVALIDATE_MODE; + z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl); + + z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 0x1); + + irq_unlock(key); + +#if defined(CONFIG_ARC_SLC) + slc_invalidate_all(); +#endif + + return 0; } int arch_dcache_flush_and_invd_all(void) { - return -ENOTSUP; + size_t line_size = sys_cache_data_line_size_get(); + unsigned int key; + uint32_t ctrl; + + if (!dcache_available() || line_size == 0U) { + return -ENOTSUP; + } + + key = irq_lock(); + + ctrl = z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL); + ctrl |= DC_CTRL_INVALIDATE_MODE; + z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, ctrl); + + z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 0x1); + + while (z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) & DC_CTRL_FLUSH_STATUS) { + /* Do nothing */ + } + + irq_unlock(key); + +#if defined(CONFIG_ARC_SLC) + slc_flush_and_invalidate_all(); +#endif + + return 0; } #if defined(CONFIG_DCACHE_LINE_SIZE_DETECT) @@ -224,6 +667,19 @@ static int init_dcache(void) init_dcache_line_size(); #endif + /* + * Init high address registers to 0 if PAE exists, cache operations for 40 bit addresses not + * implemented + */ + if (pae_exists()) { +#if defined(CONFIG_ARC_DCACHE_REGION_OPERATIONS) + dcache_high_addr_init(); +#endif +#if defined(CONFIG_ARC_SLC) + slc_high_addr_init(); +#endif + } + return 0; } diff --git a/arch/arc/core/dsp/Kconfig b/arch/arc/core/dsp/Kconfig index 48a910198ec..74704bd14fb 100644 --- a/arch/arc/core/dsp/Kconfig +++ b/arch/arc/core/dsp/Kconfig @@ -39,7 +39,7 @@ config ARC_XY_ENABLE bool "ARC address generation unit registers" help Processors with XY memory and AGU registers can configure this - option to accelerate DSP instrctions. + option to accelerate DSP instructions. config ARC_AGU_SHARING bool "ARC address generation unit register sharing" diff --git a/arch/arc/core/elf.c b/arch/arc/core/elf.c index db2a74e164e..b0dd1aceb84 100644 --- a/arch/arc/core/elf.c +++ b/arch/arc/core/elf.c @@ -15,6 +15,7 @@ LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); #define R_ARC_32 4 #define R_ARC_B26 5 /* AKA R_ARC_64 */ +#define R_ARC_S25H_PCREL 16 #define R_ARC_S25W_PCREL 17 #define R_ARC_32_ME 27 @@ -68,12 +69,28 @@ int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *r case R_ARC_B26: UNALIGNED_PUT(sym_base_addr, (uint32_t *)loc); break; - case R_ARC_S25W_PCREL: - /* ((S + A) - P) >> 2 + case R_ARC_S25H_PCREL: + /* ((S + A) - P) >> 1 * S = symbol address * A = addend * P = relative offset to PCL */ + value = (sym_base_addr + rel->r_addend - (loc & ~0x3)) >> 1; + + insn = ME(insn); + + /* disp25h */ + insn = insn & ~0x7feffcf; + insn |= ((value >> 0) & 0x03ff) << 17; + insn |= ((value >> 10) & 0x03ff) << 6; + insn |= ((value >> 20) & 0x000f) << 0; + + insn = ME(insn); + + UNALIGNED_PUT(insn, (uint32_t *)loc); + break; + case R_ARC_S25W_PCREL: + /* ((S + A) - P) >> 2 */ value = (sym_base_addr + rel->r_addend - (loc & ~0x3)) >> 2; insn = ME(insn); diff --git a/arch/arc/core/fatal.c b/arch/arc/core/fatal.c index 512d1cc442c..72a93ed15db 100644 --- a/arch/arc/core/fatal.c +++ b/arch/arc/core/fatal.c @@ -17,26 +17,25 @@ #include #include #include -#include -#include +#include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #ifdef CONFIG_EXCEPTION_DEBUG static void dump_arc_esf(const struct arch_esf *esf) { - ARC_EXCEPTION_DUMP(" r0: 0x%" PRIxPTR " r1: 0x%" PRIxPTR " r2: 0x%" PRIxPTR + EXCEPTION_DUMP(" r0: 0x%" PRIxPTR " r1: 0x%" PRIxPTR " r2: 0x%" PRIxPTR " r3: 0x%" PRIxPTR "", esf->r0, esf->r1, esf->r2, esf->r3); - ARC_EXCEPTION_DUMP(" r4: 0x%" PRIxPTR " r5: 0x%" PRIxPTR " r6: 0x%" PRIxPTR + EXCEPTION_DUMP(" r4: 0x%" PRIxPTR " r5: 0x%" PRIxPTR " r6: 0x%" PRIxPTR " r7: 0x%" PRIxPTR "", esf->r4, esf->r5, esf->r6, esf->r7); - ARC_EXCEPTION_DUMP(" r8: 0x%" PRIxPTR " r9: 0x%" PRIxPTR " r10: 0x%" PRIxPTR + EXCEPTION_DUMP(" r8: 0x%" PRIxPTR " r9: 0x%" PRIxPTR " r10: 0x%" PRIxPTR " r11: 0x%" PRIxPTR "", esf->r8, esf->r9, esf->r10, esf->r11); - ARC_EXCEPTION_DUMP("r12: 0x%" PRIxPTR " r13: 0x%" PRIxPTR " pc: 0x%" PRIxPTR "", + EXCEPTION_DUMP("r12: 0x%" PRIxPTR " r13: 0x%" PRIxPTR " pc: 0x%" PRIxPTR "", esf->r12, esf->r13, esf->pc); - ARC_EXCEPTION_DUMP(" blink: 0x%" PRIxPTR " status32: 0x%" PRIxPTR "", + EXCEPTION_DUMP(" blink: 0x%" PRIxPTR " status32: 0x%" PRIxPTR "", esf->blink, esf->status32); #ifdef CONFIG_ARC_HAS_ZOL - ARC_EXCEPTION_DUMP("lp_end: 0x%" PRIxPTR " lp_start: 0x%" PRIxPTR + EXCEPTION_DUMP("lp_end: 0x%" PRIxPTR " lp_start: 0x%" PRIxPTR " lp_count: 0x%" PRIxPTR "", esf->lp_end, esf->lp_start, esf->lp_count); #endif /* CONFIG_ARC_HAS_ZOL */ } diff --git a/arch/arc/core/fault.c b/arch/arc/core/fault.c index adbd6da12bb..c36f000c8cb 100644 --- a/arch/arc/core/fault.c +++ b/arch/arc/core/fault.c @@ -20,7 +20,6 @@ #include #include #include -#include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -138,32 +137,32 @@ static void dump_protv_exception(uint32_t cause, uint32_t parameter) { switch (cause) { case 0x0: - ARC_EXCEPTION_DUMP("Instruction fetch violation (%s)", + EXCEPTION_DUMP("Instruction fetch violation (%s)", get_protv_access_err(parameter)); break; case 0x1: - ARC_EXCEPTION_DUMP("Memory read protection violation (%s)", + EXCEPTION_DUMP("Memory read protection violation (%s)", get_protv_access_err(parameter)); break; case 0x2: - ARC_EXCEPTION_DUMP("Memory write protection violation (%s)", + EXCEPTION_DUMP("Memory write protection violation (%s)", get_protv_access_err(parameter)); break; case 0x3: - ARC_EXCEPTION_DUMP("Memory read-modify-write violation (%s)", + EXCEPTION_DUMP("Memory read-modify-write violation (%s)", get_protv_access_err(parameter)); break; case 0x10: - ARC_EXCEPTION_DUMP("Normal vector table in secure memory"); + EXCEPTION_DUMP("Normal vector table in secure memory"); break; case 0x11: - ARC_EXCEPTION_DUMP("NS handler code located in S memory"); + EXCEPTION_DUMP("NS handler code located in S memory"); break; case 0x12: - ARC_EXCEPTION_DUMP("NSC Table Range Violation"); + EXCEPTION_DUMP("NSC Table Range Violation"); break; default: - ARC_EXCEPTION_DUMP("unknown"); + EXCEPTION_DUMP("unknown"); break; } } @@ -172,46 +171,46 @@ static void dump_machine_check_exception(uint32_t cause, uint32_t parameter) { switch (cause) { case 0x0: - ARC_EXCEPTION_DUMP("double fault"); + EXCEPTION_DUMP("double fault"); break; case 0x1: - ARC_EXCEPTION_DUMP("overlapping TLB entries"); + EXCEPTION_DUMP("overlapping TLB entries"); break; case 0x2: - ARC_EXCEPTION_DUMP("fatal TLB error"); + EXCEPTION_DUMP("fatal TLB error"); break; case 0x3: - ARC_EXCEPTION_DUMP("fatal cache error"); + EXCEPTION_DUMP("fatal cache error"); break; case 0x4: - ARC_EXCEPTION_DUMP("internal memory error on instruction fetch"); + EXCEPTION_DUMP("internal memory error on instruction fetch"); break; case 0x5: - ARC_EXCEPTION_DUMP("internal memory error on data fetch"); + EXCEPTION_DUMP("internal memory error on data fetch"); break; case 0x6: - ARC_EXCEPTION_DUMP("illegal overlapping MPU entries"); + EXCEPTION_DUMP("illegal overlapping MPU entries"); if (parameter == 0x1) { - ARC_EXCEPTION_DUMP(" - jump and branch target"); + EXCEPTION_DUMP(" - jump and branch target"); } break; case 0x10: - ARC_EXCEPTION_DUMP("secure vector table not located in secure memory"); + EXCEPTION_DUMP("secure vector table not located in secure memory"); break; case 0x11: - ARC_EXCEPTION_DUMP("NSC jump table not located in secure memory"); + EXCEPTION_DUMP("NSC jump table not located in secure memory"); break; case 0x12: - ARC_EXCEPTION_DUMP("secure handler code not located in secure memory"); + EXCEPTION_DUMP("secure handler code not located in secure memory"); break; case 0x13: - ARC_EXCEPTION_DUMP("NSC target address not located in secure memory"); + EXCEPTION_DUMP("NSC target address not located in secure memory"); break; case 0x80: - ARC_EXCEPTION_DUMP("uncorrectable ECC or parity error in vector memory"); + EXCEPTION_DUMP("uncorrectable ECC or parity error in vector memory"); break; default: - ARC_EXCEPTION_DUMP("unknown"); + EXCEPTION_DUMP("unknown"); break; } } @@ -220,54 +219,54 @@ static void dump_privilege_exception(uint32_t cause, uint32_t parameter) { switch (cause) { case 0x0: - ARC_EXCEPTION_DUMP("Privilege violation"); + EXCEPTION_DUMP("Privilege violation"); break; case 0x1: - ARC_EXCEPTION_DUMP("disabled extension"); + EXCEPTION_DUMP("disabled extension"); break; case 0x2: - ARC_EXCEPTION_DUMP("action point hit"); + EXCEPTION_DUMP("action point hit"); break; case 0x10: switch (parameter) { case 0x1: - ARC_EXCEPTION_DUMP("N to S return using incorrect return mechanism"); + EXCEPTION_DUMP("N to S return using incorrect return mechanism"); break; case 0x2: - ARC_EXCEPTION_DUMP("N to S return with incorrect operating mode"); + EXCEPTION_DUMP("N to S return with incorrect operating mode"); break; case 0x3: - ARC_EXCEPTION_DUMP("IRQ/exception return fetch from wrong mode"); + EXCEPTION_DUMP("IRQ/exception return fetch from wrong mode"); break; case 0x4: - ARC_EXCEPTION_DUMP("attempt to halt secure processor in NS mode"); + EXCEPTION_DUMP("attempt to halt secure processor in NS mode"); break; case 0x20: - ARC_EXCEPTION_DUMP("attempt to access secure resource from normal mode"); + EXCEPTION_DUMP("attempt to access secure resource from normal mode"); break; case 0x40: - ARC_EXCEPTION_DUMP("SID violation on resource access (APEX/UAUX/key NVM)"); + EXCEPTION_DUMP("SID violation on resource access (APEX/UAUX/key NVM)"); break; default: - ARC_EXCEPTION_DUMP("unknown"); + EXCEPTION_DUMP("unknown"); break; } break; case 0x13: switch (parameter) { case 0x20: - ARC_EXCEPTION_DUMP("attempt to access secure APEX feature from NS mode"); + EXCEPTION_DUMP("attempt to access secure APEX feature from NS mode"); break; case 0x40: - ARC_EXCEPTION_DUMP("SID violation on access to APEX feature"); + EXCEPTION_DUMP("SID violation on access to APEX feature"); break; default: - ARC_EXCEPTION_DUMP("unknown"); + EXCEPTION_DUMP("unknown"); break; } break; default: - ARC_EXCEPTION_DUMP("unknown"); + EXCEPTION_DUMP("unknown"); break; } } @@ -275,7 +274,7 @@ static void dump_privilege_exception(uint32_t cause, uint32_t parameter) static void dump_exception_info(uint32_t vector, uint32_t cause, uint32_t parameter) { if (vector >= 0x10 && vector <= 0xFF) { - ARC_EXCEPTION_DUMP("interrupt %u", vector); + EXCEPTION_DUMP("interrupt %u", vector); return; } @@ -284,55 +283,55 @@ static void dump_exception_info(uint32_t vector, uint32_t cause, uint32_t parame */ switch (vector) { case ARC_EV_RESET: - ARC_EXCEPTION_DUMP("Reset"); + EXCEPTION_DUMP("Reset"); break; case ARC_EV_MEM_ERROR: - ARC_EXCEPTION_DUMP("Memory Error"); + EXCEPTION_DUMP("Memory Error"); break; case ARC_EV_INS_ERROR: - ARC_EXCEPTION_DUMP("Instruction Error"); + EXCEPTION_DUMP("Instruction Error"); break; case ARC_EV_MACHINE_CHECK: - ARC_EXCEPTION_DUMP("EV_MachineCheck"); + EXCEPTION_DUMP("EV_MachineCheck"); dump_machine_check_exception(cause, parameter); break; case ARC_EV_TLB_MISS_I: - ARC_EXCEPTION_DUMP("EV_TLBMissI"); + EXCEPTION_DUMP("EV_TLBMissI"); break; case ARC_EV_TLB_MISS_D: - ARC_EXCEPTION_DUMP("EV_TLBMissD"); + EXCEPTION_DUMP("EV_TLBMissD"); break; case ARC_EV_PROT_V: - ARC_EXCEPTION_DUMP("EV_ProtV"); + EXCEPTION_DUMP("EV_ProtV"); dump_protv_exception(cause, parameter); break; case ARC_EV_PRIVILEGE_V: - ARC_EXCEPTION_DUMP("EV_PrivilegeV"); + EXCEPTION_DUMP("EV_PrivilegeV"); dump_privilege_exception(cause, parameter); break; case ARC_EV_SWI: - ARC_EXCEPTION_DUMP("EV_SWI"); + EXCEPTION_DUMP("EV_SWI"); break; case ARC_EV_TRAP: - ARC_EXCEPTION_DUMP("EV_Trap"); + EXCEPTION_DUMP("EV_Trap"); break; case ARC_EV_EXTENSION: - ARC_EXCEPTION_DUMP("EV_Extension"); + EXCEPTION_DUMP("EV_Extension"); break; case ARC_EV_DIV_ZERO: - ARC_EXCEPTION_DUMP("EV_DivZero"); + EXCEPTION_DUMP("EV_DivZero"); break; case ARC_EV_DC_ERROR: - ARC_EXCEPTION_DUMP("EV_DCError"); + EXCEPTION_DUMP("EV_DCError"); break; case ARC_EV_MISALIGNED: - ARC_EXCEPTION_DUMP("EV_Misaligned"); + EXCEPTION_DUMP("EV_Misaligned"); break; case ARC_EV_VEC_UNIT: - ARC_EXCEPTION_DUMP("EV_VecUnit"); + EXCEPTION_DUMP("EV_VecUnit"); break; default: - ARC_EXCEPTION_DUMP("unknown"); + EXCEPTION_DUMP("unknown"); break; } } @@ -386,9 +385,9 @@ void z_arc_fault(struct arch_esf *esf, uint32_t old_sp) } #ifdef CONFIG_EXCEPTION_DEBUG - ARC_EXCEPTION_DUMP("***** Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x", + EXCEPTION_DUMP("***** Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x", vector, cause, parameter); - ARC_EXCEPTION_DUMP("Address 0x%x", exc_addr); + EXCEPTION_DUMP("Address 0x%x", exc_addr); dump_exception_info(vector, cause, parameter); #endif diff --git a/arch/arc/core/reset.S b/arch/arc/core/reset.S index a2b038d387e..5824d524c57 100644 --- a/arch/arc/core/reset.S +++ b/arch/arc/core/reset.S @@ -163,20 +163,20 @@ hw_pf_setup_done: #if defined(CONFIG_SMP) || CONFIG_MP_MAX_NUM_CPUS > 1 _get_cpu_id r0 - breq r0, 0, _master_core_startup + breq r0, 0, _primary_core_startup /* - * Non-masters wait for master core (core 0) to boot enough + * Non-primary cores wait for primary core (core 0) to boot enough */ -_slave_core_wait: +_secondary_core_wait: #if CONFIG_MP_MAX_NUM_CPUS == 1 kflag 1 #endif ld r1, [arc_cpu_wake_flag] - brne r0, r1, _slave_core_wait + brne r0, r1, _secondary_core_wait LDR sp, arc_cpu_sp - /* signal master core that slave core runs */ + /* signal primary core that secondary core runs */ st 0, [arc_cpu_wake_flag] #if defined(CONFIG_ARC_FIRQ_STACK) @@ -186,7 +186,7 @@ _slave_core_wait: #endif j arch_secondary_cpu_init -_master_core_startup: +_primary_core_startup: #endif #ifdef CONFIG_INIT_STACKS diff --git a/arch/arc/core/smp.c b/arch/arc/core/smp.c index 1b06c2ac7d1..9da905ca5d2 100644 --- a/arch/arc/core/smp.c +++ b/arch/arc/core/smp.c @@ -25,10 +25,10 @@ volatile struct { } arc_cpu_init[CONFIG_MP_MAX_NUM_CPUS]; /* - * arc_cpu_wake_flag is used to sync up master core and slave cores - * Slave core will spin for arc_cpu_wake_flag until master core sets - * it to the core id of slave core. Then, slave core clears it to notify - * master core that it's waken + * arc_cpu_wake_flag is used to sync up primary core and secondary cores + * Secondary core will spin for arc_cpu_wake_flag until primary core sets + * it to the core id of secondary core. Then, secondary core clears it to notify + * primary core that it's waken * */ volatile uint32_t arc_cpu_wake_flag; @@ -50,13 +50,13 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, /* set the initial sp of target sp through arc_cpu_sp * arc_cpu_wake_flag will protect arc_cpu_sp that - * only one slave cpu can read it per time + * only one secondary cpu can read it per time */ arc_cpu_sp = K_KERNEL_STACK_BUFFER(stack) + sz; arc_cpu_wake_flag = cpu_num; - /* wait slave cpu to start */ + /* wait secondary cpu to start */ while (arc_cpu_wake_flag != 0U) { ; } @@ -90,7 +90,7 @@ static void arc_connect_debug_mask_update(int cpu_num) void arc_core_private_intc_init(void); -/* the C entry of slave cores */ +/* the C entry of secondary cores */ void arch_secondary_cpu_init(int cpu_num) { arch_cpustart_t fn; @@ -162,7 +162,7 @@ int arch_smp_init(void) { struct arc_connect_bcr bcr; - /* necessary master core init */ + /* necessary primary core init */ _curr_cpu[0] = &(_kernel.cpus[0]); bcr.val = z_arc_v2_aux_reg_read(_ARC_V2_CONNECT_BCR); @@ -173,7 +173,7 @@ int arch_smp_init(void) } if (bcr.ipi) { - /* register ici interrupt, just need master core to register once */ + /* register ici interrupt, just need primary core to register once */ z_arc_connect_ici_clear(); IRQ_CONNECT(DT_IRQN(DT_NODELABEL(ici)), DT_IRQ(DT_NODELABEL(ici), priority), diff --git a/arch/arc/core/thread.c b/arch/arc/core/thread.c index 4b1d836103e..387f983780b 100644 --- a/arch/arc/core/thread.c +++ b/arch/arc/core/thread.c @@ -276,6 +276,15 @@ int arch_float_enable(struct k_thread *thread, unsigned int options) } #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ +int arch_coprocessors_disable(struct k_thread *thread) +{ +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + return arch_float_disable(thread); +#else + return -ENOTSUP; +#endif +} + #if !defined(CONFIG_MULTITHREADING) K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_ISR_STACK_SIZE); diff --git a/arch/arc/core/vector_table.c b/arch/arc/core/vector_table.c index 5ad6e5763e8..d334ae2b8a4 100644 --- a/arch/arc/core/vector_table.c +++ b/arch/arc/core/vector_table.c @@ -47,7 +47,7 @@ struct vector_table { uintptr_t unused_2; }; -struct vector_table _VectorTable Z_GENERIC_SECTION(.exc_vector_table) = { +const struct vector_table _VectorTable Z_GENERIC_SECTION(.exc_vector_table) = { (uintptr_t)__reset, (uintptr_t)__memory_error, (uintptr_t)__instruction_error, diff --git a/arch/arc/include/err_dump_handling.h b/arch/arc/include/err_dump_handling.h deleted file mode 100644 index 2bda8b86687..00000000000 --- a/arch/arc/include/err_dump_handling.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2023 Synopsys. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_ARCH_ARC_INCLUDE_ERR_DUMP_HANDLING_H_ -#define ZEPHYR_ARCH_ARC_INCLUDE_ERR_DUMP_HANDLING_H_ - -#if defined CONFIG_LOG -#define ARC_EXCEPTION_DUMP(...) LOG_ERR(__VA_ARGS__) -#else -#define ARC_EXCEPTION_DUMP(format, ...) printk(format "\n", ##__VA_ARGS__) -#endif - -#endif /* ZEPHYR_ARCH_ARC_INCLUDE_ERR_DUMP_HANDLING_H_ */ diff --git a/arch/archs.yml b/arch/archs.yml index 352a296dde2..c8ee38ab437 100644 --- a/arch/archs.yml +++ b/arch/archs.yml @@ -1,21 +1,31 @@ archs: - name: arc path: arc + full_name: Synopsys DesignWare ARC - name: arm path: arm + full_name: ARM - name: arm64 path: arm64 + full_name: ARM 64 - name: mips path: mips + full_name: MIPS - name: posix path: posix + full_name: POSIX - name: riscv path: riscv + full_name: RISC-V - name: sparc path: sparc + full_name: SPARC - name: xtensa path: xtensa + full_name: Xtensa - name: x86 path: x86 + full_name: x86 - name: rx path: rx + full_name: Renesas RX diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3ce78334cb6..7b6b292b5c1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -49,7 +49,7 @@ config ROMSTART_RELOCATION_ROM Most SOCs include an alias for the boot-vector at address 0x00000000 so a default which might be supported by the corresponding Linux rproc driver. - If it is not, additionnal options allows to specify the addresses. + If it is not, additional options allow to specify the addresses. In general this option should be chosen if the zephyr,flash chosen node is not placed into the boot-vector memory area. diff --git a/arch/arm/core/Kconfig.vfp b/arch/arm/core/Kconfig.vfp index 71c94b71ff1..8654d5f9ad0 100644 --- a/arch/arm/core/Kconfig.vfp +++ b/arch/arm/core/Kconfig.vfp @@ -109,6 +109,17 @@ config VFP_U_DP_D16_FP16_FMAC fused multiply-accumulate) and floating-point exception trapping with 16 double-word registers. +config VFP_DP_D32 + bool + select CPU_HAS_VFP + select VFP_FEATURE_SINGLE_PRECISION + select VFP_FEATURE_DOUBLE_PRECISION + select VFP_FEATURE_REGS_S64_D32 + help + This option signifies the use of a VFP floating-point coprocessor + that supports single- and double-precision operations + with 32 double-word registers. + config VFP_DP_D32_FP16_FMAC bool select CPU_HAS_VFP diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c index cab76d32f49..eb0b2c39e68 100644 --- a/arch/arm/core/cortex_a_r/cache.c +++ b/arch/arm/core/cortex_a_r/cache.c @@ -203,11 +203,16 @@ int arch_icache_flush_and_invd_all(void) int arch_icache_flush_range(void *start_addr, size_t size) { + ARG_UNUSED(start_addr); + ARG_UNUSED(size); + return -ENOTSUP; } int arch_icache_invd_range(void *start_addr, size_t size) { + ARG_UNUSED(start_addr); + ARG_UNUSED(size); /* Cortex A/R do have the ICIMVAU operation to selectively invalidate * the instruction cache, but not currently supported by CMSIS. * For now, invalidate the entire cache. @@ -219,6 +224,9 @@ int arch_icache_invd_range(void *start_addr, size_t size) int arch_icache_flush_and_invd_range(void *start_addr, size_t size) { + ARG_UNUSED(start_addr); + ARG_UNUSED(size); + return -ENOTSUP; } diff --git a/arch/arm/core/cortex_a_r/fault.c b/arch/arm/core/cortex_a_r/fault.c index b6916706d6f..0dc141a1435 100644 --- a/arch/arm/core/cortex_a_r/fault.c +++ b/arch/arm/core/cortex_a_r/fault.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -51,7 +52,7 @@ static void dump_debug_event(void) uint32_t moe = (dbgdscr & DBGDSCR_MOE_Msk) >> DBGDSCR_MOE_Pos; /* Print debug event information */ - LOG_ERR("Debug Event (%s)", get_dbgdscr_moe_string(moe)); + EXCEPTION_DUMP("Debug Event (%s)", get_dbgdscr_moe_string(moe)); } static uint32_t dump_fault(uint32_t status, uint32_t addr) @@ -65,27 +66,27 @@ static uint32_t dump_fault(uint32_t status, uint32_t addr) switch (status) { case FSR_FS_ALIGNMENT_FAULT: reason = K_ERR_ARM_ALIGNMENT_FAULT; - LOG_ERR("Alignment Fault @ 0x%08x", addr); + EXCEPTION_DUMP("Alignment Fault @ 0x%08x", addr); break; case FSR_FS_PERMISSION_FAULT: reason = K_ERR_ARM_PERMISSION_FAULT; - LOG_ERR("Permission Fault @ 0x%08x", addr); + EXCEPTION_DUMP("Permission Fault @ 0x%08x", addr); break; case FSR_FS_SYNC_EXTERNAL_ABORT: reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT; - LOG_ERR("Synchronous External Abort @ 0x%08x", addr); + EXCEPTION_DUMP("Synchronous External Abort @ 0x%08x", addr); break; case FSR_FS_ASYNC_EXTERNAL_ABORT: reason = K_ERR_ARM_ASYNC_EXTERNAL_ABORT; - LOG_ERR("Asynchronous External Abort"); + EXCEPTION_DUMP("Asynchronous External Abort"); break; case FSR_FS_SYNC_PARITY_ERROR: reason = K_ERR_ARM_SYNC_PARITY_ERROR; - LOG_ERR("Synchronous Parity/ECC Error @ 0x%08x", addr); + EXCEPTION_DUMP("Synchronous Parity/ECC Error @ 0x%08x", addr); break; case FSR_FS_ASYNC_PARITY_ERROR: reason = K_ERR_ARM_ASYNC_PARITY_ERROR; - LOG_ERR("Asynchronous Parity/ECC Error"); + EXCEPTION_DUMP("Asynchronous Parity/ECC Error"); break; case FSR_FS_DEBUG_EVENT: reason = K_ERR_ARM_DEBUG_EVENT; @@ -94,73 +95,77 @@ static uint32_t dump_fault(uint32_t status, uint32_t addr) #if defined(CONFIG_AARCH32_ARMV8_R) case FSR_FS_TRANSLATION_FAULT: reason = K_ERR_ARM_TRANSLATION_FAULT; - LOG_ERR("Translation Fault @ 0x%08x", addr); + EXCEPTION_DUMP("Translation Fault @ 0x%08x", addr); break; case FSR_FS_UNSUPPORTED_EXCLUSIVE_ACCESS_FAULT: reason = K_ERR_ARM_UNSUPPORTED_EXCLUSIVE_ACCESS_FAULT; - LOG_ERR("Unsupported Exclusive Access Fault @ 0x%08x", addr); + EXCEPTION_DUMP("Unsupported Exclusive Access Fault @ 0x%08x", addr); break; #elif defined(CONFIG_ARMV7_A) case FSR_FS_PERMISSION_FAULT_2ND_LEVEL: reason = K_ERR_ARM_PERMISSION_FAULT_2ND_LEVEL; - LOG_ERR("2nd Level Permission Fault @ 0x%08x", addr); + EXCEPTION_DUMP("2nd Level Permission Fault @ 0x%08x", addr); break; case FSR_FS_ACCESS_FLAG_FAULT_1ST_LEVEL: reason = K_ERR_ARM_ACCESS_FLAG_FAULT_1ST_LEVEL; - LOG_ERR("1st Level Access Flag Fault @ 0x%08x", addr); + EXCEPTION_DUMP("1st Level Access Flag Fault @ 0x%08x", addr); break; case FSR_FS_ACCESS_FLAG_FAULT_2ND_LEVEL: reason = K_ERR_ARM_ACCESS_FLAG_FAULT_2ND_LEVEL; - LOG_ERR("2nd Level Access Flag Fault @ 0x%08x", addr); + EXCEPTION_DUMP("2nd Level Access Flag Fault @ 0x%08x", addr); break; case FSR_FS_CACHE_MAINTENANCE_INSTRUCTION_FAULT: reason = K_ERR_ARM_CACHE_MAINTENANCE_INSTRUCTION_FAULT; - LOG_ERR("Cache Maintenance Instruction Fault @ 0x%08x", addr); + EXCEPTION_DUMP("Cache Maintenance Instruction Fault @ 0x%08x", addr); break; case FSR_FS_TRANSLATION_FAULT: reason = K_ERR_ARM_TRANSLATION_FAULT; - LOG_ERR("1st Level Translation Fault @ 0x%08x", addr); + EXCEPTION_DUMP("1st Level Translation Fault @ 0x%08x", addr); break; case FSR_FS_TRANSLATION_FAULT_2ND_LEVEL: reason = K_ERR_ARM_TRANSLATION_FAULT_2ND_LEVEL; - LOG_ERR("2nd Level Translation Fault @ 0x%08x", addr); + EXCEPTION_DUMP("2nd Level Translation Fault @ 0x%08x", addr); break; case FSR_FS_DOMAIN_FAULT_1ST_LEVEL: reason = K_ERR_ARM_DOMAIN_FAULT_1ST_LEVEL; - LOG_ERR("1st Level Domain Fault @ 0x%08x", addr); + EXCEPTION_DUMP("1st Level Domain Fault @ 0x%08x", addr); break; case FSR_FS_DOMAIN_FAULT_2ND_LEVEL: reason = K_ERR_ARM_DOMAIN_FAULT_2ND_LEVEL; - LOG_ERR("2nd Level Domain Fault @ 0x%08x", addr); + EXCEPTION_DUMP("2nd Level Domain Fault @ 0x%08x", addr); break; case FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL: reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL; - LOG_ERR("1st Level Synchronous External Abort Translation Table @ 0x%08x", addr); + EXCEPTION_DUMP("1st Level Synchronous External Abort Translation Table @ 0x%08x", + addr); break; case FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL: reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL; - LOG_ERR("2nd Level Synchronous External Abort Translation Table @ 0x%08x", addr); + EXCEPTION_DUMP("2nd Level Synchronous External Abort Translation Table @ 0x%08x", + addr); break; case FSR_FS_TLB_CONFLICT_ABORT: reason = K_ERR_ARM_TLB_CONFLICT_ABORT; - LOG_ERR("TLB Conflict Abort @ 0x%08x", addr); + EXCEPTION_DUMP("TLB Conflict Abort @ 0x%08x", addr); break; case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL: reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL; - LOG_ERR("1st Level Synchronous Parity Error Translation Table @ 0x%08x", addr); + EXCEPTION_DUMP("1st Level Synchronous Parity Error Translation Table @ 0x%08x", + addr); break; case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL: reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL; - LOG_ERR("2nd Level Synchronous Parity Error Translation Table @ 0x%08x", addr); + EXCEPTION_DUMP("2nd Level Synchronous Parity Error Translation Table @ 0x%08x", + addr); break; #else case FSR_FS_BACKGROUND_FAULT: reason = K_ERR_ARM_BACKGROUND_FAULT; - LOG_ERR("Background Fault @ 0x%08x", addr); + EXCEPTION_DUMP("Background Fault @ 0x%08x", addr); break; #endif default: - LOG_ERR("Unknown (%u)", status); + EXCEPTION_DUMP("Unknown (%u)", status); } return reason; } @@ -280,7 +285,7 @@ bool z_arm_fault_undef_instruction(struct arch_esf *esf) #endif /* Print fault information */ - LOG_ERR("***** UNDEFINED INSTRUCTION ABORT *****"); + EXCEPTION_DUMP("***** UNDEFINED INSTRUCTION ABORT *****"); uint32_t reason = IS_ENABLED(CONFIG_SIMPLIFIED_EXCEPTION_CODES) ? K_ERR_CPU_EXCEPTION : @@ -325,7 +330,7 @@ bool z_arm_fault_prefetch(struct arch_esf *esf) return false; #endif /* Print fault information*/ - LOG_ERR("***** PREFETCH ABORT *****"); + EXCEPTION_DUMP("***** PREFETCH ABORT *****"); if (FAULT_DUMP_VERBOSE) { reason = dump_fault(fs, ifar); } @@ -409,7 +414,7 @@ bool z_arm_fault_data(struct arch_esf *esf) #endif /* Print fault information*/ - LOG_ERR("***** DATA ABORT *****"); + EXCEPTION_DUMP("***** DATA ABORT *****"); if (FAULT_DUMP_VERBOSE) { reason = dump_fault(fs, dfar); } diff --git a/arch/arm/core/cortex_a_r/irq_manage.c b/arch/arm/core/cortex_a_r/irq_manage.c index 5303d1d7178..34d3d3502f9 100644 --- a/arch/arm/core/cortex_a_r/irq_manage.c +++ b/arch/arm/core/cortex_a_r/irq_manage.c @@ -132,7 +132,7 @@ static inline void z_arm_irq_dynamic_direct_isr_dispatch(void) uint32_t irq = __get_IPSR() - 16; if (irq < IRQ_TABLE_SIZE) { - struct _isr_table_entry *isr_entry = &_sw_isr_table[irq]; + const struct _isr_table_entry *isr_entry = &_sw_isr_table[irq]; isr_entry->isr(isr_entry->arg); } diff --git a/arch/arm/core/cortex_a_r/reset.S b/arch/arm/core/cortex_a_r/reset.S index b5b899194e0..1a58d76d3c7 100644 --- a/arch/arm/core/cortex_a_r/reset.S +++ b/arch/arm/core/cortex_a_r/reset.S @@ -227,12 +227,12 @@ EL1_Reset_Handler: /* signal our desire to vote */ mov r5, #1 strb r5, [r4, r2] + mov r7, #0 ldr r3, [r0, #BOOT_PARAM_MPID_OFFSET] cmn r3, #1 beq 1f /* some core already won, release */ - mov r7, #0 strb r7, [r4, r2] b _secondary_core diff --git a/arch/arm/core/cortex_a_r/thread.c b/arch/arm/core/cortex_a_r/thread.c index b3bd91ce5c1..96d32b8f58d 100644 --- a/arch/arm/core/cortex_a_r/thread.c +++ b/arch/arm/core/cortex_a_r/thread.c @@ -409,7 +409,18 @@ int arch_float_disable(struct k_thread *thread) int arch_float_enable(struct k_thread *thread, unsigned int options) { + ARG_UNUSED(thread); + ARG_UNUSED(options); /* This is not supported in Cortex-A and Cortex-R */ return -ENOTSUP; } #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ + +int arch_coprocessors_disable(struct k_thread *thread) +{ +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + return arch_float_disable(thread); +#else + return -ENOTSUP; +#endif +} diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index eb54301c30c..cb7f134598f 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -63,6 +63,17 @@ config CPU_CORTEX_M33 help This option signifies the use of a Cortex-M33 CPU +config CPU_CORTEX_M52 + bool + select CPU_CORTEX_M + select ARMV8_1_M_MAINLINE + select ARMV8_M_SE if CPU_HAS_TEE + select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + help + This option signifies the use of a Cortex-M52 CPU + config CPU_CORTEX_M55 bool select CPU_CORTEX_M diff --git a/arch/arm/core/cortex_m/cache.c b/arch/arm/core/cortex_m/cache.c index a56996c8931..ba9d02cfdb2 100644 --- a/arch/arm/core/cortex_m/cache.c +++ b/arch/arm/core/cortex_m/cache.c @@ -96,6 +96,9 @@ int arch_icache_flush_and_invd_all(void) int arch_icache_flush_range(void *start_addr, size_t size) { + ARG_UNUSED(start_addr); + ARG_UNUSED(size); + return -ENOTSUP; } @@ -108,6 +111,9 @@ int arch_icache_invd_range(void *start_addr, size_t size) int arch_icache_flush_and_invd_range(void *start_addr, size_t size) { + ARG_UNUSED(start_addr); + ARG_UNUSED(size); + return -ENOTSUP; } diff --git a/arch/arm/core/cortex_m/debug.c b/arch/arm/core/cortex_m/debug.c index 47141d913dd..1b7646605da 100644 --- a/arch/arm/core/cortex_m/debug.c +++ b/arch/arm/core/cortex_m/debug.c @@ -13,6 +13,7 @@ #include #include #include +#include /** * @brief Assess whether a debug monitor event should be treated as an error diff --git a/arch/arm/core/cortex_m/fault.c b/arch/arm/core/cortex_m/fault.c index 27ce260dad5..204b403535c 100644 --- a/arch/arm/core/cortex_m/fault.c +++ b/arch/arm/core/cortex_m/fault.c @@ -15,14 +15,17 @@ #include #include #include +#include #include #include #include #include +#include + LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #if defined(CONFIG_PRINTK) || defined(CONFIG_LOG) -#define PR_EXC(...) LOG_ERR(__VA_ARGS__) +#define PR_EXC(...) EXCEPTION_DUMP(__VA_ARGS__) #define STORE_xFAR(reg_var, reg) uint32_t reg_var = (uint32_t)reg #else #define PR_EXC(...) diff --git a/arch/arm/core/cortex_m/fpu.c b/arch/arm/core/cortex_m/fpu.c index b937d725c28..0b8499afd6e 100644 --- a/arch/arm/core/cortex_m/fpu.c +++ b/arch/arm/core/cortex_m/fpu.c @@ -16,7 +16,7 @@ void z_arm_save_fp_context(struct fpu_ctx_full *buffer) { -#if defined(CONFIG_FPU_SHARING) +#if defined(CONFIG_FPU) __ASSERT_NO_MSG(buffer != NULL); uint32_t CONTROL = __get_CONTROL(); @@ -44,7 +44,7 @@ void z_arm_save_fp_context(struct fpu_ctx_full *buffer) void z_arm_restore_fp_context(const struct fpu_ctx_full *buffer) { -#if defined(CONFIG_FPU_SHARING) +#if defined(CONFIG_FPU) if (buffer->ctx_saved) { /* Set FPCA first so it is set even if an interrupt happens * during restoration. diff --git a/arch/arm/core/cortex_m/irq_manage.c b/arch/arm/core/cortex_m/irq_manage.c index 6d1c8917c4d..80d2f1bc3d0 100644 --- a/arch/arm/core/cortex_m/irq_manage.c +++ b/arch/arm/core/cortex_m/irq_manage.c @@ -132,33 +132,17 @@ void z_irq_spurious(const void *unused) #ifdef CONFIG_PM void _arch_isr_direct_pm(void) { -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) unsigned int key; - /* irq_lock() does what we want for this CPU */ - key = irq_lock(); -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - /* Lock all interrupts. irq_lock() will on this CPU only disable those - * lower than BASEPRI, which is not what we want. See comments in - * arch/arm/core/cortex_m/isr_wrapper.c - */ - __asm__ volatile("cpsid i" : : : "memory"); -#else -#error Unknown ARM architecture -#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ + /* Disable all interrupts except ZLIs. */ + key = arch_irq_lock(); if (_kernel.idle) { _kernel.idle = 0; pm_system_resume(); } -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) - irq_unlock(key); -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - __asm__ volatile("cpsie i" : : : "memory"); -#else -#error Unknown ARM architecture -#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ + arch_irq_unlock(key); } #endif @@ -272,7 +256,7 @@ static inline void z_arm_irq_dynamic_direct_isr_dispatch(void) uint32_t irq = __get_IPSR() - 16; if (irq < IRQ_TABLE_SIZE) { - struct _isr_table_entry *isr_entry = &_sw_isr_table[irq]; + const struct _isr_table_entry *isr_entry = &_sw_isr_table[irq]; isr_entry->isr(isr_entry->arg); } diff --git a/arch/arm/core/cortex_m/isr_wrapper.c b/arch/arm/core/cortex_m/isr_wrapper.c index cb72797e2ec..c9f6b1db21c 100644 --- a/arch/arm/core/cortex_m/isr_wrapper.c +++ b/arch/arm/core/cortex_m/isr_wrapper.c @@ -38,21 +38,21 @@ void _isr_wrapper(void) #ifdef CONFIG_PM /* - * All interrupts are disabled when handling idle wakeup. For tickless - * idle, this ensures that the calculation and programming of the - * device for the next timer deadline is not interrupted. For + * All non-ZLI interrupts are disabled when handling idle wakeup. For + * tickless idle, this ensures that the calculation and programming of + * the device for the next timer deadline is not interrupted. For * non-tickless idle, this ensures that the clearing of the kernel idle - * state is not interrupted. In each case, pm_system_resume - * is called with interrupts disabled. + * state is not interrupted. In each case, pm_system_resume is called + * with non-ZLI interrupts disabled. */ /* - * Disable interrupts to prevent nesting while exiting idle state. This - * is only necessary for the Cortex-M because it is the only ARM - * architecture variant that automatically enables interrupts when + * Disable non-ZLI interrupts to prevent nesting while exiting idle + * state. This is only necessary for the Cortex-M because it is the only + * ARM architecture variant that automatically enables interrupts when * entering an ISR. */ - __disable_irq(); + unsigned int key = arch_irq_lock(); /* is this a wakeup from idle ? */ /* requested idle duration, in ticks */ @@ -62,7 +62,7 @@ void _isr_wrapper(void) pm_system_resume(); } /* re-enable interrupts */ - __enable_irq(); + arch_irq_unlock(key); #endif /* CONFIG_PM */ #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) @@ -76,7 +76,7 @@ void _isr_wrapper(void) */ irq_number -= 16; - struct _isr_table_entry *entry = &_sw_isr_table[irq_number]; + const struct _isr_table_entry *entry = &_sw_isr_table[irq_number]; (entry->isr)(entry->arg); #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index 632fc142003..bc317f8ddec 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -22,6 +22,7 @@ #include #include #include +#include /* * GCC can detect if memcpy is passed a NULL argument, however one of diff --git a/arch/arm/core/cortex_m/thread.c b/arch/arm/core/cortex_m/thread.c index f1fc2019d9c..7abba0cdeef 100644 --- a/arch/arm/core/cortex_m/thread.c +++ b/arch/arm/core/cortex_m/thread.c @@ -455,11 +455,22 @@ int arch_float_disable(struct k_thread *thread) int arch_float_enable(struct k_thread *thread, unsigned int options) { + ARG_UNUSED(thread); + ARG_UNUSED(options); /* This is not supported in Cortex-M */ return -ENOTSUP; } #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ +int arch_coprocessors_disable(struct k_thread *thread) +{ +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + return arch_float_disable(thread); +#else + return -ENOTSUP; +#endif +} + /* Internal function for Cortex-M initialization, * applicable to either case of running Zephyr * with or without multi-threading support. @@ -557,6 +568,10 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, "ldr r4, =z_thread_entry\n" /* We don’t intend to return, so there is no need to link. */ "bx r4\n" + /* Force a literal pool placement for the addresses referenced above */ +#ifndef __IAR_SYSTEMS_ICC__ + ".ltorg\n" +#endif : : "r"(_main), "r"(stack_ptr) : "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory"); @@ -623,6 +638,10 @@ FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(k_thread_entry_t main_ "ldr r0, =arch_irq_lock_outlined\n" "blx r0\n" "loop: b loop\n\t" /* while (true); */ + /* Force a literal pool placement for the addresses referenced above */ +#ifndef __IAR_SYSTEMS_ICC__ + ".ltorg\n" +#endif : : [_p1] "r"(p1), [_p2] "r"(p2), [_p3] "r"(p3), [_psp] "r"(psp), [_main_entry] "r"(main_entry) diff --git a/arch/arm/core/elf.c b/arch/arm/core/elf.c index d44e7dd2e2c..1012d846b34 100644 --- a/arch/arm/core/elf.c +++ b/arch/arm/core/elf.c @@ -104,6 +104,8 @@ static inline int prel31_decode(elf_word reloc_type, uint32_t loc, { int ret; + ARG_UNUSED(reloc_type); + *offset = sign_extend(*(int32_t *)loc, SHIFT_PREL31_SIGN); *offset += sym_base_addr - loc; if (*offset >= PREL31_UPPER_BOUNDARY || *offset < PREL31_LOWER_BOUNDARY) { @@ -142,6 +144,8 @@ static inline int jumps_decode(elf_word reloc_type, uint32_t loc, { int ret; + ARG_UNUSED(reloc_type); + *offset = MEM2ARMOPCODE(*(uint32_t *)loc); *offset = (*offset & MASK_BRANCH_OFFSET) << SHIFT_BRANCH_OFFSET; *offset = sign_extend(*offset, SHIFT_JUMPS_SIGN); @@ -211,6 +215,8 @@ static inline int thm_jumps_decode(elf_word reloc_type, uint32_t loc, int ret; uint32_t j_one, j_two, sign; + ARG_UNUSED(reloc_type); + *upper = MEM2THM16OPCODE(*(uint16_t *)loc); *lower = MEM2THM16OPCODE(*(uint16_t *)(loc + 2)); diff --git a/arch/arm/core/fatal.c b/arch/arm/core/fatal.c index d64855b6b8e..78b3b5b5090 100644 --- a/arch/arm/core/fatal.c +++ b/arch/arm/core/fatal.c @@ -13,6 +13,7 @@ */ #include +#include #include #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -20,14 +21,14 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #ifdef CONFIG_EXCEPTION_DEBUG static void esf_dump(const struct arch_esf *esf) { - LOG_ERR("r0/a1: 0x%08x r1/a2: 0x%08x r2/a3: 0x%08x", + EXCEPTION_DUMP("r0/a1: 0x%08x r1/a2: 0x%08x r2/a3: 0x%08x", esf->basic.a1, esf->basic.a2, esf->basic.a3); - LOG_ERR("r3/a4: 0x%08x r12/ip: 0x%08x r14/lr: 0x%08x", + EXCEPTION_DUMP("r3/a4: 0x%08x r12/ip: 0x%08x r14/lr: 0x%08x", esf->basic.a4, esf->basic.ip, esf->basic.lr); - LOG_ERR(" xpsr: 0x%08x", esf->basic.xpsr); + EXCEPTION_DUMP(" xpsr: 0x%08x", esf->basic.xpsr); #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) for (int i = 0; i < ARRAY_SIZE(esf->fpu.s); i += 4) { - LOG_ERR("s[%2d]: 0x%08x s[%2d]: 0x%08x" + EXCEPTION_DUMP("s[%2d]: 0x%08x s[%2d]: 0x%08x" " s[%2d]: 0x%08x s[%2d]: 0x%08x", i, (uint32_t)esf->fpu.s[i], i + 1, (uint32_t)esf->fpu.s[i + 1], @@ -36,7 +37,7 @@ static void esf_dump(const struct arch_esf *esf) } #ifdef CONFIG_VFP_FEATURE_REGS_S64_D32 for (int i = 0; i < ARRAY_SIZE(esf->fpu.d); i += 4) { - LOG_ERR("d[%2d]: 0x%16llx d[%2d]: 0x%16llx" + EXCEPTION_DUMP("d[%2d]: 0x%16llx d[%2d]: 0x%16llx" " d[%2d]: 0x%16llx d[%2d]: 0x%16llx", i, (uint64_t)esf->fpu.d[i], i + 1, (uint64_t)esf->fpu.d[i + 1], @@ -44,24 +45,24 @@ static void esf_dump(const struct arch_esf *esf) i + 3, (uint64_t)esf->fpu.d[i + 3]); } #endif - LOG_ERR("fpscr: 0x%08x", esf->fpu.fpscr); + EXCEPTION_DUMP("fpscr: 0x%08x", esf->fpu.fpscr); #endif #if defined(CONFIG_EXTRA_EXCEPTION_INFO) const struct _callee_saved *callee = esf->extra_info.callee; if (callee != NULL) { - LOG_ERR("r4/v1: 0x%08x r5/v2: 0x%08x r6/v3: 0x%08x", + EXCEPTION_DUMP("r4/v1: 0x%08x r5/v2: 0x%08x r6/v3: 0x%08x", callee->v1, callee->v2, callee->v3); - LOG_ERR("r7/v4: 0x%08x r8/v5: 0x%08x r9/v6: 0x%08x", + EXCEPTION_DUMP("r7/v4: 0x%08x r8/v5: 0x%08x r9/v6: 0x%08x", callee->v4, callee->v5, callee->v6); - LOG_ERR("r10/v7: 0x%08x r11/v8: 0x%08x psp: 0x%08x", + EXCEPTION_DUMP("r10/v7: 0x%08x r11/v8: 0x%08x psp: 0x%08x", callee->v7, callee->v8, callee->psp); } - LOG_ERR("EXC_RETURN: 0x%0x", esf->extra_info.exc_return); + EXCEPTION_DUMP("EXC_RETURN: 0x%0x", esf->extra_info.exc_return); #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ - LOG_ERR("Faulting instruction address (r15/pc): 0x%08x", + EXCEPTION_DUMP("Faulting instruction address (r15/pc): 0x%08x", esf->basic.pc); } #endif /* CONFIG_EXCEPTION_DEBUG */ @@ -79,7 +80,7 @@ void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf) if (reason == K_ERR_SPURIOUS_IRQ) { uint32_t irqn = __get_IPSR() - 16; - LOG_ERR("Unhandled IRQn: %d", irqn); + EXCEPTION_DUMP("Unhandled IRQn: %d", irqn); } #endif diff --git a/arch/arm/core/mpu/arm_mpu.c b/arch/arm/core/mpu/arm_mpu.c index f9a5397da46..03fa079f81d 100644 --- a/arch/arm/core/mpu/arm_mpu.c +++ b/arch/arm/core/mpu/arm_mpu.c @@ -14,11 +14,18 @@ #include #include #include +#include #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL #include LOG_MODULE_DECLARE(mpu); +#if Z_ARM_CPU_HAS_PMSAV8_MPU +#define ATTRIBUTE_AND_SIZE_REG_NAME RLAR +#else +#define ATTRIBUTE_AND_SIZE_REG_NAME RASR +#endif + #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) /* The order here is on purpose since ARMv8-M SoCs may define * CONFIG_ARMV6_M_ARMV8_M_BASELINE or CONFIG_ARMV7_M_ARMV8_M_MAINLINE @@ -62,6 +69,7 @@ static uint8_t static_regions_num; #include "arm_mpu_v7_internal.h" #elif defined(CONFIG_CPU_CORTEX_M23) || \ defined(CONFIG_CPU_CORTEX_M33) || \ + defined(CONFIG_CPU_CORTEX_M52) || \ defined(CONFIG_CPU_CORTEX_M55) || \ defined(CONFIG_CPU_CORTEX_M85) || \ defined(CONFIG_AARCH32_ARMV8_R) @@ -407,6 +415,72 @@ void arm_core_mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition } } +#if defined(CONFIG_CPU_CORTEX_M) +/** + * @brief Save the current MPU configuration into the provided context struct. + */ +void z_arm_save_mpu_context(struct z_mpu_context_retained *ctx) +{ + uint32_t regions = get_num_regions(); + + __ASSERT_NO_MSG(ctx != NULL); + + if (regions == 0 || regions > Z_ARM_MPU_MAX_REGIONS) { + LOG_DBG("Invalid MPU region count: %u", regions); + ctx->num_valid_regions = 0; + return; + } + + ctx->num_valid_regions = regions; + + for (uint32_t i = 0; i < regions; i++) { + MPU->RNR = i; + __DSB(); /* Ensure MPU->RNR write completes before reading registers */ + __ISB(); + ctx->rbar[i] = MPU->RBAR; + ctx->rasr_rlar[i] = MPU->ATTRIBUTE_AND_SIZE_REG_NAME; + } +#if Z_ARM_CPU_HAS_PMSAV8_MPU + ctx->mair[0] = MPU->MAIR0; + ctx->mair[1] = MPU->MAIR1; +#endif + ctx->ctrl = MPU->CTRL; +} + +/** + * @brief Restore the MPU configuration from the provided context struct. + */ +void z_arm_restore_mpu_context(const struct z_mpu_context_retained *ctx) +{ + __ASSERT_NO_MSG(ctx != NULL); + + if (ctx->num_valid_regions == 0 || ctx->num_valid_regions > Z_ARM_MPU_MAX_REGIONS) { + LOG_DBG("Invalid MPU context num_valid_regions: %u", ctx->num_valid_regions); + return; + } + + /* Disable MPU before reprogramming */ + arm_core_mpu_disable(); + + for (uint32_t i = 0; i < ctx->num_valid_regions; i++) { + MPU->RNR = i; + MPU->RBAR = ctx->rbar[i]; + MPU->ATTRIBUTE_AND_SIZE_REG_NAME = ctx->rasr_rlar[i]; + } + +#if Z_ARM_CPU_HAS_PMSAV8_MPU + MPU->MAIR0 = ctx->mair[0]; + MPU->MAIR1 = ctx->mair[1]; +#endif + /* Restore MPU control register (including enable bit if set) */ + MPU->CTRL = ctx->ctrl; + + /* Ensure MPU settings take effect before continuing */ + __DSB(); + __ISB(); +} +#endif /* CONFIG_CPU_CORTEX_M */ + /* ARM MPU Driver Initial Setup */ /* diff --git a/arch/arm/core/mpu/arm_mpu_v8_internal.h b/arch/arm/core/mpu/arm_mpu_v8_internal.h index 0716c017ff9..2ce810047e1 100644 --- a/arch/arm/core/mpu/arm_mpu_v8_internal.h +++ b/arch/arm/core/mpu/arm_mpu_v8_internal.h @@ -32,7 +32,8 @@ struct dynamic_region_info { */ static struct dynamic_region_info dyn_reg_info[MPU_DYNAMIC_REGION_AREAS_NUM]; #if defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) || \ - defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85) + defined(CONFIG_CPU_CORTEX_M52) || defined(CONFIG_CPU_CORTEX_M55) || \ + defined(CONFIG_CPU_CORTEX_M85) static inline void mpu_set_mair0(uint32_t mair0) { MPU->MAIR0 = mair0; diff --git a/arch/arm/include/cortex_a_r/exception.h b/arch/arm/include/cortex_a_r/exception.h index 4326444f112..6103bb78620 100644 --- a/arch/arm/include/cortex_a_r/exception.h +++ b/arch/arm/include/cortex_a_r/exception.h @@ -32,15 +32,24 @@ extern "C" { extern volatile irq_offload_routine_t offload_routine; #endif -/* Check the CPSR mode bits to see if we are in IRQ or FIQ mode */ static ALWAYS_INLINE bool arch_is_in_isr(void) { - return (arch_curr_cpu()->nested != 0U); + uint32_t nested; +#ifdef CONFIG_SMP + unsigned int key; + + key = arch_irq_lock(); +#endif + nested = arch_curr_cpu()->nested; +#ifdef CONFIG_SMP + arch_irq_unlock(key); +#endif + return nested != 0U; } static ALWAYS_INLINE bool arch_is_in_nested_exception(const struct arch_esf *esf) { - return (arch_curr_cpu()->arch.exc_depth > 1U) ? (true) : (false); + return (_current_cpu->arch.exc_depth > 1U) ? (true) : (false); } /** diff --git a/arch/arm/include/cortex_m/debug.h b/arch/arm/include/cortex_m/debug.h new file mode 100644 index 00000000000..3950519fd0b --- /dev/null +++ b/arch/arm/include/cortex_m/debug.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief ARM Cortex-M debug monitor functions interface based on DWT + * + */ + +#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_DEBUG_H_ +#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_DEBUG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Assess whether a debug monitor event should be treated as an error + * + * This routine checks the status of a debug_monitor() exception, and + * evaluates whether this needs to be considered as a processor error. + * + * @return true if the DM exception is a processor error, otherwise false + */ +bool z_arm_debug_monitor_event_error_check(void); + +int z_arm_debug_enable_null_pointer_detection(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_DEBUG_H_ */ diff --git a/arch/arm/include/cortex_m/dwt.h b/arch/arm/include/cortex_m/dwt.h index fe946ecb590..97a56b2df5b 100644 --- a/arch/arm/include/cortex_m/dwt.h +++ b/arch/arm/include/cortex_m/dwt.h @@ -36,14 +36,11 @@ extern "C" { * update to CMSIS_6. */ #if !defined DWT_LSR_Present_Msk -#define DWT_LSR_Present_Msk \ - IF_ENABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_Present_Msk)) \ - IF_DISABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_PRESENT_Msk)) +#define DWT_LSR_Present_Msk ITM_LSR_PRESENT_Msk #endif + #if !defined DWT_LSR_Access_Msk -#define DWT_LSR_Access_Msk \ - IF_ENABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_Access_Msk)) \ - IF_DISABLED(CONFIG_ZEPHYR_CMSIS_MODULE, (ITM_LSR_ACCESS_Msk)) +#define DWT_LSR_Access_Msk ITM_LSR_ACCESS_Msk #endif static inline void dwt_access(bool ena) diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h index cbac2724587..02408c5cef1 100644 --- a/arch/arm/include/cortex_m/exception.h +++ b/arch/arm/include/cortex_m/exception.h @@ -261,16 +261,6 @@ static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_ #endif /* CONFIG_DEBUG_COREDUMP */ } -/** - * @brief Assess whether a debug monitor event should be treated as an error - * - * This routine checks the status of a debug_monitor() exception, and - * evaluates whether this needs to be considered as a processor error. - * - * @return true if the DM exception is a processor error, otherwise false - */ -bool z_arm_debug_monitor_event_error_check(void); - #ifdef __cplusplus } #endif diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig index 21327f62c1b..57d87e016f1 100644 --- a/arch/arm64/core/Kconfig +++ b/arch/arm64/core/Kconfig @@ -357,4 +357,20 @@ config MAX_XLAT_TABLES endif # ARM_MMU +config ARM64_DCACHE_ALL_OPS + bool "Provide data cache APIs to operate all data caches" + depends on CACHE_MANAGEMENT && DCACHE + help + Enable this option to provide the data cache APIs to flush or + invalidate all data caches. + +config ARM64_BOOT_DISABLE_DCACHE + bool "Disable data cache before enable MMU when booting from EL2" + depends on ARM64_DCACHE_ALL_OPS + help + To make it safe, if data cache is enabled in case of Zephyr is booting + from EL2, enable this option, it will clean and invalidate all data + cache and then disable data cache, it will will be re-enabled after + MMU is configured and enabled. + endif # CPU_CORTEX_A || CPU_AARCH64_CORTEX_R diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c index cb5f485c0d5..cca65252021 100644 --- a/arch/arm64/core/fatal.c +++ b/arch/arm64/core/fatal.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "paging.h" @@ -179,24 +180,24 @@ static void dump_esr(uint64_t esr, bool *dump_far) err = "Unknown"; } - LOG_ERR("ESR_ELn: 0x%016llx", esr); - LOG_ERR(" EC: 0x%llx (%s)", GET_ESR_EC(esr), err); - LOG_ERR(" IL: 0x%llx", GET_ESR_IL(esr)); - LOG_ERR(" ISS: 0x%llx", GET_ESR_ISS(esr)); + EXCEPTION_DUMP("ESR_ELn: 0x%016llx", esr); + EXCEPTION_DUMP(" EC: 0x%llx (%s)", GET_ESR_EC(esr), err); + EXCEPTION_DUMP(" IL: 0x%llx", GET_ESR_IL(esr)); + EXCEPTION_DUMP(" ISS: 0x%llx", GET_ESR_ISS(esr)); } static void esf_dump(const struct arch_esf *esf) { - LOG_ERR("x0: 0x%016llx x1: 0x%016llx", esf->x0, esf->x1); - LOG_ERR("x2: 0x%016llx x3: 0x%016llx", esf->x2, esf->x3); - LOG_ERR("x4: 0x%016llx x5: 0x%016llx", esf->x4, esf->x5); - LOG_ERR("x6: 0x%016llx x7: 0x%016llx", esf->x6, esf->x7); - LOG_ERR("x8: 0x%016llx x9: 0x%016llx", esf->x8, esf->x9); - LOG_ERR("x10: 0x%016llx x11: 0x%016llx", esf->x10, esf->x11); - LOG_ERR("x12: 0x%016llx x13: 0x%016llx", esf->x12, esf->x13); - LOG_ERR("x14: 0x%016llx x15: 0x%016llx", esf->x14, esf->x15); - LOG_ERR("x16: 0x%016llx x17: 0x%016llx", esf->x16, esf->x17); - LOG_ERR("x18: 0x%016llx lr: 0x%016llx", esf->x18, esf->lr); + EXCEPTION_DUMP("x0: 0x%016llx x1: 0x%016llx", esf->x0, esf->x1); + EXCEPTION_DUMP("x2: 0x%016llx x3: 0x%016llx", esf->x2, esf->x3); + EXCEPTION_DUMP("x4: 0x%016llx x5: 0x%016llx", esf->x4, esf->x5); + EXCEPTION_DUMP("x6: 0x%016llx x7: 0x%016llx", esf->x6, esf->x7); + EXCEPTION_DUMP("x8: 0x%016llx x9: 0x%016llx", esf->x8, esf->x9); + EXCEPTION_DUMP("x10: 0x%016llx x11: 0x%016llx", esf->x10, esf->x11); + EXCEPTION_DUMP("x12: 0x%016llx x13: 0x%016llx", esf->x12, esf->x13); + EXCEPTION_DUMP("x14: 0x%016llx x15: 0x%016llx", esf->x14, esf->x15); + EXCEPTION_DUMP("x16: 0x%016llx x17: 0x%016llx", esf->x16, esf->x17); + EXCEPTION_DUMP("x18: 0x%016llx lr: 0x%016llx", esf->x18, esf->lr); } #endif /* CONFIG_EXCEPTION_DEBUG */ @@ -298,10 +299,11 @@ static bool print_trace_address(void *arg, unsigned long lr, void *fp) uint32_t offset = 0; const char *name = symtab_find_symbol_name(lr, &offset); - LOG_ERR(" %d: fp: 0x%016llx lr: 0x%016lx [%s+0x%x]", (*i)++, (uint64_t)fp, lr, name, - offset); + EXCEPTION_DUMP(" %d: fp: 0x%016llx lr: 0x%016lx [%s+0x%x]", + (*i)++, (uint64_t)fp, lr, name, offset); #else - LOG_ERR(" %d: fp: 0x%016llx lr: 0x%016lx", (*i)++, (uint64_t)fp, lr); + EXCEPTION_DUMP(" %d: fp: 0x%016llx lr: 0x%016lx", + (*i)++, (uint64_t)fp, lr); #endif /* CONFIG_SYMTAB */ return true; @@ -311,10 +313,10 @@ static void esf_unwind(const struct arch_esf *esf) { int i = 0; - LOG_ERR(""); - LOG_ERR("call trace:"); + EXCEPTION_DUMP(""); + EXCEPTION_DUMP("call trace:"); walk_stackframe(print_trace_address, &i, esf, CONFIG_ARCH_STACKWALK_MAX_FRAMES); - LOG_ERR(""); + EXCEPTION_DUMP(""); } #endif /* CONFIG_EXCEPTION_STACK_TRACE */ @@ -338,7 +340,8 @@ static bool z_arm64_stack_corruption_check(struct arch_esf *esf, uint64_t esr, u write_cpacr_el1(read_cpacr_el1() | CPACR_EL1_FPEN_NOTRAP); #endif arch_curr_cpu()->arch.corrupted_sp = 0UL; - LOG_ERR("STACK OVERFLOW FROM KERNEL, SP: 0x%llx OR FAR: 0x%llx INVALID," + EXCEPTION_DUMP("STACK OVERFLOW FROM KERNEL," + " SP: 0x%llx OR FAR: 0x%llx INVALID," " SP LIMIT: 0x%llx", sp, far, sp_limit); return true; } @@ -349,8 +352,9 @@ static bool z_arm64_stack_corruption_check(struct arch_esf *esf, uint64_t esr, u guard_start = sp_limit - Z_ARM64_STACK_GUARD_SIZE; sp = esf->sp; if (sp <= sp_limit || (guard_start <= far && far <= sp_limit)) { - LOG_ERR("STACK OVERFLOW FROM USERSPACE, SP: 0x%llx OR FAR: 0x%llx INVALID," - " SP LIMIT: 0x%llx", sp, far, sp_limit); + EXCEPTION_DUMP("STACK OVERFLOW FROM USERSPACE," + "SP: 0x%llx OR FAR: 0x%llx INVALID," + " SP LIMIT: 0x%llx", sp, far, sp_limit); return true; } } @@ -362,6 +366,10 @@ static bool z_arm64_stack_corruption_check(struct arch_esf *esf, uint64_t esr, u static bool is_recoverable(struct arch_esf *esf, uint64_t esr, uint64_t far, uint64_t elr) { + ARG_UNUSED(esr); + ARG_UNUSED(far); + ARG_UNUSED(elr); + if (!esf) { return false; } @@ -423,15 +431,15 @@ void z_arm64_fatal_error(unsigned int reason, struct arch_esf *esf) #ifdef CONFIG_EXCEPTION_DEBUG bool dump_far = false; - LOG_ERR("ELR_ELn: 0x%016llx", elr); + EXCEPTION_DUMP("ELR_ELn: 0x%016llx", elr); dump_esr(esr, &dump_far); if (dump_far) { - LOG_ERR("FAR_ELn: 0x%016llx", far); + EXCEPTION_DUMP("FAR_ELn: 0x%016llx", far); } - LOG_ERR("TPIDRRO: 0x%016llx", read_tpidrro_el0()); + EXCEPTION_DUMP("TPIDRRO: 0x%016llx", read_tpidrro_el0()); #endif /* CONFIG_EXCEPTION_DEBUG */ if (is_recoverable(esf, esr, far, elr) && diff --git a/arch/arm64/core/fpu.c b/arch/arm64/core/fpu.c index a585165b943..f6162fa2ab3 100644 --- a/arch/arm64/core/fpu.c +++ b/arch/arm64/core/fpu.c @@ -346,6 +346,8 @@ int arch_float_disable(struct k_thread *thread) int arch_float_enable(struct k_thread *thread, unsigned int options) { + ARG_UNUSED(thread); + ARG_UNUSED(options); /* floats always gets enabled automatically at the moment */ return 0; } diff --git a/arch/arm64/core/isr_wrapper.S b/arch/arm64/core/isr_wrapper.S index 809762f27f9..a54e88ddc71 100644 --- a/arch/arm64/core/isr_wrapper.S +++ b/arch/arm64/core/isr_wrapper.S @@ -64,6 +64,14 @@ SECTION_FUNC(TEXT, _isr_wrapper) bl z_soc_irq_get_active #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ + /* Preserve original IAR value */ + str x0, [sp, #-16]! + +#if CONFIG_GIC_VER == 2 && defined(CONFIG_SMP) + /* Mask out GICC_IAR.CPUID [12:10] */ + bic x0, x0, #0x1c00 +#endif + #if CONFIG_GIC_VER >= 3 /* * Ignore Special INTIDs 1020..1023 see 2.2.1 of Arm Generic Interrupt Controller @@ -82,8 +90,6 @@ oob: cmp x0, x1 b.hi spurious_continue - stp x0, xzr, [sp, #-16]! - /* Retrieve the interrupt service routine */ ldr x1, =_sw_isr_table add x1, x1, x0, lsl #4 /* table is 16-byte wide */ @@ -97,10 +103,12 @@ oob: blr x3 msr daifset, #(DAIFSET_IRQ_BIT) - /* Signal end-of-interrupt */ - ldp x0, xzr, [sp], #16 - spurious_continue: + + /* Retrieve original IAR value */ + ldr x0, [sp], #16 + + /* Signal end-of-interrupt */ #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) bl arm_gic_eoi #else diff --git a/arch/arm64/core/macro_priv.inc b/arch/arm64/core/macro_priv.inc index 22cefe235fe..00adcdc8383 100644 --- a/arch/arm64/core/macro_priv.inc +++ b/arch/arm64/core/macro_priv.inc @@ -25,7 +25,7 @@ * Get CPU logic id by looking up cpu_node_list * returns * xreg0: MPID - * xreg1: logic id (0 ~ CONFIG_MP_MAX_NUM_CPUS - 1) + * xreg1: logic id (0 ~ DT_CHILD_NUM_STATUS_OKAY(DT_PATH(cpus)) - 1) * clobbers: xreg0, xreg1, xreg2, xreg3 */ .macro get_cpu_logic_id xreg0, xreg1, xreg2, xreg3 @@ -36,7 +36,7 @@ cmp \xreg2, \xreg0 beq 2f add \xreg1, \xreg1, 1 - cmp \xreg1, #CONFIG_MP_MAX_NUM_CPUS + cmp \xreg1, #DT_CHILD_NUM_STATUS_OKAY(DT_PATH(cpus)) bne 1b b . 2: diff --git a/arch/arm64/core/reset.S b/arch/arm64/core/reset.S index 235156f9a1c..929e986019e 100644 --- a/arch/arm64/core/reset.S +++ b/arch/arm64/core/reset.S @@ -8,6 +8,7 @@ #include #include #include +#include #include "boot.h" #include "macro_priv.inc" @@ -58,10 +59,9 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c) b out #endif /* CONFIG_ARMV8_R */ 2: - /* Disable alignment fault checking, disable D-Cache, I-Cache, MMU for safety */ + /* Disable alignment fault checking */ mrs x0, sctlr_el2 - mov x1, #(SCTLR_A_BIT | SCTLR_C_BIT | SCTLR_M_BIT | SCTLR_I_BIT) - bic x0, x0, x1 + bic x0, x0, SCTLR_A_BIT msr sctlr_el2, x0 isb @@ -164,7 +164,7 @@ resetwait: /* wait */ bne 2b add x5, x5, #1 - cmp x5, #CONFIG_MP_MAX_NUM_CPUS + cmp x5, #DT_CHILD_NUM_STATUS_OKAY(DT_PATH(cpus)) bne 2b diff --git a/arch/arm64/core/reset.c b/arch/arm64/core/reset.c index 03cf389007d..48ff0e29f79 100644 --- a/arch/arm64/core/reset.c +++ b/arch/arm64/core/reset.c @@ -5,6 +5,7 @@ */ #include +#include #include #include "boot.h" @@ -122,6 +123,21 @@ void z_arm64_el2_init(void) uint64_t reg; reg = read_sctlr_el2(); +#ifdef CONFIG_ARM64_BOOT_DISABLE_DCACHE + /* Disable D-Cache if it is enabled, it will re-enabled when MMU is enabled at EL1 */ + if (reg & SCTLR_C_BIT) { + /* Clean and invalidate the data cache before disabling it to ensure memory + * remains coherent. + */ + arch_dcache_flush_and_invd_all(); + barrier_isync_fence_full(); + /* Disable D-Cache and MMU for EL2 */ + reg &= ~(SCTLR_C_BIT | SCTLR_M_BIT); + write_sctlr_el2(reg); + /* Invalidate TLB entries */ + __asm__ volatile("dsb ishst; tlbi alle2; dsb ish; isb" : : : "memory"); + } +#endif reg |= (SCTLR_EL2_RES1 | /* RES1 */ SCTLR_I_BIT | /* Enable i-cache */ SCTLR_SA_BIT); /* Enable SP alignment check */ diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index fd9d457ea7d..c09ddd33616 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -37,7 +37,7 @@ struct boot_params { uint64_t mpid; char *sp; - uint8_t voting[CONFIG_MP_MAX_NUM_CPUS]; + uint8_t voting[DT_CHILD_NUM_STATUS_OKAY(DT_PATH(cpus))]; arch_cpustart_t fn; void *arg; int cpu_num; @@ -56,6 +56,8 @@ const uint64_t cpu_node_list[] = { DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), DT_REG_ADDR, (,)) }; +BUILD_ASSERT(ARRAY_SIZE(cpu_node_list) == DT_CHILD_NUM_STATUS_OKAY(DT_PATH(cpus))); + /* cpu_map saves the maping of core id and mpid */ static uint64_t cpu_map[CONFIG_MP_MAX_NUM_CPUS] = { [0 ... (CONFIG_MP_MAX_NUM_CPUS - 1)] = INV_MPID @@ -70,11 +72,11 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, int cpu_count; static int i; uint64_t cpu_mpid = 0; - uint64_t master_core_mpid; + uint64_t primary_core_mpid; - /* Now it is on master core */ + /* Now it is on primary core */ __ASSERT(arch_curr_cpu()->id == 0, ""); - master_core_mpid = MPIDR_TO_CORE(GET_MPIDR()); + primary_core_mpid = MPIDR_TO_CORE(GET_MPIDR()); cpu_count = ARRAY_SIZE(cpu_node_list); @@ -92,7 +94,7 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arm64_cpu_boot_params.cpu_num = cpu_num; for (; i < cpu_count; i++) { - if (cpu_node_list[i] == master_core_mpid) { + if (cpu_node_list[i] == primary_core_mpid) { continue; } diff --git a/arch/arm64/core/thread.c b/arch/arm64/core/thread.c index c48672a5f07..3d93eb4b824 100644 --- a/arch/arm64/core/thread.c +++ b/arch/arm64/core/thread.c @@ -199,3 +199,12 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, CODE_UNREACHABLE; } #endif + +int arch_coprocessors_disable(struct k_thread *thread) +{ +#if defined(CONFIG_FPU_SHARING) + return arch_float_disable(thread); +#else + return -ENOTSUP; +#endif +} diff --git a/arch/arm64/include/exception.h b/arch/arm64/include/exception.h index 6ab6bbbfeff..04f92b8818e 100644 --- a/arch/arm64/include/exception.h +++ b/arch/arm64/include/exception.h @@ -28,7 +28,17 @@ extern "C" { static ALWAYS_INLINE bool arch_is_in_isr(void) { - return arch_curr_cpu()->nested != 0U; + uint32_t nested; +#ifdef CONFIG_SMP + unsigned int key; + + key = arch_irq_lock(); +#endif + nested = arch_curr_cpu()->nested; +#ifdef CONFIG_SMP + arch_irq_unlock(key); +#endif + return nested != 0U; } #ifdef __cplusplus diff --git a/arch/common/CMakeLists.txt b/arch/common/CMakeLists.txt index 6f84bb96351..6f1042b0050 100644 --- a/arch/common/CMakeLists.txt +++ b/arch/common/CMakeLists.txt @@ -83,8 +83,7 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY nocache.ld ) -# Only ARM, X86 and RISCV use ROM_START_OFFSET. -if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64 OR DEFINED CONFIG_RISCV) +if (DEFINED CONFIG_ARCH_SUPPORTS_ROM_OFFSET) # Exclamation mark is printable character with lowest number in ASCII table. # We are sure that this file will be included as a first. zephyr_linker_sources(ROM_START SORT_KEY ! rom_start_address.ld) diff --git a/arch/common/Kconfig b/arch/common/Kconfig index 1cc91d7c25b..1684b9f16fd 100644 --- a/arch/common/Kconfig +++ b/arch/common/Kconfig @@ -4,15 +4,15 @@ # SPDX-License-Identifier: Apache-2.0 config SEMIHOST - bool "Semihosting support for ARM and RISC-V targets" - depends on ARM || ARM64 || RISCV + bool "Semihosting support for ARM, RISC-V and Xtensa targets" + depends on ARM || ARM64 || RISCV || (XTENSA && !SIMULATOR_XTENSA) help - Semihosting is a mechanism that enables code running on an ARM or - RISC-V target to communicate and use the Input/Output facilities on + Semihosting is a mechanism that enables code running on an ARM, RISC-V + or Xtensa target to communicate and use the Input/Output facilities on a host computer that is running a debugger. Additional information can be found in: https://developer.arm.com/documentation/dui0471/m/what-is-semihosting- - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc + https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc This option is compatible with hardware and with QEMU, through the (automatic) use of the -semihosting-config switch when invoking it. @@ -23,6 +23,14 @@ config ISR_TABLE_SHELL help This option enables a shell command to dump the ISR tables. +config ARCH_SUPPORTS_ROM_OFFSET + bool + default y + depends on (ARM || X86 || ARM64 || RISCV || ARC) + help + Hidden option to enable support for ROM offset within the linker + script, which will place a block of 0x0 of size + CONFIG_ROM_START_OFFSET at the start of the ROM region. config ARM_MPU bool "ARM MPU Support" diff --git a/arch/common/include/semihost_types.h b/arch/common/include/semihost_types.h new file mode 100644 index 00000000000..277b8d83f3d --- /dev/null +++ b/arch/common/include/semihost_types.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022, Commonwealth Scientific and Industrial Research + * Organisation (CSIRO) ABN 41 687 119 230. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ARCH_COMMON_SEMIHOST_TYPES_H_ +#define ZEPHYR_INCLUDE_ARCH_COMMON_SEMIHOST_TYPES_H_ + +struct semihost_poll_in_args { + long zero; +} __packed; + +struct semihost_open_args { + const char *path; + long mode; + long path_len; +} __packed; + +struct semihost_close_args { + long fd; +} __packed; + +struct semihost_flen_args { + long fd; +} __packed; + +struct semihost_seek_args { + long fd; + long offset; +} __packed; + +struct semihost_read_args { + long fd; + char *buf; + long len; +} __packed; + +struct semihost_write_args { + long fd; + const char *buf; + long len; +} __packed; + +#endif /* ZEPHYR_INCLUDE_ARCH_COMMON_SEMIHOST_TYPES_H_ */ diff --git a/arch/common/isr_tables.c b/arch/common/isr_tables.c index 183f80738fe..ea9ac3331a8 100644 --- a/arch/common/isr_tables.c +++ b/arch/common/isr_tables.c @@ -78,7 +78,7 @@ void __irq_vector_table __attribute__((naked)) _irq_vector_table(void) { #else /* The IRQ vector table is an array of vector addresses */ -uintptr_t __irq_vector_table _irq_vector_table[IRQ_TABLE_SIZE] = { +const uintptr_t __irq_vector_table _irq_vector_table[IRQ_TABLE_SIZE] = { [0 ...(IRQ_TABLE_SIZE - 1)] = (uintptr_t)&IRQ_VECTOR_TABLE_DEFAULT_ISR, }; #endif /* CONFIG_IRQ_VECTOR_TABLE_JUMP_BY_CODE */ @@ -88,6 +88,9 @@ uintptr_t __irq_vector_table _irq_vector_table[IRQ_TABLE_SIZE] = { * type and bypass the _sw_isr_table, then do not generate one. */ #ifdef CONFIG_GEN_SW_ISR_TABLE +#ifndef CONFIG_DYNAMIC_INTERRUPTS +const +#endif struct _isr_table_entry __sw_isr_table _sw_isr_table[IRQ_TABLE_SIZE] = { [0 ...(IRQ_TABLE_SIZE - 1)] = {(const void *)0x42, &z_irq_spurious}, @@ -95,6 +98,9 @@ struct _isr_table_entry __sw_isr_table _sw_isr_table[IRQ_TABLE_SIZE] = { #endif #ifdef CONFIG_SHARED_INTERRUPTS +#ifndef CONFIG_DYNAMIC_INTERRUPTS +const +#endif struct z_shared_isr_table_entry __shared_sw_isr_table z_shared_sw_isr_table[IRQ_TABLE_SIZE] = { }; #endif diff --git a/arch/common/isr_tables_shell.c b/arch/common/isr_tables_shell.c index 232878f2b29..272872a287c 100644 --- a/arch/common/isr_tables_shell.c +++ b/arch/common/isr_tables_shell.c @@ -8,7 +8,8 @@ #include #include -static void dump_isr_table_entry(const struct shell *sh, int idx, struct _isr_table_entry *entry) +static void dump_isr_table_entry(const struct shell *sh, int idx, + const struct _isr_table_entry *entry) { if ((entry->isr == z_irq_spurious) || (entry->isr == NULL)) { diff --git a/arch/common/semihost.c b/arch/common/semihost.c index f22891c6487..ac25dd29981 100644 --- a/arch/common/semihost.c +++ b/arch/common/semihost.c @@ -8,41 +8,7 @@ #include #include #include - -struct semihost_poll_in_args { - long zero; -} __packed; - -struct semihost_open_args { - const char *path; - long mode; - long path_len; -} __packed; - -struct semihost_close_args { - long fd; -} __packed; - -struct semihost_flen_args { - long fd; -} __packed; - -struct semihost_seek_args { - long fd; - long offset; -} __packed; - -struct semihost_read_args { - long fd; - char *buf; - long len; -} __packed; - -struct semihost_write_args { - long fd; - const char *buf; - long len; -} __packed; +#include "semihost_types.h" char semihost_poll_in(void) { diff --git a/arch/mips/core/fatal.c b/arch/mips/core/fatal.c index aee7a597d4d..a3f70d6d9d6 100644 --- a/arch/mips/core/fatal.c +++ b/arch/mips/core/fatal.c @@ -13,25 +13,25 @@ FUNC_NORETURN void z_mips_fatal_error(unsigned int reason, { #ifdef CONFIG_EXCEPTION_DEBUG if (esf != NULL) { - LOG_ERR("$ 0 : (ze) %08lx(at) %08lx(v0) %08lx(v1)\n", + EXCEPTION_DUMP("$ 0 : (ze) %08lx(at) %08lx(v0) %08lx(v1)\n", esf->at, esf->v0, esf->v1); - LOG_ERR("$ 4 : %08lx(a0) %08lx(a1) %08lx(a2) %08lx(a3)\n", + EXCEPTION_DUMP("$ 4 : %08lx(a0) %08lx(a1) %08lx(a2) %08lx(a3)\n", esf->a0, esf->a1, esf->a2, esf->a3); - LOG_ERR("$ 8 : %08lx(t0) %08lx(t1) %08lx(t2) %08lx(t3)\n", + EXCEPTION_DUMP("$ 8 : %08lx(t0) %08lx(t1) %08lx(t2) %08lx(t3)\n", esf->t0, esf->t1, esf->t2, esf->t3); - LOG_ERR("$12 : %08lx(t4) %08lx(t5) %08lx(t6) %08lx(t7)\n", + EXCEPTION_DUMP("$12 : %08lx(t4) %08lx(t5) %08lx(t6) %08lx(t7)\n", esf->t4, esf->t5, esf->t6, esf->t7); - LOG_ERR("...\n"); - LOG_ERR("$24 : %08lx(t8) %08lx(t9)\n", + EXCEPTION_DUMP("...\n"); + EXCEPTION_DUMP("$24 : %08lx(t8) %08lx(t9)\n", esf->t8, esf->t9); - LOG_ERR("$28 : %08lx(gp) (sp) (s8) %08lx(ra)\n", + EXCEPTION_DUMP("$28 : %08lx(gp) (sp) (s8) %08lx(ra)\n", esf->gp, esf->ra); - LOG_ERR("EPC : %08lx\n", esf->epc); + EXCEPTION_DUMP("EPC : %08lx\n", esf->epc); - LOG_ERR("Status: %08lx\n", esf->status); - LOG_ERR("Cause : %08lx\n", esf->cause); - LOG_ERR("BadVA : %08lx\n", esf->badvaddr); + EXCEPTION_DUMP("Status: %08lx\n", esf->status); + EXCEPTION_DUMP("Cause : %08lx\n", esf->cause); + EXCEPTION_DUMP("BadVA : %08lx\n", esf->badvaddr); } #endif /* CONFIG_EXCEPTION_DEBUG */ z_fatal_error(reason, esf); @@ -90,8 +90,8 @@ void z_mips_fault(struct arch_esf *esf) cause = (read_c0_cause() & CAUSE_EXP_MASK) >> CAUSE_EXP_SHIFT; - LOG_ERR(""); - LOG_ERR(" cause: %ld, %s", cause, cause_str(cause)); + EXCEPTION_DUMP(""); + EXCEPTION_DUMP(" cause: %ld, %s", cause, cause_str(cause)); z_mips_fatal_error(K_ERR_CPU_EXCEPTION, esf); } diff --git a/arch/mips/core/irq_manage.c b/arch/mips/core/irq_manage.c index 73582ab2a19..be3e2ed3604 100644 --- a/arch/mips/core/irq_manage.c +++ b/arch/mips/core/irq_manage.c @@ -70,7 +70,7 @@ void z_mips_enter_irq(uint32_t ipending) while (ipending) { int index; - struct _isr_table_entry *ite; + const struct _isr_table_entry *ite; if (IS_ENABLED(CONFIG_TRACING_ISR)) { sys_trace_isr_enter(); diff --git a/arch/mips/core/thread.c b/arch/mips/core/thread.c index 7966ff462f5..1f2be889c23 100644 --- a/arch/mips/core/thread.c +++ b/arch/mips/core/thread.c @@ -39,3 +39,8 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, thread->callee_saved.sp = (unsigned long)stack_init; } + +int arch_coprocessors_disable(struct k_thread *thread) +{ + return -ENOTSUP; +} diff --git a/arch/posix/CMakeLists.txt b/arch/posix/CMakeLists.txt index 21b6bf7f197..1bd4bf36e40 100644 --- a/arch/posix/CMakeLists.txt +++ b/arch/posix/CMakeLists.txt @@ -71,53 +71,43 @@ zephyr_compile_options( ${ARCH_FLAG} ) -if (CONFIG_NATIVE_APPLICATION) - zephyr_compile_options( - -include ${ZEPHYR_BASE}/arch/posix/include/posix_cheats.h - ) - # About this -include directive: The reason to do it this way, is because in this - # manner it is transparent to the application. Otherwise posix_cheats.h needs to - # be included in all the applications' files which define main( ), and in any - # app file which uses any of the APIs renamed in that header. -elseif (CONFIG_NATIVE_LIBRARY) - zephyr_compile_options( - -fvisibility=hidden +zephyr_compile_options( + -fvisibility=hidden +) + +# While doing the partial linking of the native library, some symbols will be missing +# which are provided by the native simulator runner +zephyr_ld_options( + -Wl,--unresolved-symbols=ignore-all +) + +if (NOT CONFIG_EXTERNAL_LIBC) + # Get the *compiler* include path, that is where the *compiler* provided headers are (not the + # default libC ones). This includes basic headers like stdint.h, stddef.h or float.h + # We expect something like + # /usr/lib/gcc/x86_64-linux-gnu/12/include or /usr/lib/llvm-14/lib/clang/14.0.0/include + execute_process( + COMMAND ${CMAKE_C_COMPILER} --print-file-name=include/stddef.h + OUTPUT_VARIABLE _OUTPUT + COMMAND_ERROR_IS_FATAL ANY ) + get_filename_component(COMPILER_OWN_INCLUDE_PATH "${_OUTPUT}" DIRECTORY) - # While doing the partial linking of the native library, some symbols will be missing - # which are provided by the native simulator runner - zephyr_ld_options( - -Wl,--unresolved-symbols=ignore-all + # Do not use the C library from this compiler/host, + # but still use the basic compiler headers, + # remove all operating system specific predefined macros, + # no_builtin to avoid the compiler using builtin replacements for std library functions + zephyr_compile_options( + -nostdinc + -isystem ${COMPILER_OWN_INCLUDE_PATH} + "SHELL:-include ${ZEPHYR_BASE}/arch/posix/include/undef_system_defines.h" + $ + $ ) +endif() - if (NOT CONFIG_EXTERNAL_LIBC) - # Get the *compiler* include path, that is where the *compiler* provided headers are (not the - # default libC ones). This includes basic headers like stdint.h, stddef.h or float.h - # We expect something like - # /usr/lib/gcc/x86_64-linux-gnu/12/include or /usr/lib/llvm-14/lib/clang/14.0.0/include - execute_process( - COMMAND ${CMAKE_C_COMPILER} --print-file-name=include/stddef.h - OUTPUT_VARIABLE _OUTPUT - COMMAND_ERROR_IS_FATAL ANY - ) - get_filename_component(COMPILER_OWN_INCLUDE_PATH "${_OUTPUT}" DIRECTORY) - - # Do not use the C library from this compiler/host, - # but still use the basic compiler headers, - # remove all operating system specific predefined macros, - # no_builtin to avoid the compiler using builtin replacements for std library functions - zephyr_compile_options( - -nostdinc - -isystem ${COMPILER_OWN_INCLUDE_PATH} - "SHELL:-include ${ZEPHYR_BASE}/arch/posix/include/undef_system_defines.h" - $ - $ - ) - endif() - - if (CONFIG_COMPILER_WARNINGS_AS_ERRORS) - target_compile_options(native_simulator INTERFACE $) - endif() +if (CONFIG_COMPILER_WARNINGS_AS_ERRORS) + target_compile_options(native_simulator INTERFACE $) endif() if(CONFIG_EXTERNAL_LIBC) @@ -143,13 +133,6 @@ if (CONFIG_GPROF) target_link_options(native_simulator INTERFACE "-pg") endif() -if (CONFIG_NATIVE_APPLICATION) - zephyr_ld_options( - -ldl - -pthread - ) -endif() - # # Support for the LLVM Sanitizer toolchain instrumentation frameworks # (supported by current gcc's as well) @@ -187,9 +170,6 @@ list(JOIN LLVM_SANITIZERS "," LLVM_SANITIZERS_ARG) if(NOT ${LLVM_SANITIZERS_ARG} STREQUAL "") set(LLVM_SANITIZERS_ARG "-fsanitize=${LLVM_SANITIZERS_ARG}") zephyr_compile_options("${LLVM_SANITIZERS_ARG}") - if (CONFIG_NATIVE_APPLICATION) - zephyr_link_libraries("${LLVM_SANITIZERS_ARG}") - endif() target_link_options(native_simulator INTERFACE ${LLVM_SANITIZERS_ARG}) target_compile_options(native_simulator INTERFACE ${LLVM_SANITIZERS_ARG}) diff --git a/arch/posix/core/CMakeLists.txt b/arch/posix/core/CMakeLists.txt index 8c46147bc0a..2abc9361871 100644 --- a/arch/posix/core/CMakeLists.txt +++ b/arch/posix/core/CMakeLists.txt @@ -11,29 +11,9 @@ zephyr_library_sources( ) if(CONFIG_ARCH_POSIX_TRAP_ON_FATAL) - if(CONFIG_NATIVE_LIBRARY) - target_sources(native_simulator INTERFACE fatal_trap.c) - else() - zephyr_library_sources(fatal_trap.c) - endif() + target_sources(native_simulator INTERFACE fatal_trap.c) endif() -if(CONFIG_NATIVE_APPLICATION) - zephyr_include_directories( - nsi_compat/ - ${ZEPHYR_BASE}/scripts/native_simulator/common/src/include/ - ) - zephyr_library_sources( - posix_core_nsi.c - nsi_compat/nsi_compat.c - ${ZEPHYR_BASE}/scripts/native_simulator/common/src/nct.c - ${ZEPHYR_BASE}/scripts/native_simulator/common/src/nce.c - ${ZEPHYR_BASE}/scripts/native_simulator/common/src/nsi_host_trampolines.c - ) - - zephyr_library_compile_definitions(_POSIX_C_SOURCE=200809L _XOPEN_SOURCE=600 _XOPEN_SOURCE_EXTENDED) -else() - zephyr_library_sources( - posix_core_nsi.c - ) -endif() +zephyr_library_sources( + posix_core_nsi.c +) diff --git a/arch/posix/core/nsi_compat/nsi_compat.c b/arch/posix/core/nsi_compat/nsi_compat.c deleted file mode 100644 index eccf419efb1..00000000000 --- a/arch/posix/core/nsi_compat/nsi_compat.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * This module exist to provide a basic compatibility shim - * from Native simulator components into the POSIX architecture. - * - * It is a transitional component, intended to facilitate - * the migration towards the Native simulator. - */ - -#include -#include -#include "posix_board_if.h" - -void nsi_print_error_and_exit(const char *format, ...) -{ - va_list variable_args; - - va_start(variable_args, format); - posix_vprint_error_and_exit(format, variable_args); - va_end(variable_args); -} - -void nsi_print_warning(const char *format, ...) -{ - va_list variable_args; - - va_start(variable_args, format); - posix_vprint_warning(format, variable_args); - va_end(variable_args); -} - -void nsi_print_trace(const char *format, ...) -{ - va_list variable_args; - - va_start(variable_args, format); - posix_vprint_trace(format, variable_args); - va_end(variable_args); -} - -FUNC_NORETURN void nsi_exit(int exit_code) -{ - posix_exit(exit_code); - CODE_UNREACHABLE; -} diff --git a/arch/posix/core/nsi_compat/nsi_compat.h b/arch/posix/core/nsi_compat/nsi_compat.h deleted file mode 100644 index 9537a516342..00000000000 --- a/arch/posix/core/nsi_compat/nsi_compat.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2023 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef ARCH_POSIX_CORE_NSI_COMPAT_H -#define ARCH_POSIX_CORE_NSI_COMPAT_H - -#include "nsi_tracing.h" -#include "nsi_safe_call.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void nsi_exit(int exit_code); - -#ifdef __cplusplus -} -#endif - -#endif /* ARCH_POSIX_CORE_NSI_COMPAT_H */ diff --git a/arch/posix/core/thread.c b/arch/posix/core/thread.c index 050d075fe57..2b0d8d9d850 100644 --- a/arch/posix/core/thread.c +++ b/arch/posix/core/thread.c @@ -115,6 +115,12 @@ int arch_float_enable(struct k_thread *thread, unsigned int options) } #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ +int arch_coprocessors_disable(struct k_thread *thread) +{ + /* Posix does not support coprocessors */ + return -ENOTSUP; +} + #if defined(CONFIG_ARCH_HAS_THREAD_ABORT) void z_impl_k_thread_abort(k_tid_t thread) { diff --git a/arch/posix/include/posix_cheats.h b/arch/posix/include/posix_cheats.h deleted file mode 100644 index fa62dc2a2aa..00000000000 --- a/arch/posix/include/posix_cheats.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2017 Oticon A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Header to be able to compile the Zephyr kernel on top of a POSIX OS via the - * POSIX ARCH - * - * This file is only used in the POSIX ARCH, and not in any other architecture - * - * Most users will be normally unaware of this file existence, unless they have - * a link issue in which their POSIX functions calls are reported in errors (as - * zap_). - * If you do see a link error telling you that zap_something is undefined, it is - * likely that you forgot to select the corresponding Zephyr POSIX API. - * - * This header is included automatically when targeting old POSIX ARCH boards - * based on the CONFIG_NATIVE_APPLICATION architecture. - * It will be included in _all_ Zephyr and application source files - * (it is passed with the option "-include" to the compiler call) - * - * A few files (those which need to access the host OS APIs) will set - * NO_POSIX_CHEATS to avoid including this file. These are typically only - * the POSIX arch private files and some of the drivers meant only for the POSIX - * architecture. - * No file which is meant to run in an embedded target should set - * NO_POSIX_CHEATS - */ - -#if !defined(ZEPHYR_ARCH_POSIX_INCLUDE_POSIX_CHEATS_H_) && !defined(NO_POSIX_CHEATS) -#define ZEPHYR_ARCH_POSIX_INCLUDE_POSIX_CHEATS_H_ - -/* - * Normally main() is the main entry point of a C executable. - * When compiling using CONFIG_NATIVE_APPLICATION, the Zephyr "application" is not the actual - * entry point of the executable but something the Zephyr OS calls during - * boot. - * Therefore we need to rename this application main something else, so - * we free the function name "main" for its normal purpose - */ -#ifndef main -#define main(...) _posix_zephyr_main(__VA_ARGS__) -#endif - -#if defined(__cplusplus) -/* To be able to define main() in C++ code we need to have its prototype - * defined somewhere visibly. Otherwise name mangling will prevent the linker - * from finding it. Zephyr assumes an int main(void) prototype and therefore - * this will be the prototype after renaming: - */ -extern "C" int _posix_zephyr_main(void); -#endif - -#ifdef CONFIG_POSIX_API - -/* - * The defines below in this header exist only to enable the Zephyr POSIX API - * (include/posix/), and applications using it, to be compiled on top of - * the deprecated CONFIG_NATIVE_APPLICATION targets. - * - * Without this header, both the Zephyr POSIX API functions and the equivalent - * host OS functions would have the same name. This would result in the linker - * not picking the correct ones. - * - * Renaming these functions allows the linker to distinguish - * which calls are meant for the Zephyr POSIX API (zap_something), and - * which are meant for the host OS. - * - * The zap_ prefix should be understood as an attempt to namespace them - * into something which is unlikely to collide with other real functions - * (Any unlikely string would have done) - * - * If you want to link an external library together with Zephyr code for a - * CONFIG_NATIVE_APPLICATION based target, where that external library calls into the Zephyr - * POSIX API, you may want to include this header when compiling that library, - * or rename the calls to match the ones in the defines below. - */ - -/* Condition variables */ -#define pthread_cond_init(...) zap_pthread_cond_init(__VA_ARGS__) -#define pthread_cond_destroy(...) zap_pthread_cond_destroy(__VA_ARGS__) -#define pthread_cond_signal(...) zap_pthread_cond_signal(__VA_ARGS__) -#define pthread_cond_broadcast(...) zap_pthread_cond_broadcast(__VA_ARGS__) -#define pthread_cond_wait(...) zap_pthread_cond_wait(__VA_ARGS__) -#define pthread_cond_timedwait(...) zap_pthread_cond_timedwait(__VA_ARGS__) -#define pthread_condattr_init(...) zap_pthread_condattr_init(__VA_ARGS__) -#define pthread_condattr_destroy(...) zap_pthread_condattr_destroy(__VA_ARGS__) - -/* Semaphore */ -#define sem_destroy(...) zap_sem_destroy(__VA_ARGS__) -#define sem_getvalue(...) zap_sem_getvalue(__VA_ARGS__) -#define sem_init(...) zap_sem_init(__VA_ARGS__) -#define sem_post(...) zap_sem_post(__VA_ARGS__) -#define sem_timedwait(...) zap_sem_timedwait(__VA_ARGS__) -#define sem_trywait(...) zap_sem_trywait(__VA_ARGS__) -#define sem_wait(...) zap_sem_wait(__VA_ARGS__) - -/* Mutex */ -#define pthread_mutex_init(...) zap_pthread_mutex_init(__VA_ARGS__) -#define pthread_mutex_destroy(...) zap_pthread_mutex_destroy(__VA_ARGS__) -#define pthread_mutex_lock(...) zap_pthread_mutex_lock(__VA_ARGS__) -#define pthread_mutex_timedlock(...) zap_pthread_mutex_timedlock(__VA_ARGS__) -#define pthread_mutex_trylock(...) zap_pthread_mutex_trylock(__VA_ARGS__) -#define pthread_mutex_unlock(...) zap_pthread_mutex_unlock(__VA_ARGS__) -#define pthread_mutexattr_init(...) zap_pthread_mutexattr_init(__VA_ARGS__) -#define pthread_mutexattr_destroy(...) \ - zap_pthread_mutexattr_destroy(__VA_ARGS__) -/* Barrier */ -#define pthread_barrier_wait(...) zap_pthread_barrier_wait(__VA_ARGS__) -#define pthread_barrier_init(...) zap_pthread_barrier_init(__VA_ARGS__) -#define pthread_barrier_destroy(...) zap_pthread_barrier_destroy(__VA_ARGS__) -#define pthread_barrierattr_init(...) zap_pthread_barrierattr_init(__VA_ARGS__) -#define pthread_barrierattr_destroy(...) \ - zap_pthread_barrierattr_destroy(__VA_ARGS__) - -/* Pthread */ -#define pthread_attr_init(...) zap_pthread_attr_init(__VA_ARGS__) -#define pthread_attr_destroy(...) zap_pthread_attr_destroy(__VA_ARGS__) -#define pthread_attr_getschedparam(...) \ - zap_pthread_attr_getschedparam(__VA_ARGS__) -#define pthread_attr_getstack(...) zap_pthread_attr_getstack(__VA_ARGS__) -#define pthread_attr_getstacksize(...) \ - zap_pthread_attr_getstacksize(__VA_ARGS__) -#define pthread_equal(...) zap_pthread_equal(__VA_ARGS__) -#define pthread_self(...) zap_pthread_self(__VA_ARGS__) -#define pthread_getschedparam(...) zap_pthread_getschedparam(__VA_ARGS__) -#define pthread_once(...) zap_pthread_once(__VA_ARGS__) -#define pthread_exit(...) zap_pthread_exit(__VA_ARGS__) -#define pthread_join(...) zap_pthread_join(__VA_ARGS__) -#define pthread_detach(...) zap_pthread_detach(__VA_ARGS__) -#define pthread_cancel(...) zap_pthread_cancel(__VA_ARGS__) -#define pthread_attr_getdetachstate(...) \ - zap_pthread_attr_getdetachstate(__VA_ARGS__) -#define pthread_attr_setdetachstate(...) \ - zap_pthread_attr_setdetachstate(__VA_ARGS__) -#define pthread_attr_setschedparam(...) \ - zap_pthread_attr_setschedparam(__VA_ARGS__) -#define pthread_attr_setschedpolicy(...)\ - zap_pthread_attr_setschedpolicy(__VA_ARGS__) -#define pthread_attr_getschedpolicy(...)\ - zap_pthread_attr_getschedpolicy(__VA_ARGS__) - -#define pthread_attr_setstack(...) zap_pthread_attr_setstack(__VA_ARGS__) -#define pthread_create(...) zap_pthread_create(__VA_ARGS__) -#define pthread_setcancelstate(...) zap_pthread_setcancelstate(__VA_ARGS__) -#define pthread_setschedparam(...) zap_pthread_setschedparam(__VA_ARGS__) - -/* Scheduler */ -#define sched_yield(...) zap_sched_yield(__VA_ARGS__) -#define sched_get_priority_min(...) zap_sched_get_priority_min(__VA_ARGS__) -#define sched_get_priority_max(...) zap_sched_get_priority_max(__VA_ARGS__) -#define sched_getparam(...) zap_sched_getparam(__VA_ARGS__) -#define sched_getscheduler(...) zap_sched_getscheduler(__VA_ARGS__) - -/* Sleep */ -#define sleep(...) zap_sleep(__VA_ARGS__) -#define usleep(...) zap_usleep(__VA_ARGS__) - -/* Clock */ -#define clock_gettime(...) zap_clock_gettime(__VA_ARGS__) -#define clock_settime(...) zap_clock_settime(__VA_ARGS__) -#define gettimeofday(...) zap_clock_gettimeofday(__VA_ARGS__) - -/* Timer */ -#define timer_create(...) zap_timer_create(__VA_ARGS__) -#define timer_delete(...) zap_timer_delete(__VA_ARGS__) -#define timer_gettime(...) zap_timer_gettime(__VA_ARGS__) -#define timer_settime(...) zap_timer_settime(__VA_ARGS__) - -/* Read/Write lock */ -#define pthread_rwlock_destroy(...) zap_pthread_rwlock_destroy(__VA_ARGS__) -#define pthread_rwlock_init(...) zap_pthread_rwlock_init(__VA_ARGS__) -#define pthread_rwlock_rdlock(...) zap_pthread_rwlock_rdlock(__VA_ARGS__) -#define pthread_rwlock_unlock(...) zap_pthread_rwlock_unlock(__VA_ARGS__) -#define pthread_rwlock_wrlock(...) zap_pthread_rwlock_wrlock(__VA_ARGS__) -#define pthread_rwlockattr_init(...) zap_pthread_rwlockattr_init(__VA_ARGS__) -#define pthread_rwlock_timedrdlock(...)\ - zap_pthread_rwlock_timedrdlock(__VA_ARGS__) -#define pthread_rwlock_timedwrlock(...)\ - zap_pthread_rwlock_timedwrlock(__VA_ARGS__) -#define pthread_rwlock_tryrdlock(...)\ - zap_pthread_rwlock_tryrdlock(__VA_ARGS__) -#define pthread_rwlock_trywrlock(...)\ - zap_pthread_rwlock_trywrlock(__VA_ARGS__) -#define pthread_rwlockattr_destroy(...)\ - zap_pthread_rwlockattr_destroy(__VA_ARGS__) - -/* Pthread key */ -#define pthread_key_create(...) zap_pthread_key_create(__VA_ARGS__) -#define pthread_key_delete(...) zap_pthread_key_delete(__VA_ARGS__) -#define pthread_setspecific(...) zap_pthread_setspecific(__VA_ARGS__) -#define pthread_getspecific(...) zap_pthread_getspecific(__VA_ARGS__) - -/* message queue */ -#define mq_open(...) zap_mq_open(__VA_ARGS__) -#define mq_close(...) zap_mq_close(__VA_ARGS__) -#define mq_unlink(...) zap_mq_unlink(__VA_ARGS__) -#define mq_getattr(...) zap_mq_getattr(__VA_ARGS__) -#define mq_receive(...) zap_mq_receive(__VA_ARGS__) -#define mq_send(...) zap_mq_send(__VA_ARGS__) -#define mq_setattr(...) zap_mq_setattr(__VA_ARGS__) -#define mq_timedreceive(...) zap_mq_timedreceive(__VA_ARGS__) -#define mq_timedsend(...) zap_mq_timedsend(__VA_ARGS__) - -/* File system */ -#define open zap_open -#define close zap_close -#define write zap_write -#define read zap_read -#define lseek zap_lseek -#define opendir zap_opendir -#define closedir zap_closedir -#define readdir zap_readdir -#define rename zap_rename -#define unlink zap_unlink -#define stat zap_stat -#define mkdir zap_mkdir - -/* eventfd */ -#define eventfd zap_eventfd -#define eventfd_read zap_eventfd_read -#define eventfd_write zap_eventfd_write - -#endif /* CONFIG_POSIX_API */ - -#endif /* ZEPHYR_ARCH_POSIX_INCLUDE_POSIX_CHEATS_H_ */ diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7f4f57eb283..1c646937240 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -53,6 +53,34 @@ config RISCV_ALWAYS_SWITCH_THROUGH_ECALL and most people should say n here to minimize context switching overhead. +choice RISCV_CMODEL + prompt "RISC-V Code Model" + default RISCV_CMODEL_LARGE if (SRAM_BASE_ADDRESS > 0xffffffff) || \ + (KERNEL_VM_BASE > 0xffffffff) + default RISCV_CMODEL_MEDANY if 64BIT + default RISCV_CMODEL_MEDLOW + +config RISCV_CMODEL_MEDLOW + bool "Medium-low code model" + help + In medium-low code model (medlow), the program and its statically defined symbols must lie + within a single 2 GiB address range and between absolute addresses -2 GiB and +2 GiB. + +config RISCV_CMODEL_MEDANY + bool "Medium-any code model" + help + In medium-any code model (medany), the program and its statically defined symbols must be + within any single 2 GiB address range. The code generated by this model is + position-independent. + +config RISCV_CMODEL_LARGE + bool "Large code model" + help + In large code model (large), the program and its statically defined symbols have no + restrictions on size and placement. + +endchoice + choice RISCV_SMP_IPI_IMPL prompt "RISC-V SMP IPI implementation" depends on SMP @@ -273,7 +301,7 @@ config RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET default 0 depends on GEN_ISR_TABLES help - On some RISCV platform the first interrupt vectors are primarly + On some RISCV platform the first interrupt vectors are primarily intended for inter-hart interrupt signaling and so retained for that purpose and not available. When this option is set, all the IRQ vectors are shifted by this offset value when installed into the @@ -464,6 +492,26 @@ config ARCH_HAS_STACKWALK Internal config to indicate that the arch_stack_walk() API is implemented and it can be enabled. +config RISCV_NO_MTVAL_ON_FP_TRAP + bool + default y if QEMU_TARGET + help + This implementation does not provide useful information in the mtval + CSR (Machine Trap Value register) when floating-point illegal + instruction exceptions occur. + + The RISC-V specification allows implementations to decide on a + case-by-case basis when mtval contains meaningful values. The spec + states that mtval is "either set to zero or written with + exception-specific information" on traps. However, this + "exception-specific information" may not necessarily be the faulting + instruction value, and implementations have flexibility in what they + provide. + + When this option is enabled, the mtval content cannot be relied upon + to contain the faulting FP instruction, requiring alternative methods + to handle FP exceptions. + rsource "Kconfig.isa" endmenu diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa index 29fc8cf9225..722becfb56d 100644 --- a/arch/riscv/Kconfig.isa +++ b/arch/riscv/Kconfig.isa @@ -34,7 +34,7 @@ config RISCV_ISA_EXT_M config RISCV_ISA_EXT_A bool imply RISCV_ISA_EXT_ZAAMO - imply RISCV_ISA_EXT_ZLRSC + imply RISCV_ISA_EXT_ZALRSC help (A) - Standard Extension for Atomic Instructions @@ -89,6 +89,9 @@ config RISCV_ISA_EXT_Q config RISCV_ISA_EXT_C bool + select RISCV_ISA_EXT_ZCA + select RISCV_ISA_EXT_ZCD if RISCV_ISA_EXT_D + select RISCV_ISA_EXT_ZCF if RISCV_ISA_EXT_F && (RISCV_ISA_RV32I || RISCV_ISA_RV32E) help (C) - Standard Extension for Compressed Instructions @@ -96,6 +99,16 @@ config RISCV_ISA_EXT_C which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations. +config RISCV_ISA_EXT_ZICNTR + bool + depends on RISCV_ISA_EXT_ZICSR + help + (Zicntr) - Standard Extension for Base Counters and Timers + + The Zicntr standard extension comprises the three counters (CYCLE, TIME, and INSTRET), + which have dedicated functions (cycle count, real-time clock and instructions retired, + respectively). + config RISCV_ISA_EXT_ZICSR bool help @@ -120,12 +133,71 @@ config RISCV_ISA_EXT_ZAAMO The Zaamo extension enables support for AMO*.W/D-style instructions. -config RISCV_ISA_EXT_ZLRSC +config RISCV_ISA_EXT_ZALRSC + bool + help + (Zalrsc) - Load-Reserved/Store-Conditional subset of the A extension + + The Zalrsc extension enables support for LR.W/D and SC.W/D-style instructions. + +config RISCV_ISA_EXT_ZCA + bool + help + (Zca) - Zba Extension for Compressed Instructions + + The Zca extension is a subset of the C extension that does not include + the floating-point load and store instructions. + +config RISCV_ISA_EXT_ZCB + bool + depends on RISCV_ISA_EXT_ZCA + help + (Zcb) - Zcb Extension for Simple Compressed Instructions + + The Zcb extension is a set of simple code-size saving instructions + which are easy to implement on all CPUs. + +config RISCV_ISA_EXT_ZCD + bool + depends on RISCV_ISA_EXT_D + depends on RISCV_ISA_EXT_ZCA + help + (Zcd) - Zcd Extension for Double-Precision FP Compressed Instructions + + The Zcd extension consists of compressed double-precision + floating-point load and store instructions. + +config RISCV_ISA_EXT_ZCF + bool + depends on RISCV_ISA_RV32I || RISCV_ISA_RV32E + depends on RISCV_ISA_EXT_F + depends on RISCV_ISA_EXT_ZCA + help + (Zcf) - Zcf Extension for Single-Precision FP Compressed Instructions + + The Zcf extension consists of compressed single-precision + floating-point load and store instructions. + +config RISCV_ISA_EXT_ZCMP + bool + depends on RISCV_ISA_EXT_ZCA + depends on !RISCV_ISA_EXT_ZCD + help + (Zcmp) - Zcmp Extension for Complex Compressed Instructions + + The Zcmp extension consists of complex operations intended for + embedded CPUs. + +config RISCV_ISA_EXT_ZCMT bool + depends on RISCV_ISA_EXT_ZICSR + depends on RISCV_ISA_EXT_ZCA + depends on !RISCV_ISA_EXT_ZCD help - (Zlrsc) - Load-Reserved/Store-Conditional subset of the A extension + (Zcmt) - Zcmt Extension for Compressed Table Jump Instructions - The Zlrsc extension enables support for LR.W/D and SC.W/D-style instructions. + The Zcmt extension consists of compressed table jump instructions for + embedded CPUs. config RISCV_ISA_EXT_ZBA bool diff --git a/arch/riscv/core/CMakeLists.txt b/arch/riscv/core/CMakeLists.txt index 52a748c3247..faf44e48a79 100644 --- a/arch/riscv/core/CMakeLists.txt +++ b/arch/riscv/core/CMakeLists.txt @@ -34,3 +34,11 @@ zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) zephyr_library_sources_ifdef(CONFIG_ARCH_STACKWALK stacktrace.c) zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) + +if(CONFIG_GEN_SW_ISR_TABLE) + if(CONFIG_DYNAMIC_INTERRUPTS) + zephyr_linker_sources(RWDATA swi_tables.ld) + else() + zephyr_linker_sources(RODATA swi_tables.ld) + endif() +endif() diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c index 3bf4e57d874..dfb5e51677f 100644 --- a/arch/riscv/core/fatal.c +++ b/arch/riscv/core/fatal.c @@ -91,52 +91,52 @@ FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const struct arc __asm__ volatile("csrr %0, mcause" : "=r" (mcause)); mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK; - LOG_ERR(""); - LOG_ERR(" mcause: %ld, %s", mcause, z_riscv_mcause_str(mcause)); + EXCEPTION_DUMP(""); + EXCEPTION_DUMP(" mcause: %ld, %s", mcause, z_riscv_mcause_str(mcause)); #ifndef CONFIG_SOC_OPENISA_RV32M1 unsigned long mtval; __asm__ volatile("csrr %0, mtval" : "=r" (mtval)); - LOG_ERR(" mtval: %lx", mtval); + EXCEPTION_DUMP(" mtval: %lx", mtval); #endif /* CONFIG_SOC_OPENISA_RV32M1 */ #ifdef CONFIG_EXCEPTION_DEBUG if (esf != NULL) { - LOG_ERR(" a0: " PR_REG " t0: " PR_REG, esf->a0, esf->t0); - LOG_ERR(" a1: " PR_REG " t1: " PR_REG, esf->a1, esf->t1); - LOG_ERR(" a2: " PR_REG " t2: " PR_REG, esf->a2, esf->t2); + EXCEPTION_DUMP(" a0: " PR_REG " t0: " PR_REG, esf->a0, esf->t0); + EXCEPTION_DUMP(" a1: " PR_REG " t1: " PR_REG, esf->a1, esf->t1); + EXCEPTION_DUMP(" a2: " PR_REG " t2: " PR_REG, esf->a2, esf->t2); #if defined(CONFIG_RISCV_ISA_RV32E) - LOG_ERR(" a3: " PR_REG, esf->a3); - LOG_ERR(" a4: " PR_REG, esf->a4); - LOG_ERR(" a5: " PR_REG, esf->a5); + EXCEPTION_DUMP(" a3: " PR_REG, esf->a3); + EXCEPTION_DUMP(" a4: " PR_REG, esf->a4); + EXCEPTION_DUMP(" a5: " PR_REG, esf->a5); #else - LOG_ERR(" a3: " PR_REG " t3: " PR_REG, esf->a3, esf->t3); - LOG_ERR(" a4: " PR_REG " t4: " PR_REG, esf->a4, esf->t4); - LOG_ERR(" a5: " PR_REG " t5: " PR_REG, esf->a5, esf->t5); - LOG_ERR(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6); - LOG_ERR(" a7: " PR_REG, esf->a7); + EXCEPTION_DUMP(" a3: " PR_REG " t3: " PR_REG, esf->a3, esf->t3); + EXCEPTION_DUMP(" a4: " PR_REG " t4: " PR_REG, esf->a4, esf->t4); + EXCEPTION_DUMP(" a5: " PR_REG " t5: " PR_REG, esf->a5, esf->t5); + EXCEPTION_DUMP(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6); + EXCEPTION_DUMP(" a7: " PR_REG, esf->a7); #endif /* CONFIG_RISCV_ISA_RV32E */ - LOG_ERR(" sp: " PR_REG, z_riscv_get_sp_before_exc(esf)); - LOG_ERR(" ra: " PR_REG, esf->ra); - LOG_ERR(" mepc: " PR_REG, esf->mepc); - LOG_ERR("mstatus: " PR_REG, esf->mstatus); - LOG_ERR(""); + EXCEPTION_DUMP(" sp: " PR_REG, z_riscv_get_sp_before_exc(esf)); + EXCEPTION_DUMP(" ra: " PR_REG, esf->ra); + EXCEPTION_DUMP(" mepc: " PR_REG, esf->mepc); + EXCEPTION_DUMP("mstatus: " PR_REG, esf->mstatus); + EXCEPTION_DUMP(""); } if (csf != NULL) { #if defined(CONFIG_RISCV_ISA_RV32E) - LOG_ERR(" s0: " PR_REG, csf->s0); - LOG_ERR(" s1: " PR_REG, csf->s1); + EXCEPTION_DUMP(" s0: " PR_REG, csf->s0); + EXCEPTION_DUMP(" s1: " PR_REG, csf->s1); #else - LOG_ERR(" s0: " PR_REG " s6: " PR_REG, csf->s0, csf->s6); - LOG_ERR(" s1: " PR_REG " s7: " PR_REG, csf->s1, csf->s7); - LOG_ERR(" s2: " PR_REG " s8: " PR_REG, csf->s2, csf->s8); - LOG_ERR(" s3: " PR_REG " s9: " PR_REG, csf->s3, csf->s9); - LOG_ERR(" s4: " PR_REG " s10: " PR_REG, csf->s4, csf->s10); - LOG_ERR(" s5: " PR_REG " s11: " PR_REG, csf->s5, csf->s11); + EXCEPTION_DUMP(" s0: " PR_REG " s6: " PR_REG, csf->s0, csf->s6); + EXCEPTION_DUMP(" s1: " PR_REG " s7: " PR_REG, csf->s1, csf->s7); + EXCEPTION_DUMP(" s2: " PR_REG " s8: " PR_REG, csf->s2, csf->s8); + EXCEPTION_DUMP(" s3: " PR_REG " s9: " PR_REG, csf->s3, csf->s9); + EXCEPTION_DUMP(" s4: " PR_REG " s10: " PR_REG, csf->s4, csf->s10); + EXCEPTION_DUMP(" s5: " PR_REG " s11: " PR_REG, csf->s5, csf->s11); #endif /* CONFIG_RISCV_ISA_RV32E */ - LOG_ERR(""); + EXCEPTION_DUMP(""); } #endif /* CONFIG_EXCEPTION_DEBUG */ diff --git a/arch/riscv/core/fpu.c b/arch/riscv/core/fpu.c index 318e97e0002..d2232c261b7 100644 --- a/arch/riscv/core/fpu.c +++ b/arch/riscv/core/fpu.c @@ -341,6 +341,9 @@ int arch_float_disable(struct k_thread *thread) int arch_float_enable(struct k_thread *thread, unsigned int options) { + ARG_UNUSED(thread); + ARG_UNUSED(options); + /* floats always gets enabled automatically at the moment */ return 0; } diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S index dad96974dcc..a819357a839 100644 --- a/arch/riscv/core/isr.S +++ b/arch/riscv/core/isr.S @@ -225,7 +225,7 @@ SECTION_FUNC(exception.entry, _isr_wrapper) bne t1, t2, no_fp /* determine if we trapped on an FP instruction. */ csrr t2, mtval /* get faulting instruction */ -#ifdef CONFIG_QEMU_TARGET +#ifdef RISCV_NO_MTVAL_ON_FP_TRAP /* * Some implementations may not support MTVAL in this capacity. * Notably QEMU when a CSR instruction is involved. diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c index f6784d28201..ca5e5a49d5a 100644 --- a/arch/riscv/core/pmp.c +++ b/arch/riscv/core/pmp.c @@ -721,6 +721,8 @@ int arch_mem_domain_init(struct k_mem_domain *domain) int arch_mem_domain_partition_add(struct k_mem_domain *domain, uint32_t partition_id) { + ARG_UNUSED(partition_id); + /* Force resynchronization for every thread using this domain */ domain->arch.pmp_update_nr += 1; return 0; @@ -729,6 +731,8 @@ int arch_mem_domain_partition_add(struct k_mem_domain *domain, int arch_mem_domain_partition_remove(struct k_mem_domain *domain, uint32_t partition_id) { + ARG_UNUSED(partition_id); + /* Force resynchronization for every thread using this domain */ domain->arch.pmp_update_nr += 1; return 0; @@ -743,6 +747,8 @@ int arch_mem_domain_thread_add(struct k_thread *thread) int arch_mem_domain_thread_remove(struct k_thread *thread) { + ARG_UNUSED(thread); + return 0; } diff --git a/arch/riscv/core/reset.S b/arch/riscv/core/reset.S index af96cb9757e..f0477ae1734 100644 --- a/arch/riscv/core/reset.S +++ b/arch/riscv/core/reset.S @@ -17,8 +17,8 @@ GTEXT(__reset) /* imports */ GTEXT(z_prep_c) -GTEXT(riscv_cpu_wake_flag) -GTEXT(riscv_cpu_sp) +GDATA(riscv_cpu_wake_flag) +GDATA(riscv_cpu_sp) GTEXT(arch_secondary_cpu_init) #if CONFIG_INCLUDE_RESET_VECTOR diff --git a/arch/riscv/core/stacktrace.c b/arch/riscv/core/stacktrace.c index 74f94d4eb86..32bd9f9edb8 100644 --- a/arch/riscv/core/stacktrace.c +++ b/arch/riscv/core/stacktrace.c @@ -254,11 +254,11 @@ static bool in_fatal_stack_bound(uintptr_t addr, const struct k_thread *const th #ifdef CONFIG_SYMTAB #define LOG_STACK_TRACE(idx, sfp, ra, name, offset) \ - LOG_ERR(" %2d: " SFP ": " PR_REG " ra: " PR_REG " [%s+0x%x]", idx, sfp, ra, name, \ - offset) + EXCEPTION_DUMP(" %2d: " SFP ": " PR_REG " ra: " PR_REG " [%s+0x%x]", \ + idx, sfp, ra, name, offset) #else #define LOG_STACK_TRACE(idx, sfp, ra, name, offset) \ - LOG_ERR(" %2d: " SFP ": " PR_REG " ra: " PR_REG, idx, sfp, ra) + EXCEPTION_DUMP(" %2d: " SFP ": " PR_REG " ra: " PR_REG, idx, sfp, ra) #endif /* CONFIG_SYMTAB */ static bool print_trace_address(void *arg, unsigned long ra, unsigned long sfp) @@ -278,8 +278,8 @@ void z_riscv_unwind_stack(const struct arch_esf *esf, const _callee_saved_t *csf { int i = 0; - LOG_ERR("call trace:"); + EXCEPTION_DUMP("call trace:"); walk_stackframe(print_trace_address, &i, _current, esf, in_fatal_stack_bound, csf); - LOG_ERR(""); + EXCEPTION_DUMP(""); } #endif /* CONFIG_EXCEPTION_STACK_TRACE */ diff --git a/arch/riscv/core/swi_tables.ld b/arch/riscv/core/swi_tables.ld new file mode 100644 index 00000000000..9c421ec37c5 --- /dev/null +++ b/arch/riscv/core/swi_tables.ld @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Google + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if LINKER_ZEPHYR_FINAL && defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION) +INCLUDE isr_tables_swi.ld +#endif diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index ab2cbfe0036..4ee23303f1a 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -255,3 +255,12 @@ FUNC_NORETURN void z_riscv_switch_to_main_no_multithreading(k_thread_entry_t mai CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ } #endif /* !CONFIG_MULTITHREADING */ + +int arch_coprocessors_disable(struct k_thread *thread) +{ +#ifdef CONFIG_FPU_SHARING + return arch_float_disable(thread); +#else + return -ENOTSUP; +#endif +} diff --git a/arch/riscv/core/vector_table.ld b/arch/riscv/core/vector_table.ld index 4ea18a5cff3..8509ff8eb87 100644 --- a/arch/riscv/core/vector_table.ld +++ b/arch/riscv/core/vector_table.ld @@ -4,4 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#if LINKER_ZEPHYR_FINAL && defined(CONFIG_ISR_TABLES_LOCAL_DECLARATION) +INCLUDE isr_tables_vt.ld +KEEP(*(.vectors.__start)) +#else KEEP(*(.vectors.*)) +#endif diff --git a/arch/rx/core/CMakeLists.txt b/arch/rx/core/CMakeLists.txt index 5b3e888db6a..a45a6d9acc9 100644 --- a/arch/rx/core/CMakeLists.txt +++ b/arch/rx/core/CMakeLists.txt @@ -11,6 +11,8 @@ zephyr_library_sources( thread.c vects.c isr_exit.S + fatal.c + reboot.c ) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) diff --git a/arch/rx/core/fatal.c b/arch/rx/core/fatal.c new file mode 100644 index 00000000000..d0272229f95 --- /dev/null +++ b/arch/rx/core/fatal.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Fatal fault handling + * + * This module implements the routines necessary for handling fatal faults on + * RX CPUs. + */ + +#include +#include +#include +#include +#include +LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); + +#ifdef CONFIG_EXCEPTION_DEBUG +static void dump_rx_esf(const struct arch_esf *esf) +{ + EXCEPTION_DUMP(" ACC_L: 0x%08x ACC_H: 0x%08x", esf->acc_l, esf->acc_h); + EXCEPTION_DUMP(" r1: 0x%08x r2: 0x%08x r3: 0x%08x", + esf->r1, esf->r2, esf->r3); + EXCEPTION_DUMP(" r4: 0x%08x r5: 0x%08x r6: 0x%08x", + esf->r4, esf->r5, esf->r6); + EXCEPTION_DUMP(" r7: 0x%08x r8: 0x%08x r9: 0x%08x", + esf->r7, esf->r8, esf->r9); + EXCEPTION_DUMP(" r10: 0x%08x r11: 0x%08x r12: 0x%08x", + esf->r10, esf->r11, esf->r12); + EXCEPTION_DUMP(" r13: 0x%08x r14: 0x%08x r15: 0x%08x", + esf->r13, esf->r14, esf->r15); + EXCEPTION_DUMP(" PC: 0x%08x PSW: 0x%08x", esf->entry_point, esf->psw); +} +#endif + +void z_rx_fatal_error(unsigned int reason, const struct arch_esf *esf) +{ +#ifdef CONFIG_EXCEPTION_DEBUG + if (esf != NULL) { + dump_rx_esf(esf); + } +#endif /* CONFIG_EXCEPTION_DEBUG */ + + z_fatal_error(reason, esf); +} +FUNC_NORETURN void arch_system_halt(unsigned int reason) +{ + ARG_UNUSED(reason); + + __asm__("brk"); + + CODE_UNREACHABLE; +} diff --git a/arch/rx/core/reboot.c b/arch/rx/core/reboot.c new file mode 100644 index 00000000000..b3c103885c9 --- /dev/null +++ b/arch/rx/core/reboot.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief RX reboot interface + */ + +#include +#include +#include + +/** + * @brief Reset the system + * + * This is stub function to avoid build error with CONFIG_REBOOT=y + * RX specification does not have a common interface for system reset. + * Each RX SoC that has reset feature should implement own reset function. + */ + +void __weak sys_arch_reboot(int type) +{ + ARG_UNUSED(type); +} diff --git a/arch/rx/core/reset.S b/arch/rx/core/reset.S index 80246fe397e..6c2538da0c5 100644 --- a/arch/rx/core/reset.S +++ b/arch/rx/core/reset.S @@ -29,10 +29,10 @@ __start : /* load data section from ROM to RAM */ - mov #_mdata,r2 /* src ROM address of data section in R2 */ - mov #_data,r1 /* dest start RAM address of data section in R1 */ - mov #_edata,r3 /* end RAM address of data section in R3 */ - sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ + mov #_image_ram_start,r2 /* src ROM address of data section in R2 */ + mov #__data_start,r1 /* dest start RAM address of data section in R1 */ + mov #__data_region_end,r3 /* end RAM address of data section in R3 */ + sub r1,r3 /* size of data section in R3 (R3=R3-R1) */ #ifdef __RX_ALLOW_STRING_INSNS__ smovf /* block copy R3 bytes from R2 to R1 */ #else diff --git a/arch/rx/core/thread.c b/arch/rx/core/thread.c index 88670bf75da..5855dac3526 100644 --- a/arch/rx/core/thread.c +++ b/arch/rx/core/thread.c @@ -51,3 +51,8 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *sta thread->switch_handle = (void *)iframe; } + +int arch_coprocessors_disable(struct k_thread *thread) +{ + return -ENOTSUP; +} diff --git a/arch/rx/core/vects.c b/arch/rx/core/vects.c index 836e9d3adb2..6835aeb8680 100644 --- a/arch/rx/core/vects.c +++ b/arch/rx/core/vects.c @@ -8,6 +8,7 @@ #include #include #include +#include typedef void (*fp)(void); extern void _start(void); @@ -24,6 +25,14 @@ extern void z_rx_irq_exit(void); #define __ISR__ __attribute__((interrupt, naked)) +#define SET_OFS1_HOCO_BITS(reg, freq) \ + ((reg) & ~(0b11 << 12)) | ((((freq) == 24000000 ? 0b10 \ + : (freq) == 32000000 ? 0b11 \ + : (freq) == 48000000 ? 0b01 \ + : (freq) == 64000000 ? 0b00 \ + : 0b11) \ + << 12)) + static ALWAYS_INLINE void REGISTER_SAVE(void) { __asm volatile( @@ -58,7 +67,7 @@ static void __ISR__ INT_Excep_SuperVisorInst(void) { REGISTER_SAVE(); ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + z_rx_fatal_error(K_ERR_CPU_EXCEPTION, NULL); ISR_DIRECT_FOOTER(1); REGISTER_RESTORE_EXIT(); } @@ -68,7 +77,7 @@ static void __ISR__ INT_Excep_AccessInst(void) { REGISTER_SAVE(); ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + z_rx_fatal_error(K_ERR_CPU_EXCEPTION, NULL); ISR_DIRECT_FOOTER(1); REGISTER_RESTORE_EXIT(); } @@ -78,7 +87,7 @@ static void __ISR__ INT_Excep_UndefinedInst(void) { REGISTER_SAVE(); ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + z_rx_fatal_error(K_ERR_CPU_EXCEPTION, NULL); ISR_DIRECT_FOOTER(1); REGISTER_RESTORE_EXIT(); } @@ -88,7 +97,7 @@ static void __ISR__ INT_Excep_FloatingPoint(void) { REGISTER_SAVE(); ISR_DIRECT_HEADER(); - z_fatal_error(K_ERR_CPU_EXCEPTION, NULL); + z_rx_fatal_error(K_ERR_CPU_EXCEPTION, NULL); ISR_DIRECT_FOOTER(1); REGISTER_RESTORE_EXIT(); } @@ -138,6 +147,28 @@ static void __ISR__ reserved_isr(void) REGISTER_RESTORE_EXIT(); } +static void __ISR__ INT_RuntimeFatalInterrupt(void) +{ + REGISTER_SAVE(); + ISR_DIRECT_HEADER(); + + uint32_t reason; + const struct arch_esf *esf; + + /* Read the current values of CPU registers r1 and r0 into C variables + * 'reason' is expected to contain the exception reason (from r1) + * 'esf' is expected to contain a pointer to the exception stack frame (from r0) + */ + __asm__ volatile("mov r1, %0\n\t" + "mov r0, %1\n\t" + : "=r"(reason), "=r"(esf)); + + z_rx_fatal_error(reason, esf); + + ISR_DIRECT_FOOTER(1); + REGISTER_RESTORE_EXIT(); +} + /* wrapper for z_rx_context_switch_isr, defined in switch.S */ extern void __ISR__ switch_isr_wrapper(void); @@ -399,7 +430,9 @@ const void *FixedVectors[] FVECT_SECT = { /* Reserved for OFSM */ (fp)0xFFFFFFFF, (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, + (fp)(SET_OFS1_HOCO_BITS( + 0xFFFFFFFF, + (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(hoco), clock_frequency, 32000000)))), (fp)0xFFFFFFFF, /* Reserved area */ (fp)0xFFFFFFFF, @@ -444,56 +477,90 @@ const void *FixedVectors[] FVECT_SECT = { }; const fp RelocatableVectors[] RVECT_SECT = { - reserved_isr, switch_isr_wrapper, reserved_isr, reserved_isr, reserved_isr, - reserved_isr, reserved_isr, reserved_isr, reserved_isr, reserved_isr, - reserved_isr, reserved_isr, reserved_isr, reserved_isr, reserved_isr, - reserved_isr, int_demux_16, int_demux_17, int_demux_18, int_demux_19, - int_demux_20, int_demux_21, int_demux_22, int_demux_23, int_demux_24, - int_demux_25, int_demux_26, int_demux_27, int_demux_28, int_demux_29, - int_demux_30, int_demux_31, int_demux_32, int_demux_33, int_demux_34, - int_demux_35, int_demux_36, int_demux_37, int_demux_38, int_demux_39, - int_demux_40, int_demux_41, int_demux_42, int_demux_43, int_demux_44, - int_demux_45, int_demux_46, int_demux_47, int_demux_48, int_demux_49, - int_demux_50, int_demux_51, int_demux_52, int_demux_53, int_demux_54, - int_demux_55, int_demux_56, int_demux_57, int_demux_58, int_demux_59, - int_demux_60, int_demux_61, int_demux_62, int_demux_63, int_demux_64, - int_demux_65, int_demux_66, int_demux_67, int_demux_68, int_demux_69, - int_demux_70, int_demux_71, int_demux_72, int_demux_73, int_demux_74, - int_demux_75, int_demux_76, int_demux_77, int_demux_78, int_demux_79, - int_demux_80, int_demux_81, int_demux_82, int_demux_83, int_demux_84, - int_demux_85, int_demux_86, int_demux_87, int_demux_88, int_demux_89, - int_demux_90, int_demux_91, int_demux_92, int_demux_93, int_demux_94, - int_demux_95, int_demux_96, int_demux_97, int_demux_98, int_demux_99, - int_demux_100, int_demux_101, int_demux_102, int_demux_103, int_demux_104, - int_demux_105, int_demux_106, int_demux_107, int_demux_108, int_demux_109, - int_demux_110, int_demux_111, int_demux_112, int_demux_113, int_demux_114, - int_demux_115, int_demux_116, int_demux_117, int_demux_118, int_demux_119, - int_demux_120, int_demux_121, int_demux_122, int_demux_123, int_demux_124, - int_demux_125, int_demux_126, int_demux_127, int_demux_128, int_demux_129, - int_demux_130, int_demux_131, int_demux_132, int_demux_133, int_demux_134, - int_demux_135, int_demux_136, int_demux_137, int_demux_138, int_demux_139, - int_demux_140, int_demux_141, int_demux_142, int_demux_143, int_demux_144, - int_demux_145, int_demux_146, int_demux_147, int_demux_148, int_demux_149, - int_demux_150, int_demux_151, int_demux_152, int_demux_153, int_demux_154, - int_demux_155, int_demux_156, int_demux_157, int_demux_158, int_demux_159, - int_demux_160, int_demux_161, int_demux_162, int_demux_163, int_demux_164, - int_demux_165, int_demux_166, int_demux_167, int_demux_168, int_demux_169, - int_demux_170, int_demux_171, int_demux_172, int_demux_173, int_demux_174, - int_demux_175, int_demux_176, int_demux_177, int_demux_178, int_demux_179, - int_demux_180, int_demux_181, int_demux_182, int_demux_183, int_demux_184, - int_demux_185, int_demux_186, int_demux_187, int_demux_188, int_demux_189, - int_demux_190, int_demux_191, int_demux_192, int_demux_193, int_demux_194, - int_demux_195, int_demux_196, int_demux_197, int_demux_198, int_demux_199, - int_demux_200, int_demux_201, int_demux_202, int_demux_203, int_demux_204, - int_demux_205, int_demux_206, int_demux_207, int_demux_208, int_demux_209, - int_demux_210, int_demux_211, int_demux_212, int_demux_213, int_demux_214, - int_demux_215, int_demux_216, int_demux_217, int_demux_218, int_demux_219, - int_demux_220, int_demux_221, int_demux_222, int_demux_223, int_demux_224, - int_demux_225, int_demux_226, int_demux_227, int_demux_228, int_demux_229, - int_demux_230, int_demux_231, int_demux_232, int_demux_233, int_demux_234, - int_demux_235, int_demux_236, int_demux_237, int_demux_238, int_demux_239, - int_demux_240, int_demux_241, int_demux_242, int_demux_243, int_demux_244, - int_demux_245, int_demux_246, int_demux_247, int_demux_248, int_demux_249, - int_demux_250, int_demux_251, int_demux_252, int_demux_253, int_demux_254, + reserved_isr, switch_isr_wrapper, INT_RuntimeFatalInterrupt, + reserved_isr, reserved_isr, reserved_isr, + reserved_isr, reserved_isr, reserved_isr, + reserved_isr, reserved_isr, reserved_isr, + reserved_isr, reserved_isr, reserved_isr, + reserved_isr, int_demux_16, int_demux_17, + int_demux_18, int_demux_19, int_demux_20, + int_demux_21, int_demux_22, int_demux_23, + int_demux_24, int_demux_25, int_demux_26, + int_demux_27, int_demux_28, int_demux_29, + int_demux_30, int_demux_31, int_demux_32, + int_demux_33, int_demux_34, int_demux_35, + int_demux_36, int_demux_37, int_demux_38, + int_demux_39, int_demux_40, int_demux_41, + int_demux_42, int_demux_43, int_demux_44, + int_demux_45, int_demux_46, int_demux_47, + int_demux_48, int_demux_49, int_demux_50, + int_demux_51, int_demux_52, int_demux_53, + int_demux_54, int_demux_55, int_demux_56, + int_demux_57, int_demux_58, int_demux_59, + int_demux_60, int_demux_61, int_demux_62, + int_demux_63, int_demux_64, int_demux_65, + int_demux_66, int_demux_67, int_demux_68, + int_demux_69, int_demux_70, int_demux_71, + int_demux_72, int_demux_73, int_demux_74, + int_demux_75, int_demux_76, int_demux_77, + int_demux_78, int_demux_79, int_demux_80, + int_demux_81, int_demux_82, int_demux_83, + int_demux_84, int_demux_85, int_demux_86, + int_demux_87, int_demux_88, int_demux_89, + int_demux_90, int_demux_91, int_demux_92, + int_demux_93, int_demux_94, int_demux_95, + int_demux_96, int_demux_97, int_demux_98, + int_demux_99, int_demux_100, int_demux_101, + int_demux_102, int_demux_103, int_demux_104, + int_demux_105, int_demux_106, int_demux_107, + int_demux_108, int_demux_109, int_demux_110, + int_demux_111, int_demux_112, int_demux_113, + int_demux_114, int_demux_115, int_demux_116, + int_demux_117, int_demux_118, int_demux_119, + int_demux_120, int_demux_121, int_demux_122, + int_demux_123, int_demux_124, int_demux_125, + int_demux_126, int_demux_127, int_demux_128, + int_demux_129, int_demux_130, int_demux_131, + int_demux_132, int_demux_133, int_demux_134, + int_demux_135, int_demux_136, int_demux_137, + int_demux_138, int_demux_139, int_demux_140, + int_demux_141, int_demux_142, int_demux_143, + int_demux_144, int_demux_145, int_demux_146, + int_demux_147, int_demux_148, int_demux_149, + int_demux_150, int_demux_151, int_demux_152, + int_demux_153, int_demux_154, int_demux_155, + int_demux_156, int_demux_157, int_demux_158, + int_demux_159, int_demux_160, int_demux_161, + int_demux_162, int_demux_163, int_demux_164, + int_demux_165, int_demux_166, int_demux_167, + int_demux_168, int_demux_169, int_demux_170, + int_demux_171, int_demux_172, int_demux_173, + int_demux_174, int_demux_175, int_demux_176, + int_demux_177, int_demux_178, int_demux_179, + int_demux_180, int_demux_181, int_demux_182, + int_demux_183, int_demux_184, int_demux_185, + int_demux_186, int_demux_187, int_demux_188, + int_demux_189, int_demux_190, int_demux_191, + int_demux_192, int_demux_193, int_demux_194, + int_demux_195, int_demux_196, int_demux_197, + int_demux_198, int_demux_199, int_demux_200, + int_demux_201, int_demux_202, int_demux_203, + int_demux_204, int_demux_205, int_demux_206, + int_demux_207, int_demux_208, int_demux_209, + int_demux_210, int_demux_211, int_demux_212, + int_demux_213, int_demux_214, int_demux_215, + int_demux_216, int_demux_217, int_demux_218, + int_demux_219, int_demux_220, int_demux_221, + int_demux_222, int_demux_223, int_demux_224, + int_demux_225, int_demux_226, int_demux_227, + int_demux_228, int_demux_229, int_demux_230, + int_demux_231, int_demux_232, int_demux_233, + int_demux_234, int_demux_235, int_demux_236, + int_demux_237, int_demux_238, int_demux_239, + int_demux_240, int_demux_241, int_demux_242, + int_demux_243, int_demux_244, int_demux_245, + int_demux_246, int_demux_247, int_demux_248, + int_demux_249, int_demux_250, int_demux_251, + int_demux_252, int_demux_253, int_demux_254, int_demux_255, }; diff --git a/arch/rx/include/kernel_arch_func.h b/arch/rx/include/kernel_arch_func.h index 70058fb5c96..65041bddc34 100644 --- a/arch/rx/include/kernel_arch_func.h +++ b/arch/rx/include/kernel_arch_func.h @@ -25,6 +25,7 @@ static inline bool arch_is_in_isr(void) } extern void z_rx_arch_switch(void *switch_to, void **switched_from); +extern void z_rx_fatal_error(unsigned int reason, const struct arch_esf *esf); static inline void arch_switch(void *switch_to, void **switched_from) { diff --git a/arch/sparc/core/fatal.c b/arch/sparc/core/fatal.c index 40fd9d16792..684c161428e 100644 --- a/arch/sparc/core/fatal.c +++ b/arch/sparc/core/fatal.c @@ -139,16 +139,16 @@ static void print_trap_type(const struct arch_esf *esf) } } } - LOG_ERR("tt = 0x%02X, %s", tt, desc); + EXCEPTION_DUMP("tt = 0x%02X, %s", tt, desc); } static void print_integer_registers(const struct arch_esf *esf) { const struct savearea *flushed = (struct savearea *) esf->out[6]; - LOG_ERR(" INS LOCALS OUTS GLOBALS"); + EXCEPTION_DUMP(" INS LOCALS OUTS GLOBALS"); for (int i = 0; i < 8; i++) { - LOG_ERR( + EXCEPTION_DUMP( " %d: %08x %08x %08x %08x", i, flushed ? flushed->in[i] : 0, @@ -161,11 +161,11 @@ static void print_integer_registers(const struct arch_esf *esf) static void print_special_registers(const struct arch_esf *esf) { - LOG_ERR( + EXCEPTION_DUMP( "psr: %08x wim: %08x tbr: %08x y: %08x", esf->psr, esf->wim, esf->tbr, esf->y ); - LOG_ERR(" pc: %08x npc: %08x", esf->pc, esf->npc); + EXCEPTION_DUMP(" pc: %08x npc: %08x", esf->pc, esf->npc); } static void print_backtrace(const struct arch_esf *esf) @@ -173,8 +173,8 @@ static void print_backtrace(const struct arch_esf *esf) const int MAX_LOGLINES = 40; const struct savearea *s = (struct savearea *) esf->out[6]; - LOG_ERR(" pc sp"); - LOG_ERR(" #0 %08x %08x", esf->pc, (unsigned int) s); + EXCEPTION_DUMP(" pc sp"); + EXCEPTION_DUMP(" #0 %08x %08x", esf->pc, (unsigned int) s); for (int i = 1; s && i < MAX_LOGLINES; i++) { const uint32_t pc = s->in[7]; const uint32_t sp = s->in[6]; @@ -182,7 +182,7 @@ static void print_backtrace(const struct arch_esf *esf) if (sp == 0U && pc == 0U) { break; } - LOG_ERR(" #%-2d %08x %08x", i, pc, sp); + EXCEPTION_DUMP(" #%-2d %08x %08x", i, pc, sp); if (sp == 0U || sp & 7U) { break; } @@ -192,15 +192,15 @@ static void print_backtrace(const struct arch_esf *esf) static void print_all(const struct arch_esf *esf) { - LOG_ERR(""); + EXCEPTION_DUMP(""); print_trap_type(esf); - LOG_ERR(""); + EXCEPTION_DUMP(""); print_integer_registers(esf); - LOG_ERR(""); + EXCEPTION_DUMP(""); print_special_registers(esf); - LOG_ERR(""); + EXCEPTION_DUMP(""); print_backtrace(esf); - LOG_ERR(""); + EXCEPTION_DUMP(""); } #endif /* CONFIG_EXCEPTION_DEBUG */ diff --git a/arch/sparc/core/thread.c b/arch/sparc/core/thread.c index e56d9f827c9..0b25da4109a 100644 --- a/arch/sparc/core/thread.c +++ b/arch/sparc/core/thread.c @@ -69,11 +69,21 @@ void *z_arch_get_next_switch_handle(struct k_thread **old_thread) #if defined(CONFIG_FPU_SHARING) int arch_float_disable(struct k_thread *thread) { + ARG_UNUSED(thread); + return -ENOTSUP; } int arch_float_enable(struct k_thread *thread, unsigned int options) { + ARG_UNUSED(thread); + ARG_UNUSED(options); + return -ENOTSUP; } #endif /* CONFIG_FPU_SHARING */ + +int arch_coprocessors_disable(struct k_thread *thread) +{ + return -ENOTSUP; +} diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a9a883a3104..27fa6e40dcc 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -187,6 +187,13 @@ endif # FPU || X86_64 endmenu +config X86_DEBUG_INFO + bool "System debugging information" + help + This option enables the addition of various information that can be + used by debuggers in debugging the system, or enable additional + debugging information to be reported at runtime. + config SRAM_OFFSET default 0x100000 if X86_PC_COMPATIBLE help diff --git a/arch/x86/core/Kconfig.ia32 b/arch/x86/core/Kconfig.ia32 index 75a3c2bbb7c..f24e7d37758 100644 --- a/arch/x86/core/Kconfig.ia32 +++ b/arch/x86/core/Kconfig.ia32 @@ -166,7 +166,7 @@ endmenu config ARCH_HAS_STACKWALK bool default y - select DEBUG_INFO + select X86_DEBUG_INFO select THREAD_STACK_INFO depends on !OMIT_FRAME_POINTER help diff --git a/arch/x86/core/Kconfig.intel64 b/arch/x86/core/Kconfig.intel64 index e1f5869c772..0f73341db31 100644 --- a/arch/x86/core/Kconfig.intel64 +++ b/arch/x86/core/Kconfig.intel64 @@ -32,7 +32,7 @@ config X86_EXCEPTION_STACK_SIZE config ARCH_HAS_STACKWALK bool default y - select DEBUG_INFO + select X86_DEBUG_INFO select THREAD_STACK_INFO depends on !OMIT_FRAME_POINTER help diff --git a/arch/x86/core/fatal.c b/arch/x86/core/fatal.c index 6511f531e3d..a5c3986deb7 100644 --- a/arch/x86/core/fatal.c +++ b/arch/x86/core/fatal.c @@ -146,13 +146,13 @@ __pinned_func static void walk_stackframe(stack_trace_callback_fn cb, void *cook } if (base_ptr == 0U) { - LOG_ERR("NULL base ptr"); + EXCEPTION_DUMP("NULL base ptr"); return; } for (i = 0; i < max_frames; i++) { if (base_ptr % sizeof(base_ptr) != 0U) { - LOG_ERR("unaligned frame ptr"); + EXCEPTION_DUMP("unaligned frame ptr"); return; } @@ -167,7 +167,7 @@ __pinned_func static void walk_stackframe(stack_trace_callback_fn cb, void *cook */ if (z_x86_check_stack_bounds((uintptr_t)frame, sizeof(*frame), cs)) { - LOG_ERR(" corrupted? (bp=%p)", frame); + EXCEPTION_DUMP(" corrupted? (bp=%p)", frame); break; } #endif @@ -200,9 +200,9 @@ static bool print_trace_address(void *arg, unsigned long addr) int *i = arg; #ifdef CONFIG_X86_64 - LOG_ERR(" %d: 0x%016lx", (*i)++, addr); + EXCEPTION_DUMP(" %d: 0x%016lx", (*i)++, addr); #else - LOG_ERR(" %d: 0x%08lx", (*i)++, addr); + EXCEPTION_DUMP(" %d: 0x%08lx", (*i)++, addr); #endif return true; @@ -253,31 +253,31 @@ static inline pentry_t *get_ptables(const struct arch_esf *esf) __pinned_func static void dump_regs(const struct arch_esf *esf) { - LOG_ERR("RAX: 0x%016lx RBX: 0x%016lx RCX: 0x%016lx RDX: 0x%016lx", + EXCEPTION_DUMP("RAX: 0x%016lx RBX: 0x%016lx RCX: 0x%016lx RDX: 0x%016lx", esf->rax, esf->rbx, esf->rcx, esf->rdx); - LOG_ERR("RSI: 0x%016lx RDI: 0x%016lx RBP: 0x%016lx RSP: 0x%016lx", + EXCEPTION_DUMP("RSI: 0x%016lx RDI: 0x%016lx RBP: 0x%016lx RSP: 0x%016lx", esf->rsi, esf->rdi, esf->rbp, esf->rsp); - LOG_ERR(" R8: 0x%016lx R9: 0x%016lx R10: 0x%016lx R11: 0x%016lx", + EXCEPTION_DUMP(" R8: 0x%016lx R9: 0x%016lx R10: 0x%016lx R11: 0x%016lx", esf->r8, esf->r9, esf->r10, esf->r11); - LOG_ERR("R12: 0x%016lx R13: 0x%016lx R14: 0x%016lx R15: 0x%016lx", + EXCEPTION_DUMP("R12: 0x%016lx R13: 0x%016lx R14: 0x%016lx R15: 0x%016lx", esf->r12, esf->r13, esf->r14, esf->r15); - LOG_ERR("RSP: 0x%016lx RFLAGS: 0x%016lx CS: 0x%04lx CR3: 0x%016lx", + EXCEPTION_DUMP("RSP: 0x%016lx RFLAGS: 0x%016lx CS: 0x%04lx CR3: 0x%016lx", esf->rsp, esf->rflags, esf->cs & 0xFFFFU, get_cr3(esf)); - LOG_ERR("RIP: 0x%016lx", esf->rip); + EXCEPTION_DUMP("RIP: 0x%016lx", esf->rip); } #else /* 32-bit */ __pinned_func static void dump_regs(const struct arch_esf *esf) { - LOG_ERR("EAX: 0x%08x, EBX: 0x%08x, ECX: 0x%08x, EDX: 0x%08x", + EXCEPTION_DUMP("EAX: 0x%08x, EBX: 0x%08x, ECX: 0x%08x, EDX: 0x%08x", esf->eax, esf->ebx, esf->ecx, esf->edx); - LOG_ERR("ESI: 0x%08x, EDI: 0x%08x, EBP: 0x%08x, ESP: 0x%08x", + EXCEPTION_DUMP("ESI: 0x%08x, EDI: 0x%08x, EBP: 0x%08x, ESP: 0x%08x", esf->esi, esf->edi, esf->ebp, esf->esp); - LOG_ERR("EFLAGS: 0x%08x CS: 0x%04x CR3: 0x%08lx", esf->eflags, + EXCEPTION_DUMP("EFLAGS: 0x%08x CS: 0x%04x CR3: 0x%08lx", esf->eflags, esf->cs & 0xFFFFU, get_cr3(esf)); - LOG_ERR("EIP: 0x%08x", esf->eip); + EXCEPTION_DUMP("EIP: 0x%08x", esf->eip); } #endif /* CONFIG_X86_64 */ @@ -286,68 +286,68 @@ static void log_exception(uintptr_t vector, uintptr_t code) { switch (vector) { case IV_DIVIDE_ERROR: - LOG_ERR("Divide by zero"); + EXCEPTION_DUMP("Divide by zero"); break; case IV_DEBUG: - LOG_ERR("Debug"); + EXCEPTION_DUMP("Debug"); break; case IV_NON_MASKABLE_INTERRUPT: - LOG_ERR("Non-maskable interrupt"); + EXCEPTION_DUMP("Non-maskable interrupt"); break; case IV_BREAKPOINT: - LOG_ERR("Breakpoint"); + EXCEPTION_DUMP("Breakpoint"); break; case IV_OVERFLOW: - LOG_ERR("Overflow"); + EXCEPTION_DUMP("Overflow"); break; case IV_BOUND_RANGE: - LOG_ERR("Bound range exceeded"); + EXCEPTION_DUMP("Bound range exceeded"); break; case IV_INVALID_OPCODE: - LOG_ERR("Invalid opcode"); + EXCEPTION_DUMP("Invalid opcode"); break; case IV_DEVICE_NOT_AVAILABLE: - LOG_ERR("Floating point unit device not available"); + EXCEPTION_DUMP("Floating point unit device not available"); break; case IV_DOUBLE_FAULT: - LOG_ERR("Double fault (code 0x%lx)", code); + EXCEPTION_DUMP("Double fault (code 0x%lx)", code); break; case IV_COPROC_SEGMENT_OVERRUN: - LOG_ERR("Co-processor segment overrun"); + EXCEPTION_DUMP("Co-processor segment overrun"); break; case IV_INVALID_TSS: - LOG_ERR("Invalid TSS (code 0x%lx)", code); + EXCEPTION_DUMP("Invalid TSS (code 0x%lx)", code); break; case IV_SEGMENT_NOT_PRESENT: - LOG_ERR("Segment not present (code 0x%lx)", code); + EXCEPTION_DUMP("Segment not present (code 0x%lx)", code); break; case IV_STACK_FAULT: - LOG_ERR("Stack segment fault"); + EXCEPTION_DUMP("Stack segment fault"); break; case IV_GENERAL_PROTECTION: - LOG_ERR("General protection fault (code 0x%lx)", code); + EXCEPTION_DUMP("General protection fault (code 0x%lx)", code); break; /* IV_PAGE_FAULT skipped, we have a dedicated handler */ case IV_X87_FPU_FP_ERROR: - LOG_ERR("x87 floating point exception"); + EXCEPTION_DUMP("x87 floating point exception"); break; case IV_ALIGNMENT_CHECK: - LOG_ERR("Alignment check (code 0x%lx)", code); + EXCEPTION_DUMP("Alignment check (code 0x%lx)", code); break; case IV_MACHINE_CHECK: - LOG_ERR("Machine check"); + EXCEPTION_DUMP("Machine check"); break; case IV_SIMD_FP: - LOG_ERR("SIMD floating point exception"); + EXCEPTION_DUMP("SIMD floating point exception"); break; case IV_VIRT_EXCEPTION: - LOG_ERR("Virtualization exception"); + EXCEPTION_DUMP("Virtualization exception"); break; case IV_SECURITY_EXCEPTION: - LOG_ERR("Security exception"); + EXCEPTION_DUMP("Security exception"); break; default: - LOG_ERR("Exception not handled (code 0x%lx)", code); + EXCEPTION_DUMP("Exception not handled (code 0x%lx)", code); break; } } @@ -360,23 +360,23 @@ static void dump_page_fault(struct arch_esf *esf) cr2 = z_x86_cr2_get(); err = esf_get_code(esf); - LOG_ERR("Page fault at address %p (error code 0x%lx)", cr2, err); + EXCEPTION_DUMP("Page fault at address %p (error code 0x%lx)", cr2, err); if ((err & PF_RSVD) != 0) { - LOG_ERR("Reserved bits set in page tables"); + EXCEPTION_DUMP("Reserved bits set in page tables"); } else { if ((err & PF_P) == 0) { - LOG_ERR("Linear address not present in page tables"); + EXCEPTION_DUMP("Linear address not present in page tables"); } - LOG_ERR("Access violation: %s thread not allowed to %s", + EXCEPTION_DUMP("Access violation: %s thread not allowed to %s", (err & PF_US) != 0U ? "user" : "supervisor", (err & PF_ID) != 0U ? "execute" : ((err & PF_WR) != 0U ? "write" : "read")); if ((err & PF_PK) != 0) { - LOG_ERR("Protection key disallowed"); + EXCEPTION_DUMP("Protection key disallowed"); } else if ((err & PF_SGX) != 0) { - LOG_ERR("SGX access control violation"); + EXCEPTION_DUMP("SGX access control violation"); } } @@ -395,7 +395,7 @@ FUNC_NORETURN void z_x86_fatal_error(unsigned int reason, dump_regs(esf); #endif #ifdef CONFIG_EXCEPTION_STACK_TRACE - LOG_ERR("call trace:"); + EXCEPTION_DUMP("call trace:"); unwind_stack(esf); #endif /* CONFIG_EXCEPTION_STACK_TRACE */ #if defined(CONFIG_ASSERT) && defined(CONFIG_X86_64) @@ -404,7 +404,7 @@ FUNC_NORETURN void z_x86_fatal_error(unsigned int reason, * never a valid RIP value. Treat this as a kernel * panic. */ - LOG_ERR("Attempt to resume un-suspended thread object"); + EXCEPTION_DUMP("Attempt to resume un-suspended thread object"); reason = K_ERR_KERNEL_PANIC; } #endif diff --git a/arch/x86/core/ia32/fatal.c b/arch/x86/core/ia32/fatal.c index 3ae8a6b67da..88a6e1be6d8 100644 --- a/arch/x86/core/ia32/fatal.c +++ b/arch/x86/core/ia32/fatal.c @@ -35,7 +35,7 @@ void z_x86_spurious_irq(const struct arch_esf *esf) int vector = z_irq_controller_isr_vector_get(); if (vector >= 0) { - LOG_ERR("IRQ vector: %d", vector); + EXCEPTION_DUMP("IRQ vector: %d", vector); } z_x86_fatal_error(K_ERR_SPURIOUS_IRQ, esf); @@ -169,7 +169,7 @@ static __used void df_handler_bottom(void) _df_tss.esp = (uint32_t)(_df_stack + sizeof(_df_stack)); _df_tss.eip = (uint32_t)df_handler_top; - LOG_ERR("Double Fault"); + EXCEPTION_DUMP("Double Fault"); #ifdef CONFIG_THREAD_STACK_INFO /* To comply with MISRA 13.2 rule necessary to exclude code that depends * on the order of evaluation of function arguments. diff --git a/arch/x86/core/ia32/thread.c b/arch/x86/core/ia32/thread.c index b639bb59fdf..21d03ca2160 100644 --- a/arch/x86/core/ia32/thread.c +++ b/arch/x86/core/ia32/thread.c @@ -72,6 +72,15 @@ int arch_float_enable(struct k_thread *thread, unsigned int options) } #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ +int arch_coprocessors_disable(struct k_thread *thread) +{ +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + return arch_float_disable(thread); +#else + return -ENOTSUP; +#endif +} + void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *stack_ptr, k_thread_entry_t entry, void *p1, void *p2, void *p3) diff --git a/arch/x86/core/intel64/fatal.c b/arch/x86/core/intel64/fatal.c index 9eed95bfaa3..941a982100c 100644 --- a/arch/x86/core/intel64/fatal.c +++ b/arch/x86/core/intel64/fatal.c @@ -46,7 +46,7 @@ void arch_syscall_oops(void *ssf_ptr) { struct x86_ssf *ssf = ssf_ptr; - LOG_ERR("Bad system call from RIP 0x%lx", ssf->rip); + EXCEPTION_DUMP("Bad system call from RIP 0x%lx", ssf->rip); z_x86_fatal_error(K_ERR_KERNEL_OOPS, NULL); } diff --git a/arch/x86/core/intel64/thread.c b/arch/x86/core/intel64/thread.c index 49cb58ec9c6..bc326b2b170 100644 --- a/arch/x86/core/intel64/thread.c +++ b/arch/x86/core/intel64/thread.c @@ -83,3 +83,11 @@ int arch_float_enable(struct k_thread *thread, unsigned int options) return 0; } + +int arch_coprocessors_disable(struct k_thread *thread) +{ + /* x86-64 always has FP/SSE enabled so cannot be disabled */ + ARG_UNUSED(thread); + + return -ENOTSUP; +} diff --git a/arch/x86/core/multiboot.c b/arch/x86/core/multiboot.c index 06d03c7b807..a7afd42444b 100644 --- a/arch/x86/core/multiboot.c +++ b/arch/x86/core/multiboot.c @@ -100,6 +100,7 @@ void z_multiboot_init(struct multiboot_info *info_pa) break; default: type = X86_MEMMAP_ENTRY_UNKNOWN; + break; } x86_memmap[index].type = type; diff --git a/arch/x86/core/x86_mmu.c b/arch/x86/core/x86_mmu.c index e4188b8670f..b2458d02767 100644 --- a/arch/x86/core/x86_mmu.c +++ b/arch/x86/core/x86_mmu.c @@ -1267,6 +1267,7 @@ static pentry_t flags_to_entry(uint32_t flags) break; default: __ASSERT(false, "bad memory mapping flags 0x%x", flags); + break; } if ((flags & K_MEM_PERM_RW) != 0U) { diff --git a/arch/x86/include/ia32/kernel_arch_data.h b/arch/x86/include/ia32/kernel_arch_data.h index 3f8c2732f9e..f1c2943295c 100644 --- a/arch/x86/include/ia32/kernel_arch_data.h +++ b/arch/x86/include/ia32/kernel_arch_data.h @@ -40,7 +40,7 @@ /* Some configurations require that the stack/registers be adjusted before * z_thread_entry. See discussion in swap.S for z_x86_thread_entry_wrapper() */ -#if defined(CONFIG_DEBUG_INFO) +#if defined(CONFIG_X86_DEBUG_INFO) #define _THREAD_WRAPPER_REQUIRED #endif diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 143607a2295..6a4f727cded 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -42,7 +42,7 @@ config XTENSA_USE_CORE_CRT1 config XTENSA_ENABLE_BACKTRACE bool "Backtrace on panic exception" default y - depends on SOC_SERIES_ESP32 || SOC_FAMILY_INTEL_ADSP || SOC_XTENSA_DC233C + depends on SOC_SERIES_ESP32 || SOC_FAMILY_INTEL_ADSP || SOC_XTENSA_DC233C || SOC_MIMXRT595S_F1 help Enable this config option to print backtrace on panic exception @@ -153,6 +153,34 @@ config XTENSA_HIFI_SHARING across context switches to allow multiple threads to perform concurrent HiFi operations. +if XTENSA_HIFI_SHARING + +choice XTENSA_HIFI_SHARING_MODEL + prompt "Xtensa HiFi Sharing Model" + depends on XTENSA_HIFI_SHARING + default XTENSA_EAGER_HIFI_SHARING + +config XTENSA_EAGER_HIFI_SHARING + bool "Eager HiFi Sharing" + help + This option enables eager sharing of HiFi registers across context + switches. This means that the HiFi registers are unconditionally + saved and restored on every context switch, allowing multiple threads + to use HiFi instructions concurrently. + +config XTENSA_LAZY_HIFI_SHARING + bool "Lazy HiFi Sharing" + depends on SCHED_IPI_SUPPORTED || (MP_MAX_NUM_CPUS = 1) + select ARCH_IPI_LAZY_COPROCESSORS_SAVE + help + This option enables lazy sharing of HiFi registers across context + switches. This means that the HiFi registers are saved and restored + only when a thread actually uses HiFi instructions, allowing for + more efficient use of resources when HiFi instructions are not used. +endchoice + +endif # XTENSA_HIFI_SHARING + endif # XTENSA_CPU_HAS_HIFI endmenu # Xtensa HiFi Options @@ -205,7 +233,7 @@ config XTENSA_MMU_NUM_L1_TABLES default 1 if !USERSPACE default 4 help - This option specifies the maximum number of traslation tables. + This option specifies the maximum number of translation tables. Translation tables are directly related to the number of memory domains in the target, considering the kernel itself requires one. diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index e3d6025a91f..9ac52b16317 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -23,6 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE debug_helpers_asm.S) zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c) zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c) zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c) +zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU ptables.c mmu.c) zephyr_library_sources_ifdef(CONFIG_XTENSA_MPU mpu.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S syscall_helper.c) @@ -90,6 +91,10 @@ else() set(NEED_FLUSH_SCRATCH_REG false) endif() +if(CONFIG_SEMIHOST) + zephyr_library_include_directories(${ZEPHYR_BASE}/arch/common/include) +endif() + # Generates a list of device-specific scratch register choices set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/zsr.h) add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM} diff --git a/arch/xtensa/core/elf.c b/arch/xtensa/core/elf.c index d16f51e61a2..d0cf6281355 100644 --- a/arch/xtensa/core/elf.c +++ b/arch/xtensa/core/elf.c @@ -32,10 +32,10 @@ LOG_MODULE_DECLARE(llext, CONFIG_LLEXT_LOG_LEVEL); #define R_XTENSA_ASM_EXPAND 11 #define R_XTENSA_SLOT0_OP 20 -static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, - const elf_rela_t *rel, uintptr_t addr, - uint8_t *loc, int type, uint32_t stb, - const struct llext_load_param *ldr_parm) +static int xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, + const elf_rela_t *rel, uintptr_t addr, + uint8_t *loc, int type, uint32_t stb, + const struct llext_load_param *ldr_parm) { elf_word *got_entry = (elf_word *)loc; @@ -59,7 +59,7 @@ static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, if (sh_ndx == ext->sect_cnt) { LOG_ERR("%#x not found in any of the sections", *got_entry); - return; + return -ENOENT; } *got_entry += (uintptr_t)llext_loaded_sect_ptr(ldr, ext, sh_ndx) - @@ -87,7 +87,7 @@ static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, } if (ret) { LOG_ERR("Failed to read a symbol table entry, LLEXT linking might fail."); - return; + return ret; } /* @@ -124,19 +124,21 @@ static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, default: LOG_DBG("Unsupported relocation type %u", type); - return; + return 0; } LOG_DBG("Applied relocation to %#x type %u at %p", *(uint32_t *)((uintptr_t)got_entry & ~3), type, (void *)got_entry); + + return 0; } /** * @brief Architecture specific function for STB_LOCAL ELF relocations */ -void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel, - const elf_sym_t *sym, uint8_t *rel_addr, - const struct llext_load_param *ldr_parm) +int arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel, + const elf_sym_t *sym, uint8_t *rel_addr, + const struct llext_load_param *ldr_parm) { int type = ELF32_R_TYPE(rel->r_info); uintptr_t sh_addr; @@ -152,15 +154,15 @@ void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, const sh_addr = ldr->sects[LLEXT_MEM_TEXT].sh_addr; } - xtensa_elf_relocate(ldr, ext, rel, sh_addr, rel_addr, type, ELF_ST_BIND(sym->st_info), - ldr_parm); + return xtensa_elf_relocate(ldr, ext, rel, sh_addr, rel_addr, type, + ELF_ST_BIND(sym->st_info), ldr_parm); } /** * @brief Architecture specific function for STB_GLOBAL ELF relocations */ -void arch_elf_relocate_global(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel, - const elf_sym_t *sym, uint8_t *rel_addr, const void *link_addr) +int arch_elf_relocate_global(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel, + const elf_sym_t *sym, uint8_t *rel_addr, const void *link_addr) { int type = ELF32_R_TYPE(rel->r_info); @@ -169,6 +171,6 @@ void arch_elf_relocate_global(struct llext_loader *ldr, struct llext *ext, const LOG_WRN("global: non-zero relative value %#x", *(elf_word *)rel_addr); } - xtensa_elf_relocate(ldr, ext, rel, (uintptr_t)link_addr, rel_addr, type, - ELF_ST_BIND(sym->st_info), NULL); + return xtensa_elf_relocate(ldr, ext, rel, (uintptr_t)link_addr, rel_addr, type, + ELF_ST_BIND(sym->st_info), NULL); } diff --git a/arch/xtensa/core/gdbstub.c b/arch/xtensa/core/gdbstub.c index 91a1d58f801..236df1c52cc 100644 --- a/arch/xtensa/core/gdbstub.c +++ b/arch/xtensa/core/gdbstub.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -178,11 +179,20 @@ static void read_sreg(struct gdb_ctx *ctx, struct xtensa_register *reg) break; #endif #if XCHAL_HAVE_WINDOWED + /* + * Returning 0 for WINDOWBASE and 1 for WINDOWSTART. This is + * effectively telling GDB that only A0-A3 and AR0-AR3 contain + * active data and other physical registers do not. GDB then + * must rely on spilled values on stack. Otherwise, GDB will try + * to look at all AR* registers for previous frame(s). Since we + * do not save all AR* register values, there is nothing for + * GDB to look at, and thus failing to unwind stack. + */ case WINDOWBASE: - val = get_one_sreg(WINDOWBASE); + val = 0; break; case WINDOWSTART: - val = get_one_sreg(WINDOWSTART); + val = 1; break; #endif #if XCHAL_NUM_INTLEVELS > 0 @@ -426,8 +436,18 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) { struct xtensa_register *reg; int idx, num_laddr_regs; + int32_t a0save; + + /* Need to spill all registers so their values are on the stack instead of + * the physical register file. This is required for GDB backtracing to + * walk through stack. + */ + __asm__ volatile("mov %0, a0;" + "call0 xtensa_spill_reg_windows;" + "mov a0, %0" + : "=r"(a0save)); - uint32_t *bsa = *(const int **)stack; + const uint32_t *bsa = *(const int **)stack; if (bsa - (const uint32_t *)stack > 12) { num_laddr_regs = 16; @@ -446,11 +466,10 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) if (reg->regno == SOC_GDB_REGNO_A1) { /* A1 is calculated */ reg->val = POINTER_TO_UINT(((char *)bsa) + sizeof(_xtensa_irq_bsa_t)); - reg->seqno = ctx->seqno; } else { reg->val = bsa[reg->stack_offset / 4]; - reg->seqno = ctx->seqno; } + reg->seqno = ctx->seqno; } /* For registers other than logical address registers */ @@ -470,26 +489,13 @@ static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack) } #if XCHAL_HAVE_WINDOWED - uint8_t a0_idx, ar_idx, wb_start; - - wb_start = (uint8_t)xtensa_gdb_ctx.regs[xtensa_gdb_ctx.wb_idx].val; + uint8_t a0_idx, ar_idx; - /* - * Copied the logical registers A0-A15 to physical registers (AR*) - * according to WINDOWBASE. - */ + /* Copied the logical registers A0-A15 to physical registers AR0-AR15. */ for (idx = 0; idx < num_laddr_regs; idx++) { - /* Index to register description array for A */ + /* Index to register description array for A and AR */ a0_idx = xtensa_gdb_ctx.a0_idx + idx; - - /* Find the start of window (== WINDOWBASE * 4) */ - ar_idx = wb_start * 4; - /* Which logical register we are working on... */ - ar_idx += idx; - /* Wrap around A64 (or A32) -> A0 */ - ar_idx %= XCHAL_NUM_AREGS; - /* Index to register description array for AR */ - ar_idx += xtensa_gdb_ctx.ar_idx; + ar_idx = xtensa_gdb_ctx.ar_idx + idx; xtensa_gdb_ctx.regs[ar_idx].val = xtensa_gdb_ctx.regs[a0_idx].val; xtensa_gdb_ctx.regs[ar_idx].seqno = xtensa_gdb_ctx.regs[a0_idx].seqno; @@ -592,8 +598,52 @@ void arch_gdb_continue(void) void arch_gdb_step(void) { + uint32_t ps = xtensa_gdb_ctx.regs[xtensa_gdb_ctx.ps_idx].val; + uint32_t intlevel = ps & PS_INTLEVEL_MASK; + bool excm = (ps & PS_EXCM_MASK) != 0; + uint32_t icountlevel; + + /* Avoid counting while in this function. */ + set_one_sreg(ICOUNT, 0); + set_one_sreg(ICOUNTLEVEL, 0); + + /* + * Note that ICOUNT only increments when current interrupt level + * is less then ICOUNTLEVEL, and that ICOUNT interrupt is triggered + * when it reaches zero. + */ + if (excm) { + icountlevel = XCHAL_EXCM_LEVEL + 1; + } else if (arch_curr_cpu()->nested > 1) { + /* + * ICOUNT, IBREAK and DBREAK all trigger interrupts. + * So we need to account for nested being 1 when we + * are running GDB stub. If nested is higher than one, + * this means we are debugging inside ISRs. + */ + icountlevel = intlevel + 1; + + /* + * PS.INTLEVEL would be zero when it is level-1 interrupts. + * A simple +1 does not work as ICOUNT would not stop inside + * the ISR. So we need to up the ICOUNTLEVEL. + */ + icountlevel = MAX(icountlevel, 2); + + /* + * Make sure instructions are only counted below debug + * interrupt level, or else ICOUNT would increment while + * we are working in this function. + */ + icountlevel = MIN(icountlevel, XCHAL_DEBUGLEVEL); + } else { + /* Will break in non-ISR, normal code execution. */ + icountlevel = 1; + } + set_one_sreg(ICOUNT, 0xFFFFFFFEU); - set_one_sreg(ICOUNTLEVEL, XCHAL_DEBUGLEVEL); + set_one_sreg(ICOUNTLEVEL, icountlevel); + __asm__ volatile("isync"); } @@ -704,13 +754,18 @@ size_t arch_gdb_reg_readone(struct gdb_ctx *ctx, uint8_t *buf, size_t buflen, int idx; size_t ret; - ret = 0; + buf[0] = 'x'; + buf[1] = 'x'; + ret = 2; for (idx = 0; idx < ctx->num_regs; idx++) { reg = &ctx->regs[idx]; /* - * GDB sends the G-packet index as register number - * instead of the actual Xtensa register number. + * Some GDB versions send the G-packet index as register number + * instead of the actual Xtensa register number. After checking + * 4 GDB versions one of them (Zephyr SDK for ESP32) sent the + * index while the others (Zephyr SDK for TGL and Cadence + * toolchain for TGL and MTL) sent register numbers. */ if (reg->idx == regno) { if (reg->seqno != ctx->seqno) { @@ -761,9 +816,8 @@ size_t arch_gdb_reg_writeone(struct gdb_ctx *ctx, uint8_t *hex, size_t hexlen, reg = &ctx->regs[idx]; /* - * Remember GDB sends index number instead of - * actual register number (as defined in Xtensa - * architecture). + * Remember some GDB versions send index number instead of + * actual register number (as defined in Xtensa architecture). */ if (reg->idx != regno) { continue; @@ -955,10 +1009,9 @@ void arch_gdb_init(void) /* AR0: 0x0100 */ xtensa_gdb_ctx.ar_idx = idx; break; - case (XTREG_GRP_SPECIAL + WINDOWBASE): - /* WINDOWBASE (Special Register) */ - xtensa_gdb_ctx.wb_idx = idx; - break; + case 0x02E6: + /* PS: 0x02E6 */ + xtensa_gdb_ctx.ps_idx = idx; default: break; }; @@ -985,3 +1038,35 @@ void arch_gdb_init(void) */ __asm__ volatile ("_break.n 0"); } + +void arch_gdb_post_memory_write(uintptr_t addr, size_t len, uint8_t align) +{ + ARG_UNUSED(addr); + ARG_UNUSED(len); + ARG_UNUSED(align); + +#if defined(CONFIG_ICACHE) && defined(CONFIG_DCACHE) + /* + * Note that a GDB memory write can write to code memory to + * insert breakpoints. We need to deal with this here so + * that the instruction cache can actually see the modified + * instructions. + * + * According to the ISA manual, after writing the instructions: + * 1. Flush the data cache so the modified instructions are + * in the main memory. + * 2. Do ISYNC or MEMW or both (depending on which part of + * manual you are reading). + * 3. Invalidate the instruction cache corresponding to + * the modified memory. + * 4. Do another ISYNC. + */ + arch_dcache_flush_range((__sparse_force void __sparse_cache *)addr, len); + + __asm__ volatile("isync; memw"); + + arch_icache_invd_range((__sparse_force void __sparse_cache *)addr, len); + + __asm__ volatile("isync"); +#endif /* CONFIG_ICACHE && CONFIG_DCACHE */ +} diff --git a/arch/xtensa/core/irq_manage.c b/arch/xtensa/core/irq_manage.c index 576eb6e62bb..e12134468dd 100644 --- a/arch/xtensa/core/irq_manage.c +++ b/arch/xtensa/core/irq_manage.c @@ -74,6 +74,28 @@ void z_irq_spurious(const void *arg) __asm__ volatile("rsr.intenable %0" : "=r"(ie)); LOG_ERR(" ** Spurious INTERRUPT(s) %p, INTENABLE = %p", (void *)irqs, (void *)ie); + +#if XCHAL_NUM_INTERRUPTS > 32 + __asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); + __asm__ volatile("rsr.intenable1 %0" : "=r"(ie)); + LOG_ERR(" ** Spurious INTERRUPT1(s) %p, INTENABLE1 = %p", + (void *)irqs, (void *)ie); +#endif + +#if XCHAL_NUM_INTERRUPTS > 64 + __asm__ volatile("rsr.interrupt2 %0" : "=r"(irqs)); + __asm__ volatile("rsr.intenable2 %0" : "=r"(ie)); + LOG_ERR(" ** Spurious INTERRUPT2(s) %p, INTENABLE2 = %p", + (void *)irqs, (void *)ie); +#endif + +#if XCHAL_NUM_INTERRUPTS > 96 + __asm__ volatile("rsr.interrupt3 %0" : "=r"(irqs)); + __asm__ volatile("rsr.intenable3 %0" : "=r"(ie)); + LOG_ERR(" ** Spurious INTERRUPT3(s) %p, INTENABLE3 = %p", + (void *)irqs, (void *)ie); +#endif + xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); } @@ -81,7 +103,30 @@ int xtensa_irq_is_enabled(unsigned int irq) { uint32_t ie; +#if XCHAL_NUM_INTERRUPTS > 32 + switch (irq >> 5) { + case 0: + __asm__ volatile("rsr.intenable %0" : "=r"(ie)); + break; + case 1: + __asm__ volatile("rsr.intenable1 %0" : "=r"(ie)); + break; +#if XCHAL_NUM_INTERRUPTS > 64 + case 2: + __asm__ volatile("rsr.intenable2 %0" : "=r"(ie)); + break; +#endif +#if XCHAL_NUM_INTERRUPTS > 96 + case 3: + __asm__ volatile("rsr.intenable3 %0" : "=r"(ie)); + break; +#endif + default: + break; + } +#else __asm__ volatile("rsr.intenable %0" : "=r"(ie)); +#endif - return (ie & (1 << irq)) != 0U; + return (ie & (1 << (irq & 31U))) != 0U; } diff --git a/arch/xtensa/core/irq_offload.c b/arch/xtensa/core/irq_offload.c index 0e83520c809..00e92e2c5e1 100644 --- a/arch/xtensa/core/irq_offload.c +++ b/arch/xtensa/core/irq_offload.c @@ -31,10 +31,63 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) offload_params[cpu_id].fn = routine; offload_params[cpu_id].arg = parameter; - __asm__ volatile("rsr %0, INTENABLE" : "=r"(intenable)); - intenable |= BIT(ZSR_IRQ_OFFLOAD_INT); - __asm__ volatile("wsr %0, INTENABLE; wsr %0, INTSET; rsync" - :: "r"(intenable), "r"(BIT(ZSR_IRQ_OFFLOAD_INT))); +#if XCHAL_NUM_INTERRUPTS > 32 + switch ((ZSR_IRQ_OFFLOAD_INT) >> 5) { + case 0: + __asm__ volatile("rsr.intenable %0" : "=r"(intenable)); + break; + case 1: + __asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); + break; +#if XCHAL_NUM_INTERRUPTS > 64 + case 2: + __asm__ volatile("rsr.intenable2 %0" : "=r"(intenable)); + break; +#endif +#if XCHAL_NUM_INTERRUPTS > 96 + case 3: + __asm__ volatile("rsr.intenable3 %0" : "=r"(intenable)); + break; +#endif + default: + break; + } +#else + __asm__ volatile("rsr.intenable %0" : "=r"(intenable)); +#endif + + intenable |= BIT((ZSR_IRQ_OFFLOAD_INT & 31U)); + +#if XCHAL_NUM_INTERRUPTS > 32 + switch ((ZSR_IRQ_OFFLOAD_INT) >> 5) { + case 0: + __asm__ volatile("wsr.intenable %0; wsr.intset %0; rsync" + :: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U)))); + break; + case 1: + __asm__ volatile("wsr.intenable1 %0; wsr.intset1 %0; rsync" + :: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U)))); + break; +#if XCHAL_NUM_INTERRUPTS > 64 + case 2: + __asm__ volatile("wsr.intenable2 %0; wsr.intset2 %0; rsync" + :: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U)))); + break; +#endif +#if XCHAL_NUM_INTERRUPTS > 96 + case 3: + __asm__ volatile("wsr.intenable3 %0; wsr.intset3 %0; rsync" + :: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U)))); + break; +#endif + default: + break; + } +#else + __asm__ volatile("wsr.intenable %0; wsr.intset %0; rsync" + :: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U)))); +#endif + arch_irq_unlock(key); } diff --git a/arch/xtensa/core/mpu.c b/arch/xtensa/core/mpu.c index 09385323dc7..80d7075db13 100644 --- a/arch/xtensa/core/mpu.c +++ b/arch/xtensa/core/mpu.c @@ -1078,7 +1078,7 @@ int arch_buffer_validate(const void *addr, size_t size, int write) return ret; } -bool xtensa_mem_kernel_has_access(void *addr, size_t size, int write) +bool xtensa_mem_kernel_has_access(const void *addr, size_t size, int write) { uintptr_t aligned_addr; size_t aligned_size, addr_offset; diff --git a/arch/xtensa/core/offsets/offsets.c b/arch/xtensa/core/offsets/offsets.c index f0b75c999cc..9edf341b7a7 100644 --- a/arch/xtensa/core/offsets/offsets.c +++ b/arch/xtensa/core/offsets/offsets.c @@ -61,7 +61,7 @@ GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu14); GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu15); #endif -#if defined(CONFIG_XTENSA_HIFI_SHARING) +#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING) GEN_OFFSET_SYM(_xtensa_irq_bsa_t, hifi); #endif diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c index b66a9bc30f1..976d5cf5a86 100644 --- a/arch/xtensa/core/ptables.c +++ b/arch/xtensa/core/ptables.c @@ -1112,7 +1112,7 @@ static int mem_buffer_validate(const void *addr, size_t size, int write, int rin return ret; } -bool xtensa_mem_kernel_has_access(void *addr, size_t size, int write) +bool xtensa_mem_kernel_has_access(const void *addr, size_t size, int write) { return mem_buffer_validate(addr, size, write, XTENSA_MMU_KERNEL_RING) == 0; } diff --git a/arch/xtensa/core/semihost.c b/arch/xtensa/core/semihost.c new file mode 100644 index 00000000000..762ae9f3f58 --- /dev/null +++ b/arch/xtensa/core/semihost.c @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2022 Intel Corporation. + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "semihost_types.h" + +#define XTENSA_SEMIHOST_OPEN (-2) +#define XTENSA_SEMIHOST_CLOSE (-3) +#define XTENSA_SEMIHOST_READ (-4) +#define XTENSA_SEMIHOST_WRITE (-5) +#define XTENSA_SEMIHOST_LSEEK (-6) +#define XTENSA_SEMIHOST_RENAME (-7) +#define XTENSA_SEMIHOST_FSTAT (-10) + +enum semihost_open_flag { + SEMIHOST_RDONLY = 0x0, + SEMIHOST_WRONLY = 0x1, + SEMIHOST_RDWR = 0x2, + SEMIHOST_APPEND = 0x8, + SEMIHOST_CREAT = 0x200, + SEMIHOST_TRUNC = 0x400, + SEMIHOST_EXCL = 0x800, +}; + +uint32_t semihost_flags(enum semihost_open_mode mode) +{ + uint32_t flags = 0; + + switch (mode) { + case SEMIHOST_OPEN_R: + case SEMIHOST_OPEN_RB: + flags = SEMIHOST_RDONLY; + break; + case SEMIHOST_OPEN_R_PLUS: + case SEMIHOST_OPEN_RB_PLUS: + flags = SEMIHOST_RDWR; + break; + case SEMIHOST_OPEN_W: + case SEMIHOST_OPEN_WB: + flags = SEMIHOST_WRONLY | SEMIHOST_CREAT | SEMIHOST_TRUNC; + break; + case SEMIHOST_OPEN_W_PLUS: + case SEMIHOST_OPEN_WB_PLUS: + flags = SEMIHOST_RDWR | SEMIHOST_CREAT | SEMIHOST_TRUNC; + break; + case SEMIHOST_OPEN_A: + case SEMIHOST_OPEN_AB: + flags = SEMIHOST_WRONLY | SEMIHOST_CREAT | SEMIHOST_APPEND; + break; + case SEMIHOST_OPEN_A_PLUS: + case SEMIHOST_OPEN_AB_PLUS: + flags = SEMIHOST_RDWR | SEMIHOST_CREAT | SEMIHOST_APPEND; + break; + default: + return -1; + } + + return flags; +} + +uint32_t semihost_mode(enum semihost_open_mode mode) +{ + switch (mode) { + case SEMIHOST_OPEN_W: + case SEMIHOST_OPEN_WB: + case SEMIHOST_OPEN_W_PLUS: + case SEMIHOST_OPEN_WB_PLUS: + case SEMIHOST_OPEN_A: + case SEMIHOST_OPEN_AB: + case SEMIHOST_OPEN_A_PLUS: + case SEMIHOST_OPEN_AB_PLUS: + /* Octal 0600, S_IRUSR | S_IWUSR */ + return 0x180; + default: + return 0; + } +} + +static inline uintptr_t xtensa_semihost_call_4(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, + uintptr_t arg4, uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + register uintptr_t a3 __asm__("%a3") = arg2; + register uintptr_t a4 __asm__("%a4") = arg3; + register uintptr_t a5 __asm__("%a5") = arg4; + + __asm__ volatile("break 1, 14\n\t" + : "=r"(a2) + : "r"(a2), "r"(a6), "r"(a3), "r"(a4), "r"(a5) + : "memory"); + + return a2; +} + +static inline uintptr_t xtensa_semihost_call_3(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, + uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + register uintptr_t a3 __asm__("%a3") = arg2; + register uintptr_t a4 __asm__("%a4") = arg3; + + __asm__ volatile("break 1, 14\n\t" + : "=r"(a2) + : "r"(a2), "r"(a6), "r"(a3), "r"(a4) + : "memory"); + + return a2; +} + +static inline uintptr_t xtensa_semihost_call_2(uintptr_t arg1, uintptr_t arg2, uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + register uintptr_t a3 __asm__("%a3") = arg2; + + __asm__ volatile("break 1, 14\n\t" : "=r"(a2) : "r"(a2), "r"(a6), "r"(a3) : "memory"); + + return a2; +} + +static inline uintptr_t xtensa_semihost_call_1(uintptr_t arg1, uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + + __asm__ volatile("break 1, 14\n\t" : "=r"(a2) : "r"(a2), "r"(a6) : "memory"); + + return a2; +} + +long xtensa_semihost_open(struct semihost_open_args *args) +{ + return xtensa_semihost_call_4((uintptr_t)args->path, semihost_flags(args->mode), + semihost_mode(args->mode), args->path_len, + XTENSA_SEMIHOST_OPEN); +} + +long xtensa_semihost_close(long fd) +{ + return xtensa_semihost_call_1(fd, XTENSA_SEMIHOST_CLOSE); +} + +long xtensa_semihost_write(long fd, const char *buf, long len) +{ + long ret; + + ret = (long)xtensa_semihost_call_3(fd, (uintptr_t)buf, len, XTENSA_SEMIHOST_WRITE); + + /* semihost_write assumes that data was written successfully if ret == 0. */ + if (ret == len) { + return 0; + } + + return -1; +} + +long xtensa_semihost_read(long fd, void *buf, long len) +{ + long ret; + + ret = (long)xtensa_semihost_call_3(fd, (uintptr_t)buf, len, XTENSA_SEMIHOST_READ); + + /* semihost_read assumes that all bytes were read if ret == 0. + * If ret == len, it means EOF was reached. + */ + if (ret == len) { + return 0; + } else if (ret <= 0) { + return len; + } else { + return ret; + } +} + +long xtensa_semihost_read_char(long fd) +{ + char c = 0; + + xtensa_semihost_call_3(fd, (uintptr_t)&c, 1, XTENSA_SEMIHOST_READ); + + return (long)c; +} + +long xtensa_semihost_seek(struct semihost_seek_args *args) +{ + long ret; + + ret = (long)xtensa_semihost_call_3(args->fd, args->offset, 0, XTENSA_SEMIHOST_LSEEK); + + if (ret == args->offset) { + return 0; + } + + return ret; +} + +long xtensa_semihost_flen(long fd) +{ + uint8_t buf[64] = {0}; + long ret; + + ret = (long)xtensa_semihost_call_2(fd, (uintptr_t)buf, XTENSA_SEMIHOST_FSTAT); + if (ret < 0) { + return -1; + } + + /* Struct stat is 64 bytes, bytes 28-35 correspond to st_size + * field. 8-bytes cannot fit into long data type so return + * only the lower 4 bytes. + */ + ret = *((long *)&buf[32]); + + return sys_be32_to_cpu(ret); +} + +long semihost_exec(enum semihost_instr instr, void *args) +{ + switch (instr) { + case SEMIHOST_OPEN: + return xtensa_semihost_open((struct semihost_open_args *)args); + case SEMIHOST_CLOSE: + return xtensa_semihost_close(((struct semihost_close_args *)args)->fd); + case SEMIHOST_WRITEC: + return xtensa_semihost_write(1, (char *)args, 1); + case SEMIHOST_WRITE: + return xtensa_semihost_write(((struct semihost_write_args *)args)->fd, + ((struct semihost_write_args *)args)->buf, + ((struct semihost_write_args *)args)->len); + case SEMIHOST_READ: + return xtensa_semihost_read(((struct semihost_read_args *)args)->fd, + ((struct semihost_read_args *)args)->buf, + ((struct semihost_read_args *)args)->len); + case SEMIHOST_READC: + return xtensa_semihost_read_char(((struct semihost_poll_in_args *)args)->zero); + case SEMIHOST_SEEK: + return xtensa_semihost_seek((struct semihost_seek_args *)args); + case SEMIHOST_FLEN: + return xtensa_semihost_flen(((struct semihost_flen_args *)args)->fd); + default: + return -1; + } +} diff --git a/arch/xtensa/core/startup/reset_vector.S b/arch/xtensa/core/startup/reset_vector.S index 21f4b25e77e..9d65da9b858 100644 --- a/arch/xtensa/core/startup/reset_vector.S +++ b/arch/xtensa/core/startup/reset_vector.S @@ -150,7 +150,16 @@ _ResetHandler: /* make sure that interrupts are shut off (*before* we lower * PS.INTLEVEL and PS.EXCM!) */ - wsr a0, INTENABLE + wsr.intenable a0 +#if (XCHAL_NUM_INTERRUPTS > 32) + wsr.intenable1 a0 +#endif +#if (XCHAL_NUM_INTERRUPTS > 64) + wsr.intenable2 a0 +#endif +#if (XCHAL_NUM_INTERRUPTS > 96) + wsr.intenable3 a0 +#endif #endif #if !XCHAL_HAVE_FULL_RESET @@ -566,7 +575,17 @@ unpackdone: * all CPENABLE bits must be set, even though they may not always * correspond to a coprocessor. */ +#ifdef CONFIG_XTENSA_LAZY_HIFI_SHARING + /* + * Disable HiFi coprocessor by default. Should a thread try using + * the HiFi coprocessor, it will trigger an exception to both enable + * it AND save/restore the HiFi state. + */ + + movi a2, 0xFF & ~(1 << XCHAL_CP_ID_AUDIOENGINELX) +#else movi a2, 0xFF /* enable *all* bits, to allow dynamic TIE */ +#endif wsr a2, CPENABLE # endif diff --git a/arch/xtensa/core/syscall_helper.c b/arch/xtensa/core/syscall_helper.c index 9e14a560e7e..345a011022b 100644 --- a/arch/xtensa/core/syscall_helper.c +++ b/arch/xtensa/core/syscall_helper.c @@ -7,8 +7,8 @@ #include #include - #include +#include #include #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER @@ -33,6 +33,7 @@ uintptr_t xtensa_syscall_helper_args_6(uintptr_t arg1, uintptr_t arg2, return a2; } +EXPORT_SYMBOL(xtensa_syscall_helper_args_6); uintptr_t xtensa_syscall_helper_args_5(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, @@ -53,6 +54,7 @@ uintptr_t xtensa_syscall_helper_args_5(uintptr_t arg1, uintptr_t arg2, return a2; } +EXPORT_SYMBOL(xtensa_syscall_helper_args_5); uintptr_t xtensa_syscall_helper_args_4(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, @@ -72,6 +74,7 @@ uintptr_t xtensa_syscall_helper_args_4(uintptr_t arg1, uintptr_t arg2, return a2; } +EXPORT_SYMBOL(xtensa_syscall_helper_args_4); #endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */ @@ -115,7 +118,7 @@ size_t arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg) * For MPU systems, this would simply results in access errors * and the exception handler will terminate the thread. */ - if (!xtensa_mem_kernel_has_access((void *)s, maxsize, 0)) { + if (arch_buffer_validate(s, maxsize, 0)) { /* * API says we need to set err_arg to -1 if there are * any errors. diff --git a/arch/xtensa/core/thread.c b/arch/xtensa/core/thread.c index 2bf1a7e11d3..f615ccd6ada 100644 --- a/arch/xtensa/core/thread.c +++ b/arch/xtensa/core/thread.c @@ -120,6 +120,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, { thread->switch_handle = init_stack(thread, (int *)stack_ptr, entry, p1, p2, p3); +#ifdef CONFIG_XTENSA_LAZY_HIFI_SHARING + memset(thread->arch.hifi_regs, 0, sizeof(thread->arch.hifi_regs)); +#endif /* CONFIG_XTENSA_LAZY_HIFI_SHARING */ + #ifdef CONFIG_KERNEL_COHERENCE __ASSERT((((size_t)stack) % XCHAL_DCACHE_LINESIZE) == 0, ""); __ASSERT((((size_t)stack_ptr) % XCHAL_DCACHE_LINESIZE) == 0, ""); @@ -130,17 +134,65 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) int arch_float_disable(struct k_thread *thread) { + ARG_UNUSED(thread); /* xtensa always has FPU enabled so cannot be disabled */ return -ENOTSUP; } int arch_float_enable(struct k_thread *thread, unsigned int options) { + ARG_UNUSED(thread); + ARG_UNUSED(options); /* xtensa always has FPU enabled so nothing to do here */ return 0; } #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ + +#if defined(CONFIG_XTENSA_LAZY_HIFI_SHARING) +void xtensa_hifi_disown(struct k_thread *thread) +{ + unsigned int cpu_id = 0; + struct k_thread *owner; + +#if CONFIG_MP_MAX_NUM_CPUS > 1 + cpu_id = thread->base.cpu; +#endif + + owner = atomic_ptr_get(&_kernel.cpus[cpu_id].arch.hifi_owner); + + if (owner == thread) { + atomic_ptr_set(&_kernel.cpus[cpu_id].arch.hifi_owner, NULL); + } +} +#endif + +int arch_coprocessors_disable(struct k_thread *thread) +{ + bool enotsup = true; + +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + arch_float_disable(thread); + enotsup = false; +#endif + +#if defined(CONFIG_XTENSA_LAZY_HIFI_SHARING) + xtensa_hifi_disown(thread); + + /* + * This routine is only called when aborting a thread and we + * deliberately do not disable the HiFi coprocessor here. + * 1. Such disabling can only be done for the current CPU, and we do + * not have control over which CPU the thread is running on. + * 2. If the thread (being deleted) is a currently executing thread, + * there will be a context switch to another thread and that CPU + * will automatically disable the HiFi coprocessor upon the switch. + */ + enotsup = false; +#endif + return enotsup ? -ENOTSUP : 0; +} + #ifdef CONFIG_USERSPACE FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, void *p1, void *p2, void *p3) diff --git a/arch/xtensa/core/vector_handlers.c b/arch/xtensa/core/vector_handlers.c index fa58b9c2133..abbf2615eae 100644 --- a/arch/xtensa/core/vector_handlers.c +++ b/arch/xtensa/core/vector_handlers.c @@ -31,6 +31,16 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); extern char xtensa_arch_except_epc[]; extern char xtensa_arch_kernel_oops_epc[]; +extern void xtensa_lazy_hifi_save(uint8_t *regs); +extern void xtensa_lazy_hifi_load(uint8_t *regs); + +#if defined(CONFIG_XTENSA_LAZY_HIFI_SHARING) && (CONFIG_MP_MAX_NUM_CPUS > 1) +#define LAZY_COPROCESSOR_LOCK + +static struct k_spinlock coprocessor_lock; +#endif + + bool xtensa_is_outside_stack_bounds(uintptr_t addr, size_t sz, uint32_t ps) { uintptr_t start, end; @@ -153,13 +163,13 @@ void xtensa_dump_stack(const void *stack) bsa = frame->ptr_to_bsa; /* Calculate number of high registers. */ - num_high_regs = (uint8_t *)bsa - (uint8_t *)frame + sizeof(void *); + num_high_regs = (uint8_t *)bsa - ((uint8_t *)frame + sizeof(void *)); num_high_regs /= sizeof(uintptr_t); /* And high registers are always comes in 4 in a block. */ reg_blks_remaining = (int)num_high_regs / 4; - LOG_ERR(" ** A0 %p SP %p A2 %p A3 %p", + EXCEPTION_DUMP(" ** A0 %p SP %p A2 %p A3 %p", (void *)bsa->a0, (void *)((char *)bsa + sizeof(*bsa)), (void *)bsa->a2, (void *)bsa->a3); @@ -167,7 +177,7 @@ void xtensa_dump_stack(const void *stack) if (reg_blks_remaining > 0) { reg_blks_remaining--; - LOG_ERR(" ** A4 %p A5 %p A6 %p A7 %p", + EXCEPTION_DUMP(" ** A4 %p A5 %p A6 %p A7 %p", (void *)frame->blks[reg_blks_remaining].r0, (void *)frame->blks[reg_blks_remaining].r1, (void *)frame->blks[reg_blks_remaining].r2, @@ -177,7 +187,7 @@ void xtensa_dump_stack(const void *stack) if (reg_blks_remaining > 0) { reg_blks_remaining--; - LOG_ERR(" ** A8 %p A9 %p A10 %p A11 %p", + EXCEPTION_DUMP(" ** A8 %p A9 %p A10 %p A11 %p", (void *)frame->blks[reg_blks_remaining].r0, (void *)frame->blks[reg_blks_remaining].r1, (void *)frame->blks[reg_blks_remaining].r2, @@ -187,7 +197,7 @@ void xtensa_dump_stack(const void *stack) if (reg_blks_remaining > 0) { reg_blks_remaining--; - LOG_ERR(" ** A12 %p A13 %p A14 %p A15 %p", + EXCEPTION_DUMP(" ** A12 %p A13 %p A14 %p A15 %p", (void *)frame->blks[reg_blks_remaining].r0, (void *)frame->blks[reg_blks_remaining].r1, (void *)frame->blks[reg_blks_remaining].r2, @@ -195,16 +205,16 @@ void xtensa_dump_stack(const void *stack) } #if XCHAL_HAVE_LOOPS - LOG_ERR(" ** LBEG %p LEND %p LCOUNT %p", + EXCEPTION_DUMP(" ** LBEG %p LEND %p LCOUNT %p", (void *)bsa->lbeg, (void *)bsa->lend, (void *)bsa->lcount); #endif - LOG_ERR(" ** SAR %p", (void *)bsa->sar); + EXCEPTION_DUMP(" ** SAR %p", (void *)bsa->sar); #if XCHAL_HAVE_THREADPTR - LOG_ERR(" ** THREADPTR %p", (void *)bsa->threadptr); + EXCEPTION_DUMP(" ** THREADPTR %p", (void *)bsa->threadptr); #endif } @@ -227,12 +237,12 @@ static void print_fatal_exception(void *print_stack, int cause, __asm__ volatile("rsr.excvaddr %0" : "=r"(vaddr)); if (is_dblexc) { - LOG_ERR(" ** FATAL EXCEPTION (DOUBLE)"); + EXCEPTION_DUMP(" ** FATAL EXCEPTION (DOUBLE)"); } else { - LOG_ERR(" ** FATAL EXCEPTION"); + EXCEPTION_DUMP(" ** FATAL EXCEPTION"); } - LOG_ERR(" ** CPU %d EXCCAUSE %d (%s)", + EXCEPTION_DUMP(" ** CPU %d EXCCAUSE %d (%s)", arch_curr_cpu()->id, cause, xtensa_exccause(cause)); @@ -241,21 +251,21 @@ static void print_fatal_exception(void *print_stack, int cause, * Or worse, cause another access violation. */ if (xtensa_is_outside_stack_bounds((uintptr_t)bsa, sizeof(*bsa), UINT32_MAX)) { - LOG_ERR(" ** VADDR %p Invalid SP %p", (void *)vaddr, print_stack); + EXCEPTION_DUMP(" ** VADDR %p Invalid SP %p", (void *)vaddr, print_stack); return; } ps = bsa->ps; pc = (void *)bsa->pc; - LOG_ERR(" ** PC %p VADDR %p", pc, (void *)vaddr); + EXCEPTION_DUMP(" ** PC %p VADDR %p", pc, (void *)vaddr); if (is_dblexc) { - LOG_ERR(" ** DEPC %p", (void *)depc); + EXCEPTION_DUMP(" ** DEPC %p", (void *)depc); } - LOG_ERR(" ** PS %p", (void *)bsa->ps); - LOG_ERR(" ** (INTLEVEL:%d EXCM: %d UM:%d RING:%d WOE:%d OWB:%d CALLINC:%d)", + EXCEPTION_DUMP(" ** PS %p", (void *)bsa->ps); + EXCEPTION_DUMP(" ** (INTLEVEL:%d EXCM: %d UM:%d RING:%d WOE:%d OWB:%d CALLINC:%d)", get_bits(0, 4, ps), get_bits(4, 1, ps), get_bits(5, 1, ps), get_bits(6, 2, ps), get_bits(18, 1, ps), @@ -279,6 +289,88 @@ static inline void *return_to(void *interrupted) #endif /* CONFIG_MULTITHREADING */ } +#if defined(LAZY_COPROCESSOR_LOCK) +/** + * Spin until thread is no longer the HiFi owner on specified CPU. + * Note: Interrupts are locked on entry. Unlock before spinning to allow + * an IPI to be caught and processed; restore them afterwards. + */ +static void spin_while_hifi_owner(struct _cpu *cpu, struct k_thread *thread) +{ + unsigned int key; + unsigned int original; + unsigned int unlocked; + + __asm__ volatile("rsr.ps %0" : "=r"(original)); + unlocked = original & ~PS_INTLEVEL_MASK; + __asm__ volatile("wsr.ps %0; rsync" :: "r"(unlocked) : "memory"); + + /* Spin until thread is no longer the HiFi owner on the other CPU */ + + while ((struct k_thread *) + atomic_ptr_get(&cpu->arch.hifi_owner) == thread) { + key = arch_irq_lock(); + arch_spin_relax(); + arch_irq_unlock(key); + } + + __asm__ volatile("wsr.ps %0; rsync" :: "r"(original) : "memory"); +} + +/** + * Determine if the thread is the owner of a HiFi on another CPU. This is + * called with the coprocessor lock held + */ +static struct _cpu *thread_hifi_owner_elsewhere(struct k_thread *thread) +{ + struct _cpu *this_cpu = arch_curr_cpu(); + struct k_thread *owner; + + for (unsigned int i = 0; i < CONFIG_MP_MAX_NUM_CPUS; i++) { + owner = (struct k_thread *) + atomic_ptr_get(&_kernel.cpus[i].arch.hifi_owner); + if ((this_cpu != &_kernel.cpus[i]) && (owner == thread)) { + return &_kernel.cpus[i]; + } + } + return NULL; +} +#endif + +/** + * This routine only needed for SMP systems with HiFi sharing. It handles the + * IPI sent to save the HiFi registers so the owner can load them onto another + * CPU. + */ +void arch_ipi_lazy_coprocessors_save(void) +{ +#if defined(LAZY_COPROCESSOR_LOCK) + k_spinlock_key_t key = k_spin_lock(&coprocessor_lock); + struct _cpu *cpu = arch_curr_cpu(); + struct k_thread *save_hifi = (struct k_thread *) + atomic_ptr_get(&cpu->arch.save_hifi); + struct k_thread *hifi_owner = (struct k_thread *) + atomic_ptr_get(&cpu->arch.hifi_owner); + + if ((save_hifi == hifi_owner) && (save_hifi != NULL)) { + unsigned int cp; + + __asm__ volatile("rsr.cpenable %0" : "=r"(cp)); + cp |= BIT(XCHAL_CP_ID_AUDIOENGINELX); + __asm__ volatile("wsr.cpenable %0" :: "r"(cp)); + + xtensa_lazy_hifi_save(save_hifi->arch.hifi_regs); + + cp &= ~BIT(XCHAL_CP_ID_AUDIOENGINELX); + __asm__ volatile("wsr.cpenable %0" :: "r"(cp)); + + atomic_ptr_set(&cpu->arch.hifi_owner, NULL); + } + atomic_ptr_set(&cpu->arch.save_hifi, NULL); + k_spin_unlock(&coprocessor_lock, key); +#endif +} + /* The wrapper code lives here instead of in the python script that * generates _xtensa_handle_one_int*(). Seems cleaner, still kind of * ugly. @@ -286,20 +378,116 @@ static inline void *return_to(void *interrupted) * This may be unused depending on number of interrupt levels * supported by the SoC. */ -#define DEF_INT_C_HANDLER(l) \ -__unused void *xtensa_int##l##_c(void *interrupted_stack) \ -{ \ - uint32_t irqs, intenable, m; \ - usage_stop(); \ - __asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \ + +#if XCHAL_NUM_INTERRUPTS <= 32 +#define DEF_INT_C_HANDLER(l) \ +__unused void *xtensa_int##l##_c(void *interrupted_stack) \ +{ \ + uint32_t irqs, intenable, m; \ + usage_stop(); \ + __asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \ __asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \ - irqs &= intenable; \ - while ((m = _xtensa_handle_one_int##l(irqs))) { \ - irqs ^= m; \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(0, irqs))) { \ + irqs ^= m; \ __asm__ volatile("wsr.intclear %0" : : "r"(m)); \ - } \ - return return_to(interrupted_stack); \ + } \ + return return_to(interrupted_stack); \ +} +#endif /* XCHAL_NUM_INTERRUPTS <= 32 */ + +#if XCHAL_NUM_INTERRUPTS > 32 && XCHAL_NUM_INTERRUPTS <= 64 +#define DEF_INT_C_HANDLER(l) \ +__unused void *xtensa_int##l##_c(void *interrupted_stack) \ +{ \ + uint32_t irqs, intenable, m; \ + usage_stop(); \ + __asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(0, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear %0" : : "r"(m)); \ + } \ + __asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(1, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \ + } \ + return return_to(interrupted_stack); \ +} +#endif /* XCHAL_NUM_INTERRUPTS > 32 && XCHAL_NUM_INTERRUPTS <= 64 */ + +#if XCHAL_NUM_INTERRUPTS > 64 && XCHAL_NUM_INTERRUPTS <= 96 +#define DEF_INT_C_HANDLER(l) \ +__unused void *xtensa_int##l##_c(void *interrupted_stack) \ +{ \ + uint32_t irqs, intenable, m; \ + usage_stop(); \ + __asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(0, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear %0" : : "r"(m)); \ + } \ + __asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(1, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \ + } \ + __asm__ volatile("rsr.interrupt2 %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable2 %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(2, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear2 %0" : : "r"(m)); \ + } \ + return return_to(interrupted_stack); \ } +#endif /* XCHAL_NUM_INTERRUPTS > 64 && XCHAL_NUM_INTERRUPTS <= 96 */ + +#if XCHAL_NUM_INTERRUPTS > 96 +#define DEF_INT_C_HANDLER(l) \ +__unused void *xtensa_int##l##_c(void *interrupted_stack) \ +{ \ + uint32_t irqs, intenable, m; \ + usage_stop(); \ + __asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(0, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear %0" : : "r"(m)); \ + } \ + __asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(1, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \ + } \ + __asm__ volatile("rsr.interrupt2 %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable2 %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(2, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear2 %0" : : "r"(m)); \ + } \ + __asm__ volatile("rsr.interrupt3 %0" : "=r"(irqs)); \ + __asm__ volatile("rsr.intenable3 %0" : "=r"(intenable)); \ + irqs &= intenable; \ + while ((m = _xtensa_handle_one_int##l(3, irqs))) { \ + irqs ^= m; \ + __asm__ volatile("wsr.intclear3 %0" : : "r"(m)); \ + } \ + return return_to(interrupted_stack); \ +} +#endif /* XCHAL_NUM_INTERRUPTS > 96 */ #if XCHAL_HAVE_NMI #define MAX_INTR_LEVEL XCHAL_NMILEVEL @@ -377,7 +565,7 @@ void *xtensa_excint1_c(void *esf) */ case EXCCAUSE_SYSCALL: /* Just report it to the console for now */ - LOG_ERR(" ** SYSCALL PS %p PC %p", + EXCEPTION_DUMP(" ** SYSCALL PS %p PC %p", (void *)bsa->ps, (void *)bsa->pc); xtensa_dump_stack(interrupted_stack); @@ -388,6 +576,59 @@ void *xtensa_excint1_c(void *esf) bsa->pc += 3; break; #endif /* !CONFIG_USERSPACE */ +#ifdef CONFIG_XTENSA_LAZY_HIFI_SHARING + case EXCCAUSE_CP_DISABLED(XCHAL_CP_ID_AUDIOENGINELX): + /* Identify the interrupted thread and the old HiFi owner */ + struct k_thread *thread = _current; + struct k_thread *owner; + unsigned int cp; + +#if defined(LAZY_COPROCESSOR_LOCK) + /* + * If the interrupted thread is a HiFi owner on another CPU, + * then send an IPI to that CPU to have it save its HiFi state + * and then return. This CPU will continue to raise the current + * exception (and send IPIs) until the other CPU has both saved + * the HiFi registers and cleared its HiFi owner. + */ + + k_spinlock_key_t key = k_spin_lock(&coprocessor_lock); + struct _cpu *cpu = thread_hifi_owner_elsewhere(thread); + + if (cpu != NULL) { + cpu->arch.save_hifi = thread; + arch_sched_directed_ipi(BIT(cpu->id)); + k_spin_unlock(&coprocessor_lock, key); + spin_while_hifi_owner(cpu, thread); + key = k_spin_lock(&coprocessor_lock); + } +#endif + owner = (struct k_thread *) + atomic_ptr_get(&arch_curr_cpu()->arch.hifi_owner); + + /* Enable the HiFi coprocessor */ + __asm__ volatile("rsr.cpenable %0" : "=r"(cp)); + cp |= BIT(XCHAL_CP_ID_AUDIOENGINELX); + __asm__ volatile("wsr.cpenable %0" :: "r"(cp)); + + if (owner == thread) { +#if defined(LAZY_COPROCESSOR_LOCK) + k_spin_unlock(&coprocessor_lock, key); +#endif + break; + } + + if (owner != NULL) { + xtensa_lazy_hifi_save(owner->arch.hifi_regs); + } + + atomic_ptr_set(&arch_curr_cpu()->arch.hifi_owner, thread); +#if defined(LAZY_COPROCESSOR_LOCK) + k_spin_unlock(&coprocessor_lock, key); +#endif + xtensa_lazy_hifi_load(thread->arch.hifi_regs); + break; +#endif /* CONFIG_XTENSA_LAZY_HIFI_SHARING */ default: reason = K_ERR_CPU_EXCEPTION; @@ -453,6 +694,9 @@ void *xtensa_excint1_c(void *esf) #ifndef CONFIG_USERSPACE case EXCCAUSE_SYSCALL: #endif /* !CONFIG_USERSPACE */ +#ifdef CONFIG_XTENSA_LAZY_HIFI_SHARING + case EXCCAUSE_CP_DISABLED(XCHAL_CP_ID_AUDIOENGINELX): +#endif /* CONFIG_XTENSA_LAZY_HIFI_SHARING */ is_fatal_error = false; break; default: diff --git a/arch/xtensa/core/xtensa_asm2_util.S b/arch/xtensa/core/xtensa_asm2_util.S index c488aeee1ce..ffa75bbc3a6 100644 --- a/arch/xtensa/core/xtensa_asm2_util.S +++ b/arch/xtensa/core/xtensa_asm2_util.S @@ -185,7 +185,7 @@ _restore_ps_after: FPU_REG_RESTORE #endif -#if defined(CONFIG_XTENSA_HIFI_SHARING) +#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING) .extern _xtensa_hifi_load call0 _xtensa_hifi_load #endif @@ -305,8 +305,14 @@ xtensa_switch: movi a0, _switch_restore_pc s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET -#if defined(CONFIG_XTENSA_HIFI_SHARING) +#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING) call0 _xtensa_hifi_save +#elif defined(CONFIG_XTENSA_LAZY_HIFI_SHARING) + /* Disable HiFi sharing */ + rsr a6, CPENABLE + movi a7, ~(1 << XCHAL_CP_ID_AUDIOENGINELX) + and a6, a6, a7 + wsr a6, CPENABLE #endif /* Now the high registers */ diff --git a/arch/xtensa/core/xtensa_backtrace.c b/arch/xtensa/core/xtensa_backtrace.c index 145d52ce58d..f4f84e91ad1 100644 --- a/arch/xtensa/core/xtensa_backtrace.c +++ b/arch/xtensa/core/xtensa_backtrace.c @@ -11,7 +11,7 @@ #include #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) #include "debug_helpers.h" -#elif defined(CONFIG_SOC_XTENSA_DC233C) +#elif defined(CONFIG_SOC_XTENSA_DC233C) || defined(CONFIG_SOC_MIMXRT595S_F1) #include "backtrace_helpers.h" #endif @@ -69,6 +69,8 @@ static inline bool xtensa_ptr_executable(const void *p) return intel_adsp_ptr_executable(p); #elif defined(CONFIG_SOC_XTENSA_DC233C) return xtensa_dc233c_ptr_executable(p); +#elif defined(CONFIG_SOC_MIMXRT595S_F1) + return xtensa_mimxrt595s_f1_ptr_executable(p); #else #warning "xtensa_ptr_executable is not defined for this platform" #endif diff --git a/arch/xtensa/core/xtensa_hifi.S b/arch/xtensa/core/xtensa_hifi.S index dff714cce18..6d5524f10d3 100644 --- a/arch/xtensa/core/xtensa_hifi.S +++ b/arch/xtensa/core/xtensa_hifi.S @@ -9,6 +9,7 @@ #include #include +#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING) /* * Load the HiFi registers from the hifi buffer in the BSA. Round the address * of this buffer up to XCHAL_CP1_SA_ALIGN bytes to guarantee the necessary @@ -51,3 +52,32 @@ _xtensa_hifi_save: xchal_cp1_store a2 a3 a3 a3 a3 /* Only A2 and A3 are used by macro */ ret +#elif defined(CONFIG_XTENSA_LAZY_HIFI_SHARING) +/* + * Load the HiFi registers from the HiFi buffer in the k_thread structure. + */ +.global xtensa_lazy_hifi_load +.align 4 +xtensa_lazy_hifi_load: + entry a1, 32 + /* Spill registers onto stack */ + call8 xthal_window_spill + + /* A2 should be address of hifi storage; A3 is scratch */ + xchal_cp1_load a2 a3 a3 a3 a3 + retw + +/* + * Save the HiFi registers to the HiFi buffer in the k_thread structure. + */ +.global xtensa_lazy_hifi_save +.align 4 +xtensa_lazy_hifi_save: + entry a1, 32 + /* Spill registers onto stack */ + call8 xthal_window_spill + + /* A2 should be address of hifi storage; A3 is scratch */ + xchal_cp1_store a2 a3 a3 a3 a3 /* Only A2 and A3 are used by macro */ + retw +#endif diff --git a/arch/xtensa/core/xtensa_intgen.py b/arch/xtensa/core/xtensa_intgen.py index 2770cb4662c..34e3bbdbad8 100755 --- a/arch/xtensa/core/xtensa_intgen.py +++ b/arch/xtensa/core/xtensa_intgen.py @@ -117,7 +117,8 @@ def emit_int_handler(ints): # Emit the handlers for lvl in ints_by_lvl: - cprint("static inline int _xtensa_handle_one_int" + str(lvl) + "(unsigned int mask)") + cprint("static inline int _xtensa_handle_one_int" + + str(lvl) + "(unsigned int set, unsigned int mask)") cprint("{") if not ints_by_lvl[lvl]: @@ -128,11 +129,14 @@ def emit_int_handler(ints): cprint("int irq;") print("") - emit_int_handler(sorted(ints_by_lvl[lvl])) + if int(len(ints_by_lvl[lvl])) > 32: + emit_int_handler((sorted(ints_by_lvl[lvl]))[0:31]) + else: + emit_int_handler(sorted(ints_by_lvl[lvl])) cprint("return 0;") cprint("handle_irq:") - cprint("_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);") + cprint("_sw_isr_table[set * 32 + irq].isr(_sw_isr_table[set * 32 + irq].arg);") cprint("return mask;") cprint("}") cprint("") diff --git a/arch/xtensa/core/xtensa_intgen.tmpl b/arch/xtensa/core/xtensa_intgen.tmpl index fe3741592d3..faca46f5de5 100644 --- a/arch/xtensa/core/xtensa_intgen.tmpl +++ b/arch/xtensa/core/xtensa_intgen.tmpl @@ -41,3 +41,99 @@ __xtensa_int_level_magic__ 28 XCHAL_INT28_LEVEL __xtensa_int_level_magic__ 29 XCHAL_INT29_LEVEL __xtensa_int_level_magic__ 30 XCHAL_INT30_LEVEL __xtensa_int_level_magic__ 31 XCHAL_INT31_LEVEL +__xtensa_int_level_magic__ 32 XCHAL_INT32_LEVEL +__xtensa_int_level_magic__ 33 XCHAL_INT33_LEVEL +__xtensa_int_level_magic__ 34 XCHAL_INT34_LEVEL +__xtensa_int_level_magic__ 35 XCHAL_INT35_LEVEL +__xtensa_int_level_magic__ 36 XCHAL_INT36_LEVEL +__xtensa_int_level_magic__ 37 XCHAL_INT37_LEVEL +__xtensa_int_level_magic__ 38 XCHAL_INT38_LEVEL +__xtensa_int_level_magic__ 39 XCHAL_INT39_LEVEL +__xtensa_int_level_magic__ 40 XCHAL_INT40_LEVEL +__xtensa_int_level_magic__ 41 XCHAL_INT41_LEVEL +__xtensa_int_level_magic__ 42 XCHAL_INT42_LEVEL +__xtensa_int_level_magic__ 43 XCHAL_INT43_LEVEL +__xtensa_int_level_magic__ 44 XCHAL_INT44_LEVEL +__xtensa_int_level_magic__ 45 XCHAL_INT45_LEVEL +__xtensa_int_level_magic__ 46 XCHAL_INT46_LEVEL +__xtensa_int_level_magic__ 47 XCHAL_INT47_LEVEL +__xtensa_int_level_magic__ 48 XCHAL_INT48_LEVEL +__xtensa_int_level_magic__ 49 XCHAL_INT49_LEVEL +__xtensa_int_level_magic__ 50 XCHAL_INT50_LEVEL +__xtensa_int_level_magic__ 51 XCHAL_INT51_LEVEL +__xtensa_int_level_magic__ 52 XCHAL_INT52_LEVEL +__xtensa_int_level_magic__ 53 XCHAL_INT53_LEVEL +__xtensa_int_level_magic__ 54 XCHAL_INT54_LEVEL +__xtensa_int_level_magic__ 55 XCHAL_INT55_LEVEL +__xtensa_int_level_magic__ 56 XCHAL_INT56_LEVEL +__xtensa_int_level_magic__ 57 XCHAL_INT57_LEVEL +__xtensa_int_level_magic__ 58 XCHAL_INT58_LEVEL +__xtensa_int_level_magic__ 59 XCHAL_INT59_LEVEL +__xtensa_int_level_magic__ 60 XCHAL_INT60_LEVEL +__xtensa_int_level_magic__ 61 XCHAL_INT61_LEVEL +__xtensa_int_level_magic__ 62 XCHAL_INT62_LEVEL +__xtensa_int_level_magic__ 63 XCHAL_INT63_LEVEL +__xtensa_int_level_magic__ 64 XCHAL_INT64_LEVEL +__xtensa_int_level_magic__ 65 XCHAL_INT65_LEVEL +__xtensa_int_level_magic__ 66 XCHAL_INT66_LEVEL +__xtensa_int_level_magic__ 67 XCHAL_INT67_LEVEL +__xtensa_int_level_magic__ 68 XCHAL_INT68_LEVEL +__xtensa_int_level_magic__ 69 XCHAL_INT69_LEVEL +__xtensa_int_level_magic__ 70 XCHAL_INT70_LEVEL +__xtensa_int_level_magic__ 71 XCHAL_INT71_LEVEL +__xtensa_int_level_magic__ 72 XCHAL_INT72_LEVEL +__xtensa_int_level_magic__ 73 XCHAL_INT73_LEVEL +__xtensa_int_level_magic__ 74 XCHAL_INT74_LEVEL +__xtensa_int_level_magic__ 75 XCHAL_INT75_LEVEL +__xtensa_int_level_magic__ 76 XCHAL_INT76_LEVEL +__xtensa_int_level_magic__ 77 XCHAL_INT77_LEVEL +__xtensa_int_level_magic__ 78 XCHAL_INT78_LEVEL +__xtensa_int_level_magic__ 79 XCHAL_INT79_LEVEL +__xtensa_int_level_magic__ 80 XCHAL_INT80_LEVEL +__xtensa_int_level_magic__ 81 XCHAL_INT81_LEVEL +__xtensa_int_level_magic__ 82 XCHAL_INT82_LEVEL +__xtensa_int_level_magic__ 83 XCHAL_INT83_LEVEL +__xtensa_int_level_magic__ 84 XCHAL_INT84_LEVEL +__xtensa_int_level_magic__ 85 XCHAL_INT85_LEVEL +__xtensa_int_level_magic__ 86 XCHAL_INT86_LEVEL +__xtensa_int_level_magic__ 87 XCHAL_INT87_LEVEL +__xtensa_int_level_magic__ 88 XCHAL_INT88_LEVEL +__xtensa_int_level_magic__ 89 XCHAL_INT89_LEVEL +__xtensa_int_level_magic__ 90 XCHAL_INT90_LEVEL +__xtensa_int_level_magic__ 91 XCHAL_INT91_LEVEL +__xtensa_int_level_magic__ 92 XCHAL_INT92_LEVEL +__xtensa_int_level_magic__ 93 XCHAL_INT93_LEVEL +__xtensa_int_level_magic__ 94 XCHAL_INT94_LEVEL +__xtensa_int_level_magic__ 95 XCHAL_INT95_LEVEL +__xtensa_int_level_magic__ 96 XCHAL_INT96_LEVEL +__xtensa_int_level_magic__ 97 XCHAL_INT97_LEVEL +__xtensa_int_level_magic__ 98 XCHAL_INT98_LEVEL +__xtensa_int_level_magic__ 99 XCHAL_INT99_LEVEL +__xtensa_int_level_magic__ 100 XCHAL_INT100_LEVEL +__xtensa_int_level_magic__ 101 XCHAL_INT101_LEVEL +__xtensa_int_level_magic__ 102 XCHAL_INT102_LEVEL +__xtensa_int_level_magic__ 103 XCHAL_INT103_LEVEL +__xtensa_int_level_magic__ 104 XCHAL_INT104_LEVEL +__xtensa_int_level_magic__ 105 XCHAL_INT105_LEVEL +__xtensa_int_level_magic__ 106 XCHAL_INT106_LEVEL +__xtensa_int_level_magic__ 107 XCHAL_INT107_LEVEL +__xtensa_int_level_magic__ 108 XCHAL_INT108_LEVEL +__xtensa_int_level_magic__ 109 XCHAL_INT109_LEVEL +__xtensa_int_level_magic__ 110 XCHAL_INT110_LEVEL +__xtensa_int_level_magic__ 111 XCHAL_INT111_LEVEL +__xtensa_int_level_magic__ 112 XCHAL_INT112_LEVEL +__xtensa_int_level_magic__ 113 XCHAL_INT113_LEVEL +__xtensa_int_level_magic__ 114 XCHAL_INT114_LEVEL +__xtensa_int_level_magic__ 115 XCHAL_INT115_LEVEL +__xtensa_int_level_magic__ 116 XCHAL_INT116_LEVEL +__xtensa_int_level_magic__ 117 XCHAL_INT117_LEVEL +__xtensa_int_level_magic__ 118 XCHAL_INT118_LEVEL +__xtensa_int_level_magic__ 119 XCHAL_INT119_LEVEL +__xtensa_int_level_magic__ 120 XCHAL_INT120_LEVEL +__xtensa_int_level_magic__ 121 XCHAL_INT121_LEVEL +__xtensa_int_level_magic__ 122 XCHAL_INT122_LEVEL +__xtensa_int_level_magic__ 123 XCHAL_INT123_LEVEL +__xtensa_int_level_magic__ 124 XCHAL_INT124_LEVEL +__xtensa_int_level_magic__ 125 XCHAL_INT125_LEVEL +__xtensa_int_level_magic__ 126 XCHAL_INT126_LEVEL +__xtensa_int_level_magic__ 127 XCHAL_INT127_LEVEL diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index 8e0641f9d4b..a53a81cb71c 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -278,7 +278,25 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread, static inline bool arch_is_in_isr(void) { - return arch_curr_cpu()->nested != 0U; + uint32_t nested; + +#if defined(CONFIG_SMP) + /* + * Lock interrupts on SMP to ensure that the caller does not migrate + * to another CPU before we get to read the nested field. + */ + unsigned int key; + + key = arch_irq_lock(); +#endif + + nested = arch_curr_cpu()->nested; + +#if defined(CONFIG_SMP) + arch_irq_unlock(key); +#endif + + return nested != 0U; } #ifdef __cplusplus diff --git a/arch/xtensa/include/xtensa_asm2_context.h b/arch/xtensa/include/xtensa_asm2_context.h index ac13a611c67..56fc84b56ac 100644 --- a/arch/xtensa/include/xtensa_asm2_context.h +++ b/arch/xtensa/include/xtensa_asm2_context.h @@ -91,7 +91,7 @@ # define _BSA_PADDING_FPU (0) #endif -#if defined(CONFIG_XTENSA_HIFI_SHARING) +#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING) # define _BSA_PADDING_HIFI (XCHAL_CP1_SA_SIZE + XCHAL_CP1_SA_ALIGN) #else # define _BSA_PADDING_HIFI (0) @@ -173,7 +173,7 @@ struct xtensa_irq_base_save_area { uintptr_t fpu15; #endif -#if defined(CONFIG_XTENSA_HIFI_SHARING) +#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING) /* * Carve space for the registers used by the HiFi audio engine diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index d7799ac1125..af345ab3083 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -17,7 +17,7 @@ * only by the assembler. */ -#if defined(CONFIG_XTENSA_HIFI_SHARING) +#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING) .extern _xtensa_hifi_save #endif @@ -437,7 +437,7 @@ _xstack_returned_\@: FPU_REG_SAVE #endif -#if defined(CONFIG_XTENSA_HIFI_SHARING) +#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING) call0 _xtensa_hifi_save /* Save HiFi registers */ #endif @@ -606,6 +606,10 @@ _excint_noflush_\@: /* Restore A1 stack pointer from "next" handle. */ mov a1, a6 +#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING + call4 z_thread_mark_switched_in +#endif + _restore_\@: j _restore_context .endm diff --git a/arch/xtensa/include/xtensa_internal.h b/arch/xtensa/include/xtensa_internal.h index 29e08e1fe43..982a2711b23 100644 --- a/arch/xtensa/include/xtensa_internal.h +++ b/arch/xtensa/include/xtensa_internal.h @@ -72,7 +72,7 @@ void xtensa_userspace_enter(k_thread_entry_t user_entry, * * @return False if the permissions don't match. */ -bool xtensa_mem_kernel_has_access(void *addr, size_t size, int write); +bool xtensa_mem_kernel_has_access(const void *addr, size_t size, int write); /** * @} diff --git a/boards/actinius/icarus/actinius_icarus_common.dtsi b/boards/actinius/icarus/actinius_icarus_common.dtsi index b44370babb1..e89ee59d3a7 100644 --- a/boards/actinius/icarus/actinius_icarus_common.dtsi +++ b/boards/actinius/icarus/actinius_icarus_common.dtsi @@ -75,7 +75,6 @@ green-pwm-led = &green_pwm_led; blue-pwm-led = &blue_pwm_led; sw0 = &button0; - bootloader-led0 = &blue_led; mcuboot-button0 = &button0; mcuboot-led0 = &blue_led; watchdog0 = &wdt0; diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi index bd692cdc9ea..badf4f48a43 100644 --- a/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi @@ -75,7 +75,6 @@ green-pwm-led = &green_pwm_led; blue-pwm-led = &blue_pwm_led; sw0 = &button0; - bootloader-led0 = &blue_led; mcuboot-button0 = &button0; mcuboot-led0 = &blue_led; watchdog0 = &wdt0; diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi index c5ff38367b6..a7e49b1bb7c 100644 --- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi @@ -50,7 +50,6 @@ pwm-led0 = &blue_pwm_led; blue-pwm-led = &blue_pwm_led; sw0 = &button0; - bootloader-led0 = &blue_led; mcuboot-button0 = &button0; mcuboot-led0 = &blue_led; watchdog0 = &wdt0; diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts index be28841df3a..fa46fe93646 100644 --- a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts +++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts @@ -19,6 +19,7 @@ aliases { backlight = &led1; + fuel-gauge0 = &max17048; }; leds { diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst index a5fb76324d9..00779bc87e3 100644 --- a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst @@ -16,7 +16,7 @@ Hardware - 320KB SRAM, 4MB flash + 2MB PSRAM - USB-C directly connected to the ESP32-S2 for USB - LiPo connector and built-in battery charging when powered via USB-C -- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- LC709203F or MAX17048 fuel gauge for battery voltage and state-of-charge reporting - Built-in NeoPixel indicator RGB LED - STEMMA QT connector for I2C devices, with switchable power for low-power mode @@ -28,12 +28,10 @@ Hardware overlay. All boards, except the `Adafruit ESP32-S2 Feather with BME280 Sensor`_ have a space for it, but will not be shipped with. - As of May 31, 2023 - Adafruit has changed the battery monitor chip from the - now-discontinued LC709203 to the MAX17048. Check the back silkscreen of your Feather to + now-discontinued LC709203F to the MAX17048. Check the back silkscreen of your Feather to see which chip you have. - - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via - a devicetree overlay. - - For the LC709203 a driver does'nt exists yet and the fuel gauge for boards with this IC - is not available. + - For the MAX17048 and LC709203F a driver in zephyr exists and is supported, but needs to be + added via a devicetree overlay. - For the `Adafruit ESP32-S2 Feather`_ there are two different Revisions ``rev B`` and ``rev C``. The ``rev C`` board has revised the power circuitry for the NeoPixel and I2C QT port. Instead of a transistor the ``rev C`` has a LDO regulator. To enable the @@ -304,19 +302,64 @@ functioning correctly with Zephyr: :board: adafruit_feather_esp32s2@C :goals: build flash -Testing the Fuel Gauge (MAX17048) -********************************* +Testing the Fuel Gauge +********************** -There is a sample available to verify that the MAX17048 fuel gauge on the board are -functioning correctly with Zephyr: +There is a sample available to verify that the MAX17048 or LC709203F fuel gauge on the board are +functioning correctly with Zephyr .. note:: - As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 + As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203F to the MAX17048. +**Rev B** + +For the Rev B a devicetree overlay for the LC709203F fuel gauge already exists in the +``samples/drivers/fuel_gauge/boards`` folder. + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/fuel_gauge + :board: adafruit_feather_esp32s2@B + :goals: build flash + +**Rev C** + +For the Rev C a devicetree overlay for the MAX17048 fuel gauge already exists in the +``samples/drivers/fuel_gauge/boards`` folder. + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/fuel_gauge + :board: adafruit_feather_esp32s2@C + :goals: build flash + +For the LC709203F a devicetree overlay needs to be added to the build. +The overlay can be added via the ``--extra-dtc-overlay`` argument and should most likely includes +the following: + +.. code-block:: devicetree + + / { + aliases { + fuel-gauge0 = &lc709203f; + }; + }; + + &i2c0 { + lc709203f: lc709203f@0b { + compatible = "onnn,lc709203f"; + status = "okay"; + reg = <0x0b>; + power-domains = <&i2c_reg>; + apa = "500mAh"; + battery-profile = <0x01>; + }; + }; + + .. zephyr-app-commands:: - :zephyr-app: samples/fuel_gauge/max17048/ + :zephyr-app: samples/drivers/fuel_gauge :board: adafruit_feather_esp32s2@C + :west-args: --extra-dtc-overlay="boards/name_of_your.overlay" :goals: build flash Testing Wi-Fi diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst index 6f44363ca4b..6629b57feee 100644 --- a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst @@ -16,7 +16,7 @@ Hardware - 320KB SRAM, 4MB flash + 2MB PSRAM - USB-C directly connected to the ESP32-S2 for USB - LiPo connector and built-in battery charging when powered via USB-C -- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- LC709203F or MAX17048 fuel gauge for battery voltage and state-of-charge reporting - Charging indicator LED, user LED, reset and boot buttons. - Built-in NeoPixel indicator RGB LED - STEMMA QT connector for I2C devices, with switchable power for low-power mode @@ -26,12 +26,10 @@ Hardware - The board has a space for a BME280, but will not be shipped with. - As of May 31, 2023 - Adafruit has changed the battery monitor chip from the - now-discontinued LC709203 to the MAX17048. Check the back silkscreen of your Feather to + now-discontinued LC709203F to the MAX17048. Check the back silkscreen of your Feather to see which chip you have. - - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via - a devicetree overlay. - - For the LC709203 a driver does'nt exists yet and the fuel gauge for boards with this IC - is not available. + - For the MAX17048 and LC709203F a driver in zephyr exists and is supported, but needs to be + added via a devicetree overlay. Supported Features ================== @@ -252,19 +250,52 @@ Testing the TFT :board: adafruit_feather_esp32s2_tft :goals: build flash -Testing the Fuel Gauge (MAX17048) -********************************* +Testing the Fuel Gauge +********************** -There is a sample available to verify that the MAX17048 fuel gauge on the board are -functioning correctly with Zephyr: +There is a sample available to verify that the MAX17048 or LC709203F fuel gauge on the board are +functioning correctly with Zephyr. .. note:: - As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 + As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203F to the MAX17048. +**LC709203F Fuel Gauge** + +For the LC709203F a devicetree overlay already exists in the ``samples/drivers/fuel_gauge/boards`` folder. + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/fuel_gauge + :board: adafruit_feather_esp32s2_tft + :goals: build flash + +**MAX17048 Fuel Gauge** + +For the MAX17048 a devicetree overlay needs to be added to the build. +The overlay can be added via the ``--extra-dtc-overlay`` argument and should most likely includes +the following: + +.. code-block:: devicetree + + / { + aliases { + fuel-gauge0 = &max17048; + }; + }; + + &i2c0 { + max17048: max17048@36 { + compatible = "maxim,max17048"; + status = "okay"; + reg = <0x36 >; + power-domains = <&i2c_reg>; + }; + }; + .. zephyr-app-commands:: - :zephyr-app: samples/fuel_gauge/max17048/ + :zephyr-app: samples/drivers/fuel_gauge :board: adafruit_feather_esp32s2_tft + :west-args: --extra-dtc-overlay="boards/name_of_your.overlay" :goals: build flash Testing Wi-Fi diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst index fcbb6352205..ad90a078582 100644 --- a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst +++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst @@ -16,7 +16,7 @@ Hardware - 320KB SRAM, 4MB flash + 2MB PSRAM - USB-C directly connected to the ESP32-S2 for USB - LiPo connector and built-in battery charging when powered via USB-C -- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- MAX17048 fuel gauge for battery voltage and state-of-charge reporting - Charging indicator LED, user LED, reset and boot buttons and has 2 additional buttons. - Built-in NeoPixel indicator RGB LED - 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset. @@ -249,18 +249,14 @@ functioning correctly with Zephyr: :board: adafruit_feather_esp32s2_tft_reverse :goals: build flash -Testing the Fuel Gauge (MAX17048) -********************************* +Testing the Fuel Gauge +********************** There is a sample available to verify that the MAX17048 fuel gauge on the board are functioning correctly with Zephyr: -.. note:: - As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203 - to the MAX17048. - .. zephyr-app-commands:: - :zephyr-app: samples/fuel_gauge/max17048/ + :zephyr-app: samples/drivers/fuel_gauge :board: adafruit_feather_esp32s2_tft_reverse :goals: build flash diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts index b745820ddaa..07536e62985 100644 --- a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts +++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts @@ -38,6 +38,7 @@ sw0 = &button0; led0 = &led0; led-strip = &led_strip; + fuel-gauge0 = &max17048; }; buttons { @@ -115,7 +116,7 @@ filter-smooth-level = ; }; -&i2c0 { +zephyr_i2c: &i2c0 { status = "okay"; clock-frequency = ; pinctrl-0 = <&i2c0_default>; diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft b/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft index cd78387ff88..febc0d77381 100644 --- a/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft +++ b/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft @@ -3,6 +3,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT - select SOC_ESP32S3_WROOM_N8 + select SOC_ESP32S3_WROOM_N4R2 select SOC_ESP32S3_PROCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_PROCPU select SOC_ESP32S3_APPCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_APPCPU diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts index f4662f4b0a3..34571911c67 100644 --- a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts @@ -6,7 +6,7 @@ */ /dts-v1/; -#include +#include #include #include "adafruit_feather_esp32s3_tft-pinctrl.dtsi" diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts index b09b6262aa1..dd425efd5c2 100644 --- a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts +++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts @@ -6,7 +6,7 @@ */ /dts-v1/; -#include +#include #include #include #include @@ -22,6 +22,7 @@ aliases { i2c-0 = &i2c0; watchdog0 = &wdt0; + fuel-gauge0 = &max17048; }; chosen { @@ -162,7 +163,7 @@ filter-smooth-level = ; }; -&i2c0 { +zephyr_i2c: &i2c0 { status = "okay"; clock-frequency = ; pinctrl-0 = <&i2c0_default>; diff --git a/boards/adafruit/feather_esp32s3_tft/doc/index.rst b/boards/adafruit/feather_esp32s3_tft/doc/index.rst index f46daa99688..7324debe849 100644 --- a/boards/adafruit/feather_esp32s3_tft/doc/index.rst +++ b/boards/adafruit/feather_esp32s3_tft/doc/index.rst @@ -16,8 +16,7 @@ Hardware - ESP32-S3 mini module, featuring the dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running at up to 240MHz -- 512KB SRAM and either 8MB flash or 4MB flash + 2MB PSRAM, depending on the - module variant +- 512KB SRAM and either 4MB flash + 2MB PSRAM - USB-C directly connected to the ESP32-S3 for USB/UART and JTAG debugging - LiPo connector and built-in battery charging when powered via USB-C - MAX17048 fuel gauge for battery voltage and state-of-charge reporting diff --git a/boards/blues/swan_r5/CMakeLists.txt b/boards/adafruit/feather_esp32s3_tft_reverse/CMakeLists.txt similarity index 100% rename from boards/blues/swan_r5/CMakeLists.txt rename to boards/adafruit/feather_esp32s3_tft_reverse/CMakeLists.txt diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig b/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig new file mode 100644 index 00000000000..785bb38993d --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig @@ -0,0 +1,11 @@ +# Adafruit ESP32-S3 Reverse TFT Feather board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2024 Leon Rinkel +# Copyright (c) 2025 Philipp Steiner +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_REVERSE_ESP32S3_PROCPU + default 256 if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_REVERSE_ESP32S3_APPCPU diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.adafruit_feather_esp32s3_tft_reverse b/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.adafruit_feather_esp32s3_tft_reverse new file mode 100644 index 00000000000..7447335883d --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.adafruit_feather_esp32s3_tft_reverse @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2024 Leon Rinkel +# Copyright (c) 2025 Philipp Steiner +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_REVERSE + select SOC_ESP32S3_WROOM_N4R2 + select SOC_ESP32S3_PROCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_REVERSE_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_REVERSE_ESP32S3_APPCPU diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.defconfig b/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.defconfig new file mode 100644 index 00000000000..e24600b09bc --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.defconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2024 Leon Rinkel +# Copyright (c) 2025 Philipp Steiner +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_REVERSE_ESP32S3_PROCPU + +if DISPLAY + +config BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_REVERSE + select BOARD_LATE_INIT_HOOK + +choice ST7789V_PIXEL_FORMAT + default ST7789V_RGB565 +endchoice + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_REVERSE_ESP32S3_PROCPU diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.sysbuild b/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.sysbuild new file mode 100644 index 00000000000..8d3acb9e11d --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse-pinctrl.dtsi b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse-pinctrl.dtsi new file mode 100644 index 00000000000..80a29d5e14a --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse-pinctrl.dtsi @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + /* Debug TX (DBG) - This is the hardware UART debug pin */ + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_ws2812_led: spim3_ws2812_led { + group1 { + pinmux = ; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu.dts b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu.dts new file mode 100644 index 00000000000..85918873980 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu.dts @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include "adafruit_feather_esp32s3_tft_reverse-pinctrl.dtsi" + +/ { + model = "Adafruit ESP32-S3 Reverse TFT Feather APPCPU"; + compatible = "adafruit,feather_esp32s3_tft_reverse", "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu.yaml b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu.yaml new file mode 100644 index 00000000000..1d3f5c950a3 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: adafruit_feather_esp32s3_tft_reverse/esp32s3/appcpu +name: Adafruit ESP32-S3 Reverse TFT Feather APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: adafruit diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu_defconfig b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu_defconfig new file mode 100644 index 00000000000..48546641cad --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_appcpu_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.dts b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.dts new file mode 100644 index 00000000000..837bf550e14 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.dts @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "feather_connector.dtsi" +#include "adafruit_feather_esp32s3_tft_reverse-pinctrl.dtsi" + +/ { + model = "Adafruit ESP32-S3 Reverse TFT Feather PROCPU"; + compatible = "adafruit,feather_esp32s3_tft_reverse", "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,display = &st7789v_tft; + }; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + uart-0 = &uart0; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + led0 = &led0; + led-strip = &led_strip; + backlight = &led1; + }; + + gpio_keys { + compatible = "gpio-keys"; + status = "okay"; + + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "D0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio0 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "D1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "D2"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led0: led_0 { + label = "Red-LED"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + + led1: led_1 { + + label = "TFT Backlight"; + gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * The neopixel on this board has its positive side hooked up to a GPIO + * pin rather than a positive voltage rail to save on power. + */ + neopixel_pwr: neopixel_pwr { + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + + /* + * On-board regulator powers I2C pull-ups and external devices connected + * via the STEMMA QT connector. + */ + i2c_reg: i2c_reg { + label = "I2C Power"; + compatible = "power-domain-gpio"; + #power-domain-cells = <0>; + enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi2>; + dc-gpios = <&gpio1 40 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 41 GPIO_ACTIVE_LOW>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v_tft: st7789v_tft@0 { + compatible = "sitronix,st7789v"; + status = "disabled"; + + /* Also powered by i2c_reg */ + power-domains = <&i2c_reg>; + + mipi-max-frequency = ; + reg = <0>; + width = <135>; + height = <240>; + x-offset = <52>; + y-offset = <40>; + vcom = <0x20>; + gctrl = <0x35>; + vrhs = <0x0b>; + vdvs = <0x20>; + mdac = <0x08>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; + nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25]; + ram-param = [00 F0]; + rgb-param = [40 02 14]; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + }; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +zephyr_i2c: &i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + max17048: max17048@36 { + compatible = "maxim,max17048"; + status = "okay"; + reg = <0x36>; + + /* + * The MAX17048 itself is directly powered by the battery, not + * through the on-board regulator. However using this device + * requires I2C pull-ups powered by the regulator. + */ + power-domains = <&i2c_reg>; + }; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_ws2812_led>; + pinctrl-names = "default"; + + /* Workaround to support WS2812 driver */ + line-idle-low; + + led_strip: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + power-domains = <&neopixel_pwr>; + + /* WS2812 */ + reg = <0>; /* ignored, but necessary for SPI bindings */ + spi-max-frequency = <6400000>; + chain-length = <1>; + spi-cpha; + spi-one-frame = <0xf0>; /* 625 ns high and 625 ns low */ + spi-zero-frame = <0xc0>; /* 312.5 ns high and 937.5 ns low */ + color-mapping = ; + }; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.yaml b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.yaml new file mode 100644 index 00000000000..1b9773f89bf --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu.yaml @@ -0,0 +1,23 @@ +identifier: adafruit_feather_esp32s3_tft_reverse/esp32s3/procpu +name: Adafruit ESP32-S3 Reverse TFT Feather PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input + - feather_serial + - feather_i2c + - feather_spi + - display +vendor: adafruit diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu_defconfig b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu_defconfig new file mode 100644 index 00000000000..d8fbaa87925 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse_procpu_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/board.c b/boards/adafruit/feather_esp32s3_tft_reverse/board.c new file mode 100644 index 00000000000..88aa3b0b354 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/board.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Leon Rinkel + * + * SPDX-License-Identifier: Apache-2.0 + * + * Automatically turns on backlight if display is configured, i.e. display DT + * node has status okay. + */ + +#include +#include +#include + +#define DISPLAY_NODE DT_CHOSEN(zephyr_display) + +#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay) +static const struct gpio_dt_spec backlight = GPIO_DT_SPEC_GET(DT_ALIAS(backlight), gpios); +#endif + +void board_late_init_hook(void) +{ +#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay) + if (gpio_is_ready_dt(&backlight)) { + gpio_pin_configure_dt(&backlight, GPIO_OUTPUT_ACTIVE); + } +#endif +} diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/board.cmake b/boards/adafruit/feather_esp32s3_tft_reverse/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/board.yml b/boards/adafruit/feather_esp32s3_tft_reverse/board.yml new file mode 100644 index 00000000000..b8c23080dc5 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_feather_esp32s3_tft_reverse + full_name: Adafruit ESP32-S3 Reverse TFT Feather + vendor: adafruit + socs: + - name: esp32s3 diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/doc/img/adafruit_feather_esp32s3_tft_reverse.webp b/boards/adafruit/feather_esp32s3_tft_reverse/doc/img/adafruit_feather_esp32s3_tft_reverse.webp new file mode 100644 index 00000000000..34bcd7400a5 Binary files /dev/null and b/boards/adafruit/feather_esp32s3_tft_reverse/doc/img/adafruit_feather_esp32s3_tft_reverse.webp differ diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/doc/index.rst b/boards/adafruit/feather_esp32s3_tft_reverse/doc/index.rst new file mode 100644 index 00000000000..98135629d74 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/doc/index.rst @@ -0,0 +1,249 @@ +.. zephyr:board:: adafruit_feather_esp32s3_tft_reverse + +Overview +******** + +The Adafruit ESP32-S3 Reverse TFT Feather is a development board in the +Feather standard layout, sharing peripheral placement with other devices +labeled as Feathers or FeatherWings. The board is equipped with an +ESP32-S3 mini module, a fuel gauge, a USB-C and Qwiic/STEMMA-QT connector. +This variant additionally comes with a 240x135 pixel IPS TFT color display +on the backside of the boards and with 3 buttons. + +For more information, check +`Adafruit ESP32-S3 Reverse TFT Feather`_. + +Hardware +******** + +- ESP32-S3 mini module, featuring the dual core 32-bit Xtensa Microprocessor + (Tensilica LX7), running at up to 240MHz +- 512KB SRAM and either 4MB flash + 2MB PSRAM +- USB-C directly connected to the ESP32-S3 for USB/UART and JTAG debugging +- LiPo connector and built-in battery charging when powered via USB-C +- MAX17048 fuel gauge for battery voltage and state-of-charge reporting +- Charging indicator LED, user LED, reset buttons +- Built-in NeoPixel indicator RGB LED +- STEMMA QT connector for I2C devices, with switchable power for low-power mode +- 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset +- Three User Tactile buttons - D0, D1, and D2. D0/BOOT0 is also used for entering ROM + bootloader mode if necessary. + + +Asymmetric Multiprocessing (AMP) +================================ + +The ESP32-S3 SoC allows 2 different applications to be executed in asymmetric +multiprocessing. Due to its dual-core architecture, each core can be enabled to +execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP +framework. See :zephyr:code-sample-category:`ipc` folder as code reference. + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The `Adafruit ESP32-S3 Reverse TFT Feather User Guide`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the +command below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +=================== + +Simple boot +----------- + +The board could be loaded using the single binary image, without 2nd stage +bootloader. It is the default option when building the application without +additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +------------------ + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +-------- + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-S3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft_reverse/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32-S3 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` +documentation. + +Manual build +------------ + +During the development cycle, it is intended to build & flash as quickly +possible. For that reason, images can be build one at a time using traditional +build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: :board: adafruit_feather_esp32s3_tft_reverse/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``adafruit_feather_esp32s3_tft_reverse`` +board. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft_reverse/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! adafruit_feather_esp32s3_tft_reverse/esp32s3/procpu + +Debugging +========= + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. Download +and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any +additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft_reverse/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_esp32s3_tft_reverse/esp32s3/procpu + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Adafruit ESP32-S3 Reverse TFT Feather`: + https://www.adafruit.com/product/5691 + +.. _`OpenOCD`: + https://github.com/openocd-org/openocd + +.. _`JTAG debugging for ESP32-S3`: + https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ + +.. _Adafruit ESP32-S3 Reverse TFT Feather User Guide: + https://learn.adafruit.com/esp32-s3-reverse-tft-feather + +.. _pinouts: + https://learn.adafruit.com/esp32-s3-reverse-tft-feather/pinouts + +.. _schematic: + https://learn.adafruit.com/esp32-s3-reverse-tft-feather/downloads + +.. _ESP32-S3 Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf + +.. _ESP32 Technical Reference Manual: + https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/feather_connector.dtsi b/boards/adafruit/feather_esp32s3_tft_reverse/feather_connector.dtsi new file mode 100644 index 00000000000..b2a4321b817 --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/feather_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2020 Richard Osterloh + * Copyright (c) 2024 Leon Rinkel + * Copyright (c) 2025 Philipp Steiner + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + feather_header: connector { + compatible = "adafruit-feather-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 18 0>, /* A0 */ + <1 0 &gpio0 17 0>, /* A1 */ + <2 0 &gpio0 16 0>, /* A2 */ + <3 0 &gpio0 15 0>, /* A3 */ + <4 0 &gpio0 14 0>, /* A4 */ + <5 0 &gpio0 8 0>, /* A5 */ + <6 0 &gpio1 36 0>, /* SCK */ + <7 0 &gpio1 35 0>, /* MOSI */ + <8 0 &gpio1 37 0>, /* MISO */ + <9 0 &gpio1 38 0>, /* RX */ + <10 0 &gpio1 39 0>, /* TX */ + <11 0 &gpio1 46 0>, /* DB */ + <12 0 &gpio0 3 0>, /* SDA */ + <13 0 &gpio0 4 0>, /* SCL */ + <14 0 &gpio0 5 0>, /* D5 */ + <15 0 &gpio0 6 0>, /* D6 */ + <16 0 &gpio0 9 0>, /* D9 */ + <17 0 &gpio0 10 0>, /* D10 */ + <18 0 &gpio0 11 0>, /* D11 */ + <19 0 &gpio0 12 0>, /* D12 */ + <20 0 &gpio0 13 0>; /* D13 */ + }; +}; + +feather_serial: &uart1 {}; +feather_i2c: &i2c0 {}; +feather_spi: &spi2 {}; diff --git a/boards/adafruit/feather_esp32s3_tft_reverse/support/openocd.cfg b/boards/adafruit/feather_esp32s3_tft_reverse/support/openocd.cfg new file mode 100644 index 00000000000..2f740b4a36a --- /dev/null +++ b/boards/adafruit/feather_esp32s3_tft_reverse/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/adafruit/kb2040/adafruit_kb2040_defconfig b/boards/adafruit/kb2040/adafruit_kb2040_defconfig index f2202a534b6..7b2969a065a 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040_defconfig +++ b/boards/adafruit/kb2040/adafruit_kb2040_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 - # Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040_defconfig b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040_defconfig index 2fb65b60022..7eab1729202 100644 --- a/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040_defconfig +++ b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040_defconfig @@ -1,7 +1,6 @@ # Copyright (c) 2025 Benjamin Cabé # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/adafruit/metro_rp2350/Kconfig.adafruit_metro_rp2350 b/boards/adafruit/metro_rp2350/Kconfig.adafruit_metro_rp2350 new file mode 100644 index 00000000000..2c16f08668e --- /dev/null +++ b/boards/adafruit/metro_rp2350/Kconfig.adafruit_metro_rp2350 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_METRO_RP2350 + select SOC_RP2350B_M33 if BOARD_ADAFRUIT_METRO_RP2350_RP2350B_M33 diff --git a/boards/adafruit/metro_rp2350/Kconfig.defconfig b/boards/adafruit/metro_rp2350/Kconfig.defconfig new file mode 100644 index 00000000000..8f2f59cb06c --- /dev/null +++ b/boards/adafruit/metro_rp2350/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_METRO_RP2350 + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_METRO_RP2350 diff --git a/boards/adafruit/metro_rp2350/adafruit_metro_rp2350-pinctrl.dtsi b/boards/adafruit/metro_rp2350/adafruit_metro_rp2350-pinctrl.dtsi new file mode 100644 index 00000000000..5dfd0c0d848 --- /dev/null +++ b/boards/adafruit/metro_rp2350/adafruit_metro_rp2350-pinctrl.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Pete Johanson + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = ; + input-enable; + }; + + group2 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , + , , ; + input-enable; + }; + }; + + pwm_default: pwm_default { + group1 { + pinmux = , , , , , + ; + }; + }; + + pio0_spi0_default: pio0_spi0_default { + /* gpio 10 is used for chip select, not assigned to the PIO */ + group1 { + pinmux = , ; + }; + }; + + pio1_ws2812_default: pio1_ws2812_default { + group1 { + pinmux = ; + }; + }; +}; diff --git a/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33.dts b/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33.dts new file mode 100644 index 00000000000..1bbfa2f2a5f --- /dev/null +++ b/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33.dts @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2025 Pete Johanson + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +/* The build system assumes that there's a cpucluster-specific file. + * + * This file provides composition of the device tree: + * 1. The common features of the SoC + * 2. Core-specific configuration. + * 3. Board-specific configuration. + */ +#include +#include + +#include + +#include +#include +#include +#include + +#include "adafruit_metro_rp2350-pinctrl.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + led-strip = &ws2812; + led0 = &user_led; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user_led { + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + label = "USER_LED"; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + arduino_adc: analog-connector { + compatible = "arduino,uno-adc"; + #io-channel-cells = <1>; + io-channel-map = <0 &adc 1>, /* A0 = GPIO41 = ADC1 */ + <1 &adc 2>, /* A1 = GPIO42 = ADC2 */ + <2 &adc 3>, /* A2 = GPIO43 = ADC3 */ + <3 &adc 4>, /* A3 = GPIO44 = ADC4 */ + <4 &adc 5>, /* A4 = GPIO45 = ADC5 */ + <5 &adc 6>; /* A5 = GPIO46 = ADC6 */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(16)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for an image definition block. The block is much + * smaller than 256 bytes, but in practice the linker places the vector + * table at a much larger alignment offset. + */ + image_def: partition@0 { + label = "image_def"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the image definition block. + * The partition size is 4MB minus the 0x100 bytes taken by the + * image definition. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(16) - 0x100)>; + read-only; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc { + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm { + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; + divider-int-0 = <255>; +}; + +&timer0 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&pio0 { + status = "okay"; + + arduion_spi: pio0_spi0 { + compatible = "raspberrypi,pico-spi-pio"; + clocks = < &clocks RPI_PICO_CLKID_CLK_SYS >; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + clk-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pio0_spi0_default>; + pinctrl-names = "default"; + }; +}; + +&pio1 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&pio1_ws2812_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + chain-length = <1>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + + +arduino_serial: &uart0 {}; +arduino_i2c: &i2c0 {}; diff --git a/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33.yaml b/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33.yaml new file mode 100644 index 00000000000..b966238ee48 --- /dev/null +++ b/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33.yaml @@ -0,0 +1,20 @@ +identifier: adafruit_metro_rp2350/rp2350b/m33 +name: Adafruit Metro RP2350 (Cortex-M33) +type: mcu +arch: arm +flash: 16384 +ram: 520 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart diff --git a/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33_defconfig b/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33_defconfig new file mode 100644 index 00000000000..4da77bdb95c --- /dev/null +++ b/boards/adafruit/metro_rp2350/adafruit_metro_rp2350_rp2350b_m33_defconfig @@ -0,0 +1,13 @@ +# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores +# are in use, but Zephyr does not support providing a qualifier-agnostic +# _defconfig file. +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/adafruit/metro_rp2350/board.cmake b/boards/adafruit/metro_rp2350/board.cmake new file mode 100644 index 00000000000..63afbae0881 --- /dev/null +++ b/boards/adafruit/metro_rp2350/board.cmake @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at +# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000") + +board_runner_args(uf2 "--board-id=RP2350") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adafruit/metro_rp2350/board.yml b/boards/adafruit/metro_rp2350/board.yml new file mode 100644 index 00000000000..5e724baa38a --- /dev/null +++ b/boards/adafruit/metro_rp2350/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_metro_rp2350 + full_name: Adafruit Metro RP2350 + vendor: adafruit + socs: + - name: rp2350b diff --git a/boards/adafruit/metro_rp2350/doc/img/adafruit_metro_rp2350.webp b/boards/adafruit/metro_rp2350/doc/img/adafruit_metro_rp2350.webp new file mode 100644 index 00000000000..2c7eb78ae06 Binary files /dev/null and b/boards/adafruit/metro_rp2350/doc/img/adafruit_metro_rp2350.webp differ diff --git a/boards/adafruit/metro_rp2350/doc/index.rst b/boards/adafruit/metro_rp2350/doc/index.rst new file mode 100644 index 00000000000..29a13da3f56 --- /dev/null +++ b/boards/adafruit/metro_rp2350/doc/index.rst @@ -0,0 +1,57 @@ +.. zephyr:board:: adafruit_metro_rp2350 + +Overview +******** + +Choo! Choo! This is the RP2350 Metro Line, making all station stops at "Dual Cortex M33 mountain", +"528K RAM round-about" and "16 Megabytes of Flash town". This train is piled high with hardware that +complements the Raspberry Pi RP2350 chip to make it an excellent development board for projects that +want Arduino-shape-compatibility or just need the extra space and debugging ports. + +The Adafruit Metro RP2350 is the second Metro board to use the Rasperry Pi Pico family. + +There are many limitations of the board currently. Including but not limited to: +- The Zephyr build only supports configuring the RP2350B with the Cortex-M33 cores. +- As with other RP2040/RP2350 devices, there's no support for running any code on the second core. + +Hardware +******** + +- RP2350 main chip, 150MHz clock, 3.3V logic +- 16 MB of QSPI flash for program storage +- 37 Available GPIO: 23 on the socket/SPI headers, 12 on HSTX port, and another 2 for USB host. 6 of which are also analog inputs +- Micro SD card socket wired up for SPI interfacing, also has extra pins connected for advanced-user SDIO interfacing (note that there's no code for SDIO in Arduino/Python, so this is a super-cutting-edge setup) +- 5V Buck Converter featuring TPS563201 6~17V DC input and up to 2A output +- Onboard RGB NeoPixel +- Onboard #23 LED +- Stemma QT port for I2C peripherals and sensors +- 22-pin 3-lane differential HSTX FPC port with 'Pi 5' compatible pinout, makes for quick DVI video output. Or, this also provides 12 extra GPIO that can be used for more pins. +- Reset and Boot buttons on PCB edge +- Pico Probe debug port - 3 pin JST SH compatible +- USB Type C power and data +- 5.5mm / 2.1mm DC jack for 6-17VDC power +- On/off switch for DC jack +- RX / TX switch for swapping D0 and D1 locations +- USB Host breakout pads - with controllable 5V power and D+/D- for bitbang USB Host. +- GPIO pin numbers match classic Arduino pins, other than GPIO 12 and 13 as those are needed for HSTX connectivity + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The default pin mapping is unchanged from the Pico 1 (see :ref:`rpi_pico_pin_mapping`). + +Programming and Debugging +************************* + +As with other RP3250 devices, the SWD interface can be used to program and debug the +device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . + +References +********** + +.. target-notes:: diff --git a/boards/adafruit/metro_rp2350/support/openocd.cfg b/boards/adafruit/metro_rp2350/support/openocd.cfg new file mode 100644 index 00000000000..82666bb5331 --- /dev/null +++ b/boards/adafruit/metro_rp2350/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts index 5d8b14a96a6..5c759d67f88 100644 --- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts @@ -71,7 +71,7 @@ pinctrl-names = "default"; }; -&i2c1 { +zephyr_i2c: &i2c1 { status = "okay"; clock-frequency = ; pinctrl-0 = <&i2c1_default>; diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts index a6eaf30bbe6..d5717512f0d 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts @@ -88,16 +88,16 @@ }; &i2c0 { - clock-frequency = ; status = "okay"; pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; + clock-frequency = ; }; -&i2c1 { +zephyr_i2c: &i2c1 { + status = "okay"; pinctrl-0 = <&i2c1_default>; pinctrl-names = "default"; - status = "okay"; clock-frequency = ; }; diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig index f2202a534b6..7b2969a065a 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 - # Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml index 495481a989d..84573f8d969 100644 --- a/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml +++ b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml @@ -9,5 +9,5 @@ toolchain: supported: - gpio - serial -ram: 1024 +ram: 32 flash: 3072 diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts index f291e50a806..f0aa1093431 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.dts +++ b/boards/adi/apard32690/apard32690_max32690_m4.dts @@ -308,3 +308,30 @@ pmod_spi: &spi4 { config-reg-vals = <0x801F>; }; }; + +&spixf { + pinctrl-0 = <&spixf_sdio0_p0_1 &spixf_sdio2_p0_2 &spixf_sck_p0_3 + &spixf_sdio3_p0_4 &spixf_sdio1_p0_5 &spixf_ss0_p0_6>; + pinctrl-names = "default"; + + mx25u64: mx25u6432f@8000000 { + compatible = "adi,max32-spixf-nor"; + reg = <0x08000000 DT_SIZE_M(8)>; /* 64 Mbits */ + qspi-max-frequency = <60000000>; + jedec-id = [c2 37 25]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 + 10 d8 00 ff d3 49 c9 00 83 a6 04 c4 44 03 17 38 + 30 b0 30 b0 f7 bd d5 5c 4a 9e 29 ff f0 d0 ff ff + ]; + page-size = <4096>; + reset-cmd; + spi-bus-width = <4>; + writeoc = "PP_1_1_4"; + }; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; diff --git a/boards/adi/apard32690/apard32690_max32690_m4.yaml b/boards/adi/apard32690/apard32690_max32690_m4.yaml index ba9f690d054..f7b0292b855 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.yaml +++ b/boards/adi/apard32690/apard32690_max32690_m4.yaml @@ -16,8 +16,9 @@ supported: - serial - spi - trng + - usbd - counter - w1 - memc -ram: 1024 +ram: 128 flash: 3072 diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts index 3b6934062e9..c49fa7eb82d 100644 --- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts @@ -269,9 +269,10 @@ zephyr_udc0: &usbotg_fs { status = "okay"; - mx25r6435f: ospi-nor-flash@90000000 { + mx25r6435f: ospi-nor-flash@0 { compatible = "st,stm32-ospi-nor"; - reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Megabits */ + reg = <0>; + size = ; /* 64 Megabits */ ospi-max-frequency = ; /* for Voltage Range 2 */ spi-bus-width = ; data-rate = ; @@ -307,7 +308,7 @@ zephyr_udc0: &usbotg_fs { sram { bank@0 { - reg = <0x0>; + reg = ; st,control = ; + pinctrl-names = "default"; +}; + +&rtc_counter { + status = "okay"; + clock-source = ; +}; + +&i3c0 { + status = "okay"; + pinctrl-0 = <&i3c_scl_p0_0 &i3c_sda_p0_1>; + pinctrl-names = "default"; + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; + + adxl367: adxl367@530000000000000000 { + compatible = "adi,adxl367"; + reg = <0x53 0x00 0x00>; + status = "okay"; + }; +}; + +&wut0 { + clock-source = ; +}; + +&wut1 { + status = "okay"; + clock-source = ; + wakeup-source; + counter_wut1: counter { + status = "okay"; + }; +}; diff --git a/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml b/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml index 82703d9e354..b44594771c9 100644 --- a/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml +++ b/boards/adi/max32657evkit/max32657evkit_max32657_ns.yaml @@ -9,5 +9,12 @@ toolchain: supported: - serial - gpio + - watchdog + - dma + - counter + - pwm + - rtc_counter + - spi + - i3c ram: 192 flash: 576 diff --git a/boards/adi/max32660evsys/max32660evsys.yaml b/boards/adi/max32660evsys/max32660evsys.yaml index da963ef091c..14aa99ea5ea 100644 --- a/boards/adi/max32660evsys/max32660evsys.yaml +++ b/boards/adi/max32660evsys/max32660evsys.yaml @@ -9,5 +9,5 @@ toolchain: supported: - gpio - serial -ram: 96 +ram: 32 flash: 256 diff --git a/boards/adi/max32662evkit/max32662evkit.dts b/boards/adi/max32662evkit/max32662evkit.dts index e8cdc4ddb94..58a71b0917b 100644 --- a/boards/adi/max32662evkit/max32662evkit.dts +++ b/boards/adi/max32662evkit/max32662evkit.dts @@ -23,6 +23,7 @@ zephyr,sram = &sram2; zephyr,flash = &flash0; zephyr,display = &st7735; + zephyr,canbus = &can0; }; leds { @@ -151,3 +152,9 @@ pinctrl-names = "default"; cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; }; + +&can0 { + status = "okay"; + pinctrl-0 = <&can0b_tx_p0_16 &can0b_rx_p0_15>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32662evkit/max32662evkit.yaml b/boards/adi/max32662evkit/max32662evkit.yaml index 9866e12e0dc..75592528f36 100644 --- a/boards/adi/max32662evkit/max32662evkit.yaml +++ b/boards/adi/max32662evkit/max32662evkit.yaml @@ -19,5 +19,6 @@ supported: - rtc_counter - pwm - flash -ram: 80 + - can +ram: 16 flash: 256 diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml index f43f703e894..a9180a342b4 100644 --- a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml @@ -19,5 +19,5 @@ supported: - pwm - w1 - flash -ram: 560 +ram: 128 flash: 1024 diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml index 9b924a56a6d..ad9094dc415 100644 --- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml @@ -21,5 +21,5 @@ supported: - w1 - flash - sdhc -ram: 560 +ram: 128 flash: 1024 diff --git a/boards/adi/max32670evkit/max32670evkit.yaml b/boards/adi/max32670evkit/max32670evkit.yaml index 266d1584aaf..a29cfd222a8 100644 --- a/boards/adi/max32670evkit/max32670evkit.yaml +++ b/boards/adi/max32670evkit/max32670evkit.yaml @@ -18,5 +18,5 @@ supported: - rtc_counter - pwm - flash -ram: 160 +ram: 64 flash: 384 diff --git a/boards/adi/max32672evkit/max32672evkit.yaml b/boards/adi/max32672evkit/max32672evkit.yaml index a8c835774e5..34174aeee42 100644 --- a/boards/adi/max32672evkit/max32672evkit.yaml +++ b/boards/adi/max32672evkit/max32672evkit.yaml @@ -19,5 +19,5 @@ supported: - rtc_counter - pwm - flash -ram: 200 +ram: 64 flash: 1024 diff --git a/boards/adi/max32672fthr/max32672fthr.yaml b/boards/adi/max32672fthr/max32672fthr.yaml index 28bb5414e07..d4e5766faf6 100644 --- a/boards/adi/max32672fthr/max32672fthr.yaml +++ b/boards/adi/max32672fthr/max32672fthr.yaml @@ -19,5 +19,5 @@ supported: - rtc_counter - pwm - flash -ram: 200 +ram: 64 flash: 1024 diff --git a/boards/adi/max32675evkit/max32675evkit.yaml b/boards/adi/max32675evkit/max32675evkit.yaml index 86bee190d25..39d468444d1 100644 --- a/boards/adi/max32675evkit/max32675evkit.yaml +++ b/boards/adi/max32675evkit/max32675evkit.yaml @@ -15,5 +15,5 @@ supported: - spi - pwm - flash -ram: 160 +ram: 64 flash: 384 diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml index 84f75d376d8..3dc5fa843ac 100644 --- a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml +++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml @@ -18,5 +18,5 @@ supported: - counter - w1 - flash -ram: 128 +ram: 48 flash: 512 diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts index 8e2aabb71f8..796747b7ebe 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts @@ -23,6 +23,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,display = &st7735; + zephyr,canbus = &can0; }; leds { @@ -196,3 +197,9 @@ zephyr_udc0: &usbhs { status = "okay"; }; + +&can0 { + status = "okay"; + pinctrl-0 = <&can0b_tx_p2_23 &can0b_rx_p2_22>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml index 83c03c9715d..7aa536ce628 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml @@ -22,5 +22,6 @@ supported: - flash - usbd - memc -ram: 1024 + - can +ram: 128 flash: 3072 diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts b/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts index 0ee5bb85f96..a82a0853ac0 100644 --- a/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts +++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4.dts @@ -140,3 +140,7 @@ feather_spi: &spi0 { pinctrl-0 = <&spi0b_mosi_p2_28 &spi0b_miso_p2_27 &spi0b_sck_p2_29>; pinctrl-names = "default"; }; + +zephyr_udc0: &usbhs { + status = "okay"; +}; diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml index 7b802ab4795..d779aa2140b 100644 --- a/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml +++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml @@ -15,5 +15,6 @@ supported: - feather_i2c - feather_spi - flash -ram: 1024 + - usbd +ram: 128 flash: 3072 diff --git a/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml b/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml index 5f7f5225041..2143c46be35 100644 --- a/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml +++ b/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml @@ -19,5 +19,5 @@ supported: - trng - w1 - watchdog -ram: 128 +ram: 48 flash: 512 diff --git a/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml b/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml index 116fa9051c5..0125687cb5e 100644 --- a/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml +++ b/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml @@ -19,5 +19,5 @@ supported: - trng - w1 - watchdog -ram: 128 +ram: 48 flash: 512 diff --git a/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml b/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml index ffe89807e7a..fb537c20e6a 100644 --- a/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml +++ b/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml @@ -20,5 +20,5 @@ supported: - pwm - w1 - flash -ram: 384 +ram: 64 flash: 2560 diff --git a/boards/adi/sdp_k1/adi_sdp_k1.yaml b/boards/adi/sdp_k1/adi_sdp_k1.yaml index b794e9be8f2..cc74c1cc123 100644 --- a/boards/adi/sdp_k1/adi_sdp_k1.yaml +++ b/boards/adi/sdp_k1/adi_sdp_k1.yaml @@ -5,7 +5,7 @@ arch: arm toolchain: - zephyr - gnuarmemb -ram: 384 +ram: 320 flash: 2048 supported: - gpio diff --git a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts index d3e99d7a45f..7cecb09a1a0 100644 --- a/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts +++ b/boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "ai_wb2_12f-pinctrl.dtsi" / { @@ -15,6 +15,7 @@ chosen { zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; zephyr,sram = &sram0; @@ -27,18 +28,30 @@ clock-frequency = ; }; -&spi1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4000b000 0x1000 0x23000000 0x400000>; - - flash0: flash@0 { - compatible = "zb,25vq32", "jedec,spi-nor"; - status = "disabled"; - size = ; - jedec-id = [5e 40 16]; - reg = <0>; - spi-max-frequency = ; +&flashctrl { + flash0: flash@23000000 { + compatible = "soc-nv-flash", "zb,25vq32"; + reg = <0x23000000 (0x400000 - 0x2000)>; + write-block-size = <256>; + erase-block-size = ; + /* jedec-id = [5e 40 16]; */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 0x00100000>; + read-only; + }; + + storage_partition: partition@100000 { + label = "storage"; + reg = <0x00100000 (0x300000 - 0x2000)>; + }; + }; }; }; diff --git a/boards/aithinker/ai_wb2_12f/support/bl60x.cfg b/boards/aithinker/ai_wb2_12f/support/bl60x.cfg index fcabb2c4e7c..25b8f1dc798 100644 --- a/boards/aithinker/ai_wb2_12f/support/bl60x.cfg +++ b/boards/aithinker/ai_wb2_12f/support/bl60x.cfg @@ -38,23 +38,22 @@ echo "Ready for Remote Connections" $_TARGETNAME.0 configure -event reset-assert-pre { echo "reset-assert-pre" - adapter speed 100 + adapter speed 400 } $_TARGETNAME.0 configure -event reset-deassert-post { echo "reset-deassert-post" - adapter speed 100 + adapter speed 400 - reg mstatus 0x7800 - reg mie 0x0 -# reg pc 0x23000000 + reg mstatus 0x0 + reg pc 0x21000000 } $_TARGETNAME.0 configure -event reset-init { echo "reset-init" - adapter speed 3000 + adapter speed 400 } $_TARGETNAME.0 configure -event gdb-attach { diff --git a/boards/aithinker/ai_wb2_12f/support/openocd.cfg b/boards/aithinker/ai_wb2_12f/support/openocd.cfg index 9a3b1644e96..ea9daa4d8b5 100644 --- a/boards/aithinker/ai_wb2_12f/support/openocd.cfg +++ b/boards/aithinker/ai_wb2_12f/support/openocd.cfg @@ -2,4 +2,4 @@ interface cmsis-dap -adapter speed 1000 +adapter speed 400 diff --git a/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts b/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts index 7661de67198..a8025833d94 100644 --- a/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts +++ b/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts @@ -75,16 +75,17 @@ &quadspi_bk1_io0_pe12 &quadspi_bk1_io1_pe13 &quadspi_bk1_io2_pe14 &quadspi_bk1_io3_pe15>; pinctrl-names = "default"; - status = "okay"; - w25q128jv: qspi-nor-flash@90000000 { - compatible = "st,stm32-qspi-nor"; - reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */ - qspi-max-frequency = <80000000>; - jedec-id = [ef 40 18]; - spi-bus-width = <4>; - writeoc = "PP_1_1_4"; - status = "okay"; + + w25q128jv: qspi-nor-flash@0 { + compatible = "st,stm32-qspi-nor"; + reg = <0>; + size = ; /* 128 Mbits */ + qspi-max-frequency = <80000000>; + jedec-id = [ef 40 18]; + spi-bus-width = <4>; + writeoc = "PP_1_1_4"; + status = "okay"; }; }; diff --git a/boards/ambiq/apollo3_evb/Kconfig.defconfig b/boards/ambiq/apollo3_evb/Kconfig.defconfig index bd2a5f91add..141f4544713 100644 --- a/boards/ambiq/apollo3_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo3_evb/Kconfig.defconfig @@ -1,11 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 # -# Copyright (c) 2024 Ambiq Micro Inc. +# Copyright (c) 2024-2025 Ambiq Micro Inc. if BOARD_APOLLO3_EVB config SYS_CLOCK_HW_CYCLES_PER_SEC default 32768 if AMBIQ_STIMER_TIMER + default 48000000 if CORTEX_M_SYSTICK config LOG_BACKEND_SWO_FREQ_HZ default 1000000 diff --git a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi index 39db2783c37..87586b6a0d8 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi @@ -140,4 +140,10 @@ ; }; }; + + pwm2_default: pwm2_default{ + group1 { + pinmux = ; + }; + }; }; diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.dts b/boards/ambiq/apollo3_evb/apollo3_evb.dts index ed7a0494a70..2c295508e9a 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb.dts +++ b/boards/ambiq/apollo3_evb/apollo3_evb.dts @@ -28,8 +28,8 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; - bootloader-led0 = &led0; mcuboot-led0 = &led0; + pwm-led0 = &pwm_led0; }; leds { @@ -74,6 +74,15 @@ zephyr,code = ; }; }; + + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; }; &flash0 { @@ -159,8 +168,20 @@ }; }; -&counter0 { - status = "disabled"; +&timer0 { + counter0: counter { + status = "disabled"; + }; +}; + +&timer2 { + pwm2: pwm { + timer-segment = "SEGMENT_B"; + pwm-type = "PWM_REPEAT"; + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + status = "disabled"; + }; }; &rtc0 { diff --git a/boards/ambiq/apollo3p_evb/Kconfig.defconfig b/boards/ambiq/apollo3p_evb/Kconfig.defconfig index 5e677acf238..8ed83de8742 100644 --- a/boards/ambiq/apollo3p_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo3p_evb/Kconfig.defconfig @@ -1,11 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 # -# Copyright (c) 2024 Ambiq Micro Inc. +# Copyright (c) 2024-2025 Ambiq Micro Inc. if BOARD_APOLLO3P_EVB config SYS_CLOCK_HW_CYCLES_PER_SEC default 32768 if AMBIQ_STIMER_TIMER + default 48000000 if CORTEX_M_SYSTICK config LOG_BACKEND_SWO_FREQ_HZ default 1000000 diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi index f8821a4c2f8..a6087b30843 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi @@ -179,4 +179,10 @@ ; }; }; + + pwm2_default: pwm2_default{ + group1 { + pinmux = ; + }; + }; }; diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts index 8b337138974..32268916366 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts @@ -26,6 +26,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + pwm-led0 = &pwm_led0; }; leds { @@ -70,6 +71,15 @@ zephyr,code = ; }; }; + + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; }; &flash0 { @@ -137,8 +147,20 @@ }; }; -&counter0 { - status = "disabled"; +&timer0 { + counter0: counter { + status = "disabled"; + }; +}; + +&timer2 { + pwm2: pwm { + timer-segment = "SEGMENT_B"; + pwm-type = "PWM_REPEAT"; + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + status = "disabled"; + }; }; &rtc0 { diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig index 2bcd67ff17c..c5d22a3d516 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig @@ -1,11 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 # -# Copyright (c) 2023 Ambiq Micro Inc. +# Copyright (c) 2023-2025 Ambiq Micro Inc. if BOARD_APOLLO4P_BLUE_KXR_EVB config SYS_CLOCK_HW_CYCLES_PER_SEC default 32768 if AMBIQ_STIMER_TIMER + default 96000000 if CORTEX_M_SYSTICK config LOG_BACKEND_SWO_FREQ_HZ default 1000000 diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi index 2cf596eadcd..4d63b444bb7 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi @@ -170,4 +170,11 @@ drive-strength = "0.1"; }; }; + pwm2_default: pwm2_default{ + group1 { + pinmux = ; + drive-open-drain; + drive-strength = "0.5"; + }; + }; }; diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts index f33e454272e..f701b27d8d7 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts @@ -26,6 +26,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + pwm-led0 = &pwm_led0; }; leds { @@ -60,6 +61,15 @@ status = "okay"; }; }; + + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; }; &uart0 { @@ -75,8 +85,18 @@ status = "okay"; }; -&counter0 { - status = "disabled"; +&timer0 { + counter0: counter { + status = "disabled"; + }; +}; + +&timer2 { + pwm2: pwm { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + status = "disabled"; + }; }; &rtc0 { diff --git a/boards/ambiq/apollo4p_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_evb/Kconfig.defconfig index 782fec1cfb6..66047990ea4 100644 --- a/boards/ambiq/apollo4p_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo4p_evb/Kconfig.defconfig @@ -1,11 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 # -# Copyright (c) 2024 Ambiq Micro Inc. +# Copyright (c) 2024-2025 Ambiq Micro Inc. if BOARD_APOLLO4P_EVB config SYS_CLOCK_HW_CYCLES_PER_SEC default 32768 if AMBIQ_STIMER_TIMER + default 96000000 if CORTEX_M_SYSTICK config LOG_BACKEND_SWO_FREQ_HZ default 1000000 diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi index ccfdfd72974..eb9a0502704 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi @@ -192,4 +192,11 @@ ambiq,pull-up-ohms = <12000>; }; }; + pwm2_default: pwm2_default{ + group1 { + pinmux = ; + drive-open-drain; + drive-strength = "0.5"; + }; + }; }; diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts index 567ec2143fe..9be6be85d88 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts @@ -25,6 +25,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + pwm-led0 = &pwm_led0; }; leds { @@ -59,6 +60,14 @@ status = "okay"; }; }; + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; }; &uart0 { @@ -80,8 +89,18 @@ status = "disabled"; }; -&counter0 { - status = "disabled"; +&timer0 { + counter0: counter { + status = "disabled"; + }; +}; + +&timer2 { + pwm2: pwm { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + status = "disabled"; + }; }; &rtc0 { @@ -158,11 +177,11 @@ pinctrl-names = "default"; txdelay = <0>; rxdelay = <0>; - status = "disabled"; + status = "okay"; mmc { compatible = "zephyr,mmc-disk"; disk-name = "SD2"; - status = "disabled"; + status = "okay"; }; }; diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml b/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml index b54f5d4150c..934a8a0c0aa 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml @@ -18,6 +18,7 @@ supported: - adc - hwinfo - usbd + - sdhc testing: ignore_tags: - net diff --git a/boards/ambiq/apollo510_evb/Kconfig.defconfig b/boards/ambiq/apollo510_evb/Kconfig.defconfig index 8fd84d081a0..3494b7ad8bf 100644 --- a/boards/ambiq/apollo510_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo510_evb/Kconfig.defconfig @@ -19,4 +19,18 @@ config MSPI_INIT_PRIORITY endif # MSPI +if MEMC + +config MEMC_INIT_PRIORITY + default 50 + +endif # MEMC + +if FLASH + +config FLASH_INIT_PRIORITY + default 50 + +endif # FLASH + endif # BOARD_APOLLO510_EVB diff --git a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi index 2f1472fc061..6c984d36bde 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi @@ -18,6 +18,12 @@ }; }; + uart0_sleep: uart0_sleep { + group1 { + pinmux = , ; + }; + }; + swo_default: swo_default { group0 { pinmux = ; @@ -26,7 +32,7 @@ adc0_default: adc0_default{ group1 { - pinmux = , ; + pinmux = , ; drive-strength = "0.1"; }; }; @@ -40,6 +46,12 @@ }; }; + i2c0_sleep: i2c0_sleep { + group1 { + pinmux = , ; + }; + }; + i2c1_default: i2c1_default { group1 { pinmux = , ; @@ -49,6 +61,12 @@ }; }; + i2c1_sleep: i2c1_sleep { + group1 { + pinmux = , ; + }; + }; + i2c2_default: i2c2_default { group1 { pinmux = , ; @@ -58,6 +76,12 @@ }; }; + i2c2_sleep: i2c2_sleep { + group1 { + pinmux = , ; + }; + }; + i2c3_default: i2c3_default { group1 { pinmux = , ; @@ -67,6 +91,27 @@ }; }; + i2c3_sleep: i2c3_sleep { + group1 { + pinmux = , ; + }; + }; + + i2c4_default: i2c4_default { + group1 { + pinmux = , ; + drive-open-drain; + drive-strength = "0.5"; + bias-pull-up; + }; + }; + + i2c4_sleep: i2c4_sleep { + group1 { + pinmux = , ; + }; + }; + i2c5_default: i2c5_default { group1 { pinmux = , ; @@ -76,6 +121,12 @@ }; }; + i2c5_sleep: i2c5_sleep { + group1 { + pinmux = , ; + }; + }; + i2c6_default: i2c6_default { group1 { pinmux = , ; @@ -85,6 +136,12 @@ }; }; + i2c6_sleep: i2c6_sleep { + group1 { + pinmux = , ; + }; + }; + i2c7_default: i2c7_default { group1 { pinmux = , ; @@ -94,60 +151,145 @@ }; }; + i2c7_sleep: i2c7_sleep { + group1 { + pinmux = , ; + }; + }; + spid0_default: spid0_default { group1 { pinmux = , , , ; }; }; + spid0_sleep: spid0_sleep { + group1 { + pinmux = , , , ; + }; + }; + spi0_default: spi0_default { group1 { pinmux = , , ; }; }; + spi0_sleep: spi0_sleep { + group1 { + pinmux = , , ; + }; + }; + spi1_default: spi1_default { group1 { pinmux = , , ; }; }; + spi1_sleep: spi1_sleep { + group1 { + pinmux = , , ; + }; + }; + spi2_default: spi2_default { group1 { pinmux = , , ; }; }; + spi2_sleep: spi2_sleep { + group1 { + pinmux = , , ; + }; + }; + spi3_default: spi3_default { group1 { pinmux = , , ; }; }; + spi3_sleep: spi3_sleep { + group1 { + pinmux = , , ; + }; + }; + spi4_default: spi4_default { group1 { pinmux = , , ; }; }; + spi4_sleep: spi4_sleep { + group1 { + pinmux = , , ; + }; + }; + spi5_default: spi5_default { group1 { pinmux = , , ; }; }; + spi5_sleep: spi5_sleep { + group1 { + pinmux = , , ; + }; + }; + spi6_default: spi6_default { group1 { pinmux = , , ; }; }; + spi6_sleep: spi6_sleep { + group1 { + pinmux = , , ; + }; + }; + spi7_default: spi7_default { group1 { pinmux = , , ; }; }; + spi7_sleep: spi7_sleep { + group1 { + pinmux = , , ; + }; + }; + + pdm0_default: pdm0_default { + group0 { + pinmux = , + ; + }; + }; + + i2s0_default: i2s0_default { + group0 { + pinmux = , + , + , + ; + }; + }; + + i2s1_default: i2s1_default { + group0 { + pinmux = , + , + , + ; + }; + }; + mspi0_default: mspi0_default { group0 { pinmux = , @@ -263,4 +405,86 @@ drive-strength = "0.5"; }; }; + + pwm2_default: pwm2_default{ + group1 { + pinmux = ; + drive-open-drain; + drive-strength = "0.5"; + }; + }; + + sdio0_default: sdio0_default { + group0 { + pinmux = , + , + , + , + , + ; + drive-strength = "1.0"; + }; + group1 { + pinmux = , + , + , + ; + drive-strength = "1.0"; + bias-pull-up; + ambiq,pull-up-ohms = <12000>; + }; + group2 { + pinmux = ; + ambiq,sdif-cdwp = <1>; + }; + group3 { + pinmux = ; + ambiq,sdif-cdwp = <2>; + }; + group4 { + pinmux = ; + ambiq,sdif-cdwp = <3>; + }; + group5 { + pinmux = ; + ambiq,sdif-cdwp = <4>; + }; + }; + + sdio1_default: sdio1_default { + group0 { + pinmux = , + , + , + , + , + ; + drive-strength = "1.0"; + }; + group1 { + pinmux = , + , + , + ; + drive-strength = "1.0"; + bias-pull-up; + ambiq,pull-up-ohms = <12000>; + }; + group2 { + pinmux = ; + ambiq,sdif-cdwp = <1>; + }; + group3 { + pinmux = ; + ambiq,sdif-cdwp = <2>; + }; + group4 { + pinmux = ; + ambiq,sdif-cdwp = <3>; + }; + group5 { + pinmux = ; + ambiq,sdif-cdwp = <4>; + }; + }; }; diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.dts b/boards/ambiq/apollo510_evb/apollo510_evb.dts index 4d4b898629c..88bba2871a5 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb.dts +++ b/boards/ambiq/apollo510_evb/apollo510_evb.dts @@ -27,6 +27,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + pwm-led0 = &pwm_led0; }; sram0: memory@SSRAM_BASE_NAME { @@ -78,6 +79,15 @@ status = "okay"; }; }; + + pwmleds: pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; }; &xo32m_xtal { @@ -95,8 +105,18 @@ status = "disabled"; }; -&counter0 { - status = "disabled"; +&timer0 { + counter0: counter { + status = "disabled"; + }; +}; + +&timer2 { + pwm2: pwm { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; + status = "disabled"; + }; }; &rtc0 { @@ -107,7 +127,8 @@ &uart0 { current-speed = <115200>; pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -119,6 +140,130 @@ status = "okay"; }; +&mspi0 { + pinctrl-0 = <&mspi0_default>; + pinctrl-1 = <&mspi0_sleep>; + pinctrl-2 = <&mspi0_psram>; + pinctrl-names = "default","sleep","psram"; + status = "disabled"; + zephyr,pm-device-runtime-auto; + + ce-gpios = <&gpio192_223 7 GPIO_ACTIVE_LOW>; + + cmdq-buffer-location = "SRAM_NO_CACHE"; + cmdq-buffer-size = <256>; + + ambiq,apmemory; + + dqs-support; + + aps51216ba: aps_z8@0 { + compatible = "ambiq,mspi-device", "mspi-aps-z8"; + size = ; + reg = <0>; + status = "disabled"; + mspi-max-frequency = <125000000>; + mspi-io-mode = "MSPI_IO_MODE_HEX_8_8_16"; + mspi-data-rate = "MSPI_DATA_RATE_S_D_D"; + mspi-hardware-ce-num = <0>; + mspi-dqs-enable; + read-command = <0x20>; + write-command = <0xA0>; + command-length = "INSTR_1_BYTE"; + address-length = "ADDR_4_BYTE"; + rx-dummy = <7>; + tx-dummy = <8>; + xip-config = <1 0 DT_SIZE_M(64) 0>; + ce-break-config = <1024 4>; + ambiq,timing-config-mask = <0x62>; + ambiq,timing-config = <8 7 1 0 0 3 10>; + zephyr,pm-device-runtime-auto; + }; +}; + +&mspi1 { + pinctrl-0 = <&mspi1_default>; + pinctrl-1 = <&mspi1_sleep>; + pinctrl-2 = <&mspi1_flash>; + pinctrl-names = "default","sleep","flash"; + status = "okay"; + zephyr,pm-device-runtime-auto; + + ce-gpios = <&gpio32_63 21 GPIO_ACTIVE_LOW>; + + cmdq-buffer-location = "SRAM_NO_CACHE"; + cmdq-buffer-size = <256>; + + dqs-support; + + is25wx064: is25wx064@0 { + compatible = "ambiq,mspi-device", "mspi-is25xX0xx"; + size = ; + reg = <0>; + status = "disabled"; + mspi-max-frequency = <96000000>; + mspi-io-mode = "MSPI_IO_MODE_OCTAL_1_8_8"; + mspi-data-rate = "MSPI_DATA_RATE_SINGLE"; + mspi-dqs-enable; + mspi-hardware-ce-num = <0>; + read-command = <0xCC>; + write-command = <0x8E>; + command-length = "INSTR_1_BYTE"; + address-length = "ADDR_4_BYTE"; /* Avoid use of 3 byte address if Ambiq MSPI */ + rx-dummy = <16>; + tx-dummy = <0>; + xip-config = <1 0 DT_SIZE_M(8) 0>; + ce-break-config = <0 0>; + ambiq,timing-config-mask = <0x62>; + ambiq,timing-config = <0 16 1 0 0 5 20>; + }; +}; + +&sdio0 { + pinctrl-0 = <&sdio0_default>; + pinctrl-names = "default"; + txdelay = <0>; + rxdelay = <0>; + status = "okay"; + mmc { + compatible = "zephyr,mmc-disk"; + disk-name = "SD2"; + status = "okay"; + }; +}; + +&sdio1 { + pinctrl-0 = <&sdio1_default>; + pinctrl-names = "default"; + txdelay = <9>; + rxdelay = <11>; + status = "okay"; +}; + +zephyr_udc0: &usb { + vddusb33-gpios = <&gpio64_95 27 (GPIO_PULL_UP)>; + vddusb0p9-gpios = <&gpio64_95 26 (GPIO_PULL_UP)>; + status = "okay"; +}; + +&pdm0 { + pinctrl-0 = <&pdm0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&i2s1 { + pinctrl-0 = <&i2s1_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + &gpio0_31 { status = "okay"; }; diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.yaml b/boards/ambiq/apollo510_evb/apollo510_evb.yaml index ca2353540b4..df8e3268398 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb.yaml +++ b/boards/ambiq/apollo510_evb/apollo510_evb.yaml @@ -18,7 +18,11 @@ supported: - rtc - hwinfo - clock_control + - usbd + - pdm + - i2s - mspi + - sdhc testing: ignore_tags: - net diff --git a/boards/amd/kv260_r5/support/xsdb.cfg b/boards/amd/kv260_r5/support/xsdb.cfg index 2976c9e763f..8639d93b2ab 100644 --- a/boards/amd/kv260_r5/support/xsdb.cfg +++ b/boards/amd/kv260_r5/support/xsdb.cfg @@ -2,23 +2,86 @@ # # SPDX-License-Identifier: Apache-2.0 +proc boot_jtag { } { + # switch to JTAG boot mode # + targets -set -filter {name =~ "PSU*"} + stop + # update multiboot to ZERO + mwr 0xffca0010 0x0 + # change boot mode to JTAG + mwr 0xff5e0200 0x0100 + # reset + rst -system +} + proc load_image args { set elf_file [lindex $args 0] - set fsblelf_file [lindex $args 1] - connect -url 127.0.0.1:3121 + set bitfile [lindex $args 1] + set fsblelf_file [lindex $args 2] + + if { [info exists ::env(HW_SERVER_URL)] } { + connect -url $::env(HW_SERVER_URL) + } else { + connect + } + after 2000 + + # setup jtag boot mode + boot_jtag + after 2000 + targets -set -nocase -filter {name =~ "*R5*#0"} + + # load bitstream if passed + if { [string length $bitfile] != 0 } { + fpga -f $bitfile -no-revision-check + } + rst -proc - dow $fsblelf_file - after 1000 - con - after 1000 - stop - targets -set -nocase -filter {name =~ "*R5*#0"} + + # load FSBL if passed + if { [string length $fsblelf_file] != 0 } { + dow $fsblelf_file + after 1000 + con + after 1000 + stop + } + after 2000 dow $elf_file con exit } -load_image {*}$argv +switch $argc { + "1" { + set zephyr_elf [lindex $argv 0] + set bitstream "" + set fsbl_elf "" + } + "2" { + set par [lindex $argv 1] + set substring "*.bit" + if { [string match -nocase $substring $par] == 0 } { + set bitstream "" + set fsbl_elf $par + } else { + set bitstream $par + set fsbl_elf "" + } + set zephyr_elf [lindex $argv 0] + } + "3" { + set zephyr_elf [lindex $argv 0] + set bitstream [lindex $argv 1] + set fsbl_elf [lindex $argv 2] + } + default { + puts "Unsifficient number for args" + exit -1 + } +} + +load_image "$zephyr_elf" "$bitstream" "$fsbl_elf" diff --git a/boards/amd/versal2_rpu/support/xsdb.cfg b/boards/amd/versal2_rpu/support/xsdb.cfg index 88313923170..e800adebc67 100644 --- a/boards/amd/versal2_rpu/support/xsdb.cfg +++ b/boards/amd/versal2_rpu/support/xsdb.cfg @@ -3,27 +3,27 @@ # SPDX-License-Identifier: Apache-2.0 proc rpu0_core0_rst { {mem "default"} } { - targets -set -filter {name =~ "DAP*"} - #CRL write protect - mwr -force 0xeb5e001c 0x0 - mwr -force 0xEB580000 1 + targets -set -filter {name =~ "Versal Gen 2*"} + # CRL write protect + mwr -force 0xeb5e001c 0 + mwr -force 0xeb580000 1 mwr -force 0xbbf20000 0xeafffffe # write BASE_HI and BASE_LO - if {$mem eq "ddr"} { - set addr 0x100000 - } elseif {$mem eq "tcm"} { - set addr 0x0 - } elseif {$mem eq "default"} { - set addr 0xbbf20000 - } - mwr -force 0xEB588008 $addr + if {$mem eq "ddr"} { + set addr 0x100000 + } elseif {$mem eq "tcm"} { + set addr 0 + } elseif {$mem eq "default"} { + set addr 0xbbf20000 + } + mwr -force 0xeb588008 $addr # write TCMBOOT as one - mask_write 0xEB588000 0x10 0x10 + mask_write 0xeb588000 0x10 0x10 # reset CORE0A_RESET out of reset A_TOPRESET and CORE0A_POR - mask_write 0xEB5E0310 0x10101 0x1 + mask_write 0xeb5e0310 0x10101 0x1 # out of reset CORE0A_RESET - mask_write 0xEB5E0310 0x1 0x0 - targets -set -filter {name =~ "Cortex-R52*0" && parent =~ "*0x00100000"} + mask_write 0xeb5e0310 0x1 0 + targets -set -filter {name =~ "Cortex-R52*0.0"} after 300 stop after 1000 @@ -33,6 +33,7 @@ proc rpu0_core0_rst { {mem "default"} } { proc load_image args { set elf_file [lindex $args 0] + set pdi_file [lindex $args 1] if { [info exists ::env(HW_SERVER_URL)] } { connect -url $::env(HW_SERVER_URL) @@ -40,12 +41,7 @@ proc load_image args { connect } - if { [info exists ::env(PDI_FILE_PATH)] } { - device program $::env(PDI_FILE_PATH) - } else { - puts "Error: env variable PDI_FILE_PATH is not set" - exit - } + device program $pdi_file if { [info exists ::env(HW_SERVER_URL)] } { set hw_server_url [split $::env(HW_SERVER_URL) ":"] @@ -58,7 +54,7 @@ proc load_image args { ta } after 1000 - targets -set -nocase -filter {name =~ "DAP*"} + targets -set -filter {name =~ "Versal Gen 2*"} after 100 # Configure timestamp generator to run global timer gracefully # Ideally these registers should be set from bootloader (cdo) diff --git a/boards/amd/versalnet_rpu/support/xsdb.cfg b/boards/amd/versalnet_rpu/support/xsdb.cfg index 087ed4c85c1..809e974f83e 100644 --- a/boards/amd/versalnet_rpu/support/xsdb.cfg +++ b/boards/amd/versalnet_rpu/support/xsdb.cfg @@ -4,6 +4,7 @@ proc load_image args { set elf_file [lindex $args 0] + set pdi_file [lindex $args 1] if { [info exists ::env(HW_SERVER_URL)] } { connect -url $::env(HW_SERVER_URL) @@ -17,12 +18,7 @@ proc load_image args { rst -system after 100 - if { [info exists ::env(PDI_FILE_PATH)] } { - device program $::env(PDI_FILE_PATH) - } else { - puts "Error: env variable PDI_FILE_PATH is not set" - exit - } + device program $pdi_file after 100 targets -set -nocase -filter {name =~ "DPC"} diff --git a/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k b/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k index a1a3daffac8..8cf2c3fb842 100644 --- a/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k +++ b/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k @@ -3,3 +3,4 @@ config BOARD_ADP_XC7K select SOC_ANDES_AE350 if BOARD_ADP_XC7K_AE350 + select SOC_ANDES_AE350_CLIC if BOARD_ADP_XC7K_AE350_CLIC diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts index 09763df9fff..c05eea810c3 100644 --- a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts @@ -7,213 +7,12 @@ /dts-v1/; #include +#include "adp_xc7k_ae350_common.dtsi" #include / { model = "Andes ADP-XC7K AE350"; compatible = "andestech,adp_xc7k_ae350"; - - aliases { - gpio-0 = &gpio0; - counter-0 = &pit0; - i2c-0 = &i2c0; - led0 = &seg7_led1_g; - led1 = &seg7_led2_g; - sw0 = &user_button1; - eeprom-0 = &eeprom; - }; - - chosen { - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,sram = &dram; - zephyr,flash = &mx25u16; - zephyr,flash-controller = &mx25u16; - }; - - leds { - compatible = "gpio-leds"; - - seg7_led1_a: led_1 { - label = "7SEG LED1 A"; - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - }; - seg7_led1_b: led_2 { - label = "7SEG LED1 B"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; - seg7_led1_c: led_3 { - label = "7SEG LED1 C"; - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - seg7_led1_d: led_4 { - label = "7SEG LED1 D"; - gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - }; - seg7_led1_e: led_5 { - label = "7SEG LED1 E"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - seg7_led1_f: led_6 { - label = "7SEG LED1 F"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - seg7_led1_g: led_7 { - label = "7SEG LED1 G"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - seg7_led1_dp: led_8 { - label = "7SEG LED1 DP"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - seg7_led2_a: led_9 { - label = "7SEG LED2 A"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - seg7_led2_b: led_10 { - label = "7SEG LED2 B"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - seg7_led2_c: led_11 { - label = "7SEG LED2 C"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - seg7_led2_d: led_12 { - label = "7SEG LED2 D"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - seg7_led2_e: led_13 { - label = "7SEG LED2 E"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - seg7_led2_f: led_14 { - label = "7SEG LED2 F"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - seg7_led2_g: led_15 { - label = "7SEG LED2 G"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - }; - seg7_led2_dp: led_16 { - label = "7SEG LED2 DP"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user_button1: button_1 { - label = "User SW1"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button2: button_2 { - label = "User SW2"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button3: button_3 { - label = "User SW3"; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button4: button_4 { - label = "User SW4"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button5: button_5 { - label = "User SW5"; - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button6: button_6 { - label = "User SW6"; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button7: button_7 { - label = "User SW7"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; -}; - -&l2_cache { - status = "okay"; -}; - -&syscon { - status = "okay"; -}; - -&uart1 { - status = "okay"; - clock-frequency = <19660800>; - current-speed = <115200>; -}; - -&gpio0 { - status = "okay"; -}; - -&pit0 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - mx25u16: qspi-nor-flash@0 { - compatible = "jedec,spi-nor", "andestech,qspi-nor"; - size = <16777216>; - spi-max-frequency = <10000000>; - jedec-id = [c2 25 35]; - status = "okay"; - reg = <0>; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb - fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 - 10 d8 00 ff - ]; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - storage_partition: partition@0 { - label = "storage"; - reg = <0x0 DT_SIZE_K(1024)>; - }; - }; - }; -}; - -&i2c0 { - status = "okay"; - eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - status = "okay"; - size = <16384>; - pagesize = <64>; - address-width = <16>; - timeout = <5>; - }; -}; - -&spi1 { - status = "okay"; - cs-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; -}; - -&wdt { - status = "okay"; -}; - -&dma0 { - status = "okay"; }; &mbox { diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic.dts b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic.dts new file mode 100644 index 00000000000..f1ea692f4c2 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic.dts @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "adp_xc7k_ae350_common.dtsi" +#include + +/ { + model = "Andes ADP-XC7K AE350 CLIC"; + compatible = "andestech,adp_xc7k_ae350-clic"; +}; diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic.yaml b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic.yaml new file mode 100644 index 00000000000..f4eb762d36b --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic.yaml @@ -0,0 +1,24 @@ +identifier: adp_xc7k/ae350/clic +name: Andes ADP-XC7K AE350 CLIC +type: mcu +arch: riscv +toolchain: + - zephyr + - cross-compile +ram: 512 +supported: + - gpio + - counter + - i2c + - spi + - eeprom + - watchdog + - flash + - dma + - led + - syscon + - hwinfo +testing: + ignore_tags: + - bluetooth +vendor: andestech diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic_defconfig b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic_defconfig new file mode 100644 index 00000000000..f34e627aed5 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_clic_defconfig @@ -0,0 +1,15 @@ +CONFIG_XIP=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Serial driver options +CONFIG_SERIAL=y + +# GPIO driver options +CONFIG_GPIO=y + +# PMP granularity options +CONFIG_PMP_GRANULARITY=8 + +# EXEC.IT options +CONFIG_SOC_ANDES_V5_EXECIT=y diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_common.dtsi b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_common.dtsi new file mode 100644 index 00000000000..20bfe4e02a1 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_common.dtsi @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2025 Andes Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + gpio-0 = &gpio0; + counter-0 = &pit0; + i2c-0 = &i2c0; + led0 = &seg7_led1_g; + led1 = &seg7_led2_g; + sw0 = &user_button1; + eeprom-0 = &eeprom; + }; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &dram; + zephyr,flash = &mx25u16; + zephyr,flash-controller = &mx25u16; + }; + + leds { + compatible = "gpio-leds"; + + seg7_led1_a: led_1 { + label = "7SEG LED1 A"; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + seg7_led1_b: led_2 { + label = "7SEG LED1 B"; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + seg7_led1_c: led_3 { + label = "7SEG LED1 C"; + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + seg7_led1_d: led_4 { + label = "7SEG LED1 D"; + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + }; + seg7_led1_e: led_5 { + label = "7SEG LED1 E"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + seg7_led1_f: led_6 { + label = "7SEG LED1 F"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + seg7_led1_g: led_7 { + label = "7SEG LED1 G"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + seg7_led1_dp: led_8 { + label = "7SEG LED1 DP"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + seg7_led2_a: led_9 { + label = "7SEG LED2 A"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + seg7_led2_b: led_10 { + label = "7SEG LED2 B"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + seg7_led2_c: led_11 { + label = "7SEG LED2 C"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + seg7_led2_d: led_12 { + label = "7SEG LED2 D"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + seg7_led2_e: led_13 { + label = "7SEG LED2 E"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + seg7_led2_f: led_14 { + label = "7SEG LED2 F"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + seg7_led2_g: led_15 { + label = "7SEG LED2 G"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + seg7_led2_dp: led_16 { + label = "7SEG LED2 DP"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button2: button_2 { + label = "User SW2"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button3: button_3 { + label = "User SW3"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button4: button_4 { + label = "User SW4"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button5: button_5 { + label = "User SW5"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button6: button_6 { + label = "User SW6"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button7: button_7 { + label = "User SW7"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&l2_cache { + status = "okay"; +}; + +&syscon { + status = "okay"; +}; + +&uart1 { + status = "okay"; + clock-frequency = <20000000>; + current-speed = <115200>; +}; + +&gpio0 { + status = "okay"; +}; + +&pit0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + mx25u16: qspi-nor-flash@0 { + compatible = "jedec,spi-nor", "andestech,qspi-nor"; + size = <16777216>; + spi-max-frequency = <10000000>; + jedec-id = [c2 25 35]; + status = "okay"; + reg = <0>; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb + fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 + 10 d8 00 ff + ]; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_K(1024)>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + status = "okay"; + size = <16384>; + pagesize = <64>; + address-width = <16>; + timeout = <5>; + }; +}; + +&spi1 { + status = "okay"; + cs-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; +}; + +&wdt { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig index 78a5b22ff6f..f34e627aed5 100644 --- a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig @@ -8,40 +8,8 @@ CONFIG_SERIAL=y # GPIO driver options CONFIG_GPIO=y -# Syscon driver options -CONFIG_SYSCON=y - -# hwinfo driver options -CONFIG_HWINFO=y -CONFIG_HWINFO_ANDES=y - -# RV64 options -#CONFIG_RV64I_CPU=y - -# FPU (single precision) options -#CONFIG_FPU=y -#CONFIG_FPU_SHARING=y -#CONFIG_FLOAT_HARD=y -#CONFIG_SINGLE_PRECISION_FPU=y - -# FPU (double precision) options -#CONFIG_FPU=y -#CONFIG_FPU_SHARING=y -#CONFIG_FLOAT_HARD=y -#CONFIG_DOUBLE_PRECISION_FPU=y - # PMP granularity options CONFIG_PMP_GRANULARITY=8 -# HW DSP options -#CONFIG_SOC_ANDES_V5_HWDSP=y - # EXEC.IT options -#CONFIG_SOC_ANDES_V5_EXECIT=y - -# Nocache memory options -#CONFIG_SOC_ANDES_V5_PMA=y -#CONFIG_NOCACHE_MEMORY=y - -# I/O Coherence Port options -#CONFIG_SOC_ANDES_V5_IOCP=y +CONFIG_SOC_ANDES_V5_EXECIT=y diff --git a/boards/andestech/adp_xc7k_ae350/board.yml b/boards/andestech/adp_xc7k_ae350/board.yml index 7c8ace7d5a0..f5ebd50f73d 100644 --- a/boards/andestech/adp_xc7k_ae350/board.yml +++ b/boards/andestech/adp_xc7k_ae350/board.yml @@ -4,3 +4,5 @@ board: vendor: andestech socs: - name: ae350 + variants: + - name: clic diff --git a/boards/arduino/giga_r1/arduino_giga_r1.dtsi b/boards/arduino/giga_r1/arduino_giga_r1.dtsi index d0e8863967e..0dc6a912f9f 100644 --- a/boards/arduino/giga_r1/arduino_giga_r1.dtsi +++ b/boards/arduino/giga_r1/arduino_giga_r1.dtsi @@ -8,6 +8,10 @@ #include / { + aliases { + sdhc0 = &sdhc; + }; + leds { compatible = "gpio-leds"; red_led: led_0 { @@ -42,3 +46,26 @@ &mailbox { status = "okay"; }; + +sdhc: &sdmmc1 { + compatible = "st,stm32-sdio"; + interrupts = <49 0>; + interrupt-names = "event"; + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + pinctrl-names = "default"; + sdhi-on-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>; + min-bus-freq = ; + max-bus-freq = ; + hw-flow-control; + bus-width = <4>; + status = "okay"; + + wifi: airoc-wifi { + status = "okay"; + compatible = "infineon,airoc-wifi"; + wifi-reg-on-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>; + wifi-host-wake-gpios = <&gpioi 8 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts index 7505ba0f2df..4feba7fb1f3 100644 --- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts @@ -173,9 +173,10 @@ pinctrl-names = "default"; status = "okay"; - n25q128a1: qspi-nor-flash@90000000 { + n25q128a1: qspi-nor-flash@0 { compatible = "st,stm32-qspi-nor"; - reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */ + reg = <0>; + size = ; /* 128 Mbits */ qspi-max-frequency = <72000000>; status = "okay"; diff --git a/boards/arduino/mkrzero/arduino_mkrzero.dts b/boards/arduino/mkrzero/arduino_mkrzero.dts index 6a30c3be9d7..7b5b3ba8372 100644 --- a/boards/arduino/mkrzero/arduino_mkrzero.dts +++ b/boards/arduino/mkrzero/arduino_mkrzero.dts @@ -40,7 +40,7 @@ clock-frequency = <48000000>; }; -&sercom0 { +zephyr_i2c: &sercom0 { status = "okay"; compatible = "atmel,sam0-i2c"; clock-frequency = ; diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi b/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi index 589d5b66241..082a9935c12 100644 --- a/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi @@ -173,6 +173,11 @@ arduino_i2c: &i2c0 { reg = <0x6b>; }; + lsm9ds1_mag: lsm9ds1_mag@1e { + compatible = "st,lsm9ds1_mag"; + reg = <0x1e>; + }; + }; /* SPI2 is used because SPI1/0 shares conflicts with I2C1/0 */ diff --git a/boards/arduino/nano_matter/Kconfig.arduino_nano_matter b/boards/arduino/nano_matter/Kconfig.arduino_nano_matter new file mode 100644 index 00000000000..90050711f60 --- /dev/null +++ b/boards/arduino/nano_matter/Kconfig.arduino_nano_matter @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# Copyright (c) 2025 Pete Johanson +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_NANO_MATTER + select SOC_MGM240SD22VNA diff --git a/boards/arduino/nano_matter/Kconfig.defconfig b/boards/arduino/nano_matter/Kconfig.defconfig new file mode 100644 index 00000000000..fac9aba27b5 --- /dev/null +++ b/boards/arduino/nano_matter/Kconfig.defconfig @@ -0,0 +1,34 @@ +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# Copyright (c) 2025 Pete Johanson +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_NANO_MATTER + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_ARDUINO_NANO_MATTER diff --git a/boards/arduino/nano_matter/arduino_nano_matter-pinctrl.dtsi b/boards/arduino/nano_matter/arduino_nano_matter-pinctrl.dtsi new file mode 100644 index 00000000000..d4fa32ac585 --- /dev/null +++ b/boards/arduino/nano_matter/arduino_nano_matter-pinctrl.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2025 Pete Johanson + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + eusart0_default: eusart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + eusart1_default: eusart1_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; + + timer0_default: timer0_default { + group0 { + pins = , , ; + drive-push-pull; + output-high; + }; + }; + + usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; +}; diff --git a/boards/arduino/nano_matter/arduino_nano_matter.dts b/boards/arduino/nano_matter/arduino_nano_matter.dts new file mode 100644 index 00000000000..53bdc166f63 --- /dev/null +++ b/boards/arduino/nano_matter/arduino_nano_matter.dts @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2025 Pete Johanson + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "arduino_nano_matter-pinctrl.dtsi" +#include "arduino_nano_matter_connector.dtsi" + +/ { + model = "Arduino Nano Matter"; + compatible = "arduino,arduino_nano_matter", "silabs,mgm240sd22vna"; + + chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart0; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + pwm-led0 = &red_pwm_led; + pwm-led1 = &green_pwm_led; + pwm-led2 = &blue_pwm_led; + sw0 = &button0; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + label = "LED 0"; + }; + + led1: led_1 { + gpios = <&gpioc 2 GPIO_ACTIVE_LOW>; + label = "LED 1"; + }; + + led2: led_2 { + gpios = <&gpioc 3 GPIO_ACTIVE_LOW>; + label = "LED 2"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + red_pwm_led: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "red"; + }; + + green_pwm_led: pwm_led_1 { + pwms = <&timer0_pwm 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "green"; + }; + + blue_pwm_led: pwm_led_2 { + pwms = <&timer0_pwm 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "blue"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&cpu0 { + clock-frequency = <78000000>; +}; + +&pstate_em3 { + status = "disabled"; +}; + +&hfxo { + ctune = <95>; + precision = <50>; + status = "okay"; +}; + +&lfxo { + ctune = <44>; + precision = <50>; + status = "okay"; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <1919>; + dpll-n = <3839>; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&eusart0 { + compatible = "silabs,eusart-uart"; + current-speed = <115200>; + pinctrl-0 = <&eusart0_default>; + pinctrl-names = "default"; +}; + +&eusart1 { + compatible = "silabs,eusart-spi"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <4000000>; + cs-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + reg = <0x0 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 736 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 0x000B8000>; + label = "image-0"; + }; + + /* Reserve 736 kB for the application in slot 1 */ + slot1_partition: partition@C4000 { + reg = <0x000C4000 0x000B8000>; + label = "image-1"; + }; + + /* Set 16 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@17c000 { + reg = <0x0017c000 DT_SIZE_K(16)>; + label = "storage"; + }; + }; +}; + +&bt_hci_silabs { + status = "okay"; +}; diff --git a/boards/arduino/nano_matter/arduino_nano_matter.yaml b/boards/arduino/nano_matter/arduino_nano_matter.yaml new file mode 100644 index 00000000000..01140066db9 --- /dev/null +++ b/boards/arduino/nano_matter/arduino_nano_matter.yaml @@ -0,0 +1,20 @@ +identifier: arduino_nano_matter +name: Arduino Nano Matter +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr + - gnuarmemb +supported: + - bluetooth + - gpio + - uart + - dma + - watchdog + - comparator +testing: + ignore_tags: + - pm +vendor: arduino diff --git a/boards/arduino/nano_matter/arduino_nano_matter_connector.dtsi b/boards/arduino/nano_matter/arduino_nano_matter_connector.dtsi new file mode 100644 index 00000000000..8641ba473a8 --- /dev/null +++ b/boards/arduino/nano_matter/arduino_nano_matter_connector.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2025 Peter Johanson + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_nano_matter_d: connector { + compatible = "arduino,arduino_nano_matter-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 4 0>, /* D0 */ + <1 0 &gpioa 5 0>, /* D1 */ + <2 0 &gpioa 3 0>, /* D2 */ + <3 0 &gpioc 6 0>, /* D3 */ + <4 0 &gpioc 7 0>, /* D4 */ + <5 0 &gpioc 8 0>, /* D5 */ + <6 0 &gpioc 9 0>, /* D6 */ + <7 0 &gpiod 2 0>, /* D7 */ + <8 0 &gpiod 3 0>, /* D8 */ + <9 0 &gpiod 4 0>, /* D9 */ + <10 0 &gpiod 5 0>, /* D10 */ + <11 0 &gpioa 9 0>, /* D11 */ + <12 0 &gpioa 8 0>, /* D12 */ + <13 0 &gpiob 4 0>, /* D13 */ + <14 0 &gpiob 0 0>, /* A0 */ + <15 0 &gpiob 2 0>, /* A1 */ + <16 0 &gpiob 5 0>, /* A2 */ + <17 0 &gpioc 0 0>, /* A3 */ + <18 0 &gpioa 6 0>, /* A4 */ + <19 0 &gpioa 7 0>, /* A5 */ + <20 0 &gpiob 1 0>, /* A6 */ + <21 0 &gpiob 3 0>; /* A7 */ + }; +}; + +arduino_nano_matter_spi: &eusart1 {}; + +arduino_nano_matter_serial: &eusart0 {}; + +arduino_nano_matter_i2c: &i2c0 {}; diff --git a/boards/arduino/nano_matter/arduino_nano_matter_defconfig b/boards/arduino/nano_matter/arduino_nano_matter_defconfig new file mode 100644 index 00000000000..e70f8f5c519 --- /dev/null +++ b/boards/arduino/nano_matter/arduino_nano_matter_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y diff --git a/boards/arduino/nano_matter/board.cmake b/boards/arduino/nano_matter/board.cmake new file mode 100644 index 00000000000..83a839991dd --- /dev/null +++ b/boards/arduino/nano_matter/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(jlink "--device=MGM240SD22VNA") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arduino/nano_matter/board.yml b/boards/arduino/nano_matter/board.yml new file mode 100644 index 00000000000..cabd42d4f61 --- /dev/null +++ b/boards/arduino/nano_matter/board.yml @@ -0,0 +1,6 @@ +board: + name: arduino_nano_matter + full_name: Arduino Nano Matter + vendor: arduino + socs: + - name: mgm240sd22vna diff --git a/boards/arduino/nano_matter/doc/index.rst b/boards/arduino/nano_matter/doc/index.rst new file mode 100644 index 00000000000..7b065609de5 --- /dev/null +++ b/boards/arduino/nano_matter/doc/index.rst @@ -0,0 +1,121 @@ +.. zephyr:board:: arduino_nano_matter + +Overview +******** + +The Nano Matter merges the well-known Arduino way of making complex technology more accessible with the +powerful MGM240S from Silicon Labs, to bring Matter closer to the maker world, in one of the +smallest form factors in the market. + +It enables 802.15.4 (Thread®) and Bluetooth® Low Energy connectivity, to interact with Matter-compatible devices +with a user-friendly software layer ready for quick prototyping. + +The Nano Matter features a compact and efficient architecture powered by the +MGM240S (32-bit Arm® Cortex®-M33) from Silicon Labs, a high-performance wireless module optimized for +the needs of battery and line-powered IoT devices for 2.4 GHz mesh networks. + +Hardware +******** + +- MGM240SD22VNA2 Mighty Gecko SiP +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 1536 kB +- RAM: 256 kB +- Transmit power: up to +20 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz). +- User RGB LED +- User button + +For more information about the EFR32MG24 SoC and the Arduino Nano Matter, refer to these +documents: + +- `MGM240S Website`_ +- `EFR32MG24 Datasheet`_ +- `EFR32xG24 Reference Manual`_ +- `Nano Matter User Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+------------------+ +| Name | Function | Usage | ++=======+=============+==================+ +| PC1 | GPIO | LED0 | ++-------+-------------+------------------+ +| PC2 | GPIO | LED1 | ++-------+-------------+------------------+ +| PC3 | GPIO | LED2 | ++-------+-------------+------------------+ +| PA0 | GPIO | Button | ++-------+-------------+------------------+ +| PC4 | USART0_TX | UART Console TX | ++-------+-------------+------------------+ +| PC5 | USART0_RX | UART Console RX | ++-------+-------------+------------------+ + +System Clock +============ + +The MGM240S SiP is configured to run at 78 MHz using DPLL and the 39 MHz internal oscillator. + +Serial Port +=========== + +The MGM240S SiP has one USART and two EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +The Arduino Nano Matter contains an SAMD11 with CMSIS-DAP, allowing flashing, debugging, logging, etc. over +the USB port. Doing so requires a version of OpenOCD that includes support for the flash on the MG24 +MCU. Until those changes are included in stock OpenOCD, the version bundled with Arduino can be +used, or can be installed from the `OpenOCD Arduino Fork`_. When flashing, debugging, etc. you may +need to include ``--openocd=/usr/local/bin/openocd +--openocd-search=/usr/local/share/openocd/scripts/`` options to the command. + +Flashing +======== + +Connect the Arduino Nano Matter board to your host computer using the USB port. A USB CDC ACM serial port +should appear on the host, that can be used to view logs from the flashed application. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_nano_matter + :goals: flash + +Open a serial terminal (minicom, putty, etc.) connecting to the UCB CDC ACM serial port. + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! arduino_nano_matter + + +.. _Nano Matter User Manual: + https://docs.arduino.cc/tutorials/nano-matter/user-manual/ + +.. _MGM240S Website: + https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-modules/device.mgm240sd22vna + +.. _EFR32MG24 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf + +.. _EFR32xG24 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/brd4187c-rm.pdf + +.. _OpenOCD Arduino Fork: + https://github.com/facchinm/OpenOCD/tree/arduino-0.12.0-rtx5 diff --git a/boards/arduino/nano_matter/doc/nano_matter.webp b/boards/arduino/nano_matter/doc/nano_matter.webp new file mode 100644 index 00000000000..1ea99f86dab Binary files /dev/null and b/boards/arduino/nano_matter/doc/nano_matter.webp differ diff --git a/boards/arduino/nano_matter/pre_dt_board.cmake b/boards/arduino/nano_matter/pre_dt_board.cmake new file mode 100644 index 00000000000..8ac3805f61e --- /dev/null +++ b/boards/arduino/nano_matter/pre_dt_board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Linaro Limited +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/arduino/nano_matter/support/openocd.cfg b/boards/arduino/nano_matter/support/openocd.cfg new file mode 100644 index 00000000000..eed46c1687d --- /dev/null +++ b/boards/arduino/nano_matter/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the CMSIS-DAP interface + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32s2_g23.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts index 52e376ed140..c3bdfea7702 100644 --- a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts +++ b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts @@ -88,7 +88,7 @@ }; /* I2C1 in datasheet */ -&i2c1 { +zephyr_i2c: &i2c1 { compatible = "nordic,nrf-twim"; /* Cannot be used together with spi1. */ status = "okay"; diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi b/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi index cec25611b1b..7c9e908060d 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi +++ b/boards/arduino/nicla_vision/arduino_nicla_vision.dtsi @@ -5,6 +5,10 @@ */ / { + aliases { + sdhc0 = &sdhc; + }; + leds { compatible = "gpio-leds"; red_led: led_0 { @@ -31,3 +35,26 @@ &mailbox { status = "okay"; }; + +sdhc: &sdmmc2 { + compatible = "st,stm32-sdio"; + interrupts = <124 0>; + interrupt-names = "event"; + pinctrl-0 = <&sdmmc2_d0_pb14 &sdmmc2_d1_pb15 + &sdmmc2_d2_pg11 &sdmmc2_d3_pb4 + &sdmmc2_ck_pd6 &sdmmc2_cmd_pd7>; + pinctrl-names = "default"; + sdhi-on-gpios = <&gpiog 4 GPIO_ACTIVE_HIGH>; + min-bus-freq = ; + max-bus-freq = ; + hw-flow-control; + bus-width = <4>; + status = "okay"; + + wifi: airoc-wifi { + status = "okay"; + compatible = "infineon,airoc-wifi"; + wifi-reg-on-gpios = <&gpiog 4 GPIO_ACTIVE_HIGH>; + wifi-host-wake-gpios = <&gpiod 15 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts index e9f39b173ae..3e1c0ddc335 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts @@ -95,7 +95,7 @@ }; }; -&i2c1 { +zephyr_i2c: &i2c1 { status = "disabled"; pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; pinctrl-names = "default"; @@ -108,9 +108,9 @@ pinctrl-names = "default"; clock-frequency = ; - vl53l1x: vl53l1x@52 { + vl53l1x: vl53l1x@29 { compatible = "st,vl53l1x"; - reg = <0x52>; + reg = <0x29>; status = "okay"; xshut-gpios = <&gpiog 10 GPIO_ACTIVE_HIGH>; int-gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>; @@ -165,9 +165,10 @@ pinctrl-names = "default"; status = "okay"; - n25q128a1: qspi-nor-flash@90000000 { + n25q128a1: qspi-nor-flash@0 { compatible = "st,stm32-qspi-nor"; - reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */ + reg = <0>; + size = ; /* 128 Mbits */ qspi-max-frequency = <72000000>; status = "okay"; diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml index 0310b5dce89..90e7c42ca08 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml @@ -11,4 +11,5 @@ supported: - gpio - spi - i2c + - usbd vendor: arduino diff --git a/boards/arduino/opta/CMakeLists.txt b/boards/arduino/opta/CMakeLists.txt index 07d2bfea9bc..0e06493c1d2 100644 --- a/boards/arduino/opta/CMakeLists.txt +++ b/boards/arduino/opta/CMakeLists.txt @@ -1,4 +1,5 @@ # Copyright (c) 2021 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -zephyr_sources(board_gpio_init.c) +zephyr_sources(board_gpio_init.c board_info.c) +zephyr_include_directories(.) diff --git a/boards/arduino/opta/arduino_opta-external-flash-partitioning.dtsi b/boards/arduino/opta/arduino_opta-external-flash-partitioning.dtsi new file mode 100644 index 00000000000..2a9908aee50 --- /dev/null +++ b/boards/arduino/opta/arduino_opta-external-flash-partitioning.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 DNDG srl + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&quadspi { + qspi_flash: qspi-nor-flash@90000000 { + + /delete-node/ partitions; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Partition 1: WiFi firmware and certificates 1MB - 4kB */ + wlan_partition: partition@1000 { + label = "wlan"; + reg=<0x001000 DT_SIZE_K(1020)>; + }; + + /* Partition 2: OTA 5MB */ + ota_partition: partition@100000 { + label = "ota"; + reg=<0x100000 DT_SIZE_M(5)>; + }; + + /* Partition 3: Provisioning KVStore 1MB */ + kvs_partition: partition@600000 { + label = "kvs"; + reg=<0x600000 DT_SIZE_M(1)>; + }; + + /* Partition 4: User data / OPTA PLC runtime 7MB (littlefs) */ + user_partition: partition@700000 { + label = "user"; + reg=<0x00000 DT_SIZE_M(7)>; + }; + }; + }; +}; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts index c3e45f6184e..7bedf04db4b 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts @@ -19,6 +19,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_uart; }; }; @@ -123,32 +124,84 @@ zephyr_udc0: &usbotg_fs { }; }; +/* Assign Bluetooth to M7 by default */ +&uart4 { + pinctrl-0 = < + &uart4_tx_pb9 + &uart4_rx_ph14 + &uart4_cts_pb15 + &uart4_rts_pa15 + >; + pinctrl-names = "default"; + current-speed = <115200>; + hw-flow-control; + status = "okay"; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + status = "okay"; + + murata-1dx { + compatible = "infineon,cyw43xxx-bt-hci"; + bt-reg-on-gpios = <&gpioj 12 GPIO_ACTIVE_HIGH>; + bt-host-wake-gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; + bt-dev-wake-gpios = <&gpioj 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Assign external flash to M7 by default */ &quadspi { - pinctrl-0 = < &quadspi_bk1_io0_pd11 - &quadspi_bk1_io1_pd12 - &quadspi_bk1_io2_pe2 - &quadspi_bk1_io3_pd13 - &quadspi_bk1_ncs_pg6 - &quadspi_clk_pb2 >; + pinctrl-0 = < + &quadspi_bk1_io0_pd11 + &quadspi_bk1_io1_pd12 + &quadspi_bk1_io2_pe2 + &quadspi_bk1_io3_pd13 + &quadspi_bk1_ncs_pg6 + &quadspi_clk_pb2 + >; pinctrl-names = "default"; status = "okay"; - at25sf128a: qspi-nor-flash@90000000 { + qspi_flash: qspi-nor-flash@0 { compatible = "st,stm32-qspi-nor"; - reg = < 0x90000000 DT_SIZE_M(16) >; /* 128 MBits */ - qspi-max-frequency = ; + reg = <0>; + size = ; /* 128 MBits */ + qspi-max-frequency = <80000000>; + jedec-id = [01 1f 89]; + spi-bus-width = <4>; + quad-enable-requirements = "NONE"; status = "okay"; - spi-bus-width = <2>; - st,read-id-dummy-cycles = <16>; + /* The following partitions are valid only if the Opta external flash + * has never been reformatted or repartitioned. Note the offset of the + * first partition, due to the presence of the MBR. + */ partitions { compatible = "fixed-partitions"; - #address-cells = < 1 >; - #size-cells = < 1 >; + #address-cells = <1>; + #size-cells = <1>; + + /* WiFi firmware and TLS certificates: 1MB - 4K for MBR using LBA */ + wlan_partition: partition@1000 { + label = "wlan"; + reg=<0x001000 DT_SIZE_K(1020)>; + }; + + /* Arduino OTA partition: 13MB */ + fs_partition: partition@100000 { + label = "fs"; + reg=<0x100000 DT_SIZE_M(13)>; + }; - storage_partition: partition@0 { - label = "storage"; - reg=< 0x0 DT_SIZE_K(15872) >; + /* The final 2MB is used to keep a memory-mapped copy of the WiFi + * firmware. The address of the firmware blob is 0xF80000 and the + * size of the partition in the MBR is 0 but, given that we can't + * specify a zero size in `reg` we just give the "correct" one. + */ + wifi_partition: partition@e00000 { + label = "4343WA1"; + reg=<0xE00000 DT_SIZE_M(2)>; }; }; }; diff --git a/boards/arduino/opta/board.h b/boards/arduino/opta/board.h new file mode 100644 index 00000000000..edab2a74f3f --- /dev/null +++ b/boards/arduino/opta/board.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 DNDG srl + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __ARDUINO_OPTA_BOARD_H +#define __ARDUINO_OPTA_BOARD_H + +#include + +#define OPTA_OTP_MAGIC 0xB5 + +#define OPTA_SERIAL_NUMBER_SIZE 24 + +struct __packed opta_board_info { + uint8_t magic; + uint8_t version; + union { + uint16_t board_functionalities; + struct { + uint8_t wifi: 1; + uint8_t rs485: 1; + uint8_t ethernet: 1; + } _board_functionalities_bits; + }; + uint16_t revision; + uint8_t external_flash_size; + uint16_t vid; + uint16_t pid; + uint8_t mac_address[6]; + uint8_t mac_address_wifi[6]; +}; + +const struct opta_board_info *const opta_get_board_info(void); + +const char *const opta_get_serial_number(void); + +#endif /* __ARDUINO_OPTA_BOARD_H */ diff --git a/boards/arduino/opta/board_gpio_init.c b/boards/arduino/opta/board_gpio_init.c index fcf8f6872a6..3bf276f761f 100644 --- a/boards/arduino/opta/board_gpio_init.c +++ b/boards/arduino/opta/board_gpio_init.c @@ -12,7 +12,7 @@ static int board_gpio_init(void) { /* The external oscillator that drives the HSE clock should be enabled * by setting the GPIOI1 pin. This function is registered at priority - * RE_KERNEL_1 to be executed before the standard STM clock + * PRE_KERNEL_1 to be executed before the standard STM clock * setup code. * * Note that the HSE should be turned on by the M7 only because M4 @@ -36,7 +36,13 @@ static int board_gpio_init(void) LL_GPIO_SetPinMode(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_MODE_OUTPUT); LL_GPIO_SetPinSpeed(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_SPEED_FREQ_LOW); LL_GPIO_SetPinOutputType(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_OUTPUT_PUSHPULL); - LL_GPIO_SetPinPull(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_PULL_UP); + LL_GPIO_SetPinPull(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_PULL_NO); + + /* No timer active yet, time a >200us pulse with CPU cycles */ + LL_GPIO_ResetOutputPin(GPIOJ, LL_GPIO_PIN_15); + for (int i = 0; i < 50000; i++) { + arch_nop(); + } LL_GPIO_SetOutputPin(GPIOJ, LL_GPIO_PIN_15); #endif diff --git a/boards/arduino/opta/board_info.c b/boards/arduino/opta/board_info.c new file mode 100644 index 00000000000..b4c42fc4c50 --- /dev/null +++ b/boards/arduino/opta/board_info.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2024 DNDG srl + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +#define AT25SF128_READ_SECURITY_REGISTERS 0x48 + +static struct opta_board_info info; +static char serial_number[OPTA_SERIAL_NUMBER_SIZE + 1]; + +#if defined(CONFIG_FLASH_STM32_QSPI_GENERIC_READ) + +const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(qspi_flash)); + +static int board_info(void) +{ + QSPI_CommandTypeDef cmd = { + .Instruction = AT25SF128_READ_SECURITY_REGISTERS, + .InstructionMode = QSPI_INSTRUCTION_1_LINE, + .Address = (1 << 13), + .AddressSize = QSPI_ADDRESS_24_BITS, + .AddressMode = QSPI_ADDRESS_1_LINE, + .AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE, + .DataMode = QSPI_DATA_1_LINE, + .NbData = sizeof(struct opta_board_info), + .DummyCycles = 8, + }; + + if (!device_is_ready(dev)) { + return -ENODEV; + } + + int ret = flash_ex_op(dev, FLASH_STM32_QSPI_EX_OP_GENERIC_READ, (uintptr_t)&cmd, &info); + + if (ret != 0) { + return -EIO; + } + + return 0; +} + +SYS_INIT(board_info, APPLICATION, 0); + +#endif /* CONFIG_FLASH_STM32_QSPI_GENERIC_READ */ + +static void uint32tohex(char *dst, uint32_t value) +{ + int v; + + for (int i = 0; i < 8; i++) { + v = (value >> ((8 - i - 1) * 4)) & 0x0F; + dst[i] = v <= 9 ? (0x30 + v) : (0x40 + v - 9); + } +} + +const struct opta_board_info *const opta_get_board_info(void) +{ + if (info.magic == OPTA_OTP_MAGIC) { + return &info; + } + return NULL; +} + +const char *const opta_get_serial_number(void) +{ + if (serial_number[0] == 0) { + uint32tohex(&serial_number[0], HAL_GetUIDw0()); + uint32tohex(&serial_number[8], HAL_GetUIDw1()); + uint32tohex(&serial_number[16], HAL_GetUIDw2()); + } + return serial_number; +} diff --git a/boards/arduino/opta/doc/index.rst b/boards/arduino/opta/doc/index.rst index 4b131659355..7f16e81c20f 100644 --- a/boards/arduino/opta/doc/index.rst +++ b/boards/arduino/opta/doc/index.rst @@ -80,6 +80,16 @@ as well as by the main PLL clock. By default, the CPU2 (Cortex-M4) System clock is driven at 240MHz. PLL clock is fed by a 25MHz high speed external clock. The M7 clock is driven at 400MHz. +External flash +============== + +External flash (16MB on QSPI) access can be enabled by the ``CONFIG_FLASH`` +option. The ``partitions`` entry provided in the default device tree is meant +as an example and is valid only if the Opta is fresh from the factory and the +flash has not been repartitioned. As a second example, the partitioning scheme +created by the new ``QSPIFormat.ino`` sketch from Arduino is available as a +DTSI in ``arduino_opta-external-flash-partitioning.dtsi``. + Resources sharing ================= diff --git a/boards/arduino/portenta_c33/CMakeLists.txt b/boards/arduino/portenta_c33/CMakeLists.txt new file mode 100644 index 00000000000..6605f129d20 --- /dev/null +++ b/boards/arduino/portenta_c33/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright 2025 Arduino SA +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_NETWORKING eth_clock.c) diff --git a/boards/arduino/portenta_c33/Kconfig.arduino_portenta_c33 b/boards/arduino/portenta_c33/Kconfig.arduino_portenta_c33 new file mode 100644 index 00000000000..1db7ac3de08 --- /dev/null +++ b/boards/arduino/portenta_c33/Kconfig.arduino_portenta_c33 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Arduino SA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_PORTENTA_C33 + select SOC_R7FA6M5BH3CFC diff --git a/boards/arduino/portenta_c33/Kconfig.defconfig b/boards/arduino/portenta_c33/Kconfig.defconfig new file mode 100644 index 00000000000..50e51f32a25 --- /dev/null +++ b/boards/arduino/portenta_c33/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arduino SA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_PORTENTA_C33 + +config USE_DT_CODE_PARTITION + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config WIFI_ESP_HOSTED + default y + +endif # NETWORKING + +endif # BOARD_ARDUINO_PORTENTA_C33 diff --git a/boards/arduino/portenta_c33/arduino_mkr_connector.dtsi b/boards/arduino/portenta_c33/arduino_mkr_connector.dtsi new file mode 100644 index 00000000000..86698259c56 --- /dev/null +++ b/boards/arduino/portenta_c33/arduino_mkr_connector.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2025 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + arduino_mkr_header: connector { + compatible = "arduino-mkr-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , /* D0 */ + , /* D1 */ + , /* D2 */ + , /* D3 */ + , /* D4 */ + , /* D5 */ + , /* D6 */ + , /* D7 */ + , /* D8 / SPI_COPI */ + , /* D9 / SPI_SCK */ + , /* D10 / SPI_CIPO */ + , /* D11 / I2C_SDA */ + , /* D12 / I2C_SCL */ + , /* D13 / UART_RX */ + , /* D14 / UART_TX */ + , /* D15 / A0 */ + , /* D16 / A1 */ + , /* D17 / A2 */ + , /* D18 / A3 */ + , /* D19 / A4 */ + , /* D20 / A5 */ + ; /* D21 / A6 */ + }; +}; + +arduino_mkr_i2c: &iic0 {}; +arduino_mkr_serial: &uart9 {}; + +/* + * TODO: enable when SCI as SPI is supported + * arduino_mkr_spi: &sci4 {}; + */ diff --git a/boards/arduino/portenta_c33/arduino_portenta_c33-pinctrl.dtsi b/boards/arduino/portenta_c33/arduino_portenta_c33-pinctrl.dtsi new file mode 100644 index 00000000000..ad9a1d7e294 --- /dev/null +++ b/boards/arduino/portenta_c33/arduino_portenta_c33-pinctrl.dtsi @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2024 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci7_default: sci7_default { + group1 { + /* tx rx */ + psels = , + , + , + ; + }; + }; + + sci9_default: sci9_default { + group1 { + /* tx rx */ + psels = , + , + , + ; + }; + }; + + sci5_default: sci5_default { + group1 { + /* tx rx */ + psels = , + , + , + ; + }; + }; + + sci6_default: sci6_default { + group1 { + /* tx rx */ + psels = , + , + , + ; + }; + }; + + sci8_default: sci8_default { + group1 { + /* tx rx rts cts - BLE */ + psels = , + , + , + ; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + iic0_default: iic0_default { + group1 { + /* SCL SDA */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi1_default: spi1_default { + group1 { + /* MISO MOSI RSPCK SSL0 SSL1 */ + psels = , + , + , + , + ; + }; + }; + + usbhs_default: usbhs_default { + group1 { + psels = ; /* USBHS-VBUS */ + drive-strength = "high"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = , + , + , + , + , + , + , + ; + renesas,analog-enable; + }; + }; + + ether_default: ether_default { + group1 { + psels = , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* RMII0_TXD_EN_B */ + , /* RMII0_TXD1_BR */ + , /* RMII0_TXD0_B */ + , /* REF50CK0_B */ + , /* RMII0_RXD0_B */ + , /* RMII0_RXD1_B */ + , /* RMII0_RX_ER_B */ + ; /* RMII0_CRS_DV_B */ + drive-strength = "high"; + }; + }; + + pwm1_default: pwm1_default { + group1 { + psels = ; + }; + }; + + pwm3_default: pwm3_default { + group1 { + psels = ; + }; + }; + + pwm4_default: pwm4_default { + group1 { + psels = ; + }; + }; + + pwm6_default: pwm6_default { + group1 { + psels = , + ; + }; + }; + + pwm7_default: pwm7_default { + group1 { + psels = ; + }; + }; + + pwm8_default: pwm8_default { + group1 { + psels = , + ; + }; + }; +}; diff --git a/boards/arduino/portenta_c33/arduino_portenta_c33.dts b/boards/arduino/portenta_c33/arduino_portenta_c33.dts new file mode 100644 index 00000000000..b4f535267e6 --- /dev/null +++ b/boards/arduino/portenta_c33/arduino_portenta_c33.dts @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2025 Arduino SA + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "arduino_portenta_c33-pinctrl.dtsi" + +/ { + model = "Arduino Portenta C33"; + compatible = "renesas,ra6m5", "renesas,ra"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; + zephyr,code-partition = &code_partition; + zephyr,flash = &flash0; + zephyr,console = &uart9; + zephyr,shell-uart = &uart9; + zephyr,entropy = &trng; + zephyr,bt-hci = &bt_hci_uart; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioport1 7 GPIO_ACTIVE_LOW>; + label = "LEDR"; + }; + + led2: led2 { + gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>; + label = "LEDG"; + }; + + led3: led3 { + gpios = <&ioport8 0 GPIO_ACTIVE_HIGH>; + label = "LEDB"; + }; + }; + + download-esp32 { + compatible = "regulator-fixed"; + regulator-name = "download_esp32"; + enable-gpios = <&ioport8 3 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + aliases { + led0 = &led1; + }; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + + uart9: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&sci8 { + pinctrl-0 = <&sci8_default>; + pinctrl-names = "default"; + status = "okay"; + + uart8: uart { + current-speed = <921600>; + status = "okay"; + hw-flow-control; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + status = "okay"; + + esp32 { + compatible = "renesas,bt-hci-da1453x"; + status = "okay"; + reset-gpios = <&ioport8 4 GPIO_ACTIVE_LOW>; + reset-assert-duration-ms = <100>; + boot-duration-ms = <2000>; + }; + }; + }; +}; + +&option_setting_ofs0 { + status = "disabled"; +}; + +&option_setting_dualsel { + status = "disabled"; +}; + +&option_setting_ofs1_sec { + status = "disabled"; +}; + +&option_setting_banksel_sec { + status = "disabled"; +}; + +&option_setting_bps_sec { + status = "disabled"; +}; + +&option_setting_pbps_sec { + status = "disabled"; +}; + +&option_setting_ofs1_sel { + status = "disabled"; +}; + +&option_setting_banksel_sel { + status = "disabled"; +}; + +&option_setting_bps_sel { + status = "disabled"; +}; + +&iic0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <87 1>, <88 1>, <89 1>, <90 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; +}; + +&iic1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <91 1>, <92 1>, <93 1>, <94 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + clock-frequency = ; + cs-gpios = <&ioport1 3 GPIO_ACTIVE_LOW>, + <&ioport1 4 GPIO_ACTIVE_LOW>; + + esp_hosted@1 { + status = "ok"; + compatible = "espressif,esp-hosted"; + reg = <0x1>; + spi-max-frequency = ; + reset-gpios = <&ioport8 4 GPIO_ACTIVE_HIGH>; + handshake-gpios = <&ioport8 6 GPIO_ACTIVE_HIGH>; + dataready-gpios = <&ioport8 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&ioport5 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&ioport7 { + status = "okay"; +}; + +&ioport8 { + status = "okay"; +}; + +&ioport9 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&ioportb { + status = "okay"; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + clocks = <&xtal>; + div = <3>; + mul = <25 0>; + status = "okay"; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + status = "okay"; + + zephyr_udc0: udc { + status = "okay"; + + board_cdc_acm_uart: board_cdc_acm_uart { + compatible = "zephyr,cdc-acm-uart"; + }; + }; +}; + +&usbhs_phy { + phys-clock-src = "xtal"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq9 { + interrupts = <41 12>; + status = "okay"; +}; + +&port_irq10 { + interrupts = <42 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + read-only; + }; + + code_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 (DT_SIZE_M(2) - DT_SIZE_K(64))>; + }; + }; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; + +&trng { + status = "okay"; +}; + +ð { + local-mac-address = [74 90 50 B0 5D E9]; + status = "okay"; + phy-handle = <&phy>; +}; + +&mdio { + pinctrl-0 = <ðer_default>; + pinctrl-names = "default"; + status = "okay"; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + reg = <0>; + status = "okay"; + }; +}; + +&pwm6 { + pinctrl-0 = <&pwm6_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; + + eth_clock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + clock-frequency = ; + #clock-cells = <1>; + pwms = <&pwm6 1 PWM_KHZ(25000) PWM_POLARITY_NORMAL>; + }; +}; + +#include "arduino_mkr_connector.dtsi" diff --git a/boards/arduino/portenta_c33/arduino_portenta_c33.yaml b/boards/arduino/portenta_c33/arduino_portenta_c33.yaml new file mode 100644 index 00000000000..7d3e1f4c567 --- /dev/null +++ b/boards/arduino/portenta_c33/arduino_portenta_c33.yaml @@ -0,0 +1,19 @@ +identifier: arduino_portenta_c33 +name: Arduino Portenta C33 +type: mcu +arch: arm +ram: 512 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - i2c + - net + - pwm + - spi + - uart + - wifi +# - usb_device (requires USB_DEVICE_STACK_NEXT) +vendor: arduino diff --git a/boards/arduino/portenta_c33/arduino_portenta_c33_defconfig b/boards/arduino/portenta_c33/arduino_portenta_c33_defconfig new file mode 100644 index 00000000000..b186cf9aadb --- /dev/null +++ b/boards/arduino/portenta_c33/arduino_portenta_c33_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Arduino SA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y + +CONFIG_BUILD_OUTPUT_BIN=y + +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +CONFIG_DYNAMIC_INTERRUPTS=y + +CONFIG_REGULATOR=y diff --git a/boards/arduino/portenta_c33/board.cmake b/boards/arduino/portenta_c33/board.cmake new file mode 100644 index 00000000000..cd9010a56d6 --- /dev/null +++ b/boards/arduino/portenta_c33/board.cmake @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Arduino SA +# SPDX-License-Identifier: Apache-2.0 + + +# FIXME: Arduino dfu-util provides -Q to reset the board after flashing +board_runner_args(dfu-util "--pid=2341:0368" "--alt=0") +board_runner_args(jlink "--device=R7FA6M5BH" "--speed=4000") +board_runner_args(pyocd "--target=r7fa6m5bh" "--frequency=4000000") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arduino/portenta_c33/board.yml b/boards/arduino/portenta_c33/board.yml new file mode 100644 index 00000000000..111e046ca64 --- /dev/null +++ b/boards/arduino/portenta_c33/board.yml @@ -0,0 +1,6 @@ +board: + name: arduino_portenta_c33 + full_name: Arduino Portenta C33 + vendor: arduino + socs: + - name: r7fa6m5bh3cfc diff --git a/boards/arduino/portenta_c33/doc/img/portenta_c33.webp b/boards/arduino/portenta_c33/doc/img/portenta_c33.webp new file mode 100644 index 00000000000..4a15d9c6bbd Binary files /dev/null and b/boards/arduino/portenta_c33/doc/img/portenta_c33.webp differ diff --git a/boards/arduino/portenta_c33/doc/index.rst b/boards/arduino/portenta_c33/doc/index.rst new file mode 100644 index 00000000000..5800eca0a3e --- /dev/null +++ b/boards/arduino/portenta_c33/doc/index.rst @@ -0,0 +1,129 @@ +.. zephyr:board:: arduino_portenta_c33 + +Overview +******** + +The Portenta C33 is a powerful System-on-Module based on the Renesas RA6M5 +microcontroller group, which utilizes the high-performance Arm® Cortex®-M33 +core. The Portenta C33 shares the same form factor as the Portenta H7 and is +backward compatible with it, making it fully compatible with all Portenta +family shields and carriers through its High-Density connectors. + +Hardware +******** + +- Renesas RA6M5 ARM Cortex-M33 processor at 200 MHz +- 24 MHz crystal oscillator +- 32.768 kHz crystal oscillator for RTC +- 2 MB flash memory and 512 KiB of RAM +- 16 MB external QSPI flash +- One RGB user LED +- One reset button +- NXP SE050 secure element +- Onboard 10/100 Ethernet PHY +- WiFi + Bluetooth via ESP32-C3 running `esp-hosted`_ firmware +- Battery charger +- MKR header connector exposing standard peripherals (UART, SPI, I2C, ADC, PWM) +- 160 pins high density Portenta connectors exposing SD, CAN, I2S, SWD interfaces + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The `Arduino store`_ has detailed information about board connections. Download +the `Arduino Portenta C33 Schematic`_ for more details. + +Serial Port +=========== + +The Portenta C33 exposes 4 serial ports with hardware flow control. + +PWM +=== + +The Portenta C33 exposes 10 dedicated independent PWM pins. + +USB Device Port +=============== + +The RA6M5 MCU has an high speed USB device port that can be used to communicate +with a host PC. See the :zephyr:code-sample-category:`usb` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. +A second full speed USB interface is exposed on the high density connectors. + +DAC +=== + +The RA6M5 MCU has two DACs with 12 bits of resolution. On the +Arduino Portenta C33, the DACs are available on pins A5 and A6. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The Arduino Portenta C33 ships with a DFU compatible bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_portenta_c33 + :goals: build + :compact: + +#. Connect the Portenta C33 to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_portenta_c33 + :goals: flash + :compact: + + You should see "Hello World! arduino_portenta_c33" in your terminal. + +References +********** + +.. target-notes:: + +.. _Arduino Store: + https://store.arduino.cc/products/portenta-c33 + +.. _Arduino Portenta C33 Schematic: + http://docs.arduino.cc/resources/schematics/ABX00074-schematics.pdf + +.. _esp-hosted: + https://github.com/espressif/esp-hosted diff --git a/boards/arduino/portenta_c33/eth_clock.c b/boards/arduino/portenta_c33/eth_clock.c new file mode 100644 index 00000000000..d8449c645cb --- /dev/null +++ b/boards/arduino/portenta_c33/eth_clock.c @@ -0,0 +1,35 @@ +/* + * Copyright 2025 Arduino SA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(eth_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL); + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(eth)) +static int eth_clock_enable(void) +{ + int ret; + const struct device *eth_clk_dev = DEVICE_DT_GET(DT_NODELABEL(eth_clock)); + + if (!device_is_ready(eth_clk_dev)) { + LOG_ERR("Invalid eth_clock device"); + return -ENODEV; + } + + ret = clock_control_on(eth_clk_dev, (clock_control_subsys_t)0); + if (ret < 0) { + LOG_ERR("Failed to enable Ethernet clock, error %d", ret); + return ret; + } + + return 0; +} + +SYS_INIT(eth_clock_enable, POST_KERNEL, CONFIG_CLOCK_CONTROL_PWM_INIT_PRIORITY); +#endif diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi index d7489b77d26..a9931c1787b 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi +++ b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi @@ -30,6 +30,7 @@ led0 = &red_led; led1 = &green_led; led2 = &blue_led; + sdhc0 = &sdhc; }; }; @@ -83,7 +84,7 @@ }; /* I2C1 in datasheet */ -&i2c1 { +zephyr_i2c: &i2c1 { pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; pinctrl-names = "default"; clock-frequency = ; @@ -179,9 +180,10 @@ pinctrl-names = "default"; status = "okay"; - mx25l12833f: qspi-nor-flash@90000000 { + mx25l12833f: qspi-nor-flash@0 { compatible = "st,stm32-qspi-nor"; - reg = < 0x90000000 DT_SIZE_M(16) >; /* 128 MBits */ + reg = <0>; + size = ; /* 128 Mbits */ qspi-max-frequency = < 40000000 >; sfdp-bfp = [ e5 20 f1 ff ff ff ff 07 44 eb 08 6b 08 3b 04 bb fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 @@ -238,6 +240,29 @@ }; }; +sdhc: &sdmmc1 { + compatible = "st,stm32-sdio"; + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + pinctrl-names = "default"; + sdhi-on-gpios = <&gpioj 1 GPIO_ACTIVE_HIGH>; + interrupts = <49 0>; + interrupt-names = "event"; + min-bus-freq = ; + max-bus-freq = ; + hw-flow-control; + bus-width = <4>; + status = "okay"; + + wifi: airoc-wifi { + status = "okay"; + compatible = "infineon,airoc-wifi"; + wifi-reg-on-gpios = <&gpioj 1 GPIO_ACTIVE_HIGH>; + wifi-host-wake-gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; + }; +}; + zephyr_udc0: &usbotg_hs { pinctrl-0 = < &usb_otg_hs_ulpi_d0_pa3 &usb_otg_hs_ulpi_ck_pa5 diff --git a/boards/arduino/uno_r4/arduino_uno_r4.dts b/boards/arduino/uno_r4/arduino_uno_r4.dts index 09ce3664f1d..5551829a9b7 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4.dts +++ b/boards/arduino/uno_r4/arduino_uno_r4.dts @@ -38,10 +38,19 @@ }; }; + +&ioport0 { + status = "okay"; +}; + &ioport1 { status = "okay"; }; +&ioport3 { + status = "okay"; +}; + &adc0 { status = "okay"; pinctrl-0 = <&adc0_default>; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay b/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay index f411487d080..8a6f987824b 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay @@ -94,6 +94,10 @@ }; }; +&ioport4 { + status = "okay"; +}; + &spi0 { pinctrl-0 = <&spi0_default>; pinctrl-names = "default"; @@ -113,6 +117,6 @@ status = "okay"; }; -qwiic_i2c: &iic0 {}; +zephyr_i2c: &iic0 {}; arduino_i2c: &iic1 {}; arduino_spi: &spi0 {}; diff --git a/boards/arm/mps4/Kconfig.defconfig b/boards/arm/mps4/Kconfig.defconfig new file mode 100644 index 00000000000..96cbd9472ea --- /dev/null +++ b/boards/arm/mps4/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE320_FVP + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +if ROMSTART_RELOCATION_ROM && (BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE320_FVP) + +config ROMSTART_REGION_ADDRESS + default $(dt_nodelabel_reg_addr_hex,itcm) + +config ROMSTART_REGION_SIZE + default $(dt_nodelabel_reg_size_hex,itcm,0,k) + +endif + +endif diff --git a/boards/arm/mps4/Kconfig.mps4 b/boards/arm/mps4/Kconfig.mps4 new file mode 100644 index 00000000000..46ce14cc062 --- /dev/null +++ b/boards/arm/mps4/Kconfig.mps4 @@ -0,0 +1,7 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS4 + select SOC_SERIES_MPS4 + select SOC_MPS4_CORSTONE315 if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE315_FVP_NS + select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS diff --git a/boards/arm/mps4/board.cmake b/boards/arm/mps4/board.cmake new file mode 100644 index 00000000000..4e5044ab1b7 --- /dev/null +++ b/boards/arm/mps4/board.cmake @@ -0,0 +1,49 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +# +# Default emulation: +# FVP is used by default for corstone320/fvp. +# + + +if(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE315_FVP_NS) + set(SUPPORTED_EMU_PLATFORMS armfvp) + set(ARMFVP_BIN_NAME FVP_Corstone_SSE-315) +elseif(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS) + set(SUPPORTED_EMU_PLATFORMS armfvp) + set(ARMFVP_BIN_NAME FVP_Corstone_SSE-320) +endif() + +if(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP) + set(ARMFVP_FLAGS + # default is '0x11000000' but should match cpu.INITSVTOR which is 0. + -C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0 + # default is 0x8, this change is needed since we split flash into itcm + # and sram and it reduces the number of available mpu regions causing a + # few MPU tests to fail. + -C mps4_board.subsystem.cpu0.MPU_S=16 + ) +endif() + +if(CONFIG_BUILD_WITH_TFM) + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex) +endif() + +# FVP Parameters +# -C indicate a config option in the form of: +# instance.parameter=value +# Run the FVP with --list-params to list all options +set(ARMFVP_FLAGS ${ARMFVP_FLAGS} + -C mps4_board.uart0.out_file=- + -C mps4_board.uart0.unbuffered_output=1 + -C mps4_board.uart1.out_file=- + -C mps4_board.uart1.unbuffered_output=1 + -C mps4_board.uart2.out_file=- + -C mps4_board.uart2.unbuffered_output=1 + -C mps4_board.visualisation.disable-visualisation=1 + -C mps4_board.telnetterminal0.start_telnet=0 + -C mps4_board.telnetterminal1.start_telnet=0 + -C mps4_board.telnetterminal2.start_telnet=0 + -C vis_hdlcd.disable_visualisation=1 + ) diff --git a/boards/arm/mps4/board.yml b/boards/arm/mps4/board.yml new file mode 100644 index 00000000000..760321039f6 --- /dev/null +++ b/boards/arm/mps4/board.yml @@ -0,0 +1,15 @@ +board: + name: mps4 + full_name: MPS4 + vendor: arm + socs: + - name: 'corstone315' + variants: + - name: 'fvp' + variants: + - name: 'ns' + - name: 'corstone320' + variants: + - name: 'fvp' + variants: + - name: 'ns' diff --git a/boards/arm/mps4/doc/index.rst b/boards/arm/mps4/doc/index.rst new file mode 100644 index 00000000000..20bbd63d9c2 --- /dev/null +++ b/boards/arm/mps4/doc/index.rst @@ -0,0 +1,189 @@ +.. zephyr:board:: mps4 + +Overview +******** + +The MPS4 board configuration is used by Zephyr applications that run +on the MPS4 board. + +`Corstone-315 FVP`_/`Corstone-320 FVP`_ are Arm reference subsystem for +secure System on Chips containing an Armv8.1-M Cortex-M85 processor, +LCM, KMU and SAM IPs. Corstone-320 FVP have Ethos-U85 while +Corstone-315 FVP have a Ethos-U65 neural network processor. +They are available free of charge for Linux and Windows systems. +The FVPs have been selected for simulation since they provide access to the +Ethos-U65/Ethos-U85 NPU, which is unavailable in QEMU or other simulation platforms. + + +Zephyr board options +==================== + +.. tabs:: + + .. tab:: MPS4 Corstone-315 (FVP) + + The MPS4 FVP is an SoC with Cortex-M85 architecture. Zephyr provides support + for building for both Secure and Non-Secure firmware. + + The BOARD options are summarized below: + + +-------------------------------+-----------------------------------------------+ + | BOARD | Description | + +===============================+===============================================+ + | ``mps4/corstone315/fvp`` | For building Secure (or Secure-only) firmware | + +-------------------------------+-----------------------------------------------+ + | ``mps4/corstone315/fvp/ns`` | For building Non-Secure firmware | + +-------------------------------+-----------------------------------------------+ + + FPGA Usage: + - N/A. + + FVP Usage: + - To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before using it. Then you can run it with ``west build -t run``. + + .. code-block:: bash + + export ARMFVP_BIN_PATH=/path/to/fvp/directory + west build -b {BOARD qualifier from table above} samples/hello_world -t run + + To run the Fixed Virtual Platform simulation tool you must download "FVP model + for the Corstone-315 MPS4" from Arm and install it on your host PC. + + QEMU Usage: + - N/A. + + .. tab:: MPS4 Corstone-320 (FVP) + + The MPS4 FVP is an SoC with Cortex-M85 architecture. Zephyr provides support + for building for both Secure and Non-Secure firmware. + + The BOARD options are summarized below: + + +-------------------------------+-----------------------------------------------+ + | BOARD | Description | + +===============================+===============================================+ + | ``mps4/corstone320/fvp`` | For building Secure (or Secure-only) firmware | + +-------------------------------+-----------------------------------------------+ + | ``mps4/corstone320/fvp/ns`` | For building Non-Secure firmware | + +-------------------------------+-----------------------------------------------+ + + FPGA Usage: + - N/A. + + FVP Usage: + - To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before using it. Then you can run it with ``west build -t run``. + + .. code-block:: bash + + export ARMFVP_BIN_PATH=/path/to/fvp/directory + west build -b {BOARD qualifier from table above} samples/hello_world -t run + + To run the Fixed Virtual Platform simulation tool you must download "FVP model + for the Corstone-320 MPS4" from Arm and install it on your host PC. This board + has been tested with version 11.27.25 (Sep 24 2024). + + QEMU Usage: + - N/A. + +.. note:: + + - Board qualifier must include the variant name as mentioned above. + ``mps4/corstone315``/ ``mps4/corstone320`` without the variant name is not a valid qualifier. + - ``mps4/corstone315/fvp/ns``/ ``mps4/corstone320/fvp/ns`` variant needs latest upstream TF-M release since Zephyr's current + TF-M doesn't support Corstone-315 FVP yet. + +Hardware +******** + +No H/W available yet, only ARMFVP simulated board variants are supported for now. + +Supported Features +=================== + +.. zephyr:board-supported-hw:: + +Serial Port +=========== + +The MPS4 has six UARTs. The Zephyr console output by default, uses +UART0. + +Serial port 0 on the Debug USB interface is the MCC board control console. + +Serial port 1 on the Debug USB interface is connected to UART 0. + +Serial port 2 on the Debug USB interface is connected to UART 1. + +Serial port 3 on the Debug USB interface is connected to UART 2. + +.. Programming and Debugging: + +Programming and Debugging +************************* + +Flashing +======== + +- N/A since the only support available is FVP. + +Building an application with Corstone-315 +----------------------------------------- + +You can build applications in the usual way. Here is an example for +the :zephyr:code-sample:`hello_world` application with Corstone-315. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mps4/corstone315/fvp + :goals: run + +Run with FVP and you should see the following message: + +.. code-block:: console + + Hello World! mps4 + +Building an application with Corstone-320 +----------------------------------------- + +You can build applications in the usual way. Here is an example for +the :zephyr:code-sample:`hello_world` application with Corstone-320. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mps4/corstone320/fvp + :goals: run + +Run with FVP and you should see the following message: + +.. code-block:: console + + Hello World! mps4 + +For more details refer to: + - `Corstone SSE-315 Reference Guide`_ + - `Corstone SSE-320 Reference Guide`_ + - `Cortex M85 Generic User Guide`_ + - `Arm Corstone-320 Reference Package Technical Overview`_ + - `Arm MPS4 FPGA Prototyping Board Technical Reference Manual`_ + +.. _Corstone-315 FVP: + https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps + +.. _Corstone-320 FVP: + https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps + +.. _Corstone SSE-315 Reference Guide: + https://developer.arm.com/documentation/109395/0000 + +.. _Corstone SSE-320 Reference Guide: + https://developer.arm.com/documentation/109760/0000/ + +.. _Cortex M85 Generic User Guide: + https://developer.arm.com/documentation/101924/latest + +.. _Arm Corstone-320 Reference Package Technical Overview: + https://developer.arm.com/documentation/109761/0000/ + +.. _Arm MPS4 FPGA Prototyping Board Technical Reference Manual: + https://developer.arm.com/documentation/102577/0000/ diff --git a/boards/arm/mps4/mps4-pinctrl.dtsi b/boards/arm/mps4/mps4-pinctrl.dtsi new file mode 100644 index 00000000000..e8b7e720703 --- /dev/null +++ b/boards/arm/mps4/mps4-pinctrl.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /omit-if-no-ref/ uart3_default: uart3_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ uart4_default: uart4_default { + group1 { + pinmux = ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ spi3_default: spi3_default { + group1 { + pinmux = , , + ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ spi4_default: spi4_default { + group1 { + pinmux = , , ; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; + + /omit-if-no-ref/ sbcon2_default: sbcon2_default { + group1 { + pinmux = , ; + input-enable; + }; + }; + + /omit-if-no-ref/ sbcon3_default: sbcon3_default { + group1 { + pinmux = , ; + input-enable; + }; + }; +}; diff --git a/boards/arm/mps4/mps4_common.dtsi b/boards/arm/mps4/mps4_common.dtsi new file mode 100644 index 00000000000..ad97dae06af --- /dev/null +++ b/boards/arm/mps4/mps4_common.dtsi @@ -0,0 +1,121 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* /dts-v1/; */ + +#include +#include +#include +#include +#include + +/ { + aliases { + led0 = &led_0; + led1 = &led_1; + sw0 = &user_button_0; + sw1 = &user_button_1; + }; + + leds { + compatible = "gpio-leds"; + + led_0: led_0 { + gpios = <&gpio_led0 0>; + label = "USERLED0"; + }; + + led_1: led_1 { + gpios = <&gpio_led0 1>; + label = "USERLED1"; + }; + + led_2: led_2 { + gpios = <&gpio_led0 2>; + label = "USERLED2"; + }; + + led_3: led_3 { + gpios = <&gpio_led0 3>; + label = "USERLED3"; + }; + + led_4: led_4 { + gpios = <&gpio_led0 4>; + label = "USERLED4"; + }; + + led_5: led_5 { + gpios = <&gpio_led0 5>; + label = "USERLED5"; + }; + + led_6: led_6 { + gpios = <&gpio_led0 6>; + label = "USERLED6"; + }; + + led_7: led_7 { + gpios = <&gpio_led0 7>; + label = "USERLED7"; + }; + + led_8: led_8 { + gpios = <&gpio_led0 8>; + label = "PB1LED"; + }; + + led_9: led_9 { + gpios = <&gpio_led0 9>; + label = "PB2LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_0: button_0 { + label = "USERPB0"; + gpios = <&gpio_button 0>; + zephyr,code = ; + }; + + user_button_1: button_1 { + label = "USERPB1"; + gpios = <&gpio_button 1>; + zephyr,code = ; + }; + }; + + null_ptr_detect: null_ptr_detect@0 { + compatible = "zephyr,memory-region"; + /* 0 - CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE> */ + reg = <0x0 0x400>; + zephyr,memory-region = "NULL_PTR_DETECT"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>; + }; + + /* DDR4 - 2G, alternates non-secure/secure every 256M */ + ddr4: memory@60000000 { + device_type = "memory"; + compatible = "zephyr,memory-region"; + reg = <0x60000000 DT_SIZE_M(256) + 0x70000000 DT_SIZE_M(256) + 0x80000000 DT_SIZE_M(256) + 0x90000000 DT_SIZE_M(256) + 0xa0000000 DT_SIZE_M(256) + 0xb0000000 DT_SIZE_M(256) + 0xc0000000 DT_SIZE_M(256) + 0xd0000000 DT_SIZE_M(256)>; + zephyr,memory-region = "DDR4"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; + +#include "mps4-pinctrl.dtsi" diff --git a/boards/arm/mps4/mps4_common_soc_peripheral.dtsi b/boards/arm/mps4/mps4_common_soc_peripheral.dtsi new file mode 100644 index 00000000000..6cc3f405ea7 --- /dev/null +++ b/boards/arm/mps4/mps4_common_soc_peripheral.dtsi @@ -0,0 +1,218 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; +}; + +gpio0: gpio@100000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x100000 0x1000>; + interrupts = <69 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio1: gpio@101000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x101000 0x1000>; + interrupts = <70 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio2: gpio@102000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x102000 0x1000>; + interrupts = <71 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio3: gpio@103000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x103000 0x1000>; + interrupts = <72 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +eth0: eth@400000 { + /* Linux has "smsc,lan9115" */ + compatible = "smsc,lan9220"; + /* Actual reg range is ~0x200 */ + reg = <0x400000 0x100000>; + interrupts = <49 3>; +}; + +i2c_touch: i2c@8100000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8100000 0x1000>; +}; + +i2c_audio_conf: i2c@8101000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8101000 0x1000>; +}; + +spi_adc: spi@8102000 { + compatible = "arm,pl022"; + reg = <0x8102000 DT_SIZE_K(4)>; + interrupts = <53 3>; + interrupt-names = "shield_adc"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; +}; + +spi_shield0: spi@8103000 { + compatible = "arm,pl022"; + reg = <0x8103000 DT_SIZE_K(4)>; + interrupts = <54 3>; + interrupt-names = "shield0_spi"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi3_default>; + pinctrl-names = "default"; +}; + +spi_shield1: spi@8104000 { + compatible = "arm,pl022"; + reg = <0x8104000 DT_SIZE_K(4)>; + interrupts = <55 3>; + interrupt-names = "shield1_spi"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi4_default>; + pinctrl-names = "default"; +}; + +i2c_shield0: i2c@8105000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8105000 0x1000>; + pinctrl-0 = <&sbcon2_default>; + pinctrl-names = "default"; +}; + +i2c_shield1: i2c@8106000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8106000 0x1000>; + pinctrl-0 = <&sbcon3_default>; + pinctrl-names = "default"; +}; + +i2c_ddr4_eeprom: i2c@8108000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8108000 0x1000>; +}; + +gpio_led0: mps4_fpgaio@8202000 { + compatible = "arm,mmio32-gpio"; + reg = <0x8202000 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <8>; +}; + +gpio_button: mps4_fpgaio@8202008 { + compatible = "arm,mmio32-gpio"; + reg = <0x8202008 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <2>; + direction-input; +}; + +gpio_misc: mps4_fpgaio@820204c { + compatible = "arm,mmio32-gpio"; + reg = <0x820204c 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <3>; +}; + +uart0: uart@8203000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8203000 0x1000>; + interrupts = <34 3 33 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart1: uart@8204000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8204000 0x1000>; + interrupts = <36 3 35 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart2: uart@8205000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8205000 0x1000>; + interrupts = <38 3 37 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart3: uart@8206000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8206000 0x1000>; + interrupts = <40 3 39 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; + pinctrl-0 = <&uart3_default>; + pinctrl-names = "default"; +}; + +uart4: uart@8207000 { + compatible = "arm,cmsdk-uart"; + reg = <0x8207000 0x1000>; + interrupts = <42 3 41 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +uart5: uart@8208000 { + compatible = "arm,cmsdk-uart"; + status = "disabled"; + reg = <0x8208000 0x1000>; + interrupt-names = "tx", "rx"; + interrupts = <126 3 125 3>; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +pinctrl: pinctrl { + compatible = "arm,mps4-pinctrl"; + status = "okay"; +}; diff --git a/boards/arm/mps4/mps4_corstone315_fvp.dts b/boards/arm/mps4/mps4_corstone315_fvp.dts new file mode 100644 index 00000000000..98c87ce7ed7 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp.dts @@ -0,0 +1,97 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps4-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram; + zephyr,flash = &isram; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@50004000 { + compatible = "arm,ethos-u"; + reg = <0x50004000>; + interrupts = <16 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@12000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x12000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(32)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 { /* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps4_common_soc_peripheral.dtsi" + }; + }; +}; + +#include "mps4_common.dtsi" diff --git a/boards/arm/mps4/mps4_corstone315_fvp.yaml b/boards/arm/mps4/mps4_corstone315_fvp.yaml new file mode 100644 index 00000000000..4af1421bcbc --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp.yaml @@ -0,0 +1,26 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps4/corstone315/fvp +name: Arm MPS4-Corstone315-FVP +type: mcu +arch: arm +ram: 2048 +flash: 4096 +simulation: + - name: armfvp + exec: FVP_Corstone_SSE-315 +toolchain: + - gnuarmemb + - zephyr +supported: + - gpio +testing: + default: true + timeout_multiplier: 4 + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps4/mps4_corstone315_fvp_defconfig b/boards/arm/mps4/mps4_corstone315_fvp_defconfig new file mode 100644 index 00000000000..26d5a732e49 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp_defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y +# ROMSTART_REGION address and size are defined in Kconfig.defconfig +CONFIG_ROMSTART_RELOCATION_ROM=y diff --git a/boards/arm/mps4/mps4_corstone315_fvp_ns.dts b/boards/arm/mps4/mps4_corstone315_fvp_ns.dts new file mode 100644 index 00000000000..cb5a38baf47 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp_ns.dts @@ -0,0 +1,102 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps4-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the non-secure addresses, if you add 0x10000000 + * you'll get the secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/HEAD/platform/ext/target/arm/mps4/common/partition/flash_layout.h + */ + + code: memory@28080000 { + reg = <0x28080000 DT_SIZE_K(512)>; + }; + + ram: memory@21020000 { + reg = <0x21020000 DT_SIZE_M(1)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps4_common_soc_peripheral.dtsi" + }; + }; +}; + +#include "mps4_common.dtsi" diff --git a/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml b/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml new file mode 100644 index 00000000000..01bee24100a --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml @@ -0,0 +1,15 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps4/corstone315/fvp/ns +name: Arm MPS4-Corstone315-FVP_ns +type: mcu +arch: arm +ram: 1024 +flash: 512 +toolchain: + - gnuarmemb + - zephyr +testing: + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps4/mps4_corstone315_fvp_ns_defconfig b/boards/arm/mps4/mps4_corstone315_fvp_ns_defconfig new file mode 100644 index 00000000000..d59d419011b --- /dev/null +++ b/boards/arm/mps4/mps4_corstone315_fvp_ns_defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y +CONFIG_BUILD_WITH_TFM=y diff --git a/boards/arm/mps4/mps4_corstone320_fvp.dts b/boards/arm/mps4/mps4_corstone320_fvp.dts new file mode 100644 index 00000000000..98c87ce7ed7 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp.dts @@ -0,0 +1,97 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps4-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram; + zephyr,flash = &isram; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@50004000 { + compatible = "arm,ethos-u"; + reg = <0x50004000>; + interrupts = <16 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@12000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x12000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(32)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 { /* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps4_common_soc_peripheral.dtsi" + }; + }; +}; + +#include "mps4_common.dtsi" diff --git a/boards/arm/mps4/mps4_corstone320_fvp.yaml b/boards/arm/mps4/mps4_corstone320_fvp.yaml new file mode 100644 index 00000000000..9549fdd43b0 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp.yaml @@ -0,0 +1,26 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps4/corstone320/fvp +name: Arm MPS4-Corstone320-FVP +type: mcu +arch: arm +ram: 2048 +flash: 4096 +simulation: + - name: armfvp + exec: FVP_Corstone_SSE-320 +toolchain: + - gnuarmemb + - zephyr +supported: + - gpio +testing: + default: true + timeout_multiplier: 4 + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps4/mps4_corstone320_fvp_defconfig b/boards/arm/mps4/mps4_corstone320_fvp_defconfig new file mode 100644 index 00000000000..26d5a732e49 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp_defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y +# ROMSTART_REGION address and size are defined in Kconfig.defconfig +CONFIG_ROMSTART_RELOCATION_ROM=y diff --git a/boards/arm/mps4/mps4_corstone320_fvp_ns.dts b/boards/arm/mps4/mps4_corstone320_fvp_ns.dts new file mode 100644 index 00000000000..c511a7cc700 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp_ns.dts @@ -0,0 +1,102 @@ +/* + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + compatible = "arm,mps4-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps4/corstone320/common/partition/flash_layout.h + */ + + code: memory@28080000 { + reg = <0x28080000 DT_SIZE_K(512)>; + }; + + ram: memory@21020000 { + reg = <0x21020000 DT_SIZE_M(1)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps4_common_soc_peripheral.dtsi" + }; + }; +}; + +#include "mps4_common.dtsi" diff --git a/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml b/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml new file mode 100644 index 00000000000..45ee954a337 --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml @@ -0,0 +1,15 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps4/corstone320/fvp/ns +name: Arm MPS4-Corstone320-FVP_ns +type: mcu +arch: arm +ram: 1024 +flash: 512 +toolchain: + - gnuarmemb + - zephyr +testing: + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig b/boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig new file mode 100644 index 00000000000..d59d419011b --- /dev/null +++ b/boards/arm/mps4/mps4_corstone320_fvp_ns_defconfig @@ -0,0 +1,19 @@ +# Copyright 2025 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y +CONFIG_BUILD_WITH_TFM=y diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro-pinctrl.dtsi b/boards/atmel/sam0/same54_xpro/same54_xpro-pinctrl.dtsi index 59f6915821d..ac156f234ee 100644 --- a/boards/atmel/sam0/same54_xpro/same54_xpro-pinctrl.dtsi +++ b/boards/atmel/sam0/same54_xpro/same54_xpro-pinctrl.dtsi @@ -60,4 +60,11 @@ ; }; }; + + dac0_default: dac0_default { + group1 { + pinmux = , + ; + }; + }; }; diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.dts b/boards/atmel/sam0/same54_xpro/same54_xpro.dts index b6b9ff9d78d..7c70da060be 100644 --- a/boards/atmel/sam0/same54_xpro/same54_xpro.dts +++ b/boards/atmel/sam0/same54_xpro/same54_xpro.dts @@ -122,6 +122,25 @@ status = "okay"; }; +&dac0 { + status = "okay"; + reference = "intref"; + + channel_0 { + oversampling = "OSR_1"; + refresh-period = <1>; + current-control = "CC1M"; + }; + channel_1 { + oversampling = "OSR_1"; + refresh-period = <1>; + current-control = "CC1M"; + }; + + pinctrl-0 = <&dac0_default>; + pinctrl-names = "default"; +}; + zephyr_udc0: &usb0 { status = "okay"; diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml index 346c7fe0869..d9a73d53e84 100644 --- a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml +++ b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml @@ -12,6 +12,7 @@ flash: 1024 ram: 256 supported: - adc + - dac - dma - flash - gpio diff --git a/boards/beagle/beagleconnect_freedom/Kconfig.sysbuild b/boards/beagle/beagleconnect_freedom/Kconfig.sysbuild new file mode 100644 index 00000000000..67757e508ad --- /dev/null +++ b/boards/beagle/beagleconnect_freedom/Kconfig.sysbuild @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation +# SPDX-License-Identifier: Apache-2.0 + +if BOOTLOADER_MCUBOOT + +choice MCUBOOT_MODE + prompt "Mode of operation" + default MCUBOOT_MODE_SWAP_SCRATCH + +endchoice + +endif # BOOTLOADER_MCUBOOT diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts index ec24ee9f6bf..306aba6ef5b 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts @@ -33,6 +33,7 @@ zephyr,flash = &flash0; zephyr,ieee802154 = &ieee802154g; zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &uart0; }; gpio_keys { @@ -100,17 +101,19 @@ #address-cells = <1>; #size-cells = <1>; - /* Allocate 128 KiB for mcuboot */ + /* Allocate 56 KiB for mcuboot */ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 0x00020000>; + reg = <0x00000000 DT_SIZE_K(56)>; }; - /* Allocate 568 KiB for application (avoid touching CCFG) */ - slot0_partition: partition@20000 { + /* Allocate 640 KiB for application */ + slot0_partition: partition@e000 { label = "image-0"; - reg = <0x00020000 0x0008e000>; + reg = <0x0000e000 DT_SIZE_K(640)>; }; + + /* (avoid touching CCFG) */ }; }; @@ -169,7 +172,8 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <2000000>; - size = <0x200000>; + // Size (2 MiB) is in bits + size = <0x1000000>; //has-be32k; has-dpd; t-enter-dpd = <20000>; @@ -181,22 +185,21 @@ #address-cells = <1>; #size-cells = <1>; - /* Allocate 568 KiB for application */ + /* Allocate 640 KiB for application */ slot1_partition: partition@0 { label = "image-1"; - reg = <0x00000000 0x0008e000>; + reg = <0x00000000 DT_SIZE_K(640)>; }; /* Allocate 128 KiB scratch for image swap */ - scratch_partition: partition@8e000 { + scratch_partition: partition@A0000 { label = "image-scratch"; - reg = <0x0008e000 0x00020000>; + reg = <0x000a0000 DT_SIZE_K(128)>; }; - /* Allocate 1 MiB storage partition */ - storage_partition: partition@ae000 { + storage_partition: partition@c0000 { label = "storage"; - reg = <0x000ae000 DT_SIZE_K(1024)>; + reg = <0x000c0000 DT_SIZE_K(1280)>; }; }; }; diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml index 989f7f8e2f0..cd21601c0c3 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml @@ -15,4 +15,5 @@ supported: - hwinfo - adc - pwm + - flash vendor: beagle diff --git a/boards/beagle/beagleplay/Kconfig.beagleplay b/boards/beagle/beagleplay/Kconfig.beagleplay index e0f220288d5..4a574eaea1c 100644 --- a/boards/beagle/beagleplay/Kconfig.beagleplay +++ b/boards/beagle/beagleplay/Kconfig.beagleplay @@ -7,5 +7,3 @@ config BOARD_BEAGLEPLAY select SOC_CC1352P7 if BOARD_BEAGLEPLAY_CC1352P7 - help - BeagleBoard.org BeaglePlay CC1352P7 diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig index ded4a47c214..56af925c7c9 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51_defconfig @@ -10,3 +10,4 @@ CONFIG_UART_CONSOLE=y CONFIG_XIP=n CONFIG_INIT_STACKS=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_RISCV_CMODEL_MEDANY=y diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig index ef99af479d4..2adde2d2057 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_defconfig @@ -11,3 +11,4 @@ CONFIG_XIP=n CONFIG_INIT_STACKS=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_RV_BOOT_HART=1 +CONFIG_RISCV_CMODEL_MEDANY=y diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig index e1e30df8b16..8acfd6e4841 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp_defconfig @@ -12,3 +12,4 @@ CONFIG_INIT_STACKS=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_RV_BOOT_HART=1 CONFIG_SMP=y +CONFIG_RISCV_CMODEL_MEDANY=y diff --git a/boards/beagle/beagley_ai/doc/index.rst b/boards/beagle/beagley_ai/doc/index.rst index 6e1e6ca7e7e..2ac99ee8e6f 100644 --- a/boards/beagle/beagley_ai/doc/index.rst +++ b/boards/beagle/beagley_ai/doc/index.rst @@ -41,18 +41,7 @@ Supported Features The board configuration supports a console UART via the HAT header pins. Future versions will also support a console over RPmsg. -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| UART | on-chip | serial port-polling | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - -Other hardware features are currently not supported. - -The default configuration can be found in the defconfig file. - -Future configurations will add support for GPIO, I2C, SPI, etc. +.. zephyr:board-supported-hw:: Running Zephyr ************** diff --git a/boards/beagle/pocketbeagle_2/doc/index.rst b/boards/beagle/pocketbeagle_2/doc/index.rst index 51852ffb8c4..53ab68bd3f4 100644 --- a/boards/beagle/pocketbeagle_2/doc/index.rst +++ b/boards/beagle/pocketbeagle_2/doc/index.rst @@ -159,6 +159,7 @@ superuser privilege, openocd needs to be launched separately for now: Start debugging .. zephyr-app-commands:: + :board: pocketbeagle_2/am6232/m4 :goals: debug References diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi index 862a798952c..2eb2d73c9ca 100644 --- a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53-pinctrl.dtsi @@ -24,4 +24,17 @@ /* (K22) GPMC0_CSn2.I2C2_SCL */ pinmux = ; }; + + led_pins_default: led-default-pins { + pinmux = < + /* (F24) OSPI0_D3.GPIO0_6 */ + K3_PINMUX(0x0018, PIN_OUTPUT, MUX_MODE_7) + /* (F25) OSPI0_D2.GPIO0_5 */ + K3_PINMUX(0x0014, PIN_OUTPUT, MUX_MODE_7) + /* (G24) OSPI0_D1.GPIO0_4 */ + K3_PINMUX(0x0010, PIN_OUTPUT, MUX_MODE_7) + /* (E25) OSPI0_D0.GPIO0_3 */ + K3_PINMUX(0x000c, PIN_OUTPUT, MUX_MODE_7) + >; + }; }; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts index b035519f59e..55d99ece1d3 100644 --- a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.dts @@ -19,6 +19,10 @@ zephyr,sram = &ddr0; }; + aliases { + led0 = &led1; + }; + cpus { cpu@0 { status = "okay"; @@ -32,6 +36,30 @@ ddr0: memory@80000000 { reg = <0x80000000 DT_SIZE_M(512)>; }; + + leds: leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + + led2: led_2 { + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + label = "LED 2"; + }; + + led3: led_3 { + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + label = "LED 3"; + }; + + led4: led_4 { + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + label = "LED 4"; + }; + }; }; &uart6 { @@ -45,3 +73,9 @@ pinctrl-names = "default"; status = "okay"; }; + +&main_gpio0 { + pinctrl-0 = <&led_pins_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml index 30d04fc3551..ba4d5887a06 100644 --- a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_a53.yaml @@ -10,3 +10,4 @@ vendor: beagle supported: - uart - i2c + - gpio diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi index 7f54984345a..4a0a814c0c5 100644 --- a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi @@ -14,4 +14,21 @@ mcu_uart0_tx_default: mcu_uart0_tx_default { pinmux = ; }; + + P2_09_D4_gpio: P2-09-D4-gpio-pins { + /* (D4) MCU_MCAN1_RX.MCU_GPIO0_16 */ + pinmux = ; + }; + + P2_11_E5_gpio: P2-11-E5-gpio-pins { + /* (E5) MCU_MCAN1_TX.MCU_GPIO0_15 */ + pinmux = ; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinmux = < + K3_PINMUX(0x1c8, PIN_INPUT, MUX_MODE_0) /* (D14/A13) UART0_RXD */ + K3_PINMUX(0x1cc, PIN_OUTPUT, MUX_MODE_0) /* (E14/E11) UART0_TXD */ + >; + }; }; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts index 6b1c256976b..10e3049146e 100644 --- a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts @@ -22,6 +22,10 @@ zephyr,sram1 = &ddr1; }; + aliases { + watchdog0 = &mcu_rti0; + }; + cpus { cpu@0 { status = "okay"; @@ -59,3 +63,7 @@ pinctrl-names = "default"; status = "okay"; }; + +&mcu_rti0 { + status = "okay"; +}; diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml index fc258c2e383..fe4ea154602 100644 --- a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml +++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml @@ -8,3 +8,4 @@ ram: 192 vendor: beagle supported: - uart + - gpio diff --git a/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts index 87e986cbfe4..c559df97218 100644 --- a/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts +++ b/boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "bl604e_iot_dvk-pinctrl.dtsi" / { @@ -15,6 +15,7 @@ chosen { zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; zephyr,sram = &sram0; @@ -27,18 +28,30 @@ clock-frequency = ; }; -&spi1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4000b000 0x1000 0x23000000 0xc00000>; - - flash0: flash@0 { - compatible = "issi,is25lp128", "jedec,spi-nor"; - status = "disabled"; - size = ; - jedec-id = [96 60 18]; - reg = <0>; - spi-max-frequency = ; +&flashctrl { + flash0: flash@23000000 { + compatible = "soc-nv-flash", "issi,is25lp128"; + reg = <0x23000000 (0x1000000 - 0x2000)>; + write-block-size = <256>; + erase-block-size = ; + /* jedec-id = [96 60 18]; */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 0x100000>; + read-only; + }; + + storage_partition: partition@100000 { + label = "storage"; + reg = <0x00100000 (0xF00000 - 0x2000)>; + }; + }; }; }; diff --git a/boards/blues/cygnet/board.cmake b/boards/blues/cygnet/board.cmake index 3f2cb762859..d508be573d2 100644 --- a/boards/blues/cygnet/board.cmake +++ b/boards/blues/cygnet/board.cmake @@ -5,6 +5,6 @@ board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L433CC" "--speed=4000") # keep first -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/blues/cygnet/cygnet.dts b/boards/blues/cygnet/cygnet.dts index 00fd5282bd2..609f183b2a2 100644 --- a/boards/blues/cygnet/cygnet.dts +++ b/boards/blues/cygnet/cygnet.dts @@ -40,9 +40,23 @@ }; }; + // PH1 can be used to discharge the 3v3 net. Disabled by default. + zephyr,user { + dischrg-gpios = <&gpioh 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + }; + + supply-3v3 { + compatible = "regulator-fixed"; + regulator-name = "supply-3v3"; + enable-gpios = <&gpioh 0 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + aliases { led0 = &user_led; sw0 = &user_button; + volt-sensor0 = &vref; + volt-sensor1 = &vbat; }; }; @@ -136,3 +150,11 @@ }; }; }; + +&vref { + status = "okay"; +}; + +&vbat { + status = "okay"; +}; diff --git a/boards/blues/cygnet/cygnet_defconfig b/boards/blues/cygnet/cygnet_defconfig index 674354645c1..5763928fe8e 100644 --- a/boards/blues/cygnet/cygnet_defconfig +++ b/boards/blues/cygnet/cygnet_defconfig @@ -15,3 +15,5 @@ CONFIG_GPIO=y # Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/blues/swan_r5/board.c b/boards/blues/swan_r5/board.c deleted file mode 100644 index f6c8a308e46..00000000000 --- a/boards/blues/swan_r5/board.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2022 Blues Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -static int board_swan_init(void) -{ - const struct gpio_dt_spec dischrg = - GPIO_DT_SPEC_GET(DT_PATH(zephyr_user), dischrg_gpios); - - - if (!gpio_is_ready_dt(&dischrg)) { - return -ENODEV; - } - - (void)gpio_pin_configure_dt(&dischrg, GPIO_OUTPUT_INACTIVE); - - return 0; -} - -SYS_INIT(board_swan_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/blues/swan_r5/board.cmake b/boards/blues/swan_r5/board.cmake index 037f4a5fd14..c33afcd16a5 100644 --- a/boards/blues/swan_r5/board.cmake +++ b/boards/blues/swan_r5/board.cmake @@ -1,6 +1,10 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32L4R5ZI" "--speed=4000") +# keep first include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/blues/swan_r5/swan_r5.dts b/boards/blues/swan_r5/swan_r5.dts index 42fb3202217..a97be481486 100644 --- a/boards/blues/swan_r5/swan_r5.dts +++ b/boards/blues/swan_r5/swan_r5.dts @@ -38,9 +38,10 @@ }; }; - + // PE6 can be used to discharge the 3v3 net. Disabled by default. zephyr,user { dischrg-gpios = <&gpioe 6 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + status = "disabled"; }; supply-3v3 { diff --git a/boards/bytesatwork/bytesensi_l/Kconfig.bytesensi_l b/boards/bytesatwork/bytesensi_l/Kconfig.bytesensi_l index 530e716b540..83988f88c9e 100644 --- a/boards/bytesatwork/bytesensi_l/Kconfig.bytesensi_l +++ b/boards/bytesatwork/bytesensi_l/Kconfig.bytesensi_l @@ -2,5 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_BYTESENSI_L - bool "bytesatwork bytesSENSI-L nRF52832" select SOC_NRF52832_QFAA diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi index d99760f762c..c11f235de7b 100644 --- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi +++ b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_common.dtsi @@ -44,7 +44,6 @@ /* These aliases are provided for compatibility with samples */ aliases { led0 = &blue_led; - bootloader-led0 = &blue_led; pwm-led0 = &pwm_led0; sw0 = &button0; mcuboot-button0 = &button0; diff --git a/boards/common/silabs_commander.board.cmake b/boards/common/silabs_commander.board.cmake index e6b5f211985..1d911797993 100644 --- a/boards/common/silabs_commander.board.cmake +++ b/boards/common/silabs_commander.board.cmake @@ -1,4 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 board_set_flasher_ifnset(silabs_commander) -board_finalize_runner_args(silabs_commander) +board_finalize_runner_args(silabs_commander "--dt-flash=y") diff --git a/boards/common/spsdk.board.cmake b/boards/common/spsdk.board.cmake new file mode 100644 index 00000000000..46e73509b00 --- /dev/null +++ b/boards/common/spsdk.board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(spsdk) +board_finalize_runner_args(spsdk) diff --git a/boards/common/stlink_gdbserver.board.cmake b/boards/common/stlink_gdbserver.board.cmake new file mode 100644 index 00000000000..5b88f0cb745 --- /dev/null +++ b/boards/common/stlink_gdbserver.board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_debugger_ifnset(stlink_gdbserver) +board_finalize_runner_args(stlink_gdbserver) diff --git a/boards/common/usb/Kconfig.cdc_acm_serial.defconfig b/boards/common/usb/Kconfig.cdc_acm_serial.defconfig index 3a5661a98f4..1d6fe82cee4 100644 --- a/boards/common/usb/Kconfig.cdc_acm_serial.defconfig +++ b/boards/common/usb/Kconfig.cdc_acm_serial.defconfig @@ -23,23 +23,20 @@ config SHELL_BACKEND_SERIAL_CHECK_DTR config UART_LINE_CTRL default SHELL -config USB_DEVICE_STACK - default y - -config USB_DEVICE_INITIALIZE_AT_BOOT +config USB_DEVICE_STACK_NEXT default y if !MCUBOOT -config USB_DEVICE_REMOTE_WAKEUP - default n +config CDC_ACM_SERIAL_INITIALIZE_AT_BOOT + default y if !MCUBOOT if LOG -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF +choice USBD_CDC_ACM_LOG_LEVEL_CHOICE + default USBD_CDC_ACM_LOG_LEVEL_OFF endchoice -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_OFF +choice USBD_LOG_LEVEL_CHOICE + default USBD_LOG_LEVEL_OFF endchoice # Wait 4000ms at startup for logging diff --git a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts index 0dd4d908fa7..41bc7157346 100644 --- a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts +++ b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts @@ -45,7 +45,6 @@ led0 = &led0; led1 = &led1; sw0 = &button0; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi index 38b48f9f5ee..7ec8ba23c4f 100644 --- a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi +++ b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi @@ -33,7 +33,6 @@ led0 = &led1; led1 = &led2; mcuboot-led0 = &led1; - bootloader-led0 = &led1; watchdog0 = &wdt0; spi-flash0 = &mx25r6435; }; diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 29959964a85..c2d72844f5a 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -13,9 +13,6 @@ # https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated, # so these aliases are eventually removed -set(adafruit_feather_DEPRECATED - adafruit_feather_nrf52840/nrf52840 -) set(arduino_uno_r4_minima_DEPRECATED arduino_uno_r4@minima ) @@ -64,3 +61,6 @@ set(esp32_devkitc_wroom/esp32/appcpu_DEPRECATED set(esp32_devkitc_wrover/esp32/appcpu_DEPRECATED esp32_devkitc/esp32/appcpu ) +set(scobc_module1_DEPRECATED + scobc_a1 +) diff --git a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts index 34ce0613736..c765bdb2525 100644 --- a/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts +++ b/boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts @@ -14,6 +14,7 @@ chosen { zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; zephyr,sram = &sram0; @@ -26,18 +27,30 @@ clock-frequency = ; }; -&spi1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4000b000 0x1000 0x23000000 0xc00000>; - - flash0: flash@0 { - compatible = "issi,is25lp128", "jedec,spi-nor"; - status = "disabled"; - size = ; - jedec-id = [96 60 18]; - reg = <0>; - spi-max-frequency = ; +&flashctrl { + flash0: flash@23000000 { + compatible = "soc-nv-flash", "issi,is25lp128"; + reg = <0x23000000 (0x1000000 - 0x2000)>; + write-block-size = <256>; + erase-block-size = ; + /* jedec-id = [96 60 18]; */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 0x100000>; + read-only; + }; + + storage_partition: partition@100000 { + label = "storage"; + reg = <0x00100000 (0xF00000 - 0x2000)>; + }; + }; }; }; diff --git a/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts index 31eb0cc7524..df42f7b16c9 100644 --- a/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts +++ b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts @@ -66,7 +66,7 @@ pwm-led0 = &pwm_led0; sw0 = &button0; sw1 = &button1; - bootloader-led0 = &led0; + mcuboot-led0 = &led0; watchdog0 = &wdt0; }; }; diff --git a/boards/ene/kb1062_evb/Kconfig.kb1062_evb b/boards/ene/kb1062_evb/Kconfig.kb1062_evb new file mode 100644 index 00000000000..5db70416366 --- /dev/null +++ b/boards/ene/kb1062_evb/Kconfig.kb1062_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2025 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KB1062_EVB + select SOC_KB1062 diff --git a/boards/ene/kb1062_evb/board.cmake b/boards/ene/kb1062_evb/board.cmake new file mode 100644 index 00000000000..15f44cb5b6c --- /dev/null +++ b/boards/ene/kb1062_evb/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=KB1062" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ene/kb1062_evb/board.yml b/boards/ene/kb1062_evb/board.yml new file mode 100644 index 00000000000..8f9797ae792 --- /dev/null +++ b/boards/ene/kb1062_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: kb1062_evb + full_name: ENE KB1062_EVB + vendor: ene + socs: + - name: kb1062 diff --git a/boards/ene/kb1062_evb/doc/index.rst b/boards/ene/kb1062_evb/doc/index.rst new file mode 100644 index 00000000000..b983044c43d --- /dev/null +++ b/boards/ene/kb1062_evb/doc/index.rst @@ -0,0 +1,53 @@ +.. zephyr:board:: kb1062_evb + +Overview +******** + +The KB1062_EVB kit is a development platform to evaluate the +ENE KB106X series microcontrollers. This board needs to be mated with +part number KB1062. + +Hardware +******** + +- ARM Cortex-M3 Processor +- 256KB Flash and 64KB RAM +- ADC & GPIO headers +- SER serial port +- FAN PWM interface +- ENE Debug interface + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The KB106x MCU is configured to use the 48Mhz internal oscillator with the +on-chip DPLL to generate a resulting EC clock rate of 48MHz/24MHz +See Processor clock control register (refer 5.1 General Configuration) + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +If the correct headers are installed, this board supports SWD Debug Interface. + +To flash with SWD, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +Debugging +========= + +Use SWD with a J-Link + +References +========== + +.. target-notes:: diff --git a/boards/ene/kb1062_evb/kb1062_evb.dts b/boards/ene/kb1062_evb/kb1062_evb.dts new file mode 100644 index 00000000000..ec6d2f19bb4 --- /dev/null +++ b/boards/ene/kb1062_evb/kb1062_evb.dts @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2025 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "KB1062 board"; + compatible = "ene,kb1062"; + + aliases { + uart0 = &uart0; + led0 = &led0; + led1 = &led1; + sw0 = &user_button; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button { + label = "User"; + gpios = <&gpio6x7x 0x1b (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* green led */ + led0: led_0 { + gpios = <&gpio0x1x 0x0f GPIO_ACTIVE_HIGH>; + label = "LED0"; + }; + + /* blue led */ + led1: led_1 { + gpios = <&gpio0x1x 0x11 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&ser0_tx_gpio16 &ser0_rx_gpio17>; + pinctrl-names = "default"; +}; + +&gpio0x1x { + status = "okay"; +}; + +&gpio6x7x { + status = "okay"; +}; diff --git a/boards/ene/kb1062_evb/kb1062_evb.yaml b/boards/ene/kb1062_evb/kb1062_evb.yaml new file mode 100644 index 00000000000..31c10b2d06e --- /dev/null +++ b/boards/ene/kb1062_evb/kb1062_evb.yaml @@ -0,0 +1,12 @@ +identifier: kb1062_evb +name: KB1062 EVB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +ram: 64 +flash: 256 diff --git a/boards/ene/kb1062_evb/kb1062_evb_defconfig b/boards/ene/kb1062_evb/kb1062_evb_defconfig new file mode 100644 index 00000000000..30c5d268b1d --- /dev/null +++ b/boards/ene/kb1062_evb/kb1062_evb_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable console & UART driver +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/espressif/common/board-variants.rst b/boards/espressif/common/board-variants.rst new file mode 100644 index 00000000000..18c912fe883 --- /dev/null +++ b/boards/espressif/common/board-variants.rst @@ -0,0 +1,45 @@ +:orphan: + +.. espressif-board-variants + +Board variants using Snippets +============================= + +ESP32 boards can be assembled with different modules using multiple combinations of SPI flash sizes, PSRAM sizes and PSRAM modes. +The snippets under ``snippets/espressif`` provide a modular way to apply these variations at build time without duplicating board definitions. + +The following snippet-based variants are supported: + +=============== ======================== +Snippet name Description +=============== ======================== +*Flash memory size* +----------------------------------------- +``flash-4M`` Board with 4MB of flash +``flash-8M`` Board with 8MB of flash +``flash-16M`` Board with 16MB of flash +``flash-32M`` Board with 32MB of flash +--------------- ------------------------ +*PSRAM memory size* +----------------------------------------- +``psram-2M`` Board with 2MB of PSRAM +``psram-4M`` Board with 4MB of PSRAM +``psram-8M`` Board with 8MB of PSRAM +--------------- ------------------------ +*PSRAM utilization* +----------------------------------------- +``psram-reloc`` Relocate flash to PSRAM +``psram-wifi`` Wi-Fi buffers in PSRAM +=============== ======================== + +To apply a board variant, use the ``-S`` flag with west build: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: + :goals: build + :west-args: -S flash-32M -S psram-4M + :compact: + +**Note:** These snippets are applicable to boards with compatible hardware support for the selected flash/PSRAM configuration. diff --git a/boards/espressif/esp32_devkitc/doc/index.rst b/boards/espressif/esp32_devkitc/doc/index.rst index b7bf86406b0..f192e978de0 100644 --- a/boards/espressif/esp32_devkitc/doc/index.rst +++ b/boards/espressif/esp32_devkitc/doc/index.rst @@ -190,6 +190,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32_devkitc +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst index 22a942989fd..adec20bb69b 100644 --- a/boards/espressif/esp32_ethernet_kit/doc/index.rst +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -551,6 +551,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32_ethernet_kit +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32c3_devkitc/doc/index.rst b/boards/espressif/esp32c3_devkitc/doc/index.rst index eae08a6b8fc..b1531195381 100644 --- a/boards/espressif/esp32c3_devkitc/doc/index.rst +++ b/boards/espressif/esp32c3_devkitc/doc/index.rst @@ -182,6 +182,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32c3_devkitc +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst index d4fcb4e1713..0c18d5c8c53 100644 --- a/boards/espressif/esp32c3_devkitm/doc/index.rst +++ b/boards/espressif/esp32c3_devkitm/doc/index.rst @@ -182,6 +182,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32c3_devkitm +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32c3_rust/doc/index.rst b/boards/espressif/esp32c3_rust/doc/index.rst index 144b6948b85..4bc469007ce 100644 --- a/boards/espressif/esp32c3_rust/doc/index.rst +++ b/boards/espressif/esp32c3_rust/doc/index.rst @@ -227,6 +227,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32c3_rust +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32c6_devkitc/doc/index.rst b/boards/espressif/esp32c6_devkitc/doc/index.rst index ee0f04afaa7..5088f42aa5a 100644 --- a/boards/espressif/esp32c6_devkitc/doc/index.rst +++ b/boards/espressif/esp32c6_devkitc/doc/index.rst @@ -224,6 +224,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32c6_devkitc/esp32c6/hpcore +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts index ef8dbea59b3..f51d7af8a0e 100644 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts @@ -21,6 +21,7 @@ zephyr,shell-uart = &uart0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; }; aliases { @@ -75,3 +76,11 @@ &wifi { status = "okay"; }; + +&ieee802154 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml index 4bc3c0cde26..895ef806005 100644 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml @@ -17,6 +17,8 @@ supported: - entropy - i2c - i2s + - netif:openthread + testing: ignore_tags: - bluetooth diff --git a/boards/espressif/esp32s2_devkitc/doc/index.rst b/boards/espressif/esp32s2_devkitc/doc/index.rst index 63bf3eca409..0aabebd7c7f 100644 --- a/boards/espressif/esp32s2_devkitc/doc/index.rst +++ b/boards/espressif/esp32s2_devkitc/doc/index.rst @@ -181,6 +181,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32s2_devkitc +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst index d86a986b5e6..5ce37ad97f6 100644 --- a/boards/espressif/esp32s2_saola/doc/index.rst +++ b/boards/espressif/esp32s2_saola/doc/index.rst @@ -181,6 +181,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32s2_saola +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32s3_devkitc/doc/index.rst b/boards/espressif/esp32s3_devkitc/doc/index.rst index 4d5b07797a2..2d183fd6fd2 100644 --- a/boards/espressif/esp32s3_devkitc/doc/index.rst +++ b/boards/espressif/esp32s3_devkitc/doc/index.rst @@ -218,6 +218,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32s3_devkitc +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst index 044a3a6a660..c1416b83e51 100644 --- a/boards/espressif/esp32s3_devkitm/doc/index.rst +++ b/boards/espressif/esp32s3_devkitm/doc/index.rst @@ -218,6 +218,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32s3_devkitm +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp32s3_eye/doc/index.rst b/boards/espressif/esp32s3_eye/doc/index.rst index 0657fa20180..73ddd1ce16c 100644 --- a/boards/espressif/esp32s3_eye/doc/index.rst +++ b/boards/espressif/esp32s3_eye/doc/index.rst @@ -253,6 +253,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp32s3_eye/esp32s3/procpu +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp8684_devkitm/doc/index.rst b/boards/espressif/esp8684_devkitm/doc/index.rst index c5e00b5b5b4..c9c6da68550 100644 --- a/boards/espressif/esp8684_devkitm/doc/index.rst +++ b/boards/espressif/esp8684_devkitm/doc/index.rst @@ -188,6 +188,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp8684_devkitm +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts index 8081d955c8f..6e731d5a511 100644 --- a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts @@ -25,6 +25,7 @@ aliases { sw0 = &user_button1; + i2c-0 = &i2c0; watchdog0 = &wdt0; }; @@ -64,3 +65,7 @@ &wifi { status = "okay"; }; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml index 870622d948c..e10093fda04 100644 --- a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml @@ -6,11 +6,13 @@ toolchain: - zephyr supported: - adc + - dma - gpio - watchdog - uart - counter - entropy + - i2c - pwm - spi vendor: espressif diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst index 0c5a2ee8dd4..f9940159500 100644 --- a/boards/espressif/esp_wrover_kit/doc/index.rst +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -581,6 +581,9 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! esp_wrover_kit +.. include:: ../../../espressif/common/board-variants.rst + :start-after: espressif-board-variants + Debugging ********* diff --git a/boards/ezurio/bl54l15_dvk/Kconfig.defconfig b/boards/ezurio/bl54l15_dvk/Kconfig.defconfig index 61d46eebccf..78ec8fa7116 100644 --- a/boards/ezurio/bl54l15_dvk/Kconfig.defconfig +++ b/boards/ezurio/bl54l15_dvk/Kconfig.defconfig @@ -15,7 +15,7 @@ endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS -config BT_CTLR +config HAS_BT_CTLR default BT config FLASH_LOAD_OFFSET diff --git a/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig b/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig index 4ee4dc3e6d2..bb4934e7fd3 100644 --- a/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig +++ b/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig @@ -15,7 +15,7 @@ endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS -config BT_CTLR +config HAS_BT_CTLR default BT config FLASH_LOAD_OFFSET diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml index 11a3347969d..646dc2b7917 100644 --- a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml @@ -1,6 +1,6 @@ # Copyright (c) 2025 Nordic Semiconductor ASA # Copyright (c) 2025 Ezurio LLC -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: Apache-2.0 identifier: bl54l15u_dvk/nrf54l15/cpuapp/ns name: BL54L15u-DVK-nRF54l15-Application-Non-Secure diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig index 24848d53b82..dea04c45f20 100644 --- a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig +++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig @@ -1,6 +1,6 @@ # Copyright (c) 2025 Nordic Semiconductor ASA # Copyright (c) 2025 Ezurio LLC -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/ezurio/bl654_usb/CMakeLists.txt b/boards/ezurio/bl654_usb/CMakeLists.txt new file mode 100644 index 00000000000..218a0602483 --- /dev/null +++ b/boards/ezurio/bl654_usb/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/ezurio/bl654_usb/Kconfig b/boards/ezurio/bl654_usb/Kconfig new file mode 100644 index 00000000000..9c412700e16 --- /dev/null +++ b/boards/ezurio/bl654_usb/Kconfig @@ -0,0 +1,15 @@ +# BL654 USB board configuration + +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# Copyright (c) 2025 Ezurio LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL654_USB + select BOARD_EARLY_INIT_HOOK + +config BOARD_HAS_NRF5_BOOTLOADER + bool + default y if !BOARD_BL654_USB_NRF52840_BARE + help + If selected, applications are linked so that they can be loaded by Nordic + nRF5 bootloader. diff --git a/boards/ezurio/bl654_usb/Kconfig.bl654_usb b/boards/ezurio/bl654_usb/Kconfig.bl654_usb index 0dba254491a..bfa019bd233 100644 --- a/boards/ezurio/bl654_usb/Kconfig.bl654_usb +++ b/boards/ezurio/bl654_usb/Kconfig.bl654_usb @@ -1,6 +1,7 @@ # BL654 USB adapter board configuration -# Copyright (c) 2021 Laird Connectivity +# Copyright (c) 2018 Nordic Semiconductor ASA +# Copyright (c) 2021-2025 Ezurio LLC # SPDX-License-Identifier: Apache-2.0 config BOARD_BL654_USB diff --git a/boards/ezurio/bl654_usb/Kconfig.defconfig b/boards/ezurio/bl654_usb/Kconfig.defconfig index 7b1a6770950..0379a227c39 100644 --- a/boards/ezurio/bl654_usb/Kconfig.defconfig +++ b/boards/ezurio/bl654_usb/Kconfig.defconfig @@ -1,25 +1,33 @@ # BL654 USB adapter board configuration -# Copyright (c) 2021-2022 Laird Connectivity +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# Copyright (c) 2021-2025 Ezurio LLC # SPDX-License-Identifier: Apache-2.0 if BOARD_BL654_USB +config HW_STACK_PROTECTION + default ARCH_HAS_STACK_PROTECTION + # To let the nRF5 bootloader load an application, the application # must be linked after Nordic MBR, that is factory-programmed on the board. +# If the application wants to use the full partition size, a "bare" board +# variant should be used instead. + # Nordic nRF5 bootloader exists outside of the partitions specified in the # DTS file, so we manually override FLASH_LOAD_OFFSET to link the application -# correctly, after Nordic MBR, and limit the maximum size to not protude into +# correctly, after Nordic MBR, and limit the maximum size to not protrude into # the bootloader at the end of flash. # When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION # which will make it link into the correct partition specified in DTS file, -# so no override or limit is necessary. +# the offset is applied here so that the full partition size can be used when +# the bootloader Kconfig option has been disabled. config FLASH_LOAD_OFFSET default 0x1000 - depends on !USE_DT_CODE_PARTITION + depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION config FLASH_LOAD_SIZE default 0xdf000 diff --git a/boards/ezurio/bl654_usb/bl654_usb-pinctrl.dtsi b/boards/ezurio/bl654_usb/bl654_usb-pinctrl.dtsi index 1f5b9655fa8..06c596f7bd7 100644 --- a/boards/ezurio/bl654_usb/bl654_usb-pinctrl.dtsi +++ b/boards/ezurio/bl654_usb/bl654_usb-pinctrl.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2022 Nordic Semiconductor + * Copyright (c) 2022-2025 Ezurio LLC * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/ezurio/bl654_usb/bl654_usb.dts b/boards/ezurio/bl654_usb/bl654_usb.dts index 6ce352bda6d..f061051dada 100644 --- a/boards/ezurio/bl654_usb/bl654_usb.dts +++ b/boards/ezurio/bl654_usb/bl654_usb.dts @@ -1,76 +1,15 @@ /* - * Copyright (c) 2021 Laird Connectivity - * Copyright (c) 2024 Ezurio + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2024-2025 Ezurio LLC * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; -#include -#include "bl654_usb-pinctrl.dtsi" +#include "bl654_usb_common.dtsi" -/ { - model = "Ezurio BL654 USB adapter"; - compatible = "ezurio,bl654_usb"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,ieee802154 = &ieee802154; - }; - - leds { - compatible = "gpio-leds"; - led1: led_1 { - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - label = "Blue LED 1"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - led1bluepwm: led_pwm_1 { - pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "PWM LED 1 Blue"; - }; - - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led1; - led1pwm = &led1bluepwm; - watchdog0 = &wdt0; - }; -}; - -®1 { - regulator-initial-mode = ; -}; - -&uicr { - gpio-as-nreset; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpiote { - status = "okay"; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; +/* Flash partition table compatible with the onboard USB bootloader */ &flash0 { partitions { @@ -79,8 +18,8 @@ #size-cells = <1>; /* MCUboot placed after Nordic MBR. - * The size of this partition ensures that MCUBoot - * can be built with CDC ACM support and w/o optimizations. + * The size of this partition ensures that MCUBoot can + * be built with CDC ACM support and w/o optimizations. */ boot_partition: partition@1000 { label = "mcuboot"; @@ -89,32 +28,24 @@ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 0x0005e000>; + reg = <0x00010000 0x00066000>; }; - slot1_partition: partition@6e000 { + + slot1_partition: partition@76000 { label = "image-1"; - reg = <0x0006e000 0x0005e000>; + reg = <0x00076000 0x00066000>; }; - storage_partition: partition@cc000 { + + storage_partition: partition@dc000 { label = "storage"; - reg = <0x000cc000 0x00008000>; - }; - scratch_partition: partition@d4000 { - label = "image-scratch"; - reg = <0x000d4000 0x0000C000>; + reg = <0x000dc000 0x00004000>; }; - /* Nordic nRF5 bootloader <0xe0000 0x1c000> + /* Onboard USB bootloader <0xe0000 0x1c000> * * In addition, the last and second last flash pages - * are used by the nRF5 bootloader and MBR to store settings. + * are used by the onboard USB bootloader and MBR to store + * settings. */ }; }; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; - -#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/ezurio/bl654_usb/bl654_usb.yaml b/boards/ezurio/bl654_usb/bl654_usb.yaml index a56efa32877..660ee57e467 100644 --- a/boards/ezurio/bl654_usb/bl654_usb.yaml +++ b/boards/ezurio/bl654_usb/bl654_usb.yaml @@ -1,7 +1,9 @@ identifier: bl654_usb -name: BL654_USB +name: BL654-USB type: mcu arch: arm +ram: 256 +flash: 1024 toolchain: - zephyr - gnuarmemb @@ -11,4 +13,6 @@ supported: - pwm - watchdog - counter + - netif:openthread + - gpio vendor: ezurio diff --git a/boards/ezurio/bl654_usb/bl654_usb_common.dtsi b/boards/ezurio/bl654_usb/bl654_usb_common.dtsi new file mode 100644 index 00000000000..c1a6a5dc05d --- /dev/null +++ b/boards/ezurio/bl654_usb/bl654_usb_common.dtsi @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl654_usb-pinctrl.dtsi" + +/ { + model = "Ezurio BL654 USB"; + compatible = "ezurio,bl654-usb-nrf52840"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Blue LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + led1bluepwm: led_pwm_1 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 1 Blue"; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + pwm-led0 = &led1bluepwm; + watchdog0 = &wdt0; + }; +}; + +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + +&gpiote { + status = "okay"; +}; + +&uicr { + gpio-as-nreset; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/ezurio/bl654_usb/bl654_usb_defconfig b/boards/ezurio/bl654_usb/bl654_usb_defconfig index 053eb9dafdb..acbb7fa61e2 100644 --- a/boards/ezurio/bl654_usb/bl654_usb_defconfig +++ b/boards/ezurio/bl654_usb/bl654_usb_defconfig @@ -1,18 +1,17 @@ # SPDX-License-Identifier: Apache-2.0 - # Enable MPU CONFIG_ARM_MPU=y -# Enable uart driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y - # Enable GPIO CONFIG_GPIO=y # 32KHz clock source CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y + +# Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote +# wakeup by default. It needs to be disabled here, because the USB nrfx +# driver always overwrites option from Kconfig mentioned above with the +# imply from CONFIG_USB_NRFX. +CONFIG_USB_DEVICE_REMOTE_WAKEUP=n diff --git a/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.dts b/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.dts new file mode 100644 index 00000000000..f84ac6acd77 --- /dev/null +++ b/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.dts @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2025 Ezurio LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "bl654_usb_common.dtsi" + +/* Flash partition table without support for the onboard USB bootloader */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* The size of this partition ensures that MCUBoot can be built + * with an RTT console, CDC ACM support, and w/o optimizations. + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00012000>; + }; + + slot0_partition: partition@12000 { + label = "image-0"; + reg = <0x00012000 0x00075000>; + }; + + slot1_partition: partition@87000 { + label = "image-1"; + reg = <0x00087000 0x00075000>; + }; + + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + }; +}; diff --git a/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.yaml b/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.yaml new file mode 100644 index 00000000000..4d92d331a2f --- /dev/null +++ b/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare.yaml @@ -0,0 +1,18 @@ +identifier: bl654_usb/nrf52840/bare +name: BL654-USB-NRF52840-bare +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - usb_device + - ble + - pwm + - watchdog + - counter + - netif:openthread + - gpio +vendor: ezurio diff --git a/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare_defconfig b/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare_defconfig new file mode 100644 index 00000000000..614f9a16853 --- /dev/null +++ b/boards/ezurio/bl654_usb/bl654_usb_nrf52840_bare_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# 32KHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y + +# Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote +# wakeup by default. It needs to be disabled here, because the USB nrfx +# driver always overwrites option from Kconfig mentioned above with the +# imply from CONFIG_USB_NRFX. +CONFIG_USB_DEVICE_REMOTE_WAKEUP=n diff --git a/boards/ezurio/bl654_usb/board.c b/boards/ezurio/bl654_usb/board.c new file mode 100644 index 00000000000..7d556386410 --- /dev/null +++ b/boards/ezurio/bl654_usb/board.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA. + * Copyright (c) 2025 Ezurio LLC. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +void board_early_init_hook(void) +{ + /* If the bl654_usb board target is powered from USB + * (high voltage mode), GPIO output voltage is set to 1.8 volts by + * default and that is not enough to turn the green and blue LEDs on. + * Increase GPIO voltage to 3.0 volts. + */ + if ((nrf_power_mainregstatus_get(NRF_POWER) == + NRF_POWER_MAINREGSTATUS_HIGH) && + ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) == + (UICR_REGOUT0_VOUT_DEFAULT << UICR_REGOUT0_VOUT_Pos))) { + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { + ; + } + + NRF_UICR->REGOUT0 = + (NRF_UICR->REGOUT0 & ~((uint32_t)UICR_REGOUT0_VOUT_Msk)) | + (UICR_REGOUT0_VOUT_3V0 << UICR_REGOUT0_VOUT_Pos); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { + ; + } + + /* a reset is required for changes to take effect */ + NVIC_SystemReset(); + } +} diff --git a/boards/ezurio/bl654_usb/board.cmake b/boards/ezurio/bl654_usb/board.cmake new file mode 100644 index 00000000000..895ec1a36bd --- /dev/null +++ b/boards/ezurio/bl654_usb/board.cmake @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ezurio/bl654_usb/board.yml b/boards/ezurio/bl654_usb/board.yml index 6329e4db30c..db6e65589e9 100644 --- a/boards/ezurio/bl654_usb/board.yml +++ b/boards/ezurio/bl654_usb/board.yml @@ -4,3 +4,5 @@ board: vendor: ezurio socs: - name: nrf52840 + variants: + - name: bare diff --git a/boards/ezurio/bl654_usb/doc/bl654_usb.rst b/boards/ezurio/bl654_usb/doc/bl654_usb.rst index 04ac5759753..46f90f2a444 100644 --- a/boards/ezurio/bl654_usb/doc/bl654_usb.rst +++ b/boards/ezurio/bl654_usb/doc/bl654_usb.rst @@ -7,7 +7,7 @@ The BL654 USB adapter hardware (Ezurio part 451-00004) provides support for the Ezurio BL654 module powered by a Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. -This USB adapter has the following features: +The BL654 USB adapter has the following features: * CLOCK * FLASH @@ -16,9 +16,9 @@ This USB adapter has the following features: * :abbr:`NVIC (Nested Vectored Interrupt Controller)` * :abbr:`PWM (Pulse Width Modulation)` * RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -* :abbr:`RTC (nRF RTC System Clock)` .. figure:: img/bl654_usb_pcb.jpg :align: center @@ -26,20 +26,23 @@ This USB adapter has the following features: BL654 USB Adapter PCB -More information about the BL654 USB adapter can be found on the `BL654 USB +More information about the BL654 USB adapter can be found in the `BL654 USB Dongle Quick Start Guide`_. There is more information on the BL654 range on the `BL654 website`_. Hardware ******** +The ``bl654_usb`` has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + Supported Features ================== .. zephyr:board-supported-hw:: -See `BL654 website`_ -for a complete list of BL654 USB adapter hardware features. +See the `BL654 website`_ for a complete list of BL654 USB adapter hardware features. Connections and IOs =================== @@ -69,19 +72,28 @@ Programming and Debugging Applications for the ``bl654_usb`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). The -``bl654_usb`` board cannot be used for debugging. The compatible BL654 DVK -board can be used for development. Documentation can be found at the :zephyr:board:`bl654_dvk` +``bl654_usb`` board can be used for debugging, but the compatible BL654 DVK +board may be preferable for convenience. Documentation can be found at the :zephyr:board:`bl654_dvk` site and :zephyr_file:`boards/ezurio/bl654_dvk/doc/bl654_dvk.rst` Flashing ======== -The board supports programming using the built-in bootloader. +The board supports the following programming options: + +1. Using the built-in bootloader only +2. Using an external :ref:`debug probe ` -The board is factory-programmed with a Ezurio variation of Nordic's -open bootloader from Nordic's nRF5x SDK. With this option, you'll use -Nordic's `nrfutil`_ program to create firmware packages supported by this -bootloader and flash them to the device. Before proceeding, make sure: +These instructions use the :ref:`west ` tool and assume you are in the +root directory of your :term:`west installation`. + +Option 1: Using the Built-In Bootloader Only +-------------------------------------------- + +The board is factory-programmed with Nordic's bootloader from Nordic's nRF5 +SDK. With this option, you'll use Nordic's `nrfutil`_ program to create +firmware packages supported by this bootloader and flash them to the +device. Before proceeding make sure: * ``nrfutil`` is installed. * The ``nrf5sdk-tools`` command is installed within ``nrfutil``. @@ -123,18 +135,45 @@ bootloader and flash them to the device. Before proceeding, make sure: nrfutil nrf5sdk-tools dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0 - When this command exits, observe the blue LED on the board blinking. + When this command exits, observe the blue LED on the board blinking, + instead of the fade pattern used by the bootloader. +For more information, see `Nordic Semiconductor USB DFU`_. -Testing Bluetooth on the BL654 USB -*********************************** -Many of the Bluetooth examples will work on the BL654 USB. -Try them out: +Option 2: Using an External Debug Probe +--------------------------------------- -* :zephyr:code-sample:`ble_peripheral` -* :zephyr:code-sample:`bluetooth_eddystone` -* :zephyr:code-sample:`bluetooth_ibeacon` +If you have one, you can also use an external :ref:`debug probe ` +to flash and debug Zephyr applications, but you need to solder an SWD header +to the board. Connection points can be found in the `board schematics`_. + +For Segger J-Link debug probes, follow the instructions in the +:ref:`nordic_segger` page to install and configure all the necessary +software. Further information can be found in :ref:`nordic_segger_flashing`. +Use the ``bl654_usb/bare`` board variant to build your application. +This variant uses a modified partition table, which does not reserve space for +the onboard USB bootloader. + +Then build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: bl654_usb/nrf52840/bare + :goals: build flash + +Observe the LED on the board blinking. + +Debugging +========= + +The ``bl654_usb`` board does not have an on-board J-Link debug IC +as some Ezurio development boards, however, instructions from the +:ref:`nordic_segger` page also apply to this board, with the additional step +of connecting an external debugger. Testing the LED on the BL654 USB ************************************************ @@ -148,14 +187,29 @@ You can build and flash the example to make sure Zephyr is running correctly on your board. The LED definitions can be found in :zephyr_file:`boards/ezurio/bl654_usb/bl654_usb.dts`. +Testing Bluetooth on the BL654 USB +*********************************** +Many of the Bluetooth examples will work on the BL654 USB. +Try them out: + +* :zephyr:code-sample:`ble_peripheral` +* :zephyr:code-sample:`bluetooth_eddystone` +* :zephyr:code-sample:`bluetooth_ibeacon` References ********** .. target-notes:: -.. _BL654 USB Dongle Quick Start Guide: https://www.ezurio.com/documentation/user-guide-bl654-usb-nordic-sdk-zephyr -.. _BL654 website: https://ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _Creating a secure bootloader image: https://www.ezurio.com/documentation/application-note-creating-secure-bootloader-image-bl654-usb -.. _nrfutil: https://github.com/NordicSemiconductor/pc-nrfutil +.. _BL654 USB Dongle Quick Start Guide: + https://www.ezurio.com/documentation/user-guide-bl654-usb-nordic-sdk-zephyr +.. _BL654 website: + https://ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html +.. _Nordic Semiconductor USB DFU: + https://docs.nordicsemi.com/bundle/sdk_nrf5_v17.1.0/page/sdk_app_serial_dfu_bootloader.html +.. _nrfutil: + https://www.nordicsemi.com/Products/Development-tools/nrf-util +.. _board schematics: + https://www.ezurio.com/documentation/schematics-usb-adapter-bl654-451-00004 diff --git a/boards/fanke/fk743m5_xih6/board.cmake b/boards/fanke/fk743m5_xih6/board.cmake index 10170d65424..a85d044e0a1 100644 --- a/boards/fanke/fk743m5_xih6/board.cmake +++ b/boards/fanke/fk743m5_xih6/board.cmake @@ -3,7 +3,9 @@ board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(jlink "--device=STM32H743XI" "--speed=4000") +board_runner_args(pyocd "--target=STM32H743XIHx") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) \ No newline at end of file diff --git a/boards/fanke/fk743m5_xih6/doc/index.rst b/boards/fanke/fk743m5_xih6/doc/index.rst index 0c7dbbfbe44..636b0365740 100644 --- a/boards/fanke/fk743m5_xih6/doc/index.rst +++ b/boards/fanke/fk743m5_xih6/doc/index.rst @@ -122,7 +122,19 @@ Then, press the RESET button, you should see the following message: Debugging ========= -This current Zephyr port does not support debugging. +You can debug an application using the SWD interface with a J-Link or ST-Link. For more +details, please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: fk743m5_xih6 + :goals: debug + :flash-args: -r pyocd + :compact: References ********** diff --git a/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts b/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts index 93f9cd88847..798418d379f 100644 --- a/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts +++ b/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts @@ -31,6 +31,21 @@ aliases { led0 = &user_led; }; + + ext_memory: memory@90000000 { + compatible = "zephyr,memory-region"; + reg = <0x90000000 DT_SIZE_M(256)>; + zephyr,memory-region = "EXTMEM"; + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; + + sdram1: sdram@c0000000 { + compatible = "zephyr,memory-region"; + reg = <0xc0000000 DT_SIZE_M(32)>; + zephyr,memory-region = "SDRAM1"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; }; &clk_hsi48 { @@ -81,9 +96,10 @@ status = "okay"; /* Winbond external flash */ - w25q64_qspi: qspi-nor-flash@90000000 { + w25q64_qspi: qspi-nor-flash@0 { compatible = "st,stm32-qspi-nor"; - reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */ + reg = <0>; + size = ; /* 64 Mbits */ qspi-max-frequency = <40000000>; status = "okay"; spi-bus-width = <4>; @@ -101,6 +117,43 @@ }; }; +&fmc { + pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 + &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_ph2 + &fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15 + &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 + &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14 + &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 + &fmc_a12_pg2 &fmc_d0_pd14 &fmc_d1_pd15 + &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 + &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 + &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 + &fmc_d15_pd10>; + pinctrl-names = "default"; + status = "okay"; + + sdram { + status = "okay"; + power-up-delay = <100>; + num-auto-refresh = <8>; + mode-register = <0x230>; + refresh-rate = <0x603>; + + bank@0 { + reg = <0>; + st,sdram-control = ; + st,sdram-timing = <2 7 4 7 3 2 2>; + }; + }; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; pinctrl-names = "default"; diff --git a/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml b/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml index 932fcb5f3f4..76da5b75819 100644 --- a/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml +++ b/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml @@ -13,4 +13,5 @@ supported: - spi - backup_sram - qspi + - memc vendor: fanke diff --git a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts index a3351b7e864..c3c1b6418bf 100644 --- a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts +++ b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts @@ -118,9 +118,10 @@ status = "okay"; /* Winbond external flash */ - w25q64_qspi: qspi-nor-flash@90000000 { + w25q64_qspi: qspi-nor-flash@0 { compatible = "st,stm32-qspi-nor"; - reg = <0x90000000 DT_SIZE_M(64)>; /* 64 Mbits */ + reg = <0>; + size = ; /* 64 Mbits */ qspi-max-frequency = <40000000>; status = "okay"; spi-bus-width = <4>; diff --git a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts index a8db5b677f2..56f65130f5a 100644 --- a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts +++ b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts @@ -85,7 +85,8 @@ /* Winbond external flash */ w25q64jvssiq_qspi: qspi-nor-flash@0 { compatible = "st,stm32-ospi-nor"; - reg = <0 DT_SIZE_M(8)>; /* 64 Mbits */ + reg = <0>; + size = ; /* 64 Mbits */ ospi-max-frequency = ; spi-bus-width = ; data-rate = ; diff --git a/boards/gardena/sgrm/Kconfig.sgrm b/boards/gardena/sgrm/Kconfig.sgrm index 3a758c2eaf7..f770afcf929 100644 --- a/boards/gardena/sgrm/Kconfig.sgrm +++ b/boards/gardena/sgrm/Kconfig.sgrm @@ -3,4 +3,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_SGRM - select SOC_PART_NUMBER_SIM3U167BGM + select SOC_SIM3U167BGM diff --git a/boards/google/quincy/google_quincy.dts b/boards/google/quincy/google_quincy.dts index 7067cd4cf31..2a075c9b564 100644 --- a/boards/google/quincy/google_quincy.dts +++ b/boards/google/quincy/google_quincy.dts @@ -61,3 +61,8 @@ pinctrl-names = "default"; status = "okay"; }; + +/* DRBG: Deterministic Random Bit Generator */ +&drbg0 { + status = "okay"; +}; diff --git a/boards/google/quincy/google_quincy_defconfig b/boards/google/quincy/google_quincy_defconfig index 0b5fcc5649f..a71b36f4875 100644 --- a/boards/google/quincy/google_quincy_defconfig +++ b/boards/google/quincy/google_quincy_defconfig @@ -1,6 +1,9 @@ # Copyright (c) 2024 Google Inc # SPDX-License-Identifier: Apache-2.0 +# Enable NPCX firmware header +CONFIG_NPCX_HEADER=y + # General Kernel Options CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000 diff --git a/boards/google/twinkie_v2/google_twinkie_v2.dts b/boards/google/twinkie_v2/google_twinkie_v2.dts index eaffe70edf4..cb41647db7a 100644 --- a/boards/google/twinkie_v2/google_twinkie_v2.dts +++ b/boards/google/twinkie_v2/google_twinkie_v2.dts @@ -80,7 +80,6 @@ led0 = &red_led_0; led1 = &green_led_1; led2 = &blue_led_2; - bootloader-led0 = &blue_led_2; vcc1 = &cc1_buf; vcc2 = &cc2_buf; vbus = &vbus_read_buf; diff --git a/boards/infineon/kit_psc3m5_evk/Kconfig.kit_psc3m5_evk b/boards/infineon/kit_psc3m5_evk/Kconfig.kit_psc3m5_evk new file mode 100644 index 00000000000..6a1d5e5d7b2 --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/Kconfig.kit_psc3m5_evk @@ -0,0 +1,7 @@ +# The Infineon PSOC™ Control C3M5 Evaluation Kit (KIT_PSC3M5_EVK) + +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KIT_PSC3M5_EVK + select SOC_PSC3M5FDS2AFQ1 diff --git a/boards/infineon/kit_psc3m5_evk/board.cmake b/boards/infineon/kit_psc3m5_evk/board.cmake new file mode 100644 index 00000000000..fbee39958f6 --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd "--target-handle=TARGET.cm33") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/infineon/kit_psc3m5_evk/board.yml b/boards/infineon/kit_psc3m5_evk/board.yml new file mode 100644 index 00000000000..5307ae73b1c --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/board.yml @@ -0,0 +1,8 @@ +board: + name: kit_psc3m5_evk + full_name: PSOC Control C3M5 Evaluation Kit + vendor: infineon + socs: + - name: psc3m5fds2afq1 + variants: + - name: 'ns' diff --git a/boards/infineon/kit_psc3m5_evk/doc/img/kit_psc3m5_evk.webp b/boards/infineon/kit_psc3m5_evk/doc/img/kit_psc3m5_evk.webp new file mode 100644 index 00000000000..d98dc4463b9 Binary files /dev/null and b/boards/infineon/kit_psc3m5_evk/doc/img/kit_psc3m5_evk.webp differ diff --git a/boards/infineon/kit_psc3m5_evk/doc/index.rst b/boards/infineon/kit_psc3m5_evk/doc/index.rst new file mode 100644 index 00000000000..96aee57fb13 --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/doc/index.rst @@ -0,0 +1,122 @@ +.. zephyr:board:: kit_psc3m5_evk + +Overview +******** + +This is the standard evaluation board for the PSOC™ Control C3 family of MCU's. PSOC™ Control C3M5 +is a high-performance and low-power 32-bit single-core Arm® Cortex® M33-based MCU. +In addition to the CPU subsystem, the devices contain advanced real-time control peripherals, +such as a high-performance programmable analog subsystem, comparators, advanced timers with +high-resolution capability, up to six SCBs, and two CAN FDs for communication. + +Hardware +******** + +For more information about the PSC3M5 SoC and KIT_PSC3M5_EVK board: + +- `PSOC Control C3 SoC Website`_ +- `KIT_PSC3M5_EVK Board Website`_ + +Kit Features: +============= + +- Onboard programmer/debugger (KitProg3) +- PSC3M5FDS2AFQ1 +- Type-C USB device interface +- Operating voltage of 3.3 V +- CAN FD interface +- Headers for MIKROE's mikroBUS shields +- Headers compatible with Arduino Uno R3 +- Mode button and a mode LED for KitProg3 +- Potentionmeter to simulate analog output +- Two (40-pin) expansion headers + +Kit Contents: +============= + +- EVK board +- Type C to USB A cable +- Quick Start Guide + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Build blinking led sample +************************* + +Here is an example for building the :zephyr:code-sample:`blinky` sample application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: kit_psc3m5_evk + :goals: build + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The KIT_PSC3M5_EVK includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. + +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b kit_psc3m5_evk -p always samples/basic/blinky + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b kit_psc3m5_evk -p always samples/basic/blinky + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the CYW20829 CM33 core. + +.. _PSOC Control C3 SoC Website: + https://www.infineon.com/cms/en/product/microcontroller/32-bit-psoc-arm-cortex-microcontroller/32-bit-psoc-control-arm-cortex-m33-mcu/ + +.. _KIT_PSC3M5_EVK Board Website: + https://www.infineon.com/cms/en/product/evaluation-boards/kit_psc3m5_evk/ + +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk-common.dtsi b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk-common.dtsi new file mode 100644 index 00000000000..0cc449be9e9 --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk-common.dtsi @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2025 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + aliases { + led0 = &user_led0; + led1 = &user_led1; + sw0 = &user_bt0; + sw1 = &user_bt1; + }; + + leds { + compatible = "gpio-leds"; + + user_led0: led_0 { + label = "LED_0"; + gpios = <&gpio_prt8 5 GPIO_ACTIVE_LOW>; + }; + + user_led1: led_1 { + label = "LED_1"; + gpios = <&gpio_prt8 4 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_bt0: user_btn0 { + label = "SW_1"; + gpios = <&gpio_prt5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + + user_bt1: user_btn1 { + label = "SW_2"; + gpios = <&gpio_prt2 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&gpio_prt0 { + status = "okay"; +}; + +&gpio_prt1 { + status = "okay"; +}; + +&gpio_prt2 { + status = "okay"; +}; + +&gpio_prt3 { + status = "okay"; +}; + +&gpio_prt5 { + status = "okay"; +}; + +&gpio_prt6 { + status = "okay"; +}; + +&gpio_prt8 { + status = "okay"; +}; diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk-pinctrl.dtsi b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk-pinctrl.dtsi new file mode 100644 index 00000000000..f2ffdc586f3 --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk-pinctrl.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Configure pin drive mode for uart pins */ +&p6_3_scb3_uart_tx { + drive-push-pull; +}; + +&p6_2_scb3_uart_rx { + input-enable; +}; + +&p6_1_scb3_uart_rts { + drive-push-pull; +}; + +&p6_0_scb3_uart_cts { + input-enable; +}; diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts new file mode 100644 index 00000000000..29f46946325 --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2025 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "kit_psc3m5_evk-common.dtsi" +#include "kit_psc3m5_evk-pinctrl.dtsi" + +/ { + model = "The Infineon PSOC™ Control C3M5 Evaluation Kit"; + compatible = "infineon,kit_psc3m5_evk", "infineon,PSC3M5"; + + aliases { + watchdog0 = &watchdog0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &slot0_partition; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; + +uart3: &scb3 { + compatible = "infineon,cat1-uart-pdl"; + status = "okay"; + current-speed = <115200>; + + clocks = <&peri0_group4_8bit_0>; + + pinctrl-0 = <&p6_3_scb3_uart_tx &p6_2_scb3_uart_rx &p6_1_scb3_uart_rts &p6_0_scb3_uart_cts>; + pinctrl-names = "default"; +}; + +&peri0_group4_8bit_0 { + status = "okay"; + scb-block = <3>; + div-value = <109>; +}; + +&path_mux0 { + status = "okay"; +}; + +&path_mux1 { + status = "okay"; +}; + +&path_mux2 { + status = "okay"; +}; + +&path_mux3 { + status = "okay"; +}; + +&clk_hf0 { + status = "okay"; +}; + +&clk_hf1 { + status = "okay"; +}; + +&clk_hf2 { + status = "okay"; +}; + +&clk_hf3 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&mcwdt0 { + status = "okay"; +}; diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.yaml b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.yaml new file mode 100644 index 00000000000..fa4ec97aa8a --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.yaml @@ -0,0 +1,17 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: kit_psc3m5_evk +name: The Infineon PSOC™ Control C3M5 Evaluation Kit (KIT_PSC3M5_EVK) +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio +vendor: infineon diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_defconfig b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_defconfig new file mode 100644 index 00000000000..3ff25ee0a17 --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_defconfig @@ -0,0 +1,22 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_TRUSTED_EXECUTION_SECURE=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts new file mode 100644 index 00000000000..49dd0814e0b --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2025 Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "kit_psc3m5_evk-common.dtsi" +#include "kit_psc3m5_evk-pinctrl.dtsi" + +/ { + model = "The Infineon PSOC™ Control C3M5 Evaluation Kit"; + compatible = "infineon,kit_psc3m5_evk", "infineon,PSC3M5"; + + aliases { + watchdog0 = &watchdog0; + }; + + chosen { + zephyr,sram = &sram0_ns; + zephyr,flash = &slot0_ns_partition; + zephyr,console = &uart3; + zephyr,shell-uart = &uart3; + }; +}; + +uart3: &scb3 { + compatible = "infineon,cat1-uart-pdl"; + status = "okay"; + current-speed = <115200>; + + clocks = <&peri0_group4_8bit_0>; + + pinctrl-0 = <&p6_3_scb3_uart_tx &p6_2_scb3_uart_rx &p6_1_scb3_uart_rts &p6_0_scb3_uart_cts>; + pinctrl-names = "default"; +}; + +&peri0_group4_8bit_0 { + status = "okay"; + scb-block = <3>; + div-value = <109>; +}; + +&path_mux0 { + status = "okay"; +}; + +&path_mux1 { + status = "okay"; +}; + +&path_mux2 { + status = "okay"; +}; + +&path_mux3 { + status = "okay"; +}; + +&clk_hf0 { + status = "okay"; +}; + +&clk_hf1 { + status = "okay"; +}; + +&clk_hf2 { + status = "okay"; +}; + +&clk_hf3 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&mcwdt0 { + status = "okay"; +}; diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.yaml b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.yaml new file mode 100644 index 00000000000..fa4ec97aa8a --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.yaml @@ -0,0 +1,17 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: kit_psc3m5_evk +name: The Infineon PSOC™ Control C3M5 Evaluation Kit (KIT_PSC3M5_EVK) +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio +vendor: infineon diff --git a/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns_defconfig b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns_defconfig new file mode 100644 index 00000000000..8ce444887c2 --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns_defconfig @@ -0,0 +1,23 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# + +# General configuration +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y diff --git a/boards/infineon/kit_psc3m5_evk/support/openocd.cfg b/boards/infineon/kit_psc3m5_evk/support/openocd.cfg new file mode 100644 index 00000000000..3a108e910dd --- /dev/null +++ b/boards/infineon/kit_psc3m5_evk/support/openocd.cfg @@ -0,0 +1,13 @@ +# +# Copyright (c) 2025 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +source [find interface/kitprog3.cfg] +set ENABLE_ACQUIRE 0 +transport select swd + +source [find target/infineon/psc3.cfg] + +if { [info exists _ZEPHYR_BOARD_SERIAL] } { + adapter serial $_ZEPHYR_BOARD_SERIAL +} diff --git a/boards/intel/adsp/Kconfig b/boards/intel/adsp/Kconfig new file mode 100644 index 00000000000..57a470699c0 --- /dev/null +++ b/boards/intel/adsp/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config RIMAGE_TARGET + string + default "tgl" if BOARD_INTEL_ADSP_CAVS25 + default "tgl-h" if BOARD_INTEL_ADSP_CAVS25_TGPH + default "mtl" if BOARD_INTEL_ADSP_ACE15_MTPM || BOARD_INTEL_ADSP_ACE15_MTPM_SIM + default "lnl" if BOARD_INTEL_ADSP_ACE20_LNL || BOARD_INTEL_ADSP_ACE20_LNL_SIM + default "ptl" if BOARD_INTEL_ADSP_ACE30_PTL || BOARD_INTEL_ADSP_ACE30_PTL_SIM + default "wcl" if BOARD_INTEL_ADSP_ACE30_WCL || BOARD_INTEL_ADSP_ACE30_WCL_SIM + default "nvl" if BOARD_INTEL_ADSP_ACE40_NVL || BOARD_INTEL_ADSP_ACE40_NVL_SIM || BOARD_INTEL_ADSP_ACE40_NVLS diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp index ac62b9e2d52..0a29c0d1381 100644 --- a/boards/intel/adsp/Kconfig.intel_adsp +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -12,3 +12,6 @@ config BOARD_INTEL_ADSP select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM + select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL + select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL_SIM + select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVLS diff --git a/boards/intel/adsp/board.cmake b/boards/intel/adsp/board.cmake index e6055be6f37..4de02537cb0 100644 --- a/boards/intel/adsp/board.cmake +++ b/boards/intel/adsp/board.cmake @@ -2,57 +2,17 @@ # # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_BOARD_INTEL_ADSP_CAVS25 OR CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) - - if($ENV{CAVS_OLD_FLASHER}) - board_set_flasher_ifnset(misc-flasher) - board_finalize_runner_args(misc-flasher) - endif() - - board_set_flasher_ifnset(intel_adsp) - - set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in cavs25/board.cmake") - - if(CONFIG_BOARD_INTEL_ADSP_CAVS25) - board_set_rimage_target(tgl) - endif() - - if(CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) - board_set_rimage_target(tgl-h) - endif() - - board_finalize_runner_args(intel_adsp) - -elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM OR CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM_SIM) - - board_set_rimage_target(mtl) - - set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace15_mtpm/board.cmake") - - board_finalize_runner_args(intel_adsp) - -elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL OR CONFIG_BOARD_INTEL_ADSP_ACE20_LNL_SIM) - +if (CONFIG_INTEL_ADSP_SIM) set(SUPPORTED_EMU_PLATFORMS acesim) +endif() - board_set_rimage_target(lnl) - - set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace20_lnl/board.cmake") - -elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SIM) - - board_set_rimage_target(ptl) - - set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key") - - board_finalize_runner_args(intel_adsp) - -elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_WCL OR CONFIG_BOARD_INTEL_ADSP_ACE30_WCL_SIM) - - board_set_rimage_target(wcl) - - set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key") - - board_finalize_runner_args(intel_adsp) +board_set_rimage_target(${CONFIG_RIMAGE_TARGET}) +board_set_flasher_ifnset(intel_adsp) +if(DEFINED ENV{RIMAGE_SIGN_KEY}) + set(RIMAGE_SIGN_KEY $ENV{RIMAGE_SIGN_KEY} CACHE STRING "default key via env") +else() + set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default key") endif() + +board_finalize_runner_args(intel_adsp) diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml index 5bc812edb37..6bfbfcdfd1e 100644 --- a/boards/intel/adsp/board.yml +++ b/boards/intel/adsp/board.yml @@ -20,3 +20,9 @@ boards: - name: 'wcl' variants: - name: 'sim' + - name: ace40 + variants: + - name: 'nvl' + variants: + - name: 'sim' + - name: 'nvls' diff --git a/boards/intel/adsp/intel_adsp_ace40_nvl.dts b/boards/intel/adsp/intel_adsp_ace40_nvl.dts new file mode 100644 index 00000000000..e088bc09163 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace40_nvl.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace40_nvl"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &mem_window3; + }; +}; diff --git a/boards/intel/adsp/intel_adsp_ace40_nvl_defconfig b/boards/intel/adsp/intel_adsp_ace40_nvl_defconfig new file mode 100644 index 00000000000..913d2a8c3e3 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace40_nvl_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace40_nvl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace40_nvl_sim_defconfig new file mode 100644 index 00000000000..4043a306c3f --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace40_nvl_sim_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_INTEL_ADSP_SIM=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/intel_adsp_ace40_nvls.dts b/boards/intel/adsp/intel_adsp_ace40_nvls.dts new file mode 100644 index 00000000000..12eeb5971cb --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace40_nvls.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace40_nvls"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &mem_window3; + }; +}; diff --git a/boards/intel/adsp/intel_adsp_ace40_nvls_defconfig b/boards/intel/adsp/intel_adsp_ace40_nvls_defconfig new file mode 100644 index 00000000000..913d2a8c3e3 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace40_nvls_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/intel/adsp/twister.yaml b/boards/intel/adsp/twister.yaml index c5d8c9f2759..1882a85f9f6 100644 --- a/boards/intel/adsp/twister.yaml +++ b/boards/intel/adsp/twister.yaml @@ -56,6 +56,23 @@ variants: - zephyr testing: timeout_multiplier: 8 + intel_adsp/ace40/nvls: + toolchain: + - xt-clang + intel_adsp/ace40/nvl: + toolchain: + - xt-clang + intel_adsp/ace40/nvl/sim: + type: sim + toolchain: + - xt-clang + simulation: + - name: custom + exec: acesim + testing: + timeout_multiplier: 8 + intel_adsp/ace40: + twister: false intel_adsp/cavs25: toolchain: - xcc diff --git a/boards/intel/niosv_g/Kconfig.niosv_g b/boards/intel/niosv_g/Kconfig.niosv_g index 2d07c1b5e15..a90f3908e09 100644 --- a/boards/intel/niosv_g/Kconfig.niosv_g +++ b/boards/intel/niosv_g/Kconfig.niosv_g @@ -4,5 +4,3 @@ config BOARD_NIOSV_G select SOC_NIOSV_G - help - Intel FPGA Nios V/g General Purpose Processor diff --git a/boards/intel/niosv_m/Kconfig.niosv_m b/boards/intel/niosv_m/Kconfig.niosv_m index c7474b4b926..85aaa23d5b5 100644 --- a/boards/intel/niosv_m/Kconfig.niosv_m +++ b/boards/intel/niosv_m/Kconfig.niosv_m @@ -4,5 +4,3 @@ config BOARD_NIOSV_M select SOC_NIOSV_M - help - Intel FPGA NIOSV Microcontroller Core Processor diff --git a/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk b/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk index 603cdb55a67..8fdb860e1d6 100644 --- a/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk +++ b/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk @@ -3,5 +3,3 @@ config BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK select SOC_AGILEX5 - help - Intel SoC FPGA Development Kit (Agilex5) diff --git a/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk b/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk index 18fcd9d69e8..0d9f585f085 100644 --- a/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk +++ b/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk @@ -3,5 +3,3 @@ config BOARD_INTEL_SOCFPGA_AGILEX_SOCDK select SOC_AGILEX - help - Intel SoC FPGA Development Kit (Agilex) diff --git a/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk index cb62866b339..ce8c2fb9ed0 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk +++ b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk @@ -3,5 +3,3 @@ config BOARD_CYCLONEV_SOCDK select SOC_CYCLONEV - help - Intel Cyclone V Development Kit diff --git a/boards/kws/pico2_spe/pico2_spe.dtsi b/boards/kws/pico2_spe/pico2_spe.dtsi index 87211d91eff..899d22e7357 100644 --- a/boards/kws/pico2_spe/pico2_spe.dtsi +++ b/boards/kws/pico2_spe/pico2_spe.dtsi @@ -16,7 +16,6 @@ zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,code-partition = &code_partition; }; aliases { @@ -59,33 +58,6 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(4)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserved memory for an image definition block. The block is much - * smaller than 256 bytes, but in practice the linker places the vector - * table at a much larger alignment offset. - */ - image_def: partition@0 { - label = "image_def"; - reg = <0x00000000 0x100>; - read-only; - }; - - /* - * Usable flash. Starts at 0x100, after the image definition block. - * The partition size is 4MB minus the 0x100 bytes taken by the - * image definition. - */ - code_partition: partition@100 { - label = "code-partition"; - reg = <0x100 (DT_SIZE_M(4) - 0x100)>; - read-only; - }; - }; }; &uart0 { diff --git a/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig index 8bd68e35113..4da77bdb95c 100644 --- a/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig +++ b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig @@ -8,7 +8,6 @@ CONFIG_CONSOLE=y CONFIG_GPIO=y CONFIG_RESET=y CONFIG_SERIAL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000 CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/kws/pico_spe/pico_spe_defconfig b/boards/kws/pico_spe/pico_spe_defconfig index df003531af9..aaaa51cbdb9 100644 --- a/boards/kws/pico_spe/pico_spe_defconfig +++ b/boards/kws/pico_spe/pico_spe_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/lilygo/ttgo_tbeam/Kconfig b/boards/lilygo/ttgo_tbeam/Kconfig index c95a97a11aa..4ca06324705 100644 --- a/boards/lilygo/ttgo_tbeam/Kconfig +++ b/boards/lilygo/ttgo_tbeam/Kconfig @@ -8,3 +8,9 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD config GNSS_INIT_PRIORITY default 87 + +config MFD + default y if !MCUBOOT + +config REGULATOR + default y if !MCUBOOT diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig index 6b1097cdb38..a38e2caf524 100644 --- a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig +++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig @@ -6,5 +6,3 @@ CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_MFD=y -CONFIG_REGULATOR=y diff --git a/boards/lilygo/twatch_s3/twatch_s3_procpu.dts b/boards/lilygo/twatch_s3/twatch_s3_procpu.dts index b78676a8b0a..60987936335 100644 --- a/boards/lilygo/twatch_s3/twatch_s3_procpu.dts +++ b/boards/lilygo/twatch_s3/twatch_s3_procpu.dts @@ -20,6 +20,7 @@ watchdog0 = &wdt0; rtc = &pfc8563_rtc; pwm-led0 = &backlight_pwm; + fuel-gauge0 = &fuel_gauge; }; chosen { @@ -228,6 +229,10 @@ regulator-boot-off; }; }; + + fuel_gauge: fuel_gauge { + compatible = "x-powers,axp2101-fuel-gauge"; + }; }; }; diff --git a/boards/m5stack/m5stack_atom_lite/grove_connectors.dtsi b/boards/m5stack/m5stack_atom_lite/grove_connectors.dtsi index a2926d68eb2..f17a986d9be 100644 --- a/boards/m5stack/m5stack_atom_lite/grove_connectors.dtsi +++ b/boards/m5stack/m5stack_atom_lite/grove_connectors.dtsi @@ -15,4 +15,4 @@ }; }; -grove_i2c1: &i2c1 {}; +zephyr_i2c: &i2c1 {}; diff --git a/boards/m5stack/m5stack_atoms3/grove_connectors.dtsi b/boards/m5stack/m5stack_atoms3/grove_connectors.dtsi index 798c40cf296..7632ecca0aa 100644 --- a/boards/m5stack/m5stack_atoms3/grove_connectors.dtsi +++ b/boards/m5stack/m5stack_atoms3/grove_connectors.dtsi @@ -14,4 +14,4 @@ }; }; -grove_i2c1: &i2c1 {}; +zephyr_i2c: &i2c1 {}; diff --git a/boards/m5stack/m5stack_atoms3_lite/grove_connectors.dtsi b/boards/m5stack/m5stack_atoms3_lite/grove_connectors.dtsi index db98d8885dd..c4d8dd2fe1a 100644 --- a/boards/m5stack/m5stack_atoms3_lite/grove_connectors.dtsi +++ b/boards/m5stack/m5stack_atoms3_lite/grove_connectors.dtsi @@ -15,4 +15,4 @@ }; }; -grove_i2c1: &i2c1 {}; +zephyr_i2c: &i2c1 {}; diff --git a/boards/m5stack/m5stack_core2/grove_connectors.dtsi b/boards/m5stack/m5stack_core2/grove_connectors.dtsi index 3a49570382d..a4bdba36b8e 100644 --- a/boards/m5stack/m5stack_core2/grove_connectors.dtsi +++ b/boards/m5stack/m5stack_core2/grove_connectors.dtsi @@ -15,5 +15,5 @@ }; }; -grove_i2c: &i2c1 {}; +zephyr_i2c: &i2c1 {}; grove_uart: &uart1 {}; diff --git a/boards/m5stack/m5stack_cores3/grove_connectors.dtsi b/boards/m5stack/m5stack_cores3/grove_connectors.dtsi index 4139a48b867..ed77ff1768b 100644 --- a/boards/m5stack/m5stack_cores3/grove_connectors.dtsi +++ b/boards/m5stack/m5stack_cores3/grove_connectors.dtsi @@ -14,5 +14,5 @@ }; }; -grove_i2c: &i2c1 {}; +zephyr_i2c: &i2c1 {}; grove_uart: &uart2 {}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi index 1d4fd8c4a6f..38b07ce3df4 100644 --- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi @@ -32,6 +32,7 @@ rtc = &bm8563_rtc; sdhc0 = &sd0; led0 = &axp2101_led; + fuel-gauge0 = &fuel_gauge; }; lvgl_pointer { @@ -165,6 +166,10 @@ status = "okay"; x-powers,mode = "by-reg"; }; + + fuel_gauge: fuel_gauge { + compatible = "x-powers,axp2101-fuel-gauge"; + }; }; bm8563_rtc: bm8563@51 { diff --git a/boards/m5stack/m5stack_fire/Kconfig b/boards/m5stack/m5stack_fire/Kconfig new file mode 100644 index 00000000000..449207a6de4 --- /dev/null +++ b/boards/m5stack/m5stack_fire/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_M5STACK_FIRE_ESP32_PROCPU + default 256 if BOARD_M5STACK_FIRE_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_fire/Kconfig.defconfig b/boards/m5stack/m5stack_fire/Kconfig.defconfig new file mode 100644 index 00000000000..370bd5845ab --- /dev/null +++ b/boards/m5stack/m5stack_fire/Kconfig.defconfig @@ -0,0 +1,29 @@ +# M5Stack Core2 board configuration +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_FIRE_ESP32_PROCPU + +config KERNEL_MEM_POOL + default y + +config GPIO_HOGS_INIT_PRIORITY + default 70 + +config INPUT + default y + +configdefault LV_COLOR_16_SWAP + default y if LVGL + +# Increase initialization priority of MIPI DBI device, so that it initializes +# after the GPIO controller +if MIPI_DBI + +config MIPI_DBI_INIT_PRIORITY + default 82 + +endif # MIPI_DBI + +endif # BOARD_M5STACK_FIRE_ESP32_PROCPU diff --git a/boards/m5stack/m5stack_fire/Kconfig.m5stack_fire b/boards/m5stack/m5stack_fire/Kconfig.m5stack_fire new file mode 100644 index 00000000000..d0aa624c788 --- /dev/null +++ b/boards/m5stack/m5stack_fire/Kconfig.m5stack_fire @@ -0,0 +1,9 @@ +# M5Stack Fire board configuration + +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_FIRE + select SOC_ESP32_D0WD_V3 + select SOC_ESP32_PROCPU if BOARD_M5STACK_FIRE_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_M5STACK_FIRE_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_fire/board.cmake b/boards/m5stack/m5stack_fire/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/m5stack/m5stack_fire/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/m5stack/m5stack_fire/board.yml b/boards/m5stack/m5stack_fire/board.yml new file mode 100644 index 00000000000..48663ae2b25 --- /dev/null +++ b/boards/m5stack/m5stack_fire/board.yml @@ -0,0 +1,6 @@ +board: + name: m5stack_fire + full_name: Fire + vendor: m5stack + socs: + - name: esp32 diff --git a/boards/m5stack/m5stack_fire/doc/img/m5stack_fire.webp b/boards/m5stack/m5stack_fire/doc/img/m5stack_fire.webp new file mode 100644 index 00000000000..b5524f912d9 Binary files /dev/null and b/boards/m5stack/m5stack_fire/doc/img/m5stack_fire.webp differ diff --git a/boards/m5stack/m5stack_fire/doc/index.rst b/boards/m5stack/m5stack_fire/doc/index.rst new file mode 100644 index 00000000000..cf9faa32f1c --- /dev/null +++ b/boards/m5stack/m5stack_fire/doc/index.rst @@ -0,0 +1,151 @@ +.. zephyr:board:: m5stack_fire + +Overview +******** + +M5Stack Fire is an ESP32-based development board from M5Stack. + +M5Stack Fire features the following integrated components: + +- ESP32-D0WDQ6 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) +- PSRAM 8MB +- Flash 16MB +- LCD IPS TFT 2", 320x240 px screen (ILI9342C) +- Charger IP5306 +- Audio NS4148 amplifier (1W-092 speaker) +- USB CH9102F +- SD-Card slot +- Grove connector +- IMO 6-axis IMU MPU6886 +- MIC BSE3729 +- Battery 500mAh 3,7V +- Three physical buttons +- LED strips + +Functional Description +********************** + +The following table below describes the key components, interfaces, and controls +of the M5Stack Core2 board. + +.. _M5Core2 Schematic: https://m5stack-doc.oss-cn-shenzhen.aliyuncs.com/480/M5-Core-Schematic_20171206.pdf +.. _MPU-ESP32: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32_datasheet_en_v3.9.pdf +.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf +.. _LCD-ILI9342C: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ILI9342C-ILITEK.pdf +.. _IP5306: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/IIC_IP5306_REG_V1.4_cn.pdf + ++------------------+------------------------------------------------------------------------+-----------+ +| Key Component | Description | Status | ++==================+========================================================================+===========+ +| ESP32-D0WDQ6-V2 | This `MPU-ESP32`_ module provides complete Wi-Fi and Bluetooth | supported | +| module | functionalities and integrates a 16-MB SPI flash. | | ++------------------+------------------------------------------------------------------------+-----------+ +| USB Port | USB interface. Power supply for the board as well as the | supported | +| | communication interface between a computer and the board. | | ++------------------+------------------------------------------------------------------------+-----------+ +| Power Switch | Power on/off button. | supported | ++------------------+------------------------------------------------------------------------+-----------+ +| General purpose | Three buttons on the front face of the device accesible using the GPIO | supported | +| buttons | interface. | | ++------------------+------------------------------------------------------------------------+-----------+ +| LCD screen | Built-in LCD TFT display \(`LCD-ILI9342C`_, 2", 320x240 px\) | supported | +| | controlled via SPI interface | | ++------------------+------------------------------------------------------------------------+-----------+ +| SD-Card slot | SD-Card connection via SPI-mode. | supported | ++------------------+------------------------------------------------------------------------+-----------+ +| 6-axis IMU | The `MPU-6886`_ is a 6-axis motion tracker (6DOF IMU) device that | supported | +| MPU6886 | combines a 3-axis gyroscope and a 3-axis accelerometer. | | ++------------------+------------------------------------------------------------------------+-----------+ +| Grove port | Used to interface with the many available modules and sensors. | supported | ++------------------+------------------------------------------------------------------------+-----------+ +| Built-in speaker | 1W speaker for analog audio output. | supported | ++------------------+------------------------------------------------------------------------+-----------+ +| Built-in | The BSE3729 analog microphone. | todo | +| microphone | | | ++------------------+------------------------------------------------------------------------+-----------+ +| LED strip | LED strips on the side of the device. | todo | ++------------------+------------------------------------------------------------------------+-----------+ +| Battery-support | Charging is supported automatically via the `IP5306`_. But there is no | todo | +| | possibility to query current battery status. | | ++------------------+------------------------------------------------------------------------+-----------+ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Start Application Development +***************************** + +Before powering up your M5Stack Fire, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +.. zephyr:board-supported-runners:: + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_fire/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_fire`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_fire/esp32/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_fire + +Debugging +--------- + +M5Stack Fire debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5Stack-Fire schematic `_ (PDF) +- `M5Stack-Fire docs `_ +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/m5stack/m5stack_fire/grove_connectors.dtsi b/boards/m5stack/m5stack_fire/grove_connectors.dtsi new file mode 100644 index 00000000000..6e756fc7824 --- /dev/null +++ b/boards/m5stack/m5stack_fire/grove_connectors.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2023 Joel Guittet + * Copyright (c) 2023 Martin Kiepfer + * Copyright (c) 2025 Jakub Novák + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + grove_header_a: grove_header_a { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 22 0>, /* D0/SCL/RX */ + <1 0 &gpio1 21 0>; /* D1/SDA/TX */ + }; + + grove_header_b: grove_header_b { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 5 0>, /* D0/SCL/RX */ + <1 0 &gpio0 26 0>; /* D1/SDA/TX */ + }; + + grove_header_c: grove_header_c { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 17 0>, /* D0/SCL/RX */ + <1 0 &gpio0 16 0>; /* D1/SDA/TX */ + }; +}; + +grove_uart: &uart1 {}; diff --git a/boards/m5stack/m5stack_fire/m5stack_fire-pinctrl.dtsi b/boards/m5stack/m5stack_fire/m5stack_fire-pinctrl.dtsi new file mode 100644 index 00000000000..7b4acb61ff3 --- /dev/null +++ b/boards/m5stack/m5stack_fire/m5stack_fire-pinctrl.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) + * Copyright (c) 2023 Martin Kiepfer + * Copyright (c) 2025 Jakub Novák + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_tx_gpio1: uart0_tx_gpio1 { + pinmux = ; + }; + + uart0_rx_gpio3: uart0_rx_gpio3 { + pinmux = ; + bias-pull-up; + }; + + uart1_rx_gpio33: uart1_rx_gpio33 { + pinmux = ; + }; + + uart2_rx_gpio13: uart2_rx_gpio13 { + pinmux = ; + }; + + uart2_tx_gpio14: uart2_rx_gpio14 { + pinmux = ; + }; + + uart1_tx_gpio32: uart1_tx_gpio32 { + pinmux = ; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + ; + }; + + group2 { + pinmux = , ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + drive-open-drain; + output-high; + }; + }; + + ledc0_default: ledc0_default { + group1 { + pinmux = ; + output-enable; + }; + + group2 { + pinmux = ; + output-enable; + }; + }; +}; diff --git a/boards/m5stack/m5stack_fire/m5stack_fire_appcpu.dts b/boards/m5stack/m5stack_fire/m5stack_fire_appcpu.dts new file mode 100644 index 00000000000..7c4890d1818 --- /dev/null +++ b/boards/m5stack/m5stack_fire/m5stack_fire_appcpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "M5Stack Fire APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_fire/m5stack_fire_appcpu.yaml b/boards/m5stack/m5stack_fire/m5stack_fire_appcpu.yaml new file mode 100644 index 00000000000..97b543e2920 --- /dev/null +++ b/boards/m5stack/m5stack_fire/m5stack_fire_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_fire/esp32/appcpu +name: M5Stack Fire APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_fire/m5stack_fire_appcpu_defconfig b/boards/m5stack/m5stack_fire/m5stack_fire_appcpu_defconfig new file mode 100644 index 00000000000..48546641cad --- /dev/null +++ b/boards/m5stack/m5stack_fire/m5stack_fire_appcpu_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/m5stack/m5stack_fire/m5stack_fire_procpu.dts b/boards/m5stack/m5stack_fire/m5stack_fire_procpu.dts new file mode 100644 index 00000000000..ca48714bbc7 --- /dev/null +++ b/boards/m5stack/m5stack_fire/m5stack_fire_procpu.dts @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2023 Martin Kiepfer + * Copyright (c) 2025 Jakub Novák + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_fire-pinctrl.dtsi" +#include "grove_connectors.dtsi" +#include "m5stack_mbus_connectors.dtsi" +#include +#include +#include + +/ { + model = "M5Stack Fire PROCPU"; + compatible = "m5stack,fire"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + accel0 = &mpu6886; + sw0 = &button0; + pwm0 = &ledc0; + lcd-bg = &lcd_bg; + }; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,display = &ili9342c; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + pwm { + compatible = "pwm-leds"; + + lcd_bg: lcd_bg { + label = "PWM LED0"; + /* The cycle duration is taken from the ILI9342c spec section 8.3.15 */ + pwms = <&ledc0 7 PWM_KHZ(16000 / 256) PWM_POLARITY_NORMAL>; + }; + + speaker: speaker { + label = "PWM speaker"; + pwms = <&ledc0 8 1000 PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + label = "button left"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + label = "button middle"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + label = "button right"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + label = "button 2"; + zephyr,code = ; + }; + + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9342c: ili9342c@0 { + status = "okay"; + compatible = "ilitek,ili9342c"; + mipi-max-frequency = <30000000>; + reg = <0>; + pixel-format = ; + display-inversion; + width = <320>; + height = <240>; + rotation = <0>; + }; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_M(16)>; +}; + +&psram0 { + size = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_gpio33 &uart1_tx_gpio32>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + scl-timeout-us = <0>; + pinctrl-names = "default"; + + mpu6886: mpu6886@68 { + status = "okay"; + compatible = "invensense,mpu6050"; + reg = <0x68>; + }; +}; + +&spi3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + dma-enabled; + clock-frequency = <20000000>; + cs-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>, <&gpio0 4 GPIO_ACTIVE_LOW>; + + sd0: sd@1 { + status = "okay"; + compatible = "zephyr,sdhc-spi-slot"; + reg = <1>; + spi-max-frequency = <20000000>; + mmc { + status = "okay"; + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + }; + + }; +}; + +&ledc0 { + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hispeed0@7 { + reg = <0x7>; + timer = <0>; + }; + + hispeed1@8 { + reg = <0x8>; + timer = <0>; + }; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_fire/m5stack_fire_procpu.yaml b/boards/m5stack/m5stack_fire/m5stack_fire_procpu.yaml new file mode 100644 index 00000000000..caea33c2525 --- /dev/null +++ b/boards/m5stack/m5stack_fire/m5stack_fire_procpu.yaml @@ -0,0 +1,16 @@ +identifier: m5stack_fire/esp32/procpu +name: M5Stack Fire PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pinmux + - nvs + - pwm +vendor: m5stack diff --git a/boards/m5stack/m5stack_fire/m5stack_fire_procpu_defconfig b/boards/m5stack/m5stack_fire/m5stack_fire_procpu_defconfig new file mode 100644 index 00000000000..bff67f69b1a --- /dev/null +++ b/boards/m5stack/m5stack_fire/m5stack_fire_procpu_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/m5stack/m5stack_fire/m5stack_mbus_connectors.dtsi b/boards/m5stack/m5stack_fire/m5stack_mbus_connectors.dtsi new file mode 100644 index 00000000000..6e454f07a69 --- /dev/null +++ b/boards/m5stack/m5stack_fire/m5stack_mbus_connectors.dtsi @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Martin Kiepfer + * Copyright (c) 2025 Jakub Novák + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + m5stack_mbus_header: m5stack_mbus_connector { + compatible = "m5stack,mbus-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = /* 0 GND */ + <1 0 &gpio1 4 0>, /* ADC0 */ + /* 2 GND */ + <3 0 &gpio1 5 0>, /* ADC1 */ + /* 4 GND */ + /* 5 RESET */ + <6 0 &gpio0 23 0>, /* MOSI */ + <7 0 &gpio0 25 0>, /* DAC0 */ + <8 0 &gpio0 19 0>, /* MISO */ + <9 0 &gpio0 26 0>, /* DAC1 */ + <10 0 &gpio0 18 0>, /* SCK */ + /* 11 3.3V */ + <12 0 &gpio0 3 0>, /* RXD0 */ + <13 0 &gpio0 1 0>, /* TXD0 */ + <14 0 &gpio0 16 0>, /* RXD1 */ + <15 0 &gpio0 17 0>, /* TXD1 */ + <16 0 &gpio0 21 0>, /* SDA */ + <17 0 &gpio0 22 0>, /* SCL */ + <18 0 &gpio0 2 0>, /* GPIO */ + <19 0 &gpio0 5 0>, /* GPIO */ + <20 0 &gpio0 12 0>, /* IIS SK */ + <21 0 &gpio0 13 0>, /* IIS WS */ + <22 0 &gpio0 15 0>, /* IIS OUT */ + <23 0 &gpio0 0 0>, /* IIS MK */ + /* 24 HPWR */ + <25 0 &gpio1 3 0>; /* IIS IN */ + /* 26 HPWR */ + /* 27 5V */ + /* 28 HPWR */ + /* 29 BAT */ + }; +}; + +m5stack_mbus_i2c0: &i2c0 {}; +m5stack_mbus_uart0: &uart1 {}; +m5stack_mbus_uart1: &uart2 {}; +m5stack_mbus_spi: &spi3 {}; diff --git a/boards/m5stack/m5stack_fire/support/openocd.cfg b/boards/m5stack/m5stack_fire/support/openocd.cfg new file mode 100644 index 00000000000..338e6e4e6ea --- /dev/null +++ b/boards/m5stack/m5stack_fire/support/openocd.cfg @@ -0,0 +1,5 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +source [find interface/ftdi/esp32_devkitj_v1.cfg] +source [find target/esp32.cfg] diff --git a/boards/madmachine/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts index cd398cc5234..d9161092353 100644 --- a/boards/madmachine/mm_feather/mm_feather.dts +++ b/boards/madmachine/mm_feather/mm_feather.dts @@ -60,7 +60,7 @@ reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = ; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts index 54ad772396c..d32a3df63a0 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.dts +++ b/boards/madmachine/mm_swiftio/mm_swiftio.dts @@ -60,7 +60,7 @@ reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = ; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; diff --git a/boards/mediatek/mt8195/Kconfig.mt8195 b/boards/mediatek/mt8195/Kconfig.mt8195 index 0fb211185c9..f054a77d261 100644 --- a/boards/mediatek/mt8195/Kconfig.mt8195 +++ b/boards/mediatek/mt8195/Kconfig.mt8195 @@ -3,5 +3,3 @@ config BOARD_MT8195 select SOC_MT8195 - help - Board with Mediatek MT8195 Audio DSP diff --git a/boards/mediatek/mt8195/mt8195_adsp.dts b/boards/mediatek/mt8195/mt8195_adsp.dts index 53346746041..8b142221c6b 100644 --- a/boards/mediatek/mt8195/mt8195_adsp.dts +++ b/boards/mediatek/mt8195/mt8195_adsp.dts @@ -46,12 +46,12 @@ #interrupt-cells = <3>; }; - intc1: intc@10680130 { + intc1: intc@10803130 { compatible = "mediatek,adsp_intc"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x10680130 4>; - status-reg = <0x10680150>; + reg = <0x10803130 4>; + status-reg = <0x10803150>; interrupts = <1 0 0>; mask = <0x3ffffff0>; interrupt-parent = <&core_intc>; diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi index 6ab77f6ae48..6397b98f659 100644 --- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi @@ -6,8 +6,8 @@ /dts-v1/; -#include -#include +#include +#include &ps2_clk0b_gpio007 { drive-open-drain; diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853-pinctrl.dtsi b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853-pinctrl.dtsi index 6ab77f6ae48..6397b98f659 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853-pinctrl.dtsi +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853-pinctrl.dtsi @@ -6,8 +6,8 @@ /dts-v1/; -#include -#include +#include +#include &ps2_clk0b_gpio007 { drive-open-drain; diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts index fbc1aa677af..c7e43293101 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts @@ -131,10 +131,6 @@ pinctrl-names = "default"; }; -&timer5 { - status = "okay"; -}; - &ps2_0 { status = "okay"; pinctrl-0 = <&ps2_clk0b_gpio007 &ps2_dat0b_gpio010>; diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts index bc2ad391664..15019a36e85 100644 --- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts @@ -6,8 +6,8 @@ /dts-v1/; -#include -#include +#include +#include / { model = "Microchip MEC172XEVB_ASSY6906 evaluation board"; @@ -285,7 +285,3 @@ pinctrl-1 = <&ps2_clk0a_gpio114_sleep &ps2_dat0a_gpio115_sleep>; pinctrl-names = "default", "sleep"; }; - -&timer5 { - status = "okay"; -}; diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts index e5d7e888baa..253d799f923 100644 --- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts @@ -6,8 +6,8 @@ /dts-v1/; -#include -#include +#include +#include / { model = "Microchip MEC172XMODULAR_ASSY6930 evaluation board"; @@ -262,7 +262,3 @@ pinctrl-0 = <&ps2_clk0a_gpio114 &ps2_dat0a_gpio115>; pinctrl-names = "default"; }; - -&timer5 { - status = "okay"; -}; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts index a2b52bd505c..0b885f29dc0 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include / { @@ -17,7 +17,6 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; - rtimer-busy-wait-timer = &timer5; }; power-states { @@ -48,12 +47,6 @@ /* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ &rtimer { - compatible = "microchip,mec5-ktimer"; - status = "okay"; -}; - -/* We chose 32-bit basic timer 5 for use by ktimer */ -&timer5 { status = "okay"; }; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts index fc4eb98d568..b395ec21bc4 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include / { @@ -17,7 +17,6 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; - rtimer-busy-wait-timer = &timer5; }; power-states { @@ -48,12 +47,6 @@ /* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ &rtimer { - compatible = "microchip,mec5-ktimer"; - status = "okay"; -}; - -/* We chose 32-bit basic timer 5 for use by ktimer */ -&timer5 { status = "okay"; }; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts index 1187fef8a07..724088b2d48 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include / { @@ -17,7 +17,6 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; - rtimer-busy-wait-timer = &timer5; }; power-states { @@ -48,12 +47,6 @@ /* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ &rtimer { - compatible = "microchip,mec5-ktimer"; - status = "okay"; -}; - -/* We chose 32-bit basic timer 5 for use by ktimer */ -&timer5 { status = "okay"; }; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts index b2e7c570cc6..ae51d202855 100644 --- a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include / { @@ -17,7 +17,6 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,console = &uart1; - rtimer-busy-wait-timer = &timer5; }; power-states { @@ -48,12 +47,6 @@ /* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ &rtimer { - compatible = "microchip,mec5-ktimer"; - status = "okay"; -}; - -/* We chose 32-bit basic timer 5 for use by ktimer */ -&timer5 { status = "okay"; }; diff --git a/boards/microchip/sam/sam_e54_xpro/Kconfig.sam_e54_xpro b/boards/microchip/sam/sam_e54_xpro/Kconfig.sam_e54_xpro new file mode 100644 index 00000000000..816c623df02 --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/Kconfig.sam_e54_xpro @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM_E54_XPRO + select SOC_ATSAME54P20A diff --git a/boards/microchip/sam/sam_e54_xpro/board.cmake b/boards/microchip/sam/sam_e54_xpro/board.cmake new file mode 100644 index 00000000000..82216ececa0 --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/board.cmake @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/microchip/sam/sam_e54_xpro/board.yml b/boards/microchip/sam/sam_e54_xpro/board.yml new file mode 100644 index 00000000000..1007736ff6c --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: sam_e54_xpro + full_name: SAM E54 Xplained Pro + vendor: microchip + socs: + - name: atsame54p20a diff --git a/boards/microchip/sam/sam_e54_xpro/doc/img/sam_e54_xpro.webp b/boards/microchip/sam/sam_e54_xpro/doc/img/sam_e54_xpro.webp new file mode 100644 index 00000000000..bd40d45bb7e Binary files /dev/null and b/boards/microchip/sam/sam_e54_xpro/doc/img/sam_e54_xpro.webp differ diff --git a/boards/microchip/sam/sam_e54_xpro/doc/index.rst b/boards/microchip/sam/sam_e54_xpro/doc/index.rst new file mode 100644 index 00000000000..57c9b78478d --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/doc/index.rst @@ -0,0 +1,94 @@ +.. zephyr:board:: sam_e54_xpro + +Overview +******** + +The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM E54 Cortex®-M4F processor-based +microcontrollers. The kit includes Microchip’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +Hardware +******** + +- ATSAME54P20A ARM Cortex-M4F processor at 120 MHz +- 32.768 kHz crystal oscillator +- 12 MHz crystal oscillator +- 1024 KiB flash memory and 256 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console +- One QTouch® PTC button +- 32 MiB QSPI Flash +- ATECC508 CryptoAuthentication™ device +- AT24MAC402 serial EEPROM with EUI-48™ MAC address +- Ethernet + + - RJ45 connector with built-in magnetics + - KSZ8091RNA PHY + - 10Base-T/100Base-TX IEE 802.3 compliant Ethernet transceiver + +- USB interface, host, and device +- SD/SDIO card connector + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The `SAM E54 Xplained Pro User Guide`_ has detailed information about board connections. + +Programming and Debugging +************************* + +The SAM E54 Xplained Pro features an on-board Microchip Embedded Debugger (EDBG), +which provides both a standard debug interface and a virtual serial port used as the Zephyr console. +SERCOM2 of the ATSAME54P20A MCU is configured as a USART for console output. + +#. Connect the board to your host machine using the debug USB port. + +#. Open a terminal and start a serial console on the corresponding port. + On Linux, this is typically ``/dev/ttyACM0``. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Build and flash the Zephyr ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_e54_xpro + :goals: flash + :compact: + +#. Observe output on the terminal. If everything is set up correctly, you should see: + + .. code-block:: console + + Hello World! same_54_xpro + +References +********** + +SAM E54 Product Page: + https://www.microchip.com/en-us/product/ATSAME54P20A + +SAM E54 Xplained Pro evaluation kit Page: + https://www.microchip.com/en-us/development-tool/ATSAME54-XPRO + +.. _SAM E54 Xplained Pro User Guide: + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/UserGuides/70005321A.pdf diff --git a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi new file mode 100644 index 00000000000..05798b46d3e --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + sercom2_uart_default: sercom2_uart_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts new file mode 100644 index 00000000000..025d49b64e9 --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "sam_e54_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM E54 Xplained Pro"; + compatible = "same54,xpro", "microchip,atsame54p20a", "microchip,same54"; + + chosen { + zephyr,console = &sercom2; + zephyr,shell-uart = &sercom2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&sercom2 { + status = "okay"; + compatible = "microchip,sercom-g1-uart"; + #address-cells = <1>; + #size-cells = <0>; + + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + stop-bits = "1"; + + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom2_uart_default>; + pinctrl-names = "default"; +}; diff --git a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml new file mode 100644 index 00000000000..d349dbd3384 --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +identifier: sam_e54_xpro +name: SAM E54 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr +flash: 1024 +ram: 256 +supported: + - pinctrl + - shell + - uart +vendor: microchip diff --git a/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro_defconfig b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro_defconfig new file mode 100644 index 00000000000..ce22ecc682d --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/sam_e54_xpro_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/microchip/sam/sam_e54_xpro/support/openocd.cfg b/boards/microchip/sam/sam_e54_xpro/support/openocd.cfg new file mode 100644 index 00000000000..a4713f87dbd --- /dev/null +++ b/boards/microchip/sam/sam_e54_xpro/support/openocd.cfg @@ -0,0 +1,25 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 +source [find interface/cmsis-dap.cfg] +transport select swd + +# chip name +set CHIPNAME same54p20a +set ENDIAN little +set CPUTAPID 0x0bc11477 + +source [find target/atsame5x.cfg] + +reset_config none +cortex_m reset_config sysresetreq + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts index 82648923842..093b2a72b42 100644 --- a/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts +++ b/boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts @@ -9,12 +9,20 @@ #include #include #include +#include +#include +#include #include / { model = "SAMA7G54-EK board"; compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; + aliases { + led0 = &led_green; + sw0 = &button_user; + }; + chosen { zephyr,sram = &ddram; zephyr,console = &usart3; @@ -35,6 +43,37 @@ compatible = "ddram"; reg = <0x60000000 DT_SIZE_M(512)>; }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led_red: red { + label = "red"; + gpios = <&piob 8 GPIO_ACTIVE_HIGH>; + }; + + led_green: green { + label = "green"; + gpios = <&pioa 13 GPIO_ACTIVE_HIGH>; + }; + + led_blue: blue { + label = "blue"; + gpios = <&piod 20 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + status = "okay"; + + button_user: button_0 { + label = "PB_USER"; + gpios = <&pioa 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; }; &flx3 { @@ -49,6 +88,37 @@ }; }; +&flx8 { + mchp,flexcom-mode = ; + status = "okay"; + + i2c8: i2c8@600 { + pinctrl-0 = <&pinctrl_i2c8_default>; + pinctrl-names = "default"; + status = "okay"; + + eeprom0: eeprom0@52 { + compatible = "atmel,24mac02e4", "atmel,at24"; + reg = <0x52>; + address-width = <8>; + pagesize = <16>; + size = <256>; + timeout = <5>; + status = "okay"; + }; + + eeprom1: eeprom1@53 { + compatible = "atmel,24mac02e4", "atmel,at24"; + reg = <0x53>; + address-width = <8>; + pagesize = <16>; + size = <256>; + timeout = <5>; + status = "okay"; + }; + }; +}; + &pinctrl { pinctrl_flx3_default: flx3_default { group1 { @@ -57,6 +127,14 @@ bias-pull-up; }; }; + + pinctrl_i2c8_default: i2c8_default { + group1 { + pinmux = , + ; + bias-disable; + }; + }; }; &pit64b0 { diff --git a/boards/native/common/natsim_config.cmake b/boards/native/common/natsim_config.cmake index d9decf2cacd..6345ef6cd6e 100644 --- a/boards/native/common/natsim_config.cmake +++ b/boards/native/common/natsim_config.cmake @@ -7,8 +7,15 @@ get_property(CCACHE GLOBAL PROPERTY RULE_LAUNCH_COMPILE) target_link_options(native_simulator INTERFACE "-T ${ZEPHYR_BASE}/boards/native/common/natsim_linker_script.ld") +if(SYSROOT_DIR) + message(NOTICE "Appending --sysroot=${SYSROOT_DIR} to native_simulator") + target_compile_options(native_simulator INTERFACE "--sysroot=${SYSROOT_DIR}") + target_link_options(native_simulator INTERFACE "--sysroot=${SYSROOT_DIR}") +endif() + set(nsi_config_content ${nsi_config_content} + "NSI_AR:=${CMAKE_AR}" "NSI_BUILD_OPTIONS:=$,\ >" "NSI_BUILD_PATH:=${zephyr_build_path}/NSI" "NSI_CC:=${CCACHE} ${CMAKE_C_COMPILER}" diff --git a/boards/native/common/sdl/CMakeLists.txt b/boards/native/common/sdl/CMakeLists.txt index 0e20283324c..fb6c7bd559e 100644 --- a/boards/native/common/sdl/CMakeLists.txt +++ b/boards/native/common/sdl/CMakeLists.txt @@ -7,20 +7,10 @@ zephyr_library_compile_definitions(NO_POSIX_CHEATS) find_package(PkgConfig REQUIRED) pkg_search_module(SDL2 REQUIRED sdl2) -if (CONFIG_NATIVE_APPLICATION) - zephyr_link_libraries(${SDL2_LIBRARIES}) - zephyr_include_directories(${SDL2_INCLUDE_DIRS}) - zephyr_compile_options(${SDL2_CFLAGS_OTHER}) -else() - list(TRANSFORM SDL2_LIBRARIES PREPEND "-l" OUTPUT_VARIABLE SDL2_LIBRARIES_OPTION) - target_link_options(native_simulator INTERFACE "${SDL2_LIBRARIES_OPTION}") - list(TRANSFORM SDL2_INCLUDE_DIRS PREPEND "-I" OUTPUT_VARIABLE SDL2_INCLUDE_DIRS_OPTION) - target_compile_options(native_simulator INTERFACE "${SDL2_INCLUDE_DIRS_OPTION}" ${SDL2_CFLAGS_OTHER}) -endif() +list(TRANSFORM SDL2_LIBRARIES PREPEND "-l" OUTPUT_VARIABLE SDL2_LIBRARIES_OPTION) +target_link_options(native_simulator INTERFACE "${SDL2_LIBRARIES_OPTION}") +list(TRANSFORM SDL2_INCLUDE_DIRS PREPEND "-I" OUTPUT_VARIABLE SDL2_INCLUDE_DIRS_OPTION) +target_compile_options(native_simulator INTERFACE "${SDL2_INCLUDE_DIRS_OPTION}" ${SDL2_CFLAGS_OTHER}) zephyr_library_sources(sdl_events.c) -if (CONFIG_NATIVE_APPLICATION) - zephyr_library_sources(sdl_events_bottom.c) -else() - target_sources(native_simulator INTERFACE sdl_events_bottom.c) -endif() +target_sources(native_simulator INTERFACE sdl_events_bottom.c) diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst index 6b6a5a5e10e..38b730a5f44 100644 --- a/boards/native/doc/arch_soc.rst +++ b/boards/native/doc/arch_soc.rst @@ -63,15 +63,11 @@ This port is designed and tested to run in Linux. .. note:: - The 32 bit version of this port does not directly work in the old Windows Subsystem - for Linux (WSL1) because WSL1 does not support native 32-bit binaries. - You may want to consider WSL2, or, if using :ref:`native_sim `, - you can also just use the ``native_sim/native/64`` - target: Check :ref:`32 and 64bit versions`. - Otherwise `with some tinkering - `_ it - should be possible to make it work. - + To use it in Windows, you will need a Virtual Machine running a Linux guest. + You can use WSL 2 (Windows Subsystem for Linux v2), or another VM running your preferred Linux + distribution. + Note: The old WSL 1 is very limited and cannot run 32-bit binaries like the default 32-bit + native_sim build configuration. .. _posix_arch_limitations: @@ -304,13 +300,6 @@ side-effects. Architecture and design *********************** -.. note:: - - This section does not describe anymore the old - :kconfig:option:`CONFIG_NATIVE_APPLICATION` based architecture. - It only describes the new native simulator based architecture used by targets built with the - :kconfig:option:`CONFIG_NATIVE_LIBRARY` option. - .. note:: This description applies to the boards on the tree, diff --git a/boards/native/doc/bsim_boards_design.rst b/boards/native/doc/bsim_boards_design.rst index b128baba7a2..e09deed2cc0 100644 --- a/boards/native/doc/bsim_boards_design.rst +++ b/boards/native/doc/bsim_boards_design.rst @@ -8,6 +8,7 @@ Bsim boards * :ref:`Simulated nRF52833 (nrf52_bsim)` * :ref:`Simulated nRF5340 (nrf5340bsim)` * :ref:`Simulated nRF54L15 (nrf54l15bsim)` +* :ref:`Simulated nRF54LM20 (nrf54lm20bsim)` .. contents:: Table of contents :depth: 2 @@ -363,7 +364,7 @@ Other considerations typically x86. x86 is little endian, which is typically also the case for the target architecture. If this is not the case, embedded code which works in one may not work in the other due to endianness bugs. - Note that Zephyr code is be written to support both big and little endian. + Note that Zephyr's code should be written to support both big and little endian. - WordSize: The bsim targets, as well as normal embedded targets are 32 bit targets. In the case of the bsim targets this is done by explicitly targeting x86 (ILP32 ABI) instead of x86_64. This is done purposefully to provide more diff --git a/boards/native/doc/layering.svg b/boards/native/doc/layering.svg deleted file mode 100644 index 54677195e31..00000000000 --- a/boards/native/doc/layering.svg +++ /dev/null @@ -1,139 +0,0 @@ - - - - - - - - - - - - - - Page-6 - - - Sheet.1 - CPU/SOC - - - - CPU/SOC - - Sheet.2 - HW peripherals - - - - HW peripherals - - Sheet.3 - Drivers - - - - Drivers - - Sheet.4 - Architecture/SOC dependent layer - - - - Architecture/SOC dependent layer - - Sheet.5 - Zephyr Kernel - - - - ZephyrKernel - - Sheet.6 - Application - - - - Application - - Sheet.7 - Host OS Kernel (i.e. Linux) - - - - Host OS Kernel (i.e. Linux) - - Sheet.8 - HW models / host HW API adaptation - - - - HW models / host HW API adaptation - - Sheet.9 - Drivers - - - - Drivers - - Sheet.10 - POSIX Arch - - - - POSIXArch - - Sheet.11 - Zephyr Kernel - - - - ZephyrKernel - - Sheet.12 - Application - - - - Application - - Sheet.13 - Normal Zephyr layering - - - - Normal Zephyr layering - - Sheet.14 - native_sim & _bsim boards Zephyr layering - - - - native_sim & _bsim boards Zephyr layering - - diff --git a/boards/native/native_sim/CMakeLists.txt b/boards/native/native_sim/CMakeLists.txt index 014b0bb049c..613b7df4f82 100644 --- a/boards/native/native_sim/CMakeLists.txt +++ b/boards/native/native_sim/CMakeLists.txt @@ -15,11 +15,7 @@ zephyr_library_sources( if(CONFIG_NATIVE_SIM_REBOOT) zephyr_library_sources(reboot.c) - if(CONFIG_NATIVE_LIBRARY) - target_sources(native_simulator INTERFACE reboot_bottom.c) - else() - zephyr_library_sources(reboot_bottom.c) - endif() + target_sources(native_simulator INTERFACE reboot_bottom.c) endif() zephyr_include_directories( diff --git a/boards/native/native_sim/Kconfig b/boards/native/native_sim/Kconfig index b04c6374691..15950566594 100644 --- a/boards/native/native_sim/Kconfig +++ b/boards/native/native_sim/Kconfig @@ -8,7 +8,6 @@ config BOARD_NATIVE_SIM select NATIVE_LIBRARY select NATIVE_SIM_TIMER select 64BIT if BOARD_NATIVE_SIM_NATIVE_64 - imply BOARD_NATIVE_POSIX if NATIVE_SIM_NATIVE_POSIX_COMPAT help Native simulator (Single Core) Will produce a console Linux process which can be executed natively. @@ -17,16 +16,6 @@ if BOARD_NATIVE_SIM comment "Native Simular (Single Core) options" -config NATIVE_SIM_NATIVE_POSIX_COMPAT - bool "Pretend to be a native_posix board" - select DEPRECATED - help - When this option is set the native_sim board will pretend to be - a native_posix board from kconfig point of view, to allow using it directly with - code which was meant for the native_posix board and checks for the macro - CONFIG_BOARD_NATIVE_POSIX, or requires other kconfig options which depend on it. - This option is deprecated and will be removed in Zephyr v4.3 - config NATIVE_SIM_SLOWDOWN_TO_REAL_TIME bool "Slow down execution to real time" default n if ARCH_POSIX_LIBFUZZER @@ -39,10 +28,6 @@ config NATIVE_SIM_SLOWDOWN_TO_REAL_TIME case the zephyr kernel and application cannot tell the difference unless they interact with some other driver/device which runs at real time. -# This option definition exists only to enable NATIVE_SIM_NATIVE_POSIX_COMPAT -config BOARD_NATIVE_POSIX - bool - config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME bool "Slow down execution to real time (native_posix compat)" select NATIVE_SIM_SLOWDOWN_TO_REAL_TIME diff --git a/boards/native/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst index 8cdffc32526..1c085cc09c1 100644 --- a/boards/native/native_sim/doc/index.rst +++ b/boards/native/native_sim/doc/index.rst @@ -1,7 +1,7 @@ .. _native_sim: -Native simulator - native_sim -############################# +native_sim +########## .. contents:: :depth: 1 @@ -504,9 +504,12 @@ The following peripherals are currently provided with this board: enabled with :kconfig:option:`CONFIG_CAN_NATIVE_LINUX` and configured with the device tree binding :dtcompatible:`zephyr,native-linux-can`. - It is possible to specify which CAN interface will be used by the app using the ``--can-if`` - command-line option. This option overrides **every** Linux SocketCAN driver instance to use the specified - interface. + By default, the native simulator expects a SocketCAN network device called ``zcan0``. It is + possible to specify which SocketCAN network device will be used by the app by using the + ``--can-if`` command-line option. This option overrides **every** Linux SocketCAN driver instance + to use the specified interface. + + SocketCAN support can be enabled by using the :ref:`snippet-socketcan-native-sim`. .. _native_ptty_uart: @@ -544,14 +547,25 @@ where :file:`/dev/{}` should be replaced with the actual PTY device. You may also chose to automatically attach a terminal emulator to any of these UARTs. To automatically attach one to all these UARTs, pass the command line option ``-attach_uart`` to the -executable. To automatically attach one to a single UART use ``-_attach_uart`` +executable. To automatically attach one to a single UART use ``-_attach_uart``. The command used for attaching to the new shell can be set for all UARTs with the command line option ``-attach_uart_cmd=<"cmd">``, or for each individual UART with ``-_attach_uart_cmd``. Where the default command is given by :kconfig:option:`CONFIG_UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD`. Note that the default command assumes both ``xterm`` and ``screen`` are installed in the system. -This driver only supports poll mode. Interrupt and async mode are not supported. +Note that these ``uart_cmd`` commands can be effectively any shell command including lists of +commands. Therefore it is possible to invoke any other script or program from it. +Those commands will be run right after the PTY is created. +For example, if one wanted to create a link to the newly created PTY, and have it removed when the +program ends, one could do: + +.. code-block:: console + + $ zephyr.exe --uart_attach_uart_cmd='ln -s %s /tmp/somename' ; rm /tmp/somename + +This driver supports poll mode or async mode with :kconfig:option:`CONFIG_UART_ASYNC_API`. +Interrupt mode is not supported. Neither runtime configuration or line control are supported. .. _native_tty_uart: diff --git a/boards/native/nrf_bsim/doc/nrf52_bsim.rst b/boards/native/nrf_bsim/doc/nrf52_bsim.rst index 3c94c82b534..a23de79af7e 100644 --- a/boards/native/nrf_bsim/doc/nrf52_bsim.rst +++ b/boards/native/nrf_bsim/doc/nrf52_bsim.rst @@ -12,7 +12,7 @@ NRF52 simulated board (BabbleSim) Overview ******** -To allow simulating a nRF52833 SOC a Zephyr target boards is provided: the +To allow simulating a nRF52833 SOC, a Zephyr target board is provided: the nrf52_bsim. This uses `BabbleSim`_ to simulate the radio activity, and the diff --git a/boards/native/nrf_bsim/doc/nrf54l15bsim.rst b/boards/native/nrf_bsim/doc/nrf54l15bsim.rst index 6ad96b9d6dc..00c1bb01815 100644 --- a/boards/native/nrf_bsim/doc/nrf54l15bsim.rst +++ b/boards/native/nrf_bsim/doc/nrf54l15bsim.rst @@ -1,7 +1,7 @@ .. _nrf54l15bsim: -NRF54L15 simulated boards (BabbleSim) -##################################### +NRF54L15 simulated board (BabbleSim) +#################################### .. contents:: :depth: 1 @@ -12,7 +12,7 @@ NRF54L15 simulated boards (BabbleSim) Overview ******** -To allow simulating nRF54L15 SOCs a Zephyr target boards is provided: the +To allow simulating nRF54L15 SOCs, a Zephyr target board is provided: the ``nrf54l15bsim/nrf54l15/cpuapp``. This uses `BabbleSim`_ to simulate the radio activity, and the @@ -35,7 +35,7 @@ on the simulated nRF54L15 SOC. This simulated target does **not** yet support targeting the cpuflpr core. -This boards include models of some of the nRF54L15 SOC peripherals: +This board includes models of some of the nRF54L15 SOC peripherals: * AAR (Accelerated Address Resolver) * CCM (AES CCM mode encryption) @@ -76,6 +76,8 @@ You can follow the instructions from the :ref:`nrf52_bsim board ` and the `native simulator`_ to +run applications natively on the development system. This has the benefit of +providing native code execution performance and easy debugging using +native tools, but inherits :ref:`its limitations `. + +Just like for the nrf54lm20dk target, the nrf54lm20bsim/nrf54lm20/cpuapp build target provides +support for the application core, on the simulated nRF54LM20 SOC. + +.. note:: + + Unlike real nRF54LM20 devices, the nrf54lm20bsim target has unlimited RAM, and code does not + occupy its RRAM. + +.. note:: + + This simulated target does **not** yet support targeting the cpuflpr core. + +.. warning:: + + This target is experimental. + +This board includes models of some of the nRF54LM20 SOC peripherals: + +* AAR (Accelerated Address Resolver) +* CCM (AES CCM mode encryption) +* CLOCK (Clock control) +* CRACEN (Crypto Accelerator Engine) +* DPPI (Distributed Programmable Peripheral Interconnect) +* ECB (AES electronic codebook mode encryption) +* EGU (Event Generator Unit) +* FICR (Factory Information Configuration Registers) +* GPIO & GPIOTE +* GRTC (Global Real-time Counter) +* PPIB (PPI Bridge) +* RADIO +* RRAMC (Resistive RAM Controller) +* TEMP (Temperature sensor) +* TIMER +* UARTE (UART with Easy DMA) +* UICR (User Information Configuration Registers) + +and will use the same drivers as the nrf54lm20dk targets for these. +For more information on what is modeled to which level of detail, +check the `HW models implementation status`_. + +.. _BabbleSim: + https://BabbleSim.github.io + +.. _native simulator: + https://github.com/BabbleSim/native_simulator/blob/main/docs/README.md + +.. _HW models implementation status: + https://github.com/BabbleSim/ext_nRF_hw_models/blob/main/docs/README_impl_status.md + + +Building for, and using this board +********************************** + +You can follow the instructions from the :ref:`nrf52_bsim board `. +Simply change the board/target appropriately when building. + + +TrustZone, TF-M and other security considerations +************************************************* + +The same considerations as for the :ref:`nrf54l15bsim` target apply to this. diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts index 0874ef8fdf2..5b9f2f56825 100644 --- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts @@ -148,7 +148,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts b/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts index fed633e30ee..120c241ef4d 100644 --- a/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts @@ -95,7 +95,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts index ddd49d23246..94ae9d93262 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts @@ -95,7 +95,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts index f32ad7a220a..0ef9d46809b 100644 --- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts @@ -125,7 +125,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts index 3a2b5ed87bc..35a9e640301 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts @@ -95,7 +95,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts index cda7bb6164d..753fbca029f 100644 --- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts @@ -135,7 +135,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf52840dongle/Kconfig b/boards/nordic/nrf52840dongle/Kconfig index c8698ad0701..0cb2532fada 100644 --- a/boards/nordic/nrf52840dongle/Kconfig +++ b/boards/nordic/nrf52840dongle/Kconfig @@ -3,13 +3,12 @@ # Copyright (c) 2018-2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -if BOARD_NRF52840DONGLE +config BOARD_NRF52840DONGLE + select BOARD_EARLY_INIT_HOOK config BOARD_HAS_NRF5_BOOTLOADER - bool "Board has nRF5 bootloader" - default y + bool + default y if !BOARD_NRF52840DONGLE_NRF52840_BARE help If selected, applications are linked so that they can be loaded by Nordic nRF5 bootloader. - -endif # BOARD_NRF52840DONGLE diff --git a/boards/nordic/nrf52840dongle/Kconfig.defconfig b/boards/nordic/nrf52840dongle/Kconfig.defconfig index 931786859b2..ce4e272cbfb 100644 --- a/boards/nordic/nrf52840dongle/Kconfig.defconfig +++ b/boards/nordic/nrf52840dongle/Kconfig.defconfig @@ -12,18 +12,12 @@ config HW_STACK_PROTECTION # To let the nRF5 bootloader load an application, the application # must be linked after Nordic MBR, that is factory-programmed on the board. -# Nordic nRF5 bootloader exists outside of the partitions specified in the -# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application -# correctly, after Nordic MBR. - -# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION -# which will make it link into the correct partition specified in DTS file, -# the offset is applied here so that the full partition size can be used when -# the bootloader Kconfig option has been disabled. +# If the application wants to use the full partition size, a "bare" board +# variant should be used instead. config FLASH_LOAD_OFFSET default 0x1000 - depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION) + depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" diff --git a/boards/nordic/nrf52840dongle/board.c b/boards/nordic/nrf52840dongle/board.c index ac37eacee21..e06fac1f1dd 100644 --- a/boards/nordic/nrf52840dongle/board.c +++ b/boards/nordic/nrf52840dongle/board.c @@ -7,10 +7,9 @@ #include #include -static int board_nrf52840dongle_nrf52840_init(void) +void board_early_init_hook(void) { - - /* if the nrf52840dongle_nrf52840 board is powered from USB + /* If the nrf52840dongle/nrf52840 board target is powered from USB * (high voltage mode), GPIO output voltage is set to 1.8 volts by * default and that is not enough to turn the green and blue LEDs on. * Increase GPIO voltage to 3.0 volts. @@ -37,9 +36,4 @@ static int board_nrf52840dongle_nrf52840_init(void) /* a reset is required for changes to take effect */ NVIC_SystemReset(); } - - return 0; } - -SYS_INIT(board_nrf52840dongle_nrf52840_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/nordic/nrf52840dongle/board.yml b/boards/nordic/nrf52840dongle/board.yml index 59eae5b3429..b5f92096eea 100644 --- a/boards/nordic/nrf52840dongle/board.yml +++ b/boards/nordic/nrf52840dongle/board.yml @@ -4,3 +4,5 @@ board: vendor: nordic socs: - name: nrf52840 + variants: + - name: bare diff --git a/boards/nordic/nrf52840dongle/doc/index.rst b/boards/nordic/nrf52840dongle/doc/index.rst index 95ec7a34288..b5da6678d00 100644 --- a/boards/nordic/nrf52840dongle/doc/index.rst +++ b/boards/nordic/nrf52840dongle/doc/index.rst @@ -254,13 +254,9 @@ For Segger J-Link debug probes, follow the instructions in the :ref:`nordic_segger` page to install and configure all the necessary software. Further information can be found in :ref:`nordic_segger_flashing`. -Locate the DTS file: :zephyr_file:`boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts`. -This file requires a small modification to use a different partition table. -Edit the include directive to include "fstab-debugger" instead of "fstab-stock". - -In addition, the Kconfig file in the same directory must be modified by setting -``BOARD_HAS_NRF5_BOOTLOADER`` to be default ``n``, otherwise the code will be -flashed with an offset. +Use the ``nrf52840dongle/nrf52840/bare`` board variant to build your application. +This variant uses a modified partition table, which does not reserve space for +the onboard USB bootloader. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -269,7 +265,7 @@ Here is an example for the :zephyr:code-sample:`blinky` application. .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky - :board: nrf52840dongle/nrf52840 + :board: nrf52840dongle/nrf52840/bare :goals: build flash Observe the LED on the board blinking. diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts index 890570b7eee..e446c5aaf54 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts @@ -6,191 +6,45 @@ */ /dts-v1/; -#include -#include "nrf52840dongle_nrf52840-pinctrl.dtsi" -#include +#include "nrf52840dongle_nrf52840_common.dtsi" -/ { - model = "Nordic nRF52840 Dongle NRF52840"; - compatible = "nordic,nrf52840-dongle-nrf52840"; +/* Flash partition table compatible with the onboard USB bootloader */ - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,ieee802154 = &ieee802154; - }; - - leds { - compatible = "gpio-leds"; +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - led0_green: led_0 { - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - label = "Green LED 0"; + /* MCUboot placed after Nordic MBR. + * The size of this partition ensures that MCUBoot can + * be built with CDC ACM support and w/o optimizations. + */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000f000>; }; - led1_red: led_1 { - gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; - label = "Red LED 1"; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00066000>; }; - led1_green: led_2 { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - label = "Green LED 1"; + slot1_partition: partition@76000 { + label = "image-1"; + reg = <0x00076000 0x00066000>; }; - led1_blue: led_3 { - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - label = "Blue LED 1"; + storage_partition: partition@dc000 { + label = "storage"; + reg = <0x000dc000 0x00004000>; }; - }; - - pwmleds { - compatible = "pwm-leds"; - red_pwm_led: pwm_led_0 { - pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - - green_pwm_led: pwm_led_1 { - pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - - blue_pwm_led: pwm_led_2 { - pwms = <&pwm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio1 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 0"; - zephyr,code = ; - }; + /* Onboard USB bootloader <0xe0000 0x1c000> + * + * In addition, the last and second last flash pages + * are used by the onboard USB bootloader and MBR to store + * settings. + */ }; - - /* These aliases are provided for compatibility with samples */ - aliases { - sw0 = &button0; - led0 = &led0_green; - led1 = &led1_red; - led2 = &led1_green; - led3 = &led1_blue; - led0-green = &led0_green; - led1-red = &led1_red; - led1-green = &led1_green; - led1-blue = &led1_blue; - pwm-led0 = &red_pwm_led; - pwm-led1 = &green_pwm_led; - pwm-led2 = &blue_pwm_led; - red-pwm-led = &red_pwm_led; - green-pwm-led = &green_pwm_led; - blue-pwm-led = &blue_pwm_led; - mcuboot-button0 = &button0; - mcuboot-led0 = &led0_green; - watchdog0 = &wdt0; - }; -}; - -®0 { - status = "okay"; -}; - -®1 { - regulator-initial-mode = ; -}; - -&adc { - status = "okay"; -}; - -&gpiote { - status = "okay"; -}; - -&uicr { - nfct-pins-as-gpios; - gpio-as-nreset; }; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&uart0 { - compatible = "nordic,nrf-uarte"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c0 { - compatible = "nordic,nrf-twi"; - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c1 { - compatible = "nordic,nrf-twi"; - /* Cannot be used together with spi1. */ - /* status = "okay"; */ - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -/* - * By default, not adding all available SPI instances (spi2, spi3) due to - * limited GPIOs available on dongle board. - */ -&spi0 { - compatible = "nordic,nrf-spi"; - /* Cannot be used together with i2c0. */ - /* status = "okay"; */ - pinctrl-0 = <&spi0_default>; - pinctrl-1 = <&spi0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi1 { - compatible = "nordic,nrf-spi"; - status = "okay"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&ieee802154 { - status = "okay"; -}; - -/* Include flash partition table. - * Two partition tables are available: - * fstab-stock -compatible with Nordic nRF5 bootloader, default - * fstab-debugger -to use an external debugger, w/o the nRF5 bootloader - */ -#include "fstab-stock.dtsi" - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; - -#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.dts b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.dts new file mode 100644 index 00000000000..b8b76a8e63b --- /dev/null +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "nrf52840dongle_nrf52840_common.dtsi" + +/* Flash partition table without support for the onboard USB bootloader */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* The size of this partition ensures that MCUBoot can be built + * with an RTT console, CDC ACM support, and w/o optimizations. + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00012000>; + }; + + slot0_partition: partition@12000 { + label = "image-0"; + reg = <0x00012000 0x00075000>; + }; + + slot1_partition: partition@87000 { + label = "image-1"; + reg = <0x00087000 0x00075000>; + }; + + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + }; +}; diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.yaml b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.yaml new file mode 100644 index 00000000000..516cd385264 --- /dev/null +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare.yaml @@ -0,0 +1,20 @@ +identifier: nrf52840dongle/nrf52840/bare +name: nRF52840-Dongle-NRF52840-bare +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - usb_device + - ble + - pwm + - spi + - watchdog + - counter + - netif:openthread + - gpio +vendor: nordic diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare_defconfig b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare_defconfig new file mode 100644 index 00000000000..ffaccd75ea8 --- /dev/null +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_bare_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y + +# Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote +# wakeup by default. It needs to be disabled here, because the USB nrfx +# driver always overwrites option from Kconfig mentioned above with the +# imply from CONFIG_USB_NRFX. +CONFIG_USB_DEVICE_REMOTE_WAKEUP=n diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_common.dtsi b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_common.dtsi new file mode 100644 index 00000000000..4039b490861 --- /dev/null +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_common.dtsi @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf52840dongle_nrf52840-pinctrl.dtsi" +#include + +/ { + model = "Nordic nRF52840 Dongle NRF52840"; + compatible = "nordic,nrf52840-dongle-nrf52840"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + + led0_green: led_0 { + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + label = "Green LED 0"; + }; + + led1_red: led_1 { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + label = "Red LED 1"; + }; + + led1_green: led_2 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + label = "Green LED 1"; + }; + + led1_blue: led_3 { + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + label = "Blue LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + red_pwm_led: pwm_led_0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + + green_pwm_led: pwm_led_1 { + pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + + blue_pwm_led: pwm_led_2 { + pwms = <&pwm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 0"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + sw0 = &button0; + led0 = &led0_green; + led1 = &led1_red; + led2 = &led1_green; + led3 = &led1_blue; + led0-green = &led0_green; + led1-red = &led1_red; + led1-green = &led1_green; + led1-blue = &led1_blue; + pwm-led0 = &red_pwm_led; + pwm-led1 = &green_pwm_led; + pwm-led2 = &blue_pwm_led; + red-pwm-led = &red_pwm_led; + green-pwm-led = &green_pwm_led; + blue-pwm-led = &blue_pwm_led; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0_green; + watchdog0 = &wdt0; + }; +}; + +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&uicr { + nfct-pins-as-gpios; + gpio-as-nreset; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uart0 { + compatible = "nordic,nrf-uarte"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c0 { + compatible = "nordic,nrf-twi"; + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c1 { + compatible = "nordic,nrf-twi"; + /* Cannot be used together with spi1. */ + /* status = "okay"; */ + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +/* + * By default, not adding all available SPI instances (spi2, spi3) due to + * limited GPIOs available on dongle board. + */ +&spi0 { + compatible = "nordic,nrf-spi"; + /* Cannot be used together with i2c0. */ + /* status = "okay"; */ + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi1 { + compatible = "nordic,nrf-spi"; + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts index 037c0c46e1c..8f1ff01454d 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts @@ -86,7 +86,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts index 1e9901d60bb..e9a50ea9ac5 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts @@ -88,7 +88,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts index 7d1a09eb357..3a3029550e9 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts @@ -136,7 +136,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig b/boards/nordic/nrf5340_audio_dk/Kconfig new file mode 100644 index 00000000000..65cbaf60c97 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/Kconfig @@ -0,0 +1,7 @@ +# nRF5340 Audio DK board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340_AUDIO_DK + select BOARD_LATE_INIT_HOOK if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_config.c b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_config.c index d907aee691a..a68eb830ee1 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_config.c +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_config.c @@ -11,7 +11,7 @@ LOG_MODULE_REGISTER(nrf5340_audio_dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -static int core_config(void) +void board_late_init_hook(void) { nrf_gpiote_latency_t latency; @@ -21,8 +21,4 @@ static int core_config(void) LOG_DBG("Setting gpiote latency to low power"); nrf_gpiote_latency_set(NRF_GPIOTE, NRF_GPIOTE_LATENCY_LOWPOWER); } - - return 0; } - -SYS_INIT(core_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi b/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi index 8c447727d89..77611791afc 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340dk_common.dtsi @@ -96,7 +96,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; }; diff --git a/boards/nordic/nrf54l09pdk/Kconfig.defconfig b/boards/nordic/nrf54l09pdk/Kconfig.defconfig deleted file mode 100644 index 22c20a6a52e..00000000000 --- a/boards/nordic/nrf54l09pdk/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF54L09PDK_NRF54L09_CPUAPP - -config HW_STACK_PROTECTION - default ARCH_HAS_STACK_PROTECTION - -config ROM_START_OFFSET - default 0x800 if BOOTLOADER_MCUBOOT - -config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE - default y - -endif # BOARD_NRF54L09PDK_NRF54L09_CPUAPP diff --git a/boards/nordic/nrf54l09pdk/Kconfig.nrf54l09pdk b/boards/nordic/nrf54l09pdk/Kconfig.nrf54l09pdk deleted file mode 100644 index 6fbd4a89c8f..00000000000 --- a/boards/nordic/nrf54l09pdk/Kconfig.nrf54l09pdk +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54L09PDK - select SOC_NRF54L09_ENGA_CPUAPP if BOARD_NRF54L09PDK_NRF54L09_CPUAPP - select SOC_NRF54L09_ENGA_CPUFLPR if BOARD_NRF54L09PDK_NRF54L09_CPUFLPR diff --git a/boards/nordic/nrf54l09pdk/board.cmake b/boards/nordic/nrf54l09pdk/board.cmake deleted file mode 100644 index 89977a4cef6..00000000000 --- a/boards/nordic/nrf54l09pdk/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_NRF54L09PDK_NRF54L09_CPUAPP) - board_runner_args(jlink "--device=cortex-m33" "--speed=4000") -elseif(CONFIG_BOARD_NRF54L09PDK_NRF54L09_CPUFLPR) - board_runner_args(jlink "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l09pdk/board.yml b/boards/nordic/nrf54l09pdk/board.yml deleted file mode 100644 index b35f4c1fafe..00000000000 --- a/boards/nordic/nrf54l09pdk/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: nrf54l09pdk - full_name: nRF54L09 PDK - vendor: nordic - socs: - - name: nrf54l09 diff --git a/boards/nordic/nrf54l09pdk/doc/index.rst b/boards/nordic/nrf54l09pdk/doc/index.rst deleted file mode 100644 index 4d5d9e3b3a9..00000000000 --- a/boards/nordic/nrf54l09pdk/doc/index.rst +++ /dev/null @@ -1,71 +0,0 @@ -.. zephyr:board:: nrf54l09pdk - -Overview -******** - -.. note:: - - All software for the nRF54L09 SoC is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF54L09 Preview Development Kit hardware provides -support for the Nordic Semiconductor nRF54L09 Arm Cortex-M33 CPU and -the following devices: - -* CLOCK -* RRAM -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`GRTC (Global real-time counter)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` - -Hardware -******** - -nRF54L09 PDK has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -The crystal oscillators can be configured to use either -internal or external capacitors. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``nrf54l09pdk/nrf54l09/cpuapp`` board target can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` -application. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF54L09 PDK, complete the following steps: - -First, connect the nRF54L09 PDK to you computer using the IMCU USB port on the PDK. -Next, build the sample by running the following command: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf54l09pdk/nrf54l09/cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF54L09 PDK -************************************************ - -Test the nRF54L09 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi deleted file mode 100644 index 9dfe9412d9b..00000000000 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "nrf54l09pdk_nrf54l09-pinctrl.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - - led0: led_0 { - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - label = "Green LED 1"; - }; - - led1: led_1 { - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - label = "Green LED 2"; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 0"; - zephyr,code = ; - }; - - button1: button_1 { - gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 1"; - zephyr,code = ; - }; - - button2: button_2 { - gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 2"; - zephyr,code = ; - }; - - button3: button_3 { - gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 3"; - zephyr,code = ; - }; - }; - - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - watchdog0 = &wdt31; - }; -}; - -&uart20 { - current-speed = <115200>; - pinctrl-0 = <&uart20_default>; - pinctrl-1 = <&uart20_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart30 { - current-speed = <115200>; - pinctrl-0 = <&uart30_default>; - pinctrl-1 = <&uart30_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&hfpll { - /* For now use 64 MHz clock for CPU and fast peripherals. */ - clock-frequency = ; -}; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi deleted file mode 100644 index a87ae590f23..00000000000 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - /omit-if-no-ref/ uart20_default: uart20_default { - group1 { - psels = ; - }; - - group2 { - psels = ; - bias-pull-up; - }; - }; - - /omit-if-no-ref/ uart20_sleep: uart20_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - /omit-if-no-ref/ uart30_default: uart30_default { - group1 { - psels = , - ; - }; - - group2 { - psels = , - ; - bias-pull-up; - }; - }; - - /omit-if-no-ref/ uart30_sleep: uart30_sleep { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; -}; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.dts b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.dts deleted file mode 100644 index 7281f237b66..00000000000 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "nrf54l09_cpuapp_common.dtsi" - -/ { - compatible = "nordic,nrf54l09pdk_nrf54l09-cpuapp"; - model = "Nordic nRF54L09 PDK nRF54L09 Application MCU"; - - chosen { - zephyr,code-partition = &slot0_partition; - zephyr,sram = &cpuapp_sram; - }; -}; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml deleted file mode 100644 index 6edd22f0a41..00000000000 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54l09pdk/nrf54l09/cpuapp -name: nRF54L09-PDK-nRF54L09-Application -type: mcu -arch: arm -toolchain: - - gnuarmemb - - zephyr -sysbuild: true -ram: 192 -flash: 200 -supported: - - counter - - gpio - - watchdog diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig deleted file mode 100644 index 33481a8f230..00000000000 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable MPU -CONFIG_ARM_MPU=y diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr.dts b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr.dts deleted file mode 100644 index 3a1e3c7dd51..00000000000 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr.dts +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf54l09pdk_nrf54l09-common.dtsi" - -/ { - model = "Nordic nRF54L09 PDK nRF54L09 FLPR MCU"; - compatible = "nordic,nrf54l09pdk_nrf54l09-cpuflpr"; - - chosen { - zephyr,console = &uart30; - zephyr,shell-uart = &uart30; - zephyr,code-partition = &cpuflpr_code_partition; - zephyr,flash = &cpuflpr_rram; - zephyr,sram = &cpuflpr_sram; - }; -}; - -&cpuflpr_sram { - status = "okay"; -}; - -&cpuflpr_rram { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - cpuflpr_code_partition: partition@0 { - label = "image-0"; - reg = <0x0 DT_SIZE_K(48)>; - }; - }; -}; - -&grtc { - owned-channels = <3 4>; - status = "okay"; -}; - -&uart30 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpiote20 { - status = "okay"; -}; - -&gpiote30 { - status = "okay"; -}; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr.yaml b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr.yaml deleted file mode 100644 index 01e5c9ffbee..00000000000 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54l09pdk/nrf54l09/cpuflpr -name: nRF54L09-PDK-nRF54L09-Fast-Lightweight-Peripheral-Processor -type: mcu -arch: riscv -toolchain: - - zephyr -sysbuild: true -ram: 48 -flash: 48 -supported: - - counter - - gpio diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr_defconfig b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr_defconfig deleted file mode 100644 index 90cf13bdee5..00000000000 --- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Execute from SRAM -CONFIG_XIP=n diff --git a/boards/nordic/nrf54l15dk/Kconfig.defconfig b/boards/nordic/nrf54l15dk/Kconfig.defconfig index fb63aaecb44..c9155426d02 100644 --- a/boards/nordic/nrf54l15dk/Kconfig.defconfig +++ b/boards/nordic/nrf54l15dk/Kconfig.defconfig @@ -20,7 +20,7 @@ config BOARD_NRF54L15DK select USE_DT_CODE_PARTITION if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || \ BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS -config BT_CTLR +config HAS_BT_CTLR default BT # By default, if we build for a Non-Secure version of the board, diff --git a/boards/nordic/nrf54l15dk/board.cmake b/boards/nordic/nrf54l15dk/board.cmake index 03383155d98..690b5c81a64 100644 --- a/boards/nordic/nrf54l15dk/board.cmake +++ b/boards/nordic/nrf54l15dk/board.cmake @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 if(CONFIG_SOC_NRF54L05_CPUAPP OR CONFIG_SOC_NRF54L10_CPUAPP OR CONFIG_SOC_NRF54L15_CPUAPP) - board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") + board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") elseif(CONFIG_SOC_NRF54L15_CPUFLPR) board_runner_args(jlink "--device=nRF54L15_RV32") elseif(CONFIG_SOC_NRF54L05_CPUFLPR OR CONFIG_SOC_NRF54L10_CPUFLPR) diff --git a/boards/nordic/nrf54l20pdk/Kconfig.defconfig b/boards/nordic/nrf54l20pdk/Kconfig.defconfig deleted file mode 100644 index 4eac6259089..00000000000 --- a/boards/nordic/nrf54l20pdk/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF54L20PDK_NRF54L20_CPUAPP - -config HW_STACK_PROTECTION - default ARCH_HAS_STACK_PROTECTION - -config ROM_START_OFFSET - default 0x800 if BOOTLOADER_MCUBOOT - -config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE - default y - -endif # BOARD_NRF54L20PDK_NRF54L20_CPUAPP diff --git a/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk b/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk deleted file mode 100644 index 3ac84ee1ea3..00000000000 --- a/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54L20PDK - select SOC_NRF54L20_ENGA_CPUAPP if BOARD_NRF54L20PDK_NRF54L20_CPUAPP - select SOC_NRF54L20_ENGA_CPUFLPR if BOARD_NRF54L20PDK_NRF54L20_CPUFLPR diff --git a/boards/nordic/nrf54l20pdk/board.cmake b/boards/nordic/nrf54l20pdk/board.cmake deleted file mode 100644 index 3bb4e520198..00000000000 --- a/boards/nordic/nrf54l20pdk/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUAPP) - board_runner_args(jlink "--device=cortex-m33" "--speed=4000") -elseif(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUFLPR) - board_runner_args(jlink "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l20pdk/board.yml b/boards/nordic/nrf54l20pdk/board.yml deleted file mode 100644 index 4eaa66669fc..00000000000 --- a/boards/nordic/nrf54l20pdk/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: nrf54l20pdk - full_name: nRF54L20 PDK - vendor: nordic - socs: - - name: nrf54l20 diff --git a/boards/nordic/nrf54l20pdk/doc/index.rst b/boards/nordic/nrf54l20pdk/doc/index.rst deleted file mode 100644 index 847380d4db6..00000000000 --- a/boards/nordic/nrf54l20pdk/doc/index.rst +++ /dev/null @@ -1,77 +0,0 @@ -.. zephyr:board:: nrf54l20pdk - -Overview -******** - -.. note:: - - All software for the nRF54L20 SoC is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF54L20 Preview Development Kit hardware provides -support for the Nordic Semiconductor nRF54L20 Arm Cortex-M33 CPU and -the following devices: - -* CLOCK -* RRAM -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`GRTC (Global real-time counter)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` - -Hardware -******** - -nRF54L20 PDK has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -The crystal oscillators can be configured to use either -internal or external capacitors. - -Supported Features -================== - -.. zephyr:board-supported-hw:: - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Applications for the ``nrf54l20pdk/nrf54l20/cpuapp`` board target can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Applications for the ``nrf54l20pdk/nrf54l20/cpuflpr`` board target need -to be built using sysbuild to include the ``vpr_launcher`` image for the application core. - -Enter the following command to compile ``hello_world`` for the FLPR core:: - west build -p -b nrf54l20pdk/nrf54l20/cpuflpr --sysbuild - -Flashing -======== - -As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` -application. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF54L20 PDK, complete the following steps: - -First, connect the nRF54L20 PDK to you computer using the IMCU USB port on the PDK. -Next, build the sample by running the following command: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf54l20pdk/nrf54l20/cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF54L20 PDK -************************************************ - -Test the nRF54L20 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi deleted file mode 100644 index 7a10c8d07ac..00000000000 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "nrf54l20pdk_nrf54l20-pinctrl.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - - led0: led_0 { - gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - label = "Green LED 0"; - }; - - led1: led_1 { - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - label = "Green LED 1"; - }; - - led2: led_2 { - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - label = "Green LED 2"; - }; - - led3: led_3 { - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - label = "Green LED 3"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - /* - * PWM signal can be exposed on GPIO pin only within same domain. - * There is only one domain which contains both PWM and GPIO: - * PWM20/21/22 and GPIO Port P1/P3. - * Only LEDs connected to P1/P3 can work with PWM, for example LED1. - */ - pwm_led1: pwm_led_1 { - pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 0"; - zephyr,code = ; - }; - - button1: button_1 { - gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 1"; - zephyr,code = ; - }; - - button2: button_2 { - gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 2"; - zephyr,code = ; - }; - - button3: button_3 { - gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button 3"; - zephyr,code = ; - }; - }; - - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - pwm-led0 = &pwm_led1; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - watchdog0 = &wdt31; - }; -}; - -&uart20 { - current-speed = <115200>; - pinctrl-0 = <&uart20_default>; - pinctrl-1 = <&uart20_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm20 { - status = "okay"; - pinctrl-0 = <&pwm20_default>; - pinctrl-1 = <&pwm20_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart30 { - current-speed = <115200>; - pinctrl-0 = <&uart30_default>; - pinctrl-1 = <&uart30_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&hfpll { - /* For now use 64 MHz clock for CPU and fast peripherals. */ - clock-frequency = ; -}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi deleted file mode 100644 index 51ea27781c9..00000000000 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - /omit-if-no-ref/ uart20_default: uart20_default { - group1 { - psels = ; - }; - - group2 { - psels = ; - bias-pull-up; - }; - }; - - /omit-if-no-ref/ uart20_sleep: uart20_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - /omit-if-no-ref/ pwm20_default: pwm20_default { - group1 { - psels = ; - }; - }; - - /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; - - /omit-if-no-ref/ uart30_default: uart30_default { - group1 { - psels = , - ; - }; - - group2 { - psels = , - ; - bias-pull-up; - }; - }; - - /omit-if-no-ref/ uart30_sleep: uart30_sleep { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; -}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts deleted file mode 100644 index af32bc27eb7..00000000000 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "nrf54l20_cpuapp_common.dtsi" - -/ { - compatible = "nordic,nrf54l20pdk_nrf54l20-cpuapp"; - model = "Nordic nRF54L20 PDK nRF54L20 Application MCU"; - - chosen { - zephyr,code-partition = &slot0_partition; - zephyr,sram = &cpuapp_sram; - }; -}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml deleted file mode 100644 index 164fd22206b..00000000000 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54l20pdk/nrf54l20/cpuapp -name: nRF54L20-PDK-nRF54L20-Application -type: mcu -arch: arm -toolchain: - - gnuarmemb - - zephyr -sysbuild: true -ram: 512 -flash: 449 -supported: - - adc - - counter - - dmic - - gpio - - i2c - - i2s - - pwm - - spi - - watchdog diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig deleted file mode 100644 index 33481a8f230..00000000000 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable MPU -CONFIG_ARM_MPU=y diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts deleted file mode 100644 index ea3c5d6ff6a..00000000000 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf54l20pdk_nrf54l20-common.dtsi" - -/ { - model = "Nordic nRF54L20 PDK nRF54L20 FLPR MCU"; - compatible = "nordic,nrf54l20pdk_nrf54l20-cpuflpr"; - - chosen { - zephyr,console = &uart30; - zephyr,shell-uart = &uart30; - zephyr,code-partition = &cpuflpr_code_partition; - zephyr,flash = &cpuflpr_rram; - zephyr,sram = &cpuflpr_sram; - }; -}; - -&cpuflpr_sram { - status = "okay"; -}; - -&cpuflpr_rram { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - cpuflpr_code_partition: partition@0 { - label = "image-0"; - reg = <0x0 DT_SIZE_K(64)>; - }; - }; -}; - -&grtc { - owned-channels = <3 4>; - status = "okay"; -}; - -&uart30 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpiote20 { - status = "okay"; -}; - -&gpiote30 { - status = "okay"; -}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml deleted file mode 100644 index 9535e42f71d..00000000000 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -identifier: nrf54l20pdk/nrf54l20/cpuflpr -name: nRF54L20-PDK-nRF54L20-Fast-Lightweight-Peripheral-Processor -type: mcu -arch: riscv -toolchain: - - zephyr -sysbuild: true -ram: 64 -flash: 64 -supported: - - counter - - gpio - - watchdog diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig deleted file mode 100644 index 90cf13bdee5..00000000000 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2025 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Execute from SRAM -CONFIG_XIP=n diff --git a/boards/nordic/nrf54lm20dk/Kconfig.defconfig b/boards/nordic/nrf54lm20dk/Kconfig.defconfig index 2efb752c97b..3424e7a9e78 100644 --- a/boards/nordic/nrf54lm20dk/Kconfig.defconfig +++ b/boards/nordic/nrf54lm20dk/Kconfig.defconfig @@ -3,6 +3,9 @@ if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP +config HW_STACK_PROTECTION + default ARCH_HAS_STACK_PROTECTION + config ROM_START_OFFSET default 0 if PARTITION_MANAGER_ENABLED default 0x800 if BOOTLOADER_MCUBOOT diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi b/boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi index 3591a800948..62ad71541f7 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi +++ b/boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi @@ -18,7 +18,7 @@ zephyr,bt-c2h-uart = &uart20; zephyr,flash-controller = &rram_controller; zephyr,flash = &cpuapp_rram; - zephyr,bt-hci = &bt_hci_sdc; + zephyr,bt-hci = &bt_hci_controller; zephyr,ieee802154 = &ieee802154; }; }; diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts index 29d616b5ece..6dd2c5b2e85 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts +++ b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts @@ -18,12 +18,8 @@ }; }; -&bt_hci_sdc { - status = "okay"; -}; - &bt_hci_controller { - status = "disabled"; + status = "okay"; }; /* Get a node label for wi-fi spi to use in shield files */ diff --git a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_defconfig b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_defconfig index 8424e66c571..6ebc615b782 100644 --- a/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_defconfig +++ b/boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_defconfig @@ -14,9 +14,6 @@ CONFIG_GPIO=y # Enable MPU CONFIG_ARM_MPU=y -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - # MPU-based null-pointer dereferencing detection cannot # be applied as the (0x0 - 0x400) is unmapped for this target. CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi index 9029ae078c0..70d2639e75c 100644 --- a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi @@ -112,7 +112,6 @@ pwm-led0 = &pwm_led0; sw0 = &button0; sw1 = &button1; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts index 64b8519fb69..61cae0bb7ce 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts @@ -101,7 +101,6 @@ led1 = &led1; sw0 = &button0; sw1 = &button1; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi index fb012ea8d3d..84127f51945 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi @@ -70,7 +70,6 @@ pwm-led1 = &pwm_led1; pwm-led2 = &pwm_led2; sw0 = &button0; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi index 9c59a0e0cf9..209608d840d 100644 --- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi @@ -133,7 +133,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf9160dk/Kconfig b/boards/nordic/nrf9160dk/Kconfig index c3687a10645..357c2b50528 100644 --- a/boards/nordic/nrf9160dk/Kconfig +++ b/boards/nordic/nrf9160dk/Kconfig @@ -8,6 +8,9 @@ config BOARD_NRF9160DK # (board.c), so it is forced here to be enabled always, not only # enabled by default (in defconfig). select GPIO if BOARD_NRF9160DK_NRF52840 + select BOARD_EARLY_INIT_HOOK if BOARD_NRF9160DK_NRF52840 && \ + $(dt_nodelabel_exists,external_flash_pins_routing) + select BOARD_LATE_INIT_HOOK if BOARD_NRF9160DK_NRF52840 if BOARD_NRF9160DK_NRF52840 diff --git a/boards/nordic/nrf9160dk/board.c b/boards/nordic/nrf9160dk/board.c index c8e680c4539..4f5310196b6 100644 --- a/boards/nordic/nrf9160dk/board.c +++ b/boards/nordic/nrf9160dk/board.c @@ -160,7 +160,7 @@ static int reset_pin_configure(void) } #endif /* USE_RESET_GPIO */ -static int init(void) +void board_late_init_hook(void) { int rc; @@ -170,7 +170,7 @@ static int init(void) if (!device_is_ready(cfg->gpio)) { LOG_ERR("%s is not ready", cfg->gpio->name); - return -ENODEV; + return; } flags |= (cfg->on ? GPIO_OUTPUT_ACTIVE @@ -188,7 +188,7 @@ static int init(void) } #endif if (rc) { - return rc; + return; } } @@ -201,21 +201,17 @@ static int init(void) rc = reset_pin_configure(); if (rc) { LOG_ERR("Unable to configure reset pin, err %d", rc); - return -EIO; + return; } #endif LOG_INF("Board configured."); - - return 0; } -SYS_INIT(init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); - #define EXT_MEM_CTRL DT_NODELABEL(external_flash_pins_routing) -#if DT_NODE_EXISTS(EXT_MEM_CTRL) -static int early_init(void) +#if DT_NODE_EXISTS(EXT_MEM_CTRL) +void board_early_init_hook(void) { /* As soon as possible after the system starts up, enable the analog * switch that routes signals to the external flash. Otherwise, the @@ -234,9 +230,5 @@ static int early_init(void) nrf_gpio_pin_set(psel); } nrf_gpio_cfg_output(psel); - - return 0; } - -SYS_INIT(early_init, PRE_KERNEL_1, 0); #endif diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi index 5033dda84c1..23561344973 100644 --- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi @@ -160,7 +160,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi index 1dc9a473cf6..a17a19c295b 100644 --- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi @@ -133,7 +133,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi index 900b9d06e65..91b90cea75f 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi @@ -102,7 +102,7 @@ fuel_gauge: fuel_gauge { compatible = "zephyr,fuel-gauge-composite"; - battery-voltage = <&vbatt>; + source-primary = <&vbatt>; device-chemistry = "lithium-ion-polymer"; ocv-capacity-table-0 = ; charge-full-design-microamp-hours = <1350000>; diff --git a/boards/nuvoton/npck3m8k_evb/Kconfig.defconfig b/boards/nuvoton/npck3m8k_evb/Kconfig.defconfig new file mode 100644 index 00000000000..dea8842cad1 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/Kconfig.defconfig @@ -0,0 +1,2 @@ +# Copyright (c) 2025 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/nuvoton/npck3m8k_evb/Kconfig.npck3m8k_evb b/boards/nuvoton/npck3m8k_evb/Kconfig.npck3m8k_evb new file mode 100644 index 00000000000..8864c728b79 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/Kconfig.npck3m8k_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCK3M8K_EVB + select SOC_NPCK3M8K diff --git a/boards/nuvoton/npck3m8k_evb/board.yml b/boards/nuvoton/npck3m8k_evb/board.yml new file mode 100644 index 00000000000..5095987b7fa --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: npck3m8k_evb + full_name: NPCK3M8K_EVB + vendor: nuvoton + socs: + - name: npck3m8k diff --git a/boards/nuvoton/npck3m8k_evb/doc/index.rst b/boards/nuvoton/npck3m8k_evb/doc/index.rst new file mode 100644 index 00000000000..753842dc6a6 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/doc/index.rst @@ -0,0 +1,60 @@ +.. zephyr:board:: npck3m8k_evb + +Overview +******** + +The NPCK3M8K_EVB kit is a development platform to evaluate the +Nuvoton NPCK3 series microcontrollers. This board is designed to provide +a range of peripherals and interfaces for development and testing. It needs +to be mated with part number NPCK3M8K. + +Hardware +******** + +- ARM Cortex-M4F Processor +- 352 KB RAM and 64 KB boot ROM +- GPIO headers +- UART0 and UART1 +- JTAG interface + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +============ + +The NPCK3M8K MCU is configured to use the 90Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock +control register (chapter 4 in user manual) + +Serial Port +=========== + +UART1 is configured for serial logs. + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Flashing +======== + +Build the application as usual for the ``npck3m8k_evb`` board. + +Debugging +========= + +Use JTAG/SWD with a J-Link. + +References +********** + +.. target-notes:: diff --git a/boards/nuvoton/npck3m8k_evb/doc/npck3m8k_evb.webp b/boards/nuvoton/npck3m8k_evb/doc/npck3m8k_evb.webp new file mode 100644 index 00000000000..5ea00e2a859 Binary files /dev/null and b/boards/nuvoton/npck3m8k_evb/doc/npck3m8k_evb.webp differ diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb-pinctrl.dtsi b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb-pinctrl.dtsi new file mode 100644 index 00000000000..62e812975ec --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb-pinctrl.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts new file mode 100644 index 00000000000..d03c6333535 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.dts @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "npck3m8k_evb-pinctrl.dtsi" + +/ { + model = "Nuvoton NPCK3M8K evaluation board"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,flash = &flash0; + zephyr,keyboard-scan = &kscan_input; + }; + + aliases { + /* For samples/basic/blinky_pwm */ + pwm-led0 = &pwm_led0_green; + + /* For gpio test suites */ + led0 = &gpio_led_red; + + /* For pwm test suites */ + pwm-0 = &pwmb; + + /* For i2c test suites */ + i2c-0 = &i2c1_a; + + /* For watchdog sample */ + watchdog0 = &twd0; + + /* For peci driver sample code */ + peci-0 = &peci0; + + /* For kscan test suites */ + kscan0 = &kscan_input; + }; + + leds-pwm { + compatible = "pwm-leds"; + + pwm_led0_green: pwm_led_0 { + pwms = <&pwmb 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "User D7 green"; + }; + }; + + leds-gpio { + compatible = "gpio-leds"; + + gpio_led_red: led_0 { + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; + label = "User D8 red"; + }; + }; +}; + +&cpu0 { + cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>; +}; + +/* Overwrite default device properties with overlays in board dt file here. */ + +&qspi_fiu0 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + + /* Use UART1_SL1 ie. PIN83.88 */ + pinctrl-0 = <&uart1_sin_gp87 + &uart1_sout_gp83>; + pinctrl-names = "default"; +}; + +&pwmb { + status = "okay"; + pinctrl-0 = <&pwmb_gp21>; + pinctrl-names = "default"; +}; + +&adc0 { + status = "disabled"; + + /* Use adc0 channel 0 and 2 for 'adc_api' driver tests */ + pinctrl-0 = <&adc0_chan0_gp90 + &adc0_chan2_gp92>; + pinctrl-names = "default"; +}; + +&espi0 { + status = "disabled"; + pinctrl-0 = <&espi_lpc_gp10_f7>; + pinctrl-names = "default"; +}; + +&i2c1_a { + status = "disabled"; + pinctrl-0 = <&i2c1_a_sda_scl_gp22_17>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&i2c_ctrl1 { + status = "disabled"; +}; + +&tach1 { + status = "okay"; + pinctrl-0 = <&ta1_1_in_gp56>; + pinctrl-names = "default"; + port = ; /* port-A is selected */ + sample-clk = ; /* Use LFCLK as sampling clock */ + pulses-per-round = <1>; /* number of pulses per round of encoder */ +}; + +&peci0 { + status = "okay"; + pinctrl-0 = <>; + pinctrl-names = "default"; +}; + +&kbd { + /* Demonstrate a 13 x 8 keyboard matrix on evb */ + pinctrl-0 = <&ksi0_1_2_3_gpa0_a1_a2_a3 /* KSI0/1/2/3 PINA0/A1/A2/A3 */ + &ksi4_5_gpa4_a5 /* KSI4/5 PINA4/A5 */ + &ksi6_7_gpa6_a7 /* KSI6/7 PINA6/A7 */ + &kso00_01_02_03_gpb0_b1_b2_b3 /* KSO00/01/02/03 PINB0/B1/B2/B3 */ + &kso04_05_06_07_gpb4_b5_b6_b7 /* KS004/05/06/07 PINB4/B5/B6/B7 */ + &kso08_09_gpc0_c1 /* KSO08/09 PINC0/C1 */ + &kso10_11_gpc2_c3 /* KSO10/11 PINC2/C3 */ + &kso12_gp64 /* KSO12 PIN64 */ + >; + pinctrl-names = "default"; + row-size = <8>; + col-size = <13>; + status = "okay"; + + kscan_input: kscan-input { + compatible = "zephyr,kscan-input"; + }; +}; diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.yaml b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.yaml new file mode 100644 index 00000000000..c39728c2c5c --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2022 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: npck3m8k_evb +name: Nuvoton NPCK3M8K EVB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 64 +flash: 192 +supported: + - clock + - gpio + - uart diff --git a/boards/nuvoton/npck3m8k_evb/npck3m8k_evb_defconfig b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb_defconfig new file mode 100644 index 00000000000..c1a473d497f --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/npck3m8k_evb_defconfig @@ -0,0 +1,28 @@ +# +# Copyright (c) 2025 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 +# + +# Enable NPCX firmware header +CONFIG_NPCX_HEADER=y +CONFIG_NPCX_IMAGE_OUTPUT_HEX=y +CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y +CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# UART Driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# GPIO Driver +CONFIG_GPIO=y + +# Console Driver +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nuvoton/npck3m8k_evb/support/openocd.cfg b/boards/nuvoton/npck3m8k_evb/support/openocd.cfg new file mode 100644 index 00000000000..6e70e381f41 --- /dev/null +++ b/boards/nuvoton/npck3m8k_evb/support/openocd.cfg @@ -0,0 +1,16 @@ +# script for Nuvoton NPCX Cortex-M4 Series + +source [find interface/jlink.cfg] +transport select swd + +set CHIPNAME npcx_v2 +set FIUNAME npck.fiu +source [find target/npcx.cfg] + +proc npcx_write_image {target_image} { + flash write_image erase $target_image 0x64000000 ihex +} + +proc npcx_verify_image {target_image} { + verify_image $target_image 0x64000000 ihex +} diff --git a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig index f57da9fa69a..414114e8b52 100644 --- a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig +++ b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig @@ -16,9 +16,6 @@ CONFIG_ARM_MPU=y # Clock configuration CONFIG_CLOCK_CONTROL=y -# General Kernel Options -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000 - # UART Driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig index 0eb25c33a79..2340c0dac71 100644 --- a/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig +++ b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig @@ -13,9 +13,6 @@ CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y # Enable MPU CONFIG_ARM_MPU=y -# General Kernel Options -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000 - # Clock configuration CONFIG_CLOCK_CONTROL=y diff --git a/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig index 443d5beff37..3ed2f750ca4 100644 --- a/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig +++ b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig @@ -16,9 +16,6 @@ CONFIG_ARM_MPU=y # Clock configuration CONFIG_CLOCK_CONTROL=y -# General Kernel Options -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000 - # UART Driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts b/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts index 9f912039eaf..e025145f6f8 100644 --- a/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts +++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts @@ -65,6 +65,10 @@ status = "okay"; }; +&gpioe { + status = "okay"; +}; + &gpioh { status = "okay"; }; diff --git a/boards/nxp/common/Kconfig b/boards/nxp/common/Kconfig new file mode 100644 index 00000000000..913c875f9e0 --- /dev/null +++ b/boards/nxp/common/Kconfig @@ -0,0 +1,8 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NXP_SPSDK_IMAGE + bool "Generate bootable firmware image with SPSDK" + help + Generate bootable firmware image with NXP Secure + Provisioning SDK (SPSDK). diff --git a/boards/nxp/frdm_k32l2b3/Kconfig.frdm_k32l2b3 b/boards/nxp/frdm_k32l2b3/Kconfig.frdm_k32l2b3 new file mode 100644 index 00000000000..5618a43edf9 --- /dev/null +++ b/boards/nxp/frdm_k32l2b3/Kconfig.frdm_k32l2b3 @@ -0,0 +1,9 @@ +# +# Copyright (c) 2025 Ishraq Ibne Ashraf +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_FRDM_K32L2B3 + select SOC_K32L2B31A + select SOC_PART_NUMBER_K32L2B31VLH0A diff --git a/boards/nxp/frdm_k32l2b3/board.cmake b/boards/nxp/frdm_k32l2b3/board.cmake new file mode 100644 index 00000000000..314fac15850 --- /dev/null +++ b/boards/nxp/frdm_k32l2b3/board.cmake @@ -0,0 +1,11 @@ +# +# Copyright (c) 2025 Ishraq Ibne Ashraf +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(linkserver "--device=K32L2B31A:FRDM-K32L2B") +board_runner_args(pyocd "--target=k32l2b3") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/frdm_k32l2b3/board.yml b/boards/nxp/frdm_k32l2b3/board.yml new file mode 100644 index 00000000000..b972cebef63 --- /dev/null +++ b/boards/nxp/frdm_k32l2b3/board.yml @@ -0,0 +1,6 @@ +board: + name: frdm_k32l2b3 + full_name: FRDM-K32L2B3 + vendor: nxp + socs: + - name: k32l2b31a diff --git a/boards/nxp/frdm_k32l2b3/doc/frdm_k32l2b3.webp b/boards/nxp/frdm_k32l2b3/doc/frdm_k32l2b3.webp new file mode 100644 index 00000000000..fa1ee57a7b0 Binary files /dev/null and b/boards/nxp/frdm_k32l2b3/doc/frdm_k32l2b3.webp differ diff --git a/boards/nxp/frdm_k32l2b3/doc/index.rst b/boards/nxp/frdm_k32l2b3/doc/index.rst new file mode 100644 index 00000000000..30307e325c8 --- /dev/null +++ b/boards/nxp/frdm_k32l2b3/doc/index.rst @@ -0,0 +1,178 @@ +.. zephyr:board:: frdm_k32l2b3 + +Overview +******** + +The FRDM-K32L2B3 FRDM development board provides a platform for evaluation and +development of the K32 L2B SoC Family. The board provides easy Access to K32 L2B +SoC I/O. + +Hardware +******** + +- K32L2B31VLH0A SoC running at up to 48 MHz, 256 kB flash memory, 32 kB SRAM memory. +- Full-speed USB port with micro A/B connector for device functionality. +- NXP FXOS8700CQ digital sensor, 3D accelerometer (±2g/±4g/±8g) + 3D magnetometer. +- On-board segment LCD. +- Form factor compatible with Arduino® Rev3 pin layout. +- OpenSDA debug interface. + +For more information about the K32L2B31VLH0A SoC and FRDM-K32L2B3 board: + +- `FRDM-KL32L2B3 Website`_ +- `KL32-L2 Website`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The K32L2B31VLH0A SoC has five pairs of pinmux/gpio controllers, and all are currently +enabled (PORTA/GPIOA, PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the +FRDM-K32L2B3 board. + ++-------+-------------+---------------------------+ +| Name | Function | Usage | ++=======+=============+===========================+ +| PTD5 | GPIO | Green LED | ++-------+-------------+---------------------------+ +| PTE31 | GPIO | Red LED | ++-------+-------------+---------------------------+ +| PTA4 | GPIO | User Button 1 (SW1) | ++-------+-------------+---------------------------+ +| PTC3 | GPIO | User Button 2 (SW2) | ++-------+-------------+---------------------------+ +| PTA1 | LPUART0_RX | UART Console | ++-------+-------------+---------------------------+ +| PTA2 | LPUART0_TX | UART Console | ++-------+-------------+---------------------------+ +| PTE24 | I2C0_SCL | I2C Accelerometer | ++-------+-------------+---------------------------+ +| PTE25 | I2C0_SDA | I2C Accelerometer | ++-------+-------------+---------------------------+ + +System Clock +============ + +The K32L2B31VLH0A SoC is configured to use the 32.768 kHz external +oscillator on the board to generate a 48 MHz system clock. + +Serial Port +=========== + +The K32L2B31VLH0A LPUART0 is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +For more information about OpenSDA and firmware applications check `OpenSDA FRDM-K32L2B3`_. + +Using LinkServer +---------------- + +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the CMSIS-DAP firmware. Please follow the +instructions on :ref:`opensda-daplink-onboard-debug-probe` and select the latest +revision of the firmware image. + +LinkServer is the default for this board, ``west flash`` and ``west debug`` will +call the linkserver runner. + +.. code-block:: console + + west flash + west debug + +Using pyOCD +----------- + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. pyOCD works with the CMSIS-DAP firmware. + +Add the arguments ``-DBOARD_FLASH_RUNNER=pyocd`` and +``-DBOARD_DEBUG_RUNNER=pyocd`` when you invoke ``west build`` to override the +default runner from linkserver to pyocd: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k32l2b3 + :gen-args: -DBOARD_FLASH_RUNNER=pyocd -DBOARD_DEBUG_RUNNER=pyocd + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J13. + +Use the following settings with your serial terminal of choice +(minicom, putty, etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k32l2b3 + :goals: flash + +Open a serial terminal, reset the board (press the SW2 button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-7032-g3198db1b1229 *** + Hello World! frdm_k32l2b3/k32l2b31a + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k32l2b3 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-7032-g3198db1b1229 *** + Hello World! frdm_k32l2b3/k32l2b31a + +.. include:: ../../common/board-footer.rst + :start-after: nxp-board-footer + +.. _KL32-L2 Website: + https://www.nxp.com/products/K32-L2 + +.. _FRDM-KL32L2B3 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/nxp-frdm-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3 + +.. _OpenSDA FRDM-K32L2B3: + https://www.nxp.com/design/design-center/development-boards-and-designs/OPENSDA#FRDM-K32L2B3 diff --git a/boards/nxp/frdm_k32l2b3/frdm_k32l2b3-pinctrl.dtsi b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3-pinctrl.dtsi new file mode 100644 index 00000000000..61778ea31ab --- /dev/null +++ b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3-pinctrl.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Ishraq Ibne Ashraf + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + lpuart0_default: lpuart0_default { + group0 { + pinmux = + , + ; + slew-rate = "slow"; + drive-strength = "low"; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pinmux = + , + ; + bias-pull-up; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; +}; diff --git a/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.dts b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.dts new file mode 100644 index 00000000000..7db15c8f12f --- /dev/null +++ b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.dts @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2025 Ishraq Ibne Ashraf + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "frdm_k32l2b3-pinctrl.dtsi" + +/ { + model = "NXP FRDM-K32L2B3 board"; + compatible = "nxp,k32l2b3", "nxp,k32lx"; + + aliases { + led0 = &led_green; + led1 = &led_red; + sw0 = &sw_1; + sw1 = &sw_3; + magn0 = &fxos8700; + accel0 = &fxos8700; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &lpuart0; + zephyr,shell-uart = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + + led_green: led_1 { + label = "Green LED"; + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + }; + + led_red: led_2 { + label = "Red LED"; + gpios = <&gpioe 31 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + sw_1: button_1 { + label = "User Button 1 (SW1)"; + zephyr,code = ; + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + }; + + sw_3: button_2 { + label = "User Button 2 (SW3)"; + zephyr,code = ; + gpios = <&gpioc 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&sim { + er32k-select = ; + pllfll-select = ; +}; + +&osc { + mode = "low-power"; + clock-frequency = <32768>; +}; + +&ftfa { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&lpuart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1c { + compatible = "nxp,fxos8700"; + reg = <0x1c>; + int1-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioe 1 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.yaml b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.yaml new file mode 100644 index 00000000000..4a133a43d36 --- /dev/null +++ b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3.yaml @@ -0,0 +1,25 @@ +# +# Copyright (c) 2025 Ishraq Ibne Ashraf +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_k32l2b3 +name: NXP FRDM-K32L2B3 +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - led + - i2c + - gpio + - sram + - flash + - lpuart + - button + - pinctrl +vendor: nxp diff --git a/boards/nxp/frdm_k32l2b3/frdm_k32l2b3_defconfig b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3_defconfig new file mode 100644 index 00000000000..0aff032ec37 --- /dev/null +++ b/boards/nxp/frdm_k32l2b3/frdm_k32l2b3_defconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2025 Ishraq Ibne Ashraf +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nxp/frdm_ke15z/frdm_ke15z.dts b/boards/nxp/frdm_ke15z/frdm_ke15z.dts index 0a1c341b000..81a7afd06ac 100644 --- a/boards/nxp/frdm_ke15z/frdm_ke15z.dts +++ b/boards/nxp/frdm_ke15z/frdm_ke15z.dts @@ -58,6 +58,35 @@ zephyr,code = ; }; }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 6 0>, /* A2 */ + <3 0 &gpioa 7 0>, /* A3 */ + <4 0 &gpioa 2 0>, /* A4 */ + <5 0 &gpioa 3 0>, /* A5 */ + <6 0 &gpioc 8 0>, /* D0 */ + <7 0 &gpioc 9 0>, /* D1 */ + <8 0 &gpiod 12 0>, /* D2 */ + <9 0 &gpioc 15 0>, /* D3 */ + <10 0 &gpioe 9 0>, /* D4 */ + <11 0 &gpioc 5 0>, /* D5 */ + <12 0 &gpioa 16 0>, /* D6 */ + <13 0 &gpioa 17 0>, /* D7 */ + <14 0 &gpioe 8 0>, /* D8 */ + <15 0 &gpioe 7 0>, /* D9 */ + <16 0 &gpioa 15 0>, /* D10 */ + <17 0 &gpioe 2 0>, /* D11 */ + <18 0 &gpioe 1 0>, /* D12 */ + <19 0 &gpioe 0 0>, /* D13 */ + <20 0 &gpiod 8 0>, /* D14 */ + <21 0 &gpiod 9 0>; /* D15 */ + }; }; &lpuart1 { diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.dts b/boards/nxp/frdm_ke17z/frdm_ke17z.dts index adc5a836aa1..8be3c16f018 100644 --- a/boards/nxp/frdm_ke17z/frdm_ke17z.dts +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.dts @@ -82,6 +82,35 @@ zephyr,code = ; }; }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 17 0>, /* A0 */ + <1 0 &gpioc 16 0>, /* A1 */ + <2 0 &gpiod 16 0>, /* A2 */ + <3 0 &gpiod 15 0>, /* A3 */ + <4 0 &gpioa 1 0>, /* A4 */ + <5 0 &gpioa 0 0>, /* A5 */ + <6 0 &gpiod 17 0>, /* D0 */ + <7 0 &gpioe 12 0>, /* D1 */ + <8 0 &gpiod 8 0>, /* D2 */ + <9 0 &gpiod 9 0>, /* D3 */ + <10 0 &gpioc 14 0>, /* D4 */ + <11 0 &gpioa 15 0>, /* D5 */ + <12 0 &gpioa 17 0>, /* D6 */ + <13 0 &gpioa 14 0>, /* D7 */ + <14 0 &gpioe 11 0>, /* D8 */ + <15 0 &gpiob 11 0>, /* D9 */ + <16 0 &gpiob 5 0>, /* D10 */ + <17 0 &gpiob 4 0>, /* D11 */ + <18 0 &gpiob 3 0>, /* D12 */ + <19 0 &gpiob 2 0>, /* D13 */ + <20 0 &gpioa 16 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; }; &idle { diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts index aa6eec2348a..6d844024306 100644 --- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts @@ -82,6 +82,35 @@ zephyr,code = ; }; }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 0 0>, /* A0 */ + <1 0 &gpioc 1 0>, /* A1 */ + <2 0 &gpiob 4 0>, /* A2 */ + <3 0 &gpioe 3 0>, /* A3 */ + <4 0 &gpioc 16 0>, /* A4 */ + <5 0 &gpioc 17 0>, /* A5 */ + <6 0 &gpioc 6 0>, /* D0 */ + <7 0 &gpioc 7 0>, /* D1 */ + <8 0 &gpiob 9 0>, /* D2 */ + <9 0 &gpioe 4 0>, /* D3 */ + <10 0 &gpioc 14 0>, /* D4 */ + <11 0 &gpioa 15 0>, /* D5 */ + <12 0 &gpioa 17 0>, /* D6 */ + <13 0 &gpioa 14 0>, /* D7 */ + <14 0 &gpioa 9 0>, /* D8 */ + <15 0 &gpiob 11 0>, /* D9 */ + <16 0 &gpioe 6 0>, /* D10 */ + <17 0 &gpioe 2 0>, /* D11 */ + <18 0 &gpioe 1 0>, /* D12 */ + <19 0 &gpioe 0 0>, /* D13 */ + <20 0 &gpioa 2 0>, /* D14 */ + <21 0 &gpioa 3 0>; /* D15 */ + }; }; &idle { diff --git a/boards/nxp/frdm_mcxa153/board.c b/boards/nxp/frdm_mcxa153/board.c index 52968d73fab..942e07a7de3 100644 --- a/boards/nxp/frdm_mcxa153/board.c +++ b/boards/nxp/frdm_mcxa153/board.c @@ -173,6 +173,10 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO12M_to_LPUART2); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ostimer0)) + CLOCK_AttachClk(kCLK_1M_to_OSTIMER); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta)) RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); #endif diff --git a/boards/nxp/frdm_mcxa153/doc/index.rst b/boards/nxp/frdm_mcxa153/doc/index.rst index 13105e605f9..22e04904aa4 100644 --- a/boards/nxp/frdm_mcxa153/doc/index.rst +++ b/boards/nxp/frdm_mcxa153/doc/index.rst @@ -55,6 +55,7 @@ System Clock The MCX-A153 SoC is configured to use FRO running at 96MHz as a source for the system clock. +The MCX-A153 uses OS timer as the kernel timer. Serial Port =========== diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts index 4765b9cd9e0..589e76e57b7 100644 --- a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts +++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts @@ -24,6 +24,7 @@ pwm-0 = &flexpwm0_pwm0; watchdog0 = &wwdt0; ambient-temp0 = &p3t1755; + die-temp0 = &temp0; }; chosen { @@ -185,6 +186,13 @@ pinctrl-names = "default"; }; +/* + * Uses OS timer as the kernel timer + */ +&ostimer0 { + status = "okay"; +}; + zephyr_udc0: &usb { status = "okay"; }; diff --git a/boards/nxp/frdm_mcxa156/board.c b/boards/nxp/frdm_mcxa156/board.c index 6a479bf3086..079bfdd1e03 100644 --- a/boards/nxp/frdm_mcxa156/board.c +++ b/boards/nxp/frdm_mcxa156/board.c @@ -9,9 +9,9 @@ #include #include -/* Core clock frequency: 150MHz */ -#define CLOCK_INIT_CORE_CLOCK 960000000U -#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 960000000U +/* Core clock frequency: 96MHz */ +#define CLOCK_INIT_CORE_CLOCK 96000000U +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /* System clock frequency. */ extern uint32_t SystemCoreClock; @@ -39,7 +39,7 @@ void board_early_init_hook(void) (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); } - CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ + CLOCK_SetupFROHFClocking(CLOCK_INIT_CORE_CLOCK); /*!< Enable FRO HF(96MHz) output */ CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ @@ -235,6 +235,10 @@ void board_early_init_hook(void) #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ostimer0)) + CLOCK_AttachClk(kCLK_1M_to_OSTIMER); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb)) RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn); CLOCK_EnableUsbfsClock(); diff --git a/boards/nxp/frdm_mcxa156/doc/index.rst b/boards/nxp/frdm_mcxa156/doc/index.rst index 01bcd2dbf5e..6987bd1a063 100644 --- a/boards/nxp/frdm_mcxa156/doc/index.rst +++ b/boards/nxp/frdm_mcxa156/doc/index.rst @@ -55,6 +55,7 @@ System Clock The MCX-A156 SoC is configured to use FRO running at 96MHz as a source for the system clock. +The MCX-A156 uses OS timer as the kernel timer. Serial Port =========== diff --git a/boards/nxp/frdm_mcxa156/dts/lpspi1_header.overlay b/boards/nxp/frdm_mcxa156/dts/lpspi1_header.overlay new file mode 100644 index 00000000000..0cc1f984d86 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/dts/lpspi1_header.overlay @@ -0,0 +1,26 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&lpspi1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpspi1>; + pinctrl-names = "default"; +}; + +&pinctrl { + /* J2 pins 12, 10, 8, 6 -> CLK, MISO, MOSI, PCS */ + pinmux_lpspi1: pinmux_lpspi1 { + group0 { + pinmux = , + , + , + ; + slew-rate = "fast"; + drive-strength = "high"; + input-enable; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts index 50698489641..61888418c72 100644 --- a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts @@ -25,6 +25,7 @@ mcuboot-button0 = &user_button_2; watchdog0 = &wwdt0; ambient-temp0 = &p3t1755; + die-temp0 = &temp0; }; chosen { @@ -80,6 +81,35 @@ <10 0 &gpio3 22 0>, /* Pin 10, LCD backlight control */ <11 0 &gpio3 0 0>; /* Pin 11, LCD and touch reset */ }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 10 0>, /* A0 */ + <1 0 &gpio2 5 0>, /* A1 */ + <2 0 &gpio2 3 0>, /* A2 */ + <3 0 &gpio2 4 0>, /* A3 */ + <4 0 &gpio1 12 0>, /* A4 */ + <5 0 &gpio1 13 0>, /* A5 */ + <6 0 &gpio2 11 0>, /* D0 */ + <7 0 &gpio2 10 0>, /* D1 */ + <8 0 &gpio3 1 0>, /* D2 */ + <9 0 &gpio3 12 0>, /* D3 */ + <10 0 &gpio3 31 0>, /* D4 */ + <11 0 &gpio3 14 0>, /* D5 */ + <12 0 &gpio3 16 0>, /* D6 */ + <13 0 &gpio1 14 0>, /* D7 */ + <14 0 &gpio1 15 0>, /* D8 */ + <15 0 &gpio3 17 0>, /* D9 */ + <16 0 &gpio3 13 0>, /* D10 */ + <17 0 &gpio3 15 0>, /* D11 */ + <18 0 &gpio2 16 0>, /* D12 */ + <19 0 &gpio2 12 0>, /* D13 */ + <20 0 &gpio0 16 0>, /* D14 */ + <21 0 &gpio0 17 0>; /* D15 */ + }; }; &gpio0 { @@ -217,6 +247,13 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd { status = "okay"; }; +/* + * Uses OS timer as the kernel timer + */ +&ostimer0 { + status = "okay"; +}; + zephyr_udc0: &usb { status = "okay"; num-bidir-endpoints = <8>; diff --git a/boards/nxp/frdm_mcxa166/board.c b/boards/nxp/frdm_mcxa166/board.c index 3e6904a7cd6..82ab7b097f4 100644 --- a/boards/nxp/frdm_mcxa166/board.c +++ b/boards/nxp/frdm_mcxa166/board.c @@ -200,6 +200,24 @@ void board_early_init_hook(void) CLOCK_EnableClock(kCLOCK_GateADC1); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0)) + CLOCK_AttachClk(kFRO_LF_DIV_to_CMP0); + CLOCK_SetClockDiv(kCLOCK_DivCMP0_FUNC, 1U); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac)); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp1)) + CLOCK_AttachClk(kFRO_LF_DIV_to_CMP1); + CLOCK_SetClockDiv(kCLOCK_DivCMP1_FUNC, 1U); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp1 | kSPC_controlCmp1Dac)); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp2)) + CLOCK_AttachClk(kFRO_LF_DIV_to_CMP2); + CLOCK_SetClockDiv(kCLOCK_DivCMP2_FUNC, 1U); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp2 | kSPC_controlCmp2Dac)); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); @@ -234,6 +252,10 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI1); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ostimer0)) + CLOCK_AttachClk(kCLK_1M_to_OSTIMER); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) /* diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi b/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi index 97e4a8c2f53..d4cc41d950f 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi @@ -34,7 +34,14 @@ drive-strength = "low"; }; }; - + pinmux_lpcmp0: pinmux_lpcmp0 { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + bias-pull-up; + }; + }; pinmux_lpi2c1: pinmux_lpi2c1 { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts b/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts index d926b02bcc3..a7823600c5e 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts +++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts @@ -21,6 +21,7 @@ sw0 = &user_button_2; sw1 = &user_button_3; watchdog0 = &wwdt0; + die-temp0 = &temp0; }; chosen { @@ -126,6 +127,11 @@ pinctrl-names = "default"; }; +&lpcmp0 { + pinctrl-0 = <&pinmux_lpcmp0>; + pinctrl-names = "default"; +}; + &lpi2c1 { status = "okay"; pinctrl-0 = <&pinmux_lpi2c1>; diff --git a/boards/nxp/frdm_mcxa276/board.c b/boards/nxp/frdm_mcxa276/board.c index 3e6904a7cd6..21842712152 100644 --- a/boards/nxp/frdm_mcxa276/board.c +++ b/boards/nxp/frdm_mcxa276/board.c @@ -192,6 +192,11 @@ void board_early_init_hook(void) CLOCK_SetClockDiv(kCLOCK_DivADC, 1u); CLOCK_AttachClk(kFRO_LF_DIV_to_ADC); +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c0)) + CLOCK_SetClockDiv(kCLOCK_DivI3C0_FCLK, 15U); + CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) CLOCK_EnableClock(kCLOCK_GateADC0); #endif @@ -200,6 +205,24 @@ void board_early_init_hook(void) CLOCK_EnableClock(kCLOCK_GateADC1); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0)) + CLOCK_AttachClk(kFRO_LF_DIV_to_CMP0); + CLOCK_SetClockDiv(kCLOCK_DivCMP0_FUNC, 1U); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac)); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp1)) + CLOCK_AttachClk(kFRO_LF_DIV_to_CMP1); + CLOCK_SetClockDiv(kCLOCK_DivCMP1_FUNC, 1U); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp1 | kSPC_controlCmp1Dac)); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp2)) + CLOCK_AttachClk(kFRO_LF_DIV_to_CMP2); + CLOCK_SetClockDiv(kCLOCK_DivCMP2_FUNC, 1U); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp2 | kSPC_controlCmp2Dac)); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); CLOCK_AttachClk(kFRO_LF_DIV_to_LPI2C0); @@ -234,6 +257,10 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO_LF_DIV_to_LPSPI1); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ostimer0)) + CLOCK_AttachClk(kCLK_1M_to_OSTIMER); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) /* diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi b/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi index 3d0eb7bc5e9..4490694d356 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi @@ -27,6 +27,22 @@ }; }; + pinmux_i3c0: pinmux_i3c0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + group1 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; pinmux_lpadc0: pinmux_lpadc0 { group0 { pinmux = ; @@ -34,7 +50,14 @@ drive-strength = "low"; }; }; - + pinmux_lpcmp0: pinmux_lpcmp0 { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + bias-pull-up; + }; + }; pinmux_lpi2c1: pinmux_lpi2c1 { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts b/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts index 0e0618e38aa..0d0f9eb960f 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts @@ -9,6 +9,7 @@ #include #include "frdm_mcxa276-pinctrl.dtsi" #include +#include / { model = "NXP FRDM_MCXA276 board"; @@ -21,6 +22,8 @@ sw0 = &user_button_2; sw1 = &user_button_3; watchdog0 = &wwdt0; + ambient-temp0 = &p3t1755; + die-temp0 = &temp0; }; chosen { @@ -120,12 +123,33 @@ status = "okay"; }; +&i3c0 { + status = "okay"; + pinctrl-0 = <&pinmux_i3c0>; + pinctrl-names = "default"; + + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; + + p3t1755: p3t1755@4800000236152a0090 { + compatible = "nxp,p3t1755"; + reg = <0x48 0x0236 0x152a0090>; + status = "okay"; + }; +}; + &lpadc0 { status = "okay"; pinctrl-0 = <&pinmux_lpadc0>; pinctrl-names = "default"; }; +&lpcmp0 { + pinctrl-0 = <&pinmux_lpcmp0>; + pinctrl-names = "default"; +}; + &lpi2c1 { status = "okay"; pinctrl-0 = <&pinmux_lpi2c1>; diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml b/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml index 075dfbac694..725d25e282a 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml +++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml @@ -23,4 +23,5 @@ supported: - watchdog - counter - dma + - i3c vendor: nxp diff --git a/boards/nxp/frdm_mcxn236/board.c b/boards/nxp/frdm_mcxn236/board.c index f990251a4f3..5d2525e5ff8 100644 --- a/boards/nxp/frdm_mcxn236/board.c +++ b/boards/nxp/frdm_mcxn236/board.c @@ -122,6 +122,12 @@ void board_early_init_hook(void) CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm0)) + /* Configure input clock to be able to reach the datasheet specified SPI band rate. */ + CLOCK_SetClkDiv(kCLOCK_DivFlexcom0Clk, 1u); + CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM0); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm1)) /* Configure input clock to be able to reach the datasheet specified SPI band rate. */ CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u); @@ -305,6 +311,19 @@ void board_early_init_hook(void) CLOCK_AttachClk(kPLL0_to_I3C1FCLK); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(smartdma)) + CLOCK_EnableClock(kCLOCK_Smartdma); + RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(video_sdma)) + /* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock + * The camera will use this clock signal to generate + * PCLK, HSYNC, and VSYNC + */ + CLOCK_AttachClk(kMAIN_CLK_to_CLKOUT); + CLOCK_SetClkDiv(kCLOCK_DivClkOut, 25U); +#endif +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; } diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi index 19a06b8453f..0b629c88a4e 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi @@ -7,6 +7,16 @@ #include &pinctrl { + pinmux_flexcomm0_lpuart: pinmux_flexcomm0_lpuart { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart { group0 { pinmux = , @@ -177,4 +187,24 @@ bias-pull-up; }; }; + + pinmux_smartdma_camera: pinmux_smartdma_camera { + group0 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + input-enable; + }; + }; }; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts index 6751b42f87c..b6c655a14af 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,7 +7,10 @@ /dts-v1/; #include -#include "frdm_mcxn236.dtsi" +#include "frdm_mcxn236-pinctrl.dtsi" +#include +#include +#include / { model = "NXP FRDM_N236 board"; @@ -28,6 +31,94 @@ watchdog0 = &wwdt0; pwm-0 = &flexpwm1_pwm0; rtc = &rtc; + die-temp0 = &temp0; + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + mcuboot-button0 = &user_button_2; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + blue_led: led_2 { + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + red_led: led_3 { + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_0 { + label = "User SW2"; + gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + user_button_3: button_1 { + label = "User SW3"; + gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio4 6 0>, /* A0 */ + <1 0 &gpio4 15 0>, /* A1 */ + <2 0 &gpio4 16 0>, /* A2 */ + <3 0 &gpio4 17 0>, /* A3 */ + <4 0 &gpio4 12 0>, /* A4 */ + <5 0 &gpio4 13 0>, /* A5 */ + <6 0 &gpio4 3 0>, /* D0 */ + <7 0 &gpio4 2 0>, /* D1 */ + <8 0 &gpio2 0 0>, /* D2 */ + <9 0 &gpio3 12 0>, /* D3 */ + <10 0 &gpio0 21 0>, /* D4 */ + <11 0 &gpio2 7 0>, /* D5 */ + <12 0 &gpio3 17 0>, /* D6 */ + <13 0 &gpio0 22 0>, /* D7 */ + <14 0 &gpio0 23 0>, /* D8 */ + <15 0 &gpio3 14 0>, /* D9 */ + <16 0 &gpio1 3 0>, /* D10 */ + <17 0 &gpio1 0 0>, /* D11 */ + <18 0 &gpio1 2 0>, /* D12 */ + <19 0 &gpio1 1 0>, /* D13 */ + <20 0 &gpio1 16 0>, /* D14 */ + <21 0 &gpio1 17 0>; /* D15 */ + }; + + /* + * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface. + */ + nxp_lcd_8080_connector: lcd-8080-connector { + compatible = "nxp,lcd-8080"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <9 0 &gpio0 23 0>, /* Pin 9, LCD touch INT */ + <10 0 &gpio4 6 0>, /* Pin 10, LCD backlight control */ + <11 0 &gpio4 7 0>; /* Pin 11, LCD and touch reset */ + }; + + dvp_20pin_connector: dvp-20pin-connector { + compatible = "arducam,dvp-20pin-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + ; }; }; @@ -163,3 +254,153 @@ zephyr_udc0: &usb1 { &rtc { status = "okay"; }; + +&flexcomm0_lpuart0 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_lpuart>; + pinctrl-names = "default"; +}; + +&flexcomm2_lpuart2 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm2_lpuart>; + pinctrl-names = "default"; +}; + +&flexcomm2_lpi2c2 { + pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { + pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&flexcomm3_lpspi3 { + pinctrl-0 = <&pinmux_flexcomm3_lpspi>; + pinctrl-names = "default"; +}; + +&flexcomm4_lpuart4 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm4_lpuart>; + pinctrl-names = "default"; +}; + +&flexcomm5_lpi2c5 { + pinctrl-0 = <&pinmux_flexcomm5_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +/* + * MCXN236 board uses OS timer as the kernel timer + * In case we need to switch to SYSTICK timer, then + * replace &os_timer with &systick + */ +&os_timer { + status = "disabled"; +}; + +&systick { + status = "okay"; +}; + +&flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 8KB. + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(80)>; + }; + /* For the MCUBoot "upgrade only" method, + * the slot sizes must be equal. + */ + slot0_partition: partition@14000 { + label = "image-0"; + reg = <0x00014000 DT_SIZE_K(440)>; + }; + slot1_partition: partition@84000 { + label = "image-1"; + reg = <0x0084000 DT_SIZE_K(440)>; + }; + storage_partition: partition@F0000 { + label = "storage"; + reg = <0x000F0000 DT_SIZE_K(64)>; + }; + }; +}; + +&flexpwm1_pwm0 { + pinctrl-0 = <&pinmux_flexpwm1_pwm0>; + pinctrl-names = "default"; +}; + +&lpadc0 { + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&lpcmp0 { + pinctrl-0 = <&pinmux_lpcmp0>; + pinctrl-names = "default"; +}; + +&flexcan1 { + pinctrl-0 = <&pinmux_flexcan1>; + pinctrl-names = "default"; +}; + +zephyr_mipi_dbi_parallel: &flexio0_lcd { + /* DMA channels 0, muxed to FlexIO TX */ + dmas = <&edma0 0 61>; + dma-names = "tx"; + shifters-count = <8>; + timers-count = <1>; + enwr-pin = <28>; + rd-pin = <27>; + data-pin-start = <4>; + reset-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinmux_flexio_lcd>; + pinctrl-names = "default"; +}; + +&i3c1 { + pinctrl-0 = <&pinmux_i3c1>; + pinctrl-names = "default"; +}; + +p3t1755dp_ard_i3c_interface: &i3c1 {}; +p3t1755dp_ard_i2c_interface: &flexcomm5_lpi2c5 {}; + +/* SmartDMA is used for video driver on this board */ +&smartdma { + /* Shields do not enable video-sdma parent node so enable it by default */ + status = "okay"; + program-mem = <0x4000000>; + + video_sdma: video-sdma { + status = "disabled"; + compatible = "nxp,video-smartdma"; + pinctrl-0 = <&pinmux_smartdma_camera>; + pinctrl-names = "default"; + vsync-pin = <4>; + hsync-pin = <5>; + pclk-pin = <7>; + }; +}; + +dvp_20pin_i2c: &flexcomm2_lpi2c2 {}; +dvp_20pin_interface: &video_sdma {}; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi deleted file mode 100644 index 8223342b414..00000000000 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "frdm_mcxn236-pinctrl.dtsi" -#include -#include - -/ { - aliases{ - led0 = &red_led; - led1 = &green_led; - led2 = &blue_led; - sw0 = &user_button_2; - sw1 = &user_button_3; - mcuboot-button0 = &user_button_2; - }; - - leds { - compatible = "gpio-leds"; - green_led: led_1 { - gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; - label = "Green LED"; - }; - blue_led: led_2 { - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; - label = "Blue LED"; - }; - red_led: led_3 { - gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - label = "Red LED"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_2: button_0 { - label = "User SW2"; - gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - zephyr,code = ; - }; - user_button_3: button_1 { - label = "User SW3"; - gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - zephyr,code = ; - }; - }; - - /* - * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface. - */ - nxp_lcd_8080_connector: lcd-8080-connector { - compatible = "nxp,lcd-8080"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <9 0 &gpio0 23 0>, /* Pin 9, LCD touch INT */ - <10 0 &gpio4 6 0>, /* Pin 10, LCD backlight control */ - <11 0 &gpio4 7 0>; /* Pin 11, LCD and touch reset */ - }; -}; - -&flexcomm2_lpuart2 { - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm2_lpuart>; - pinctrl-names = "default"; -}; - -&flexcomm2_lpi2c2 { - pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; - pinctrl-names = "default"; - clock-frequency = ; -}; - -nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { - pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; - pinctrl-names = "default"; - clock-frequency = ; -}; - -&flexcomm3_lpspi3 { - pinctrl-0 = <&pinmux_flexcomm3_lpspi>; - pinctrl-names = "default"; -}; - -&flexcomm4_lpuart4 { - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm4_lpuart>; - pinctrl-names = "default"; -}; - -&flexcomm5_lpi2c5 { - pinctrl-0 = <&pinmux_flexcomm5_lpi2c>; - pinctrl-names = "default"; - clock-frequency = ; -}; - -/* - * MCXN236 board uses OS timer as the kernel timer - * In case we need to switch to SYSTICK timer, then - * replace &os_timer with &systick - */ -&os_timer { - status = "disabled"; -}; - -&systick { - status = "okay"; -}; - -&flash { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * Partition sizes must be aligned - * to the flash memory sector size of 8KB. - */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(80)>; - }; - /* For the MCUBoot "upgrade only" method, - * the slot sizes must be equal. - */ - slot0_partition: partition@14000 { - label = "image-0"; - reg = <0x00014000 DT_SIZE_K(440)>; - }; - slot1_partition: partition@84000 { - label = "image-1"; - reg = <0x0084000 DT_SIZE_K(440)>; - }; - storage_partition: partition@F0000 { - label = "storage"; - reg = <0x000F0000 DT_SIZE_K(64)>; - }; - }; -}; - -&flexpwm1_pwm0 { - pinctrl-0 = <&pinmux_flexpwm1_pwm0>; - pinctrl-names = "default"; -}; - -&lpadc0 { - pinctrl-0 = <&pinmux_lpadc0>; - pinctrl-names = "default"; -}; - -&lpcmp0 { - pinctrl-0 = <&pinmux_lpcmp0>; - pinctrl-names = "default"; -}; - -&flexcan1 { - pinctrl-0 = <&pinmux_flexcan1>; - pinctrl-names = "default"; -}; - -zephyr_mipi_dbi_parallel: &flexio0_lcd { - /* DMA channels 0, muxed to FlexIO TX */ - dmas = <&edma0 0 61>; - dma-names = "tx"; - shifters-count = <8>; - timers-count = <1>; - enwr-pin = <28>; - rd-pin = <27>; - data-pin-start = <4>; - reset-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; - rs-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pinmux_flexio_lcd>; - pinctrl-names = "default"; -}; - -&i3c1 { - pinctrl-0 = <&pinmux_i3c1>; - pinctrl-names = "default"; -}; - -p3t1755dp_ard_i3c_interface: &i3c1 {}; -p3t1755dp_ard_i2c_interface: &flexcomm5_lpi2c5 {}; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml index 1a234da09cd..ded66dd4b3e 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml @@ -26,5 +26,6 @@ supported: - regulator - spi - usbd + - video - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/Kconfig.defconfig b/boards/nxp/frdm_mcxn947/Kconfig.defconfig index 5334a121e40..461a4ed6286 100644 --- a/boards/nxp/frdm_mcxn947/Kconfig.defconfig +++ b/boards/nxp/frdm_mcxn947/Kconfig.defconfig @@ -14,11 +14,4 @@ config MAIN_STACK_SIZE endif -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - endif diff --git a/boards/nxp/frdm_mcxn947/Kconfig.sysbuild b/boards/nxp/frdm_mcxn947/Kconfig.sysbuild deleted file mode 100644 index 4625c7d2929..00000000000 --- a/boards/nxp/frdm_mcxn947/Kconfig.sysbuild +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice MCUBOOT_MODE - default MCUBOOT_MODE_OVERWRITE_ONLY -endchoice diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index 9e6195fd746..aa399db64ed 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -300,6 +300,11 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO_HF_to_ADC0); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) + CLOCK_SetClkDiv(kCLOCK_DivAdc1Clk, 1U); + CLOCK_AttachClk(kFRO_HF_to_ADC1); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI) SPC0->ACTIVE_VDELAY = 0x0500; /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index bc96afa35ed..68e56f31e53 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -55,6 +55,33 @@ }; }; + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <2 0 &gpio0 14 0>, /* A2 */ + <3 0 &gpio0 22 0>, /* A3 */ + <4 0 &gpio0 15 0>, /* A4 */ + <5 0 &gpio0 23 0>, /* A5 */ + <6 0 &gpio4 3 0>, /* D0 */ + <7 0 &gpio4 2 0>, /* D1 */ + <8 0 &gpio0 29 0>, /* D2 */ + <9 0 &gpio1 23 0>, /* D3 */ + <10 0 &gpio0 30 0>, /* D4 */ + <11 0 &gpio1 21 0>, /* D5 */ + <12 0 &gpio1 2 0>, /* D6 */ + <13 0 &gpio0 31 0>, /* D7 */ + <14 0 &gpio0 28 0>, /* D8 */ + <15 0 &gpio0 10 0>, /* D9 */ + <16 0 &gpio0 27 0>, /* D10 */ + <17 0 &gpio0 24 0>, /* D11 */ + <18 0 &gpio0 26 0>, /* D12 */ + <19 0 &gpio0 25 0>, /* D13 */ + <20 0 &gpio4 0 0>, /* D14 */ + <21 0 &gpio4 1 0>; /* D15 */ + }; + /* * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface. */ @@ -67,6 +94,15 @@ <10 0 &gpio4 5 0>, /* Pin 10, LCD backlight control */ <11 0 &gpio4 7 0>; /* Pin 11, LCD and touch reset */ }; + + dvp_20pin_connector: dvp-20pin-connector { + compatible = "arducam,dvp-20pin-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; + gpio-map = , + ; + }; }; &flexcomm1_lpspi1 { @@ -153,9 +189,6 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(80)>; }; - /* For the MCUBoot "upgrade only" method, - * the slot sizes must be equal. - */ slot0_partition: partition@14000 { label = "image-0"; reg = <0x00014000 DT_SIZE_K(984)>; @@ -286,21 +319,6 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd { pinctrl-names = "default"; }; -/* - * Connection with camera modules such as the dvp_20pin_ov7670 shield - */ - -/ { - dvp_20pin_connector: dvp-20pin-connector { - compatible = "arducam,dvp-20pin-connector"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>; - gpio-map = , - ; - }; -}; - dvp_20pin_i2c: &flexcomm7_lpi2c7 {}; dvp_20pin_interface: &video_sdma {}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 1648313dc3d..462e1eb809f 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -31,5 +31,6 @@ supported: - sdhc - spi - usb_device + - video - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts index 48a35e2e661..14759e4e870 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts @@ -19,6 +19,7 @@ chosen { zephyr,flash = &w25q64jvssiq; + zephyr,flash-controller = &w25q64jvssiq; }; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi index e1b876ee0b0..9574a189f8f 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi @@ -80,4 +80,13 @@ slew-rate = "fast"; }; }; + + pinmux_flexio_pwm: pinmux_flexio_pwm { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index b8fc2e6aec4..e67859dbf5a 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -62,6 +62,35 @@ status = "okay"; }; }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpiod 1 0>, /* A0 */ + <1 0 &gpiod 2 0>, /* A1 */ + <2 0 &gpiod 3 0>, /* A2 */ + <3 0 &gpioa 4 0>, /* A3 */ + <4 0 &gpioc 3 0>, /* A4 */ + <5 0 &gpioc 2 0>, /* A5 */ + <6 0 &gpioa 16 0>, /* D0 */ + <7 0 &gpioa 17 0>, /* D1 */ + <8 0 &gpioc 4 0>, /* D2 */ + <9 0 &gpioc 5 0>, /* D3 */ + <10 0 &gpioa 19 0>, /* D4 */ + <11 0 &gpioc 1 0>, /* D5 */ + <12 0 &gpioa 20 0>, /* D6 */ + <13 0 &gpioa 21 0>, /* D7 */ + <14 0 &gpioc 4 0>, /* D8 */ + <15 0 &gpioa 18 0>, /* D9 */ + <16 0 &gpiob 0 0>, /* D10 */ + <17 0 &gpiob 3 0>, /* D11 */ + <18 0 &gpiob 1 0>, /* D12 */ + <19 0 &gpiob 2 0>, /* D13 */ + <20 0 &gpiob 4 0>, /* D14 */ + <21 0 &gpiob 5 0>; /* D15 */ + }; }; &vref { diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml index 24b5be8c10f..efa4848c49b 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml @@ -12,6 +12,7 @@ supported: - can - counter - flash + - flexio - gpio - i2c - pinctrl diff --git a/boards/nxp/frdm_mcxw72/doc/index.rst b/boards/nxp/frdm_mcxw72/doc/index.rst index 56f84381b1e..997e12ae701 100644 --- a/boards/nxp/frdm_mcxw72/doc/index.rst +++ b/boards/nxp/frdm_mcxw72/doc/index.rst @@ -29,6 +29,16 @@ Supported Features .. zephyr:board-supported-hw:: +Fetch Binary Blobs +****************** + +To support Bluetooth, frdm_mcxw72 requires fetching binary blobs, which can be +achieved by running the following command: + +.. code-block:: console + + west blobs fetch hal_nxp + Programming and Debugging ************************* @@ -80,8 +90,24 @@ Connect a USB cable from your PC to J14, and use the serial terminal of your cho - Parity: None - Stop bits: 1 -Flashing -======== +Application Building +==================== + +Openthread applications +----------------------- + +.. zephyr-app-commands:: + :zephyr-app: samples/net/sockets/echo_server + :board: frdm_mcxw72/mcxw727c/cpu0 + :goals: build + +.. zephyr-app-commands:: + :zephyr-app: samples/net/sockets/echo_client + :board: frdm_mcxw72/mcxw727c/cpu0 + :goals: build + +Application Flashing +==================== Here is an example for the :zephyr:code-sample:`hello_world` application. @@ -116,6 +142,50 @@ should see the following message in the terminal: *** Booting Zephyr OS build v3.7.0-xxx-xxxx *** Hello World! frdm_mcxw72/mcxw727c/cpu0 +NBU Flashing +============ + +BLE functionality requires to fetch binary blobs, so make sure to follow +the ``Fetch Binary Blobs`` section first. + +Two images must be written to the board: one for the host (CM33) and one for the NBU (CM3). + +- To flash the application (CM33) refer to the ``Application Flashing`` section above. + +- To flash the ``NBU Flashing``, follow the instructions below: + + * Install ``blhost`` from NXP's website. This is the tool that will allow you to flash the NBU. + * Enter ISP mode. To boot the MCU in ISP mode, follow these steps: + - Disconnect the ``FRDM-MCXW72`` board from all power sources. + - Keep the ``SW4`` and ``SW1`` buttons on the board pressed, while connecting the board to the host computer USB port. + - Release the ``SW4`` and ``SW1`` buttons. The MCXW72 MCU boots in ISP mode. + - Reconnect any external power supply, if needed. + * Use the following command to flash NBU file: + +.. tabs:: + + .. group-tab:: DYN NBU - Windows + + .. code-block:: console + :caption: Flash Dynamic NBU (BLE + 15.4) on Windows + + blhost.exe -p COMxx flash-erase-all 0 + blhost.exe -p COMxx flash-erase-all 2 + blhost.exe -p COMxx write-memory 0x48800000 + + .. group-tab:: DYN NBU - Linux + + .. code-block:: console + :caption: Flash Dynamic NBU (BLE + 15.4) on Linux + + ./blhost -p /dev/ttyxx flash-erase-all 0 + /blhost -p /dev/ttyxx flash-erase-all 2 + /blhost -p /dev/ttyxx write-memory 0x48800000 + +Please consider changing ``COMxx`` on Windows or ``ttyxx`` on Linux to the serial port used by your board. + +The NBU files can be found in : ``/modules/hal/nxp/zephyr/blobs/mcxw72/`` folder. + Troubleshooting =============== diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72-pinctrl.dtsi b/boards/nxp/frdm_mcxw72/frdm_mcxw72-pinctrl.dtsi index 81d37051ec6..a7f307f1cdc 100644 --- a/boards/nxp/frdm_mcxw72/frdm_mcxw72-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72-pinctrl.dtsi @@ -77,4 +77,12 @@ drive-open-drain; }; }; + + pinmux_flexio_pwm: pinmux_flexio_pwm { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; }; diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts index b9981c6f9b3..3cdd5b2b410 100644 --- a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts +++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts @@ -61,6 +61,35 @@ status = "okay"; }; }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpiod 1 0>, /* A0 */ + <1 0 &gpiod 2 0>, /* A1 */ + <2 0 &gpiod 3 0>, /* A2 */ + <3 0 &gpioa 4 0>, /* A3 */ + <4 0 &gpioc 3 0>, /* A4 */ + <5 0 &gpioc 2 0>, /* A5 */ + <6 0 &gpioa 16 0>, /* D0 */ + <7 0 &gpioa 17 0>, /* D1 */ + <8 0 &gpioc 4 0>, /* D2 */ + <9 0 &gpioc 5 0>, /* D3 */ + <10 0 &gpioa 19 0>, /* D4 */ + <11 0 &gpioc 1 0>, /* D5 */ + <12 0 &gpioa 20 0>, /* D6 */ + <13 0 &gpioa 21 0>, /* D7 */ + <14 0 &gpioc 4 0>, /* D8 */ + <15 0 &gpioa 18 0>, /* D9 */ + <16 0 &gpiob 0 0>, /* D10 */ + <17 0 &gpiob 3 0>, /* D11 */ + <18 0 &gpiob 1 0>, /* D12 */ + <19 0 &gpiob 2 0>, /* D13 */ + <20 0 &gpiob 4 0>, /* D14 */ + <21 0 &gpiob 5 0>; /* D15 */ + }; }; &gpioa { diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml index b41068a1c99..afce29da538 100644 --- a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml +++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml @@ -12,6 +12,7 @@ supported: - can - counter - gpio + - flexio - i2c - pinctrl - pwm diff --git a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi index 13611d653ca..cd464f29de2 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi @@ -63,14 +63,18 @@ pinmux_lcdic: pinmux_lcdic { group0 { - pinmux = ; slew-rate = "ultra"; }; + group1 { + pinmux = ; + slew-rate = "ultra"; + sleep-output = "high"; + }; }; pinmux_flexcomm1_i2s: pinmux_flexcomm1_i2s { @@ -83,12 +87,19 @@ pinmux_hsgpio0: pinmux_hsgpio0 { group0 { pinmux = ; slew-rate = "normal"; }; + group1 { + pinmux = ; + slew-rate = "normal"; + sleep-output = "high"; + }; }; pinmux_hsgpio1: pinmux_hsgpio1 { diff --git a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi index 31ef74793d3..1f0d336cbd7 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi @@ -55,6 +55,32 @@ gpio-map = <10 0 &hsgpio1 12 0>, /* Pin 10, LCD and touch reset */ <12 0 &hsgpio0 18 0>; /* Pin 11, LCD touch INT */ }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &hsgpio1 10 0>, /* A0 */ + <1 0 &hsgpio1 11 0>, /* A1 */ + <2 0 &hsgpio1 13 0>, /* A2 */ + <6 0 &hsgpio0 9 0>, /* D0 */ + <7 0 &hsgpio0 8 0>, /* D1 */ + <8 0 &hsgpio0 11 0>, /* D2 */ + <9 0 &hsgpio0 15 0>, /* D3 */ + <10 0 &hsgpio0 18 0>, /* D4 */ + <11 0 &hsgpio0 27 0>, /* D5 */ + <12 0 &hsgpio0 0 0>, /* D6 */ + <13 0 &hsgpio0 20 0>, /* D7 */ + <14 0 &hsgpio1 18 0>, /* D8 */ + <15 0 &hsgpio1 20 0>, /* D9 */ + <16 0 &hsgpio0 6 0>, /* D10 */ + <17 0 &hsgpio0 9 0>, /* D11 */ + <18 0 &hsgpio0 8 0>, /* D12 */ + <19 0 &hsgpio0 7 0>, /* D13 */ + <20 0 &hsgpio0 16 0>, /* D14 */ + <21 0 &hsgpio0 17 0>; /* D15 */ + }; }; &flexcomm3 { @@ -101,6 +127,7 @@ reg = <0>; size = ; status = "okay"; + jedec-id = [ef 40 20]; erase-block-size = <4096>; write-block-size = <1>; spi-max-frequency = <104000000>; @@ -163,7 +190,7 @@ pinctrl-0 = <&pinmux_enet>; pinctrl-names = "default"; phy-handle = <&phy>; - zephyr,random-mac-address; + nxp,unique-mac; phy-connection-type = "rmii"; }; diff --git a/boards/nxp/imx8mm_evk/board.cmake b/boards/nxp/imx8mm_evk/board.cmake index ddcd01410a3..950e31fa777 100644 --- a/boards/nxp/imx8mm_evk/board.cmake +++ b/boards/nxp/imx8mm_evk/board.cmake @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright 2024 NXP +# Copyright 2024-2025 NXP if(CONFIG_BOARD_IMX8MM_EVK_MIMX8MM6_M4) board_set_debugger_ifnset(jlink) @@ -8,3 +8,9 @@ if(CONFIG_BOARD_IMX8MM_EVK_MIMX8MM6_M4) board_runner_args(jlink "--device=MIMX8MD6_M4") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) endif() + +if(CONFIG_SOC_MIMX8MM6_A53) + board_runner_args(jlink "--device=MIMX8MM6_A53_0" "--no-reset" "--flash-sram") + + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx8mm_evk/doc/index.rst b/boards/nxp/imx8mm_evk/doc/index.rst index 3c2a8540aba..dffd5aea21a 100644 --- a/boards/nxp/imx8mm_evk/doc/index.rst +++ b/boards/nxp/imx8mm_evk/doc/index.rst @@ -68,6 +68,50 @@ Programming and Debugging (A53) .. zephyr:board-supported-runners:: +There are multiple methods to program and debug Zephyr on the A53 core: + +Option 1. Boot Zephyr by Using JLink Runner +=========================================== + +The default runner for the board is JLink, connect the EVK board's JTAG connector to +the host computer using a J-Link debugger, power up the board and stop the board at +U-Boot command line. + +Then use "west flash" or "west debug" command to load the zephyr.bin +image from the host computer and start the Zephyr application on A53 core0. + +Flash and Run +------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx8mm_evk/mimx8mm6/a53 + :goals: flash + +Then the following log could be found on UART4 console: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-3063-g38519ca2c028 *** + Hello World! imx8mm_evk/mimx8mm6/a53 + +Debug +----- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx8mm_evk/mimx8mm6/a53 + :goals: debug + +Option 2. Boot Zephyr by Using U-Boot Command +============================================= + U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y, xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example @@ -79,22 +123,45 @@ v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Sof .. _Real-Time Edge Software: https://www.nxp.com/rtedge -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. +Step 1: Download Zephyr Image into DDR Memory +--------------------------------------------- + +Firstly need to download Zephyr binary image into DDR memory, it can use tftp: + +.. code-block:: console + + tftp 0x93c00000 zephyr.bin -Use U-Boot to load and kick zephyr.bin to Cortex-A53 Core0: +Or copy the Zephyr image ``zephyr.bin`` SD card and plug the card into the board, for example +if copy to the FAT partition of the SD card, use the following U-Boot command to load the image +into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed +based on actual setup): .. code-block:: console - fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; go 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; -Or kick zephyr.bin to the other Cortex-A53 Core, for example Core2: +Step 2: Boot Zephyr +------------------- + +Then use the following command to boot Zephyr on the core0: + +.. code-block:: console + + dcache off; icache flush; go 0x93c00000; + +Or use "cpu" command to boot from secondary Core, for example Core1: .. code-block:: console - fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; cpu 2 release 0x93c00000 + dcache flush; icache flush; cpu 1 release 0x93c00000 +Option 3. Boot Zephyr by Using Remoteproc under Linux +===================================================== + +When running Linux on the A55 core, it can use the remoteproc framework to load and boot Zephyr, +refer to Real-Time Edge user guide for more details. Pre-build images and user guide can be found +at `Real-Time Edge Software`_. Use this configuration to run basic Zephyr applications and kernel tests, for example, with the :zephyr:code-sample:`synchronization` sample: @@ -103,28 +170,19 @@ for example, with the :zephyr:code-sample:`synchronization` sample: :zephyr-app: samples/synchronization :host-os: unix :board: imx8mm_evk/mimx8mm6/a53 - :goals: run + :goals: build This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: +display the following console output: .. code-block:: console - #jailhouse enable imx8mm.cell - #jailhouse cell create imx8mm-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0x93c00000 - #jailhouse cell start 1 + *** Booting Zephyr OS build v4.1.0-3063-g38519ca2c028 *** + thread_a: Hello World from cpu 0 on mimx8mm_evk! + thread_b: Hello World from cpu 0 on mimx8mm_evk! + thread_a: Hello World from cpu 0 on mimx8mm_evk! + thread_b: Hello World from cpu 0 on mimx8mm_evk! + thread_a: Hello World from cpu 0 on mimx8mm_evk! Programming and Debugging (M4) ****************************** diff --git a/boards/nxp/imx8mn_evk/board.cmake b/boards/nxp/imx8mn_evk/board.cmake index 9881313609a..ff37ad0855d 100644 --- a/boards/nxp/imx8mn_evk/board.cmake +++ b/boards/nxp/imx8mn_evk/board.cmake @@ -1 +1,10 @@ +# +# Copyright 2025 NXP +# # SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8MN6_A53) + board_runner_args(jlink "--device=MIMX8MN6_A53_0" "--no-reset" "--flash-sram") + + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx8mn_evk/doc/index.rst b/boards/nxp/imx8mn_evk/doc/index.rst index 3102e2a159b..0231f1194a1 100644 --- a/boards/nxp/imx8mn_evk/doc/index.rst +++ b/boards/nxp/imx8mn_evk/doc/index.rst @@ -62,28 +62,88 @@ Programming and Debugging .. zephyr:board-supported-runners:: +There are multiple methods to program and debug Zephyr on the A53 core: + +Option 1. Boot Zephyr by Using JLink Runner +=========================================== + +The default runner for the board is JLink, connect the EVK board's JTAG connector to +the host computer using a J-Link debugger, power up the board and stop the board at +U-Boot command line. + +Then use "west flash" or "west debug" command to load the zephyr.bin +image from the host computer and start the Zephyr application on A53 core0. + +Flash and Run +------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx8mn_evk/mimx8mn6/a53 + :goals: flash + +Then the following log could be found on UART4 console: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-3063-g38519ca2c028 *** + Hello World! imx8mn_evk/mimx8mn6/a53 + +Debug +----- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx8mn_evk/mimx8mn6/a53 + :goals: debug + +Option 2. Boot Zephyr by Using U-Boot Command +============================================= + U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it has been supported in latest U-Boot version by `patch serials`_. .. _patch serials: https://patchwork.ozlabs.org/project/uboot/list/?series=417536&archive=both&state=* -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. +Step 1: Download Zephyr Image into DDR Memory +--------------------------------------------- + +Firstly need to download Zephyr binary image into DDR memory, it can use tftp: + +.. code-block:: console + + tftp 0x93c00000 zephyr.bin -Use U-Boot to load and kick zephyr.bin to Cortex-A53 Core0: +Or copy the Zephyr image ``zephyr.bin`` SD card and plug the card into the board, for example +if copy to the FAT partition of the SD card, use the following U-Boot command to load the image +into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed +based on actual setup): .. code-block:: console - fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; go 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; -Or kick zephyr.bin to the other Cortex-A53 Core, for example Core2: +Step 2: Boot Zephyr +------------------- + +Then use the following command to boot Zephyr on the core0: .. code-block:: console - fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; cpu 2 release 0x93c00000 + dcache off; icache flush; go 0x93c00000; + +Or use "cpu" command to boot from secondary Core, for example Core1: + +.. code-block:: console + dcache flush; icache flush; cpu 1 release 0x93c00000 Use this configuration to run basic Zephyr applications and kernel tests, for example, with the :zephyr:code-sample:`synchronization` sample: @@ -92,28 +152,19 @@ for example, with the :zephyr:code-sample:`synchronization` sample: :zephyr-app: samples/synchronization :host-os: unix :board: imx8mn_evk/mimx8mn6/a53 - :goals: run + :goals: build This will build an image with the synchronization sample app, boot it and display the following ram console output: .. code-block:: console - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: - -.. code-block:: console - - #jailhouse enable imx8mn.cell - #jailhouse cell create imx8mn-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0x93c00000 - #jailhouse cell start 1 + *** Booting Zephyr OS build v4.1.0-3063-g38519ca2c028 *** + thread_a: Hello World from cpu 0 on mimx8mn_evk! + thread_b: Hello World from cpu 0 on mimx8mn_evk! + thread_a: Hello World from cpu 0 on mimx8mn_evk! + thread_b: Hello World from cpu 0 on mimx8mn_evk! + thread_a: Hello World from cpu 0 on mimx8mn_evk! .. include:: ../../common/board-footer.rst :start-after: nxp-board-footer diff --git a/boards/nxp/imx8mp_evk/Kconfig.defconfig b/boards/nxp/imx8mp_evk/Kconfig.defconfig index 8dcef5acccd..f638ec666ad 100644 --- a/boards/nxp/imx8mp_evk/Kconfig.defconfig +++ b/boards/nxp/imx8mp_evk/Kconfig.defconfig @@ -1,4 +1,4 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # SPDX-License-Identifier: Apache-2.0 if BOARD_IMX8MP_EVK @@ -39,6 +39,15 @@ endif # NET_SOCKETS_SERVICE endif # NETWORKING +if CAN && GPIO_PCA6416 + +# For FlexCAN2, SAI5 PDM/CAN2 IOMUX select is controlled by IO expandor PCA6416 +# IO port, so CAN transceiver must be initialized after PCA6416 initialization +config CAN_TRANSCEIVER_INIT_PRIORITY + default 75 + +endif # CAN && GPIO_PCA6416 + endif # BOARD_IMX8MP_EVK_MIMX8ML8_A53 || BOARD_IMX8MP_EVK_MIMX8ML8_A53_SMP endif # BOARD_IMX8MP_EVK diff --git a/boards/nxp/imx8mp_evk/board.cmake b/boards/nxp/imx8mp_evk/board.cmake index 5a232f11d56..f28ed3ff33d 100644 --- a/boards/nxp/imx8mp_evk/board.cmake +++ b/boards/nxp/imx8mp_evk/board.cmake @@ -1,5 +1,5 @@ # -# Copyright (c) 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: Apache-2.0 # @@ -18,3 +18,9 @@ if(CONFIG_SOC_MIMX8ML8_M7) board_runner_args(jlink "--device=MIMX8ML8_M7") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) endif() + +if(CONFIG_SOC_MIMX8ML8_A53) + board_runner_args(jlink "--device=MIMX8ML8_A53_0" "--no-reset" "--flash-sram") + + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst index 70f14700813..9c1c17bdbd8 100644 --- a/boards/nxp/imx8mp_evk/doc/index.rst +++ b/boards/nxp/imx8mp_evk/doc/index.rst @@ -64,6 +64,50 @@ Programming and Debugging (A53) .. zephyr:board-supported-runners:: +There are multiple methods to program and debug Zephyr on the A53 core: + +Option 1. Boot Zephyr by Using JLink Runner +=========================================== + +The default runner for the board is JLink, connect the EVK board's JTAG connector to +the host computer using a J-Link debugger, power up the board and stop the board at +U-Boot command line. + +Then use "west flash" or "west debug" command to load the zephyr.bin +image from the host computer and start the Zephyr application on A53 core0. + +Flash and Run +------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx8mp_evk/mimx8ml8/a53 + :goals: flash + +Then the following log could be found on UART4 console: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-3063-g38519ca2c028 *** + Hello World! imx8mp_evk/mimx8ml8/a53 + +Debug +----- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx8mp_evk/mimx8ml8/a53 + :goals: debug + +Option 2. Boot Zephyr by Using U-Boot Command +============================================= + U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y, xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example @@ -75,21 +119,45 @@ v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Sof .. _Real-Time Edge Software: https://www.nxp.com/rtedge -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. +Step 1: Download Zephyr Image into DDR Memory +--------------------------------------------- -Use U-Boot to load and kick zephyr.bin to Cortex-A53 Core0: +Firstly need to download Zephyr binary image into DDR memory, it can use tftp: .. code-block:: console - fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; go 0xc0000000 + tftp 0xc0000000 zephyr.bin -Or kick zephyr.bin to the other Cortex-A53 Core, for example Core2: +Or copy the Zephyr image ``zephyr.bin`` SD card and plug the card into the board, for example +if copy to the FAT partition of the SD card, use the following U-Boot command to load the image +into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed +based on actual setup): .. code-block:: console - fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; cpu 2 release 0xc0000000 + fatload mmc 1:1 0xc0000000 zephyr.bin; + +Step 2: Boot Zephyr +------------------- + +Then use the following command to boot Zephyr on the core0: + +.. code-block:: console + + dcache off; icache flush; go 0xc0000000; + +Or use "cpu" command to boot from secondary Core, for example Core1: + +.. code-block:: console + + dcache flush; icache flush; cpu 1 release 0xc0000000 + +Option 3. Boot Zephyr by Using Remoteproc under Linux +===================================================== + +When running Linux on the A55 core, it can use the remoteproc framework to load and boot Zephyr, +refer to Real-Time Edge user guide for more details. Pre-build images and user guide can be found +at `Real-Time Edge Software`_. Use this configuration to run basic Zephyr applications and kernel tests, for example, with the :zephyr:code-sample:`synchronization` sample: @@ -98,28 +166,38 @@ for example, with the :zephyr:code-sample:`synchronization` sample: :zephyr-app: samples/synchronization :host-os: unix :board: imx8mp_evk/mimx8ml8/a53 - :goals: run + :goals: build This will build an image with the synchronization sample app, boot it and display the following console output: .. code-block:: console - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: + *** Booting Zephyr OS build v4.1.0-3063-g38519ca2c028 *** + thread_a: Hello World from cpu 0 on mimx8mp_evk! + thread_b: Hello World from cpu 0 on mimx8mp_evk! + thread_a: Hello World from cpu 0 on mimx8mp_evk! + thread_b: Hello World from cpu 0 on mimx8mp_evk! + thread_a: Hello World from cpu 0 on mimx8mp_evk! + +CAN bus (FlexCAN) (A53) +======================= +The FlexCAN controller is a CAN 2.0B controller that supports both standard +and extended frames. The FlexCAN controller has two independent FlexCAN +modules, FlexCAN1 and FlexCAN2. By default, FlexCAN1 is enabled in the device +tree. To enable FlexCAN2, you need to add the following overlay to the +device tree: +:zephyr_file:`boards/nxp/imx8mp_evk/dts/flexcan2.overlay`. + +For example, building the :zephyr:code-sample:`hello_world` sample with the CAN shell and +CAN statistics enabled, and using the FlexCAN1 controller, you can use the following +configuration: -.. code-block:: console - - #jailhouse enable imx8mp.cell - #jailhouse cell create imx8mp-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0xc0000000 - #jailhouse cell start 1 +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx8mp_evk/mimx8ml8/a53 + :gen-args: -DCONFIG_SHELL=y -DCONFIG_CAN=y -DCONFIG_CAN_SHELL=y -DCONFIG_STATS=y -DCONFIG_CAN_STATS=y + :goals: build Programming and Debugging (M7) ****************************** diff --git a/boards/nxp/imx8mp_evk/dts/flexcan2.overlay b/boards/nxp/imx8mp_evk/dts/flexcan2.overlay new file mode 100644 index 00000000000..320363b5d4f --- /dev/null +++ b/boards/nxp/imx8mp_evk/dts/flexcan2.overlay @@ -0,0 +1,23 @@ +/* + * Copyright 2025 NXP + * + * DTS binding overlay for enabling FlexCAN2 + */ + +/ { + chosen { + zephyr,canbus = &flexcan2; + }; +}; + +&can_phy2 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi index dd9346bc19c..654005ccd7e 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi +++ b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi @@ -7,6 +7,26 @@ #include &pinctrl { + flexcan1_default: flexcan1_default { + group0 { + pinmux = <&iomuxc_spdif_rx_can_rx_can1_rx>, + <&iomuxc_spdif_tx_can_tx_can1_tx>; + bias-pull-up; + slew-rate = "fast"; + drive-strength = "x2"; + }; + }; + + flexcan2_default: flexcan2_default { + group0 { + pinmux = <&iomuxc_sai5_mclk_can_rx_can2_rx>, + <&iomuxc_sai5_rxd3_can_tx_can2_tx>; + bias-pull-up; + slew-rate = "fast"; + drive-strength = "x2"; + }; + }; + sai3_default: sai3_default { group0 { pinmux = <&iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync>, diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts index 01dd37b68c2..acd8acfe9c6 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts @@ -16,6 +16,7 @@ compatible = "fsl,mimx8mp"; chosen { + zephyr,canbus = &flexcan1; zephyr,console = &uart4; zephyr,shell-uart = &uart4; /* sram node actually locates at DDR DRAM */ @@ -38,6 +39,23 @@ reg = <0xc0000000 DT_SIZE_M(1)>; }; + can_phy1: can-phy1{ + compatible = "nxp,tja1048", "can-transceiver-gpio"; + enable-gpios = <&gpio_exp1 2 GPIO_ACTIVE_LOW>; + standby-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + max-bitrate = <8000000>; + #phy-cells = <0>; + status = "okay"; + }; + + can_phy2: can-phy2{ + compatible = "nxp,tja1048", "can-transceiver-gpio"; + enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + max-bitrate = <8000000>; + #phy-cells = <0>; + status = "disabled"; + }; }; &enet { @@ -64,6 +82,20 @@ }; }; +&flexcan1 { + pinctrl-0 = <&flexcan1_default>; + pinctrl-names = "default"; + phys = <&can_phy1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-0 = <&flexcan2_default>; + pinctrl-names = "default"; + phys = <&can_phy2>; + status = "disabled"; +}; + &uart4 { status = "okay"; current-speed = <115200>; @@ -91,3 +123,7 @@ &gpio1 { status = "okay"; }; + +&gpio5 { + status = "okay"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml index bbacbcfd9fd..5a3be7c576e 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml @@ -13,10 +13,11 @@ toolchain: - cross-compile ram: 1024 supported: - - uart - - net + - can - gpio - i2c + - net + - uart testing: ignore_tags: - bluetooth diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi index d6dbcdcfa95..b1faef6b7d5 100644 --- a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,6 +30,46 @@ iomuxc_aud_sai1_txfs_sai1_txfs: IOMUXC_AUD_SAI1_TXFS_SAI1_TXFS { pinmux = ; }; + + iomuxc_aud_esai0_fsr_esai0_fsr: IOMUXC_AUD_ESAI0_FSR_ESAI0_FSR { + pinmux = ; + }; + + iomuxc_aud_esai0_fst_esai0_fst: IOMUXC_AUD_ESAI0_FST_ESAI0_FST { + pinmux = ; + }; + + iomuxc_aud_esai0_sckr_esai0_sckr: IOMUXC_AUD_ESAI0_SCKR_ESAI0_SCKR { + pinmux = ; + }; + + iomuxc_aud_esai0_sckt_esai0_sckt: IOMUXC_AUD_ESAI0_SCKT_ESAI0_SCKT { + pinmux = ; + }; + + iomuxc_aud_esai0_tx0_esai0_tx0: IOMUXC_AUD_ESAI0_TX0_ESAI0_TX0 { + pinmux = ; + }; + + iomuxc_aud_esai0_tx1_esai0_tx1: IOMUXC_AUD_ESAI0_TX1_ESAI0_TX1 { + pinmux = ; + }; + + iomuxc_aud_esai0_tx2_rx3_esai0_tx2_rx3: IOMUXC_AUD_ESAI0_TX2_RX3_ESAI0_TX2_RX3 { + pinmux = ; + }; + + iomuxc_aud_esai0_tx3_rx2_esai0_tx3_rx2: IOMUXC_AUD_ESAI0_TX3_RX2_ESAI0_TX3_RX2 { + pinmux = ; + }; + + iomuxc_aud_esai0_tx4_rx1_esai0_tx4_rx1: IOMUXC_AUD_ESAI0_TX4_RX1_ESAI0_TX4_RX1 { + pinmux = ; + }; + + iomuxc_aud_esai0_tx5_rx0_esai0_tx5_rx0: IOMUXC_AUD_ESAI0_TX5_RX0_ESAI0_TX5_RX0 { + pinmux = ; + }; }; &pinctrl { @@ -48,4 +88,19 @@ <&iomuxc_aud_sai1_txfs_sai1_txfs>; }; }; + + esai0_default: esai0_default { + group0 { + pinmux = <&iomuxc_aud_esai0_fsr_esai0_fsr>, + <&iomuxc_aud_esai0_fst_esai0_fst>, + <&iomuxc_aud_esai0_sckr_esai0_sckr>, + <&iomuxc_aud_esai0_sckt_esai0_sckt>, + <&iomuxc_aud_esai0_tx0_esai0_tx0>, + <&iomuxc_aud_esai0_tx1_esai0_tx1>, + <&iomuxc_aud_esai0_tx2_rx3_esai0_tx2_rx3>, + <&iomuxc_aud_esai0_tx3_rx2_esai0_tx3_rx2>, + <&iomuxc_aud_esai0_tx4_rx1_esai0_tx4_rx1>, + <&iomuxc_aud_esai0_tx5_rx0_esai0_tx5_rx0>; + }; + }; }; diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts index 81daabb579f..65108a5c004 100644 --- a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, 2024 NXP + * Copyright (c) 2021, 2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,6 +20,11 @@ }; }; +&esai0 { + pinctrl-0 = <&esai0_default>; + pinctrl-names = "default"; +}; + &lpuart2 { status = "okay"; current-speed = <115200>; diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi index 33ba2c5446c..de9b7e84840 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,6 +30,46 @@ iomuxc_adma_sai1_txd_spi0_cs1: IOMUXC_ADMA_SAI1_TXD_SPI0_CS1 { pinmux = ; }; + + iomuxc_adma_esai0_fsr_esai0_fsr: IOMUXC_ADMA_ESAI0_FSR_ESAI0_FSR { + pinmux = ; + }; + + iomuxc_adma_esai0_fst_esai0_fst: IOMUXC_ADMA_ESAI0_FST_ESAI0_FST { + pinmux = ; + }; + + iomuxc_adma_esai0_sckr_esai0_sckr: IOMUXC_ADMA_ESAI0_SCKR_ESAI0_SCKR { + pinmux = ; + }; + + iomuxc_adma_esai0_sckt_esai0_sckt: IOMUXC_ADMA_ESAI0_SCKT_ESAI0_SCKT { + pinmux = ; + }; + + iomuxc_adma_esai0_tx0_esai0_tx0: IOMUXC_ADMA_ESAI0_TX0_ESAI0_TX0 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx1_esai0_tx1: IOMUXC_ADMA_ESAI0_TX1_ESAI0_TX1 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx2_rx3_esai0_tx2_rx3: IOMUXC_ADMA_ESAI0_TX2_RX3_ESAI0_TX2_RX3 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx3_rx2_esai0_tx3_rx2: IOMUXC_ADMA_ESAI0_TX3_RX2_ESAI0_TX3_RX2 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx4_rx1_esai0_tx4_rx1: IOMUXC_ADMA_ESAI0_TX4_RX1_ESAI0_TX4_RX1 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx5_rx0_esai0_tx5_rx0: IOMUXC_ADMA_ESAI0_TX5_RX0_ESAI0_TX5_RX0 { + pinmux = ; + }; }; &pinctrl { @@ -48,4 +88,19 @@ <&iomuxc_adma_sai1_txd_spi0_cs1>; }; }; + + esai0_default: esai0_default { + group0 { + pinmux = <&iomuxc_adma_esai0_fsr_esai0_fsr>, + <&iomuxc_adma_esai0_fst_esai0_fst>, + <&iomuxc_adma_esai0_sckr_esai0_sckr>, + <&iomuxc_adma_esai0_sckt_esai0_sckt>, + <&iomuxc_adma_esai0_tx0_esai0_tx0>, + <&iomuxc_adma_esai0_tx1_esai0_tx1>, + <&iomuxc_adma_esai0_tx2_rx3_esai0_tx2_rx3>, + <&iomuxc_adma_esai0_tx3_rx2_esai0_tx3_rx2>, + <&iomuxc_adma_esai0_tx4_rx1_esai0_tx4_rx1>, + <&iomuxc_adma_esai0_tx5_rx0_esai0_tx5_rx0>; + }; + }; }; diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts index 460ca19029c..d260715b23a 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, 2024 NXP + * Copyright (c) 2021, 2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,6 +20,11 @@ }; }; +&esai0 { + pinctrl-0 = <&esai0_default>; + pinctrl-names = "default"; +}; + &lpuart2 { status = "okay"; current-speed = <115200>; diff --git a/boards/nxp/imx91_evk/board.cmake b/boards/nxp/imx91_evk/board.cmake new file mode 100644 index 00000000000..25a91be4733 --- /dev/null +++ b/boards/nxp/imx91_evk/board.cmake @@ -0,0 +1,8 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=MIMX9131" "--no-reset" "--flash-sram") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/imx91_evk/doc/index.rst b/boards/nxp/imx91_evk/doc/index.rst index be734dfb1ce..e6f7ff26c1b 100644 --- a/boards/nxp/imx91_evk/doc/index.rst +++ b/boards/nxp/imx91_evk/doc/index.rst @@ -72,6 +72,53 @@ CPU's UART1 for A55 core. Programming and Debugging ******************************* +.. zephyr:board-supported-runners:: + +There are multiple methods to program and debug Zephyr + +Option 1. Boot Zephyr by Using JLink Runner +=========================================== + +The default runner for the board is JLink, connect the EVK board's JTAG connector to +the host computer using a J-Link debugger, power up the board and stop the board at +U-Boot command line. + +Then use "west flash" or "west debug" command to load the zephyr.bin +image from the host computer and start the Zephyr application on A55 core0. + +Flash and Run +------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx91_evk/mimx9131 + :goals: flash + +Then the following log could be found on UART1 console: + +.. code-block:: console + + + *** Booting Zephyr OS build v4.1.0-3063-g2c7ef313ac38 *** + Hello World! imx91_evk/mimx9131 + +Debug +----- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx91_evk/mimx9131 + :goals: debug + +Option 2. Boot Zephyr by Using U-Boot Command +============================================= + U-Boot "go" command is used to load and kick Zephyr to Cortex-A55 Core. Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and diff --git a/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi b/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi index 94d9f0f7f91..92a24fe894d 100644 --- a/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi +++ b/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi @@ -26,4 +26,26 @@ drive-strength = "x5"; }; }; + + i2c1_default: i2c1_default { + group0 { + pinmux = <&iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl>, + <&iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda>; + drive-strength = "x5"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + i2c2_default: i2c2_default { + group0 { + pinmux = <&iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl>, + <&iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda>; + drive-strength = "x5"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; }; diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts b/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts index 1e48ac89b07..4a7defbff98 100644 --- a/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts +++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts @@ -75,3 +75,21 @@ &gpio2{ status = "okay"; }; + +&lpi2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c2 { + clock-frequency = ; + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tpm2 { + status = "okay"; +}; diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml b/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml index 555e96cb20c..e9f3d386948 100644 --- a/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml +++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml @@ -13,6 +13,8 @@ toolchain: - cross-compile ram: 1024 supported: + - counter - gpio - uart + - i2c vendor: nxp diff --git a/boards/nxp/imx93_evk/Kconfig.defconfig b/boards/nxp/imx93_evk/Kconfig.defconfig index 46bd77e3c32..d60fa2c203f 100644 --- a/boards/nxp/imx93_evk/Kconfig.defconfig +++ b/boards/nxp/imx93_evk/Kconfig.defconfig @@ -3,7 +3,7 @@ if BOARD_IMX93_EVK -if BOARD_IMX93_EVK_MIMX9352_A55 +if BOARD_IMX93_EVK_MIMX9352_A55 || BOARD_IMX93_EVK_MIMX9352_A55_SMP if CAN diff --git a/boards/nxp/imx93_evk/Kconfig.imx93_evk b/boards/nxp/imx93_evk/Kconfig.imx93_evk index 3dec8b2b8ba..cd1eb29fe84 100644 --- a/boards/nxp/imx93_evk/Kconfig.imx93_evk +++ b/boards/nxp/imx93_evk/Kconfig.imx93_evk @@ -1,7 +1,7 @@ -# Copyright 2022,2024 NXP +# Copyright 2022,2024-2025 NXP # SPDX-License-Identifier: Apache-2.0 config BOARD_IMX93_EVK - select SOC_MIMX9352_A55 if BOARD_IMX93_EVK_MIMX9352_A55 + select SOC_MIMX9352_A55 if BOARD_IMX93_EVK_MIMX9352_A55 || BOARD_IMX93_EVK_MIMX9352_A55_SMP select SOC_MIMX9352_M33 if BOARD_IMX93_EVK_MIMX9352_M33 || BOARD_IMX93_EVK_MIMX9352_M33_DDR select SOC_PART_NUMBER_MIMX9352DVVXM diff --git a/boards/nxp/imx93_evk/board.yml b/boards/nxp/imx93_evk/board.yml index f85fa29a0c3..b206ed1b2bf 100644 --- a/boards/nxp/imx93_evk/board.yml +++ b/boards/nxp/imx93_evk/board.yml @@ -5,5 +5,7 @@ board: socs: - name: mimx9352 variants: + - name: smp + cpucluster: a55 - name: ddr cpucluster: m33 diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst index 906e395bf21..27e8ac8b627 100644 --- a/boards/nxp/imx93_evk/doc/index.rst +++ b/boards/nxp/imx93_evk/doc/index.rst @@ -9,8 +9,9 @@ small and low cost package. The MCIMX93-EVK board is an entry-level development board, which helps developers to get familiar with the processor before investing a large amount of resources in more specific designs. -i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single -Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core. +i.MX93 MPU is composed of one cluster of 2x Cortex®-A55 cores and a single +Cortex®-M33 core. Zephyr OS is ported on Cortex®-A55 core and Cortex®-M33 +core. - Board features: @@ -47,6 +48,13 @@ Supported Features .. zephyr:board-supported-hw:: +TPM +--- + +TPM2 is enabled for PWM for M33 core. Signals can be observerd with +oscilloscope or logic analyzer. +Connect J1005-3 and J1005-7(GND) to Oscilloscope or logic analyzer + Devices ======== System Clock @@ -245,6 +253,10 @@ Or use "cpu" command to boot from secondary Core, for example Core1: dcache flush; icache flush; cpu 1 release 0xd0000000 +.. note:: + + Use U-Boot "go" command to boot Zephyr when build with target ``imx93_evk/mimx9352/a55/smp``, since i.MX 93 only has 2 Cortex-A55 cores. + Option 3. Boot Zephyr by Using Remoteproc under Linux ===================================================== diff --git a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi index dbf35b8dc98..61d8e07375d 100644 --- a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi +++ b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi @@ -323,4 +323,15 @@ bias-pull-up; }; }; + + tpm2_default: tpm2_default { + group0 { + pinmux = <&iomuxc1_i2c1_scl_tpm_ch_tpm2_ch0>, + <&iomuxc1_i2c1_sda_tpm_ch_tpm2_ch1>; + drive-open-drain; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + input-enable; + }; + }; }; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp.dts new file mode 100644 index 00000000000..ae8deb62d18 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "imx93_evk_mimx9352_a55.dts" + +/ { + cpus { + cpu@0 { + status = "okay"; + }; + }; + + psci { + compatible = "arm,psci-1.1"; + method = "smc"; + }; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp.yaml new file mode 100644 index 00000000000..1b449077020 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp.yaml @@ -0,0 +1,26 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx93_evk/mimx9352/a55/smp +name: NXP i.MX93 EVK A55 SMP +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - gpio + - uart + - i2c + - spi + - can + - net + - smp +testing: + ignore_tags: + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp_defconfig b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp_defconfig new file mode 100644 index 00000000000..9e3e327bd00 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_smp_defconfig @@ -0,0 +1,35 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts index e8db0b54929..31d66c97801 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts @@ -84,3 +84,9 @@ &gpio4 { status = "okay"; }; + +&tpm2 { + pinctrl-0 = <&tpm2_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml index b450925b272..7d20abefd28 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.yaml @@ -13,4 +13,5 @@ flash: 128 supported: - gpio - uart + - pwm vendor: nxp diff --git a/boards/nxp/imx943_evk/CMakeLists.txt b/boards/nxp/imx943_evk/CMakeLists.txt new file mode 100644 index 00000000000..218a0602483 --- /dev/null +++ b/boards/nxp/imx943_evk/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/nxp/imx943_evk/Kconfig.defconfig b/boards/nxp/imx943_evk/Kconfig.defconfig new file mode 100644 index 00000000000..3b836c3aa60 --- /dev/null +++ b/boards/nxp/imx943_evk/Kconfig.defconfig @@ -0,0 +1,31 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config INTC_INIT_PRIORITY + default 2 + +config MBOX_INIT_PRIORITY + default 3 + +if ETH_NXP_IMX_NETC + +config ETH_NXP_IMX_RX_RING_LEN + default 16 + +config ETH_NXP_IMX_TX_RING_LEN + default 16 + +config NET_IF_MAX_IPV4_COUNT + default 6 + +config NET_IF_MAX_IPV6_COUNT + default 6 + +endif # ETH_NXP_IMX_NETC + +if NET_GPTP + +config NET_GPTP_MONITOR_SYNC_STATUS + default y + +endif # NET_GPTP diff --git a/boards/nxp/imx943_evk/Kconfig.imx943_evk b/boards/nxp/imx943_evk/Kconfig.imx943_evk new file mode 100644 index 00000000000..49ceb9ad534 --- /dev/null +++ b/boards/nxp/imx943_evk/Kconfig.imx943_evk @@ -0,0 +1,7 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX943_EVK + select SOC_MIMX94398_A55 if BOARD_IMX943_EVK_MIMX94398_A55 + select SOC_MIMX94398_M33 if BOARD_IMX943_EVK_MIMX94398_M33 || BOARD_IMX943_EVK_MIMX94398_M33_DDR + select SOC_PART_NUMBER_MIMX94398AVKM diff --git a/boards/nxp/imx943_evk/board.c b/boards/nxp/imx943_evk/board.c new file mode 100644 index 00000000000..f131042c2a8 --- /dev/null +++ b/boards/nxp/imx943_evk/board.c @@ -0,0 +1,78 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +static int board_init(void) +{ +#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0) + /* + * PCS(Physical Coding Sublayer) protocols on link0-5, + * xxxx xxxx xxxx xxx1: 1G SGMII + * xxxx xxxx xxxx xx1x: OC-SGMII(i.e.: OverClock 2.5 G SGMII) + */ + BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_0 |= + BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_0_CFG_LINK_PCS_PROT_0(2U); + BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_1 |= + BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_1_CFG_LINK_PCS_PROT_1(2U); + BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_2 |= + BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_2_CFG_LINK_PCS_PROT_2(1U); + BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_3 |= + BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_3_CFG_LINK_PCS_PROT_3(1U); + BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_4 |= + BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_4_CFG_LINK_PCS_PROT_4(1U); + BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_5 |= + BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_5_CFG_LINK_PCS_PROT_5(1U); + + /* + * MII protocol for port0~5 + * 0b0000..MII + * 0b0001..RMII + * 0b0010..RGMII + * 0b0011..SGMII + * 0b0100~0b1111..Reserved + */ + BLK_CTRL_NETCMIX->NETC_LINK_CFG0 |= + BLK_CTRL_NETCMIX_NETC_LINK_CFG0_MII_PROT(0x0U); + BLK_CTRL_NETCMIX->NETC_LINK_CFG1 |= + BLK_CTRL_NETCMIX_NETC_LINK_CFG1_MII_PROT(0x0U); + BLK_CTRL_NETCMIX->NETC_LINK_CFG2 |= + BLK_CTRL_NETCMIX_NETC_LINK_CFG2_MII_PROT(0x2U); + BLK_CTRL_NETCMIX->NETC_LINK_CFG3 |= + BLK_CTRL_NETCMIX_NETC_LINK_CFG3_MII_PROT(0x2U); + BLK_CTRL_NETCMIX->NETC_LINK_CFG4 |= + BLK_CTRL_NETCMIX_NETC_LINK_CFG4_MII_PROT(0x2U); + BLK_CTRL_NETCMIX->NETC_LINK_CFG5 |= + BLK_CTRL_NETCMIX_NETC_LINK_CFG5_MII_PROT(0x2U); + + /* + * ETH2 selection: MAC2(switch port2) or MAC3(enetc0) + * 0b - MAC2 selected + * 1b - MAC3 selected + */ + BLK_CTRL_NETCMIX->EXT_PIN_CONTROL |= BLK_CTRL_NETCMIX_EXT_PIN_CONTROL_mac2_mac3_sel(1U); + + /* Unlock the IERB. It will warm reset whole NETC. */ + NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK; + while ((NETC_PRIV->NETCRR & NETC_PRIV_NETCRR_LOCK_MASK) != 0U) { + } + + /* Lock the IERB. */ + NETC_PRIV->NETCRR |= NETC_PRIV_NETCRR_LOCK_MASK; + while ((NETC_PRIV->NETCSR & NETC_PRIV_NETCSR_STATE_MASK) != 0U) { + } +#endif + return 0; +} + +/* + * Because platform is using ARM SCMI, drivers like scmi, mbox etc. are + * initialized during PRE_KERNEL_1. Common init hooks is not able to use. + * SoC early init and board early init could be run during PRE_KERNEL_2 instead. + */ +SYS_INIT(board_init, PRE_KERNEL_2, 10); diff --git a/boards/nxp/imx943_evk/board.cmake b/boards/nxp/imx943_evk/board.cmake new file mode 100644 index 00000000000..adb33a524bb --- /dev/null +++ b/boards/nxp/imx943_evk/board.cmake @@ -0,0 +1,10 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX94398_A55) + board_runner_args(jlink "--device=MIMX94398_A55" "--no-reset" "--flash-sram") + + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx943_evk/board.yml b/boards/nxp/imx943_evk/board.yml new file mode 100644 index 00000000000..568781db2cc --- /dev/null +++ b/boards/nxp/imx943_evk/board.yml @@ -0,0 +1,9 @@ +board: + name: imx943_evk + full_name: i.MX943 EVK + vendor: nxp + socs: + - name: mimx94398 + variants: + - name: ddr + cpucluster: m33 diff --git a/boards/nxp/imx943_evk/doc/index.rst b/boards/nxp/imx943_evk/doc/index.rst new file mode 100644 index 00000000000..a3d6122e2ad --- /dev/null +++ b/boards/nxp/imx943_evk/doc/index.rst @@ -0,0 +1,345 @@ +.. zephyr:board:: imx943_evk + +Overview +******** + +The IMX943LP5EVK-19 board is a design and evaluation platform based on the +NXP i.MX 943 processor. The i.MX 943 processor integrates up to four Arm +Cortex-A55 cores, along with two Arm Cortex-M33 cores and two Arm Cortex-M7 +cores for functional safety. With PLCs, I/O controllers, V2X accelerators, +ML acceleration, energy management, and advanced security, the i.MX 943 +processor provides optimized performance and power efficiency for industrial, +IoT, and automotive devices. The i.MX943 device on the board comes in a +compact 19 x 19 mm package. + +Hardware +******** + +- i.MX 943 automotive applications processor + + - The processor integrates up to four Arm Cortex-A55 cores, and supports + functional safety with built-in Arm Cortex-M33 and -M7 cores + +- DRAM memory: 8-Gbit LPDDR5 DRAM +- XSPI interface: 64 MB octal SPI NOR flash memory +- eMMC: 32 GB eMMC NAND flash memory +- uSDHC interface: an SD card slot +- USB interface: Two USB Type-C ports +- Ethernet interface: seven Ethernet ports +- PCIe interface: one M.2 slot and one PCIe x4 slot. +- FlexCAN interface: four CAN controller with four CAN connector. +- LPUART interface +- LPSPI interface +- LPI2C interface +- SAI interface +- MQS interface +- MICFIL interface +- LVDS interface +- ADC interface +- SINC interface +- Debug interface + + - One USB-to-UART/MPSSE device, FT4232H + - One USB 3.2 Type-C connector (J15) for FT4232H provides quad serial ports + - JTAG header J16 + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz for Cortex-A55. +Cortex-A55 Core runs up to 1.7 GHz. +Cortex-M33 Core runs up to 333MHz in which SYSTICK runs on same frequency. + + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART1 for Cortex-A55, and UART8 for Cortex-M33. + +Ethernet +-------- + +NETC driver supports to manage the Physical Station Interface (PSI). +The ENET0, ENETC1, ENETC2 ports could be enabled for M33 by west build option +``-DEXTRA_DTC_OVERLAY_FILE=enetc.overlay``. + +Programming and Debugging (A55) +******************************* + +.. zephyr:board-supported-runners:: + +There are multiple methods to program and debug Zephyr on the A55 core: + +Option 1. Boot Zephyr by Using JLink Runner +=========================================== + +Dependency +---------- + +Need to disable all watchdog in U-Boot, otherwise, watchdog will reset the board +after Zephyr start up from the same A55 Core. + +Setup +----- + +The default runner for the board is JLink, connect the EVK board's JTAG connector to +the host computer using a J-Link debugger, power up the board and stop the board at +U-Boot command line. + +Then use "west flash" or "west debug" command to load the zephyr.bin +image from the host computer and start the Zephyr application on A55 core0. + +Flash and Run +------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx943_evk/mimx94398/a55 + :goals: flash + +Then the following log could be found on UART1 console: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-3650-gdb71736adb68 *** + Hello World! imx943_evk/mimx94398/a55 + +Debug +----- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx943_evk/mimx94398/a55 + :goals: debug + +Option 2. Boot Zephyr by Using U-Boot Command +============================================= + +U-Boot "go" command can be used to start Zephyr on A55 Core0. + +Dependency +---------- + +Need to disable all watchdog in U-Boot, otherwise, watchdog will reset the board +after Zephyr start up from the same A55 Core. + +Step 1: Build Zephyr application +-------------------------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx943_evk/mimx94398/a55 + :goals: build + +Step 2: Download Zephyr Image into DDR Memory +--------------------------------------------- + +Firstly need to download Zephyr binary image into DDR memory, it can use tftp: + +.. code-block:: console + + tftp 0xd0000000 zephyr.bin + +Or copy the Zephyr image ``zephyr.bin`` SD card and plug the card into the board, for example +if copy to the FAT partition of the SD card, use the following U-Boot command to load the image +into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed +based on actual setup): + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; + +Step 3: Boot Zephyr +------------------- + +Use the following command to boot Zephyr on the core0: + +.. code-block:: console + + dcache flush; icache flush; go 0xd0000000; + +Then the following log could be found on UART1 console: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-3650-gdb71736adb68 *** + Hello World! imx943_evk/mimx94398/a55 + +.. include:: ../../common/board-footer.rst + :start-after: nxp-board-footer + +Programming and Debugging (M33) +******************************* + +Step 1. Build Zephyr application +================================ + +Here is an example to build the :zephyr:code-sample:`hello_world` application. + +For TCM target + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx943_evk/mimx94398/m33 + :goals: build + +For DDR target + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx943_evk/mimx94398/m33/ddr + :goals: build + +Step 2. Build bootable firmware +=============================== + +The imx-mkimage tool and some other firmware files from `i.MX Linux BSP release`_ +are required to make a bootable firmware to program to SD/eMMC. + +Below is an operations example on Linux host. (For more detail, refer to +`i.MX Linux BSP release`_ 6.12.3_1.0.0) + +.. code-block:: console + + # download + + git clone https://github.com/nxp-imx/imx-mkimage.git -b lf-6.12.3_1.0.0 + git clone https://github.com/nxp-imx/imx-sm.git -b lf-6.12.3-imx943-er1 + git clone https://github.com/nxp-imx/imx-oei.git -b lf-6.12.3-imx943-er1 + + wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.27-5af0ceb.bin + wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.1-0a66c34.bin + + # some firmware files need to be unpacked + + chmod 777 firmware-imx-8.27-5af0ceb.bin + chmod 777 firmware-ele-imx-2.0.1-0a66c34.bin + ./firmware-imx-8.27-5af0ceb.bin --auto-accept + ./firmware-ele-imx-2.0.1-0a66c34.bin --auto-accept + + # some firmware files need to be built from source + + export TOOLS=$ARMGCC_DIR + export SM_CROSS_COMPILE=${TOOLS}/bin/arm-none-eabi- + export OEI_CROSS_COMPILE=${TOOLS}/bin/arm-none-eabi- + + make -C imx-oei board=mx943lp5-19 oei=ddr d=1 all + make -C imx-sm config=mx94alt cfg + make -C imx-sm config=mx94alt all + + # make bootable firmware flash.bin + + cp firmware-imx-8.27-5af0ceb/firmware/ddr/synopsys/lpddr5*v202409.bin imx-mkimage/iMX94/ + cp firmware-ele-imx-2.0.1-0a66c34/mx943a0-ahab-container.img imx-mkimage/iMX94/ + cp imx-sm/build/mx94alt/m33_image.bin imx-mkimage/iMX94/ + cp imx-oei/build/mx943lp5-19/ddr/oei-m33-ddr.bin imx-mkimage/iMX94/ + cp zephyr/build/zephyr/zephyr.bin imx-mkimage/iMX94/m33s_image.bin + + cd imx-mkimage + make SOC=iMX94 OEI=YES flash_m33s # for TCM target + make SOC=iMX94 OEI=YES flash_m33s_ddr # for DDR target + + # Program to SD card + + dd if=iMX94/flash.bin of=/dev/sdb bs=1k seek=32 && sync + +Note: for this Linux BSP release version, we need to do some changes in imx-sm and imx-mkimage +to support M33 boot and DDR target. + +imx-sm changes: + +.. code-block:: console + + diff --git a/configs/mx94alt.cfg b/configs/mx94alt.cfg + index 4613900..069992a 100755 + --- a/configs/mx94alt.cfg + +++ b/configs/mx94alt.cfg + @@ -308,7 +308,7 @@ FAULT_SWNCF04 OWNER, reaction=sys_shutdown + # Boot EENV # + #==========================================================================# + + -LM1 name="Boot", rpc=scmi, boot=2, skip=1, did=3, default + +LM1 name="Boot", rpc=scmi, boot=2, skip=1, did=13, default + + DFMT0: sa=secure + DFMT1: sa=secure, pa=privileged + @@ -322,10 +322,6 @@ DATA: perm=rw + + PD_NETC stop=6 + CPU_M33S start=1, stop=5 + -PD_M70 stop=4 + -CPU_M7P0 start=2, stop=3 + -PD_M71 stop=2 + -CPU_M7P1 start=3, stop=1 + + # Start/Stop (mSel=1) + +imx-mkimage changes: + +.. code-block:: console + + diff --git a/iMX94/soc.mak b/iMX94/soc.mak + index 838d2a2..bc756f9 100644 + --- a/iMX94/soc.mak + +++ b/iMX94/soc.mak + @@ -392,6 +392,11 @@ flash_m33s: $(MKIMG) $(AHAB_IMG) $(MCU_IMG) $(M33S_IMG) $(OEI_IMG_M33) + -m33 $(MCU_IMG) 0 $(MCU_TCM_ADDR) \ + -m33 $(M33S_IMG) 1 $(M33S_TCM_ADDR) $(M33S_TCM_ADDR_ALIAS) -out flash.bin + + +flash_m33s_ddr: $(MKIMG) $(AHAB_IMG) $(MCU_IMG) $(M33S_IMG) $(OEI_IMG_M33) + + ./$(MKIMG) -soc IMX9 -cntr_version 2 -u 1 -append $(AHAB_IMG) -c $(OEI_OPT_M33) -msel $(MSEL) \ + + -m33 $(MCU_IMG) 0 $(MCU_TCM_ADDR) \ + + -m33 $(M33S_IMG) 1 0x86000000 0x86000000 -out flash.bin + + + flash_m33s_xspi: $(MKIMG) $(AHAB_IMG) $(MCU_IMG) $(M33S_IMG) $(OEI_IMG_M33) + ./$(MKIMG) -soc IMX9 -cntr_version 2 -u 1 -append $(AHAB_IMG) -dev flexspi -c $(OEI_OPT_M33) -msel $(MSEL) \ + -m33 $(MCU_IMG) 0 $(MCU_TCM_ADDR) \ + +Step 3. Boot Zephyr +=================== + +Boot board from SD card. It will display the following console output. + +For TCM target + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-5264-g8654b4029d16 *** + Hello World! imx943_evk/mimx94398/m33 + +For DDR target + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-5264-g8654b4029d16 *** + Hello World! imx943_evk/mimx94398/m33/ddr + +Note: there will be 4 serial ports identified when connect USB cable to debug port. +The first serial port will be UART8 for M33. As there is multiplexing between JTAG +and UART8, below bcu (`bcu 1.1.113 download`_) configuration is needed to use UART8. + +.. code-block:: console + + bcu lsftdi + bcu set_gpio fta_jtag_host_en 0 -board=imx943evk19b1 -id=1-1 + +.. _bcu 1.1.113 download: + https://github.com/nxp-imx/bcu/releases/tag/bcu_1.1.113 + +.. _i.MX Linux BSP release: + https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX diff --git a/boards/nxp/imx943_evk/dts/enetc.overlay b/boards/nxp/imx943_evk/dts/enetc.overlay new file mode 100644 index 00000000000..0d57349b4d8 --- /dev/null +++ b/boards/nxp/imx943_evk/dts/enetc.overlay @@ -0,0 +1,40 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&emdio { + status = "okay"; + + phy2: phy@5 { + status = "okay"; + }; + + phy3: phy@6 { + status = "okay"; + }; + + phy4: phy@7 { + status = "okay"; + }; +}; + +&enetc_psi0 { + ptp-clock = <&netc_ptp_clock0>; + status = "okay"; +}; + +&enetc_psi1 { + ptp-clock = <&netc_ptp_clock0>; + status = "okay"; +}; + +&enetc_psi2 { + ptp-clock = <&netc_ptp_clock0>; + status = "okay"; +}; + +&netc_ptp_clock0 { + status = "okay"; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk-pinctrl.dtsi b/boards/nxp/imx943_evk/imx943_evk-pinctrl.dtsi new file mode 100644 index 00000000000..82513537f5d --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk-pinctrl.dtsi @@ -0,0 +1,188 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + emdio_default: emdio_default { + group1 { + pinmux = <&iomuxc_eth4_mdc_gpio1_netc_emdc_netc_emdc>, + <&iomuxc_eth4_mdio_gpio2_netc_emdio_netc_emdio>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + }; + + eth0_default: eth0_default { + group1 { + pinmux = <&iomuxc_eth0_rx_dv_netc_swt_eth_rx_dv_netc_swt_eth0_rx_dv>, + <&iomuxc_eth0_rx_er_netc_swt_eth_rx_er_netc_swt_eth0_rx_er>, + <&iomuxc_eth0_rxd0_netc_swt_eth_rxd_netc_swt_eth0_rxd0>, + <&iomuxc_eth0_rxd1_netc_swt_eth_rxd_netc_swt_eth0_rxd1>, + <&iomuxc_eth0_rxd2_netc_swt_eth_rxd_netc_swt_eth0_rxd2>, + <&iomuxc_eth0_rxd3_netc_swt_eth_rxd_netc_swt_eth0_rxd3>, + <&iomuxc_eth0_tx_en_netc_swt_eth_tx_en_netc_swt_eth0_tx_en>, + <&iomuxc_eth0_tx_er_netc_swt_eth_tx_er_netc_swt_eth0_tx_er>, + <&iomuxc_eth0_txd0_netc_swt_eth_txd_netc_swt_eth0_txd0>, + <&iomuxc_eth0_txd1_netc_swt_eth_txd_netc_swt_eth0_txd1>, + <&iomuxc_eth0_txd2_netc_swt_eth_txd_netc_swt_eth0_txd2>, + <&iomuxc_eth0_txd3_netc_swt_eth_txd_netc_swt_eth0_txd3>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + group2 { + pinmux = <&iomuxc_eth0_rx_clk_netc_swt_eth_rx_clk_netc_swt_eth0_rx_clk>, + <&iomuxc_eth0_tx_clk_netc_swt_eth_tx_clk_netc_swt_eth0_tx_clk>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + }; + + eth1_default: eth1_default { + group1 { + pinmux = <&iomuxc_eth1_rx_dv_netc_swt_eth_rx_dv_netc_swt_eth1_rx_dv>, + <&iomuxc_eth1_rx_er_netc_swt_eth_rx_er_netc_swt_eth1_rx_er>, + <&iomuxc_eth1_rxd0_netc_swt_eth_rxd_netc_swt_eth1_rxd0>, + <&iomuxc_eth1_rxd1_netc_swt_eth_rxd_netc_swt_eth1_rxd1>, + <&iomuxc_eth1_rxd2_netc_swt_eth_rxd_netc_swt_eth1_rxd2>, + <&iomuxc_eth1_rxd3_netc_swt_eth_rxd_netc_swt_eth1_rxd3>, + <&iomuxc_eth1_tx_en_netc_swt_eth_tx_en_netc_swt_eth1_tx_en>, + <&iomuxc_eth1_tx_er_netc_swt_eth_tx_er_netc_swt_eth1_tx_er>, + <&iomuxc_eth1_txd0_netc_swt_eth_txd_netc_swt_eth1_txd0>, + <&iomuxc_eth1_txd1_netc_swt_eth_txd_netc_swt_eth1_txd1>, + <&iomuxc_eth1_txd2_netc_swt_eth_txd_netc_swt_eth1_txd2>, + <&iomuxc_eth1_txd3_netc_swt_eth_txd_netc_swt_eth1_txd3>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + group2 { + pinmux = <&iomuxc_eth1_rx_clk_netc_swt_eth_rx_clk_netc_swt_eth1_rx_clk>, + <&iomuxc_eth1_tx_clk_netc_swt_eth_tx_clk_netc_swt_eth1_tx_clk>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + }; + + eth2_default: eth2_default { + group1 { + pinmux = + <&iomuxc_eth2_rx_ctl_netc_enetc_swt_eth_rx_ctl_netc_enetc2_swt_eth2_rx_ctl>, + <&iomuxc_eth2_rxd0_netc_enetc_swt_eth_rxd_netc_enetc2_swt_eth2_rxd0>, + <&iomuxc_eth2_rxd1_netc_enetc_swt_eth_rxd_netc_enetc2_swt_eth2_rxd1>, + <&iomuxc_eth2_rxd2_netc_enetc_swt_eth_rxd_netc_enetc2_swt_eth2_rxd2>, + <&iomuxc_eth2_rxd3_netc_enetc_swt_eth_rxd_netc_enetc2_swt_eth2_rxd3>, + <&iomuxc_eth2_tx_ctl_netc_enetc_swt_eth_tx_ctl_netc_enetc2_swt_eth2_tx_ctl>, + <&iomuxc_eth2_txd0_netc_enetc_swt_eth_txd_netc_enetc2_swt_eth2_txd0>, + <&iomuxc_eth2_txd1_netc_enetc_swt_eth_txd_netc_enetc2_swt_eth2_txd1>, + <&iomuxc_eth2_txd2_netc_enetc_swt_eth_txd_netc_enetc2_swt_eth2_txd2>, + <&iomuxc_eth2_txd3_netc_enetc_swt_eth_txd_netc_enetc2_swt_eth2_txd3>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + group2 { + pinmux = + <&iomuxc_eth2_rx_clk_netc_enetc_swt_eth_rx_clk_netc_enetc2_swt_eth2_rx_clk>, + <&iomuxc_eth2_tx_clk_netc_enetc_swt_eth_tx_clk_netc_enetc2_swt_eth2_tx_clk>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + }; + + eth3_default: eth3_default { + group1 { + pinmux = + <&iomuxc_eth3_rx_ctl_netc_enetc_eth_rx_ctl_netc_enetc1_eth3_rx_ctl>, + <&iomuxc_eth3_rxd0_netc_enetc_eth_rxd_netc_enetc1_eth3_rxd0>, + <&iomuxc_eth3_rxd1_netc_enetc_eth_rxd_netc_enetc1_eth3_rxd1>, + <&iomuxc_eth3_rxd2_netc_enetc_eth_rxd_netc_enetc1_eth3_rxd2>, + <&iomuxc_eth3_rxd3_netc_enetc_eth_rxd_netc_enetc1_eth3_rxd3>, + <&iomuxc_eth3_tx_ctl_netc_enetc_eth_tx_ctl_netc_enetc1_eth3_tx_ctl>, + <&iomuxc_eth3_txd0_netc_enetc_eth_txd_netc_enetc1_eth3_txd0>, + <&iomuxc_eth3_txd1_netc_enetc_eth_txd_netc_enetc1_eth3_txd1>, + <&iomuxc_eth3_txd2_netc_enetc_eth_txd_netc_enetc1_eth3_txd2>, + <&iomuxc_eth3_txd3_netc_enetc_eth_txd_netc_enetc1_eth3_txd3>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + group2 { + pinmux = + <&iomuxc_eth3_rx_clk_netc_enetc_eth_rx_clk_netc_enetc1_eth3_rx_clk>, + <&iomuxc_eth3_tx_clk_netc_enetc_eth_tx_clk_netc_enetc1_eth3_tx_clk>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + }; + + + eth4_default: eth4_default { + group1 { + pinmux = + <&iomuxc_eth4_rx_ctl_netc_enetc_eth_rx_ctl_netc_enetc0_eth4_rx_ctl>, + <&iomuxc_eth4_rxd0_netc_enetc_eth_rxd_netc_enetc0_eth4_rxd0>, + <&iomuxc_eth4_rxd1_netc_enetc_eth_rxd_netc_enetc0_eth4_rxd1>, + <&iomuxc_eth4_rxd2_netc_enetc_eth_rxd_netc_enetc0_eth4_rxd2>, + <&iomuxc_eth4_rxd3_netc_enetc_eth_rxd_netc_enetc0_eth4_rxd3>, + <&iomuxc_eth4_tx_ctl_netc_enetc_eth_tx_ctl_netc_enetc0_eth4_tx_ctl>, + <&iomuxc_eth4_txd0_netc_enetc_eth_txd_netc_enetc0_eth4_txd0>, + <&iomuxc_eth4_txd1_netc_enetc_eth_txd_netc_enetc0_eth4_txd1>, + <&iomuxc_eth4_txd2_netc_enetc_eth_txd_netc_enetc0_eth4_txd2>, + <&iomuxc_eth4_txd3_netc_enetc_eth_txd_netc_enetc0_eth4_txd3>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x6"; + }; + group2 { + pinmux = + <&iomuxc_eth4_rx_clk_netc_enetc_eth_rx_clk_netc_enetc0_eth4_rx_clk>, + <&iomuxc_eth4_tx_clk_netc_enetc_eth_tx_clk_netc_enetc0_eth4_tx_clk>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "x6"; + }; + + }; + + flexio1_io5_default: flexio1_io5_default { + group0 { + pinmux = + <&iomuxc_gpio_io31_flexio_1_3_mux1_flexio5_flexio_1_3_mux1_flexio5>; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; + + lpuart1_default: lpuart1_default { + group0 { + pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>, + <&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; + + lpuart8_default: lpuart8_default { + group0 { + pinmux = <&iomuxc_dap_tclk_swclk_lpuart_rx_lpuart8_rx>, + <&iomuxc_dap_tms_swdio_lpuart_tx_lpuart8_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts new file mode 100644 index 00000000000..92c34f41d6b --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx943_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX943 A55"; + compatible = "fsl,mimx943"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + + cpu@100 { + status = "disabled"; + }; + + cpu@200 { + status = "disabled"; + }; + }; + + dram: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml new file mode 100644 index 00000000000..470b86e0f45 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.yaml @@ -0,0 +1,18 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx943_evk/mimx94398/a55 +name: NXP i.MX943 EVK A55 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - gpio + - uart +vendor: nxp diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_defconfig b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_defconfig new file mode 100644 index 00000000000..f52643966b7 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_a55_defconfig @@ -0,0 +1,33 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=24 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y + +CONFIG_MBOX=y +CONFIG_ARM_SCMI=y diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts new file mode 100644 index 00000000000..f144db44377 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts @@ -0,0 +1,107 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx943_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX943 EVK board"; + compatible = "nxp,imx943_evk"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &lpuart8; + zephyr,shell-uart = &lpuart8; + }; +}; + +&emdio { + pinctrl-0 = <&emdio_default>; + pinctrl-names = "default"; + status = "disabled"; + + phy0: phy@f { + compatible = "ethernet-phy"; + reg = <0xf>; + status = "disabled"; + }; + + phy1: phy@10 { + compatible = "ethernet-phy"; + reg = <0x10>; + status = "disabled"; + }; + + phy2: phy@5 { + compatible = "realtek,rtl8211f"; + reg = <0x5>; + status = "disabled"; + }; + + phy3: phy@6 { + compatible = "realtek,rtl8211f"; + reg = <0x6>; + status = "disabled"; + }; + + phy4: phy@7 { + compatible = "realtek,rtl8211f"; + reg = <0x7>; + status = "disabled"; + }; +}; + +&enetc_psi0 { + pinctrl-0 = <ð2_default>; + pinctrl-names = "default"; + phy-handle = <&phy2>; + phy-connection-type = "rgmii"; + status = "disabled"; +}; + +&enetc_psi1 { + pinctrl-0 = <ð3_default>; + pinctrl-names = "default"; + phy-handle = <&phy3>; + phy-connection-type = "rgmii"; + status = "disabled"; +}; + +&enetc_psi2 { + pinctrl-0 = <ð4_default>; + pinctrl-names = "default"; + phy-handle = <&phy4>; + phy-connection-type = "rgmii"; + status = "disabled"; +}; + +&flexio1 { + status = "okay"; + /* Signal can be checked by the connector J44 Pin10(M1_LED_TP1) via logic analyzer */ + flexio1_pwm: flexio1_pwm { + compatible = "nxp,flexio-pwm"; + #pwm-cells = <3>; + pinctrl-0 = <&flexio1_io5_default>; + pinctrl-names = "default"; + pwm_1 { + pin-id = <5>; + prescaler = <1>; + }; + status = "okay"; + }; +}; + +&lpuart8 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart8_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.yaml b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.yaml new file mode 100644 index 00000000000..f5059517316 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.yaml @@ -0,0 +1,21 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx943_evk/mimx94398/m33 +name: NXP i.MX943 EVK M33 +type: mcu +arch: arm +ram: 256 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - netif:eth + - gpio + - pwm +vendor: nxp diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr.dts b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr.dts new file mode 100644 index 00000000000..75450555de1 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "imx943_evk_mimx94398_m33.dts" + +/ { + model = "NXP i.MX943 EVK board DDR variant"; + + chosen { + zephyr,sram = &ddr; + /delete-property/ zephyr,flash; + }; + + ddr: memory@86000000 { + device_type = "memory"; + reg = <0x86000000 DT_SIZE_M(4)>; + }; +}; diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr.yaml b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr.yaml new file mode 100644 index 00000000000..248cba022ce --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr.yaml @@ -0,0 +1,18 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx943_evk/mimx94398/m33/ddr +name: NXP i.MX943 EVK M33 DDR variant +type: mcu +arch: arm +ram: 4096 +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - netif:eth +vendor: nxp diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr_defconfig b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr_defconfig new file mode 100644 index 00000000000..41008c1ec7f --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_ddr_defconfig @@ -0,0 +1,23 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# clock-related configurations +CONFIG_CLOCK_CONTROL=y + +# serial interface-related configurations +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +# SCMI-related configurations +CONFIG_MBOX=y +CONFIG_MBOX_INIT_PRIORITY=0 +CONFIG_ARM_SCMI=y +CONFIG_ARM_SCMI_NXP_VENDOR_EXTENSIONS=y + +# kernel-related configurations +CONFIG_XIP=n diff --git a/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_defconfig b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_defconfig new file mode 100644 index 00000000000..154aa547ef0 --- /dev/null +++ b/boards/nxp/imx943_evk/imx943_evk_mimx94398_m33_defconfig @@ -0,0 +1,23 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# clock-related configurations +CONFIG_CLOCK_CONTROL=y + +# serial interface-related configurations +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +# SCMI-related configurations +CONFIG_MBOX=y +CONFIG_MBOX_INIT_PRIORITY=0 +CONFIG_ARM_SCMI=y +CONFIG_ARM_SCMI_NXP_VENDOR_EXTENSIONS=y + +# kernel-related configurations +CONFIG_XIP=y diff --git a/boards/nxp/imx95_evk/CMakeLists.txt b/boards/nxp/imx95_evk/CMakeLists.txt index 19302b77d01..8c6c965ce06 100644 --- a/boards/nxp/imx95_evk/CMakeLists.txt +++ b/boards/nxp/imx95_evk/CMakeLists.txt @@ -12,5 +12,118 @@ if (CONFIG_SOF AND CONFIG_BOARD_IMX95_EVK_MIMX9596_M7_DDR) ) endif() +if(CONFIG_BOARD_NXP_SPSDK_IMAGE OR (DEFINED ENV{USE_NXP_SPSDK_IMAGE} + AND "$ENV{USE_NXP_SPSDK_IMAGE}" STREQUAL "y")) + find_program(7Z_EXECUTABLE 7z REQUIRED) + set(FIRMWARE_RELEASE "imx95-19x19-lpddr5-evk-boot-firmware-0.1") + # Parse SPSDK version + execute_process( + COMMAND spsdk --version + OUTPUT_VARIABLE SPSDK_VERSION_OUTPUT + OUTPUT_STRIP_TRAILING_WHITESPACE + ) + string(REGEX MATCH "[0-9]+\\.[0-9]+\\.[0-9]+" SPSDK_VERSION "${SPSDK_VERSION_OUTPUT}") + message(STATUS "SPSDK version is ${SPSDK_VERSION}") + + if(CONFIG_BOARD_IMX95_EVK_MIMX9596_M7) + set(AHAB_CONFIG_FILE "imx95_evk_mimx9596_m7_ahab.yaml") + + file(WRITE ${CMAKE_BINARY_DIR}/zephyr/${AHAB_CONFIG_FILE} + " + family: mimx9596 + revision: a1 + target_memory: standard + output: ${CMAKE_BINARY_DIR}/zephyr/flash.bin + containers: + - binary_container: + path: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/mx95a0-ahab-container.img + - container: + srk_set: none + images: + - lpddr_imem: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/lpddr5_imem_v202311.bin + lpddr_imem_qb: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/lpddr5_imem_qb_v202311.bin + lpddr_dmem: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/lpddr5_dmem_v202311.bin + lpddr_dmem_qb: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/lpddr5_dmem_qb_v202311.bin + oei_ddr: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/oei-m33-ddr.bin + - oei_tcm: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/oei-m33-tcm.bin + - system_manager: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/m33_image-mx95alt.bin + - cortex_m7_app: ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + - v2x_dummy: true + ") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${7Z_EXECUTABLE} x ${ZEPHYR_HAL_NXP_MODULE_DIR}/zephyr/blobs/imx-boot-firmware/${FIRMWARE_RELEASE}.bin -o./imx-boot-firmware -aos -bso0 -bse1 + COMMAND ${7Z_EXECUTABLE} x imx-boot-firmware/${FIRMWARE_RELEASE} -aos -bso0 -bse1 + COMMAND nxpimage ahab export -c ${CMAKE_BINARY_DIR}/zephyr/${AHAB_CONFIG_FILE} + ) + elseif(CONFIG_SOC_MIMX9596_A55) + file(WRITE ${CMAKE_BINARY_DIR}/zephyr/imx95_evk_mimx9596_a55_ahab_primary.yaml + " + family: mimx9596 + revision: a1 + target_memory: standard + output: ${CMAKE_BINARY_DIR}/zephyr/primary_ahab.bin + containers: + - binary_container: + path: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/mx95a0-ahab-container.img + - container: + srk_set: none + images: + - lpddr_imem: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/lpddr5_imem_v202311.bin + lpddr_imem_qb: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/lpddr5_imem_qb_v202311.bin + lpddr_dmem: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/lpddr5_dmem_v202311.bin + lpddr_dmem_qb: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/lpddr5_dmem_qb_v202311.bin + oei_ddr: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/oei-m33-ddr.bin + - oei_tcm: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/oei-m33-tcm.bin + - system_manager: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/m33_image-mx95evk.bin + - spl: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/u-boot-spl.bin-imx95-19x19-lpddr5-evk-sd + - v2x_dummy: true + ") + file(WRITE ${CMAKE_BINARY_DIR}/zephyr/imx95_evk_mimx9596_a55_ahab_secondary.yaml + " + family: mimx9596 + revision: a1 + target_memory: standard + output: ${CMAKE_BINARY_DIR}/zephyr/secondary_ahab.bin + containers: + - container: + srk_set: none + images: + - atf: ${CMAKE_BINARY_DIR}/zephyr/${FIRMWARE_RELEASE}/bl31-imx95-zephyr.bin + - image_path: ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + load_address: '${CONFIG_SRAM_BASE_ADDRESS}' + entry_point: '${CONFIG_SRAM_BASE_ADDRESS}' + image_type: executable + core_id: cortex-a55 + is_encrypted: false + ") + file(WRITE ${CMAKE_BINARY_DIR}/zephyr/imx95_evk_mimx9596_a55_ahab_flash_template.yaml + " + family: mimx9596 + revision: latest + memory_type: serial_downloader + primary_image_container_set: ${CMAKE_BINARY_DIR}/zephyr/imx95_evk_mimx9596_a55_ahab_primary.yaml + secondary_image_container_set: ${CMAKE_BINARY_DIR}/zephyr/imx95_evk_mimx9596_a55_ahab_secondary.yaml + ") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${7Z_EXECUTABLE} x ${ZEPHYR_HAL_NXP_MODULE_DIR}/zephyr/blobs/imx-boot-firmware/${FIRMWARE_RELEASE}.bin -o./imx-boot-firmware -aos -bso0 -bse1 + COMMAND ${7Z_EXECUTABLE} x imx-boot-firmware/${FIRMWARE_RELEASE} -aos -bso0 -bse1 + ) + if(SPSDK_VERSION VERSION_GREATER_EQUAL "3.0.0") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND nxpimage bootable-image export -c ${CMAKE_BINARY_DIR}/zephyr/imx95_evk_mimx9596_a55_ahab_flash_template.yaml -o flash.bin + ) + else() + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND nxpimage bootable-image merge -c ${CMAKE_BINARY_DIR}/zephyr/imx95_evk_mimx9596_a55_ahab_flash_template.yaml -o flash.bin + ) + endif() + else() + message(FATAL_ERROR "SPSDK Image not supported on the platform!") + endif() + zephyr_blobs_verify(FILES + ${ZEPHYR_HAL_NXP_MODULE_DIR}/zephyr/blobs/imx-boot-firmware/${FIRMWARE_RELEASE}.bin + REQUIRED) +endif() + zephyr_library() zephyr_library_sources(board.c) diff --git a/boards/nxp/imx95_evk/Kconfig b/boards/nxp/imx95_evk/Kconfig new file mode 100644 index 00000000000..1fd7aaba5e1 --- /dev/null +++ b/boards/nxp/imx95_evk/Kconfig @@ -0,0 +1,4 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +source "boards/nxp/common/Kconfig" diff --git a/boards/nxp/imx95_evk/Kconfig.defconfig b/boards/nxp/imx95_evk/Kconfig.defconfig new file mode 100644 index 00000000000..9635d000893 --- /dev/null +++ b/boards/nxp/imx95_evk/Kconfig.defconfig @@ -0,0 +1,66 @@ +# Copyright 2024-2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX9596_A55 + +if ETH_NXP_IMX_NETC + +config GIC_V3_ITS + default y + +endif # ETH_NXP_IMX_NETC + +# GIC ITS depends on kernel heap which init priority is 30, so set +# GIC to be 31, mailbox and SCMI will be initialized by the order +# according to dts dependency although they use the same init priority. +config INTC_INIT_PRIORITY + default 31 + +config MBOX_INIT_PRIORITY + default 31 + +config ARM_SCMI_SHMEM_INIT_PRIORITY + default 31 + +config ARM_SCMI_TRANSPORT_INIT_PRIORITY + default 31 + +config CLOCK_CONTROL_INIT_PRIORITY + default 31 + +# Enlarge default networking stack +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +if NET_SOCKETS_SERVICE + +config NET_SOCKETS_SERVICE_STACK_SIZE + default 8192 + +endif # NET_SOCKETS_SERVICE + +endif # NETWORKING + +endif # SOC_MIMX9596_A55 diff --git a/boards/nxp/imx95_evk/board.c b/boards/nxp/imx95_evk/board.c index 477bcc38f6a..2b43501bfec 100644 --- a/boards/nxp/imx95_evk/board.c +++ b/boards/nxp/imx95_evk/board.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * SPDX-License-Identifier: Apache-2.0 */ @@ -10,21 +10,6 @@ static int board_init(void) { -#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0) - /* Port 0 to 2 protocol configure: RGMII, RGMII, XGMII */ - BLK_CTRL_NETCMIX->CFG_LINK_MII_PROT = 0x00000522; - BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_2 = 0x00000040; - - /* Unlock the IERB. It will warm reset whole NETC. */ - NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK; - while ((NETC_PRIV->NETCRR & NETC_PRIV_NETCRR_LOCK_MASK) != 0U) { - } - - /* Lock the IERB. */ - NETC_PRIV->NETCRR |= NETC_PRIV_NETCRR_LOCK_MASK; - while ((NETC_PRIV->NETCSR & NETC_PRIV_NETCSR_STATE_MASK) != 0U) { - } -#endif return 0; } diff --git a/boards/nxp/imx95_evk/board.cmake b/boards/nxp/imx95_evk/board.cmake index 57089c3f1b0..daca6ade79f 100644 --- a/boards/nxp/imx95_evk/board.cmake +++ b/boards/nxp/imx95_evk/board.cmake @@ -3,3 +3,24 @@ if (CONFIG_SOF AND CONFIG_BOARD_IMX95_EVK_MIMX9596_M7_DDR) board_set_rimage_target(imx95) endif() + +if(CONFIG_BOARD_NXP_SPSDK_IMAGE OR (DEFINED ENV{USE_NXP_SPSDK_IMAGE} + AND "$ENV{USE_NXP_SPSDK_IMAGE}" STREQUAL "y")) + board_set_flasher_ifnset(spsdk) + + board_runner_args(spsdk "--family=mimx9596") + board_runner_args(spsdk "--bootloader=${CMAKE_BINARY_DIR}/zephyr/imx95-19x19-lpddr5-evk-boot-firmware-0.1/imx-boot-imx95-19x19-lpddr5-evk-sd.bin-flash_all") + board_runner_args(spsdk "--flashbin=${CMAKE_BINARY_DIR}/zephyr/flash.bin") + if(CONFIG_CPU_CORTEX_A55) + board_runner_args(spsdk "--containers=two") + else() + board_runner_args(spsdk "--containers=one") + endif() + + include(${ZEPHYR_BASE}/boards/common/spsdk.board.cmake) +endif() + +if(CONFIG_SOC_MIMX9596_A55) + board_runner_args(jlink "--device=MIMX9556_A55_0" "--no-reset" "--flash-sram") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx95_evk/doc/index.rst b/boards/nxp/imx95_evk/doc/index.rst index 75aba8fd01d..5df5410a0e3 100644 --- a/boards/nxp/imx95_evk/doc/index.rst +++ b/boards/nxp/imx95_evk/doc/index.rst @@ -106,45 +106,130 @@ Ethernet -------- NETC driver supports to manage the Physical Station Interface (PSI). -The first ENET1 port could be enabled for M7 by west build option -``-DEXTRA_DTC_OVERLAY_FILE=enetc_psi0.overlay``. +The first ENET1 port could be enabled on M7 DDR and A55 platforms. +For A55 Core, NETC depends on GIC ITS, so need to make sure to allocate heap memory to +be larger than 851968 byes by setting CONFIG_HEAP_MEM_POOL_SIZE. Programming and Debugging (A55) ******************************* .. zephyr:board-supported-runners:: -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: +There are multiple methods to program and run Zephyr on the A55 core: + +Option 1. Boot Zephyr by Using SPSDK Runner +=========================================== + +SPSDK runner leverages SPSDK tools (https://spsdk.readthedocs.io), it builds an +bootable flash image ``flash.bin`` which includes all necessary firmware components, +such as ELE+V2X firmware, System Manager, TCM OEI, TF-A images etc. Using west flash +command will download the boot image flash.bin to DDR memory, SD card or eMMC flash. +By using flash.bin, as no U-Boot image is available, so TF-A will boot up Zephyr on +the first Cortex-A55 Core directly. + +In order to use SPSDK runner, it requires fetching binary blobs, which can be achieved +by running the following command: + +.. code-block:: console + + west blobs fetch hal_nxp + +.. note:: + + It is recommended running the command above after :file:`west update`. -1. Build and run the Non-SMP application +SPSDK runner is enabled by configure item :kconfig:option:`CONFIG_BOARD_NXP_SPSDK_IMAGE`, currently +it is not enabled by default for i.MX95 EVK board, so use this configuration to enable +it, for example, with the :zephyr:code-sample:`synchronization` sample: .. zephyr-app-commands:: :zephyr-app: samples/synchronization :host-os: unix :board: imx95_evk/mimx9596/a55 :goals: build + :gen-args: -DCONFIG_BOARD_NXP_SPSDK_IMAGE=y -This will build an image (zephyr.bin) with the synchronization sample app. +If :kconfig:option:`CONFIG_BOARD_NXP_SPSDK_IMAGE` is available and enabled for the board variant, +``flash.bin`` will be built automatically. The programming could be through below commands. +Before that, switch SW7[1:4] should be configured to 0b1001 for usb download mode +to boot, and USB1 and DBG ports should be connected to PC. There are 4 serial ports +enumerated (115200 8n1), and we use the first for M7 and the fourth for M33 System Manager. +(The flasher is spsdk which already installed via scripts/requirements.txt. +On linux host, usb device permission should be configured per Installation Guide +of https://spsdk.readthedocs.io) + +.. code-block:: none + + # load and run without programming. for next flashing, execute 'reset' in the + # fourth serail port + $ west flash -r spsdk + + # program to SD card, then set SW7[1:4]=0b1011 to reboot + $ west flash -r spsdk --bootdevice sd + + # program to emmc card, then set SW7[1:4]=0b1010 to reboot + $ west flash -r spsdk --bootdevice=emmc + + +Option 2. Boot Zephyr by Using U-Boot Command +============================================= + +U-Boot "go" command can be used to start Zephyr on A55 core0 and U-Boot "cpu" command +is used to load and kick Zephyr to the other A55 secondary Cores. Currently "cpu" command +is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y, +xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example +"uboot_v2023.04-2.9.0" branch is U-Boot v2023.04 used in Real-Time Edge Software release +v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Software`_. + +.. _Real-Time Edge U-Boot: + https://github.com/nxp-real-time-edge-sw/real-time-edge-uboot +.. _Real-Time Edge Software: + https://www.nxp.com/rtedge -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. +Step 1: Download Zephyr Image into DDR Memory +--------------------------------------------- -Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: +Firstly need to download Zephyr binary image into DDR memory, it can use tftp: .. code-block:: console - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000 + tftp 0xd0000000 zephyr.bin +Or copy the Zephyr image ``zephyr.bin`` SD card and plug the card into the board, for example +if copy to the FAT partition of the SD card, use the following U-Boot command to load the image +into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed +based on actual setup): -Or use the following command to kick zephyr.bin to Cortex-A55 Core0: +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; + +Step 2: Boot Zephyr +------------------- + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx95_evk/mimx9596/a55 + :goals: build + +This will build an image (zephyr.bin) with the synchronization sample app. + +Then use the following command to boot Zephyr on the core0: .. code-block:: console - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000 + dcache off; icache flush; go 0xd0000000; +Or use "cpu" command to boot from secondary Core, for example Core1: + +.. code-block:: console + + dcache flush; icache flush; cpu 1 release 0xd0000000 It will display the following console output: @@ -157,46 +242,80 @@ It will display the following console output: thread_b: Hello World from cpu 0 on imx95_evk! thread_a: Hello World from cpu 0 on imx95_evk! -2. Build and run the SMP application +Option 3. Boot Zephyr by Using Remoteproc under Linux +===================================================== + +When running Linux on the A55 core, it can use the remoteproc framework to load and boot Zephyr, +refer to Real-Time Edge user guide for more details. Pre-build images and user guide can be found +at `Real-Time Edge Software`_. + +Option 4. Boot Zephyr by Using JLink Runner +=========================================== + +The board support using JLink runner to flash and debug Zephyr, connect the EVK board's JTAG connector +to the host computer using a J-Link debugger. + +If run and debug Zephyr on the Core0, just power up the board and stop the board at U-Boot command line. + +Then use "west flash -r jlink" command to load the zephyr.bin image from the host computer and start +Zephyr, or use "west debug -r jlink" to debug Zephyr. + +Flash and Run +------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: - :zephyr-app: samples/synchronization + :zephyr-app: samples/hello_world :host-os: unix - :board: imx95_evk/mimx9596/a55/smp - :goals: build + :board: imx95_evk/mimx9596/a55 + :goals: flash + :flash-args: -r jlink -This will build an image (zephyr.bin) with the synchronization sample app. +Debug +----- -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. +Here is an example for the :zephyr:code-sample:`hello_world` application. -Use the following command to kick zephyr.bin to Cortex-A55 Core0: +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: imx95_evk/mimx9596/a55 + :goals: debug + :debug-args: -r jlink + +Notes +----- + +If run and debug Zephyr on the other Cortex-A Core except Core0, for example Core2, need to execute the +following command under U-Boot command line to release specific CPU Core to a dead loop state (U-Boot +needs to support "cpu" command, refer to "Option 2. Boot Zephyr by Using U-Boot Command" to get specific +U-Boot version). .. code-block:: console - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000 + mw.l 0xD0000000 14000000; dcache flush; icache flush; cpu 2 release 0xD0000000 +And also need to modify jlink device by using the following update, change device ID MIMX9556_A55_0 to +specified ID, for example MIMX9556_A55_2 for CPU Core2: -It will display the following console output: .. code-block:: console - *** Booting Zephyr OS build v3.7.0-rc3-15-g2f0beaea144a *** - Secondary CPU core 1 (MPID:0x100) is up - Secondary CPU core 2 (MPID:0x200) is up - Secondary CPU core 3 (MPID:0x300) is up - Secondary CPU core 4 (MPID:0x400) is up - Secondary CPU core 5 (MPID:0x500) is up - thread_a: Hello World from cpu 0 on imx95_evk! - thread_b: Hello World from cpu 4 on imx95_evk! - thread_a: Hello World from cpu 0 on imx95_evk! - thread_b: Hello World from cpu 3 on imx95_evk! - thread_a: Hello World from cpu 0 on imx95_evk! - thread_b: Hello World from cpu 1 on imx95_evk! - thread_a: Hello World from cpu 0 on imx95_evk! - thread_b: Hello World from cpu 5 on imx95_evk! - thread_a: Hello World from cpu 0 on imx95_evk! - thread_b: Hello World from cpu 2 on imx95_evk! + diff --git a/boards/nxp/imx95_evk/board.cmake b/boards/nxp/imx95_evk/board.cmake + index daca6ade79f..c58de8c2431 100644 + --- a/boards/nxp/imx95_evk/board.cmake + +++ b/boards/nxp/imx95_evk/board.cmake + @@ -21,6 +21,6 @@ if(CONFIG_BOARD_NXP_SPSDK_IMAGE OR (DEFINED ENV{USE_NXP_SPSDK_IMAGE} + endif() + + if(CONFIG_SOC_MIMX9596_A55) + - board_runner_args(jlink "--device=MIMX9556_A55_0" "--no-reset" "--flash-sram") + + board_runner_args(jlink "--device=MIMX9556_A55_2" "--no-reset" "--flash-sram") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + endif() + +Then use "west flash -r jlink" command to load the zephyr.bin image from the host computer and start +Zephyr, or use "west debug -r jlink" to debug Zephyr. Programming and Debugging (M7) ****************************** @@ -213,13 +332,47 @@ To program M7, an i.MX container image ``flash.bin`` must be made, which contain multiple elements required, like ELE+V2X firmware, System Manager, TCM OEI, Cortex-M7 image and so on. -The steps making flash.bin and programming should refer to ``Getting Started with +SPSDK runner is used to build ``flash.bin``, and it requires fetching binary blobs, which +can be achieved by running the following command: + +.. code-block:: console + + west blobs fetch hal_nxp + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Two methods to build and program ``flash.bin``. + +1. If :kconfig:option:`CONFIG_BOARD_NXP_SPSDK_IMAGE` is not available for the board variant, +the steps making flash.bin and programming should refer to ``Getting Started with MCUXpresso SDK for IMX95LPD5EVK-19.pdf`` in i.MX95 `MCUX SDK release`_. Note that for the DDR variant, one should use the Makefile targets containing the ``ddr`` keyword. - See ``4.2 Run an example application``, just rename ``zephyr.bin`` to ``m7_image.bin`` to make flash.bin and program to SD/eMMC. +2. If :kconfig:option:`CONFIG_BOARD_NXP_SPSDK_IMAGE` is available and enabled for the board variant, +``flash.bin`` will be built automatically. The programming could be through below commands. +Before that, switch SW7[1:4] should be configured to 0b1001 for usb download mode +to boot, and USB1 and DBG ports should be connected to PC. There are 4 serial ports +enumerated (115200 8n1), and we use the first for M7 and the fourth for M33 System Manager. +(The flasher is spsdk which already installed via scripts/requirements.txt. +On linux host, usb device permission should be configured per Installation Guide +of https://spsdk.readthedocs.io) + +.. code-block:: none + + # load and run without programming. for next flashing, execute 'reset' in the + # fourth serail port + $ west flash + + # program to SD card, then set SW7[1:4]=0b1011 to reboot + $ west flash --bootdevice sd + + # program to emmc card, then set SW7[1:4]=0b1010 to reboot + $ west flash --bootdevice=emmc + Zephyr supports two M7-based i.MX95 boards: ``imx95_evk/mimx9596/m7`` and ``imx95_evk/mimx9596/m7/ddr``. The main difference between them is the memory used. ``imx95_evk/mimx9596/m7`` uses TCM (ITCM for code and, generally, read-only diff --git a/boards/nxp/imx95_evk/dts/enetc_psi0.overlay b/boards/nxp/imx95_evk/dts/enetc_psi0.overlay deleted file mode 100644 index 2e24f5ff94b..00000000000 --- a/boards/nxp/imx95_evk/dts/enetc_psi0.overlay +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2025 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&emdio { - status = "okay"; - - phy0: phy@1 { - status = "okay"; - }; -}; - -&enetc_psi0 { - status = "okay"; -}; diff --git a/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi b/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi index 607e84753d8..9bdda182eb2 100644 --- a/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi +++ b/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi @@ -42,6 +42,26 @@ }; + flexspi_default: flexspi_default { + group0 { + pinmux = <&iomuxc_xspi1_sclk_flexspi_a_sclk_flexspi1_a_sclk>, + <&iomuxc_xspi1_ss0_b_flexspi_a_ss_b_flexspi1_a_ss0_b>, + <&iomuxc_xspi1_ss1_b_flexspi_a_ss_b_flexspi1_a_ss1_b>, + <&iomuxc_xspi1_dqs_flexspi_a_dqs_flexspi1_a_dqs>, + <&iomuxc_xspi1_data0_flexspi_a_data_bit_flexspi1_a_data_bit0>, + <&iomuxc_xspi1_data1_flexspi_a_data_bit_flexspi1_a_data_bit1>, + <&iomuxc_xspi1_data2_flexspi_a_data_bit_flexspi1_a_data_bit2>, + <&iomuxc_xspi1_data3_flexspi_a_data_bit_flexspi1_a_data_bit3>, + <&iomuxc_xspi1_data4_flexspi_a_data_bit_flexspi1_a_data_bit4>, + <&iomuxc_xspi1_data5_flexspi_a_data_bit_flexspi1_a_data_bit5>, + <&iomuxc_xspi1_data6_flexspi_a_data_bit_flexspi1_a_data_bit6>, + <&iomuxc_xspi1_data7_flexspi_a_data_bit_flexspi1_a_data_bit7>; + bias-pull-down; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; + lpi2c5_default: lpi2c5_default { group0 { pinmux = <&iomuxc_gpio_io23_lpi2c_scl_lpi2c5_scl>, @@ -96,6 +116,16 @@ }; }; + lpuart5_default: lpuart5_default { + group0 { + pinmux = <&iomuxc_gpio_io01_lpuart_rx_lpuart5_rx>, + <&iomuxc_gpio_io00_lpuart_tx_lpuart5_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; + sai3_default: sai3_default { group0 { pinmux = <&iomuxc_gpio_io16_sai_tx_bclk_sai3_tx_bclk>, diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts index d4aff0f100d..0ba83b5bf96 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx95_evk-pinctrl.dtsi" / { @@ -43,10 +43,35 @@ }; dram: memory@d0000000 { - reg = <0xd0000000 DT_SIZE_M(1)>; + reg = <0xd0000000 DT_SIZE_M(10)>; }; }; +&emdio { + pinctrl-0 = <&emdio_default>; + pinctrl-names = "default"; + status = "okay"; + + phy0: phy@1 { + compatible = "realtek,rtl8211f"; + reg = <0x1>; + status = "okay"; + }; +}; + +&enetc_psi0 { + local-mac-address = [00 00 00 01 02 00]; + pinctrl-0 = <ð0_default>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-connection-type = "rgmii"; + status = "okay"; +}; + +&enetc_ptp_clock { + status = "okay"; +}; + &lpi2c5 { pinctrl-0 = <&lpi2c5_default>; pinctrl-names = "default"; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml index a4597d08db3..d0f7816c5d7 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml @@ -1,5 +1,5 @@ # -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: Apache-2.0 # @@ -16,4 +16,8 @@ supported: - counter - i2c - uart + - net +testing: + binaries: + - flash.bin vendor: nxp diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig index 23e5dd52c5a..88a5148a54e 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig @@ -31,5 +31,3 @@ CONFIG_CLOCK_CONTROL=y CONFIG_MBOX=y CONFIG_ARM_SCMI=y -CONFIG_INTC_INIT_PRIORITY=2 -CONFIG_MBOX_INIT_PRIORITY=3 diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts index 3dec65cf983..5eba5dc2b5e 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx95_evk-pinctrl.dtsi" / { diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts index bfb43284081..6c5167634d2 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,12 +26,12 @@ &emdio { pinctrl-0 = <&emdio_default>; pinctrl-names = "default"; - status = "disabled"; + status = "okay"; phy0: phy@1 { compatible = "realtek,rtl8211f"; reg = <0x1>; - status = "disabled"; + status = "okay"; }; }; @@ -41,7 +41,57 @@ pinctrl-names = "default"; phy-handle = <&phy0>; phy-connection-type = "rgmii"; - status = "disabled"; + status = "okay"; +}; + +&enetc_ptp_clock { + status = "okay"; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + pinctrl-0 = <&flexspi_default>; + pinctrl-names = "default"; + mt35xu01gbba: mt35xu01gbba@0 { + compatible = "nxp,imx-flexspi-nor"; + size = ; + reg = <0>; + spi-max-frequency = <200000000>; + status = "okay"; + jedec-id = [2c 5b 1b]; + erase-block-size = <4096>; + write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Partition sizes must be aligned + * to the flash memory sector size of 4KB. + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 DT_SIZE_M(7)>; + }; + slot1_partition: partition@720000 { + label = "image-1"; + reg = <0x00720000 DT_SIZE_M(7)>; + }; + storage_partition: partition@E20000 { + label = "storage"; + reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>; + }; + }; + }; }; &lpi2c5 { @@ -69,6 +119,13 @@ pinctrl-names = "default"; }; +&lpuart5 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart5_default>; + pinctrl-names = "default"; +}; + &sai3 { pinctrl-0 = <&sai3_default>; pinctrl-names = "default"; @@ -83,3 +140,7 @@ &lptmr2 { status = "okay"; }; + +&edma2 { + status = "okay"; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml index 2d4eade0557..c36640e0d05 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml @@ -20,4 +20,8 @@ supported: - spi - netif:eth - counter + - dma +testing: + binaries: + - flash.bin vendor: nxp diff --git a/boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15 b/boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15 new file mode 100644 index 00000000000..7ec64a53b83 --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15 @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX95_EVK_15X15 + select SOC_MIMX9596_A55 if BOARD_IMX95_EVK_15X15_MIMX9596_A55 + select SOC_PART_NUMBER_MIMX9596AVTXN diff --git a/boards/nxp/imx95_evk_15x15/board.yml b/boards/nxp/imx95_evk_15x15/board.yml new file mode 100644 index 00000000000..88f587e65ff --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/board.yml @@ -0,0 +1,6 @@ +board: + name: imx95_evk_15x15 + full_name: i.MX95 15x15 EVK + vendor: nxp + socs: + - name: mimx9596 diff --git a/boards/nxp/imx95_evk_15x15/doc/index.rst b/boards/nxp/imx95_evk_15x15/doc/index.rst new file mode 100644 index 00000000000..d8cd50dc668 --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/doc/index.rst @@ -0,0 +1,138 @@ +.. zephyr:board:: imx95_evk_15x15 + +Overview +******** + +The i.MX95 EVK (IMX95LP4XEVK-15) board is a platform designed to show the +most commonly used features of the i.MX 95 applications processor. +It is an entry-level development board, which helps developers to get familiar +with the processor before investing a large amount of resources in more +specific designs. The i.MX 95 device on the board comes in a compact +15 x 15 mm package. + +Hardware +******** + +- i.MX 95 applications processor + + - The processor integrates up to six Arm Cortex-A55 cores, and supports + functional safety with built-in Arm Cortex-M33 and -M7 cores + +- DRAM memory: 8-Gbit LPDDR4x DRAM +- eMMC: 64 GB Micron eMMC +- USB interface: Two USB ports: Type-A and Type-C +- Audio codec interface + + - One audio codec WM8962B + - One 3.5 mm 4-pole CTIA standard audio jack + - One 4-pin connector to connect speaker + +- Ethernet interface + + - ENET2 controller + + - Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45 + connector connected with an external PHY, RTL8211 + + - ENET1 controller + + - Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45 + connector connected with an external PHY, RTL8211 + +- M.2 interface: One Wi-Fi/Bluetooth Murata Type-2EL module based on NXP AW612 + chip supporting 1x1 Wi-Fi 6 and Bluetooth 5.3 + +- MIPI CSI interface: Connects to one 22-pin or 36-pin miniSAS connector using x4 lane + configuration +- MIPI CSIDSI interface: Connects to one 36-pin miniSAS connector using x4 lane + configuration +- LVDS interface: two mini-SAS connectors each with x4-lane configuration +- CAN interface: One 4-pin CAN headers for external connection +- SD card interface: one 4-bit SD3.0 microSD card +- I2C interface: I2C1 to I2C6 controllers +- FT4232H I2C interface: PCT2075 temperature sensor and current monitoring devices +- ADC interface: two 4-channel ADC header +- Debug interface + + - One USB-to-UART/MPSSE device, FT4232H + - One USB 2.0 Type-C connector (J31) for FT4232H provides quad serial ports + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz for Cortex-A55. +Cortex-A55 Core runs up to 1.8 GHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART1 for Cortex-A55. + +Programming and Debugging (A55) +******************************* + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +1. Build and run the Non-SMP application + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx95_evk_15x15/mimx9596/a55 + :goals: build + +This will build an image (zephyr.bin) with the synchronization sample app. + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000 + + +Or use the following command to kick zephyr.bin to Cortex-A55 Core0: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000 + + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 *** + thread_a: Hello World from cpu 0 on imx95_evk_15x15! + thread_b: Hello World from cpu 0 on imx95_evk_15x15! + thread_a: Hello World from cpu 0 on imx95_evk_15x15! + thread_b: Hello World from cpu 0 on imx95_evk_15x15! + thread_a: Hello World from cpu 0 on imx95_evk_15x15! + +.. _System Control and Management Interface (SCMI): + https://developer.arm.com/documentation/den0056/latest/ + +.. _i.MX Linux BSP release: + https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX + +.. _MCUX SDK release: + https://mcuxpresso.nxp.com/ + +References +========== + +More information can refer to NXP official website: +`NXP website`_. + +.. _NXP website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-95-applications-processor-family-high-performance-safety-enabled-platform-with-eiq-neutron-npu:iMX95 diff --git a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi new file mode 100644 index 00000000000..cfe6eebb51c --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + + lpuart1_default: lpuart1_default { + group0 { + pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>, + <&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; + + lpuart3_default: lpuart3_default { + group0 { + pinmux = <&iomuxc_gpio_io15_lpuart_rx_lpuart3_rx>, + <&iomuxc_gpio_io14_lpuart_tx_lpuart3_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; +}; diff --git a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.dts b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.dts new file mode 100644 index 00000000000..38e28f41ce7 --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx95_evk_15x15-pinctrl.dtsi" + +/ { + model = "NXP i.MX95 15x15 A55"; + compatible = "fsl,mimx95"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + + cpu@100 { + status = "disabled"; + }; + + cpu@200 { + status = "disabled"; + }; + + cpu@300 { + status = "disabled"; + }; + + cpu@400 { + status = "disabled"; + }; + }; + + dram: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.yaml b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.yaml new file mode 100644 index 00000000000..2d7f8c35597 --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.yaml @@ -0,0 +1,18 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx95_evk_15x15/mimx9596/a55 +name: NXP i.MX95 15x15 EVK A55 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - uart + - counter +vendor: nxp diff --git a/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55_defconfig b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55_defconfig new file mode 100644 index 00000000000..962f30006cf --- /dev/null +++ b/boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55_defconfig @@ -0,0 +1,35 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y + +CONFIG_MBOX=y +CONFIG_ARM_SCMI=y +CONFIG_INTC_INIT_PRIORITY=2 +CONFIG_MBOX_INIT_PRIORITY=3 diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi index f363d52a886..f86b4e0d655 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi @@ -64,4 +64,23 @@ slew-rate = "standard"; }; }; + + pinmux_sdif_default: pinmux_sdif_default { + group0 { + pinmux = , + , + , + , + , + , + ; + slew-rate = "fast"; + }; + + group1 { + pinmux = , + ; + slew-rate = "standard"; + }; + }; }; diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts index d9d46ed50ed..f7912ac14b0 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts @@ -126,6 +126,7 @@ zephyr_udc0: &usbhs { status = "okay"; + phy-handle = <&usbphy1>; }; zephyr_uhc0: &usbhfs { @@ -138,7 +139,7 @@ zephyr_uhc1: &usbhhs { pinctrl-0 = <&pinmux_usbhhs>; pinctrl-names = "default"; status = "okay"; - phy_handle = <&usbphy1>; + phy-handle = <&usbphy1>; }; &usbphy1 { @@ -147,3 +148,15 @@ zephyr_uhc1: &usbhhs { tx-cal-45-dp-ohms = <10>; tx-cal-45-dm-ohms = <10>; }; + +&sdif { + status = "okay"; + pinctrl-0 = <&pinmux_sdif_default>; + pinctrl-names = "default"; + + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + disk-name = "SD"; + }; +}; diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts index 44caca0d327..5049eec3f5f 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts @@ -165,7 +165,7 @@ zephyr_uhc1: &usbhhs { pinctrl-0 = <&pinmux_usbhhs>; pinctrl-names = "default"; status = "okay"; - phy_handle = <&usbphy1>; + phy-handle = <&usbphy1>; }; &usbphy1 { diff --git a/boards/nxp/mcx_n9xx_evk/Kconfig.defconfig b/boards/nxp/mcx_n9xx_evk/Kconfig.defconfig index 286acdad25f..3defc126f7e 100644 --- a/boards/nxp/mcx_n9xx_evk/Kconfig.defconfig +++ b/boards/nxp/mcx_n9xx_evk/Kconfig.defconfig @@ -14,11 +14,4 @@ config MAIN_STACK_SIZE endif -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - endif diff --git a/boards/nxp/mcx_n9xx_evk/Kconfig.sysbuild b/boards/nxp/mcx_n9xx_evk/Kconfig.sysbuild deleted file mode 100644 index 4625c7d2929..00000000000 --- a/boards/nxp/mcx_n9xx_evk/Kconfig.sysbuild +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice MCUBOOT_MODE - default MCUBOOT_MODE_OVERWRITE_ONLY -endchoice diff --git a/boards/nxp/mcx_n9xx_evk/board.c b/boards/nxp/mcx_n9xx_evk/board.c index 5b5a13c1ae9..760812971a3 100644 --- a/boards/nxp/mcx_n9xx_evk/board.c +++ b/boards/nxp/mcx_n9xx_evk/board.c @@ -325,6 +325,11 @@ void board_early_init_hook(void) CLOCK_AttachClk(kFRO_HF_to_ADC0); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc1)) + CLOCK_SetClkDiv(kCLOCK_DivAdc1Clk, 1U); + CLOCK_AttachClk(kFRO_HF_to_ADC1); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb0)) && (CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS) CLOCK_AttachClk(kCLK_48M_to_USB0); CLOCK_EnableClock(kCLOCK_Usb0Ram); diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk.dtsi b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk.dtsi index e85fcff4ffd..b159581e3cf 100644 --- a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk.dtsi +++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk.dtsi @@ -135,9 +135,6 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(80)>; }; - /* For the MCUBoot "upgrade only" method, - * the slot sizes must be equal. - */ slot0_partition: partition@14000 { label = "image-0"; reg = <0x00014000 DT_SIZE_K(984)>; diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts index f6e9db814cb..7f718db2e6d 100644 --- a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts +++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts @@ -19,6 +19,7 @@ chosen { zephyr,flash = &w25q64jwtbjq; + zephyr,flash-controller = &w25q64jwtbjq; }; }; diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.yaml b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.yaml index 0aa11cb627f..0ec1320c246 100644 --- a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.yaml +++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.yaml @@ -5,7 +5,7 @@ # identifier: mcx_n9xx_evk/mcxn947/cpu1 -name: NXP FRDM MCXN947 (CPU1) +name: NXP MCX-N9XX-EVK (CPU1) type: mcu arch: arm ram: 64 diff --git a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts index 41e634bfecf..751541d3d26 100644 --- a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts +++ b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts @@ -61,6 +61,35 @@ status = "okay"; }; }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpiod 1 0>, /* A0 */ + <1 0 &gpiod 2 0>, /* A1 */ + <2 0 &gpiod 3 0>, /* A2 */ + <3 0 &gpioa 4 0>, /* A3 */ + <4 0 &gpioc 3 0>, /* A4 */ + <5 0 &gpioc 2 0>, /* A5 */ + <6 0 &gpioa 16 0>, /* D0 */ + <7 0 &gpioa 17 0>, /* D1 */ + <8 0 &gpioc 4 0>, /* D2 */ + <9 0 &gpioc 5 0>, /* D3 */ + <10 0 &gpioa 19 0>, /* D4 */ + <11 0 &gpioc 1 0>, /* D5 */ + <12 0 &gpioa 20 0>, /* D6 */ + <13 0 &gpioa 21 0>, /* D7 */ + <14 0 &gpioc 4 0>, /* D8 */ + <15 0 &gpioa 18 0>, /* D9 */ + <16 0 &gpiob 0 0>, /* D10 */ + <17 0 &gpiob 3 0>, /* D11 */ + <18 0 &gpiob 1 0>, /* D12 */ + <19 0 &gpiob 2 0>, /* D13 */ + <20 0 &gpiob 4 0>, /* D14 */ + <21 0 &gpiob 5 0>; /* D15 */ + }; }; &gpioa { diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts index 29d52275d89..e5206937193 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts @@ -97,11 +97,11 @@ arduino_serial: &lpuart2 { reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25lp064: is25lp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; - jedec-id = [9d 70 17]; + jedec-id = [9d 60 17]; erase-block-size = <4096>; write-block-size = <1>; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi index 0886b2ac912..d9f27f8c29c 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi @@ -183,7 +183,7 @@ zephyr_lcdif: &lcdif { pinctrl-0 = <&pinmux_enet>; pinctrl-names = "default"; phy-handle = <&phy>; - zephyr,random-mac-address; + nxp,unique-mac; phy-connection-type = "rmii"; }; @@ -213,12 +213,12 @@ zephyr_udc0: &usb1 { zephyr_uhc0: &usbh1 { status = "okay"; - phy_handle = <&usbphy1>; + phy-handle = <&usbphy1>; }; zephyr_uhc1: &usbh2 { status = "okay"; - phy_handle = <&usbphy2>; + phy-handle = <&usbphy2>; }; &usbphy1 { diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts index fa124ba3570..7cf60300b68 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts @@ -34,7 +34,7 @@ word-addressable; cs-interval-unit = <1>; cs-interval = <2>; - cs-hold-time = <0>; + cs-hold-time = <3>; cs-setup-time = <3>; data-valid-time = <1>; column-space = <3>; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts index 47e46ce6ee4..0ebe7520216 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts @@ -22,7 +22,7 @@ reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; diff --git a/boards/nxp/mimxrt1060_evk/board.cmake b/boards/nxp/mimxrt1060_evk/board.cmake index 9fe7e3718ea..7711aaf963a 100644 --- a/boards/nxp/mimxrt1060_evk/board.cmake +++ b/boards/nxp/mimxrt1060_evk/board.cmake @@ -27,6 +27,6 @@ elseif ("${BOARD_QUALIFIERS}" MATCHES "hyperflash") board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash") endif() +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst index d2a04b18421..0935c50e51b 100644 --- a/boards/nxp/mimxrt1060_evk/doc/index.rst +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -313,7 +313,7 @@ This board supports 3 debug host tools. Please install your preferred host tool, then follow the instructions in `Configuring a Debug Probe`_ to configure the board appropriately. -* :ref:`jlink-debug-host-tools` (Default, Supported by NXP) +* :ref:`jlink-debug-host-tools` (Supported by NXP) * :ref:`linkserver-debug-host-tools` (Supported by NXP) * :ref:`pyocd-debug-host-tools` (Not Supported by NXP) @@ -438,7 +438,7 @@ Shield for M.2 Wi-Fi and BT Interface Rev C version is tested with :ref:`nxp_m2_wifi_bt` shield to attach any M.2 module with BT HCI UART interface and Wi-Fi SDIO interface. The shield binds the required NXP HCI driver or SDIO driver to perform firmware-load and other setup configurations -for NXP SoC IW416/IW612. +for NXP SoC IW416/IW612/IW610. Troubleshooting =============== diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi index 3b8bae22183..148d29cb661 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi @@ -21,7 +21,7 @@ }; }; - /* conflicts with lpuart3 */ + /* conflicts with lpuart3 and lpuart8 */ pinmux_csi: pinmux_csi { group0 { pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>; @@ -302,6 +302,33 @@ }; }; + pinmux_lpuart8: pinmux_lpuart8 { + group0 { + pinmux = <&iomuxc_gpio_ad_b1_11_lpuart8_rx>, + <&iomuxc_gpio_ad_b1_10_lpuart8_tx>; + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + }; + + pinmux_lpuart8_sleep: pinmux_lpuart8_sleep { + group0 { + pinmux = <&iomuxc_gpio_ad_b1_11_gpio1_io27>; + drive-strength = "r0"; + bias-pull-up; + bias-pull-up-value = "100k"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + group1 { + pinmux = <&iomuxc_gpio_ad_b1_10_lpuart8_tx>; + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + }; + }; + pinmux_lpuart3_sleep: pinmux_lpuart3_sleep { group0 { pinmux = <&iomuxc_gpio_ad_b1_06_gpio1_io22>; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi index 4143a7b6430..3fefd221c0f 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi @@ -148,6 +148,13 @@ arduino_i2c: &lpi2c1 { pinctrl-names = "default", "sleep"; }; +&lpuart8 { + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart8>; + pinctrl-1 = <&pinmux_lpuart8_sleep>; + pinctrl-names = "default", "sleep"; +}; + &enet_mac { status = "okay"; pinctrl-0 = <&pinmux_enet>; @@ -190,12 +197,12 @@ zephyr_udc0: &usb1 { zephyr_uhc0: &usbh1 { status = "okay"; - phy_handle = <&usbphy1>; + phy-handle = <&usbphy1>; }; zephyr_uhc1: &usbh2 { status = "okay"; - phy_handle = <&usbphy2>; + phy-handle = <&usbphy2>; }; &usbphy1 { diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts index 392675c9a0b..6a7e9d1e693 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts @@ -32,7 +32,7 @@ word-addressable; cs-interval-unit = <1>; cs-interval = <2>; - cs-hold-time = <0>; + cs-hold-time = <3>; cs-setup-time = <3>; data-valid-time = <1>; column-space = <3>; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts index bf24282e161..39f72f29dbe 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts @@ -24,7 +24,7 @@ reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.overlay index 284679eaa9f..3a8aabbf032 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.overlay +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.overlay @@ -4,6 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ +/ { + /* FLEXPWM not routed to LED on this EVK */ + pwmleds { + status = "disabled"; + }; +}; + /* FLEXPWM not routed to LED on this EVK */ &flexpwm2_pwm3 { status = "disabled"; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay index 284679eaa9f..da558e3b5c5 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay @@ -4,6 +4,18 @@ * SPDX-License-Identifier: Apache-2.0 */ +/ { + aliases { + i2s-codec-tx = &sai1; + i2s-tx = &sai1; + }; + + /* FLEXPWM not routed to LED on this EVK */ + pwmleds { + status = "disabled"; + }; +}; + /* FLEXPWM not routed to LED on this EVK */ &flexpwm2_pwm3 { status = "disabled"; @@ -13,3 +25,18 @@ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; label = "User LED1"; }; + +&lpi2c1 { + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + audio_codec: wm8962@1a { + compatible = "wolfson,wm8962"; + reg = <0x1a>; + clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>; + clock-names = "mclk"; + }; + +}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.yaml index 2a1c3311647..a8600ac2bfe 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.yaml +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.yaml @@ -25,6 +25,7 @@ supported: - dma - gpio - i2c + - i2s - netif:eth - sdhc - spi diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts index af31e2168e1..5373d5a8131 100644 --- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts @@ -193,7 +193,7 @@ word-addressable; cs-interval-unit = <1>; cs-interval = <2>; - cs-hold-time = <0>; + cs-hold-time = <3>; cs-setup-time = <3>; data-valid-time = <1>; column-space = <3>; diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts index 0ad53064524..c57860d7f22 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts @@ -162,7 +162,7 @@ nxp_parallel_i2c: &lpi2c1 {}; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; - size = ; + size = ; reg = <0>; spi-max-frequency = <104000000>; status = "okay"; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi index 15ad56deb2d..1d2369893e0 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi @@ -141,7 +141,7 @@ }; }; - pinmux_lpadc0: pinmux_lpadc0 { + pinmux_lpadc1: pinmux_lpadc1 { group0 { pinmux = <&iomuxc_gpio_ad_06_adc1_ch0a>; drive-strength = "high"; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi index bf272c435fc..e30ad84fd30 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi @@ -97,7 +97,7 @@ reg = <0>; spi-max-frequency = <104000000>; status = "okay"; - jedec-id = [9d 70 17]; + jedec-id = [9d 70 18]; erase-block-size = <4096>; write-block-size = <1>; @@ -201,8 +201,8 @@ pinctrl-names = "default"; }; -&lpadc0 { - pinctrl-0 = <&pinmux_lpadc0>; +&lpadc1 { + pinctrl-0 = <&pinmux_lpadc1>; pinctrl-names = "default"; }; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts index 475a166e787..7496dce5b2d 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1160_evk.dtsi" / { @@ -20,7 +20,7 @@ * sram region is changed and DMA is in use, you will * encounter issues! */ - zephyr,sram = &ocram; + zephyr,sram = &sram1; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; zephyr,flash-controller = &is25wp128; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts index daf97cca88c..d9a56f6e4ba 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1160_evk.dtsi" / { @@ -108,7 +108,7 @@ status = "okay"; }; -&lpadc0 { +&lpadc1 { status = "okay"; }; diff --git a/boards/nxp/mimxrt1170_evk/board.cmake b/boards/nxp/mimxrt1170_evk/board.cmake index 8781a87cdd6..f2227d38e31 100644 --- a/boards/nxp/mimxrt1170_evk/board.cmake +++ b/boards/nxp/mimxrt1170_evk/board.cmake @@ -6,10 +6,7 @@ if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX) board_runner_args(pyocd "--target=mimxrt1170_cm7") - board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load") - # ITCM is not defined in RT1170's LinkServer device file - board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x00000000\",\ - \"size\":\"0x00040000\",\"type\":\"RAM\"\}") + board_runner_args(jlink "--device=MIMXRT1176xxxA_M7") if(${BOARD_REVISION} STREQUAL "A") board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") @@ -30,6 +27,11 @@ elseif(CONFIG_SOC_MIMXRT1176_CM4) board_runner_args(linkserver "--core=cm4") endif() +if(NOT SYSBUILD) + board_runner_args(jlink "--no-reset") + board_runner_args(linkserver "--no-reset") +endif() + include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi index d33ed7cfb33..3d5a3c013bb 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi @@ -201,7 +201,7 @@ }; }; - pinmux_lpadc0: pinmux_lpadc0 { + pinmux_lpadc1: pinmux_lpadc1 { group0 { pinmux = <&iomuxc_gpio_ad_06_adc1_ch0a>; drive-strength = "high"; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi index 0ec66b87b2f..91bd93ac8ea 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi @@ -49,9 +49,43 @@ pwms = <&flexpwm1_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; }; + + arduino_header: connector { + /* NOTE: + * The CM7 has no interrupt numbers for gpio9/gpio11/gpio12, so it isn't possible + * to use input interrupts with A0-A5 or D0-D15. + * The CM4 does support input interrupts. + */ + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio9 9 0>, /* A0 */ + <1 0 &gpio9 10 0>, /* A1 */ + <2 0 &gpio9 11 0>, /* A2 */ + <3 0 &gpio9 12 0>, /* A3 */ + <4 0 &gpio9 8 0>, /* A4 */ + <5 0 &gpio9 7 0>, /* A5 */ + <6 0 &gpio11 12 0>, /* D0 */ + <7 0 &gpio11 11 0>, /* D1 */ + <8 0 &gpio11 13 0>, /* D2 */ + <9 0 &gpio9 3 0>, /* D3 */ + <10 0 &gpio9 5 0>, /* D4 */ + <11 0 &gpio9 4 0>, /* D5 */ + <12 0 &gpio8 31 0>, /* D6 */ + <13 0 &gpio9 13 0>, /* D7 */ + <14 0 &gpio9 6 0>, /* D8 */ + <15 0 &gpio9 0 0>, /* D9 */ + <16 0 &gpio9 28 0>, /* D10 */ + <17 0 &gpio9 29 0>, /* D11 */ + <18 0 &gpio9 30 0>, /* D12 */ + <19 0 &gpio9 27 0>, /* D13 */ + <20 0 &gpio12 4 0>, /* D14 */ + <21 0 &gpio12 5 0>; /* D15 */ + }; }; -&lpi2c5 { +arduino_i2c: &lpi2c5 { status = "okay"; pinctrl-0 = <&pinmux_lpi2c5>; pinctrl-names = "default"; @@ -78,7 +112,8 @@ current-speed = <115200>; }; -&lpuart2 { +arduino_serial: &lpuart2 { + /* No HW flow control possible for Arduino Header due to missing LPUART2 RTS on D3 */ pinctrl-0 = <&pinmux_lpuart2>; pinctrl-1 = <&pinmux_lpuart2_sleep>; pinctrl-names = "default", "sleep"; @@ -180,7 +215,7 @@ pinctrl-names = "default"; }; -&lpspi1 { +arduino_spi: &lpspi1 { pinctrl-0 = <&pinmux_lpspi1>; pinctrl-names = "default"; }; @@ -196,8 +231,8 @@ pinctrl-names = "default"; }; -&lpadc0 { - pinctrl-0 = <&pinmux_lpadc0>; +&lpadc1 { + pinctrl-0 = <&pinmux_lpadc1>; pinctrl-names = "default"; }; @@ -224,7 +259,7 @@ reg = <0>; spi-max-frequency = <104000000>; status = "okay"; - jedec-id = [9d 70 17]; + jedec-id = [9d 70 18]; erase-block-size = <4096>; write-block-size = <1>; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts index 25978af90dc..83cc63bfce9 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1170_evk.dtsi" / { diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts index 0da2e365a25..9d01d947e52 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "mimxrt1170_evk.dtsi" / { @@ -118,7 +118,7 @@ nxp_mipi_i2c: &lpi2c5 { #size-cells = <0>; }; -&lpadc0 { +&lpadc1 { status = "okay"; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index 2a13ccbd635..fa5fb867959 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -6,7 +6,6 @@ / { chosen { - zephyr,flash = &w25q512nw; zephyr,flash-controller = &w25q512nw; zephyr,flash = &w25q512nw; zephyr,code-partition = &slot0_partition; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi index 38afe5b0445..d05530a66f3 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi @@ -9,7 +9,7 @@ / { aliases { - led0 = &green_led; + led0 = &red_led; sw0 = &user_button; pwm-led0 = &green_pwm_led; sdhc0 = &usdhc1; @@ -17,9 +17,9 @@ leds { compatible = "gpio-leds"; - green_led: led-1 { - gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; - label = "User LED D6"; + red_led: led-2 { + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + label = "User LED D7"; }; }; @@ -162,10 +162,6 @@ status = "okay"; }; -&green_led { - status = "okay"; -}; - &gpio1 { status = "okay"; }; diff --git a/boards/nxp/mimxrt700_evk/CMakeLists.txt b/boards/nxp/mimxrt700_evk/CMakeLists.txt index 32c47fe3d95..f1791d8f7f8 100644 --- a/boards/nxp/mimxrt700_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt700_evk/CMakeLists.txt @@ -26,3 +26,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) zephyr_library_sources(${RT7XX_BOARD_DIR}/flash_config/flash_config.c) zephyr_library_include_directories(${RT7XX_BOARD_DIR}/flash_config) endif() + +if(CONFIG_IMX_USDHC) + zephyr_compile_definitions(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1) +endif() diff --git a/boards/nxp/mimxrt700_evk/board.c b/boards/nxp/mimxrt700_evk/board.c index b50ea6b178d..d3e24ed9b48 100644 --- a/boards/nxp/mimxrt700_evk/board.c +++ b/boards/nxp/mimxrt700_evk/board.c @@ -434,10 +434,34 @@ void board_early_init_hook(void) DT_PROP_BY_PHANDLE(DT_NODELABEL(usb0), clocks, clock_frequency)); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC + /*Make sure USDHC ram buffer has power up*/ + POWER_DisablePD(kPDRUNCFG_APD_SDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_SDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + POWER_ApplyPD(); + + /* USDHC0 */ + /* usdhc depend on 32K clock also */ + CLOCK_AttachClk(kLPOSC_DIV32_to_32K_WAKE); + CLOCK_InitAudioPfd(kCLOCK_Pfd0, 24U); /* Target 400MHZ. */ + CLOCK_AttachClk(kAUDIO_PLL_PFD0_to_SDIO0); + CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); + RESET_ClearPeripheralReset(kUSDHC0_RST_SHIFT_RSTn); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) CLOCK_AttachClk(kLPOSC_to_WWDT0); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sai0), okay) + /* SAI clock 368.64 / 15 = 24.576MHz */ + CLOCK_AttachClk(kAUDIO_PLL_PFD3_to_AUDIO_VDD2); + CLOCK_AttachClk(kAUDIO_VDD2_to_SAI012); + CLOCK_SetClkDiv(kCLOCK_DivSai012Clk, 15U); + RESET_ClearPeripheralReset(kSAI0_RST_SHIFT_RSTn); +#endif + #if DT_NODE_HAS_STATUS(DT_NODELABEL(sc_timer), okay) CLOCK_AttachClk(kFRO0_DIV6_to_SCT); #endif @@ -503,6 +527,11 @@ void board_early_init_hook(void) CLOCK_AttachClk(kSENSE_BASE_to_I3C23); CLOCK_SetClkDiv(kCLOCK_DivI3c23Clk, 4U); #endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(acmp), okay) + CLOCK_EnableClock(kCLOCK_Acmp0); + RESET_ClearPeripheralReset(kACMP0_RST_SHIFT_RSTn); +#endif } static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx) diff --git a/boards/nxp/mimxrt700_evk/board.cmake b/boards/nxp/mimxrt700_evk/board.cmake index 800d65c1ead..77a08ce2509 100644 --- a/boards/nxp/mimxrt700_evk/board.cmake +++ b/boards/nxp/mimxrt700_evk/board.cmake @@ -1,5 +1,5 @@ # -# Copyright 2024 NXP +# Copyright 2024, 2025 NXP # # SPDX-License-Identifier: Apache-2.0 # @@ -13,6 +13,8 @@ elseif(CONFIG_SOC_MIMXRT798S_CM33_CPU1) board_runner_args(jlink "--device=MIMXRT798S_M33_1") board_runner_args(linkserver "--device=MIMXRT798S:MIMXRT700-EVK") board_runner_args(linkserver "--core=cm33_core1") +elseif(CONFIG_SOC_MIMXRT798S_HIFI4) + board_runner_args(jlink "--device=MIMXRT798S_HiFi4") endif() include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/mimxrt700_evk/doc/index.rst b/boards/nxp/mimxrt700_evk/doc/index.rst index a02f8a1c705..3d2ddb0d978 100644 --- a/boards/nxp/mimxrt700_evk/doc/index.rst +++ b/boards/nxp/mimxrt700_evk/doc/index.rst @@ -175,6 +175,9 @@ Connect a USB cable from your PC to J54, and use the serial terminal of your cho Flashing ======== +The DIP switch SW10 selects the boot options. Set SW10 to Off-On (01) to boot from the default +external flash on XSPI0. + Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi b/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi index 1ba82cd4c5e..866a906e0a9 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi @@ -20,6 +20,18 @@ }; }; + pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c { + group0 { + pinmux = , + ; + bias-pull-up; + input-enable; + slew-rate = "normal"; + drive-strength = "high"; + drive-open-drain; + }; + }; + pinmux_flexcomm8_i2c: pinmux_flexcomm8_i2c { group0 { pinmux = , @@ -76,6 +88,21 @@ }; }; + pinmux_sai0: pinmux_sai0 { + group0 { + pinmux = , + , + , + , + , + , + ; + drive-strength = "high"; + slew-rate = "normal"; + input-enable; + }; + }; + pinmux_sctimer: pinmux_sctimer { group0 { pinmux = ; @@ -101,4 +128,51 @@ input-enable; }; }; + + pinmux_usdhc: pinmux_usdhc { + group0 { + pinmux = , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + input-enable; + slew-rate = "normal"; + drive-strength = "normal"; + }; + group1 { + pinmux = ; + bias-pull-down; + input-enable; + slew-rate = "normal"; + drive-strength = "normal"; + }; + group2 { + pinmux = ; + bias-pull-down; + slew-rate = "normal"; + drive-strength = "normal"; + }; + group3 { + pinmux = ; + bias-pull-down; + input-enable; + slew-rate = "slow"; + drive-strength = "normal"; + }; + }; + + pinmux_acmp: pinmux_acmp { + group0 { + pinmux = ; + drive-strength = "normal"; + slew-rate = "normal"; + }; + }; }; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts index df8e0d77bb6..f322a5a7176 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts @@ -22,6 +22,10 @@ sw1 = &user_button_2; watchdog0 = &wwdt0; pwm-0 = &sc_timer; + i2s-codec-tx = &sai0; + i2s-tx = &sai0; + sdhc0 = &usdhc0; + rtc = &rtc0; }; chosen { @@ -127,6 +131,27 @@ pinctrl-names = "default"; }; +&flexcomm2{ + status = "okay"; +}; + +&flexcomm2_lpi2c2 { + status = "okay"; + pinctrl-0 = <&pinmux_flexcomm2_i2c>; + pinctrl-names = "default"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + audio_codec: wm8962@1a { + compatible = "wolfson,wm8962"; + reg = <0x1a>; + clock-source = "MCLK"; + clocks = <&clkctl0 MCUX_SAI0_CLK>; + clock-names = "mclk"; + }; +}; + &flexcomm8{ status = "okay"; }; @@ -159,6 +184,10 @@ zephyr_lcdif: &lcdif {}; status = "okay"; }; +&gpio7 { + status = "okay"; +}; + &green_led { status = "okay"; }; @@ -177,6 +206,12 @@ zephyr_lcdif: &lcdif {}; status = "okay"; }; +&sai0 { + status = "okay"; + pinctrl-0 = <&pinmux_sai0>; + pinctrl-names = "default"; +}; + &sc_timer { status = "okay"; pinctrl-0 = <&pinmux_sctimer>; @@ -211,8 +246,40 @@ zephyr_udc0: &usb0 { tx-cal-45-dm-ohms = <6>; }; +&usdhc0 { + status = "okay"; + pwr-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; + mmc { + compatible = "zephyr,mmc-disk"; + disk-name = "SD2"; + status = "okay"; + }; + pinctrl-0 = <&pinmux_usdhc>; + pinctrl-names = "default"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; + &wwdt0 { status = "okay"; }; +&acmp { + status = "okay"; + pinctrl-0 = <&pinmux_acmp>; + pinctrl-names = "default"; +}; + p3t1755dp_ard_i2c_interface: &flexcomm8_lpi2c8 {}; + +&rtc0 { + status = "okay"; +}; + +&dsp { + status = "okay"; +}; + +&mbox4 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml index 10b049b8277..523db8150a8 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml @@ -18,6 +18,7 @@ supported: - gpio - i2c - uart + - sdhc - spi - adc - usb_device diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig index 2e0bfcbd83e..5a4efbdf804 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig @@ -1,5 +1,5 @@ # -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # # SPDX-License-Identifier: Apache-2.0 # @@ -15,3 +15,6 @@ CONFIG_HW_STACK_PROTECTION=y # Enable TrustZone-M CONFIG_TRUSTED_EXECUTION_SECURE=y +# Nocache memory options +CONFIG_NOCACHE_MEMORY=y +CONFIG_IMX_USDHC_DMA_SUPPORT=n diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts index 78115a84e22..49fcd56cf57 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts @@ -19,6 +19,7 @@ led0 = &red_led; sw0 = &user_button_1; ambient-temp0 = &p3t1755; + rtc = &rtc1; }; chosen { @@ -97,3 +98,13 @@ status = "okay"; }; }; + +&acmp { + status = "okay"; + pinctrl-0 = <&pinmux_acmp>; + pinctrl-names = "default"; +}; + +&rtc1 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts index 392a4c27a1d..2c44fb7c761 100644 --- a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts @@ -1,18 +1,78 @@ /* - * Copyright 2024 NXP + * Copyright 2024, 2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; +#include +#include +#include + #include +#include "mimxrt700_evk-pinctrl.dtsi" + / { model = "NXP MIMXRT700-EVK HiFi4 DSP"; compatible = "nxp,mimxrt798s"; + aliases { + i2s-codec-tx = &sai0; + i2s-tx = &sai0; + }; + chosen { - zephyr,sram = &dtcm; + zephyr,sram = &adsp_data; + zephyr,console = &flexcomm0_lpuart0; + zephyr,shell-uart = &flexcomm0_lpuart0; + }; +}; + +&flexcomm0 { + status = "okay"; +}; + +&flexcomm0_lpuart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_lpuart>; + pinctrl-names = "default"; +}; + +&flexcomm2 { + status = "okay"; +}; + +&flexcomm2_lpi2c2 { + status = "okay"; + pinctrl-0 = <&pinmux_flexcomm2_i2c>; + pinctrl-names = "default"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + audio_codec: wm8962@1a { + compatible = "wolfson,wm8962"; + reg = <0x1a>; + clock-source = "MCLK"; + clocks = <&clkctl0 MCUX_SAI0_CLK>; + clock-names = "mclk"; }; }; + +&edma1 { + status = "okay"; +}; + +&sai0 { + status = "okay"; + pinctrl-0 = <&pinmux_sai0>; + pinctrl-names = "default"; + mclk-output; +}; + +&mbox4 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4_defconfig b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4_defconfig new file mode 100644 index 00000000000..980c9597c60 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4_defconfig @@ -0,0 +1,10 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/nxp/s32k148_evb/Kconfig.defconfig b/boards/nxp/s32k148_evb/Kconfig.defconfig new file mode 100644 index 00000000000..7a162d20ce4 --- /dev/null +++ b/boards/nxp/s32k148_evb/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_S32K148_EVB + +if SERIAL + +config UART_CONSOLE + default y + +endif # SERIAL + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_S32K148_EVB diff --git a/boards/nxp/s32k148_evb/Kconfig.s32k148_evb b/boards/nxp/s32k148_evb/Kconfig.s32k148_evb new file mode 100644 index 00000000000..50f931e7b76 --- /dev/null +++ b/boards/nxp/s32k148_evb/Kconfig.s32k148_evb @@ -0,0 +1,6 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_S32K148_EVB + select SOC_S32K148 + select SOC_PART_NUMBER_FS32K148HAT0MLUT diff --git a/boards/nxp/s32k148_evb/board.cmake b/boards/nxp/s32k148_evb/board.cmake new file mode 100644 index 00000000000..c26e0862b29 --- /dev/null +++ b/boards/nxp/s32k148_evb/board.cmake @@ -0,0 +1,12 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink + "--device=S32K148" + "--speed=4000" + "--iface=jtag" + "--reset" + "--tool-opt=-jtagconf -1,-1" +) + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/s32k148_evb/board.yml b/boards/nxp/s32k148_evb/board.yml new file mode 100644 index 00000000000..90d9decc827 --- /dev/null +++ b/boards/nxp/s32k148_evb/board.yml @@ -0,0 +1,6 @@ +board: + name: s32k148_evb + full_name: S32K148EVB-Q176 + vendor: nxp + socs: + - name: s32k148 diff --git a/boards/nxp/s32k148_evb/doc/img/s32k148_evb.webp b/boards/nxp/s32k148_evb/doc/img/s32k148_evb.webp new file mode 100644 index 00000000000..4ea4b280bf1 Binary files /dev/null and b/boards/nxp/s32k148_evb/doc/img/s32k148_evb.webp differ diff --git a/boards/nxp/s32k148_evb/doc/index.rst b/boards/nxp/s32k148_evb/doc/index.rst new file mode 100644 index 00000000000..6fc3c12e291 --- /dev/null +++ b/boards/nxp/s32k148_evb/doc/index.rst @@ -0,0 +1,167 @@ +.. zephyr:board:: s32k148_evb + +Overview +******** + +`NXP S32K148-Q176`_ is a low-cost evaluation and development board for general-purpose industrial +and automotive applications. +The S32K148-Q176 is based on the 32-bit Arm Cortex-M4F `NXP S32K148`_ microcontroller. +The onboard OpenSDA serial and debug adapter, running a mass storage device (MSD) bootloader +and a collection of OpenSDA Applications, offers options for serial communication, +flash programming, and run-control debugging. +It is a bridge between a USB host and the embedded target processor. + +Hardware +******** + +- NXP S32K148 + + - Arm Cortex-M4F @ up to 112 Mhz + - 1.5 MB Flash + - 256 KB SRAM + - up to 127 I/Os + - 3x FlexCAN with FD + - eDMA, 12-bit ADC, MPU, ECC and more. + +- Interfaces + + - CAN, LIN, UART/SCI + - Ethernet connector compatible with different ethernet daughter cards + - 2 touchpads, potentiometer, user RGB LED and 2 buttons. + +More information about the hardware and design resources can be found at +`NXP S32K148-Q176`_ website. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + Before using the Ethernet interface, please take note of the following: + + - For boards with the part number ``LSF24D`` at ``U16``, ``R553`` needs to be depopulated. + +Connections and IOs +=================== + +This board has 5 GPIO ports named from ``gpioa`` to ``gpioe``. + +Pin control can be further configured from your application overlay by adding +children nodes with the desired pinmux configuration to the singleton node +``pinctrl``. Supported properties are described in +:zephyr_file:`dts/bindings/pinctrl/nxp,port-pinctrl.yaml`. + +LEDs +---- + +The NXP S32K148-Q176 board has one user RGB LED that can be used either as a GPIO +LED or as a PWM LED. + +.. table:: RGB LED as GPIO LED + + +-----------------+------------------+----------------+-------+ + | Devicetree node | Devicetree alias | Label | Pin | + +=================+==================+================+=======+ + | led1_red | led0 | LED1_RGB_RED | PTE21 | + +-----------------+------------------+----------------+-------+ + | led1_green | led1 | LED1_RGB_GREEN | PTE22 | + +-----------------+------------------+----------------+-------+ + | led1_blue | led2 | LED1_RGB_BLUE | PTE23 | + +-----------------+------------------+----------------+-------+ + +.. table:: RGB LED as PWM LED + + +-----------------+--------------------------+--------------------+------------------+ + | Devicetree node | Devicetree alias | Label | Pin | + +=================+==========================+====================+==================+ + | led1_red_pwm | pwm-led0 / red-pwm-led | LED1_RGB_RED_PWM | PTE21 / FTM4_CH1 | + +-----------------+--------------------------+--------------------+------------------+ + | led1_green_pwm | pwm-led1 / green-pwm-led | LED1_RGB_GREEN_PWM | PTE22 / FTM4_CH2 | + +-----------------+--------------------------+--------------------+------------------+ + | led1_blue_pwm | pwm-led2 / blue-pwm-led | LED1_RGB_BLUE_PWM | PTE23 / FTM4_CH3 | + +-----------------+--------------------------+--------------------+------------------+ + +The user can control the LEDs in any way. An output of ``0`` illuminates the LED. + +Buttons +------- + +The NXP S32K148-Q176 board has two user buttons: + ++-----------------+-------+-------+ +| Devicetree node | Label | Pin | ++=================+=======+=======+ +| sw0 / button_3 | SW3 | PTC12 | ++-----------------+-------+-------+ +| sw1 / button_4 | SW4 | PTC13 | ++-----------------+-------+-------+ + +Serial Console +============== + +The serial console is provided via ``lpuart1`` on the OpenSDA adapter. + ++------+--------------+ +| Pin | Pin Function | ++======+==============+ +| PTC7 | LPUART1_TX | ++------+--------------+ +| PTC6 | LPUART1_RX | ++------+--------------+ + +System Clock +============ + +The Arm Cortex-M4F core is configured to run at 80 MHz (RUN mode). + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``s32k148_evb`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +This board configuration supports `SEGGER J-Link`_ West runner for flashing and +debugging applications. Follow the steps described in :ref:`jlink-debug-host-tools`, +to setup the flash and debug host tools for this runner. + +Flashing +======== + +Run the ``west flash`` command to flash the application using SEGGER J-Link. + +Debugging +========= + +Run the ``west debug`` command to start a GDB session using SEGGER J-Link. + +Configuring a Console +===================== + +We will use OpenSDA as a USB-to-serial adapter for the serial console. + +Use the following settings with your serial terminal of choice (minicom, putty, etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +.. include:: ../../common/board-footer.rst + :start-after: nxp-board-footer + +References +********** + +.. target-notes:: + +.. _NXP S32K148-Q176: + https://www.nxp.com/design/design-center/development-boards-and-designs/automotive-development-platforms/s32k-mcu-platforms/s32k148-q176-evaluation-board-for-automotive-general-purpose:S32K148EVB + +.. _NXP S32K148: + https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k1-microcontrollers-for-automotive-general-purpose:S32K1 + +.. _SEGGER J-Link: + https://wiki.segger.com/S32Kxxx diff --git a/boards/nxp/s32k148_evb/s32k148_evb-pinctrl.dtsi b/boards/nxp/s32k148_evb/s32k148_evb-pinctrl.dtsi new file mode 100644 index 00000000000..181018407d8 --- /dev/null +++ b/boards/nxp/s32k148_evb/s32k148_evb-pinctrl.dtsi @@ -0,0 +1,87 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + lpuart0_default: lpuart0_default { + group0 { + pinmux = , ; + drive-strength = "low"; + }; + }; + + lpuart1_default: lpuart1_default { + group0 { + pinmux = , ; + drive-strength = "low"; + }; + }; + + lpi2c0_default: lpi2c0_default { + group1 { + pinmux = , ; + drive-strength = "low"; + }; + }; + + lpspi0_default: lpspi0_default { + group0 { + pinmux = , + , + , + ; + drive-strength = "low"; + }; + }; + + ftm4_default: ftm4_default { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + }; + }; + + flexcan0_default: flexcan0_default { + group0 { + pinmux = , ; + drive-strength = "low"; + }; + }; + + pinmux_enet: pinmux_enet { + group1 { + pinmux = , + , + , + , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + pinmux_enet_mdio: pinmux_enet_mdio { + group0 { + pinmux = ; + drive-strength = "low"; + drive-open-drain; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; +}; diff --git a/boards/nxp/s32k148_evb/s32k148_evb.dts b/boards/nxp/s32k148_evb/s32k148_evb.dts new file mode 100644 index 00000000000..881287544bc --- /dev/null +++ b/boards/nxp/s32k148_evb/s32k148_evb.dts @@ -0,0 +1,193 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "s32k148_evb-pinctrl.dtsi" + +/ { + model = "NXP S32K148EVB"; + compatible = "nxp,s32k148_evb"; + + chosen { + zephyr,sram = &sram_l; + zephyr,flash = &flash0; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,uart-pipe = &lpuart1; + zephyr,canbus = &flexcan0; + }; + + aliases { + led0 = &led1_red; + led1 = &led1_green; + led2 = &led1_blue; + pwm-led0 = &led1_red_pwm; + pwm-led1 = &led1_green_pwm; + pwm-led2 = &led1_blue_pwm; + red-pwm-led = &led1_red_pwm; + green-pwm-led = &led1_green_pwm; + blue-pwm-led = &led1_blue_pwm; + sw0 = &button_3; + sw1 = &button_4; + i2c-0 = &lpi2c0; + }; + + leds { + compatible = "gpio-leds"; + + led1_red: led_0 { + gpios = <&gpioe 21 GPIO_ACTIVE_LOW>; + label = "LED1_RGB_RED"; + }; + + led1_green: led_1 { + gpios = <&gpioe 22 GPIO_ACTIVE_LOW>; + label = "LED1_RGB_GREEN"; + }; + + led1_blue: led_2 { + gpios = <&gpioe 23 GPIO_ACTIVE_LOW>; + label = "LED1_RGB_BLUE"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + led1_red_pwm: led_pwm_0 { + pwms = <&ftm4 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "LED1_RGB_RED_PWM"; + }; + + led1_green_pwm: led_pwm_1 { + pwms = <&ftm4 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "LED1_RGB_GREEN_PWM"; + }; + + led1_blue_pwm: led_pwm_2 { + pwms = <&ftm4 3 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "LED1_RGB_BLUE_PWM"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button_3: button_0 { + label = "SW3"; + gpios = <&gpioc 12 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + button_4: button_1 { + label = "SW4"; + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <80000000>; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&lpuart0 { + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; + current-speed = <115200>; +}; + +&lpuart1 { + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&lpi2c0 { + pinctrl-0 = <&lpi2c0_default>; + pinctrl-names = "default"; + scl-gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&lpspi0 { + pinctrl-0 = <&lpspi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ftm4 { + compatible = "nxp,ftm-pwm"; + pinctrl-0 = <&ftm4_default>; + pinctrl-names = "default"; + clock-source = "system"; + prescaler = <4>; + #pwm-cells = <3>; + status = "okay"; +}; + +/* + * The S32K148EVB board contains a UJA1132 SBC which needs to be configured via SPI. + * The factory preset forces it to normal mode though, so the CAN phy is enabled + * even without configuration. + * Therefore, we don't reference a can phy driver node here for now. + */ +&flexcan0 { + pinctrl-0 = <&flexcan0_default>; + pinctrl-names = "default"; + bitrate = <125000>; + status = "okay"; +}; + +&adc0 { + sample-time = <65>; + vref-mv = <5000>; + status = "okay"; +}; + +&adc1 { + sample-time = <65>; + vref-mv = <5000>; + status = "okay"; +}; + +&enet_mac { + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + zephyr,random-mac-address; + phy-connection-type = "rmii"; +}; + +&enet_mdio { + pinctrl-0 = <&pinmux_enet_mdio>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/s32k148_evb/s32k148_evb.yaml b/boards/nxp/s32k148_evb/s32k148_evb.yaml new file mode 100644 index 00000000000..caa76f3afef --- /dev/null +++ b/boards/nxp/s32k148_evb/s32k148_evb.yaml @@ -0,0 +1,22 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32k148_evb +name: NXP S32K148EVB-Q176 +vendor: nxp +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr +supported: + - mpu + - gpio + - uart + - pinctrl + - pwm + - can + - watchdog + - counter + - adc diff --git a/boards/nxp/s32k148_evb/s32k148_evb_defconfig b/boards/nxp/s32k148_evb/s32k148_evb_defconfig new file mode 100644 index 00000000000..08e047dd7bb --- /dev/null +++ b/boards/nxp/s32k148_evb/s32k148_evb_defconfig @@ -0,0 +1,13 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +# Run from internal program flash +CONFIG_XIP=y + +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml index 60b258ad5a1..fada2cf5ea9 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml @@ -1,4 +1,4 @@ -# Copyright 2022-2024 NXP +# Copyright 2022-2025 NXP # SPDX-License-Identifier: Apache-2.0 identifier: s32z2xxdc2/s32z270/rtu0 @@ -20,4 +20,6 @@ supported: - i2c - dma - pwm + - sent + - psi5 vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml index c35cc47699b..e5593f47784 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml @@ -1,4 +1,4 @@ -# Copyright 2023-2024 NXP +# Copyright 2023-2025 NXP # SPDX-License-Identifier: Apache-2.0 identifier: s32z2xxdc2@D/s32z270/rtu0 @@ -20,4 +20,6 @@ supported: - i2c - dma - pwm + - sent + - psi5 vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml index 3d4f2062cc9..b2030af22d1 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml @@ -1,4 +1,4 @@ -# Copyright 2022-2024 NXP +# Copyright 2022-2025 NXP # SPDX-License-Identifier: Apache-2.0 identifier: s32z2xxdc2/s32z270/rtu1 @@ -20,4 +20,6 @@ supported: - i2c - dma - pwm + - sent + - psi5 vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml index 334d75319ca..993bc5d8ecb 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml @@ -1,4 +1,4 @@ -# Copyright 2022-2024 NXP +# Copyright 2022-2025 NXP # SPDX-License-Identifier: Apache-2.0 identifier: s32z2xxdc2@D/s32z270/rtu1 @@ -20,4 +20,6 @@ supported: - i2c - dma - pwm + - sent + - psi5 vendor: nxp diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512.yaml b/boards/nxp/usb_kw24d512/usb_kw24d512.yaml index 4320277c684..7c16acfe9df 100644 --- a/boards/nxp/usb_kw24d512/usb_kw24d512.yaml +++ b/boards/nxp/usb_kw24d512/usb_kw24d512.yaml @@ -10,5 +10,6 @@ toolchain: supported: - flash - usb_device + - usbd - watchdog vendor: nxp diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi index e6d00911b13..1f77666f514 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi +++ b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi @@ -179,7 +179,7 @@ }; }; - pinmux_lpadc1: pinmux_lpadc1 { + pinmux_lpadc2: pinmux_lpadc2 { group0 { pinmux = <&iomuxc_gpio_ad_10_adc1_ch2a>; drive-strength = "normal"; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi index b8b8a0c06ae..7ee956ae52e 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi @@ -109,9 +109,9 @@ &enet1g_mdio { pinctrl-0 = <&pinmux_enet1g_mdio>; pinctrl-names = "default"; - enet1g_phy: phy@1 { + enet1g_phy: phy@f { compatible = "nxp,tja1103"; - reg = <1>; + reg = <0xf>; master-slave = "master"; }; }; @@ -176,8 +176,8 @@ pinctrl-names = "default"; }; -&lpadc1 { - pinctrl-0 = <&pinmux_lpadc1>; +&lpadc2 { + pinctrl-0 = <&pinmux_lpadc2>; pinctrl-names = "default"; }; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts index 205b2149c8b..573ed8a3926 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include #include "vmu_rt1170.dtsi" #include @@ -243,32 +243,40 @@ }; }; -#include +#include &lpspi1 { status = "okay"; cs-gpios =<&gpio2 11 GPIO_ACTIVE_LOW>; - icm42688_0: icm42688p0@0 { - compatible = "invensense,icm42688"; + icm42686_0: icm42686p0@0 { + compatible = "invensense,icm42686", "invensense,icm4268x"; reg = <0>; int-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; spi-max-frequency = <24000000>; - accel-pwr-mode = ; - accel-odr = ; - accel-fs = ; - gyro-pwr-mode = ; - gyro-odr = ; - gyro-fs = ; + accel-pwr-mode = ; + accel-odr = ; + accel-fs = ; + gyro-pwr-mode = ; + gyro-odr = ; + gyro-fs = ; + axis-align-x = ; + axis-align-y = ; + axis-align-z = ; + axis-align-x-sign = ; + axis-align-z-sign = ; + fifo-hires; }; }; +#include + &lpspi2 { status = "okay"; cs-gpios =<&gpio3 24 GPIO_ACTIVE_LOW>; - icm42688_1: icm42688p1@0 { - compatible = "invensense,icm42688"; + icm42688_0: icm42688p0@0 { + compatible = "invensense,icm42688", "invensense,icm4268x"; reg = <0>; int-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; spi-max-frequency = <24000000>; @@ -278,6 +286,11 @@ gyro-pwr-mode = ; gyro-odr = ; gyro-fs = ; + axis-align-x = ; + axis-align-y = ; + axis-align-z = ; + axis-align-x-sign = ; + fifo-hires; }; }; @@ -468,7 +481,7 @@ status = "okay"; }; -&lpadc1 { +&lpadc2 { status = "okay"; }; @@ -498,10 +511,11 @@ &enet1g_mdio { status = "okay"; - enet1g_phy: phy@1 { - status = "okay"; - int-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; - }; +}; + +&enet1g_phy { + status = "okay"; + int-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; }; zephyr_udc0: &usb1 { diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig index 5c88c2339dc..e1fbd742d0c 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig @@ -15,6 +15,6 @@ CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 # Enable Regulators CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_INIT_PRIORITY=75 +CONFIG_REGULATOR_FIXED_INIT_PRIORITY=65 CONFIG_TICKLESS_KERNEL=n diff --git a/boards/others/canbardo/board.cmake b/boards/others/canbardo/board.cmake index 470cf0a5322..78a4abb3312 100644 --- a/boards/others/canbardo/board.cmake +++ b/boards/others/canbardo/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=ATSAME70N20B") +board_runner_args(openocd --cmd-post-verify "atsamv gpnvm set 1") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/others/canbardo/canbardo_defconfig b/boards/others/canbardo/canbardo_defconfig index 72c0c1bffff..4f05a2b8cb7 100644 --- a/boards/others/canbardo/canbardo_defconfig +++ b/boards/others/canbardo/canbardo_defconfig @@ -1,6 +1,8 @@ # Copyright (c) 2024-2025 Henrik Brix Andersen # SPDX-License-Identifier: Apache-2.0 +CONFIG_BUILD_OUTPUT_HEX=y + CONFIG_ARM_MPU=y CONFIG_CACHE_MANAGEMENT=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/others/canbardo/support/openocd.cfg b/boards/others/canbardo/support/openocd.cfg new file mode 100644 index 00000000000..590201b532e --- /dev/null +++ b/boards/others/canbardo/support/openocd.cfg @@ -0,0 +1,24 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME atsame70n20b + +source [find target/atsamv.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/others/neorv32/Kconfig b/boards/others/neorv32/Kconfig index 038c6c6cc86..816f2ae1543 100644 --- a/boards/others/neorv32/Kconfig +++ b/boards/others/neorv32/Kconfig @@ -5,7 +5,6 @@ if BOARD_NEORV32_NEORV32_MINIMALBOOT config BOARD_NEORV32 select RISCV_ISA_RV32I - select ATOMIC_OPERATIONS_C endif # BOARD_NEORV32_NEORV32_MINIMALBOOT @@ -14,6 +13,5 @@ if BOARD_NEORV32_NEORV32_UP5KDEMO config BOARD_NEORV32 select RISCV_ISA_RV32I select RISCV_ISA_EXT_M - select ATOMIC_OPERATIONS_C endif # BOARD_NEORV32_NEORV32_UP5KDEMO diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst index b10d7a2f007..62e78d1ef59 100644 --- a/boards/others/neorv32/doc/index.rst +++ b/boards/others/neorv32/doc/index.rst @@ -13,7 +13,7 @@ For more information about the NEORV32, see the following websites: - `The NEORV32 RISC-V Processor Datasheet`_ - `The NEORV32 RISC-V Processor User Guide`_ -The currently supported version is NEORV32 v1.11.3. +The currently supported version is NEORV32 v1.11.6. Supported Board Targets ======================= diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_common.dts b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_common.dts index c8a8b77e62c..ba1d53cb6f3 100644 --- a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_common.dts +++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_common.dts @@ -41,7 +41,6 @@ led0 = &led0; pwm-led0 = &red_pwm_led; red-pwm-led = &red_pwm_led; - bootloader-led0 = &led0; mcuboot-led0 = &led0; spi = &spi2; watchdog0 = &wdt0; diff --git a/boards/panasonic/pan1770_evb/pan1770_evb.dts b/boards/panasonic/pan1770_evb/pan1770_evb.dts index 886539344f4..6a4d6502583 100644 --- a/boards/panasonic/pan1770_evb/pan1770_evb.dts +++ b/boards/panasonic/pan1770_evb/pan1770_evb.dts @@ -128,7 +128,7 @@ sw1 = &evb_sw2; sw2 = &evb_sw3; sw3 = &evb_sw4; - bootloader-led0 = &evb_led1; + mcuboot-led0 = &evb_led1; watchdog0 = &wdt0; }; }; diff --git a/boards/panasonic/pan1780_evb/pan1780_evb.dts b/boards/panasonic/pan1780_evb/pan1780_evb.dts index 0fdde8ec355..9bf6d4344d9 100644 --- a/boards/panasonic/pan1780_evb/pan1780_evb.dts +++ b/boards/panasonic/pan1780_evb/pan1780_evb.dts @@ -128,7 +128,7 @@ sw1 = &evb_sw2; sw2 = &evb_sw3; sw3 = &evb_sw4; - bootloader-led0 = &evb_led1; + mcuboot-led0 = &evb_led1; watchdog0 = &wdt0; }; }; diff --git a/boards/panasonic/pan1782_evb/pan1782_evb.dts b/boards/panasonic/pan1782_evb/pan1782_evb.dts index 181aa6cb372..33f7f6bdebe 100644 --- a/boards/panasonic/pan1782_evb/pan1782_evb.dts +++ b/boards/panasonic/pan1782_evb/pan1782_evb.dts @@ -89,7 +89,7 @@ pwm-led0 = &pwm_evb_led1; sw0 = &evb_sw1; sw1 = &evb_sw2; - bootloader-led0 = &evb_led1; + mcuboot-led0 = &evb_led1; watchdog0 = &wdt0; }; }; diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi index 709934b9ad7..1ad125207eb 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi @@ -152,7 +152,6 @@ sw1 = &evb_sw2; sw2 = &evb_sw3; sw3 = &evb_sw4; - bootloader-led0 = &evb_led1; mcuboot-button0 = &evb_sw1; mcuboot-led0 = &evb_led1; watchdog0 = &wdt0; diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi index fba45dba2aa..62df4a9d677 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi @@ -125,7 +125,6 @@ sw1 = &evb_sw2; sw2 = &evb_sw3; sw3 = &evb_sw4; - bootloader-led0 = &evb_led1; mcuboot-button0 = &evb_sw1; mcuboot-led0 = &evb_led1; watchdog0 = &wdt0; diff --git a/boards/panasonic/panb511evb/Kconfig.defconfig b/boards/panasonic/panb511evb/Kconfig.defconfig index 1c4e4be6637..595e01692cc 100644 --- a/boards/panasonic/panb511evb/Kconfig.defconfig +++ b/boards/panasonic/panb511evb/Kconfig.defconfig @@ -14,7 +14,7 @@ endif # BOARD_PANB511EVB_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS -config BT_CTLR +config HAS_BT_CTLR default BT config FLASH_LOAD_OFFSET diff --git a/boards/peregrine/sam4l_wm400_cape/Kconfig.defconfig b/boards/peregrine/sam4l_wm400_cape/Kconfig.defconfig index 1f95ae349d0..66c7e7eeabe 100644 --- a/boards/peregrine/sam4l_wm400_cape/Kconfig.defconfig +++ b/boards/peregrine/sam4l_wm400_cape/Kconfig.defconfig @@ -17,6 +17,4 @@ endif # NETWORKING config USE_DT_CODE_PARTITION default y -source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" - endif # BOARD_SAM4L_WM400_CAPE diff --git a/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.dts b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.dts index 5f181100344..391d4b99f99 100644 --- a/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.dts +++ b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.dts @@ -23,6 +23,8 @@ }; chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition= &code_partition; @@ -185,5 +187,3 @@ zephyr_udc0: &usbc { pinctrl-0 = <&usbc_default>; pinctrl-names = "default"; }; - -#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4.dts b/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4.dts index cc243d6243c..55a26e55b0f 100644 --- a/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4.dts +++ b/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include +#include #include / { @@ -15,8 +17,8 @@ chosen { zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; + zephyr,console = &mcu_uart0; + zephyr,shell-uart = &mcu_uart0; zephyr,ipc_shm = &ddr0; zephyr,sram1 = &ddr1; }; @@ -52,13 +54,15 @@ leds: leds { compatible = "gpio-leds"; heartbeat_led: led_0 { - gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + gpios = <&mcu_gpio0 6 GPIO_ACTIVE_HIGH>; label = "Heartbeat LED"; }; }; }; -&pinctrl { +&mcu_pinctrl { + status = "okay"; + mcu_uart0_rx_default: mcu_uart0_rx_default { pinmux = ; }; @@ -70,14 +74,14 @@ }; }; -&uart0 { +&mcu_uart0 { current-speed = <115200>; pinctrl-0 = <&mcu_uart0_rx_default &mcu_uart0_tx_default>; pinctrl-names = "default"; status = "okay"; }; -&gpio0 { +&mcu_gpio0 { pinctrl-0 = <&mcu_gpio0_led_default>; pinctrl-names = "default"; status = "okay"; diff --git a/boards/phytec/phyboard_lyra/Kconfig.phyboard_lyra b/boards/phytec/phyboard_lyra/Kconfig.phyboard_lyra index 93076900cf3..498690d9911 100644 --- a/boards/phytec/phyboard_lyra/Kconfig.phyboard_lyra +++ b/boards/phytec/phyboard_lyra/Kconfig.phyboard_lyra @@ -8,5 +8,3 @@ config BOARD_PHYBOARD_LYRA select SOC_AM6234_A53 if BOARD_PHYBOARD_LYRA_AM6234_A53 select SOC_AM6234_M4 if BOARD_PHYBOARD_LYRA_AM6234_M4 - help - PHYTEC phyBOARD-Lyra AM62x M4/A53 diff --git a/boards/phytec/phyboard_pollux/doc/index.rst b/boards/phytec/phyboard_pollux/doc/index.rst index 73fa347b783..dee06c512d1 100644 --- a/boards/phytec/phyboard_pollux/doc/index.rst +++ b/boards/phytec/phyboard_pollux/doc/index.rst @@ -6,11 +6,11 @@ phyBOARD-Pollux i.MX8M Plus Overview ******** -The phyBOARD-Pollux is based upon the phyCORE-i.MX8M Plus SOM which is based on +The phyBOARD-Pollux is based upon the phyCORE-i.MX8M Plus SoM which is based on the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one Coretex-M7 core for real time applications like Zephyr. The phyBOARD-Pollux -can be used for various applications like SmartHomes, Industry 4.0, IoT etc. -It features a lots of interfaces and computing capacity. It can be used as +can be used for various applications like SmartHome, Industry 4.0, IoT etc. +It features a lot of interfaces and computing capacity. It can be used as a reference, to develop or in the final product too. @@ -52,7 +52,7 @@ More information about the board can be found at the `PHYTEC website`_. Supported Features ================== -The Zephyr phyboard_polis board configuration supports the following hardware +The ``phyboard_pollux/mimx8ml8/m7`` board configuration supports the following hardware features: +-----------+------------+------------------------------------+ @@ -72,6 +72,10 @@ features: | GPIO | on-chip | GPIO output | | | | GPIO input | +-----------+------------+------------------------------------+ +| I2C | on-chip | ii2c | ++-----------+------------+------------------------------------+ +| PCA95533 | I2C | RGB LED via I2C2 | ++-----------+------------+------------------------------------+ The default configuration can be found in the defconfig file: :zephyr_file:`boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7_defconfig`. @@ -83,7 +87,7 @@ Zephyr on the M7-Core. Connections and IOs =================== -The following Compontens are tested and working correctly. +The following components are tested and working correctly. UART ---- @@ -110,6 +114,38 @@ created by NXP and can be found at :zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. The Pinout of the phyBOARD-Polis can be found at the `PHYTEC website`_. +I2C +--- + +There are multiple on-device I2C devices already connected to +I2C busses. +Some of these devices should not be used by the M7-Core if +running the PHYTEC BSP on the A53-Core. + +Here is an overview of the on-device I2C devices: + ++-----------------+-----------------+--------------------+--------------------+ +| I2C Device | Address | Usage | Can be used by M7? | ++=================+=================+====================+====================+ +| PMIC | 0x25@i2c1 | Power Management | Should not be used | ++-----------------+-----------------+--------------------+--------------------+ +| EEPROM | 0x51@i2c1 | EEPROM | Should not be used | +| (Atmel 24C32) | | (U-Boot config) | | ++-----------------+-----------------+--------------------+--------------------+ +| RTC (RV3028) | 0x51@i2c1 | Real Time Clock | Should not be used | ++-----------------+-----------------+--------------------+--------------------+ +| EEPROM | 0x51@i2c2 | EEPROM | yes | +| (Atmel 24C02) | | (On carrier-board) | | ++-----------------+-----------------+--------------------+--------------------+ +| PCA9553 | 0x62@i2c2 | RGB LED | yes | ++-----------------+-----------------+--------------------+--------------------+ + +.. note:: + i2c1 is used by the A53-Core to communicate with the PMIC. + Because the PMIC is a crucial part of the system, i2c1 should be + used by the A53-Core only to avoid conflicts. + + Programming and Debugging ************************* diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux-pinctrl.dtsi b/boards/phytec/phyboard_pollux/phyboard_pollux-pinctrl.dtsi index 8a31136da6e..4c99bb8f7b3 100644 --- a/boards/phytec/phyboard_pollux/phyboard_pollux-pinctrl.dtsi +++ b/boards/phytec/phyboard_pollux/phyboard_pollux-pinctrl.dtsi @@ -36,4 +36,52 @@ drive-strength = "x1"; }; }; + + i2c1_default: i2c1_default { + group0 { + pinmux = <&iomuxc_i2c1_scl_i2c_scl_i2c1_scl>, + <&iomuxc_i2c1_sda_i2c_sda_i2c1_sda>; + bias-pull-up; + input-schmitt-enable; + slew-rate = "slow"; + drive-strength = "x4"; + input-enable; + }; + }; + + i2c2_default: i2c2_default { + group0 { + pinmux = <&iomuxc_i2c2_scl_i2c_scl_i2c2_scl>, + <&iomuxc_i2c2_sda_i2c_sda_i2c2_sda>; + bias-pull-up; + input-schmitt-enable; + slew-rate = "slow"; + drive-strength = "x4"; + input-enable; + }; + }; + + i2c3_default: i2c3_default { + group0 { + pinmux = <&iomuxc_i2c3_scl_i2c_scl_i2c3_scl>, + <&iomuxc_i2c3_sda_i2c_sda_i2c3_sda>; + bias-pull-up; + input-schmitt-enable; + slew-rate = "slow"; + drive-strength = "x4"; + input-enable; + }; + }; + + i2c4_default: i2c4_default { + group0 { + pinmux = <&iomuxc_i2c4_scl_i2c_scl_i2c4_scl>, + <&iomuxc_i2c4_sda_i2c_sda_i2c4_sda>; + bias-pull-up; + input-schmitt-enable; + slew-rate = "slow"; + drive-strength = "x4"; + input-enable; + }; + }; }; diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts index 9376bfb1df7..ce0b98e49a2 100644 --- a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts +++ b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "phyboard_pollux-pinctrl.dtsi" / { @@ -63,6 +64,47 @@ pinctrl-names = "default"; }; +/* + * Has PMIC and EEPROM connected to it. + * Used by u-boot and Linux. + */ +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +/* + * Has PCA9533 I2C expander and a EEPROM connected. + * There is no driver for the PCA9533 in zephyr yet. + * Accessible via X6(Expansion header) and X10(mini PCIe). + */ +&i2c2 { + clock-frequency = ; + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +/* + * Nothing connected. + * Accessible via connector X11 (phyCAM-M). + */ +&i2c3 { + clock-frequency = ; + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; +}; + +/* + * Nothing connected. + * Accessible via connector X15(A/V), X24(Display) and X21(MIPI-DSI). + */ +&i2c4 { + clock-frequency = ; + pinctrl-0 = <&i2c4_default>; + pinctrl-names = "default"; +}; + &mailbox0 { status = "okay"; }; diff --git a/boards/phytec/reel_board/doc/index.rst b/boards/phytec/reel_board/doc/index.rst index 7e588bebf86..e710106dcc5 100644 --- a/boards/phytec/reel_board/doc/index.rst +++ b/boards/phytec/reel_board/doc/index.rst @@ -563,4 +563,4 @@ References https://www.phytec.de/reelboard/ .. _DAPLink reel board Firmware: - https://github.com/PHYTEC-Messtechnik-GmbH/DAPLink/tree/reel-board + https://github.com/phytec/DAPLink/tree/reel-board diff --git a/boards/pimoroni/pico_plus2/pico_plus2.dtsi b/boards/pimoroni/pico_plus2/pico_plus2.dtsi index f77ae33e042..b44cf839279 100644 --- a/boards/pimoroni/pico_plus2/pico_plus2.dtsi +++ b/boards/pimoroni/pico_plus2/pico_plus2.dtsi @@ -18,7 +18,6 @@ zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,code-partition = &code_partition; }; aliases { @@ -92,33 +91,6 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(16)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserved memory for an image definition block. The block is much - * smaller than 256 bytes, but in practice the linker places the vector - * table at a much larger alignment offset. - */ - image_def: partition@0 { - label = "image_def"; - reg = <0x00000000 0x100>; - read-only; - }; - - /* - * Usable flash. Starts at 0x100, after the image definition block. - * The partition size is 16MB minus the 0x100 bytes taken by the - * image definition. - */ - code_partition: partition@100 { - label = "code-partition"; - reg = <0x100 (DT_SIZE_M(16) - 0x100)>; - read-only; - }; - }; }; &uart0 { @@ -175,4 +147,4 @@ pico_spi: &spi0 {}; pico_i2c0: &i2c0 {}; pico_i2c1: &i2c1 {}; pico_serial: &uart0 {}; -stemma_qt_i2c: &i2c0 {}; +zephyr_i2c: &i2c0 {}; diff --git a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33_defconfig b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33_defconfig index 8bd68e35113..4da77bdb95c 100644 --- a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33_defconfig +++ b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33_defconfig @@ -8,7 +8,6 @@ CONFIG_CONSOLE=y CONFIG_GPIO=y CONFIG_RESET=y CONFIG_SERIAL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000 CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/qemu/cortex_a53/board.cmake b/boards/qemu/cortex_a53/board.cmake index 7cc424e4544..90c1739dfea 100644 --- a/boards/qemu/cortex_a53/board.cmake +++ b/boards/qemu/cortex_a53/board.cmake @@ -12,8 +12,14 @@ else() set(QEMU_MACH virt,secure=on,gic-version=3) endif() +if(CONFIG_ENTROPY_VIRTIO) + set(QEMU_VIRTIO_ENTROPY_FLAGS -device virtio-rng-device,bus=virtio-mmio-bus.0) +endif() + set(QEMU_FLAGS_${ARCH} + -global virtio-mmio.force-legacy=false -cpu ${QEMU_CPU_TYPE_${ARCH}} + ${QEMU_VIRTIO_ENTROPY_FLAGS} -nographic -machine ${QEMU_MACH} ) diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53.dts b/boards/qemu/cortex_a53/qemu_cortex_a53.dts index ef1324d0199..41cba16b437 100644 --- a/boards/qemu/cortex_a53/qemu_cortex_a53.dts +++ b/boards/qemu/cortex_a53/qemu_cortex_a53.dts @@ -31,6 +31,229 @@ reg = <0x0 0x40000000 0x0 DT_SIZE_M(128)>; }; + virtio_mmio0: virtio_mmio@a000000 { + compatible = "virtio,mmio"; + reg = <0x0 0xa000000 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio1: virtio_mmio@a000200 { + compatible = "virtio,mmio"; + reg = <0x0 0xa000200 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio2: virtio_mmio@a000400 { + compatible = "virtio,mmio"; + reg = <0x0 0xa000400 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio3: virtio_mmio@a000600 { + compatible = "virtio,mmio"; + reg = <0x0 0xa000600 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio4: virtio_mmio@a000800 { + compatible = "virtio,mmio"; + reg = <0x0 0xa000800 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio5: virtio_mmio@a000a00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa000a00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio6: virtio_mmio@a000c00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa000c00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio7: virtio_mmio@a000e00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa000e00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio8: virtio_mmio@a001000 { + compatible = "virtio,mmio"; + interrupts = ; + reg = <0x0 0xa001000 0x0 0x200>; + status = "disabled"; + }; + + virtio_mmio9: virtio_mmio@a001200 { + compatible = "virtio,mmio"; + reg = <0x0 0xa001200 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio10: virtio_mmio@a001400 { + compatible = "virtio,mmio"; + reg = <0x0 0xa001400 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio11: virtio_mmio@a001600 { + compatible = "virtio,mmio"; + reg = <0x0 0xa001600 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio12: virtio_mmio@a001800 { + compatible = "virtio,mmio"; + reg = <0x0 0xa001800 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio13: virtio_mmio@a001a00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa001a00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio14: virtio_mmio@a001c00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa001c00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio15: virtio_mmio@a001e00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa001e00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio16: virtio_mmio@a002000 { + compatible = "virtio,mmio"; + reg = <0x0 0xa002000 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio17: virtio_mmio@a002200 { + compatible = "virtio,mmio"; + reg = <0x0 0xa002200 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio18: virtio_mmio@a002400 { + compatible = "virtio,mmio"; + reg = <0x0 0xa002400 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio19: virtio_mmio@a002600 { + compatible = "virtio,mmio"; + reg = <0x0 0xa002600 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio20: virtio_mmio@a002800 { + compatible = "virtio,mmio"; + reg = <0x0 0xa002800 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio21: virtio_mmio@a002a00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa002a00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio22: virtio_mmio@a002c00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa002c00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio23: virtio_mmio@a002e00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa002e00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio24: virtio_mmio@a003000 { + compatible = "virtio,mmio"; + reg = <0x0 0xa003000 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio25: virtio_mmio@a003200 { + compatible = "virtio,mmio"; + reg = <0x0 0xa003200 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio26: virtio_mmio@a003400 { + compatible = "virtio,mmio"; + reg = <0x0 0xa003400 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio27: virtio_mmio@a003600 { + compatible = "virtio,mmio"; + reg = <0x0 0xa003600 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio28: virtio_mmio@a003800 { + compatible = "virtio,mmio"; + reg = <0x0 0xa003800 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio29: virtio_mmio@a003a00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa003a00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio30: virtio_mmio@a003c00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa003c00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; + + virtio_mmio31: virtio_mmio@a003e00 { + compatible = "virtio,mmio"; + reg = <0x0 0xa003e00 0x0 0x200>; + interrupts = ; + status = "disabled"; + }; }; }; diff --git a/boards/qemu/cortex_m3/Kconfig.defconfig b/boards/qemu/cortex_m3/Kconfig.defconfig index 13b7fc07a9b..54a26f37a56 100644 --- a/boards/qemu/cortex_m3/Kconfig.defconfig +++ b/boards/qemu/cortex_m3/Kconfig.defconfig @@ -13,7 +13,7 @@ choice NULL_POINTER_EXCEPTION_DETECTION endchoice # BT relies on PSA Crypto API to perform crypto operations and, on this platform, -# these APIs are provided thougth Mbed TLS. Unfortunately this platform is not +# these APIs are provided through Mbed TLS. Unfortunately, this platform is not # provided with a true random number generator which is required to properly # initialize the PSA Crypto core, so we need to enable the fake TEST_RANDOM_GENERATOR. config TEST_RANDOM_GENERATOR diff --git a/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 b/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 index 0e8d2cb2301..1dd87bba37c 100644 --- a/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 +++ b/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 @@ -3,5 +3,3 @@ config BOARD_QEMU_CORTEX_M3 select SOC_TI_LM3S6965 - help - Cortex-M3 Emulation (QEMU) diff --git a/boards/qemu/rx/qemu_rx.yaml b/boards/qemu/rx/qemu_rx.yaml index 86c6513f138..db6f4879156 100644 --- a/boards/qemu/rx/qemu_rx.yaml +++ b/boards/qemu/rx/qemu_rx.yaml @@ -9,7 +9,14 @@ simulation: arch: rx toolchain: - cross-compile + - zephyr supported: - serial +testing: + default: true + ignore_tags: + - net + - bluetooth + - can ram: 96 flash: 512 diff --git a/boards/qemu/x86/board.cmake b/boards/qemu/x86/board.cmake index 660a07fae31..57edffbe96c 100644 --- a/boards/qemu/x86/board.cmake +++ b/boards/qemu/x86/board.cmake @@ -61,11 +61,16 @@ if(NOT CONFIG_X86_64 AND CONFIG_CACHE_MANAGEMENT) string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "clflush") endif() +if(CONFIG_ENTROPY_VIRTIO) + set(QEMU_VIRTIO_ENTROPY_FLAGS -device virtio-rng-pci) +endif() + set(QEMU_FLAGS_${ARCH} -m ${QEMU_MEMORY_SIZE_MB} -cpu ${QEMU_CPU_TYPE_${ARCH}}${QEMU_CPU_FLAGS} -machine q35 -device isa-debug-exit,iobase=0xf4,iosize=0x04 + ${QEMU_VIRTIO_ENTROPY_FLAGS} ${REBOOT_FLAG} -nographic ) diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig b/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig index 6b67200e544..8c10c786e83 100644 --- a/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig @@ -8,7 +8,7 @@ CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_X86_MMU=y diff --git a/boards/qemu/x86/qemu_x86_64_defconfig b/boards/qemu/x86/qemu_x86_64_defconfig index 9ca58bfcb70..1ffccaa4903 100644 --- a/boards/qemu/x86/qemu_x86_64_defconfig +++ b/boards/qemu/x86/qemu_x86_64_defconfig @@ -8,7 +8,7 @@ CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SMP=y CONFIG_MP_MAX_NUM_CPUS=2 CONFIG_X86_MMU=y diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig b/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig index 33cbf5de6b4..a2c8d1557f4 100644 --- a/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig @@ -9,7 +9,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y diff --git a/boards/qemu/x86/qemu_x86_atom_nommu_defconfig b/boards/qemu/x86/qemu_x86_atom_nommu_defconfig index 3215747a004..11ab9b67f70 100644 --- a/boards/qemu/x86/qemu_x86_atom_nommu_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_nommu_defconfig @@ -9,7 +9,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=n -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SCHED_SIMPLE=y CONFIG_WAITQ_SIMPLE=y CONFIG_X86_VERY_EARLY_CONSOLE=n diff --git a/boards/qemu/x86/qemu_x86_atom_nopae_defconfig b/boards/qemu/x86/qemu_x86_atom_nopae_defconfig index bccb2e2771e..f9b6a84df16 100644 --- a/boards/qemu/x86/qemu_x86_atom_nopae_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_nopae_defconfig @@ -9,7 +9,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y diff --git a/boards/qemu/x86/qemu_x86_atom_virt_defconfig b/boards/qemu/x86/qemu_x86_atom_virt_defconfig index f4a79e4d306..16f4f9f30f7 100644 --- a/boards/qemu/x86/qemu_x86_atom_virt_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_virt_defconfig @@ -9,7 +9,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y diff --git a/boards/qemu/x86/qemu_x86_atom_xip_defconfig b/boards/qemu/x86/qemu_x86_atom_xip_defconfig index 230d6ea36d2..aa6784d44ac 100644 --- a/boards/qemu/x86/qemu_x86_atom_xip_defconfig +++ b/boards/qemu/x86/qemu_x86_atom_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=n -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y diff --git a/boards/qemu/x86/qemu_x86_defconfig b/boards/qemu/x86/qemu_x86_defconfig index 754f0a47c83..a1860500edf 100644 --- a/boards/qemu/x86/qemu_x86_defconfig +++ b/boards/qemu/x86/qemu_x86_defconfig @@ -9,7 +9,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y diff --git a/boards/qemu/x86/qemu_x86_lakemont_defconfig b/boards/qemu/x86/qemu_x86_lakemont_defconfig index 754f0a47c83..a1860500edf 100644 --- a/boards/qemu/x86/qemu_x86_lakemont_defconfig +++ b/boards/qemu/x86/qemu_x86_lakemont_defconfig @@ -9,7 +9,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y diff --git a/boards/qemu/x86/qemu_x86_tiny_defconfig b/boards/qemu/x86/qemu_x86_tiny_defconfig index 349e1b6ec71..6b3ac0756c9 100644 --- a/boards/qemu/x86/qemu_x86_tiny_defconfig +++ b/boards/qemu/x86/qemu_x86_tiny_defconfig @@ -9,7 +9,7 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y +CONFIG_X86_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y diff --git a/boards/rakwireless/rak11720/rak11720.dts b/boards/rakwireless/rak11720/rak11720.dts index 6596d689962..e27d195477b 100644 --- a/boards/rakwireless/rak11720/rak11720.dts +++ b/boards/rakwireless/rak11720/rak11720.dts @@ -32,7 +32,6 @@ led0 = &blue_led; led1 = &green_led; lora0 = &lora; - bootloader-led0 = &blue_led; mcuboot-led0 = &blue_led; }; @@ -150,36 +149,46 @@ }; }; -&counter0 { - status = "okay"; -}; - -&counter1 { - status = "okay"; +&timer0 { + counter0: counter { + status = "okay"; + }; }; -&counter2 { - status = "okay"; +&timer1 { + counter1: counter { + status = "okay"; + }; }; -&counter3 { - status = "okay"; +&timer2 { + counter2: counter { + status = "okay"; + }; }; -&counter4 { - status = "okay"; +&timer4 { + counter4: counter { + status = "okay"; + }; }; -&counter5 { - status = "okay"; +&timer5 { + counter5: counter { + status = "okay"; + }; }; -&counter6 { - status = "okay"; +&timer6 { + counter6: counter { + status = "okay"; + }; }; -&counter7 { - status = "okay"; +&timer7 { + counter7: counter { + status = "okay"; + }; }; &gpio0_31 { diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst index ea279a93192..6303419ad0d 100644 --- a/boards/raspberrypi/rpi_pico/doc/index.rst +++ b/boards/raspberrypi/rpi_pico/doc/index.rst @@ -4,7 +4,7 @@ Overview ******** The `Raspberry Pi Pico`_ and Pico W are small, low-cost, versatile boards from -Raspberry Pi. They are equipped with an `RP2040 `_ SoC, an on-board LED, +Raspberry Pi. They are equipped with an `RP2040 `_ SoC, an on-board LED, a USB connector, and an SWD interface. The Pico W additionally contains an `Infineon CYW43439`_ 2.4 GHz Wi-Fi/Bluetooth module. diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_defconfig index df003531af9..aaaa51cbdb9 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico_defconfig +++ b/boards/raspberrypi/rpi_pico/rpi_pico_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts index cba2142f7b5..55a41e48954 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts @@ -28,8 +28,7 @@ airoc_wifi_host_wake: airoc_wifi_host_wake { /* Assign GPIO24 to SIO (GPIO) for use as an interrupt source */ group1 { - /* Lacking a specific SIO pin definition, use the RP2040_PINMUX macro */ - pinmux = ; + pinmux = ; input-enable; }; }; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig index d1e96b968c5..9438a979c63 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig @@ -1,4 +1,3 @@ -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/raspberrypi/rpi_pico2/Kconfig b/boards/raspberrypi/rpi_pico2/Kconfig new file mode 100644 index 00000000000..50f0cba2750 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Magpie Embedded +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 16384 if NETWORKING diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.defconfig b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig index d122f3e4918..f0c7c0a89a2 100644 --- a/boards/raspberrypi/rpi_pico2/Kconfig.defconfig +++ b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig @@ -6,4 +6,15 @@ if BOARD_RPI_PICO2 config USB_SELF_POWERED default n +if WIFI_AIROC + +choice AIROC_PART + default CYW43439 +endchoice + +config WHD_DISABLE_SDIO_PULLUP_DURING_SPI_SLEEP + default y + +endif # WIFI_AIROC + endif # BOARD_RPI_PICO2 diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 index bcce97758fb..6e7a1a44569 100644 --- a/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 +++ b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 @@ -1,5 +1,6 @@ # Copyright (c) 2024 Andrew Featherstone +# Copyright (c) 2025 Magpie Embedded # SPDX-License-Identifier: Apache-2.0 config BOARD_RPI_PICO2 - select SOC_RP2350A_M33 if BOARD_RPI_PICO2_RP2350A_M33 + select SOC_RP2350A_M33 if BOARD_RPI_PICO2_RP2350A_M33 || BOARD_RPI_PICO2_RP2350A_M33_W diff --git a/boards/raspberrypi/rpi_pico2/board.cmake b/boards/raspberrypi/rpi_pico2/board.cmake index feae063129a..dc6406b4122 100644 --- a/boards/raspberrypi/rpi_pico2/board.cmake +++ b/boards/raspberrypi/rpi_pico2/board.cmake @@ -12,7 +12,9 @@ board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") # https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000") +board_runner_args(jlink "--device=RP2350_M33_0") board_runner_args(uf2 "--board-id=RP2350") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/raspberrypi/rpi_pico2/board.yml b/boards/raspberrypi/rpi_pico2/board.yml index 2ab8ee59989..46364e8cbd0 100644 --- a/boards/raspberrypi/rpi_pico2/board.yml +++ b/boards/raspberrypi/rpi_pico2/board.yml @@ -4,3 +4,6 @@ board: vendor: raspberrypi socs: - name: rp2350a + variants: + - name: w + cpucluster: m33 diff --git a/boards/raspberrypi/rpi_pico2/doc/index.rst b/boards/raspberrypi/rpi_pico2/doc/index.rst index 612497a0b3c..2c0810b1153 100644 --- a/boards/raspberrypi/rpi_pico2/doc/index.rst +++ b/boards/raspberrypi/rpi_pico2/doc/index.rst @@ -3,9 +3,10 @@ Overview ******** -The Raspberry Pi Pico 2 is the second-generation product in the Raspberry Pi +The Raspberry Pi Pico 2 and Pico 2W are second-generation products in the Raspberry Pi Pico family. From the `Raspberry Pi website `_ is referred to as Pico 2. + There are many limitations of the board currently. Including but not limited to: - The Zephyr build only supports configuring the RP2350A with the Cortex-M33 cores. - As with the Pico 1, there's no support for running any code on the second core. @@ -23,6 +24,7 @@ Hardware - 2 Timer with 4 alarms, 1 AON Timer - Temperature sensor - 3 Programmable IO (PIO) blocks, 12 state machines total for custom peripheral support +- Infineon CYW43439 2.4 GHz Wi-Fi chip (Pico 2W only) - Flexible, user-programmable high-speed IO - Can emulate interfaces such as SD Card and VGA @@ -42,16 +44,24 @@ Programming and Debugging .. zephyr:board-supported-runners:: -The overall explanation regarding flashing and debugging is the same as or :zephyr:board:`rpi_pico`. +The overall explanation regarding flashing and debugging is the same as for :zephyr:board:`rpi_pico`. See :ref:`rpi_pico_programming_and_debugging` in :zephyr:board:`rpi_pico` documentation. N.b. OpenOCD support requires using Raspberry Pi's forked version of OpenOCD. Below is an example of building and flashing the :zephyr:code-sample:`blinky` application. .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: rpi_pico2/rp2350a/m33 - :goals: build flash - :flash-args: --openocd /usr/local/bin/openocd + :zephyr-app: samples/basic/blinky + :board: rpi_pico2/rp2350a/m33 + :goals: build flash + :flash-args: --openocd /usr/local/bin/openocd + +The blinky sample is not yet supported on Pico 2W, so try the :zephyr:code-sample:`wifi-shell` application to connect to the network: + +.. zephyr-app-commands:: + :zephyr-app: samples/net/wifi/shell + :board: rpi_pico2/rp2350a/m33/w + :goals: build flash + :flash-args: --openocd /usr/local/bin/openocd References ********** diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi index 522413c94f1..3b499811147 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi @@ -16,9 +16,9 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,flash-controller = &qmi; zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,code-partition = &code_partition; }; aliases { @@ -61,33 +61,6 @@ &flash0 { reg = <0x10000000 DT_SIZE_M(4)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserved memory for an image definition block. The block is much - * smaller than 256 bytes, but in practice the linker places the vector - * table at a much larger alignment offset. - */ - image_def: partition@0 { - label = "image_def"; - reg = <0x00000000 0x100>; - read-only; - }; - - /* - * Usable flash. Starts at 0x100, after the image definition block. - * The partition size is 4MB minus the 0x100 bytes taken by the - * image definition. - */ - code_partition: partition@100 { - label = "code-partition"; - reg = <0x100 (DT_SIZE_M(4) - 0x100)>; - read-only; - }; - }; }; &uart0 { diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig index 8bd68e35113..4da77bdb95c 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig @@ -8,7 +8,6 @@ CONFIG_CONSOLE=y CONFIG_GPIO=y CONFIG_RESET=y CONFIG_SERIAL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000 CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.dts b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.dts new file mode 100644 index 00000000000..9c36addf655 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.dts @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 Magpie Embedded + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +/* The build system assumes that there's a cpucluster-specific file. + * + * This file provides composition of the device tree: + * 1. The common features of the SoC + * 2. Core-specific configuration. + * 3. Board-specific configuration. + */ +#include +#include + +/* there's nothing specific to the Cortex-M33 cores vs the (not yet + * implemented) Hazard3 cores. + */ +#include "rpi_pico2.dtsi" + +&pinctrl { + pio0_spi0_default: pio0_spi0_default { + /* gpio 25 is used for chip select, not assigned to the PIO */ + group1 { + pinmux = ; + }; + }; + + airoc_wifi_default: airoc_wifi_default { + /* Control of GPIO24 is done through the WiFi driver */ + group1 { + pinmux = ; + input-enable; + }; + }; + + airoc_wifi_host_wake: airoc_wifi_host_wake { + /* Assign GPIO24 to SIO (GPIO) for use as an interrupt source */ + group1 { + pinmux = ; + input-enable; + }; + }; +}; + +&pio0 { + status = "okay"; + + pio0_spi0: pio0_spi0 { + compatible = "raspberrypi,pico-spi-pio"; + clocks = < &clocks RPI_PICO_CLKID_CLK_SYS >; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + clk-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + sio-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pio0_spi0_default>; + pinctrl-names = "default"; + status = "okay"; + + airoc-wifi@0 { + compatible = "infineon,airoc-wifi"; + reg = < 0 >; + wifi-reg-on-gpios = < &gpio0 23 GPIO_ACTIVE_HIGH >; + bus-select-gpios = < &gpio0 24 GPIO_ACTIVE_HIGH >; + wifi-host-wake-gpios = < &gpio0 24 GPIO_ACTIVE_HIGH >; + spi-max-frequency = < 10000000 >; + spi-half-duplex; + spi-data-irq-shared; + pinctrl-0 = <&airoc_wifi_default>; + pinctrl-1 = <&airoc_wifi_host_wake>; + pinctrl-names = "default", "host_wake"; + status = "okay"; + }; + }; +}; diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.yaml new file mode 100644 index 00000000000..afed35e60ed --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w.yaml @@ -0,0 +1,22 @@ +identifier: rpi_pico2/rp2350a/m33/w +name: Raspberry Pi Pico 2 (Cortex-M33) WiFi +type: mcu +arch: arm +flash: 4096 +ram: 520 +toolchain: + - zephyr + - gnuarmemb +supported: + - adc + - clock + - counter + - dma + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart + - watchdog + - wifi diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_defconfig new file mode 100644 index 00000000000..4da77bdb95c --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_w_defconfig @@ -0,0 +1,13 @@ +# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores +# are in use, but Zephyr does not support providing a qualifier-agnostic +# _defconfig file. +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/raytac/an54l15q_db/Kconfig.defconfig b/boards/raytac/an54l15q_db/Kconfig.defconfig index 82d59ecdbe3..72616407eb7 100644 --- a/boards/raytac/an54l15q_db/Kconfig.defconfig +++ b/boards/raytac/an54l15q_db/Kconfig.defconfig @@ -15,7 +15,7 @@ endif # BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP if BOARD_RAYTAC_AN54L15Q_DB_NRF54L15_CPUAPP_NS -config BT_CTLR +config HAS_BT_CTLR default BT config FLASH_LOAD_OFFSET diff --git a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml index 11ee50ba277..8662a82fad6 100644 --- a/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml +++ b/boards/raytac/an54l15q_db/raytac_an54l15q_db_nrf54l15_cpuapp_ns.yaml @@ -1,6 +1,6 @@ # Copyright (c) 2025 Nordic Semiconductor ASA # Copyright (c) 2025 Raytac Corporation. -# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# SPDX-License-Identifier: Apache-2.0 identifier: raytac_an54l15q_db/nrf54l15/cpuapp/ns name: Raytac-AN54L15Q-DB-nRF54l15-Application-Non-Secure diff --git a/boards/raytac/an7002q_db/Kconfig b/boards/raytac/an7002q_db/Kconfig new file mode 100644 index 00000000000..f5493e172d7 --- /dev/null +++ b/boards/raytac/an7002q_db/Kconfig @@ -0,0 +1,29 @@ +# Raytac AN7002Q-DB-5340 board configuration + +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUAPP + +config BT_HCI_IPC + default y if BT + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif + +if BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUNET + +config BT_ECC + default y if BT + +endif diff --git a/boards/raytac/an7002q_db/Kconfig.raytac_an7002q_db b/boards/raytac/an7002q_db/Kconfig.raytac_an7002q_db new file mode 100644 index 00000000000..ecd82f1392d --- /dev/null +++ b/boards/raytac/an7002q_db/Kconfig.raytac_an7002q_db @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_AN7002Q_DB + select SOC_NRF5340_CPUNET_QKAA if BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUNET + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUAPP diff --git a/boards/raytac/an7002q_db/board.cmake b/boards/raytac/an7002q_db/board.cmake new file mode 100644 index 00000000000..7031dfcfe37 --- /dev/null +++ b/boards/raytac/an7002q_db/board.cmake @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUAPP) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(CONFIG_BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/raytac/an7002q_db/board.yml b/boards/raytac/an7002q_db/board.yml new file mode 100644 index 00000000000..cccc739b091 --- /dev/null +++ b/boards/raytac/an7002q_db/board.yml @@ -0,0 +1,6 @@ +board: + name: raytac_an7002q_db + full_name: AN7002Q-DB-5340 + vendor: raytac + socs: + - name: nrf5340 diff --git a/boards/raytac/an7002q_db/doc/img/raytac_an7002q_db_5340.webp b/boards/raytac/an7002q_db/doc/img/raytac_an7002q_db_5340.webp new file mode 100644 index 00000000000..3a31653c646 Binary files /dev/null and b/boards/raytac/an7002q_db/doc/img/raytac_an7002q_db_5340.webp differ diff --git a/boards/raytac/an7002q_db/doc/index.rst b/boards/raytac/an7002q_db/doc/index.rst new file mode 100644 index 00000000000..518f20bb884 --- /dev/null +++ b/boards/raytac/an7002q_db/doc/index.rst @@ -0,0 +1,261 @@ +.. zephyr:board:: raytac_an7002q_db + +Overview +******** + +The Raytac AN7002Q-DB-5340 is a single-board development kit for evaluation and development on +the nRF7002, a Wi-Fi companion IC to Raytac's MDBT53 module host processor. +It is certified for the Wi-Fi Alliance® `Wi-Fi Certification program`_ in the +Connectivity, Security, and Optimization categories. See `UG Wi-Fi certification`_ for detailed +information. + +The nRF7002 is an IEEE 802.11ax (Wi-Fi 6) compliant solution that implements the Wi-Fi physical +layer and Medium Access Control (MAC) layer protocols. It implements the nRF Wi-Fi driver +software on the nRF5340 host processor communicating over the QSPI bus. + +The nRF5340 host is a dual-core SoC based on the Arm® Cortex®-M33 architecture. +It has the following features: + +* A full-featured Arm Cortex-M33F core with DSP instructions, FPU, and Armv8-M Security Extension, + running at up to 128 MHz, referred to as the application core. +* A secondary Arm Cortex-M33 core, with a reduced feature set, running at a fixed 64 MHz, + referred to as the network core. + +The ``raytac_an7002q_db/nrf5340/cpuapp`` board target provides support for the application core on the +nRF5340 SoC. The ``raytac_an7002q_db/nrf5340/cpunet`` board target provides support for the network +core on the nRF5340 SoC. + +More information about the board can be found at the +`Raytac AN7002Q-DB-5340 website`_. +The `Raytac AN7002Q-DB-5340 Product Specification`_ +contains the processor's information and the datasheet. + +Hardware +======== + +* Raytac AN7002Q-DB-5340: + The Raytac AN7002Q-DB-5340 has two modules. + + * The WiFi module of the AN7002Q-P. + * The BLE module of the MDBT5340-P. + + +Supported features +------------------ + +.. zephyr:board-supported-hw:: + +See `Raytac AN7002Q-DB-5340 Product Specification`_ +for a complete list of Raytac AN7002Q-DB-5340 board hardware features. + +Connections and IOs +------------------- + +The connections and IOs supported by the development kit are listed in this section. + +LED +^^^ + +* **LED 1** (green) = **P1.06** +* **LED 2** (green) = **P1.07** + +Push buttons +^^^^^^^^^^^^ + +* **Button 1** = **SW1** = **P1.08** +* **Button 2** = **SW2** = **P1.09** + +Wi-Fi control +^^^^^^^^^^^^^ + +* BUCKEN = **P0.12** +* HOST IRQ = **P0.23** +* COEX_REQ = **P0.28** +* COEX_STATUS0 = **P0.30** +* COEX_STATUS1 = **P0.29** +* COEX_GRANT = **P0.24** + +Security components +------------------- + +The following security components are available: + +* Implementation Defined Attribution Unit (`IDAU`_) on the application core. + + The IDAU is implemented with the System Protection Unit and is used to define + secure and non-secure memory maps. By default, the entire memory space + (Flash, SRAM, and peripheral address space) is defined to be secure-accessible only. + +* Secure boot. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The nRF5340 application core supports the Armv8-M Security Extension. +Applications built for the ``raytac_an7002q_db/nrf5340/cpuapp`` board boot by default in the +secure state. + +The nRF5340 network core does not support the Armv8-M Security Extension. +nRF5340 IDAU can configure bus accesses by the nRF5340 network core to have the secure +attribute set. This allows to build and run secure-only applications on the nRF5340 SoC. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the nRF5340 may contain a Secure and a Non-Secure firmware +image for the application core. The Secure image can be built using either +Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure firmware +images are always built using Zephyr. The two alternatives are described below. + +.. note:: + + By default, SPE for the nRF5340 application core is built using TF-M. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for the application core using ``-DBOARD=raytac_an7002q_db/nrf5340/cpuapp/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +2. Build the application firmware for the network core using + ``-DBOARD=raytac_an7002q_db/nrf5340/cpunet``. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for the application core + using ``-DBOARD=raytac_an7002q_db/nrf5340/cpuapp`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for the application core + using ``-DBOARD=raytac_an7002q_db/nrf5340/cpuapp/ns``. +3. Merge the two binaries together. +4. Build the application firmware for the network core using + ``-DBOARD=raytac_an7002q_db/nrf5340/cpunet``. + +When building a Secure/Non-Secure application for the nRF5340 application core, +the Secure application will have to set the IDAU (SPU) configuration to allow +Non-Secure access to all CPU resources utilized by the Non-Secure application +firmware. SPU configuration shall take place before jumping to the Non-Secure +application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=raytac_an7002q_db/nrf5340/cpuapp`` for +the firmware running on the nRF5340 application core, and using +``-DBOARD=raytac_an7002q_db/nrf5340/cpunet`` for the firmware running +on the nRF5340 network core. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The nRF5340 has a flash read-back protection feature. When flash read-back + protection is active, you will need to recover the chip before reflashing. + If you are flashing with :ref:`west `, run + this command for more details on the related ``--recover`` option: + + .. code-block:: console + + $ west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the nRF5340 DK requires + upgrading the nRF Command Line Tools to version 10.12.0. Further + information on how to install the nRF Command Line Tools can be + found in :ref:`nordic_segger_flashing`. + +Here is an example for the :zephyr:code-sample:`hello_world` application running on the +nRF5340 application core. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF7002 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: raytac_an7002q_db/nrf5340/cpuapp + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + +Next steps +********** + +You have now completed getting started with the Raytac AN7002Q-DB-5340. +See the following links for where to go next: + +* `Installation`_ and `Configuring and Building`_ documentation to install the + nRF Connect SDK and learn more about its development environment. +* `Developing with nRF70`_ documentation for more advanced topics related to the nRF70 Series. +* `Wi-Fi`_ documentation for information related to Wi-Fi protocol and Wi-Fi modes of operation. + +References +********** + +.. target-notes:: + +.. _Wi-Fi Certification program: + https://www.wi-fi.org/certification +.. _UG Wi-Fi certification: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/protocols/wifi/wifi_certification.html#ug-wifi-certification +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _Raytac AN7002Q-DB-5340 website: + https://www.raytac.com/product/ins.php?index_id=139 +.. _Raytac AN7002Q-DB-5340 Product Specification: + https://www.raytac.com/download/index.php?index_id=79 +.. _Trusted Firmware M: + https://www.trustedfirmware.org/projects/tf-m/ +.. _Installation: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/installation.html#installation +.. _Configuring and Building: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/config_and_build/index.html#configuration-and-build +.. _Developing with nRF70: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf70/index.html#ug-nrf70-developing +.. _Wi-Fi: + https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/protocols/wifi/index.html#ug-wifi diff --git a/boards/raytac/an7002q_db/nrf5340_cpuapp_common.dtsi b/boards/raytac/an7002q_db/nrf5340_cpuapp_common.dtsi new file mode 100644 index 00000000000..aa07ccff7c4 --- /dev/null +++ b/boards/raytac/an7002q_db/nrf5340_cpuapp_common.dtsi @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "nrf5340_cpuapp_common_pinctrl.dtsi" +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,bt-hci = &bt_hci_ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + }; + + gpio_fwd: nrf-gpio-forwarder { + compatible = "nordic,nrf-gpio-forwarder"; + + status = "okay"; + + uart { + gpios = <&gpio1 1 0>, <&gpio1 0 0>, <&gpio1 5 0>, <&gpio1 4 0>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + sw0 = &button0; + sw1 = &button1; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0; + watchdog0 = &wdt0; + }; + + nrf_radio_coex: coex { + status = "okay"; + compatible = "nordic,nrf7002-coex"; + req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; + swctrl1-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; +}; + +&vregmain { + regulator-initial-mode = ; +}; + +&vregradio { + regulator-initial-mode = ; +}; + +&vregh { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c1 { + compatible = "nordic,nrf-twim"; + + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi4 { + compatible = "nordic,nrf-spim"; + status = "okay"; + + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + compatible = "nordic,nrf-uarte"; + + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi3 { + compatible = "nordic,nrf-spim"; + + cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + + status = "okay"; +}; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/raytac/an7002q_db/nrf5340_cpuapp_common_pinctrl.dtsi b/boards/raytac/an7002q_db/nrf5340_cpuapp_common_pinctrl.dtsi new file mode 100644 index 00000000000..0243f07df1d --- /dev/null +++ b/boards/raytac/an7002q_db/nrf5340_cpuapp_common_pinctrl.dtsi @@ -0,0 +1,128 @@ +&pinctrl { + i2c1_default: i2c1_default { + group1 { + psels = , + ; + }; + }; + + i2c1_sleep: i2c1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + pwm0_default: pwm0_default { + group1 { + psels = ; + }; + }; + + pwm0_sleep: pwm0_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + qspi_default: qspi_default { + group1 { + psels = , + , + , + , + , + ; + }; + }; + + qspi_sleep: qspi_sleep { + group1 { + psels = , + , + , + , + , + ; + low-power-enable; + }; + }; + + uart1_default: uart1_default { + group1 { + psels = ; + }; + + group2 { + psels = ; + bias-pull-up; + }; + }; + + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi3_default: spi3_default { + group1 { + psels = , + , + ; + }; + }; + + spi3_sleep: spi3_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi4_default: spi4_default { + group1 { + psels = , + , + ; + }; + }; + + spi4_sleep: spi4_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/raytac/an7002q_db/nrf70_common.dtsi b/boards/raytac/an7002q_db/nrf70_common.dtsi new file mode 100644 index 00000000000..cd9cd23bb89 --- /dev/null +++ b/boards/raytac/an7002q_db/nrf70_common.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +iovdd-ctrl-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; +bucken-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; +host-irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; +srrf-switch-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + +wifi-max-tx-pwr-2g-dsss = <21>; +wifi-max-tx-pwr-2g-mcs0 = <16>; +wifi-max-tx-pwr-2g-mcs7 = <16>; + +wlan0: wlan { + compatible = "nordic,wlan"; +}; diff --git a/boards/raytac/an7002q_db/nrf70_common_5g.dtsi b/boards/raytac/an7002q_db/nrf70_common_5g.dtsi new file mode 100644 index 00000000000..8be559cebc3 --- /dev/null +++ b/boards/raytac/an7002q_db/nrf70_common_5g.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +wifi-max-tx-pwr-5g-low-mcs0 = <9>; +wifi-max-tx-pwr-5g-low-mcs7 = <9>; +wifi-max-tx-pwr-5g-mid-mcs0 = <11>; +wifi-max-tx-pwr-5g-mid-mcs7 = <11>; +wifi-max-tx-pwr-5g-high-mcs0 = <13>; +wifi-max-tx-pwr-5g-high-mcs7 = <13>; diff --git a/boards/raytac/an7002q_db/pre_dt_board.cmake b/boards/raytac/an7002q_db/pre_dt_board.cmake new file mode 100644 index 00000000000..5db1310639d --- /dev/null +++ b/boards/raytac/an7002q_db/pre_dt_board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - flash-controller@39000 & kmu@39000 +# - power@5000 & clock@5000 +# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.dts b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.dts new file mode 100644 index 00000000000..8bcae1610db --- /dev/null +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.dts @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Raytac Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf5340_cpuapp_common.dtsi" +#include "raytac_an7002q_db_nrf5340_cpuapp_pinctrl.dtsi" + +/ { + model = "Raytac AN7002-DB NRF5340 Application"; + compatible = "raytac,raytac-an7002q-db-nrf5340-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + zephyr,wifi = &wlan0; + }; +}; + +&qspi { + nrf70: nrf7002@1 { + compatible = "nordic,nrf7002-qspi"; + status = "okay"; + reg = <1>; + qspi-frequency = <24000000>; + qspi-quad-mode; + + #include "nrf70_common.dtsi" + #include "nrf70_common_5g.dtsi" + }; +}; diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.yaml b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000..2fabdbda30e --- /dev/null +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.yaml @@ -0,0 +1,19 @@ +identifier: raytac_an7002q_db/nrf5340/cpuapp +name: Raytac-AN7002Q-DB-NRF5340-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usbd + - usb_device + - netif:openthread +vendor: raytac diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp_defconfig b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..49f3e03e263 --- /dev/null +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable RNG +CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG=y +CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG_ALLOW_NON_CSPRNG=y + +# ISN needs CS-Rand which isn't supported upstream for nRF boards +CONFIG_NET_TCP_ISN_RFC6528=n diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp_pinctrl.dtsi b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp_pinctrl.dtsi new file mode 100644 index 00000000000..a7cde7241e5 --- /dev/null +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp_pinctrl.dtsi @@ -0,0 +1,18 @@ +&pinctrl { + spi2_default: spi2_default { + group1 { + psels = , + , + ; + }; + }; + + spi2_sleep: spi2_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.dts b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.dts new file mode 100644 index 00000000000..dab7f282e85 --- /dev/null +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.dts @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * Copyright (c) 2025 Raytac Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "raytac_an7002q_db_nrf5340_cpunet_pinctrl.dtsi" +#include + +/ { + model = "Raytac AN7002Q-DB NRF5340 Network"; + compatible = "raytac,raytac-an7002q-db-nrf5340-cpunet"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,bt-hci-ipc = &ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + }; + + nrf_radio_coex: coex { + status = "okay"; + compatible = "nordic,nrf7002-coex"; + + req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; + swctrl1-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0; + watchdog0 = &wdt0; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c0 { + compatible = "nordic,nrf-twim"; + /* Cannot be used together with uart0. */ + /* status = "okay"; */ + + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi0 { + compatible = "nordic,nrf-spim"; + /* Cannot be used together with uart0. */ + /* status = "okay"; */ + + cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xc000>; + }; + + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x17000>; + }; + + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 0x17000>; + }; + + storage_partition: partition@3a000 { + label = "storage"; + reg = <0x0003a000 0x6000>; + }; + }; +}; + +&ieee802154 { + status = "okay"; +}; + +/* Include default shared RAM configuration file */ +#include diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.yaml b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.yaml new file mode 100644 index 00000000000..84c0987c08d --- /dev/null +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.yaml @@ -0,0 +1,13 @@ +identifier: raytac_an7002q_db/nrf5340/cpunet +name: Raytac AN7002Q-DB-NRF5340-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - zephyr +ram: 64 +flash: 256 +supported: + - gpio + - watchdog +vendor: raytac diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet_defconfig b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..56940c43a09 --- /dev/null +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet_pinctrl.dtsi b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet_pinctrl.dtsi new file mode 100644 index 00000000000..0abcb4724d5 --- /dev/null +++ b/boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet_pinctrl.dtsi @@ -0,0 +1,56 @@ +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + psels = , + , + ; + }; + }; + + spi0_sleep: spi0_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/raytac/mdbt50q_cx_40_dongle/CMakeLists.txt b/boards/raytac/mdbt50q_cx_40_dongle/CMakeLists.txt new file mode 100644 index 00000000000..218a0602483 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/raytac/mdbt50q_cx_40_dongle/Kconfig b/boards/raytac/mdbt50q_cx_40_dongle/Kconfig new file mode 100644 index 00000000000..36da7f834a6 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/Kconfig @@ -0,0 +1,16 @@ +# Raytac MDBT50Q-CX Dongle NRF52840 board configuration +# +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT50Q_CX_40_DONGLE + +config BOARD_HAS_NRF5_BOOTLOADER + bool "Board has nRF5 bootloader" + default y + help + If selected, applications are linked so that they can be loaded by Nordic + nRF5 bootloader. + +endif # BOARD_RAYTAC_MDBT50Q_CX_40_DONGLE diff --git a/boards/raytac/mdbt50q_cx_40_dongle/Kconfig.defconfig b/boards/raytac/mdbt50q_cx_40_dongle/Kconfig.defconfig new file mode 100644 index 00000000000..ddfe9b77256 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Raytac MDBT50Q-CX-40 Dongle NRF52840 board configuration +# +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT50Q_CX_40_DONGLE + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# the offset is applied here so that the full partition size can be used when +# the bootloader Kconfig option has been disabled. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION) + +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" + +endif # BOARD_RAYTAC_MDBT50Q_CX_40_DONGLE diff --git a/boards/raytac/mdbt50q_cx_40_dongle/Kconfig.raytac_mdbt50q_cx_40_dongle b/boards/raytac/mdbt50q_cx_40_dongle/Kconfig.raytac_mdbt50q_cx_40_dongle new file mode 100644 index 00000000000..416aa75a1b5 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/Kconfig.raytac_mdbt50q_cx_40_dongle @@ -0,0 +1,8 @@ +# Raytac MDBT50Q-CX-40 Dongle nRF52840 board configuration +# +# Copyright (c) 2018 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT50Q_CX_40_DONGLE + select SOC_NRF52840_QIAA diff --git a/boards/raytac/mdbt50q_cx_40_dongle/board.c b/boards/raytac/mdbt50q_cx_40_dongle/board.c new file mode 100644 index 00000000000..04c1abe7f6f --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/board.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA. + * Copyright (c) 2025 Raytac Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +void board_early_init_hook(void) +{ + /* if the raytac_mdbt50q_cx_40_dongle is powered from USB + * (high voltage mode), GPIO output voltage is set to 1.8 volts by + * default and that is not enough to turn the LEDs on. + * Increase GPIO voltage to 3.0 volts. + */ + if ((nrf_power_mainregstatus_get(NRF_POWER) == + NRF_POWER_MAINREGSTATUS_HIGH) && + ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) == + (UICR_REGOUT0_VOUT_DEFAULT << UICR_REGOUT0_VOUT_Pos))) { + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { + __NOP(); + } + + NRF_UICR->REGOUT0 = + (NRF_UICR->REGOUT0 & ~((uint32_t)UICR_REGOUT0_VOUT_Msk)) | + (UICR_REGOUT0_VOUT_3V0 << UICR_REGOUT0_VOUT_Pos); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { + __NOP(); + } + + /* a reset is required for changes to take effect */ + NVIC_SystemReset(); + } +} diff --git a/boards/raytac/mdbt50q_cx_40_dongle/board.cmake b/boards/raytac/mdbt50q_cx_40_dongle/board.cmake new file mode 100644 index 00000000000..b052a8936bf --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nrf52840_xxaa" "--speed=4000") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/raytac/mdbt50q_cx_40_dongle/board.yml b/boards/raytac/mdbt50q_cx_40_dongle/board.yml new file mode 100644 index 00000000000..7d320d72e92 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/board.yml @@ -0,0 +1,6 @@ +board: + name: raytac_mdbt50q_cx_40_dongle + full_name: MDBT50Q-CX-40 Dongle + vendor: raytac + socs: + - name: nrf52840 diff --git a/boards/raytac/mdbt50q_cx_40_dongle/doc/img/raytac_mdbt50q_cx_40_dongle.webp b/boards/raytac/mdbt50q_cx_40_dongle/doc/img/raytac_mdbt50q_cx_40_dongle.webp new file mode 100644 index 00000000000..4bc0abb90b7 Binary files /dev/null and b/boards/raytac/mdbt50q_cx_40_dongle/doc/img/raytac_mdbt50q_cx_40_dongle.webp differ diff --git a/boards/raytac/mdbt50q_cx_40_dongle/doc/img/raytac_mdbt50q_cx_40_dongle_button_led.webp b/boards/raytac/mdbt50q_cx_40_dongle/doc/img/raytac_mdbt50q_cx_40_dongle_button_led.webp new file mode 100644 index 00000000000..bd88377bfce Binary files /dev/null and b/boards/raytac/mdbt50q_cx_40_dongle/doc/img/raytac_mdbt50q_cx_40_dongle_button_led.webp differ diff --git a/boards/raytac/mdbt50q_cx_40_dongle/doc/index.rst b/boards/raytac/mdbt50q_cx_40_dongle/doc/index.rst new file mode 100644 index 00000000000..ba046fb55b7 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/doc/index.rst @@ -0,0 +1,296 @@ +.. zephyr:board:: raytac_mdbt50q_cx_40_dongle + +Overview +******** + +The Raytac MDBT50Q-CX-40 Dongle hardware provides support for the Nordic +Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +- Nordic nRF52840 SoC Solution Dongle +- A recommended 3rd-party module by Nordic Semiconductor. +- BT5.4 & BT5.2 & BT5.1 & BT5 Bluetooth Specification Certified. +- Type C USB +- Supports Open Bootloader +- Supports BT5 Long Range Feature +- Deployed Raytac MDBT50Q-P1M Module +- Certifications: FCC, IC, CE, UKCA, Telec (MIC), KC, SRRC, NCC, RCM, WPC +- 32-bit ARM® Cortex™ M4F CPU +- 1MB Flash Memory / 256kB RAM +- RoHS & Reach Compliant. +- Dimension：26.2 x 15.1 x 6.8 mm (excluding Type C USB Connector) +- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, + ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. + +Hardware +******** + +The ``raytac_mdbt50q_cx_40_dongle/nrf52840`` board target has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock is 32 MHz. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +LED +--- + +* LED0 ( blue ) = P0.8 +* LED1 ( blue ) = P0.6 (No pasted components by default) + +Push buttons +------------ + +* BUTTON1 = SW1 = P1.6 + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``raytac_mdbt50q_cx_40_dongle/nrf52840`` board target can be +built in the usual way (see :ref:`build_an_application` for more details). + +Flashing +======== + +The board supports the following programming options: + +1. Using the built-in bootloader only +2. Using MCUboot in serial recovery mode +3. Using an external :ref:`debug probe ` + +These instructions use the :ref:`west ` tool and assume you are in the +root directory of your :term:`west installation`. + +Option 1: Using the Built-In Bootloader Only +-------------------------------------------- + +The board is factory-programmed with Open bootloader from Nordic's nRF5 +SDK. With this option, you'll use Nordic's `nrfutil`_ program to create +firmware packages supported by this bootloader and flash them to the +device. Make sure ``nrfutil`` is installed before proceeding. + +#. Hold the button and plug it into the USB socket in the bootloader. + + The push button is on the far side of the board from the USB connector. Note + that the button does not face up. You will have to push it from the outside + in, towards the USB connector: + + .. image:: img/raytac_mdbt50q_cx_40_dongle_button_led.webp + :alt: Location of the user button and LED. + + The red LED should start a fade pattern, signalling the bootloader is + running. + +#. Compile a Zephyr application; we'll use :zephyr:code-sample:`blinky`. + + .. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: raytac_mdbt50q_cx_40_dongle/nrf52840 + :goals: build + +#. Package the application for the bootloader using ``nrfutil``: + + .. code-block:: console + + nrfutil nrf5sdk-tools pkg generate \ + --hw-version 52 \ + --sd-req=0x00 \ + --application build/zephyr/zephyr.hex \ + --application-version 1 \ + blinky.zip + +#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be + something like ``COMx`` on Windows, and something else on macOS. + + .. code-block:: console + + nrfutil nrf5sdk-tools dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0 + + When this command exits, observe the green LED on the board blinking, + instead of the red LED used by the bootloader. + +For more information, see `Nordic Semiconductor USB DFU`_. + +Option 2: Using MCUboot in Serial Recovery Mode +----------------------------------------------- + +It is also possible to use the MCUboot bootloader with this board to flash +Zephyr applications. You need to do some one-time set-up to build and flash +MCUboot on your board. From that point on, you can build and flash other Zephyr +applications using MCUboot's serial recovery mode. This process does not +overwrite the built-in Nordic bootloader, so you can always go back to using +Option 1 later. + +Install `nrfutil`_ and `mcumgr`_ first, and make sure MCUboot's ``imgtool`` is +available for signing your binary for MCUboot as described on :ref:`west-sign`. + +Next, do the **one-time setup** to flash MCUboot. We'll assume you've cloned +the `MCUboot`_ repository into the directory ``mcuboot``, and that it is next +to the zephyr repository on your computer. + +#. Reset the board into the Nordic bootloader as described above. + +#. Compile MCUboot as a Zephyr application. + + .. zephyr-app-commands:: + :app: mcuboot/boot/zephyr + :board: raytac_mdbt50q_cx_40_dongle/nrf52840 + :build-dir: mcuboot + :goals: build + +#. Package the application for the bootloader using ``nrfutil``: + + .. code-block:: console + + nrfutil nrf5sdk-tools pkg generate \ + --hw-version 52 \ + --sd-req=0x00 \ + --application build/mcuboot/zephyr/zephyr.hex \ + --application-version 1 \ + mcuboot.zip + +#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be + something like ``COMx`` on Windows, and something else on macOS. + + .. code-block:: console + + nrfutil nrf5sdk-tools dfu usb-serial -pkg mcuboot.zip -p /dev/ttyACM0 + +You can now flash a Zephyr application to the board using MCUboot's serial +recovery mode. We'll use the :zephyr:code-sample:`smp-svr` sample since it's ready to be +compiled for chain-loading by MCUboot (and itself supports firmware updates +over Bluetooth). + +#. Boot into MCUboot serial recovery mode by plugging the board in with the SW1 + button pressed down. See above for a picture showing where SW1 is. + + A serial port will enumerate on your board. On Windows, "MCUBOOT" should + appear under "Other Devices" in the Device Manager (in addition to the usual + ``COMx`` device). On Linux, something like + :file:`/dev/serial/by-id/usb-ZEPHYR_MCUBOOT_0.01-if00` should be created. + + If no serial port appears, try plugging it in again, making sure SW1 is + pressed. If it still doesn't appear, retry the one-time MCUboot setup. + +#. Compile ``smp_svr``. + + .. zephyr-app-commands:: + :app: zephyr/samples/subsys/mgmt/mcumgr/smp_svr + :board: raytac_mdbt50q_cx_40_dongle/nrf52840 + :build-dir: smp_svr + :goals: build + +#. Sign ``smp_svr`` for chain-loading by MCUboot. + + .. code-block:: console + + west sign -t imgtool --bin --no-hex -d build/smp_svr \ + -B smp_svr.signed.bin -- --key mcuboot/root-rsa-2048.pem + +#. Flash the application to the MCUboot serial port using ``mcumgr``: + + .. code-block:: console + + mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' \ + image upload -e smp_svr.signed.bin + +#. Reset the device: + + .. code-block:: console + + mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' reset + +You should now be able to scan for Bluetooth devices using a smartphone or +computer. The device you just flashed will be listed with ``Zephyr`` in its +name. + +.. note:: + + This board supports building other Zephyr applications for flashing with + MCUboot in this way also. Just make sure :kconfig:option:`CONFIG_BOOTLOADER_MCUBOOT` + is set when building your application. For example, to compile blinky for + loading by MCUboot, use this: + + .. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: raytac_mdbt50q_cx_40_dongle/nrf52840 + :build-dir: blinky + :goals: build + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y + + You can then sign and flash it using the steps above. + +Option 3: Using an External Debug Probe +--------------------------------------- + +If you have one, you can also use an external :ref:`debug probe ` +to flash and debug Zephyr applications, but you need to solder an SWD header +onto the back side of the board. + +For Segger J-Link debug probes, follow the instructions in the +:ref:`nordic_segger` page to install and configure all the necessary +software. Further information can be found in :ref:`nordic_segger_flashing`. + +Locate the DTS file: :``boards/raytac/raytac_mdbt50q_cx_40_dongle_nrf52840.dts``. +This file requires a small modification to use a different partition table. +Edit the include directive to include "fstab-debugger" instead of "fstab-stock". + +In addition, the Kconfig file in the same directory must be modified by setting +``BOARD_HAS_NRF5_BOOTLOADER`` to be default ``n``, otherwise the code will be +flashed with an offset. + +Then build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: raytac_mdbt50q_cx_40_dongle/nrf52840 + :goals: build flash + +Observe the LED on the board blinking. + +Debugging +========= + +The ``raytac_mdbt50q_cx_40_dongle/nrf52840`` board does not have an on-board J-Link debug IC +as some nRF5x development boards, however, instructions from the +:ref:`nordic_segger` page also apply to this board, with the additional step +of connecting an external debugger. + +Testing the LEDs and buttons on the Raytac MDBT50Q-CX-40 Dongle +*************************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and program the examples to make sure Zephyr is running correctly +on your board. + + +References +********** + +.. target-notes:: + +.. _Raytac MDBT50Q-CX-40 Dongle website: + https://www.raytac.com/product/ins.php?index_id=156 +.. _Raytac MDBT50Q-CX-40 Dongle Spec: https://www.raytac.com/download/index.php?index_id=72 +.. _Raytac MDBT50Q-CX-40 Dongle Hardware description: https://www.raytac.com/product/ins.php?index_id=156 +.. _Nordic Semiconductor USB DFU: + https://docs.nordicsemi.com/bundle/sdk_nrf5_v17.1.0/page/sdk_app_serial_dfu_bootloader.html +.. _nrfutil: + https://www.nordicsemi.com/Products/Development-tools/nrf-util +.. _MCUboot: + https://github.com/JuulLabs-OSS/mcuboot +.. _mcumgr: + https://github.com/apache/mynewt-mcumgr-cli diff --git a/boards/nordic/nrf52840dongle/fstab-debugger.dtsi b/boards/raytac/mdbt50q_cx_40_dongle/fstab-debugger.dtsi similarity index 100% rename from boards/nordic/nrf52840dongle/fstab-debugger.dtsi rename to boards/raytac/mdbt50q_cx_40_dongle/fstab-debugger.dtsi diff --git a/boards/nordic/nrf52840dongle/fstab-stock.dtsi b/boards/raytac/mdbt50q_cx_40_dongle/fstab-stock.dtsi similarity index 85% rename from boards/nordic/nrf52840dongle/fstab-stock.dtsi rename to boards/raytac/mdbt50q_cx_40_dongle/fstab-stock.dtsi index b487f02c153..7c16ea6ab8a 100644 --- a/boards/nordic/nrf52840dongle/fstab-stock.dtsi +++ b/boards/raytac/mdbt50q_cx_40_dongle/fstab-stock.dtsi @@ -1,5 +1,6 @@ /* - * Copyright (c) 2019 Nordic Semiconductor ASA + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2025 Raytac Corporation. * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,10 +35,10 @@ storage_partition: partition@dc000 { label = "storage"; - reg = <0x000dc000 0x00004000>; + reg = <0x000f0000 0x00004000>; }; - /* Nordic nRF5 bootloader <0xe0000 0x1c000> + /* Nordic nRF5 bootloader <0xf4000 0xa000> * * In addition, the last and second last flash pages * are used by the nRF5 bootloader and MBR to store settings. diff --git a/boards/raytac/mdbt50q_cx_40_dongle/pre_dt_board.cmake b/boards/raytac/mdbt50q_cx_40_dongle/pre_dt_board.cmake new file mode 100644 index 00000000000..3369c21d3af --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - power@40000000 & clock@40000000 & bprot@40000000 +# - acl@4001e000 & flash-controller@4001e000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840-pinctrl.dtsi b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840-pinctrl.dtsi new file mode 100644 index 00000000000..ecf992611e5 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840-pinctrl.dtsi @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2025 Raytac Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + pwm0_default: pwm0_default { + group1 { + psels = , + ; + nordic,invert; + }; + }; + + pwm0_sleep: pwm0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.dts b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.dts new file mode 100644 index 00000000000..5033b663707 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.dts @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2025 Raytac Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "raytac_mdbt50q_cx_40_dongle_nrf52840-pinctrl.dtsi" +#include +/ { + model = "raytac_mdbt50q_cx_40_dongle_nrf52840"; + compatible = "raytac,raytac-mdbt50q-cx-40-dongle-nrf52840"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + + led0_d1: led_0 { + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + label = "LED D1"; + }; + + led1_d2: led_1 { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + label = "LED D2"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + d1_pwm_led: pwm_led_0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + + d2_pwm_led: pwm_led_1 { + pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 0"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + sw0 = &button0; + led0 = &led0_d1; + led1 = &led1_d2; + led0-green = &led0_d1; + led1-red = &led1_d2; + pwm-led0 = &d1_pwm_led; + pwm-led1 = &d2_pwm_led; + red-pwm-led = &d2_pwm_led; + green-pwm-led = &d1_pwm_led; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0_d1; + watchdog0 = &wdt0; + }; +}; + +®0 { + status = "disabled"; +}; + +®1 { + regulator-initial-mode = <0>; +}; + +&gpiote { + status = "okay"; +}; + +&uicr { + nfct-pins-as-gpios; + gpio-as-nreset; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uart0 { + compatible = "nordic,nrf-uarte"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&ieee802154 { + status = "okay"; +}; + +/* Include flash partition table. + * Two partition tables are available: + * fstab-stock -compatible with Nordic nRF5 bootloader, default + * fstab-debugger -to use an external debugger, w/o the nRF5 bootloader + */ +#include "fstab-stock.dtsi" + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.yaml b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.yaml new file mode 100644 index 00000000000..90e1c1cde51 --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# Copyright (c) 2025 Raytac Corporation. +# SPDX-License-Identifier: Apache-2.0 + +identifier: raytac_mdbt50q_cx_40_dongle/nrf52840 +name: Raytac MDBT50Q-CX-40 Dongle +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - usb_device + - usb_cdc + - ble + - pwm + - watchdog + - counter + - netif:openthread + - gpio +vendor: raytac diff --git a/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840_defconfig b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840_defconfig new file mode 100644 index 00000000000..d0b5322cfeb --- /dev/null +++ b/boards/raytac/mdbt50q_cx_40_dongle/raytac_mdbt50q_cx_40_dongle_nrf52840_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote +# wakeup by default. It needs to be disabled here, because the USB nrfx +# driver always overwrites option from Kconfig mentioned above with the +# imply from CONFIG_USB_NRFX. +CONFIG_USB_DEVICE_REMOTE_WAKEUP=n diff --git a/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts index c440759815d..76624c34455 100644 --- a/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts +++ b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts @@ -82,7 +82,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts index 025b8e7ec85..2eca5ef89cd 100644 --- a/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts +++ b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts @@ -80,7 +80,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts index 86e5f8f2013..f8a88173661 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts @@ -89,7 +89,6 @@ sw1 = &button1; sw2 = &button2; sw3 = &button3; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts index 468243a71d5..658f3bf515d 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts @@ -68,7 +68,6 @@ sw0 = &button0; sw1 = &button1; sw2 = &button2; - bootloader-led0 = &led0; mcuboot-button0 = &button0; mcuboot-led0 = &led0; watchdog0 = &wdt0; diff --git a/boards/realtek/rts5912_evb/rts5912_evb.dts b/boards/realtek/rts5912_evb/rts5912_evb.dts index 7f1f476b5c0..64b867b8217 100644 --- a/boards/realtek/rts5912_evb/rts5912_evb.dts +++ b/boards/realtek/rts5912_evb/rts5912_evb.dts @@ -16,6 +16,7 @@ chosen { zephyr,sram = &sram0; zephyr,console = &uart0; + zephyr,shell-uart = &uart0; zephyr,flash = &flash0; }; }; diff --git a/boards/realtek/rts5912_evb/rts5912_evb_defconfig b/boards/realtek/rts5912_evb/rts5912_evb_defconfig index a454f6a87a0..64454c374d5 100644 --- a/boards/realtek/rts5912_evb/rts5912_evb_defconfig +++ b/boards/realtek/rts5912_evb/rts5912_evb_defconfig @@ -17,9 +17,3 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Input Driver -CONFIG_INPUT=y - -# Enable ADC -CONFIG_ADC=y diff --git a/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts b/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts index 96c241aa9d1..2a21c4bcc5e 100644 --- a/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts @@ -20,6 +20,7 @@ zephyr,console = &uart; zephyr,shell-uart = &uart; zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_da1469x; }; leds { @@ -214,6 +215,11 @@ zephyr_udc0: &usbd { pinctrl-names = "default", "sleep"; }; +&bt_hci_da1469x { + status = "okay"; +}; + + mikrobus_1_i2c: &i2c {}; mikrobus_1_spi: &spi {}; diff --git a/boards/renesas/da14695_dk_usb/doc/index.rst b/boards/renesas/da14695_dk_usb/doc/index.rst index bb530186668..2ee502fe912 100644 --- a/boards/renesas/da14695_dk_usb/doc/index.rst +++ b/boards/renesas/da14695_dk_usb/doc/index.rst @@ -45,6 +45,23 @@ The pin connections are as follows: * UART RX, connected to J-Link serial = P0.08 * UART TX, connected to J-Link serial = P0.09 +System requirements +******************* + +Prerequisites +============= + +Renesas HAL requires Bluetooth controller binary blobs in order to work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_renesas + +.. note:: + + It is recommended running the command above after :file:`west update`. + Programming and Debugging ************************* diff --git a/boards/renesas/da1469x_dk_pro/doc/index.rst b/boards/renesas/da1469x_dk_pro/doc/index.rst index 3c8b643b5b8..0520b94fa55 100644 --- a/boards/renesas/da1469x_dk_pro/doc/index.rst +++ b/boards/renesas/da1469x_dk_pro/doc/index.rst @@ -47,6 +47,23 @@ The pin connections are as follows: * UART RX, via USB1 on motherboard = P0.08 * UART TX, via USB1 on motherboard = P0.09 +System requirements +******************* + +Prerequisites +============= + +Renesas HAL requires Bluetooth controller binary blobs in order to work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_renesas + +.. note:: + + It is recommended running the command above after :file:`west update`. + Programming and Debugging ************************* diff --git a/boards/renesas/ek_ra2a1/Kconfig.defconfig b/boards/renesas/ek_ra2a1/Kconfig.defconfig new file mode 100644 index 00000000000..842902a62b9 --- /dev/null +++ b/boards/renesas/ek_ra2a1/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if !INPUT_RENESAS_RA_QE_TOUCH_CFG + +config INPUT_RENESAS_RA_CTSU_NUM_SELF_ELEMENTS + default 1 + +endif # INPUT_RENESAS_RA_QE_TOUCH_CFG diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi index 690f5736c75..79fe9745813 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi +++ b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi @@ -51,4 +51,12 @@ renesas,analog-enable; }; }; + + ctsu_default: ctsu_default { + group1 { + /* TS01 TSCAP */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts index 39d5d372cd9..6004c429c1e 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1.dts +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts @@ -83,6 +83,10 @@ status = "okay"; }; +&ioport4 { + status = "okay"; +}; + &port_irq6 { interrupts = <29 3>; status = "okay"; @@ -120,3 +124,40 @@ &wdt { status = "okay"; }; + +&ctsu { + pinctrl-0 = <&ctsu_default>; + pinctrl-names = "default"; + interrupts = <10 3>, <11 3>, <12 3>; + interrupt-names = "ctsuwr", "ctsurd", "ctsufn"; + clock-div = <1>; + pwr-supply-sel = "vcc"; + atune1 = "normal"; + measure-mode = "self-multi-scan"; + tscap-gpios = <&ioport4 9 0>; + status = "okay"; + + group1 { + ctsuchac = <0x00>, <0x80>, <0x00>, <0x00>, <0x00>; + ctsuchtrc = <0x00>, <0x00>, <0x00>, <0x00>, <0x00>; + rx-count = <1>; + tx-count = <0>; + ssdiv = "1.00"; + so = <0x108>; + snum = <0x01>; + sdpa = <0x0B>; + on-freq = <3>; + off-freq = <3>; + drift-freq = <255>; + cancel-freq = <0>; + num-moving-avg = <4>; + + ts1: button1 { + compatible = "renesas,ra-ctsu-button"; + event-code = ; + elements = <0>; + threshold = <2305>; + hysteresis = <115>; + }; + }; +}; diff --git a/boards/renesas/ek_ra2l1/board.cmake b/boards/renesas/ek_ra2l1/board.cmake index e39493b726b..486f34de85c 100644 --- a/boards/renesas/ek_ra2l1/board.cmake +++ b/boards/renesas/ek_ra2l1/board.cmake @@ -6,7 +6,9 @@ board_set_flasher_ifnset(jlink) board_runner_args(jlink "--device=r7fa2l1ab") board_runner_args(pyocd "--target=r7fa2l1ab") +board_runner_args(probe-rs "--chip=r7fa2l1ab") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/probe-rs.board.cmake) diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi b/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi index 851d8543bee..3916d051ea9 100644 --- a/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi +++ b/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * SPDX-License-Identifier: Apache-2.0 */ @@ -11,4 +11,20 @@ ; }; }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + dac0_default: dac0_default { + group1 { + /* output */ + psels = ; + renesas,analog-enable; + }; + }; }; diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.dts b/boards/renesas/ek_ra2l1/ek_ra2l1.dts index 546451d10ac..af8a217ea40 100644 --- a/boards/renesas/ek_ra2l1/ek_ra2l1.dts +++ b/boards/renesas/ek_ra2l1/ek_ra2l1.dts @@ -1,6 +1,6 @@ /** * Copyright (c) 2021-2024 MUNIC SA - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * DTS for Renesas EK-RA2L1 eval. board * @@ -14,6 +14,8 @@ #include #include +#include +#include #include "ek_ra2l1-pinctrl.dtsi" / { @@ -25,6 +27,7 @@ zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,entropy = &trng; }; leds { @@ -36,8 +39,26 @@ }; }; + buttons { + compatible = "gpio-keys"; + + button0: s1 { + gpios = <&ioport0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + + button1: s2 { + gpios = <&ioport0 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; watchdog0 = &wdt; }; }; @@ -46,6 +67,10 @@ status = "okay"; }; +&ioport0 { + status = "okay"; +}; + &sci0 { pinctrl-0 = <&sci0_default>; pinctrl-names = "default"; @@ -60,3 +85,31 @@ &wdt { status = "okay"; }; + +&trng { + status = "okay"; +}; + +&adc0 { + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + interrupts = <8 1>; + interrupt-names = "scanend"; + status = "okay"; +}; + +&dac0 { + pinctrl-0 = <&dac0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&port_irq3 { + interrupts = <11 1>; + status = "okay"; +}; + +&port_irq7 { + interrupts = <15 1>; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4e2/CMakeLists.txt b/boards/renesas/ek_ra4e2/CMakeLists.txt new file mode 100644 index 00000000000..aec8a5c7734 --- /dev/null +++ b/boards/renesas/ek_ra4e2/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/renesas/ek_ra4e2/board.c b/boards/renesas/ek_ra4e2/board.c new file mode 100644 index 00000000000..3f2cf4e54be --- /dev/null +++ b/boards/renesas/ek_ra4e2/board.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(board_control, CONFIG_LOG_DEFAULT_LEVEL); + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c0)) && defined(CONFIG_I3C) +static int i3c_init(void) +{ + const struct gpio_dt_spec i3c_pullup_gpios[2] = { + GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), i3c_pullup_gpios, 0), + GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), i3c_pullup_gpios, 1), + }; + + if (!gpio_is_ready_dt(&i3c_pullup_gpios[0]) || !gpio_is_ready_dt(&i3c_pullup_gpios[1])) { + LOG_ERR("I3C pull-up control is not ready"); + return -ENODEV; + } + + if (gpio_pin_configure_dt(&i3c_pullup_gpios[0], GPIO_INPUT) || + gpio_pin_configure_dt(&i3c_pullup_gpios[1], GPIO_INPUT)) { + LOG_ERR("Failed to configure pull-up control"); + return -EIO; + } + + return 0; +} + +SYS_INIT(i3c_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +#endif diff --git a/boards/renesas/ek_ra4e2/board.cmake b/boards/renesas/ek_ra4e2/board.cmake index 18c2bdf71e9..9184efbd6c6 100644 --- a/boards/renesas/ek_ra4e2/board.cmake +++ b/boards/renesas/ek_ra4e2/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA4E2B9") +board_runner_args(pyocd "--target=R7FA4E2B9") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi index 29ce6c5c302..ea0ce597fd5 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi +++ b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi @@ -22,6 +22,14 @@ }; }; + i3c0_default: i3c0_default { + group1 { + /* SCL SDA */ + psels = , + ; + }; + }; + canfd0_default: canfd0_default { group1 { /* CRX0 CTX0 */ diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index 923c73fabed..6723f22e331 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -68,6 +68,11 @@ max-bitrate = <5000000>; #phy-cells = <0>; }; + + zephyr,user { + i3c-pullup-gpios = <&ioport2 5 GPIO_ACTIVE_LOW>, + <&ioport2 6 GPIO_ACTIVE_LOW>; + }; }; &xtal { @@ -116,6 +121,16 @@ status = "okay"; }; +&i3c0 { + i2c-scl-hz = ; + i3c-scl-hz = ; + pinctrl-0 = <&i3c0_default>; + pinctrl-names = "default"; + interrupts = <51 1>, <52 1>, <53 1>, <54 1>, <55 1>, <56 1>; + interrupt-names = "resp", "rx", "tx", "rcv", "ibi", "eei"; + status = "okay"; +}; + &ioport4 { status = "okay"; }; @@ -126,6 +141,12 @@ status = "okay"; }; +&i3cclk { + clocks = <&pll>; + div = <2>; + status = "okay"; +}; + &canfd_global { status = "okay"; canfd0 { diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml index 6e1f8a12710..b8f7c201c57 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml @@ -12,4 +12,5 @@ supported: - uart - watchdog - counter + - i3c vendor: renesas diff --git a/boards/renesas/ek_ra4l1/CMakeLists.txt b/boards/renesas/ek_ra4l1/CMakeLists.txt new file mode 100644 index 00000000000..aec8a5c7734 --- /dev/null +++ b/boards/renesas/ek_ra4l1/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/renesas/ek_ra4l1/board.c b/boards/renesas/ek_ra4l1/board.c new file mode 100644 index 00000000000..3f2cf4e54be --- /dev/null +++ b/boards/renesas/ek_ra4l1/board.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(board_control, CONFIG_LOG_DEFAULT_LEVEL); + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c0)) && defined(CONFIG_I3C) +static int i3c_init(void) +{ + const struct gpio_dt_spec i3c_pullup_gpios[2] = { + GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), i3c_pullup_gpios, 0), + GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), i3c_pullup_gpios, 1), + }; + + if (!gpio_is_ready_dt(&i3c_pullup_gpios[0]) || !gpio_is_ready_dt(&i3c_pullup_gpios[1])) { + LOG_ERR("I3C pull-up control is not ready"); + return -ENODEV; + } + + if (gpio_pin_configure_dt(&i3c_pullup_gpios[0], GPIO_INPUT) || + gpio_pin_configure_dt(&i3c_pullup_gpios[1], GPIO_INPUT)) { + LOG_ERR("Failed to configure pull-up control"); + return -EIO; + } + + return 0; +} + +SYS_INIT(i3c_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +#endif diff --git a/boards/renesas/ek_ra4l1/board.cmake b/boards/renesas/ek_ra4l1/board.cmake index ede2ff300bb..93c30c30612 100644 --- a/boards/renesas/ek_ra4l1/board.cmake +++ b/boards/renesas/ek_ra4l1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA4L1BD") +board_runner_args(pyocd "--target=R7FA4L1BD") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi b/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi index 23b0ff8bd65..3b85c0a0c75 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi +++ b/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi @@ -22,6 +22,14 @@ }; }; + i3c0_default: i3c0_default { + group1 { + /* SCL SDA */ + psels = , + ; + }; + }; + adc0_default: adc0_default { group1 { /* input */ diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.dts b/boards/renesas/ek_ra4l1/ek_ra4l1.dts index ec2fca6b8f4..3f7e15acd91 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.dts +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.dts @@ -72,6 +72,11 @@ max-bitrate = <5000000>; #phy-cells = <0>; }; + + zephyr,user { + i3c-pullup-gpios = <&ioport5 8 GPIO_ACTIVE_LOW>, + <&ioport5 9 GPIO_ACTIVE_LOW>; + }; }; &xtal { @@ -98,6 +103,12 @@ status = "okay"; }; +&i3cclk { + clocks = <&pll>; + div = <1>; + status = "okay"; +}; + &sci5 { pinctrl-0 = <&sci5_default>; pinctrl-names = "default"; @@ -135,6 +146,16 @@ status = "okay"; }; +&i3c0 { + i2c-scl-hz = ; + i3c-scl-hz = ; + pinctrl-0 = <&i3c0_default>; + pinctrl-names = "default"; + interrupts = <32 1>, <33 1>, <34 1>, <35 1>, <36 1>, <37 1>; + interrupt-names = "resp", "rx", "tx", "rcv", "ibi", "eei"; + status = "okay"; +}; + &adc0 { status = "okay"; pinctrl-0 = <&adc0_default>; diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.yaml b/boards/renesas/ek_ra4l1/ek_ra4l1.yaml index 77368c10346..c31f23d4869 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.yaml +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.yaml @@ -12,4 +12,6 @@ supported: - uart - watchdog - counter + - i2s + - i3c vendor: renesas diff --git a/boards/renesas/ek_ra4m1/board.cmake b/boards/renesas/ek_ra4m1/board.cmake index 8711194800b..4d4b0c7d85d 100644 --- a/boards/renesas/ek_ra4m1/board.cmake +++ b/boards/renesas/ek_ra4m1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA4M1AB") +board_runner_args(pyocd "--target=R7FA4M1AB") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra4m2/board.cmake b/boards/renesas/ek_ra4m2/board.cmake index f0faf6c179a..69f6b4f69f5 100644 --- a/boards/renesas/ek_ra4m2/board.cmake +++ b/boards/renesas/ek_ra4m2/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA4M2AD") +board_runner_args(pyocd "--target=R7FA4M2AD") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra4m3/board.cmake b/boards/renesas/ek_ra4m3/board.cmake index 98f1f87f5b7..2b2c89ee866 100644 --- a/boards/renesas/ek_ra4m3/board.cmake +++ b/boards/renesas/ek_ra4m3/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA4M3AF") +board_runner_args(pyocd "--target=R7FA4M3AF") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra4w1/board.cmake b/boards/renesas/ek_ra4w1/board.cmake index 6a1b1617cb8..09515156e90 100644 --- a/boards/renesas/ek_ra4w1/board.cmake +++ b/boards/renesas/ek_ra4w1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA4W1AD") +board_runner_args(pyocd "--target=R7FA4W1AD") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra6e2/board.cmake b/boards/renesas/ek_ra6e2/board.cmake index 368e10209f9..1d0dd4380c3 100644 --- a/boards/renesas/ek_ra6e2/board.cmake +++ b/boards/renesas/ek_ra6e2/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA6E2BB") +board_runner_args(pyocd "--target=R7FA6E2BB") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra6m1/board.cmake b/boards/renesas/ek_ra6m1/board.cmake index 1a34ff99958..dfd361e8128 100644 --- a/boards/renesas/ek_ra6m1/board.cmake +++ b/boards/renesas/ek_ra6m1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA6M1AD") +board_runner_args(pyocd "--target=R7FA6M1AD") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra6m2/board.cmake b/boards/renesas/ek_ra6m2/board.cmake index 4ebea5664ca..21488a73528 100644 --- a/boards/renesas/ek_ra6m2/board.cmake +++ b/boards/renesas/ek_ra6m2/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA6M2AF") +board_runner_args(pyocd "--target=R7FA6M2AF") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra6m3/board.cmake b/boards/renesas/ek_ra6m3/board.cmake index a395cf75494..84360ad46cc 100644 --- a/boards/renesas/ek_ra6m3/board.cmake +++ b/boards/renesas/ek_ra6m3/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA6M3AH") +board_runner_args(pyocd "--target=R7FA6M3AH") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra6m4/board.cmake b/boards/renesas/ek_ra6m4/board.cmake index 66f79828a34..e6b80a0fddd 100644 --- a/boards/renesas/ek_ra6m4/board.cmake +++ b/boards/renesas/ek_ra6m4/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA6M4AF") +board_runner_args(pyocd "--target=R7FA6M4AF") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index e8ab9b35966..c6ed4cbcff0 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include "ek_ra6m4-pinctrl.dtsi" @@ -64,6 +65,35 @@ /* GND */ }; + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + buttons { compatible = "gpio-keys"; button0: s1 { @@ -135,6 +165,10 @@ status = "okay"; }; +&ioport3 { + status = "okay"; +}; + &ioport4 { status = "okay"; }; @@ -147,6 +181,10 @@ status = "okay"; }; +&ioport7 { + status = "okay"; +}; + &xtal { clock-frequency = ; mosel = <0>; @@ -245,6 +283,10 @@ mikrobus_serial: &uart7 {}; mikrobus_i2c: &iic1 {}; mikrobus_spi: &spi0 {}; +arduino_serial: &uart7 {}; +arduino_i2c: &iic1 {}; +arduino_spi: &spi0 {}; + &wdt { status = "okay"; }; diff --git a/boards/renesas/ek_ra6m5/board.cmake b/boards/renesas/ek_ra6m5/board.cmake index 5aabef8bb75..aecd6957c40 100644 --- a/boards/renesas/ek_ra6m5/board.cmake +++ b/boards/renesas/ek_ra6m5/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA6M5BH") +board_runner_args(pyocd "--target=R7FA6M5BH") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra8d1/CMakeLists.txt b/boards/renesas/ek_ra8d1/CMakeLists.txt index 86d1cedc6f4..f52c37df739 100644 --- a/boards/renesas/ek_ra8d1/CMakeLists.txt +++ b/boards/renesas/ek_ra8d1/CMakeLists.txt @@ -3,5 +3,8 @@ zephyr_include_directories(.) +zephyr_library() +zephyr_library_sources(board.c) + zephyr_linker_sources_ifdef(CONFIG_MEMC SECTIONS sdram.ld) diff --git a/boards/renesas/ek_ra8d1/board.c b/boards/renesas/ek_ra8d1/board.c new file mode 100644 index 00000000000..3f2cf4e54be --- /dev/null +++ b/boards/renesas/ek_ra8d1/board.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(board_control, CONFIG_LOG_DEFAULT_LEVEL); + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c0)) && defined(CONFIG_I3C) +static int i3c_init(void) +{ + const struct gpio_dt_spec i3c_pullup_gpios[2] = { + GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), i3c_pullup_gpios, 0), + GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), i3c_pullup_gpios, 1), + }; + + if (!gpio_is_ready_dt(&i3c_pullup_gpios[0]) || !gpio_is_ready_dt(&i3c_pullup_gpios[1])) { + LOG_ERR("I3C pull-up control is not ready"); + return -ENODEV; + } + + if (gpio_pin_configure_dt(&i3c_pullup_gpios[0], GPIO_INPUT) || + gpio_pin_configure_dt(&i3c_pullup_gpios[1], GPIO_INPUT)) { + LOG_ERR("Failed to configure pull-up control"); + return -EIO; + } + + return 0; +} + +SYS_INIT(i3c_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +#endif diff --git a/boards/renesas/ek_ra8d1/board.cmake b/boards/renesas/ek_ra8d1/board.cmake index ee93597a92c..473e68838fc 100644 --- a/boards/renesas/ek_ra8d1/board.cmake +++ b/boards/renesas/ek_ra8d1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA8D1BH") +board_runner_args(pyocd "--target=R7FA8D1BH") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra8d1/doc/index.rst b/boards/renesas/ek_ra8d1/doc/index.rst index 027f08a261d..b92b707f810 100644 --- a/boards/renesas/ek_ra8d1/doc/index.rst +++ b/boards/renesas/ek_ra8d1/doc/index.rst @@ -102,8 +102,7 @@ Supported Features | OFF | OFF | OFF | OFF | OFF | ON | ON | OFF | +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ - - For using the Parallel Graphics Expansion Port (J57) with the Graphics Expansion Board supplied as part of the kit, - please set switch SW1 as following configuration: + - For using the Parallel Graphics Expansion Port (J57), please set switch SW1 to the following configuration: +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ | SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C | @@ -111,6 +110,14 @@ Supported Features | OFF | OFF | OFF | OFF | OFF | ON | ON | OFF | +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + - For using I3C on RA8D1 board please set switch SW1 as following configuration: + + +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + | SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C | + +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + | OFF | OFF | OFF | OFF | OFF | OFF | OFF | ON | + +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + .. warning:: Do not enable SW1-4 and SW1-5 together diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi index ba342a63572..a1bef58722e 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi +++ b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi @@ -25,6 +25,18 @@ }; }; + sci3_default: sci3_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; + }; + }; + spi1_default: spi1_default { group1 { /* MISO MOSI RSPCK SSL */ @@ -35,6 +47,14 @@ }; }; + i3c0_default: i3c0_default { + group1 { + /* SCL SDA */ + psels = , + ; + }; + }; + pwm7_default: pwm7_default { group1 { /* GTIOC7A */ @@ -270,4 +290,23 @@ psels = ; }; }; + + ospi0_default: ospi0_default { + group1 { + /* sclk dqs sio0-7 */ + psels = , , + , , + , , + , , + , ; + drive-strength = "highspeed-high"; + }; + + group2 { + /* cs1 rst ecsint1 */ + psels = , , + ; + drive-strength = "high"; + }; + }; }; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index 9fb7fec4dd1..fe0c703a1e8 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include #include @@ -43,6 +44,29 @@ }; }; + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport0 4 0>, /* AN */ + <1 0 &ioport5 7 0>, /* RST */ + <2 0 &ioport4 13 0>, /* CS */ + <3 0 &ioport4 12 0>, /* SCK */ + <4 0 &ioport4 10 0>, /* MISO */ + <5 0 &ioport4 11 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &ioport9 7 0>, /* PWM */ + <7 0 &ioport0 10 0>, /* INT */ + <8 0 &ioport4 8 0>, /* RX */ + <9 0 &ioport4 9 0>, /* TX */ + <10 0 &ioport4 0 0>, /* SCL */ + <11 0 &ioport4 1 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + buttons { compatible = "gpio-keys"; button0: s1 { @@ -77,6 +101,18 @@ <18 0 &ioporta 1 0>; /* DISP_RST */ }; + ek_ra8d1_parallel_graphics_expansion: parallel-graphics-expansion { + compatible = "renesas,ra-parallel-graphics-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <1 0 &ioport4 4 0>, /* DISP_BLEN */ + <2 0 &ioport5 11 0>, /* IIC_SDA */ + <3 0 &ioport5 10 0>, /* DISP_INT */ + <4 0 &ioport5 12 0>, /* IIC_SCL */ + <6 0 &ioporta 1 0>; /* DISP_RST */ + }; + aliases { led0 = &led1; sw0 = &button0; @@ -84,6 +120,11 @@ mipi-dsi = &mipi_dsi; watchdog0 = &wdt; }; + + zephyr,user { + i3c-pullup-gpios = <&ioportb 2 GPIO_ACTIVE_LOW>, + <&ioport7 11 GPIO_ACTIVE_LOW>; + }; }; &xtal { @@ -114,6 +155,19 @@ }; }; +&pll2 { + status = "okay"; + clocks = <&xtal>; + div = <2>; + mul = <80 0>; + + pll2p { + status = "okay"; + freq = ; + div = <2>; + }; +}; + &sciclk { clocks = <&pllp>; div = <4>; @@ -132,12 +186,24 @@ status = "okay"; }; +&octaspiclk { + clocks = <&pll2p>; + div = <2>; + status = "okay"; +}; + &uclk { clocks = <&pllq>; div = <5>; status = "okay"; }; +&i3cclk { + clocks = <&pllp>; + div = <3>; + status = "okay"; +}; + &ioport0 { status = "okay"; }; @@ -158,10 +224,22 @@ status = "okay"; }; +&ioport7 { + status = "okay"; +}; + +&ioport9 { + status = "okay"; +}; + &ioporta { status = "okay"; }; +&ioportb { + status = "okay"; +}; + &sci9 { pinctrl-0 = <&sci9_default>; pinctrl-names = "default"; @@ -183,6 +261,17 @@ }; }; +&sci3 { + pinctrl-0 = <&sci3_default>; + pinctrl-names = "default"; + status = "okay"; + + uart3: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + &trng { status = "okay"; }; @@ -193,6 +282,16 @@ status = "okay"; }; +&i3c0 { + i2c-scl-hz = ; + i3c-scl-hz = ; + pinctrl-0 = <&i3c0_default>; + pinctrl-names = "default"; + interrupts = <60 1>, <61 1>, <62 1>, <63 1>, <64 1>, <65 1>; + interrupt-names = "resp", "rx", "tx", "rcv", "ibi", "eei"; + status = "okay"; +}; + &flash1 { partitions { compatible = "fixed-partitions"; @@ -342,3 +441,51 @@ pmod_sd_shield: &sdhc1 {}; status = "okay"; }; }; + +&ospi0 { + pinctrl-0 = <&ospi0_default>; + pinctrl-names = "default"; + status = "okay"; + + s28hl512t: ospi-nor-flash@90000000 { + compatible = "renesas,ra-ospi-b-nor"; + protocol-mode = ; + data-rate = ; + ospi-max-frequency = ; + reg = <0x90000000 DT_SIZE_M(64)>; + write-block-size = <1>; + status = "okay"; + + pages_layout: pages_layout { + + pages_layout_4k: pages_layout_4k { + pages-count = <32>; + pages-size = ; + }; + + pages_layout_128k: pages_layout_128k { + pages-count = <1>; + pages-size = ; + }; + + pages_layout_256k: pages_layout_256k { + pages-count = <255>; + pages-size = ; + }; + }; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "nor"; + reg = <0x00000000 DT_SIZE_M(64)>; + }; + }; + }; +}; + +mikrobus_serial: &uart3 {}; +mikrobus_spi: &spi1 {}; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml index c4348dcc7f5..11d214225c7 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml @@ -14,4 +14,6 @@ supported: - usbd - display - counter + - i2s + - i3c vendor: renesas diff --git a/boards/renesas/ek_ra8m1/CMakeLists.txt b/boards/renesas/ek_ra8m1/CMakeLists.txt new file mode 100644 index 00000000000..aec8a5c7734 --- /dev/null +++ b/boards/renesas/ek_ra8m1/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/renesas/ek_ra8m1/board.c b/boards/renesas/ek_ra8m1/board.c new file mode 100644 index 00000000000..3f2cf4e54be --- /dev/null +++ b/boards/renesas/ek_ra8m1/board.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(board_control, CONFIG_LOG_DEFAULT_LEVEL); + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c0)) && defined(CONFIG_I3C) +static int i3c_init(void) +{ + const struct gpio_dt_spec i3c_pullup_gpios[2] = { + GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), i3c_pullup_gpios, 0), + GPIO_DT_SPEC_GET_BY_IDX(DT_PATH(zephyr_user), i3c_pullup_gpios, 1), + }; + + if (!gpio_is_ready_dt(&i3c_pullup_gpios[0]) || !gpio_is_ready_dt(&i3c_pullup_gpios[1])) { + LOG_ERR("I3C pull-up control is not ready"); + return -ENODEV; + } + + if (gpio_pin_configure_dt(&i3c_pullup_gpios[0], GPIO_INPUT) || + gpio_pin_configure_dt(&i3c_pullup_gpios[1], GPIO_INPUT)) { + LOG_ERR("Failed to configure pull-up control"); + return -EIO; + } + + return 0; +} + +SYS_INIT(i3c_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +#endif diff --git a/boards/renesas/ek_ra8m1/board.cmake b/boards/renesas/ek_ra8m1/board.cmake index 839e642d478..3badfe83b59 100644 --- a/boards/renesas/ek_ra8m1/board.cmake +++ b/boards/renesas/ek_ra8m1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA8M1AH") +board_runner_args(pyocd "--target=R7FA8M1AH") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra8m1/doc/index.rst b/boards/renesas/ek_ra8m1/doc/index.rst index c5553bc608f..4c1ca73df49 100644 --- a/boards/renesas/ek_ra8m1/doc/index.rst +++ b/boards/renesas/ek_ra8m1/doc/index.rst @@ -80,6 +80,7 @@ Supported Features - For using Ethernet module on EK-RA8M1, remove jumper J61 to enable Ethernet B - For using SDHC driver on EK-RA8M1, remove jumper J61 to use with channel 0 + - For using I3C driver on EK-RA8M1, install jumper J61 to use with channel 0 Programming and Debugging ************************* diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi index e8a26e09905..69b981b4896 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi +++ b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi @@ -95,6 +95,14 @@ }; }; + i3c0_default: i3c0_default { + group1 { + /* SCL SDA */ + psels = , + ; + }; + }; + pwm7_default: pwm7_default { group1 { /* GTIOC7A */ @@ -212,4 +220,23 @@ psels = ; }; }; + + ospi0_default: ospi0_default { + group1 { + /* sclk dqs sio0-7 */ + psels = , , + , , + , , + , , + , ; + drive-strength = "highspeed-high"; + }; + + group2 { + /* cs1 rst ecsint1 */ + psels = , , + ; + drive-strength = "high"; + }; + }; }; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index e1c08487718..da52851eff2 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -7,6 +7,7 @@ #include #include +#include #include #include #include "ek_ra8m1-pinctrl.dtsi" @@ -121,6 +122,11 @@ max-bitrate = <5000000>; #phy-cells = <0>; }; + + zephyr,user { + i3c-pullup-gpios = <&ioportb 0 GPIO_ACTIVE_LOW>, + <&ioport7 11 GPIO_ACTIVE_LOW>; + }; }; &xtal { @@ -151,6 +157,18 @@ }; }; +&pll2 { + status = "okay"; + clocks = <&xtal>; + div = <2>; + mul = <80 0>; + + pll2p { + status = "okay"; + freq = ; + div = <2>; + }; +}; &sciclk { clocks = <&pllp>; @@ -170,6 +188,18 @@ status = "okay"; }; +&octaspiclk { + clocks = <&pll2p>; + div = <2>; + status = "okay"; +}; + +&i3cclk { + clocks = <&pllp>; + div = <3>; + status = "okay"; +}; + &ioport0 { status = "okay"; }; @@ -198,6 +228,10 @@ status = "okay"; }; +&ioport7 { + status = "okay"; +}; + &ioport8 { status = "okay"; }; @@ -210,6 +244,10 @@ status = "okay"; }; +&ioportb { + status = "okay"; +}; + &sci0 { pinctrl-0 = <&sci0_default>; pinctrl-names = "default"; @@ -262,6 +300,7 @@ }; mikrobus_serial: &uart3 {}; +mikrobus_spi: &spi1 {}; &iic1 { #address-cells = <1>; @@ -294,6 +333,16 @@ mikrobus_serial: &uart3 {}; status = "okay"; }; +&i3c0 { + i2c-scl-hz = ; + i3c-scl-hz = ; + pinctrl-0 = <&i3c0_default>; + pinctrl-names = "default"; + interrupts = <60 1>, <61 1>, <62 1>, <63 1>, <64 1>, <65 1>; + interrupt-names = "resp", "rx", "tx", "rcv", "ibi", "eei"; + status = "okay"; +}; + &pwm7 { pinctrl-0 = <&pwm7_default>; interrupts = <40 1>, <41 1>; @@ -401,3 +450,48 @@ pmod_sd_shield: &sdhc0 {}; status = "okay"; }; }; + +&ospi0 { + pinctrl-0 = <&ospi0_default>; + pinctrl-names = "default"; + status = "okay"; + + s28hl512t: ospi-nor-flash@90000000 { + compatible = "renesas,ra-ospi-b-nor"; + protocol-mode = ; + data-rate = ; + ospi-max-frequency = ; + reg = <0x90000000 DT_SIZE_M(64)>; + write-block-size = <1>; + status = "okay"; + + pages_layout: pages_layout { + + pages_layout_4k: pages_layout_4k { + pages-count = <32>; + pages-size = ; + }; + + pages_layout_128k: pages_layout_128k { + pages-count = <1>; + pages-size = ; + }; + + pages_layout_256k: pages_layout_256k { + pages-count = <255>; + pages-size = ; + }; + }; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "nor"; + reg = <0x00000000 DT_SIZE_M(64)>; + }; + }; + }; +}; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml index 6c6a7e1976f..1dffeb2effb 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml @@ -13,4 +13,6 @@ supported: - watchdog - usbd - counter + - i2s + - i3c vendor: renesas diff --git a/boards/renesas/ek_ra8p1/CMakeLists.txt b/boards/renesas/ek_ra8p1/CMakeLists.txt new file mode 100644 index 00000000000..6e7e11bab96 --- /dev/null +++ b/boards/renesas/ek_ra8p1/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_linker_sources_ifdef(CONFIG_MEMC + SECTIONS sdram.ld) diff --git a/boards/renesas/ek_ra8p1/Kconfig.defconfig b/boards/renesas/ek_ra8p1/Kconfig.defconfig new file mode 100644 index 00000000000..6b28a167475 --- /dev/null +++ b/boards/renesas/ek_ra8p1/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EK_RA8P1 + +if DISK_DRIVER_SDMMC + +config SD_CMD_TIMEOUT + default 1000 + +endif # DISK_DRIVER_SDMMC + +endif # BOARD_EK_RA8P1 diff --git a/boards/renesas/ek_ra8p1/Kconfig.ek_ra8p1 b/boards/renesas/ek_ra8p1/Kconfig.ek_ra8p1 new file mode 100644 index 00000000000..5446de2c56e --- /dev/null +++ b/boards/renesas/ek_ra8p1/Kconfig.ek_ra8p1 @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RA8P1 + select SOC_R7KA8P1KFLCAC_CM85 if BOARD_EK_RA8P1_R7KA8P1KFLCAC_CM85 + select SOC_R7KA8P1KFLCAC_CM33 if BOARD_EK_RA8P1_R7KA8P1KFLCAC_CM33 diff --git a/boards/renesas/ek_ra8p1/board.cmake b/boards/renesas/ek_ra8p1/board.cmake new file mode 100644 index 00000000000..596be747fa5 --- /dev/null +++ b/boards/renesas/ek_ra8p1/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_R7KA8P1KFLCAC_CM85) + board_runner_args(jlink "--device=R7KA8P1KF_CPU0" "--reset-after-load") + board_runner_args(pyocd "--target=R7KA8P1KF_CPU0") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/ek_ra8p1/board.yml b/boards/renesas/ek_ra8p1/board.yml new file mode 100644 index 00000000000..355514fe072 --- /dev/null +++ b/boards/renesas/ek_ra8p1/board.yml @@ -0,0 +1,6 @@ +board: + name: ek_ra8p1 + full_name: RA8P1 Evaluation Kit + vendor: renesas + socs: + - name: r7ka8p1kflcac diff --git a/boards/renesas/ek_ra8p1/doc/ek_ra8p1.webp b/boards/renesas/ek_ra8p1/doc/ek_ra8p1.webp new file mode 100644 index 00000000000..3380250b5c6 Binary files /dev/null and b/boards/renesas/ek_ra8p1/doc/ek_ra8p1.webp differ diff --git a/boards/renesas/ek_ra8p1/doc/index.rst b/boards/renesas/ek_ra8p1/doc/index.rst new file mode 100644 index 00000000000..0a155f0e85f --- /dev/null +++ b/boards/renesas/ek_ra8p1/doc/index.rst @@ -0,0 +1,148 @@ +.. zephyr:board:: ek_ra8p1 + +Overview +******** + +The EK-RA8P1 is an Evaluation Kit for Renesas RA8P1 MCU Group which integrates multiple series of software-compatible +Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient +platform-based product development. + +The MCU in this series incorporates a high-performance Arm® Cortex®-M85 core running up to 1 GHz and Arm® +Cortex®-M33 core running up to 250 MHz with the following features: + +- Up to 1 MB MRAM +- 2 MB SRAM (256 KB of CM85 TCM RAM, 128 KB CM33 TCM RAM, 1664 KB of user SRAM) +- Arm® Ethos™-U55 NPU +- Octal Serial Peripheral Interface (OSPI) +- Layer 3 Ethernet Switch Module (ESWM), USBFS, USBHS, SD/MMC Host Interface +- Graphics LCD Controller (GLCDC) +- 2D Drawing Engine (DRW) +- MIPI DSI/CSI interface +- Analog peripherals +- Security and safety features + +**MCU Native Pin Access** + +- 1 GHz Arm Cortex-M85 and 250 MHz Arm Cortex-M33 based RA8P1 MCU in 289 pins, BGA package +- Native pin access through 2 x 20-pin, and 2 x 40-pin headers (no populated) +- Camera Expansion connector (present on the underside of the EK-RA8P1 board) +- 2-Lane MIPI Display connector (present on the underside of the EK-RA8P1 board) +- Parallel graphics display interface connector +- MCU current measurement points for precision current consumption measurement +- Multiple clock sources - RA8P1 MCU oscillator and sub-clock oscillator crystals, + providing precision 24.000 MHz and 32,768 Hz reference clocks. + Additional low precision clocks are available internal to the RA8P1 MCU + +**System Control and Ecosystem Access** + +- USB Full Speed Host and Device (USB-C connector) +- Four 5V input sources + + - USB (Debug, Full Speed, High Speed) + - External power supply (using surface mount clamp test points and power input vias) + +- Three Debug modes + + - Debug on-board (SWD and JTAG) + - Debug in (ETM, SWD, SWO and JTAG) + - Debug out (SWD, SWO, and JTAG) + +- User LEDs and buttons + + - Three User LEDs (red, blue, green) + - Power LED (white) indicating availability of regulated power + - Debug LED (yellow) indicating the debug connection + - Ethernet LEDs (amber, yellow, green) + - Two User buttons + - One Reset button + +- Five most popular ecosystems expansions + + - Two Seeed Grove system (I2C/I3C/Analog) connectors (not populated) + - One SparkFun Qwiic connector (not populated) + - Two Digilent Pmod (SPI, UART and I2C) connectors + - Arduino (Uno R3) connector + - MikroElektronika mikroBUS connector (not populated) + +- MCU boot configuration jumper + +**Special Feature Access** + +- Ethernet (RJ45 RGMII interface) +- USB High Speed Host and Device (USB-C connector) +- 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8P1 board) + +Hardware +******** + +Detailed hardware features can be found at: + +- RA8P1 MCU: `RA8P1 Group User's Manual Hardware`_ +- EK-RA8P1 board: `EK-RA8P1 - User's Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +.. note:: + + - Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +Applications for the ``ek_ra8p1`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Here is an example for the :zephyr:code-sample:`hello_world` application on CM85 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ek_ra8p1/r7ka8p1kflcac/cm85 + :goals: flash + +Open a serial terminal, reset the board (press the S3 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v4.2.0-xxx-xxxxxxxxxxxxx ***** + Hello World! ek_ra8p1/r7ka8p1kflcac/cm85 + +Flashing +======== + +Program can be flashed to EK-RA8P1 via the on-board SEGGER J-Link debugger. +SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/ + +To flash the program to board + +1. Connect to J-Link OB via USB port to host PC + +2. Make sure J-Link OB jumper is in default configuration as described in `EK-RA8P1 - User's Manual`_ + +3. Execute west command + + .. code-block:: console + + west flash -r jlink + +References +********** +- `EK-RA8P1 Website`_ +- `RA8P1 MCU group Website`_ + +.. _EK-RA8P1 Website: + https://www.renesas.com/en/design-resources/boards-kits/ek-ra8p1 + +.. _RA8P1 MCU group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8p1-1ghz-arm-cortex-m85-and-ethos-u55-npu-based-ai-microcontroller + +.. _EK-RA8P1 - User's Manual: + https://www.renesas.com/en/document/mat/ek-ra8p1-v1-users-manual + +.. _RA8P1 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/ra8p1-group-users-manual-hardware diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi b/boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi new file mode 100644 index 00000000000..a19b0152fba --- /dev/null +++ b/boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci8_default: sci8_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + + group2 { + /* rx */ + psels = ; + }; + }; + + sci1_default: sci1_default { + group1 { + /* SDA SCL */ + psels = , + ; + drive-strength = "medium"; + drive-open-drain; + }; + }; + + spi1_default: spi1_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A */ + psels = ; + }; + + group2 { + /* GTIOC1B */ + psels = ; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1*/ + psels = , + ; + drive-strength = "medium"; + }; + }; + + canfd0_default: canfd0_default { + group1 { + /* CRX0 CTX0 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + sdram_default: sdram_default { + group1 { + /* SDRAM_DQM1 */ + psels = , + /* SDRAM_CKE */ + , + /* SDRAM_WE */ + , + /* SDRAM_CS */ + , + /* SDRAM_A0 */ + , + /* SDRAM_A1 */ + , + /* SDRAM_A2 */ + , + /* SDRAM_A3 */ + , + /* SDRAM_A4 */ + , + /* SDRAM_A5 */ + , + /* SDRAM_A6 */ + , + /* SDRAM_A7 */ + , + /* SDRAM_A8 */ + , + /* SDRAM_A9 */ + , + /* SDRAM_A10 */ + , + /* SDRAM_A11 */ + , + /* SDRAM_A12 */ + , + /* SDRAM_D0 */ + , + /* SDRAM_D1 */ + , + /* SDRAM_D2 */ + , + /* SDRAM_D3 */ + , + /* SDRAM_D4 */ + , + /* SDRAM_D5 */ + , + /* SDRAM_D6 */ + , + /* SDRAM_D8 */ + , + /* SDRAM_D9 */ + , + /* SDRAM_D10 */ + , + /* SDRAM_D11 */ + , + /* SDRAM_D12 */ + , + /* SDRAM_D13 */ + , + /* SDRAM_D14 */ + , + /* SDRAM_BA0 */ + , + /* SDRAM_BA1 */ + , + /* SDRAM_RAS */ + , + /* SDRAM_CAS */ + ; + }; + + group2 { + /* SDRAM_SDCLK */ + psels = ; + drive-strength = "highspeed-high"; + }; + + group3 { + /* SDRAM_D7 */ + psels = , + /* SDRAM_D15 */ + , + /* SDRAM_DQM0 */ + ; + }; + }; +}; diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.dts b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.dts new file mode 100644 index 00000000000..2313a057587 --- /dev/null +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.dts @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "ek_ra8p1-pinctrl.dtsi" + +/ { + model = "Renesas EK-RA8P1"; + compatible = "renesas,ra8p1", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + status = "okay"; + + pllp: pllp { + status = "okay"; + }; + + pllq: pllq { + status = "okay"; + }; + + pllr: pllr { + status = "okay"; + }; +}; diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.yaml b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.yaml new file mode 100644 index 00000000000..fb9618948d6 --- /dev/null +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm33.yaml @@ -0,0 +1,10 @@ +identifier: ek_ra8p1/r7ka8p1kflcac/cm33 +name: Renesas EK-RA8P1 +type: mcu +arch: arm +ram: 1664 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +vendor: renesas diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts new file mode 100644 index 00000000000..d25cf464f69 --- /dev/null +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "ek_ra8p1-pinctrl.dtsi" +#include +#include + +/ { + model = "Renesas EK-RA8P1"; + compatible = "renesas,ra8p1", "renesas,ra8"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart8; + zephyr,shell-uart = &uart8; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioport3 3 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioporta 7 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: s1 { + gpios = <&ioport0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + + button1: s2 { + gpios = <&ioport0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + + sdram1: sdram@68000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x68000000 DT_SIZE_M(64)>; /* 512 Mbits */ + zephyr,memory-region = "SDRAM"; + status = "okay"; + }; + + aliases { + led0 = &led1; + sw0 = &button0; + sw1 = &button1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + status = "okay"; + + pllp: pllp { + status = "okay"; + }; + + pllq: pllq { + status = "okay"; + }; + + pllr: pllr { + status = "okay"; + }; +}; + +&pll2 { + status = "okay"; + clocks = <&xtal>; + div = <3>; + mul = <120 0>; + + pll2p { + div = <2>; + freq = ; + status = "okay"; + }; + + pll2q { + div = <3>; + freq = ; + status = "okay"; + }; + + pll2r { + div = <5>; + freq = ; + status = "okay"; + }; +}; + +&sciclk { + clocks = <&pllp>; + div = <10>; + status = "okay"; +}; + +&lcdclk { + clocks = <&pll2p>; + div = <2>; + status = "okay"; +}; + +&uclk { + clocks = <&pll2p>; + div = <10>; + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&ioport5 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&ioport7 { + status = "okay"; +}; + +&ioport8 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&sci8 { + pinctrl-0 = <&sci8_default>; + pinctrl-names = "default"; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart8: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&sci1 { + pinctrl-0 = <&sci1_default>; + pinctrl-names = "default"; + interrupts = <4 1>, <5 1>, <6 1>, <7 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + + i2c1: i2c { + sda-output-delay = <300>; + noise-filter-clock-select = <1>; + bit-rate-modulation; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + interrupts = <8 1>, <9 1>, <10 1>, <11 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + interrupts = <12 1>, <13 1>; + interrupt-names = "gtioca", "overflow"; + pinctrl-names = "default"; + status = "okay"; +}; + +&iic1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; + interrupts = <14 1>, <15 1>, <16 1>, <17 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&port_irq12 { + interrupts = <18 12>; + status = "okay"; +}; + +&port_irq13 { + interrupts = <19 12>; + status = "okay"; +}; + +&ulpt0 { + interrupts = <20 1>; + interrupt-names = "ulpti"; + status = "okay"; + + timer { + status = "okay"; + }; +}; + +&ulpt1 { + status = "okay"; + + timer { + status = "okay"; + }; +}; + +zephyr_lcdif: &lcdif {}; + +&sdram { + pinctrl-0 = <&sdram_default>; + pinctrl-names = "default"; + status = "okay"; + auto-refresh-interval = ; + auto-refresh-count = ; + precharge-cycle-count = ; + multiplex-addr-shift = "10-bit"; + edian-mode = "little-endian"; + continuous-access; + bus-width = "32-bit"; + + bank@0 { + reg = <0>; + renesas,ra-sdram-timing = ; + }; +}; + +pmod_sd_shield: &sdhc0 {}; diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.yaml b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.yaml new file mode 100644 index 00000000000..b4fc6f65184 --- /dev/null +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.yaml @@ -0,0 +1,13 @@ +identifier: ek_ra8p1/r7ka8p1kflcac/cm85 +name: Renesas EK-RA8P1 +type: mcu +arch: arm +ram: 1664 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart +vendor: renesas diff --git a/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85_defconfig b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85_defconfig new file mode 100644 index 00000000000..2f9e7c58490 --- /dev/null +++ b/boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/ek_ra8p1/sdram.ld b/boards/renesas/ek_ra8p1/sdram.ld new file mode 100644 index 00000000000..44d2efd360c --- /dev/null +++ b/boards/renesas/ek_ra8p1/sdram.ld @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) + +SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),) +{ + __SDRAM_Start = .; + KEEP(*(.sdram*)) +#ifdef CONFIG_LVGL + KEEP(*(.lvgl_buf*)) +#endif + __SDRAM_End = .; +} GROUP_LINK_IN(SDRAM) + +#endif diff --git a/boards/renesas/ek_rx261/Kconfig.ek_rx261 b/boards/renesas/ek_rx261/Kconfig.ek_rx261 new file mode 100644 index 00000000000..1398477e9ba --- /dev/null +++ b/boards/renesas/ek_rx261/Kconfig.ek_rx261 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RX261 + select SOC_R5F52618BGFP diff --git a/boards/renesas/ek_rx261/board.cmake b/boards/renesas/ek_rx261/board.cmake new file mode 100644 index 00000000000..5a5399d5f2f --- /dev/null +++ b/boards/renesas/ek_rx261/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" +board_runner_args(jlink "--device=R5F52618" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1" ) +board_runner_args(rfp "--device=RX200" "--tool=e2l" "--interface=fine" "--erase") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) diff --git a/boards/renesas/ek_rx261/board.yml b/boards/renesas/ek_rx261/board.yml new file mode 100644 index 00000000000..3b120fa6c6b --- /dev/null +++ b/boards/renesas/ek_rx261/board.yml @@ -0,0 +1,6 @@ +board: + name: ek_rx261 + full_name: RX261 Evaluation Kit + vendor: renesas + socs: + - name: r5f52618bgfp diff --git a/boards/renesas/ek_rx261/doc/ek_rx261.webp b/boards/renesas/ek_rx261/doc/ek_rx261.webp new file mode 100644 index 00000000000..1f30eeff33e Binary files /dev/null and b/boards/renesas/ek_rx261/doc/ek_rx261.webp differ diff --git a/boards/renesas/ek_rx261/doc/index.rst b/boards/renesas/ek_rx261/doc/index.rst new file mode 100644 index 00000000000..f9e5c284384 --- /dev/null +++ b/boards/renesas/ek_rx261/doc/index.rst @@ -0,0 +1,176 @@ +.. zephyr:board:: ek_rx261 + +Overview +******** + +The EK-RX261 is an Evaluation Kit for the Renesas RX261 MCU Group, designed to evaluate features +of the RX261 family and accelerate embedded system development. The board includes rich +interfaces, peripheral connectors, and expansion support for popular ecosystem modules. + +The key features of the EK-RX261 board are categorized in three groups: + +**MCU Native Pin Access** + +- RX261 MCU (R5F52618BGFP), 32-bit RXv3 core at 64MHz +- 512KB Code Flash, 8KB Data Flash, 128KB RAM +- Native pin access through 6 x 2-pin and 14 x 2-pin x 3-piece male headers +- MCU current measurement points for current consumption measurement +- Precision 8.000MHz main oscillator and 32.768kHz sub-clock + +**System Control and Ecosystem Access** + +- Four 5V input sources: + + - USB (USB DEBUG1, USB FULL SPEED, USB SERIAL) + - External power supply (via TP5, TP6) + +- Two Debug Modes: + - Debug on-board via E2 Emulator OB (FINE interface) + - Debug in via 14-pin external header (FINE interface) + +- User LEDs: + - 3 User LEDs (Red, Green, Blue) + - 1 Power LED (White) + - 1 Debug LED (Yellow) + +- User Buttons: + - 2 User Switches + - 1 Reset Switch + +- Popular ecosystem expansion connectors: + + - 2x Grove connectors (I2C / Analog) + - 1x SparkFun Qwiic connector (I2C) + - 2x Digilent Pmod connectors (UART/SPI/I2C) + - Arduino Uno R3-compatible header + - mikroBUS connector + +- USB Full Speed Host and Device (micro-B connector) +- USB to Serial communication via FT234XD + +**Special Feature Access** + +- CAN FD transceiver with 3-pin header +- Touch interface (2 buttons) + +Hardware +******** + +Detailed hardware features can be found at: +- RX261 MCU: `RX261 Group User's Manual Hardware`_. +- EK-RX261 board: `EK-RX261 - User's Manual`_. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``ek_rx261`` board can be built, flashed, and debugged using standard +Zephyr workflows. Refer to :ref:`build_an_application` and :ref:`application_run` for more details. + +**Note:** Currently, the RX261 is built and programmed using the Renesas GCC RX toolchain. +Please follow the steps below to program it onto the board: + + - Download and install GCC for RX toolchain: + + https://llvm-gcc-renesas.com/rx-download-toolchains/ + + - Set env variable: + + .. code-block:: console + + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + export CROSS_COMPILE=/bin/rx-elf- + + - Build the Blinky Sample for EK-RX261 + + .. code-block:: console + + cd ~/zephyrproject/zephyr + west build -p always -b ek_rx261 samples/basic/blinky + +Flashing +======== + +Program can be flashed to EK-RX261 via either the on-board **E2 Emulator OB** or +an external **SEGGER J-Link** debugger (using the FINE interface). + +- **Renesas Flash Programmer (RFP)** can be used with the on-board E2 Emulator OB. + RFP is available at: https://www.renesas.com/software-tool/renesas-flash-programmer-programming-gui + +- **SEGGER J-Link** can be used with the 14-pin FINE connector (J27) for external flashing. + J-Link drivers are available at: https://www.segger.com/downloads/jlink/ + +1. **Connect to the debugger:** + + - For E2 Emulator OB: connect **USB DEBUG1 (J26)** + - For J-Link: connect to **14-pin FINE header (J27)** + +2. **Set jumper configuration according to the selected flash mode:** + + - **E2 Emulator OB (on-board):** + + - J22: Open + - J23: Jumper on pins **2-3** + - J24: Open + - J25: Open + + - **J-Link (external debugger):** + + - J22: Open + - J23: Jumper on pins **1-2** or **2-3** + - J24: **Closed** + - J25: Open + +3. **Run flashing command:** + + .. code-block:: console + + west flash # For E2 Emulator OB + west flash -r jlink # For J-Link (external debugger) + +Debugging +========= + +The EK-RX261 supports debugging through: + +- **On-board E2 Emulator OB (via USB DEBUG1)** +- **External debugger** using the 14-pin FINE header (J27) + +To use on-board E2 Emulator: + +- J22: Open +- J23: Jumper on pins **2-3** +- J24: Open +- J25: Open + +To use external debugger: + +- J24: Closed +- J22: Open +- J23: Jumper on pins 1-2 or 2-3 (depending on desired pull-up/down) +- J25: Open + +**Note:** External debugger (e.g., E2 Lite) cannot power the board. Supply external 5V via USB or TP5/TP6. + +References +********** +- `EK-RX261 Website`_ +- `RX261 MCU group Website`_ + +.. _EK-RX261 Website: + https://www.renesas.com/en/design-resources/boards-kits/ek-rx261 + +.. _RX261 MCU group Website: + https://www.renesas.com/en/products/rx261 + +.. _EK-RX261 - User's Manual: + https://www.renesas.com/en/document/mat/ek-rx261-v1-users-manual + +.. _RX261 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/rx260-group-rx261-group-users-manual-hardware diff --git a/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi b/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi new file mode 100644 index 00000000000..4b893daead4 --- /dev/null +++ b/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci6_default: sci6_default { + group1 { + psels = , /* TX */ + ; /* RX */ + }; + }; +}; diff --git a/boards/renesas/ek_rx261/ek_rx261.dts b/boards/renesas/ek_rx261/ek_rx261.dts new file mode 100644 index 00000000000..d1bf7269322 --- /dev/null +++ b/boards/renesas/ek_rx261/ek_rx261.dts @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_rx261-pinctrl.dtsi" + +/ { + model = "Renesas EK-RX261 KIT"; + compatible = "renesas,ek_rx261"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,console = &uart6; + zephyr,shell-uart = &uart6; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioportj 1 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioportc 5 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioporta 3 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + + }; + + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&pll { + div = <1>; + mul = ; + status = "okay"; +}; + +&cmt { + clock-frequency = ; + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&ioportc { + status = "okay"; +}; + +&ioportd { + status = "okay"; +}; + +&ioportj { + status = "okay"; +}; + +&sci6 { + pinctrl-0 = <&sci6_default>; + pinctrl-names = "default"; + status = "okay"; + + uart6: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/ek_rx261/ek_rx261.yaml b/boards/renesas/ek_rx261/ek_rx261.yaml new file mode 100644 index 00000000000..aa807dbe4ce --- /dev/null +++ b/boards/renesas/ek_rx261/ek_rx261.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: ek_rx261 +name: Renesas EK-RX261 +type: mcu +arch: rx +toolchain: + - cross-compile +supported: + - gpio + - serial + - timer +ram: 128 +flash: 512 +testing: + timeout_multiplier: 5 diff --git a/boards/renesas/ek_rx261/ek_rx261_defconfig b/boards/renesas/ek_rx261/ek_rx261_defconfig new file mode 100644 index 00000000000..c23cdd58f2a --- /dev/null +++ b/boards/renesas/ek_rx261/ek_rx261_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/fpb_ra4e1/board.cmake b/boards/renesas/fpb_ra4e1/board.cmake index 590f06a5743..a599fce2dd8 100644 --- a/boards/renesas/fpb_ra4e1/board.cmake +++ b/boards/renesas/fpb_ra4e1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA4E10D") +board_runner_args(pyocd "--target=R7FA4E10D") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/fpb_ra6e1/board.cmake b/boards/renesas/fpb_ra6e1/board.cmake index f4e7c1669a5..77a3a60450d 100644 --- a/boards/renesas/fpb_ra6e1/board.cmake +++ b/boards/renesas/fpb_ra6e1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA6E10F") +board_runner_args(pyocd "--target=R7FA6E10F") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/fpb_ra6e2/board.cmake b/boards/renesas/fpb_ra6e2/board.cmake index 368e10209f9..1d0dd4380c3 100644 --- a/boards/renesas/fpb_ra6e2/board.cmake +++ b/boards/renesas/fpb_ra6e2/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA6E2BB") +board_runner_args(pyocd "--target=R7FA6E2BB") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/fpb_rx261/Kconfig.fpb_rx261 b/boards/renesas/fpb_rx261/Kconfig.fpb_rx261 new file mode 100644 index 00000000000..3689a86dcb4 --- /dev/null +++ b/boards/renesas/fpb_rx261/Kconfig.fpb_rx261 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FPB_RX261 + select SOC_R5F52618BGFP diff --git a/boards/renesas/fpb_rx261/board.cmake b/boards/renesas/fpb_rx261/board.cmake new file mode 100644 index 00000000000..e7d620c2557 --- /dev/null +++ b/boards/renesas/fpb_rx261/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" +board_runner_args(jlink "--device=R5F52618" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1" ) +board_runner_args(rfp "--device=RX200" "--tool=e2l" "--interface=fine" "--erase") + +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/fpb_rx261/board.yml b/boards/renesas/fpb_rx261/board.yml new file mode 100644 index 00000000000..ffd674c7069 --- /dev/null +++ b/boards/renesas/fpb_rx261/board.yml @@ -0,0 +1,6 @@ +board: + name: fpb_rx261 + full_name: RX261 Fast Prototyping Board + vendor: renesas + socs: + - name: r5f52618bgfp diff --git a/boards/renesas/fpb_rx261/doc/fpb_rx261.webp b/boards/renesas/fpb_rx261/doc/fpb_rx261.webp new file mode 100644 index 00000000000..cbcac381b2e Binary files /dev/null and b/boards/renesas/fpb_rx261/doc/fpb_rx261.webp differ diff --git a/boards/renesas/fpb_rx261/doc/index.rst b/boards/renesas/fpb_rx261/doc/index.rst new file mode 100644 index 00000000000..09ba45824f0 --- /dev/null +++ b/boards/renesas/fpb_rx261/doc/index.rst @@ -0,0 +1,148 @@ +.. zephyr:board:: fpb_rx261 + +Overview +******** + +The FPB-RX261 is a Fast Prototyping Board for the Renesas RX261 MCU Group, designed to +evaluate features of the RX261 family and accelerate embedded system development. The board +includes native MCU pin access, integrated debugger, power flexibility, and expansion connectors. + +The key features of the FPB-RX261 board are categorized in two groups: + +**MCU Native Pin Access** + +- R5F52618BGFP MCU +- 64 MHz Renesas RXv3-based RX261 MCU in 100-pin LFQFP package +- 512 KB Code Flash, 8 KB Data Flash, 128 KB RAM +- Native pin access through 2 x 50-pin male headers (not fitted) +- MCU current measurement point for precision current consumption measurement +- RX MCU on-chip oscillators as main clock +- Providing 32.768 kHz crystal oscillator as sub clock + +**System Control and Ecosystem Access** + +- 5V input sources: + + - USB (USB DEBUG1 - J5) + - External 5V via 2-pin header (J8) + +- On-board debugger via E2 Emulator OB (FINE interface) + +- User LEDs: + + - 2 Green User LEDs (PJ1, PC5) + - 1 Green Power LED + - 1 Yellow Debug LED + +- User Buttons: + + - 1 User Switch (S1 - P32) + - 1 Reset Switch (S2) + +- Popular expansion connectors: + + - 2x Digilent Pmod connectors (J13, J14 - UART/SPI/I2C) + - Arduino Uno R3-compatible header (J9-J12) + +Hardware +******** + +Detailed hardware features can be found at: +- RX261 MCU: `RX261 Group User's Manual Hardware`_. +- FPB-RX261 board: `FPB-RX261 - User's Manual`_. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``fpb_rx261`` board can be built, flashed, and debugged using standard Zephyr workflows. +Refer to :ref:`build_an_application` and :ref:`application_run` for more details. + +**Note:** Currently, the RX261 is built and programmed using the Renesas GCC RX toolchain. +Please follow the steps below to program it onto the board: + + - Download and install GCC for RX toolchain: + + https://llvm-gcc-renesas.com/rx-download-toolchains/ + + - Set env variable: + + .. code-block:: console + + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + export CROSS_COMPILE=/bin/rx-elf- + + - Build the Blinky Sample for FPB-RX261 + + .. code-block:: console + + cd ~/zephyrproject/zephyr + west build -p always -b fpb_rx261 samples/basic/blinky + +Flashing +======== + +The program can be flashed to FPB-RX261 via the on-board **E2 Emulator OB**. + +- **Renesas Flash Programmer (RFP)** can be used with the on-board debugger + https://www.renesas.com/software-tool/renesas-flash-programmer-programming-gui + +1. **Connect the board:** + + - Use USB DEBUG1 (J5) to connect the on-board E2 Emulator to the PC + +2. **Configure jumpers for flashing:** + + - J4: Jumper on pins **2-3** (enable E2 OB) + - J7: Jumper on pins **1-2** (3.3V system voltage) + +3. **Run flashing command:** + + .. code-block:: console + + west flash + + Or use Renesas Flash Programmer with settings: + - Debugger: E2 Emulator Lite + - Interface: FINE + - MCU: R5F52618 + +Debugging +========= + +Debugging is supported via: + +- **On-board E2 Emulator OB** using USB DEBUG1 (J5) + +To use debugger: + +- J4: Jumper on pins **2-3** (enable E2 OB) +- J7: Jumper on pins **1-2** (3.3V) +- LED4 (Yellow) indicates debugger status + +**Note:** Only one FPB-RX261 board can be debugged per PC at a time using E2 OB. + +References +********** +- `FPB-RX261 Website`_ +- `RX261 MCU group Website`_ + +.. _FPB-RX261 Website: + https://www.renesas.com/en/design-resources/boards-kits/fpb-rx261 + +.. _RX261 MCU group Website: + https://www.renesas.com/en/products/rx261 + +.. _FPB-RX261 - User's Manual: + http://renesas.com/en/document/mat/fpb-rx261-v1-users-manual?r=25565483 + +.. _RX261 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/rx260-group-rx261-group-users-manual-hardware?r=25565707 diff --git a/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi b/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi new file mode 100644 index 00000000000..e00377a7d4b --- /dev/null +++ b/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci5_default: sci5_default { + group1 { + psels = , /* TX */ + ; /* RX */ + }; + }; +}; diff --git a/boards/renesas/fpb_rx261/fpb_rx261.dts b/boards/renesas/fpb_rx261/fpb_rx261.dts new file mode 100644 index 00000000000..aa024097aa9 --- /dev/null +++ b/boards/renesas/fpb_rx261/fpb_rx261.dts @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "fpb_rx261-pinctrl.dtsi" + +/ { + model = "Renesas FPB-RX261"; + compatible = "renesas,fpb_rx261"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,console = &uart5; + zephyr,shell-uart = &uart5; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioportj 1 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioportc 5 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + }; +}; + +&subclk { + status = "okay"; +}; + +&cmt { + clock-frequency = ; + status = "okay"; +}; + +&pclkblock { + clocks = <&hoco>; +}; + +&clkout { + clocks = <&hoco>; +}; + +&uclk { + clocks = <&hoco>; +}; + +&ioport3 { + status = "okay"; +}; + +&ioportc { + status = "okay"; +}; + +&ioportj { + status = "okay"; +}; + +&sci5 { + pinctrl-0 = <&sci5_default>; + pinctrl-names = "default"; + status = "okay"; + + uart5: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/fpb_rx261/fpb_rx261.yaml b/boards/renesas/fpb_rx261/fpb_rx261.yaml new file mode 100644 index 00000000000..0f182d6d028 --- /dev/null +++ b/boards/renesas/fpb_rx261/fpb_rx261.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: fpb_rx261 +name: Renesas RX261 Fast Prototyping Board +type: mcu +arch: rx +toolchain: + - cross-compile +supported: + - gpio + - serial + - timer +ram: 128 +flash: 512 +testing: + timeout_multiplier: 5 diff --git a/boards/renesas/fpb_rx261/fpb_rx261_defconfig b/boards/renesas/fpb_rx261/fpb_rx261_defconfig new file mode 100644 index 00000000000..c23cdd58f2a --- /dev/null +++ b/boards/renesas/fpb_rx261/fpb_rx261_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/mck_ra8t1/board.cmake b/boards/renesas/mck_ra8t1/board.cmake index 17d45a20094..ca2636c4d9a 100644 --- a/boards/renesas/mck_ra8t1/board.cmake +++ b/boards/renesas/mck_ra8t1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA8T1AH") +board_runner_args(pyocd "--target=R7FA8T1AH") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi index e9d127f2dfd..31482a1e4d2 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi +++ b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi @@ -35,6 +35,14 @@ }; }; + i3c0_default: i3c0_default { + group1 { + /* SCL SDA */ + psels = , + ; + }; + }; + pwm2_default: pwm2_default { group1 { /* GTIOC2A */ diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index 75cb5fc5c8e..dd56259d909 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -97,6 +97,12 @@ status = "okay"; }; +&i3cclk { + clocks = <&pllp>; + div = <3>; + status = "okay"; +}; + &ioport3 { status = "okay"; }; @@ -140,6 +146,16 @@ status = "okay"; }; +&i3c0 { + i2c-scl-hz = ; + i3c-scl-hz = ; + pinctrl-0 = <&i3c0_default>; + pinctrl-names = "default"; + interrupts = <60 1>, <61 1>, <62 1>, <63 1>, <64 1>, <65 1>; + interrupt-names = "resp", "rx", "tx", "rcv", "ibi", "eei"; + status = "okay"; +}; + &flash1 { partitions { compatible = "fixed-partitions"; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml index 7bb910b764a..c1f389fdaa8 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml @@ -13,4 +13,5 @@ supported: - watchdog - usbd - counter + - i3c vendor: renesas diff --git a/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 b/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 index 3587994f266..5e28304e1eb 100644 --- a/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 +++ b/boards/renesas/rsk_rx130/Kconfig.rsk_rx130 @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_RSK_RX130 - select SOC_R5F513083XFB + select SOC_R5F51308AXFP diff --git a/boards/renesas/rsk_rx130/board.yml b/boards/renesas/rsk_rx130/board.yml index 90573aed223..3c74175468e 100644 --- a/boards/renesas/rsk_rx130/board.yml +++ b/boards/renesas/rsk_rx130/board.yml @@ -10,4 +10,4 @@ board: - name: 512kb - name: 128kb socs: - - name: r5f513083xfb + - name: r5f51308axfp diff --git a/boards/renesas/rsk_rx130/doc/index.rst b/boards/renesas/rsk_rx130/doc/index.rst index c76d4b9bcb8..857cee1e5a4 100644 --- a/boards/renesas/rsk_rx130/doc/index.rst +++ b/boards/renesas/rsk_rx130/doc/index.rst @@ -64,12 +64,14 @@ Programming and Debugging .. zephyr:board-supported-runners:: -Applications for the ``rsk_rx130@512kb`` board target configuration can be -built, flashed, and debugged as below. +Applications for the ``rsk_rx130@512kb`` board target can be built, flashed, and +debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. -Currently, the Zephyr SDK hasn't added support for RX builds yet, so the GCC for RX toolchain is required and build system need to be set to use "cross-compile". +If you want to build Zephyr application for RSK-RX130 board using Renesas GCC RX toolchain follow +the steps below: - - Download and install GCC for RX v8.3.0.202405 toolchain: + - Download and install GCC for RX toolchain: https://llvm-gcc-renesas.com/rx-download-toolchains/ @@ -90,17 +92,14 @@ Currently, the Zephyr SDK hasn't added support for RX builds yet, so the GCC for Flashing ======== -Program can be flashed to RSKRX130-512KB via Jlink with RX adapter boards. +Program can be flashed to RSKRX130-512KB using Jlink with RX adapter boards, by +connecting the board's debug connector port to the host PC. Here's an example +for building and flashing the :zephyr:code-sample:`hello_world` application. -To flash the program to board - - 1. Connect from board's debug connector port to host PC using Jlink debugger. - - 2. Execute west command - - .. code-block:: console - - west flash +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rsk_rx130@512kb + :goals: build flash Debugging ========= diff --git a/boards/renesas/rsk_rx130/rsk_rx130.dts b/boards/renesas/rsk_rx130/rsk_rx130.dts index 1ca2ac91d81..b132e672872 100644 --- a/boards/renesas/rsk_rx130/rsk_rx130.dts +++ b/boards/renesas/rsk_rx130/rsk_rx130.dts @@ -6,9 +6,10 @@ /dts-v1/; -#include +#include #include #include "rsk_rx130_512kb-pinctrl.dtsi" +#include / { model = "Renesas RSK+RX130-512KB KIT"; @@ -17,6 +18,7 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &code_flash; + zephyr,flash-controller = &flash; zephyr,console = &uart1; zephyr,shell-uart = &uart1; }; @@ -35,9 +37,20 @@ }; }; + buttons { + compatible = "gpio-keys"; + + sw1: button { + label = "sw1"; + gpios = <&ioport3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; led1 = &led3; + sw0 = &sw1; }; }; @@ -63,6 +76,10 @@ status = "okay"; }; +&ioport3 { + status = "okay"; +}; + &ioportd { status = "okay"; }; @@ -81,3 +98,43 @@ status = "okay"; }; }; + +&rspi0 { + pinctrl-0 = <&rspi0_default>; + pinctrl-names = "default"; + ssl-assert = <0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&port_irq1 { + status = "okay"; +}; + +&mtu1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + + pwm1: pwm { + status = "okay"; + }; +}; + +&data_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi b/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi index 8b4006931bc..fb048e8519e 100644 --- a/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi +++ b/boards/renesas/rsk_rx130/rsk_rx130_512kb-pinctrl.dtsi @@ -5,10 +5,32 @@ */ &pinctrl { - sci1_default: sci1_default { + sci1_default: sci1_default { group1 { psels = , /* TX */ ; /* RX */ }; }; + + rspi0_default: rspi0_default { + group1 { + psels = , + , + , + ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , /* SDA P13*/ + ; /* SCL P12*/ + }; + }; + + pwm1_default: pwm1_default { + group1 { + psels = ; /* P20 MTIOC1A JA2-PIN22*/ + }; + }; }; diff --git a/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml b/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml index 49890d8e2fb..4a715faaf2d 100644 --- a/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml +++ b/boards/renesas/rsk_rx130/rsk_rx130_512kb.yaml @@ -7,9 +7,12 @@ type: mcu arch: rx toolchain: - cross-compile + - zephyr supported: - gpio - serial - timer + - spi + - i2c ram: 48 flash: 512 diff --git a/boards/renesas/rssk_ra2l1/Kconfig.rssk_ra2l1 b/boards/renesas/rssk_ra2l1/Kconfig.rssk_ra2l1 new file mode 100644 index 00000000000..26883572896 --- /dev/null +++ b/boards/renesas/rssk_ra2l1/Kconfig.rssk_ra2l1 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RSSK_RA2L1 + select SOC_R7FA2L1ABXXFP diff --git a/boards/renesas/rssk_ra2l1/board.cmake b/boards/renesas/rssk_ra2l1/board.cmake new file mode 100644 index 00000000000..77d8090ea70 --- /dev/null +++ b/boards/renesas/rssk_ra2l1/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=r7fa2l1ab") +board_runner_args(pyocd "--target=r7fa2l1ab") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/renesas/rssk_ra2l1/board.yml b/boards/renesas/rssk_ra2l1/board.yml new file mode 100644 index 00000000000..61447d9e96c --- /dev/null +++ b/boards/renesas/rssk_ra2l1/board.yml @@ -0,0 +1,6 @@ +board: + name: rssk_ra2l1 + full_name: Capacitive Touch Evaluation System for RA2L1 + vendor: renesas + socs: + - name: r7fa2l1abxxfp diff --git a/boards/renesas/rssk_ra2l1/doc/index.rst b/boards/renesas/rssk_ra2l1/doc/index.rst new file mode 100644 index 00000000000..a8fb57ace93 --- /dev/null +++ b/boards/renesas/rssk_ra2l1/doc/index.rst @@ -0,0 +1,142 @@ +.. zephyr:board:: rssk_ra2l1 + +Overview +******** + +The RA2L1 MCU Group Capacitive Touch Evaluation System (RTK0EG0022S01001BJ) is a +kit created for evaluating the RA2L1 MCU Group Capacitive Touch Sensing Unit (CTSU). + +RTK0EG0022S01001BJ is composed of two boards: The RA2L1 Cap Touch CPU Board is mounted with an +RA2L1 MCU which includes an on-chip CTSU. The Capacitive Touch Application Board Capacitive Touch +Application Board is equipped with self-capacitance touch buttons, wheel and slider electrodes, and LEDs +touch electrodes. + +Renesas RA2L1 Microcontroller Group has following features + +- 48MHz, Arm Cortex-M23 core +- 256kB or 128kB Code Flash, 8kB Data Flash, 32kB SRAM (divided on 2 equal areas + with- and without- ECC support) +- SCI x 5 +- SPI x 2 +- I2C x 2 +- CAN x 1 +- 12-bit A/D Converter +- 12-bit D/A Converter +- Low-Power Analog Comparator x 2 +- Temperature Sensor +- General PWM Timer 32-bit x 4 +- General PWM Timer 16-bit x 6 +- Low Power Asynchronous General-Purpose Timer x 2 +- Watchdog Timer (WDT) +- Independent Watchdog Timer (IWDT) +- Up to 85 Input/Output pins (depends on the package type) + +Hardware +******** + +The main functions of the RA2L1 Cap Touch CPU board are as follows: + +- Renesas RA2L1 MCU Group + + - R7FA2L1AB2DFP + - 100-pin LFQFP package + - 48MHz Arm Cortex®-M23 Core with built-in Arm® MPU (Armv8-M architecture) + - 32KB SRAM + - 256KB code flash memory + - 8KB data flash memory + - 32-channel capacitive touch sensing unit (CTSU) pins + +- Connectivity + + - USB serial conversion interface (FT234XD manufactured by FTDI) + - 10-pin JTAG/SWD interface for connecting external debugger or programmer (option) + - Application board GPIO interface: 2.54mm pitch, 16 pins (8 x 2 DIL) + - Application board CTSU interface: 2.54mm pitch, 40 pins (20 x 2 DIL) + +- Other functions + + - MCU current measurement jumper + - User push button switches: 2 + - User LEDs: 2 + +.. figure:: rtk0eg0018c01001bj.webp + :width: 300 + :align: center + + RA2L1 Cap Touch CPU Board (Credit: Renesas Electronics Corporation) + +Key functions of the Capacitive Touch Application Board are as follows: + +- Self-capacitance detection touch electrodes + + - Buttons: 3 + - Wheel (4-electrode configuration): 1 + - Slider (5-electrode configuration): 1 + +- LEDs: 16 + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and debugging +************************* + +Building & Flashing +=================== + +You can build and flash an application with an external J-Link debug adapter connect to +J1 connector. +:ref:`build_an_application` and +:ref:`application_run` for more details. + +Here is an example for building and flashing the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: rssk_ra2l1 + :goals: build flash + + +Debugging +========= + +Debugging also can be done with an external J-Link debug adapter connected to +J1 connector. +For the debug log output through UART console, you need to connect a USB cable +from the host PC to the USB Serial Conversion on CN5. +The following command is debugging the :zephyr:code-sample:`blinky` application. +Also, see the instructions specific to the debug server that you use. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: rssk_ra2l1 + :maybe-skip-config: + :goals: debug + +Or you can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface + +Once downloaded and installed, open Segger Ozone and configure the debug project +like so: + +* Target Device: R7FA2L1AB +* Target Interface: SWD +* Target Interface Speed: 4 MHz +* Host Interface: USB +* Program File: + + +References +********** +- `RSSK-RA2L1 Web site`_ +- `RA2L1 MCU Group Website`_ + +.. _RSSK-RA2L1 Web site: + https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/rtk0eg0022s01001bj-capacitive-touch-evaluation-system-ra2l1 + +.. _RA2L1 MCU Group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra2l1-48mhz-arm-cortex-m23-ultra-low-power-general-purpose-microcontroller + +.. _Segger Ozone Download: + https://www.segger.com/downloads/jlink#Ozone diff --git a/boards/renesas/rssk_ra2l1/doc/rssk_ra2l1.webp b/boards/renesas/rssk_ra2l1/doc/rssk_ra2l1.webp new file mode 100644 index 00000000000..2951997525c Binary files /dev/null and b/boards/renesas/rssk_ra2l1/doc/rssk_ra2l1.webp differ diff --git a/boards/renesas/rssk_ra2l1/doc/rtk0eg0018c01001bj.webp b/boards/renesas/rssk_ra2l1/doc/rtk0eg0018c01001bj.webp new file mode 100644 index 00000000000..044a8482747 Binary files /dev/null and b/boards/renesas/rssk_ra2l1/doc/rtk0eg0018c01001bj.webp differ diff --git a/boards/renesas/rssk_ra2l1/rssk_ra2l1-pinctrl.dtsi b/boards/renesas/rssk_ra2l1/rssk_ra2l1-pinctrl.dtsi new file mode 100644 index 00000000000..8002bddb347 --- /dev/null +++ b/boards/renesas/rssk_ra2l1/rssk_ra2l1-pinctrl.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* TXD RXD */ + psels = , + ; + }; + }; +}; diff --git a/boards/renesas/rssk_ra2l1/rssk_ra2l1.dts b/boards/renesas/rssk_ra2l1/rssk_ra2l1.dts new file mode 100644 index 00000000000..101dd455936 --- /dev/null +++ b/boards/renesas/rssk_ra2l1/rssk_ra2l1.dts @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include + +#include +#include +#include "rssk_ra2l1-pinctrl.dtsi" + +/ { + model = "Renesas RSSK-RA2L1"; + compatible = "renesas,r7fa2l1abxxfp", "renesas,ra2l1"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart9; + zephyr,shell-uart = &uart9; + }; + + leds { + compatible = "gpio-leds"; + + led2: led2 { + gpios = <&ioport3 5 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioport3 4 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: s2 { + gpios = <&ioport2 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + + button1: s3 { + gpios = <&ioport2 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led2; + led1 = &led3; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdt; + }; +}; + +&ioport2 { + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&port_irq0 { + interrupts = <8 3>; + status = "okay"; +}; + +&port_irq1 { + interrupts = <9 3>; + status = "okay"; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + interrupts = <0 3>, <1 3>, <2 3>, <3 3>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; + + uart9: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&wdt { + status = "okay"; +}; diff --git a/boards/renesas/rssk_ra2l1/rssk_ra2l1.yaml b/boards/renesas/rssk_ra2l1/rssk_ra2l1.yaml new file mode 100644 index 00000000000..82954661006 --- /dev/null +++ b/boards/renesas/rssk_ra2l1/rssk_ra2l1.yaml @@ -0,0 +1,16 @@ +identifier: rssk_ra2l1 +name: Renesas RSSK-RA2L1 +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - watchdog +vendor: renesas +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/renesas/rssk_ra2l1/rssk_ra2l1_defconfig b/boards/renesas/rssk_ra2l1/rssk_ra2l1_defconfig new file mode 100644 index 00000000000..f26066de3e5 --- /dev/null +++ b/boards/renesas/rssk_ra2l1/rssk_ra2l1_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y diff --git a/boards/renesas/rzg2ul_smarc/Kconfig.rzg2ul_smarc b/boards/renesas/rzg2ul_smarc/Kconfig.rzg2ul_smarc new file mode 100644 index 00000000000..190fcdcb4cc --- /dev/null +++ b/boards/renesas/rzg2ul_smarc/Kconfig.rzg2ul_smarc @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZG2UL_SMARC + select SOC_R9A07G043U11GBG diff --git a/boards/renesas/rzg2ul_smarc/board.cmake b/boards/renesas/rzg2ul_smarc/board.cmake new file mode 100644 index 00000000000..5281957a3d5 --- /dev/null +++ b/boards/renesas/rzg2ul_smarc/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R9A07G043U11") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rzg2ul_smarc/board.yml b/boards/renesas/rzg2ul_smarc/board.yml new file mode 100644 index 00000000000..81c2355335c --- /dev/null +++ b/boards/renesas/rzg2ul_smarc/board.yml @@ -0,0 +1,6 @@ +board: + name: rzg2ul_smarc + full_name: RZ/G2UL SMARC Evaluation Board Kit + vendor: renesas + socs: + - name: r9a07g043u11gbg diff --git a/boards/renesas/rzg2ul_smarc/doc/index.rst b/boards/renesas/rzg2ul_smarc/doc/index.rst new file mode 100644 index 00000000000..6d2a3fe5629 --- /dev/null +++ b/boards/renesas/rzg2ul_smarc/doc/index.rst @@ -0,0 +1,232 @@ +.. zephyr:board:: rzg2ul_smarc + +Overview +******** + +The Renesas RZ/G2UL SMARC Evaluation Board Kit (RZ/G2UL-EVKIT) consists of a SMARC v2.1 module board and a carrier board. + +* Device: RZ/G2UL (Type-1) R9A07G043U11GBG + + * Cortex-A55 Single, Cortex-M33 + * BGA361pin, 13mmSq body, 0.5mm pitch + +* SMARC v2.1 Module Board Functions + + * DDR4 SDRAM: 1GB x 1pc + * QSPI flash memory: 128Mb x 1pc `AT25QL128A `_ + * eMMC memory: 64GB x 1pc + * The microSD card slot is implemented and used as an eSD for boot + * 5-output clock oscillator `5P35023 `_ implemented + * PMIC power supply `DA9062 `_ implemented + +* Carrier Board Functions + + * The FFC/FPC connector is mounted as standard for connection to high-speed serial interface for camera module. + * The Micro-HDMI connector via DSI/HDMI conversion module is mounted as standard for connection to high-speed serial interface for digital video module. + * The Micro-AB receptacle (ch0: USB2.0 OTG) and A receptacle (ch1: USB2.0 Host) are respectively mounted as standard for connection to USB interface. + * The RJ45 connector is mounted as standard for software development and evaluation using Ethernet. + * The audio codec is mounted as standard for advance development of audio system. The audio jack is implemented for connection to audio interface. + * The Micro-AB receptacles are implemented for connection to asynchronous serial port interface. + * The microSD card slot and two sockets for PMOD are implemented as an interface for peripheral functions. + * For power supply, a mounted USB Type-C receptacle supports the USB PD standard. + +Hardware +******** + +The Renesas RZ/G2UL MPU documentation can be found at `RZ/G2UL Group Website`_ + +.. figure:: rzg2ul_block_diagram.webp + :width: 600px + :align: center + :alt: RZ/G2UL group feature + + RZ/G2UL block diagram (Credit: Renesas Electronics Corporation) + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +Applications for the ``rzg2ul_smarc`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +Console +======= + +By default, `J-Link RTT Viewer`_ is used by Zephyr running on CM33 for providing serial console. +The only serial port (SER3_UART micro-USB) is reserved for CA55 to run Linux. + +.. note:: + + Set SW1-1 on the board to "OFF" to select JTAG debug mode, which is required for + RTT to work. + +There are two ways to use the RTT Viewer on this board. The basic steps for each method are +described below: + +1. Using with Ozone +------------------- + +After the Zephyr application has been built successfully, open J-Link RTT Viewer and configure the +connection as follows: + +- **Connect to J-Link**: Existing Session (enable Auto Reconnect) +- **RTT Control Block**: Auto Detection +- Click **OK** + +Next, open `Ozone Debugger`_ and choose "Create New Project". Inside the "New Project Wizard" +configure the settings as follows: + +- **Device**: R9A07G043U11 +- **Register Set**: Cortex-M33 +- Click **Next** +- **Target Interface**: SWD +- **Target Interface Speed**: 4MHz +- **Host Interface**: USB +- Click **Next** +- Set the full path of ``zephyr.elf`` file. The path should resemble ``zephyrproject/zephyr/build/zephyr/zephyr.elf`` +- Click **Next**, leave all options by default, and click **Finish** +- Press **F5** to download and reset program + +2. Using with U-Boot +-------------------- + +After the Zephyr application has been built successfully, open the ``zephyr.map`` file located in +``zephyrproject\zephyr\build\zephyr\zephyr.map``. Locate the symbol ``_SEGGER_RTT`` and copy its +address value in hexadecimal. + +Then, perform the "Flashing" steps described below to run the Zephyr application using U-Boot. As soon as the +application is invoked, open J-Link RTT Viewer and configure the connection as follows: + +- **Connect to J-Link**: USB +- **Specify Target Device**: R9A07G043U11 (enable Force go on connect) +- **Target Interface & Speed**: SWD @ 4000 kHz +- **RTT Control Block**: Select "Address", then paste the address of the ``_SEGGER_RTT`` symbol copied earlier. +- Click **OK** + +.. note:: + + When using RTT Viewer with a Zephyr application launched by U-Boot, it is important to connect + the RTT Viewer immediately after executing the U-Boot command sequence. This helps avoid losing + early log output. + +Debugging +========= + +It is possible to load and execute a Zephyr application binary on +this board on the Cortex-M33 System Core from +the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`). + +Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rzg2ul_smarc/r9a07g043u11gbg/cm33 + :goals: build debug + +Flashing +======== + +RZ/G2UL-EVKIT is designed to start different systems on different cores. +It uses Yocto as the build system to build Linux system and boot loaders +to run Zephyr on Cortex-M33 with u-boot. The minimal steps are described below. + +1. Follow "2.2 Building Images" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to prepare the build environment. + +2. At step (4), follow step "2. Download Multi-OS Package" and "3. Add the layer for Multi-OS Package" + of "3.2 OpenAMP related stuff Integration for RZ/G2L, RZ/G2LC and RZ/G2UL" of `Release Note for RZ/G Multi-OS Package V2.2.0`_ + to add the layer for Multi-OS Package. + + .. code-block:: console + + $ cd ~/rzg_vlp_ + $ unzip /r01an5869ej0220-rzg-multi-os-pkg.zip + $ tar zxvf r01an5869ej0220-rzg-multi-os-pkg/meta-rz-features_multi-os_v2.2.0.tar.gz + $ bitbake-layers add-layer ../meta-rz-features/meta-rz-multi-os/meta-rzg2l + +3. Start the build: + + .. code-block:: console + + $ MACHINE=smarc-rzg2ul bitbake core-image-minimal + + The below necessary artifacts will be located in the build/tmp/deploy/images + + +---------------+------------------------------------------------------+ + | Artifacts | File name | + +===============+======================================================+ + | Boot loader | bl2_bp-smarc-rzg2ul.srec | + | | | + | | fip-smarc-rzg2ul.srec | + +---------------+------------------------------------------------------+ + | Flash Writer | Flash_Writer_SCIF_RZG2UL_SMARC_DDR4_1GB_1PCS.mot | + +---------------+------------------------------------------------------+ + +4. Follow "4.2 Startup Procedure" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ for power supply and board setting + at SCIF download (SW11[1:4] = OFF, ON, OFF, ON) and (SW1[1:3] = ON, OFF, OFF) + +5. Follow "4.3 Download Flash Writer to RAM" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to download Flash Writer to RAM + +6. Follow "4.4 Write the Bootloader" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to write the boot loader + to the target board by using Flash Writer. + +7. Follow "4.5 Change Back to Normal Boot Mode" with switch setting (SW11[1:4] = OFF, OFF, OFF, ON) and (SW1[1:2] = ON, OFF) + +8. Follow "3. Preparing the SD Card" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to write files to the microSD Card + +9. Copy zephyr.bin file to microSD card + +10. Follow "4.4.2 CM33 Sample Program Invocation with u-boot" from the beginning to step 4 of `Release Note for RZ/G Multi-OS Package V2.2.0`_ + +11. Execute the commands stated below on the console to start zephyr application with CM33 core. + Here, "N" stands for the partition number in which you stored zephyr.bin file. + + .. code-block:: console + + Hit any key to stop autoboot: 2 + => dcache off + => mmc dev 1 + => fatload mmc 1:N 0x00010000 zephyr.bin + => fatload mmc 1:N 0x40010000 zephyr.bin + => cm33 start_normal 0x00010000 0x40010000 + => dcache on + +Troubleshooting +=============== + +By default, the only valid serial port (SER3_UART micro-USB port) controlled by SCIF0 is used by Linux to +print Linux console output. Therefore, in order to use it from Zephyr, the Linux console must first be disabled. +To do this, run the following command in the Linux console to unbind the SCIF0 driver: + +.. code-block:: console + + $ echo 1004b800.serial | tee /sys/bus/platform/drivers/sh-sci/unbind + +This allows the SCIF0 to be accessed from the Zephyr side in debug mode for providing serial console. +Please note that the SCIF0 driver is disabled by default on the Zephyr side to prevent conflicts. + +References +********** + +.. target-notes:: + +.. _RZ/G2UL Group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg2ul-general-purpose-microprocessors-single-core-arm-cortex-a55-10ghz-cpu-and-single-core-arm-cortex-m33 + +.. _RZG2UL-EVKIT Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg2ul-evkit-evaluation-board-kit-rzg2ul-mpu + +.. _SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide: + https://www.renesas.com/en/document/gde/smarc-evk-rzg2l-rzg2lc-rzg2ul-linux-start-guide-rev106 + +.. _Release Note for RZ/G Multi-OS Package V2.2.0: + https://www.renesas.com/en/document/rln/release-note-rzg-multi-os-package-v220?r=1522841 + +.. _J-Link RTT Viewer: + https://www.segger.com/products/debug-probes/j-link/tools/rtt-viewer + +.. _Ozone Debugger: + https://www.segger.com/products/development-tools/ozone-j-link-debugger/ diff --git a/boards/renesas/rzg2ul_smarc/doc/rzg2ul_block_diagram.webp b/boards/renesas/rzg2ul_smarc/doc/rzg2ul_block_diagram.webp new file mode 100644 index 00000000000..17ff3ebd9bc Binary files /dev/null and b/boards/renesas/rzg2ul_smarc/doc/rzg2ul_block_diagram.webp differ diff --git a/boards/renesas/rzg2ul_smarc/doc/rzg2ul_smarc.webp b/boards/renesas/rzg2ul_smarc/doc/rzg2ul_smarc.webp new file mode 100644 index 00000000000..0f5f17ccede Binary files /dev/null and b/boards/renesas/rzg2ul_smarc/doc/rzg2ul_smarc.webp differ diff --git a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc-pinctrl.dtsi b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc-pinctrl.dtsi new file mode 100644 index 00000000000..13eecfb3d0b --- /dev/null +++ b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc-pinctrl.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ scif0_pins: scif0 { + scif0-pinmux { + pinmux = , /* RXD */ + ; /* TXD */ + }; + }; +}; diff --git a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.dts b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.dts new file mode 100644 index 00000000000..56d363e2fa5 --- /dev/null +++ b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "rzg2ul_smarc-pinctrl.dtsi" + +/ { + model = "Renesas RZ/G2UL SMARC"; + compatible = "renesas,rzg2ul-smarc"; + + chosen { + zephyr,sram = &ddr; + }; + + ddr: memory@60010000 { + compatible = "mmio-sram"; + reg = <0x60010000 DT_SIZE_M(46)>; + }; +}; diff --git a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.yaml b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.yaml new file mode 100644 index 00000000000..c547a2c5385 --- /dev/null +++ b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33.yaml @@ -0,0 +1,10 @@ +identifier: rzg2ul_smarc/r9a07g043u11gbg/cm33 +name: Cortex-M33 for Renesas RZ/G2UL SMARC +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio diff --git a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33_defconfig b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33_defconfig new file mode 100644 index 00000000000..dc2dd68d75c --- /dev/null +++ b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc_r9a07g043u11gbg_cm33_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +# Enable console +CONFIG_CONSOLE=y + +# Segger RTT +CONFIG_RTT_CONSOLE=y +CONFIG_USE_SEGGER_RTT=y diff --git a/boards/renesas/rzv2h_evk/Kconfig.rzv2h_evk b/boards/renesas/rzv2h_evk/Kconfig.rzv2h_evk new file mode 100644 index 00000000000..57f0850a8c4 --- /dev/null +++ b/boards/renesas/rzv2h_evk/Kconfig.rzv2h_evk @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZV2H_EVK + select SOC_R9A09G057H44GBG_CM33 if BOARD_RZV2H_EVK_R9A09G057H44GBG_CM33 + select SOC_R9A09G057H44GBG_CR8 if BOARD_RZV2H_EVK_R9A09G057H44GBG_CR8_0 diff --git a/boards/renesas/rzv2h_evk/board.cmake b/boards/renesas/rzv2h_evk/board.cmake new file mode 100644 index 00000000000..d9a2d4b7a51 --- /dev/null +++ b/boards/renesas/rzv2h_evk/board.cmake @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_RZV2H_EVK_R9A09G057H44GBG_CM33) + board_runner_args(jlink "--device=R9A09G057H44_M33_0") +endif() + +if (CONFIG_BOARD_RZV2H_EVK_R9A09G057H44GBG_CR8_0) + board_runner_args(jlink "--device=R9A09G057H44_R8_0") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rzv2h_evk/board.yml b/boards/renesas/rzv2h_evk/board.yml new file mode 100644 index 00000000000..dd3d70893e8 --- /dev/null +++ b/boards/renesas/rzv2h_evk/board.yml @@ -0,0 +1,6 @@ +board: + name: rzv2h_evk + full_name: RZ/V2H Evaluation Board Kit + vendor: renesas + socs: + - name: r9a09g057h44gbg diff --git a/boards/renesas/rzv2h_evk/doc/index.rst b/boards/renesas/rzv2h_evk/doc/index.rst new file mode 100644 index 00000000000..95d94032d88 --- /dev/null +++ b/boards/renesas/rzv2h_evk/doc/index.rst @@ -0,0 +1,244 @@ +.. zephyr:board:: rzv2h_evk + +Overview +******** + +The RZ/V2H high-end AI MPU boasts Renesas' proprietary dynamically reconfigurable processor AI accelerator (DRP-AI3), +quad Arm Cortex-A55 (1.8GHz) Linux processors, and dual Cortex-R8 (800MHz) real-time processors. +Furthermore, the RZ/V2H also includes another dynamically reconfigurable processor (DRP). +This processor can accelerate image processing, such as OpenCV, and dynamics calculations required for robotics applications. +It also features high-speed interfaces like PCIe, USB 3.2, and Gigabit Ethernet, +making it an ideal microprocessor for applications such as autonomous robots and machine vision in factory automation, +where advanced AI processing must be implemented with low power consumption. + +* RZ/V2H Secure Evaluation Board (CPU Board) + + * PMIC: RAA215300 + * Clock generator: 5L35023B + * Main memory: LPDDR4X 8GB x 2 + * xSPI Flash memory: 64MB + * External memory: Micro SD x 2 + * High-speed interface: + + * Gigabit Ethernet x 2 ports + * USB 3.2 Gen2 x 2ch (Host only) + * USB 2.0 x 2ch (On-the-Go (OTG) x 1ch, Host x 1ch) + * PCIe Gen3 x 1ch (4 lanes max) + * MIPI CSI-2 x 4ch + * MIPI DSI x 1ch + * GPIO: 86 pins + +* RZ/V2H-EVK Expansion Board (EXP Board): + + * HDMI Tx x 1 + * Audio AUX connector x 1ch + * Audio MIC connector x 1ch + * Audio HP connector x 1ch + * Pmod x 4 + +Hardware +******** + +The Renesas RZ/V2H documentation can be found at `RZ/V2H Group Website`_ + +.. figure:: rzv2h_block_diagram.webp + :width: 600px + :align: center + :alt: RZ/V2H group feature + + RZ/V2H block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware features for the board can be found at `RZV2H-EVK Website`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +By default, the board is configured for use with: + +SCI_UART +-------- + +* SCI_UART0: + + * TX = Pmod 3A pin 2 + * RX = Pmod 3A pin 3 + +LED +--- + +* LED5 (yelow) = P0_0 +* LED6 (yelow) = P0_1 + +Programming and Debugging (M33/R8) +********************************** + +.. zephyr:board-supported-runners:: + +Applications for the ``rzv2h_evk`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +Console +======= + +The UART port for Cortex-M33/Cortex-R8 System Core can be accessed by connecting `Pmod USBUART `_ +to the upper side of ``PMOD Type 3A``. + +Debugging +========= + +It is possible to load and execute a Zephyr application binary on +this board on the Cortex-M33/Cortex-R8 System Core from +the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`). + +Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application. + +**CM33:** + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rzv2h_evk/r9a09g057h44gbg/cm33 + :goals: build debug + +**CR8:** + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rzv2h_evk/r9a09g057h44gbg/cr8_0 + :goals: build debug + +Flashing +======== + +RZ/V2H-EVK is designed to start different systems on different cores. +It uses Yocto as the build system to build Linux system and boot loaders +to run Zephyr on Cortex-M33/Cortex-R8 with u-boot. The minimal steps are described below. + +1. Download Multi-OS Package from the `RZ/V2H Easy Download Guide`_ + +2. Unzip Multi-OS Package then open "r01qs0077ej****-rzv2h-multi-os-pkg" PDF file. + +3. Follow "3.2 Integration of Multi-OS Package related stuff" to build RZ/V2H AI SDK Source Code. + Uncomment the following lines in **meta-rz-features/meta-rz-multi-os/meta-rzv2h/conf/layer.conf**. + +.. code-block:: console + + #MACHINE_FEATURES_append = " RZV2H_CM33_BOOT" + MACHINE_FEATURES_append = " SRAM_REGION_ACCESS" + #MACHINE_FEATURES_append = " CM33_FIRMWARE_LOAD" + #MACHINE_FEATURES_append = " CA55_CPU_CLOCKUP" + +The below necessary artifacts will be located in the build/tmp/deploy/image + ++---------------+-------------------------------------------------+ +| Artifacts | File name | ++===============+=================================================+ +| Boot loader | bl2_bp_spi-rzv2h-evk-ver1.srec | +| | | +| | fip-rzv2h-evk-ver1.srec | ++---------------+-------------------------------------------------+ +| Flash Writer | Flash_Writer_SCIF_RZV2H_DEV_INTERNAL_MEMORY.mot | ++---------------+-------------------------------------------------+ +| SD card image | core-image-weston-rzv2h-evk-ver1.wic.bmap | +| | | +| | core-image-weston-rzv2h-evk-ver1.wic.gz | ++---------------+-------------------------------------------------+ + +4. Carry out 1-9 of Step "1-B Write the Linux files to SD card" at `Step 7 Deploy AI Application`_ to prepare SD card. + +5. Run the following commands to write **zephyr.bin** to SD card. + +.. code-block:: console + + $ sudo mkdir /mnt/sd -p + $ sudo mount /dev/sdb2 /mnt/sd + $ sudo cp /path/to/zephyr.bin /mnt/sd/boot + $ sync + $ sudo umount /mnt/sd + +.. warning:: + + Change ``/dev/sdb`` to your microSD card device name. Use ``dh -h`` to check. + +6. Insert the SD card into SD1 of RZ/V2H EVK, set up board at eSD mode (DSW1[4:5] = ON, OFF). + +7. Turn on the board carefully, see "3.2.2.4 Power Supply" in `Getting Started with Flexible Software Package`_ + Then, you should see the following message on the console associated with CN12 of RZ/V2H EVK. + +.. code-block:: console + + U-Boot 2021.10 (Jun 14 2024 - 18:14:19 +0000) + CPU: Renesas Electronics CPU rev 1.0 + Model: Renesas EVK Version 1 based on r9a09g057h4 + DRAM: 15.9 GiB + MMC: mmc@15c00000: 0, mmc@15c10000: 1(snip) + Net: eth0: ethernet@15c30000, eth1: ethernet@15c40000 + Hit any key to stop autoboot: 3 + +8. Hit any key within 3 sec to stop autoboot. + +9. Carry out the following setup of u-boot to kick CM33/CR8 Core. + +**CM33:** + +.. code-block:: console + + => setenv cm33start 'dcache off + => mw.l 0x10420D2C 0x02000000 + => mw.l 0x1043080c 0x08003000 + => mw.l 0x10430810 0x18003000 + => mw.l 0x10420604 0x00040004 + => mw.l 0x10420C1C 0x00003100 + => mw.l 0x10420C0C 0x00000001 + => mw.l 0x10420904 0x00380008 + => mw.l 0x10420904 0x00380038 + => ext4load mmc 0:2 0x08003000 boot/zephyr.bin + => mw.l 0x10420C0C 0x00000000 + => dcache on' + => saveenv + => run cm33start + +**CR8:** + +.. code-block:: console + + => setenv cr8start 'dcache off + => mw.l 0x10420D24 0x04000000 + => mw.l 0x10420600 0xE000E000 + => mw.l 0x10420604 0x00030003 + => mw.l 0x10420908 0x1FFF0000 + => mw.l 0x10420C44 0x003F0000 + => mw.l 0x10420C14 0x00000000 + => mw.l 0x10420908 0x10001000 + => mw.l 0x10420C48 0x00000020 + => mw.l 0x10420908 0x1FFF1FFF + => mw.l 0x10420C48 0x00000000 + => ext4load mmc 0:2 0x12040000 boot/zephyr.bin + => mw.l 0x10420C14 0x00000003 + => dcache on' + => saveenv + => run cr8start + +References +********** + +.. target-notes:: + +.. _RZ/V2H Easy Download Guide: + https://www.renesas.com/en/document/gde/rzv2h-easy-download-guide + +.. _Step 7 Deploy AI Application: + https://renesas-rz.github.io/rzv_ai_sdk/5.00/getting_started_v2h.html#step7 + +.. _Getting Started with Flexible Software Package: + https://www.renesas.com/en/document/apn/rzv-getting-started-flexible-software-package + +.. _RZV2H-EVK Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzv2h-evk-rzv2h-quad-core-vision-ai-mpu-evaluation-kit + +.. _RZ/V2H Group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzv2h-quad-core-vision-ai-mpu-drp-ai3-accelerator-and-high-performance-real-time-processor diff --git a/boards/renesas/rzv2h_evk/doc/rzv2h_block_diagram.webp b/boards/renesas/rzv2h_evk/doc/rzv2h_block_diagram.webp new file mode 100644 index 00000000000..dff3e77c9ae Binary files /dev/null and b/boards/renesas/rzv2h_evk/doc/rzv2h_block_diagram.webp differ diff --git a/boards/renesas/rzv2h_evk/doc/rzv2h_evk.webp b/boards/renesas/rzv2h_evk/doc/rzv2h_evk.webp new file mode 100644 index 00000000000..3bc82ed883f Binary files /dev/null and b/boards/renesas/rzv2h_evk/doc/rzv2h_evk.webp differ diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk-pinctrl.dtsi b/boards/renesas/rzv2h_evk/rzv2h_evk-pinctrl.dtsi new file mode 100644 index 00000000000..cb87c2794f5 --- /dev/null +++ b/boards/renesas/rzv2h_evk/rzv2h_evk-pinctrl.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ sci0_pins: sci0 { + sci0-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + drive-strength = <1>; + }; + }; +}; diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.dts b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.dts new file mode 100644 index 00000000000..e9714ad044b --- /dev/null +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.dts @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rzv2h_evk-pinctrl.dtsi" + +/ { + model = "Renesas RZ/V2H EVK"; + compatible = "renesas,rzv2h-evk"; + + aliases { + led0 = &led5; + led1 = &led6; + }; + + chosen { + zephyr,sram = &sram; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + + led5: led5 { + gpios = <&gpio0 0 0>; + label = "led5"; + }; + + led6: led6 { + gpios = <&gpio0 1 0>; + label = "led6"; + }; + }; + + ddr: memory@80000000 { + compatible = "mmio-sram"; + reg = <0x80000000 DT_SIZE_M(256)>; + }; + + sram: memory@8003000 { + compatible = "mmio-sram"; + reg = <0x08003000 0xfbfff>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_pins>; + pinctrl-names = "default"; + status = "okay"; + + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.yaml b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.yaml new file mode 100644 index 00000000000..9e45f21aa04 --- /dev/null +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33.yaml @@ -0,0 +1,11 @@ +identifier: rzv2h_evk/r9a09g057h44gbg/cm33 +name: Cortex-M33 for Renesas RZ/V2H EVK +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio +vendor: renesas diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33_defconfig b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33_defconfig new file mode 100644 index 00000000000..c9dd44d6c70 --- /dev/null +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cm33_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.dts b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.dts new file mode 100644 index 00000000000..ecad70dc716 --- /dev/null +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.dts @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "rzv2h_evk-pinctrl.dtsi" + +/ { + model = "Renesas RZ/V2H EVK"; + compatible = "renesas,rzv2h-evk"; + + aliases { + led0 = &led5; + led1 = &led6; + }; + + chosen { + zephyr,sram = &sram; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + + led5: led5 { + gpios = <&gpio0 0 0>; + label = "led5"; + }; + + led6: led6 { + gpios = <&gpio0 1 0>; + label = "led6"; + }; + }; + + sram: memory@0 { + compatible = "mmio-sram"; + reg = <0x0 DT_SIZE_M(256)>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_pins>; + pinctrl-names = "default"; + status = "okay"; + + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.yaml b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.yaml new file mode 100644 index 00000000000..1195932fbc8 --- /dev/null +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0.yaml @@ -0,0 +1,11 @@ +identifier: rzv2h_evk/r9a09g057h44gbg/cr8_0 +name: Cortex-R8 for Renesas RZ/V2H EVK +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio +vendor: renesas diff --git a/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0_defconfig b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0_defconfig new file mode 100644 index 00000000000..c5b3b483bf8 --- /dev/null +++ b/boards/renesas/rzv2h_evk/rzv2h_evk_r9a09g057h44gbg_cr8_0_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +# MPU Config +CONFIG_ARM_MPU=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y diff --git a/boards/renesas/rzv2n_evk/Kconfig.rzv2n_evk b/boards/renesas/rzv2n_evk/Kconfig.rzv2n_evk new file mode 100644 index 00000000000..847bf9d6aa0 --- /dev/null +++ b/boards/renesas/rzv2n_evk/Kconfig.rzv2n_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZV2N_EVK + select SOC_R9A09G056N48GBG_CM33 diff --git a/boards/renesas/rzv2n_evk/board.cmake b/boards/renesas/rzv2n_evk/board.cmake new file mode 100644 index 00000000000..f59e0d0ebf4 --- /dev/null +++ b/boards/renesas/rzv2n_evk/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R9A09G056N48_M33_0") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rzv2n_evk/board.yml b/boards/renesas/rzv2n_evk/board.yml new file mode 100644 index 00000000000..24b62784859 --- /dev/null +++ b/boards/renesas/rzv2n_evk/board.yml @@ -0,0 +1,6 @@ +board: + name: rzv2n_evk + full_name: RZ/V2N Evaluation Board Kit + vendor: renesas + socs: + - name: r9a09g056n48gbg diff --git a/boards/renesas/rzv2n_evk/doc/index.rst b/boards/renesas/rzv2n_evk/doc/index.rst new file mode 100644 index 00000000000..c88a6a3a594 --- /dev/null +++ b/boards/renesas/rzv2n_evk/doc/index.rst @@ -0,0 +1,219 @@ +.. zephyr:board:: rzv2n_evk + +Overview +******** + +The RZ/V2N is a vision AI microprocessor (MPU) with Renesas proprietary AI accelerator (DRP-AI3) +supporting up to 15TOPS AI performance. Its CPUs are quad Arm Cortex-A55 (1.8GHz) and Arm Cortex-M33 (200MHz). +The RZ/V2N is equipped with an ISP (Image Signal Processor) and dual-channel MIPI CSI-2 camera interfaces +for supporting dual camera signal processing, which is crucial for realizing vision systems. +It is also equipped with high-speed interfaces such as PCIe and USB 3.2, allowing for the expansion of external devices. +The RZ/V2N is an ideal microprocessor for applications requiring both low power consumption and advanced AI inference, +such as DMS (Driver Monitoring System), monitoring cameras, mobile robots, and more. + +* RZ/V2N Evaluation Board (CPU Board): + + * CPU: RZ/V2N + * PMIC: RAA215300 + * Clock generator: 5L35023B + * Main memory: LPDDR4X 8GB x1 + * xSPI Flash memory: 64MB + * External memory: microSD x1 + * Board-to-board connector for sub boards + * High-speed interface: + * Gigabit Ethernet x2 ports + * USB 3.2 Gen2 x1ch (Host only) + * USB 2.0 x1ch (OTG) + * PCIe Gen3 x1ch (2 lanes max) + * MIPI CSI-2 x2ch + * MIPI DSI x 1ch + * GPIO: 86 pins + +* RZ/V2H-EVK Expansion Board (EXP Board): Shared with RZ/V2H + + * HDMI Tx x1ch + * Audio auxiliary input connector x1ch + * Audio microphone input connector x1ch + * Audio headphone output connector x1ch + * Pmod x4 + +Hardware +******** + +The Renesas RZ/V2N documentation can be found at `RZ/V2N Group Website`_ + +.. figure:: rzv2n_block_diagram.webp + :width: 600px + :align: center + :alt: RZ/V2N group feature + + RZ/V2N block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware features for the board can be found at `RZV2N-EVK Website`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +By default, the board is configured for use with: + +SCI_UART +-------- + +* SCI_UART0: + + * TX = Pmod 3A pin 2 + * RX = Pmod 3A pin 3 + +LED +--- + +* LED5 (yelow) = P0_0 +* LED6 (yelow) = P0_1 + +Programming and Debugging (M33) +******************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``rzv2n_evk`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +Console +======= + +The UART port for Cortex-M33 System Core can be accessed by connecting `Pmod USBUART `_ +to the upper side of ``PMOD Type 3A``. + +Debugging +========= + +It is possible to load and execute a Zephyr application binary on +this board on the Cortex-M33 System Core from +the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`). + +Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rzv2n_evk/r9a09g056n48gbg/cm33 + :goals: build debug + +Flashing +======== + +RZ/V2N-EVK is designed to start different systems on different cores. +It uses Yocto as the build system to build Linux system and boot loaders +to run Zephyr on Cortex-M33 with u-boot. The minimal steps are described below. + +1. Download Multi-OS Package from the `RZ/V2N Group Handbook`_ + +2. Unzip Multi-OS Package then open "r01qs0078ej****-rzv2n-multi-os-pkg" PDF file. + +3. Follow "3.2 Integration of OpenAMP related stuff" to build RZ/V2N AI SDK Source Code. + Uncomment the following lines in **meta-rz-features/meta-rz-multi-os/meta-rzv2n/conf/layer.conf**. + +.. code-block:: console + + #MACHINE_FEATURES_append = " RZV2N_CM33_BOOT" + MACHINE_FEATURES_append = " SRAM_REGION_ACCESS" + #MACHINE_FEATURES_append = " CM33_FIRMWARE_LOAD" + #MACHINE_FEATURES_append = " CA55_CPU_CLOCKUP" + +The below necessary artifacts will be located in the build/tmp/deploy/image + ++---------------+-----------------------------------------+ +| Artifacts | File name | ++===============+=========================================+ +| Boot loader | bl2_bp_spi-rzv2n-evk.srec | +| | | +| | fip-rzv2n-evk.srec | ++---------------+-----------------------------------------+ +| Flash Writer | Flash_Writer_SCIF_RZV2N_DEV_LPDDR4X.mot | ++---------------+-----------------------------------------+ +| SD card image | core-image-weston-rzv2n-evk.wic.bmap | +| | | +| | core-image-weston-rzv2n-evk.wic.gz | ++---------------+-----------------------------------------+ + +4. Carry out 1-9 of Step "1-B Write the Linux files to SD card" at `Step 7 Deploy AI Application`_ to prepare SD card. + +5. Run the following commands to write **zephyr.bin** to SD card. + +.. code-block:: console + + $ sudo mkdir /mnt/sd -p + $ sudo mount /dev/sdb2 /mnt/sd + $ sudo cp /path/to/zephyr.bin /mnt/sd/boot + $ sync + $ sudo umount /mnt/sd + +.. warning:: + + Change ``/dev/sdb`` to your microSD card device name. Use ``dh -h`` to check. + +6. Insert the SD card into SD1 of RZ/V2N EVK, set up board at eSD mode (DSW1[4:5] = ON, OFF). + +7. Turn on the board carefully, see "3.3.2.4 Power Supply" in `Getting Started with Flexible Software Package`_ + Then, you should see the following message on the console associated with CN12 of RZ/V2N EVK. + +.. code-block:: console + + U-Boot 2021.10 (Sep 19 2024 - 10:13:55 +0000) + CPU: Renesas Electronics CPU rev 1.0 + Model: Renesas EVK based on r9a09g056 + DRAM: 7.9 GiB + MMC: mmc@15c00000: 0, mmc@15c10000: 1 + Loading Environment from SPIFlash... + SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB + OK + In: serial@11c01400 + Out: serial@11c01400 + Err: serial@11c01400 + Net: eth0: ethernet@15c30000 + Hit any key to stop autoboot: 3 + +8. Hit any key within 3 sec to stop autoboot. + +9. Carry out the following setup of u-boot to kick CM33 Core. + +.. code-block:: console + + => setenv cm33start 'dcache off + => mw.l 0x10420D2C 0x02000000 + => mw.l 0x1043080c 0x08003000 + => mw.l 0x10430810 0x18003000 + => mw.l 0x10420604 0x00040004 + => mw.l 0x10420C1C 0x00003100 + => mw.l 0x10420C0C 0x00000001 + => mw.l 0x10420904 0x00380008 + => mw.l 0x10420904 0x00380038 + => ext4load mmc 0:2 0x08003000 boot/zephyr.bin + => mw.l 0x10420C0C 0x00000000 + => dcache on' + => saveenv + => run cm33start + +References +********** + +.. target-notes:: + +.. _RZ/V2N Group Handbook: + https://www.renesas.com/en/document/gde/rzv2n-group-handbook + +.. _Step 7 Deploy AI Application: + https://renesas-rz.github.io/rzv_ai_sdk/5.10/getting_started_v2n.html#step7 + +.. _Getting Started with Flexible Software Package: + https://www.renesas.com/en/document/apn/rzv-getting-started-flexible-software-package + +.. _RZV2N-EVK Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzv2n-evk-rzv2n-quad-core-vision-ai-mpu-evaluation-kit + +.. _RZ/V2N Group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzv2n-15tops-quad-core-vision-ai-mpu-2-camera-connection-and-excellent-power-efficiency diff --git a/boards/renesas/rzv2n_evk/doc/rzv2n_block_diagram.webp b/boards/renesas/rzv2n_evk/doc/rzv2n_block_diagram.webp new file mode 100644 index 00000000000..be065cc3314 Binary files /dev/null and b/boards/renesas/rzv2n_evk/doc/rzv2n_block_diagram.webp differ diff --git a/boards/renesas/rzv2n_evk/doc/rzv2n_evk.webp b/boards/renesas/rzv2n_evk/doc/rzv2n_evk.webp new file mode 100644 index 00000000000..ed95dcb2c64 Binary files /dev/null and b/boards/renesas/rzv2n_evk/doc/rzv2n_evk.webp differ diff --git a/boards/renesas/rzv2n_evk/rzv2n_evk-pinctrl.dtsi b/boards/renesas/rzv2n_evk/rzv2n_evk-pinctrl.dtsi new file mode 100644 index 00000000000..bbd5d1f77b7 --- /dev/null +++ b/boards/renesas/rzv2n_evk/rzv2n_evk-pinctrl.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ sci0_pins: sci0 { + sci0-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + }; + }; +}; diff --git a/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.dts b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.dts new file mode 100644 index 00000000000..9f560ddf782 --- /dev/null +++ b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.dts @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rzv2n_evk-pinctrl.dtsi" + +/ { + model = "Renesas RZ/V2N EVK"; + compatible = "renesas,rzv2n-evk"; + + aliases { + led0 = &led5; + led1 = &led6; + }; + + chosen { + zephyr,sram = &sram; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + + led5: led5 { + gpios = <&gpio0 0 0>; + label = "led5"; + }; + + led6: led6 { + gpios = <&gpio0 1 0>; + label = "led6"; + }; + }; + + ddr: memory@80000000 { + compatible = "mmio-sram"; + reg = <0x80000000 DT_SIZE_M(256)>; + }; + + sram: memory@8003000 { + compatible = "mmio-sram"; + reg = <0x08003000 0xfbfff>; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_pins>; + pinctrl-names = "default"; + status = "okay"; + + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.yaml b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.yaml new file mode 100644 index 00000000000..7bdedda75f7 --- /dev/null +++ b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33.yaml @@ -0,0 +1,11 @@ +identifier: rzv2n_evk/r9a09g056n48gbg/cm33 +name: Cortex-M33 for Renesas RZ/V2N EVK +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio +vendor: renesas diff --git a/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33_defconfig b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33_defconfig new file mode 100644 index 00000000000..c9dd44d6c70 --- /dev/null +++ b/boards/renesas/rzv2n_evk/rzv2n_evk_r9a09g056n48gbg_cm33_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/voice_ra4e1/board.cmake b/boards/renesas/voice_ra4e1/board.cmake index 590f06a5743..a599fce2dd8 100644 --- a/boards/renesas/voice_ra4e1/board.cmake +++ b/boards/renesas/voice_ra4e1/board.cmake @@ -2,5 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=R7FA4E10D") +board_runner_args(pyocd "--target=R7FA4E10D") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ruiside/ra8d1_vision_board/Kconfig.defconfig b/boards/ruiside/ra8d1_vision_board/Kconfig.defconfig new file mode 100644 index 00000000000..1305f828c36 --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Shan Pen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RA8D1_VISION_BOARD + +if DISK_DRIVER_SDMMC + +config SD_CMD_TIMEOUT + default 1000 + +endif # DISK_DRIVER_SDMMC + +endif # BOARD_RA8D1_VISION_BOARD diff --git a/boards/ruiside/ra8d1_vision_board/Kconfig.ra8d1_vision_board b/boards/ruiside/ra8d1_vision_board/Kconfig.ra8d1_vision_board new file mode 100644 index 00000000000..79b9537d9c1 --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/Kconfig.ra8d1_vision_board @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Shan Pen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RA8D1_VISION_BOARD + select SOC_R7FA8D1BHECBD diff --git a/boards/ruiside/ra8d1_vision_board/board.cmake b/boards/ruiside/ra8d1_vision_board/board.cmake new file mode 100644 index 00000000000..50fa8d9c031 --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(pyocd "--target=R7FA8D1BH") + +# keep first +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/ruiside/ra8d1_vision_board/board.yml b/boards/ruiside/ra8d1_vision_board/board.yml new file mode 100644 index 00000000000..779834f7fe6 --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/board.yml @@ -0,0 +1,6 @@ +board: + name: ra8d1_vision_board + full_name: RA8D1 Vision Board + vendor: ruiside + socs: + - name: r7fa8d1bhecbd diff --git a/boards/ruiside/ra8d1_vision_board/doc/index.rst b/boards/ruiside/ra8d1_vision_board/doc/index.rst new file mode 100644 index 00000000000..9e7ff464e90 --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/doc/index.rst @@ -0,0 +1,96 @@ +.. zephyr:board:: ra8d1_vision_board + +Overview +******** + +The RA8D1-VISION-BOARD, based on the Renesas Cortex-M85 architecture RA8D1 chip, offers +engineers a flexible and comprehensive development platform, empowering them to explore the realm of +machine vision more deeply. + +Key Features + +- Arm Cortex-M85 +- 480MHz frequency, on-chip 2Mb Flash, 1Mb SRAM +- 32Mb-SDRAM; 8Mb-QSPI Flash +- MIPI-DSI; RGB666; 8bit Camera +- On-board DAP-LINK debugger with CMSIS-DAP +- Raspberry Pi Interface + +More information about the board can be found at the `RA8D1-VISION-BOARD website`_. + +Hardware +******** +Detailed Hardware features for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The RA8D1-VISION-BOARD board features a On-board CMSIS-DAP debugger/programmer. Board is configured as follows: + +- UART9 TX/RX : P209/P208 (CMSIS-DAP Virtual Port Com) +- LED0 : P102 +- LED1 : P106 +- LED2 : PA07 +- USER BUTTON : P907 + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``ra8d1_vision_board`` board can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available. +To build for RA8D1-VISION-BOARD user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6 + +Flashing +======== + +Program can be flashed to RA8D1-VISION-BOARD via the on-board DAP-LINK debugger. + +Linux users: to fix the permission issue, simply add the following udev rule for the +CMSIS-DAP interface: + +.. code-block:: console + + $ echo 'SUBSYSTEM=="usb", ATTR{idVendor}=="0416", ATTR{idProduct}=="7687", MODE:="666"' > /etc/udev/rules.d/50-cmsis-dap.rules + +To flash the program to board + +1. Connect to DAP-LINK via USB port to host PC + +2. Execute west command + + .. code-block:: console + + west flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ra8d1_vision_board + :maybe-skip-config: + :goals: debug + +References +********** +.. target-notes:: + +.. _RA8D1-VISION-BOARD Website: + https://github.com/RT-Thread-Studio/sdk-bsp-ra8d1-vision-board + +.. _RA8D1 Group User's Manual Hardware: + https://www.renesas.com/us/en/document/mah/ra8d1-group-users-manual-hardware diff --git a/boards/ruiside/ra8d1_vision_board/doc/ra8d1_vision_board.webp b/boards/ruiside/ra8d1_vision_board/doc/ra8d1_vision_board.webp new file mode 100644 index 00000000000..1c1dafef60c Binary files /dev/null and b/boards/ruiside/ra8d1_vision_board/doc/ra8d1_vision_board.webp differ diff --git a/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board-pinctrl.dtsi b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board-pinctrl.dtsi new file mode 100644 index 00000000000..d5de306a80a --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board-pinctrl.dtsi @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2025 Shan Pen + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci9_default: sci9_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + + group2 { + /* rx */ + psels = ; + }; + }; + + sdram_default: sdram_default { + group1 { + /* SDRAM_DQM1 */ + psels = , + /* SDRAM_CKE */ + , + /* SDRAM_WE */ + , + /* SDRAM_CS */ + , + /* SDRAM_A0 */ + , + /* SDRAM_A1 */ + , + /* SDRAM_A2 */ + , + /* SDRAM_A3 */ + , + /* SDRAM_A4 */ + , + /* SDRAM_A5 */ + , + /* SDRAM_A6 */ + , + /* SDRAM_A7 */ + , + /* SDRAM_A8 */ + , + /* SDRAM_A9 */ + , + /* SDRAM_A10 */ + , + /* SDRAM_A11 */ + , + /* SDRAM_A12 */ + , + /* SDRAM_A13 */ + , + /* SDRAM_A14 */ + , + /* SDRAM_A15 */ + , + /* SDRAM_D0 */ + , + /* SDRAM_D1 */ + , + /* SDRAM_D2 */ + , + /* SDRAM_D3 */ + , + /* SDRAM_D4 */ + , + /* SDRAM_D5 */ + , + /* SDRAM_D6 */ + , + /* SDRAM_D8 */ + , + /* SDRAM_D9 */ + , + /* SDRAM_D10 */ + , + /* SDRAM_D11 */ + , + /* SDRAM_D12 */ + , + /* SDRAM_D13 */ + , + /* SDRAM_D14 */ + , + /* SDRAM_RAS */ + , + /* SDRAM_CAS */ + ; + drive-strength = "high"; + }; + + group2 { + /* SDRAM_SDCLK */ + psels = ; + drive-strength = "highspeed-high"; + }; + + group3 { + /* SDRAM_D7 */ + psels = , + /* SDRAM_D15 */ + , + /* SDRAM_DQM0 */ + ; + drive-strength = "high"; + }; + }; + + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + ; /* SDDATA3 */ + drive-strength = "high"; + }; + + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; +}; diff --git a/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.dts b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.dts new file mode 100644 index 00000000000..e87f9eee310 --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.dts @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2025 Shan Pen + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "ra8d1_vision_board-pinctrl.dtsi" + +/ { + model = "Ruiside Electronic RA8D1-VISION-BOARD"; + compatible = "ruiside,ra8d1-vision-board"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart9; + zephyr,shell-uart = &uart9; + zephyr,entropy = &trng; + zephyr,flash-controller = &flash; + }; + + leds { + compatible = "gpio-leds"; + + led0: led0 { + gpios = <&ioport1 2 GPIO_ACTIVE_LOW>; + label = "LED0"; + }; + + led1: led1 { + gpios = <&ioport1 6 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioporta 7 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + user_button: button_0 { + gpios = <&ioport9 7 GPIO_ACTIVE_LOW>; + label = "User Button"; + zephyr,code = ; + }; + }; + + sdram1: sdram@68000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x68000000 DT_SIZE_M(32)>; + zephyr,memory-region = "SDRAM"; + status = "okay"; + }; + + aliases { + led0 = &led0; + sw0 = &user_button; + watchdog0 = &wdt; + sdhc0 = &sdhc1; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&subclk { + status = "okay"; +}; + +&pll { + status = "okay"; + + pllp { + status = "okay"; + }; + + pllq { + div = <4>; + freq = ; + status = "okay"; + }; + + pllr { + status = "okay"; + }; +}; + +&sciclk { + clocks = <&pllp>; + div = <4>; + status = "okay"; +}; + +&uclk { + clocks = <&pllq>; + div = <5>; + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&ioport5 { + status = "okay"; +}; + +&ioport6 { + status = "okay"; +}; + +&ioport8 { + status = "okay"; +}; + +&ioport9 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&sci9 { + pinctrl-0 = <&sci9_default>; + pinctrl-names = "default"; + status = "okay"; + + uart9: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&trng { + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(12)>; + }; + }; +}; + +&port_irq10 { + interrupts = <86 12>; + status = "okay"; +}; + +&sdram { + pinctrl-0 = <&sdram_default>; + pinctrl-names = "default"; + status = "okay"; + auto-refresh-interval = ; + auto-refresh-count = ; + precharge-cycle-count = ; + multiplex-addr-shift = "9-bit"; + edian-mode = "little-endian"; + continuous-access; + bus-width = "16-bit"; + + bank@0 { + reg = <0>; + renesas,ra-sdram-timing = ; + }; +}; + +&sdhc1 { + pinctrl-names = "default"; + interrupt-names = "accs", "card", "dma-req"; + interrupts = <60 12>, <61 12>, <62 12>; + pinctrl-0 = <&sdhc1_default>; + status = "okay"; + /delete-property/ card-detect; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + +&wdt { + status = "okay"; +}; diff --git a/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.yaml b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.yaml new file mode 100644 index 00000000000..682545a8b09 --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.yaml @@ -0,0 +1,15 @@ +identifier: ra8d1_vision_board +name: ra8d1 vision board +type: mcu +arch: arm +ram: 1024 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - uart + - watchdog + - memc +vendor: ruiside diff --git a/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board_defconfig b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board_defconfig new file mode 100644 index 00000000000..6a3a48ad85c --- /dev/null +++ b/boards/ruiside/ra8d1_vision_board/ra8d1_vision_board_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Shan Pen +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Console +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y diff --git a/boards/sc/scobc_a1/Kconfig.defconfig b/boards/sc/scobc_a1/Kconfig.defconfig new file mode 100644 index 00000000000..133b09b0d9a --- /dev/null +++ b/boards/sc/scobc_a1/Kconfig.defconfig @@ -0,0 +1,17 @@ +# SC-OBC Module A1 + +# Copyright (c) 2021 Space Cubics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SCOBC_A1 + +config CPU_CORTEX_M_HAS_SYSTICK + default y + +config CPU_HAS_ARM_MPU + default y + +config NUM_IRQS + default 32 + +endif # BOARD_SCOBC_A1 diff --git a/boards/sc/scobc_a1/Kconfig.scobc_a1 b/boards/sc/scobc_a1/Kconfig.scobc_a1 new file mode 100644 index 00000000000..7f77e0878ce --- /dev/null +++ b/boards/sc/scobc_a1/Kconfig.scobc_a1 @@ -0,0 +1,7 @@ +# SC-OBC Module A1 configuration + +# Copyright (c) 2021 Space Cubics, LLC. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SCOBC_A1 + select SOC_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/boards/sc/scobc_a1/board.cmake b/boards/sc/scobc_a1/board.cmake new file mode 100644 index 00000000000..da21e750556 --- /dev/null +++ b/boards/sc/scobc_a1/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/scobc-a1.cfg") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/sc/scobc_a1/board.yml b/boards/sc/scobc_a1/board.yml new file mode 100644 index 00000000000..45881e6617d --- /dev/null +++ b/boards/sc/scobc_a1/board.yml @@ -0,0 +1,12 @@ +board: + name: scobc_a1 + full_name: SC-OBC Module A1 + vendor: sc + revision: + format: major.minor.patch + default: 2.0.0 + revisions: + - name: 1.0.0 + - name: 2.0.0 + socs: + - name: designstart_fpga_cortex_m3 diff --git a/boards/sc/scobc_a1/doc/index.rst b/boards/sc/scobc_a1/doc/index.rst new file mode 100644 index 00000000000..c45b8dc62db --- /dev/null +++ b/boards/sc/scobc_a1/doc/index.rst @@ -0,0 +1,112 @@ +.. zephyr:board:: scobc_a1 + +Overview +******** + +`Space Cubics`_ OBC Module A1 (SC-OBC Module A1) is a single board computer for spacecraft, +especially for 3U CubeSats. The board is based on Xilinx Artix-7 FPGA and +implements ARM Cortex M3 as the main CPU. + +It is designed to survive in the severe space environment, extreme temperature, +vacuum, and space radiation. + +As the name suggests, the board form factor is a module and requires a base I/O +board connected at CON1, a board-to-board connector. This modularity allows +CubeSat designers the freedom to connect and expand the capability required for +their mission. + +Hardware +******** + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The board has two 24 MHz external oscillators connected to the FPGA for +redundancy. The FPGA will select an active oscillator as CPU system clock. The +selected clock signal is then used by the CMT in the FPGA, and drives the CPU at +48 MHz by default. + +Serial Port +=========== + +The default configuration contains one SC UART IP, which is register compatible +with Xilinx UART Lite for basic TX and RX. This UART is configured as the +default console and is accessible through the CON1 pin 43 and 45 for Rx and Tx, +respectively. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Here is an example for building and flashing the \`hello\_world\` +application for the board: + +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application +for the default design: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: scobc_a1 + :goals: flash + +After flashing, you should see message similar to the following in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-4619-gd571a59b0a43 *** + Hello World! scobc_a1/designstart_fpga_cortex_m3 + +Note, however, that the application was not persisted in flash memory by the +above steps. It was merely written to internal RAM in the FPGA. + +You can flash the board using an external debug adapter such as CMSIS-DAP, FT2232D, or FT232R. By +default, the SC-OBC Module A1 uses a CMSIS-DAP interface (e.g., Raspberry Pi Pico Debug Probe). +However, if you're using an adapter such as FT2232D or FT232R, specify the interface via the +``OPENOCD_INTERFACE`` environment variable before running ``west flash``. + +For example: + +.. code-block:: console + + $ export OPENOCD_INTERFACE=FT2232D + $ west flash + + $ export OPENOCD_INTERFACE=FT232R + $ west flash + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: scobc_a1 + :goals: debug + +Step through the application in your debugger, and you should see a message +similar to the following in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v4.1.0-4619-gd571a59b0a43 *** + Hello World! scobc_a1/designstart_fpga_cortex_m3 + +References +********** + +.. target-notes:: + +.. _Space Cubics: + https://spacecubics.com/ diff --git a/boards/sc/scobc_module1/doc/scobc.jpg b/boards/sc/scobc_a1/doc/scobc.jpg similarity index 100% rename from boards/sc/scobc_module1/doc/scobc.jpg rename to boards/sc/scobc_a1/doc/scobc.jpg diff --git a/boards/sc/scobc_module1/dts/bindings/sc,hrmem.yaml b/boards/sc/scobc_a1/dts/bindings/sc,hrmem.yaml similarity index 100% rename from boards/sc/scobc_module1/dts/bindings/sc,hrmem.yaml rename to boards/sc/scobc_a1/dts/bindings/sc,hrmem.yaml diff --git a/boards/sc/scobc_a1/dts/bindings/sc,sysmon.yaml b/boards/sc/scobc_a1/dts/bindings/sc,sysmon.yaml new file mode 100644 index 00000000000..49dcb7ad6cd --- /dev/null +++ b/boards/sc/scobc_a1/dts/bindings/sc,sysmon.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Space Cubics Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: SC-OBC Module A1 System Monitor + +compatible: "sc,sysmon" + +include: base.yaml + +properties: + reg: + required: true diff --git a/boards/sc/scobc_a1/dts/bindings/sc,sysreg.yaml b/boards/sc/scobc_a1/dts/bindings/sc,sysreg.yaml new file mode 100644 index 00000000000..1eef3bce9e9 --- /dev/null +++ b/boards/sc/scobc_a1/dts/bindings/sc,sysreg.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Space Cubics Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: SC-OBC Module A1 System Register + +compatible: "sc,sysreg" + +include: base.yaml + +properties: + reg: + required: true diff --git a/boards/sc/scobc_a1/scobc_a1.dts b/boards/sc/scobc_a1/scobc_a1.dts new file mode 100644 index 00000000000..118afb44316 --- /dev/null +++ b/boards/sc/scobc_a1/scobc_a1.dts @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Space Cubics, LLC. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "SC-OBC Module A1"; + + chosen { + zephyr,console = &uartlite0; + zephyr,shell-uart = &uartlite0; + zephyr,sram = &hrmem; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m3"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + hrmem: memory@0 { + compatible = "sc,hrmem"; + reg = <0x00000000 DT_SIZE_M(4)>; + }; + + uartlite0: uartlite@4f010000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + interrupts = <0 0>; + reg = <0x4f010000 0x10000>; + }; + + sysreg: sysreg@4f000000 { + compatible = "sc,sysreg"; + reg = <0x4f000000 0x10000>; + }; + + sysmon: sysmon@4f040000 { + compatible = "sc,sysmon"; + reg = <0x4f040000 0x1000>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/boards/sc/scobc_a1/scobc_a1.yaml b/boards/sc/scobc_a1/scobc_a1.yaml new file mode 100644 index 00000000000..c493d5e62e2 --- /dev/null +++ b/boards/sc/scobc_a1/scobc_a1.yaml @@ -0,0 +1,8 @@ +identifier: scobc_a1 +name: SC-OBC Module A1 +type: mcu +arch: arm +toolchain: + - zephyr +supported: + - uart diff --git a/boards/sc/scobc_a1/scobc_a1_1_0_0.overlay b/boards/sc/scobc_a1/scobc_a1_1_0_0.overlay new file mode 100644 index 00000000000..203040a0ebb --- /dev/null +++ b/boards/sc/scobc_a1/scobc_a1_1_0_0.overlay @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Space Cubics Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/delete-node/ &hrmem; +/delete-node/ &uartlite0; + +/ { + soc { + hrmem: memory@0 { + compatible = "sc,hrmem"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + + uartlite0: uartlite@50010000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + interrupts = <0 0>; + reg = <0x50010000 0x10000>; + }; + }; +}; diff --git a/boards/sc/scobc_module1/scobc_module1_defconfig b/boards/sc/scobc_a1/scobc_a1_defconfig similarity index 100% rename from boards/sc/scobc_module1/scobc_module1_defconfig rename to boards/sc/scobc_a1/scobc_a1_defconfig diff --git a/boards/sc/scobc_module1/support/akizuki-m-02990.cfg b/boards/sc/scobc_a1/support/akizuki-m-02990.cfg similarity index 100% rename from boards/sc/scobc_module1/support/akizuki-m-02990.cfg rename to boards/sc/scobc_a1/support/akizuki-m-02990.cfg diff --git a/boards/sc/scobc_a1/support/scobc-a1.cfg b/boards/sc/scobc_a1/support/scobc-a1.cfg new file mode 100644 index 00000000000..ab77552be5e --- /dev/null +++ b/boards/sc/scobc_a1/support/scobc-a1.cfg @@ -0,0 +1,52 @@ +# Copyright (C) 2025 Space Cubics Inc. + +if {[info exists env(OPENOCD_INTERFACE)]} { + set _INTERFACE $env(OPENOCD_INTERFACE) +} else { + # Default CMIS-DAP + set _INTERFACE "CMSIS-DAP" +} + +if { $_INTERFACE == "FT2232D" } { + source [find akizuki-m-02990.cfg] +} elseif { $_INTERFACE == "FT232R" } { + source [find interface/ft232r.cfg] +} else { + source [find interface/cmsis-dap.cfg] + source [find target/swj-dp.tcl] +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cortex_m3 +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +adapter speed 5000 + +if [using_swd] { + swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +} else { + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +} +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if {![using_hla]} { + cortex_m reset_config sysresetreq +} diff --git a/boards/sc/scobc_module1/Kconfig.defconfig b/boards/sc/scobc_module1/Kconfig.defconfig deleted file mode 100644 index 35aae169147..00000000000 --- a/boards/sc/scobc_module1/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Space Cubics OBC module 1 - -# Copyright (c) 2021 Space Cubics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SCOBC_MODULE1 - -config CPU_CORTEX_M_HAS_SYSTICK - default y - -config CPU_HAS_ARM_MPU - default y - -config NUM_IRQS - default 7 - -endif # BOARD_SCOBC_MODULE1 diff --git a/boards/sc/scobc_module1/Kconfig.scobc_module1 b/boards/sc/scobc_module1/Kconfig.scobc_module1 deleted file mode 100644 index d8a7a3e5ac7..00000000000 --- a/boards/sc/scobc_module1/Kconfig.scobc_module1 +++ /dev/null @@ -1,7 +0,0 @@ -# Space Cubics OBC module 1 configuration - -# Copyright (c) 2021 Space Cubics, LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SCOBC_MODULE1 - select SOC_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/boards/sc/scobc_module1/board.cmake b/boards/sc/scobc_module1/board.cmake deleted file mode 100644 index a0f4d5f5fed..00000000000 --- a/boards/sc/scobc_module1/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd-ftdi.cfg") - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/sc/scobc_module1/board.yml b/boards/sc/scobc_module1/board.yml deleted file mode 100644 index 02c931595cb..00000000000 --- a/boards/sc/scobc_module1/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: scobc_module1 - full_name: OBC module 1 - vendor: sc - socs: - - name: designstart_fpga_cortex_m3 diff --git a/boards/sc/scobc_module1/doc/index.rst b/boards/sc/scobc_module1/doc/index.rst deleted file mode 100644 index 264e27801ea..00000000000 --- a/boards/sc/scobc_module1/doc/index.rst +++ /dev/null @@ -1,111 +0,0 @@ -.. zephyr:board:: scobc_module1 - -Overview -******** - -`Space Cubics`_ OBC module 1 is a single board computer for spacecraft, -especially for 3U CubeSats. The board is based on Xilinx Artix-7 FPGA and -implements ARM Cortex M3 as the main CPU. - -It is designed to survive in the severe space environment, extreme temperature, -vacuum, and space radiation. - -As the name suggests, the board form factor is a module and requires a base I/O -board connected at CON1, a board-to-board connector. This modularity allows -CubeSat designers the freedom to connect and expand the capability required for -their mission. - -Hardware -******** - -Supported Features -================== - -The Space Cubics OBC module 1 provides the following hardware features: - -+-----------+------------+------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+------------------------------------+ - -The default configuration for the board can be found in the defconfig file: -:file:`boards/arm/scobc_module1/scobc_module1_defconfig`. - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The board has two 24 MHz external oscillators connected to the FPGA for -redundancy. The FPGA will select an active oscillator as CPU system clock. The -selected clock signal is then used by the CMT in the FPGA, and drives the CPU at -48 MHz by default. - -Serial Port -=========== - -The default configuration contains one SC UART IP, which is register compatible -with Xilinx UART Lite for basic TX and RX. This UART is configured as the -default console and is accessible through the CON1 pin 43 and 45 for Rx and Tx, -respectively. - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Flashing -======== - -Here is an example for building and flashing the \`hello\_world\` -application for the board: - -Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application -for the default design: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: scobc_module1 - :goals: flash - -After flashing, you should see message similar to the following in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.7.99 *** - Hello World! scobc_module1 - -Note, however, that the application was not persisted in flash memory by the -above steps. It was merely written to internal RAM in the FPGA. - -Debugging -========= - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: scobc_module1 - :goals: debug - -Step through the application in your debugger, and you should see a message -similar to the following in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.7.99 *** - Hello World! scobc_module1 - -References -********** - -.. target-notes:: - -.. _Space Cubics: - https://spacecubics.com/ diff --git a/boards/sc/scobc_module1/scobc_module1.dts b/boards/sc/scobc_module1/scobc_module1.dts deleted file mode 100644 index 3f704e1113d..00000000000 --- a/boards/sc/scobc_module1/scobc_module1.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2021 Space Cubics, LLC. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include - -/ { - model = "Space Cubics OBC module 1"; - - chosen { - zephyr,console = &uartlite0; - zephyr,shell-uart = &uartlite0; - zephyr,sram = &hrmem; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-m3"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - mpu: mpu@e000ed90 { - compatible = "arm,armv7m-mpu"; - reg = <0xe000ed90 0x40>; - }; - }; - }; - - soc { - hrmem: memory@0 { - compatible = "sc,hrmem"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - - uartlite0: uartlite@50010000 { - compatible = "xlnx,xps-uartlite-1.00.a"; - interrupts = <0 0>; - reg = <0x50010000 0x10000>; - }; - }; -}; - -&nvic { - arm,num-irq-priority-bits = <3>; -}; diff --git a/boards/sc/scobc_module1/scobc_module1.yaml b/boards/sc/scobc_module1/scobc_module1.yaml deleted file mode 100644 index c7d16760a31..00000000000 --- a/boards/sc/scobc_module1/scobc_module1.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: scobc_module1 -name: Space Cubics OBC module 1 -type: mcu -arch: arm -toolchain: - - zephyr -supported: - - uart diff --git a/boards/sc/scobc_module1/support/openocd-ft232r.cfg b/boards/sc/scobc_module1/support/openocd-ft232r.cfg deleted file mode 100644 index ccdcd2b68d6..00000000000 --- a/boards/sc/scobc_module1/support/openocd-ft232r.cfg +++ /dev/null @@ -1,2 +0,0 @@ -source [find interface/ft232r.cfg] -source [find scobc-module1.cfg] diff --git a/boards/sc/scobc_module1/support/openocd-ftdi.cfg b/boards/sc/scobc_module1/support/openocd-ftdi.cfg deleted file mode 100644 index 14d6ef55b76..00000000000 --- a/boards/sc/scobc_module1/support/openocd-ftdi.cfg +++ /dev/null @@ -1,3 +0,0 @@ -source [find akizuki-m-02990.cfg] -adapter speed 2000 -source [find scobc-module1.cfg] diff --git a/boards/sc/scobc_module1/support/openocd.cfg b/boards/sc/scobc_module1/support/openocd.cfg deleted file mode 100644 index bfd27c5b491..00000000000 --- a/boards/sc/scobc_module1/support/openocd.cfg +++ /dev/null @@ -1,21 +0,0 @@ -source [find interface/cmsis-dap.cfg] -transport select swd -source [find target/swj-dp.tcl] - -adapter speed 5000 - -set _CHIPNAME cortex_m3 -set _ENDIAN little -set _WORKAREASIZE 0x4000 -set _CPUTAPID 0x412FC231 - -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -if {![using_hla]} { - cortex_m reset_config sysresetreq -} diff --git a/boards/sc/scobc_module1/support/scobc-module1.cfg b/boards/sc/scobc_module1/support/scobc-module1.cfg deleted file mode 100644 index aad20e5e5cc..00000000000 --- a/boards/sc/scobc_module1/support/scobc-module1.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright (C) 2021 Space Cubics, LLC. -# Yasushi SHOJI - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME cortex_m3 -} - -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -if {![using_hla]} { - cortex_m reset_config sysresetreq -} diff --git a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts index f3df8911ee8..8c81c2638fc 100644 --- a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts @@ -168,7 +168,7 @@ stm32_lp_tick_source: &lptim1 { /* connectors: */ grove_serial: &usart1 {}; -grove_i2c: &i2c2 {}; +zephyr_i2c: &i2c2 {}; &flash0 { partitions { diff --git a/boards/seeed/wio_terminal/grove_connectors.dtsi b/boards/seeed/wio_terminal/grove_connectors.dtsi index c8c213ac79a..51e68061daf 100644 --- a/boards/seeed/wio_terminal/grove_connectors.dtsi +++ b/boards/seeed/wio_terminal/grove_connectors.dtsi @@ -22,4 +22,4 @@ }; }; -grove_i2c1: &sercom3 {}; +zephyr_i2c: &sercom3 {}; diff --git a/boards/seeed/xiao_ble/xiao_ble_common.dtsi b/boards/seeed/xiao_ble/xiao_ble_common.dtsi index 7b87b6db76f..47c3b300ae1 100644 --- a/boards/seeed/xiao_ble/xiao_ble_common.dtsi +++ b/boards/seeed/xiao_ble/xiao_ble_common.dtsi @@ -44,7 +44,6 @@ led1 = &led1; led2 = &led2; pwm-led0 = &pwm_led0; - bootloader-led0 = &led0; mcuboot-led0 = &led0; watchdog0 = &wdt0; }; diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.dts b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.dts index 4789d7ccf76..e859eca809e 100644 --- a/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.dts +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.dts @@ -22,6 +22,7 @@ zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; }; leds: leds { @@ -80,3 +81,11 @@ &wifi { status = "okay"; }; + +&ieee802154 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.yaml b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.yaml index 7108d35e997..58f0e27949b 100644 --- a/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.yaml +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.yaml @@ -16,6 +16,8 @@ supported: - xiao_i2c - xiao_serial - xiao_spi + - netif:openthread + testing: ignore_tags: - bluetooth diff --git a/boards/seeed/xiao_mg24/Kconfig.xiao_mg24 b/boards/seeed/xiao_mg24/Kconfig.xiao_mg24 index 441384dd416..86aaf2c14fa 100644 --- a/boards/seeed/xiao_mg24/Kconfig.xiao_mg24 +++ b/boards/seeed/xiao_mg24/Kconfig.xiao_mg24 @@ -4,4 +4,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_XIAO_MG24 - select SOC_PART_NUMBER_EFR32MG24B220F1536IM48 + select SOC_EFR32MG24B220F1536IM48 diff --git a/boards/seeed/xiao_mg24/xiao_mg24-pinctrl.dtsi b/boards/seeed/xiao_mg24/xiao_mg24-pinctrl.dtsi index a1930b8e78b..8eb12a18c53 100644 --- a/boards/seeed/xiao_mg24/xiao_mg24-pinctrl.dtsi +++ b/boards/seeed/xiao_mg24/xiao_mg24-pinctrl.dtsi @@ -1,10 +1,11 @@ /* * Copyright (c) 2025 Pete Johanson + * Copyright (c) 2025 Silicon Laboratories Inc. * * SPDX-License-Identifier: Apache-2.0 */ -#include +#include &pinctrl { eusart0_default: eusart0_default { @@ -56,4 +57,12 @@ bias-pull-up; }; }; + + timer0_default: timer0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; }; diff --git a/boards/seeed/xiao_mg24/xiao_mg24.dts b/boards/seeed/xiao_mg24/xiao_mg24.dts index 86181585bcb..c0235a95ded 100644 --- a/boards/seeed/xiao_mg24/xiao_mg24.dts +++ b/boards/seeed/xiao_mg24/xiao_mg24.dts @@ -1,11 +1,13 @@ /* * Copyright (c) 2025 Pete Johanson + * Copyright (c) 2025 Silicon Laboratories Inc. * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; #include +#include #include "xiao_mg24-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" @@ -26,6 +28,7 @@ /* These aliases are provided for compatibility with samples */ aliases { led0 = &led0; + pwm-led0 = &pwm_led0; watchdog0 = &wdog0; }; @@ -37,6 +40,25 @@ label = "LED 0"; }; }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "PWM LED 0"; + }; + }; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; }; &cpu0 { @@ -119,7 +141,6 @@ }; &gpio { - location-swo = <0>; status = "okay"; }; @@ -176,15 +197,15 @@ read-only; }; - /* Reserve 720 kB for the application in slot 0 */ + /* Reserve 736 kB for the application in slot 0 */ slot0_partition: partition@c000 { reg = <0x0000c000 0x000B8000>; label = "image-0"; }; - /* Reserve 720 kB for the application in slot 1 */ + /* Reserve 736 kB for the application in slot 1 */ slot1_partition: partition@C4000 { - reg = <0x000C0000 0x000B8000>; + reg = <0x000C4000 0x000B8000>; label = "image-1"; }; diff --git a/boards/seeed/xiao_nrf54l15/Kconfig.defconfig b/boards/seeed/xiao_nrf54l15/Kconfig.defconfig new file mode 100644 index 00000000000..dd9a6feb90e --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Seeed Technology Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 +if BOARD_XIAO_NRF54L15_NRF54L15_CPUAPP + +config HAS_BT_CTLR + default BT + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +endif # BOARD_XIAO_NRF54L15_NRF54L15_CPUAPP diff --git a/boards/seeed/xiao_nrf54l15/Kconfig.xiao_nrf54l15 b/boards/seeed/xiao_nrf54l15/Kconfig.xiao_nrf54l15 new file mode 100644 index 00000000000..bd54b0bb79a --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/Kconfig.xiao_nrf54l15 @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Seeed Technology Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 +config BOARD_XIAO_NRF54L15 + select SOC_NRF54L15_CPUAPP if BOARD_XIAO_NRF54L15_NRF54L15_CPUAPP + select SOC_NRF54L15_CPUFLPR if \ + BOARD_XIAO_NRF54L15_NRF54L15_CPUFLPR || \ + BOARD_XIAO_NRF54L15_NRF54L15_CPUFLPR_XIP diff --git a/boards/seeed/xiao_nrf54l15/board.cmake b/boards/seeed/xiao_nrf54l15/board.cmake new file mode 100644 index 00000000000..a762e80d16d --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/board.cmake @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54L15_CPUAPP) + board_runner_args(openocd "--cmd-load=nrf54l-load" -c "targets nrf54l.cpu") + board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000") +elseif(CONFIG_SOC_NRF54L15_CPUFLPR) + board_runner_args(openocd "--cmd-load=nrf54l-load" -c "targets nrf54l.aux") + board_runner_args(jlink "--device=nRF54L15_RV32") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) \ No newline at end of file diff --git a/boards/seeed/xiao_nrf54l15/board.yml b/boards/seeed/xiao_nrf54l15/board.yml new file mode 100644 index 00000000000..8641807b8e1 --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/board.yml @@ -0,0 +1,9 @@ +board: + name: xiao_nrf54l15 + full_name: XIAO NRF54L15 + vendor: seeed + socs: + - name: nrf54l15 + variants: + - name: xip + cpucluster: cpuflpr diff --git a/boards/seeed/xiao_nrf54l15/doc/index.rst b/boards/seeed/xiao_nrf54l15/doc/index.rst new file mode 100644 index 00000000000..911574fff9c --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/doc/index.rst @@ -0,0 +1,106 @@ +.. zephyr:board:: xiao_nrf54l15 + +Overview +******** + +`Seeed Studio XIAO nRF54L15`_ is a compact, high-performance development board featuring the cutting-edge +Nordic nRF54L15 chip. This next-generation SoC integrates an ultra-low power multiprotocol 2.4 GHz +radio and an MCU with a 128 MHz Arm® Cortex®-M33 processor and an Arm® Cortex®-M0+ for advanced +power management. It offers scalable memory up to 1.5 MB NVM and 256 KB RAM. +Designed for exceptional ultra-low power consumption, it significantly extends battery life. +Its robust radio supports Bluetooth® 6.0 (including Channel Sounding), Matter, Thread, Zigbee, +and a high-throughput 2.4 GHz proprietary mode (up to 4 Mbps). + +The board includes a comprehensive set of peripherals, an integrated 128 MHz RISC-V coprocessor, +and advanced security features like TrustZone® isolation and cryptographic engine protection. +With built-in lithium battery management, XIAO nRF54L15 is ideal for compact, secure, +and energy-efficient IoT solutions such as smart wearables, industrial sensors, and advanced human-machine interfaces. + + +Hardware +******** + +- 128 MHz Arm® Cortex®-M33 processor +- Scalable memory configurations up to 1.5 MB NVM and up to 256 KB RAM +- Multiprotocol 2.4 GHz radio supporting Bluetooth Low Energy, 802.15.4-2020, + and 2.4 GHz proprietary modes (up to 4 Mbps) +- Comprehensive set of peripherals including new Global RTC available in System OFF, + 14-bit ADC, and high-speed serial interfaces +- 128 MHz RISC-V coprocessor +- Advanced security including TrustZone® isolation, tamper detection, + and cryptographic engine side-channel leakage protection + + +For more information about the nRF54L15 SoC and XIAO nRF54L15 board, refer to these +documents: + +- `nRF54L15 Website`_ +- `nRF54L15 Datasheet`_ +- `XIAO nRF54L15 Wiki`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, P2_0 +means Pin number 0 on PORT2, as used in the board's datasheets and manuals. + ++-------+-------------+------------------+ +| Name | Function | Usage | ++=======+=============+==================+ +| P2_0 | GPIO | LED0 | ++-------+-------------+------------------+ +| P1_9 | USART20_TX | UART Console TX | ++-------+-------------+------------------+ +| P1_8 | USART20_RX | UART Console RX | ++-------+-------------+------------------+ + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +The XIAO nRF54L15 contains a SAMD11 with CMSIS-DAP, allowing flashing, debugging, logging, etc. over +the USB port. + +Flashing +======== + +Connect the XIAO nRF54L15 board to your host computer using the USB port. A USB CDC ACM serial port +should appear on the host, that can be used to view logs from the flashed application. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_nrf54l15 + :goals: flash + +Open a serial terminal (minicom, putty, etc.) connecting to the UCB CDC ACM serial port. + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! xiao_nrf54l15 + + +.. _Seeed Studio XIAO nRF54L15: + https://www.seeedstudio.com/XIAO-nRF54L15-Sense-p-6494 + +.. _XIAO nRF54L15 Wiki: + https://wiki.seeedstudio.com/getting_started_with_xiao_nrf54l15/ + +.. _nRF54L15 Website: + https://www.nordicsemi.com/Products/nRF54L15 + +.. _nRF54L15 Datasheet: + https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/keyfeatures_html5.html + +.. _OpenOCD Arduino: + https://github.com/arduino/OpenOCD diff --git a/boards/seeed/xiao_nrf54l15/doc/xiao_nrf54l15.webp b/boards/seeed/xiao_nrf54l15/doc/xiao_nrf54l15.webp new file mode 100644 index 00000000000..5cf6aa6ed42 Binary files /dev/null and b/boards/seeed/xiao_nrf54l15/doc/xiao_nrf54l15.webp differ diff --git a/boards/seeed/xiao_nrf54l15/pre_dt_board.cmake b/boards/seeed/xiao_nrf54l15/pre_dt_board.cmake new file mode 100644 index 00000000000..8a1f7e61396 --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/pre_dt_board.cmake @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 +# Suppress "unique_unit_address_if_enabled" to handle some overlaps +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/seeed/xiao_nrf54l15/seeed_xiao_connector.dtsi b/boards/seeed/xiao_nrf54l15/seeed_xiao_connector.dtsi new file mode 100644 index 00000000000..959079090de --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/seeed_xiao_connector.dtsi @@ -0,0 +1,28 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + xiao_d: connector { + compatible = "seeed,xiao-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 4 0>, /* D0 */ + <1 0 &gpio1 5 0>, /* D1 */ + <2 0 &gpio1 6 0>, /* D2 */ + <3 0 &gpio1 7 0>, /* D3 */ + <4 0 &gpio1 10 0>, /* D4 */ + <5 0 &gpio1 11 0>, /* D5 */ + <6 0 &gpio2 8 0>, /* D6 */ + <7 0 &gpio2 7 0>, /* D7 */ + <8 0 &gpio2 1 0>, /* D8 */ + <9 0 &gpio2 4 0>, /* D9 */ + <10 0 &gpio2 2 0>; /* D10 */ + }; +}; + +xiao_i2c: &i2c22 {}; +xiao_spi: &spi00 {}; +xiao_serial: &uart21 {}; +xiao_adc: &adc {}; diff --git a/boards/seeed/xiao_nrf54l15/support/openocd.cfg b/boards/seeed/xiao_nrf54l15/support/openocd.cfg new file mode 100644 index 00000000000..82f6bb5f25b --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/support/openocd.cfg @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: Apache-2.0 + +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the CMSIS-DAP interface + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +set _CHIPNAME nrf54l + +# Work-area is a space in RAM used for flash programming, by default use 16 KiB. +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +# Multidrop instance ID should be configurable by FW in TAD TINSTANCE register. +# Writes to the register are ignored due to a silicon erratum. +if { [info exists SWD_INSTANCE_ID] } { + set _SWD_INSTANCE_ID $SWD_INSTANCE_ID +} else { + set _SWD_INSTANCE_ID 0 +} + +transport select swd + +swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +if { [info exists SWD_MULTIDROP] } { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x001c0289 -instance-id $_SWD_INSTANCE_ID +} else { + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0 + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# Create target for the AUX access port (AUX-AP). +target create $_CHIPNAME.aux mem_ap -dap $_CHIPNAME.dap -ap-num 1 + +# AUX-AP is accessible only if CSW Prot[0] bit (Data Access) is set +$_CHIPNAME.dap apsel 1 +$_CHIPNAME.dap apcsw 0x01000000 0x01000000 + +adapter speed 1000 + +# Use main processor as default target. +targets $_TARGETNAME + +if {![using_hla]} { + $_TARGETNAME cortex_m reset_config sysresetreq +} + +proc nrf54l-load {file} { + mww 0x5004b500 0x101 + load_image $file +} \ No newline at end of file diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15-pinctrl.dtsi b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15-pinctrl.dtsi new file mode 100644 index 00000000000..0161931a64c --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15-pinctrl.dtsi @@ -0,0 +1,114 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = ; + }; + + group2 { + psels = ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart21_default: uart21_default { + group1 { + psels = ; + }; + + group2 { + psels = ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart21_sleep: uart21_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ i2c22_default: i2c22_default { + group1 { + psels = , + ; + }; + }; + + /omit-if-no-ref/ i2c22_sleep: i2c22_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ i2c30_default: i2c30_default { + group1 { + psels = , + ; + }; + }; + + /omit-if-no-ref/ i2c30_sleep: i2c30_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi22_default: spi22_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi22_sleep: spi22_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + pdm20_default: pdm20_default { + group1 { + psels = , + ; + }; + }; +}; diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_common.dtsi b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_common.dtsi new file mode 100644 index 00000000000..595cc808c63 --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_common.dtsi @@ -0,0 +1,166 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "xiao_nrf54l15-pinctrl.dtsi" +#include + +/ { + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + }; + + buttons: buttons { + compatible = "gpio-keys"; + + usr_btn: usr-btn { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "USR"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + buttons = &buttons; + dmic20 = &pdm20; + sw0 = &usr_btn; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart21 { + current-speed = <115200>; + pinctrl-0 = <&uart21_default>; + pinctrl-1 = <&uart21_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c22 { + pinctrl-0 = <&i2c22_default>; + pinctrl-1 = <&i2c22_sleep>; + pinctrl-names = "default", "sleep"; + clock-frequency = <400000>; +}; + +&i2c30 { + pinctrl-0 = <&i2c30_default>; + pinctrl-1 = <&i2c30_sleep>; + pinctrl-names = "default", "sleep"; + clock-frequency = <400000>; +}; + +&spi00 { + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi22 { + pinctrl-0 = <&spi22_default>; + pinctrl-1 = <&spi22_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pdm20 { + pinctrl-0 = <&pdm20_default>; + pinctrl-names = "default"; + clock-source = "PCLK32M"; +}; + +&adc { + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <12>; + zephyr,oversampling = <8>; + }; + + channel@1 { + reg = <1>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <12>; + zephyr,oversampling = <8>; + }; + + channel@2 { + reg = <2>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <12>; + zephyr,oversampling = <8>; + }; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <12>; + zephyr,oversampling = <8>; + }; + + channel@4 { + reg = <4>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <12>; + zephyr,oversampling = <8>; + }; + + channel@5 { + reg = <5>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <12>; + zephyr,oversampling = <8>; + }; + + channel@6 { + reg = <6>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <12>; + zephyr,oversampling = <8>; + }; + + channel@7 { + reg = <7>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,input-positive = ; + zephyr,resolution = <12>; + zephyr,oversampling = <8>; + }; +}; diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.dts b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.dts new file mode 100644 index 00000000000..85124713b17 --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.dts @@ -0,0 +1,148 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "seeed_xiao_connector.dtsi" +#include "xiao_nrf54l15_common.dtsi" + +/ { + model = "Seeed XIAO nRF54L15"; + compatible = "seeed,xiao-nrf54l15-cpuapp"; + + pdm_imu_pwr: pdm-imu-pwr { + compatible = "regulator-fixed"; + regulator-name = "pdm-imu-pwr"; + enable-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + startup-delay-us = <5000>; + }; + + rfsw_ctl: rfsw-ctl { + compatible = "regulator-fixed"; + regulator-name = "rfsw-ctl"; + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + }; + + rfsw_pwr: rfsw-pwr { + compatible = "regulator-fixed"; + regulator-name = "rfsw-pwr"; + enable-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + }; + + vbat_pwr: vbat-pwr { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + enable-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + zephyr,flash = &cpuapp_rram; + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + nordic,rpc-uart = &uart20; + }; + + aliases { + imu0 = &lsm6dso; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&uart20 { + status = "okay"; +}; + +&uart21 { + status = "okay"; +}; + +&i2c22 { + status = "okay"; +}; + +&i2c30 { + status = "okay"; + + lsm6dso: lsm6dso@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + irq-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + accel-pm = ; + gyro-pm = ; + status = "okay"; + }; +}; + +&spi00 { + status = "okay"; +}; + +dmic_dev: &pdm20 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&gpio0 { + status = "okay"; + + imu_power_default_on: imu_power_default_on { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "imu-power-enable"; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +®ulators { + status = "okay"; +}; + +&vregmain { + status = "okay"; + regulator-initial-mode = ; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <16000>; + status = "okay"; +}; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.yaml b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.yaml new file mode 100644 index 00000000000..bc9602413b5 --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp.yaml @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Seeed Technology Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +identifier: xiao_nrf54l15/nrf54l15/cpuapp +name: XIAO nRF54L15 +vendor: seeed +arch: arm +toolchain: + - zephyr +sysbuild: true +ram: 188 +flash: 1428 +supported: + - adc + - counter + - dmic + - gpio + - i2c + - pwm + - retained_mem + - spi + - watchdog + - i2s + - xiao_gpio + - xiao_i2c + - xiao_spi + - xiao_serial + - xiao_adc diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp_defconfig b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp_defconfig new file mode 100644 index 00000000000..842c2c6d5a8 --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuapp_defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2025 Seeed Technology Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_PM_DEVICE=y +CONFIG_NRFX_POWER=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_INIT_PRIORITY=45 diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.dts b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.dts new file mode 100644 index 00000000000..42d316aaa48 --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.dts @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2025 Seeed Technology Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "xiao_nrf54l15_common.dtsi" + +/ { + model = "Seeed XIAO nRF54L15"; + compatible = "seeed,xiao-nrf54l15-cpuflpr"; + + chosen { + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_rram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&cpuflpr_sram { + status = "okay"; + /* size must be increased due to booting from SRAM */ + reg = <0x20028000 DT_SIZE_K(96)>; + ranges = <0x0 0x20028000 0x18000>; +}; + +&cpuflpr_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(96)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.yaml b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.yaml new file mode 100644 index 00000000000..23b75fd4ba1 --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Seeed Technology Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +identifier: xiao_nrf54l15/nrf54l15/cpuflpr +name: XIAO nRF54L15 +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 96 +flash: 96 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr_defconfig b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr_defconfig new file mode 100644 index 00000000000..743d365496a --- /dev/null +++ b/boards/seeed/xiao_nrf54l15/xiao_nrf54l15_nrf54l15_cpuflpr_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Seeed Technology Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n + +# Use internal LFCLK +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040_defconfig b/boards/seeed/xiao_rp2040/xiao_rp2040_defconfig index ef4e863884a..e382af25445 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040_defconfig +++ b/boards/seeed/xiao_rp2040/xiao_rp2040_defconfig @@ -1,6 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_RESET=y # Enable UART driver diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts index 04993ff48f3..48538044e9a 100644 --- a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts @@ -30,7 +30,7 @@ reg = <0x0>; status = "okay"; - reset-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; microchip,interface-type = "rgmii"; }; diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts index 04993ff48f3..48538044e9a 100644 --- a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts @@ -30,7 +30,7 @@ reg = <0x0>; status = "okay"; - reset-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; microchip,interface-type = "rgmii"; }; diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.dts b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.dts index b587927127c..3ef730a681f 100644 --- a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.dts +++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.dts @@ -41,7 +41,7 @@ reg = <0x0b>; status = "okay"; - reset-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; microchip,interface-type = "rgmii"; }; diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.dts b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.dts index b587927127c..3ef730a681f 100644 --- a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.dts +++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.dts @@ -41,7 +41,7 @@ reg = <0x0b>; status = "okay"; - reset-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; microchip,interface-type = "rgmii"; }; diff --git a/boards/shields/adafruit_aw9523/adafruit_aw9523.overlay b/boards/shields/adafruit_aw9523/adafruit_aw9523.overlay index 1b3ea5550e3..1498c9c9a0b 100644 --- a/boards/shields/adafruit_aw9523/adafruit_aw9523.overlay +++ b/boards/shields/adafruit_aw9523/adafruit_aw9523.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -&stemma_qt_i2c { +&zephyr_i2c { status = "okay"; adafruit_aw9523: aw9523b@58 { diff --git a/boards/shields/adafruit_featherwing_128x32_oled/Kconfig.defconfig b/boards/shields/adafruit_featherwing_128x32_oled/Kconfig.defconfig new file mode 100644 index 00000000000..0492383d3af --- /dev/null +++ b/boards/shields/adafruit_featherwing_128x32_oled/Kconfig.defconfig @@ -0,0 +1,30 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_ADAFRUIT_FEATHERWING_128X32_OLED + +if DISPLAY + +if LVGL + +config LV_Z_VDB_SIZE + default 64 + +config LV_DPI_DEF + default 148 + +config LV_Z_BITS_PER_PIXEL + default 1 + +config LV_Z_COLOR_MONO_HW_INVERSION + default y + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_1 +endchoice + +endif # LVGL + +endif # DISPLAY + +endif # SHIELD_ADAFRUIT_FEATHERWING_128X32_OLED diff --git a/boards/shields/adafruit_featherwing_128x32_oled/Kconfig.shield b/boards/shields/adafruit_featherwing_128x32_oled/Kconfig.shield new file mode 100644 index 00000000000..4443030aef2 --- /dev/null +++ b/boards/shields/adafruit_featherwing_128x32_oled/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_FEATHERWING_128X32_OLED + def_bool $(shields_list_contains,adafruit_featherwing_128x32_oled) diff --git a/boards/shields/adafruit_featherwing_128x32_oled/adafruit_featherwing_128x32_oled.overlay b/boards/shields/adafruit_featherwing_128x32_oled/adafruit_featherwing_128x32_oled.overlay new file mode 100644 index 00000000000..585d214847e --- /dev/null +++ b/boards/shields/adafruit_featherwing_128x32_oled/adafruit_featherwing_128x32_oled.overlay @@ -0,0 +1,55 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,display = &ssd1306_ssd1306_128x32; + }; + + aliases { + sw0 = &buttonA; + }; + + buttons { + compatible = "gpio-keys"; + + buttonA: button_A { + gpios = <&feather_header 16 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; /* D9 */ + label = "Button A"; + zephyr,code = ; + }; + + buttonB: button_B { + /* Button B has a pull up resistor on board. */ + gpios = <&feather_header 15 GPIO_ACTIVE_LOW>; /* D6 */ + label = "Button B"; + zephyr,code = ; + }; + + buttonC: button_C { + gpios = <&feather_header 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; /* D5 */ + label = "Button C"; + zephyr,code = ; + }; + }; +}; + +&feather_i2c { + ssd1306_ssd1306_128x32: ssd1306@3c { + compatible = "solomon,ssd1306fb"; + reg = <0x3c>; + width = <128>; + height = <32>; + segment-offset = <0>; + page-offset = <0>; + display-offset = <0>; + multiplex-ratio = <31>; + segment-remap; + com-invdir; + com-sequential; + prechargep = <0x22>; + }; +}; diff --git a/boards/shields/adafruit_featherwing_128x32_oled/doc/index.rst b/boards/shields/adafruit_featherwing_128x32_oled/doc/index.rst new file mode 100644 index 00000000000..b8bb0367c76 --- /dev/null +++ b/boards/shields/adafruit_featherwing_128x32_oled/doc/index.rst @@ -0,0 +1,47 @@ +.. _adafruit_featherwing_128x32_oled: + +Adafruit FeatherWing 128x32 OLED Shield +####################################### + +Overview +******** + +The `Adafruit OLED FeatherWing Shield`_ features a SSD1306 compatible OLED display +with a resolution of 128x32 pixels and three user buttons. + +Pins Assignment of the Adafruit FeatherWing 128x32 OLED shield +============================================================== + ++-----------------------+---------------------------------------------+ +| Shield Connector Pin | Function | ++=======================+=============================================+ +| SDA | SSD1306 I2C SDA | ++-----------------------+---------------------------------------------+ +| SCL | SSD1306 I2C SCL | ++-----------------------+---------------------------------------------+ +| GPIO5 | Button C (INPUT_KEY_C) | ++-----------------------+---------------------------------------------+ +| GPIO6 | Button B (INPUT_KEY_B) | ++-----------------------+---------------------------------------------+ +| GPIO9 | Button A (INPUT_KEY_A) | ++-----------------------+---------------------------------------------+ + +Requirements +************ + +This shield can only be used with a board which provides a configuration for Feather connector and +defines a node alias for I2C (see :ref:`shields` for more details). + +Programming +*********** + +Set ``--shield adafruit_featherwing_128x32_oled`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/display/lvgl + :board: adafruit_feather_nrf52840 + :shield: adafruit_featherwing_128x32_oled + :goals: build + +.. _Adafruit OLED FeatherWing Shield: + https://learn.adafruit.com/adafruit-oled-featherwing diff --git a/boards/shields/adafruit_featherwing_128x32_oled/shield.yml b/boards/shields/adafruit_featherwing_128x32_oled/shield.yml new file mode 100644 index 00000000000..2eac3c35c21 --- /dev/null +++ b/boards/shields/adafruit_featherwing_128x32_oled/shield.yml @@ -0,0 +1,7 @@ +shields: + - name: adafruit_featherwing_128x32_oled + full_name: Adafruit FeatherWing 128x32 OLED + vendor: adafruit + supported_features: + - display + - input diff --git a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf index 27961f09f2f..2d53a5fd9c1 100644 --- a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf +++ b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf @@ -6,3 +6,4 @@ CONFIG_STM32_LTDC_RGB565=y CONFIG_DISPLAY_INIT_PRIORITY=87 CONFIG_STM32_LTDC_DISABLE_FMC_BANK1=y CONFIG_INPUT_GT911_INTERRUPT=y +CONFIG_INPUT_GT911_MAX_TOUCH_POINTS=5 diff --git a/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay b/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay index 96c84cbfb43..10f47dbe529 100644 --- a/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay +++ b/boards/shields/arduino_modulino_buttons/arduino_modulino_buttons.overlay @@ -7,7 +7,7 @@ #include #include -&qwiic_i2c { +&zephyr_i2c { modulino-buttons@3e { compatible = "i2c-device"; reg = <0x3e>; diff --git a/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay b/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay index 8873c1312bb..f7081719dfb 100644 --- a/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay +++ b/boards/shields/arduino_modulino_smartleds/arduino_modulino_smartleds.overlay @@ -12,7 +12,7 @@ }; }; -&qwiic_i2c { +&zephyr_i2c { modulino_smartleds: modulino-smartleds@36 { compatible = "arduino,modulino-smartleds"; reg = <0x36>; diff --git a/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/Kconfig.shield b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/Kconfig.shield new file mode 100644 index 00000000000..6d096438795 --- /dev/null +++ b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_EK_RA8D1_RTK7EKA6M3B00001BU + def_bool $(shields_list_contains,ek_ra8d1_rtk7eka6m3b00001bu) diff --git a/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/img/bottom.webp b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/img/bottom.webp new file mode 100644 index 00000000000..287f773ba7c Binary files /dev/null and b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/img/bottom.webp differ diff --git a/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/img/top.webp b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/img/top.webp new file mode 100644 index 00000000000..b57c499cf8a Binary files /dev/null and b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/img/top.webp differ diff --git a/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/index.rst b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/index.rst new file mode 100644 index 00000000000..e7f48f6a065 --- /dev/null +++ b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/doc/index.rst @@ -0,0 +1,46 @@ +.. _ek_ra8d1_rtk7eka6m3b00001bu: + +EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter +############################################## + +Overview +******** + +The EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter is an open-source hardware converter PCB that +adapts the EK-RA8D1 Parallel Graphics Expansion Port (J57) to the RTK7EKA6M3B00001BU display +shield. + +.. figure:: img/top.webp + :align: center + :alt: EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter (top) + :width: 300 + + EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter (top) + +.. figure:: img/bottom.webp + :align: center + :alt: EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter (bottom) + :width: 300 + + EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter (bottom) + +Programming +*********** + +Set ``--shield ek_ra8d1_rtk7eka6m3b00001bu`` when you invoke ``west build``. +This shield is just a converter, so it is usually used with RTK7EKA6M3B00001BU shield. + +For example, + +.. zephyr-app-commands:: + :zephyr-app: tests/drivers/display/display_read_write + :board: ek_ra8d1 + :shield: ek_ra8d1_rtk7eka6m3b00001bu,rtk7eka6m3b00001bu + :goals: build + +References +********** +- `EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter`_ + +.. _EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter: + https://oshpark.com/shared_projects/pzfp0mCD diff --git a/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/ek_ra8d1_rtk7eka6m3b00001bu.overlay b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/ek_ra8d1_rtk7eka6m3b00001bu.overlay new file mode 100644 index 00000000000..6fcb994d2cf --- /dev/null +++ b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/ek_ra8d1_rtk7eka6m3b00001bu.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + lcd_expansion_rtk7eka6m3b00001bu: parallel-graphics-connector { + compatible = "renesas,ra-parallel-graphics-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <5 0 &ek_ra8d1_parallel_graphics_expansion 4 0>, /* IIC_SCL */ + <21 0 &ek_ra8d1_parallel_graphics_expansion 2 0>, /* IIC_SDA */ + <35 0 &ek_ra8d1_parallel_graphics_expansion 6 0>, /* DISP_RST */ + <38 0 &ek_ra8d1_parallel_graphics_expansion 3 0>, /* DISP_INT */ + <39 0 &ek_ra8d1_parallel_graphics_expansion 1 0>; /* DISP_BLEN */ + }; +}; diff --git a/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/shield.yml b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/shield.yml new file mode 100644 index 00000000000..7c444ab63f5 --- /dev/null +++ b/boards/shields/ek_ra8d1_rtk7eka6m3b00001bu/shield.yml @@ -0,0 +1,6 @@ +shield: + name: ek_ra8d1_rtk7eka6m3b00001bu + full_name: EK-RA8D1 to RTK7EKA6M3B00001BU Display Adapter + vendor: renesas + supported_features: + - display diff --git a/boards/shields/esp_8266/boards/numaker_m55m1.overlay b/boards/shields/esp_8266/boards/numaker_m55m1.overlay new file mode 100644 index 00000000000..0ed221f6235 --- /dev/null +++ b/boards/shields/esp_8266/boards/numaker_m55m1.overlay @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2025 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart8_esp8266: uart8_esp8266 { + group0 { + pinmux = , + , + , + ; + }; + }; +}; + +&uart8 { + status = "okay"; + current-speed = <115200>; + hw-flow-control; + + pinctrl-0 = <&uart8_esp8266>; + pinctrl-names = "default"; + + esp8266: esp8266 { + compatible = "espressif,esp-at"; + reset-gpios = <&gpiod 2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&gpiod { + status = "okay"; +}; + +&gpioi { + status = "okay"; +}; + +&gpioj { + status = "okay"; +}; diff --git a/boards/shields/eval_ad4052_ardz/doc/index.rst b/boards/shields/eval_ad4052_ardz/doc/index.rst index 771920affdc..8123277f471 100644 --- a/boards/shields/eval_ad4052_ardz/doc/index.rst +++ b/boards/shields/eval_ad4052_ardz/doc/index.rst @@ -9,6 +9,10 @@ Overview The EVAL-AD4052-ARDZ is a 16-Bit SAR ADC Arduino shield powered by the Analog Devices AD4052. +.. figure:: eval_ad4052_ardz.webp + :align: center + :alt: EVAL-AD4052-ARDZ + Programming *********** diff --git a/boards/shields/eval_adxl362_ardz/doc/index.rst b/boards/shields/eval_adxl362_ardz/doc/index.rst index e14f708f3f1..3412e43ce77 100644 --- a/boards/shields/eval_adxl362_ardz/doc/index.rst +++ b/boards/shields/eval_adxl362_ardz/doc/index.rst @@ -9,6 +9,10 @@ Overview The EVAL-ADXL362-ARDZ is a 3-axis digital accelerometer Arduino shield powered by the Analog Devices ADXL362. +.. figure:: eval_adxl362_ardz.webp + :align: center + :alt: EVAL-ADXL362-ARDZ + Programming *********** diff --git a/boards/shields/eval_adxl367_ardz/doc/index.rst b/boards/shields/eval_adxl367_ardz/doc/index.rst index e144b28ecfe..65bf3cb66b1 100644 --- a/boards/shields/eval_adxl367_ardz/doc/index.rst +++ b/boards/shields/eval_adxl367_ardz/doc/index.rst @@ -9,6 +9,10 @@ Overview The EVAL-ADXL367-ARDZ is a 3-axis digital accelerometer Arduino shield powered by the Analog Devices ADXL367. +.. figure:: eval_adxl367_ardz.webp + :align: center + :alt: EVAL-ADXL367-ARDZ + Programming *********** diff --git a/boards/shields/eval_adxl372_ardz/doc/index.rst b/boards/shields/eval_adxl372_ardz/doc/index.rst index b4210d2d9ca..03e35f1b416 100644 --- a/boards/shields/eval_adxl372_ardz/doc/index.rst +++ b/boards/shields/eval_adxl372_ardz/doc/index.rst @@ -9,6 +9,10 @@ Overview The EVAL-ADXL372-ARDZ is a 3-axis digital accelerometer Arduino shield powered by the Analog Devices ADXL372. +.. figure:: eval_adxl372_ardz.webp + :align: center + :alt: EVAL-ADXL372-ARDZ + Programming *********** diff --git a/boards/shields/g1120b0mipi/g1120b0mipi.overlay b/boards/shields/g1120b0mipi/g1120b0mipi.overlay index 48b724ea588..9201348f0a2 100644 --- a/boards/shields/g1120b0mipi/g1120b0mipi.overlay +++ b/boards/shields/g1120b0mipi/g1120b0mipi.overlay @@ -20,6 +20,7 @@ lvgl_pointer { compatible = "zephyr,lvgl-pointer-input"; input = <&ft3267_g1120b0mipi>; + display = <&rm67162_g1120b0mipi>; invert-y; }; }; diff --git a/boards/shields/ls0xx_generic/doc/index.rst b/boards/shields/ls0xx_generic/doc/index.rst index 665aaa07180..30c8f5d8beb 100644 --- a/boards/shields/ls0xx_generic/doc/index.rst +++ b/boards/shields/ls0xx_generic/doc/index.rst @@ -63,10 +63,8 @@ for LS013B7DH03. Other shields can be added by using the LS013B7DH03 as a reference and changing the width, height, etc configurations. LS012B7DD01 -LS012B7DD06 LS013B7DH03 LS013B7DH05 -LS013B7DH06 LS027B7DH01A LS032B7DD02 LS044Q7DH01 diff --git a/boards/shields/mikroe_h_bridge_4_click/Kconfig.shield b/boards/shields/mikroe_h_bridge_4_click/Kconfig.shield new file mode 100644 index 00000000000..76f6c0f2f90 --- /dev/null +++ b/boards/shields/mikroe_h_bridge_4_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Jilay Sandeep Pandya +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_H_BRIDGE_4_CLICK + def_bool $(shields_list_contains,mikroe_h_bridge_4_click) diff --git a/boards/shields/mikroe_h_bridge_4_click/doc/h-bridge-4-click.webp b/boards/shields/mikroe_h_bridge_4_click/doc/h-bridge-4-click.webp new file mode 100644 index 00000000000..fea30d8411d Binary files /dev/null and b/boards/shields/mikroe_h_bridge_4_click/doc/h-bridge-4-click.webp differ diff --git a/boards/shields/mikroe_h_bridge_4_click/doc/index.rst b/boards/shields/mikroe_h_bridge_4_click/doc/index.rst new file mode 100644 index 00000000000..7216d08246e --- /dev/null +++ b/boards/shields/mikroe_h_bridge_4_click/doc/index.rst @@ -0,0 +1,37 @@ +.. _mikroe_h_bridge_4_click_shield: + +MikroElektronika H Bridge 4 Click +################################# + +Overview +******** + +H-Bridge 4 Click is a Click board™ that contains the AP1010AEN, which is a two channel H-Bridge +motor driver compatible with a motor operating voltage up to 18V and can drive two DC motors or +one stepper motor. The protection circuit has under voltage lockout circuit, thermal shutdown +circuit, and overcurrent protection circuit, and overcurrent protection circuit can be disabled +with the DIS OCP terminal. + +H-Bridge 4 click supports multiple connection options and can be used in different application +setups which might include DC or Stepper motors. + +.. figure:: h-bridge-4-click.webp + :align: center + :alt: MikroElektronika H Bridge 4 Click + + MikroElektronika H Bridge 4 Click (Credit: MikroElektronika) + +Requirements +************ + +This shield can be used with a board that defines the ``mikrobus_header`` node label (see +:ref:`shields` for more details). + +Programming +*********** + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/stepper/generic + :board: + :west-args: --shield mikroe_h_bridge_4_click + :goals: build flash diff --git a/boards/shields/mikroe_h_bridge_4_click/mikroe_h_bridge_4_click.overlay b/boards/shields/mikroe_h_bridge_4_click/mikroe_h_bridge_4_click.overlay new file mode 100644 index 00000000000..953280a470e --- /dev/null +++ b/boards/shields/mikroe_h_bridge_4_click/mikroe_h_bridge_4_click.overlay @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Jilay Sandeep Pandya + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + mikroe_h_bridge_4_click: h_bridge_4_click { + status = "okay"; + compatible = "zephyr,h-bridge-stepper"; + + en-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + gpios = <&mikrobus_header 0 GPIO_ACTIVE_LOW>, /* IN1 */ + <&mikrobus_header 1 GPIO_ACTIVE_LOW>, /* IN2 */ + <&mikrobus_header 6 GPIO_ACTIVE_LOW>, /* IN3 */ + <&mikrobus_header 7 GPIO_ACTIVE_LOW>; /* IN4 */ + + }; +}; diff --git a/boards/shields/mikroe_h_bridge_4_click/shield.yml b/boards/shields/mikroe_h_bridge_4_click/shield.yml new file mode 100644 index 00000000000..2ecbf167f18 --- /dev/null +++ b/boards/shields/mikroe_h_bridge_4_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_h_bridge_4_click + full_name: H Bridge 4 Click + vendor: mikroe + supported_features: + - stepper diff --git a/boards/shields/mikroe_stepper_18_click/Kconfig.shield b/boards/shields/mikroe_stepper_18_click/Kconfig.shield new file mode 100644 index 00000000000..267be0d1f2a --- /dev/null +++ b/boards/shields/mikroe_stepper_18_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Navimatix GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_STEPPER_18_CLICK + def_bool $(shields_list_contains,mikroe_stepper_18_click) diff --git a/boards/shields/mikroe_stepper_18_click/doc/index.rst b/boards/shields/mikroe_stepper_18_click/doc/index.rst new file mode 100644 index 00000000000..3fc3cb9100f --- /dev/null +++ b/boards/shields/mikroe_stepper_18_click/doc/index.rst @@ -0,0 +1,48 @@ +.. _mikroe_stepper_18_click_shield: + +MikroElektronika Stepper 18 Click +################################# + +Overview +******** + +Stepper 18 Click shield has a TI DRV426 stepper driver accessed via GPIO. +It also features a Microchip MCP4726 DAC to allow for current control. The +micro-step pins are controlled via physical switches, making them unavailable +in Zephyr. +The DRV8426 uses the work-queue timing source by default. + +Note that the MCP4726 is compatible with the MCP4725 driver. + +More information about the shield can be found at +`Mikroe Stepper 18 click`_. + +.. figure:: stepper_18_click.webp + :align: center + :alt: MikroElektronika Stepper 18 Click + + MikroElektronika Stepper 18 Click (Credit: MikroElektronika) + +Requirements +************ + +The shield uses a mikroBUS interface. The target board must define +a ``mikrobus_i2c`` and ``mikrobus_header`` node labels +(see :ref:`shields` for more details). + +Programming +*********** + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/stepper/generic/ + :board: + :shield: mikroe_stepper_18_click + :goals: build flash + +References +********** + +.. target-notes:: + +.. _Mikroe Stepper 18 click: + https://www.mikroe.com/stepper-18-click diff --git a/boards/shields/mikroe_stepper_18_click/doc/stepper_18_click.webp b/boards/shields/mikroe_stepper_18_click/doc/stepper_18_click.webp new file mode 100644 index 00000000000..0da2202834b Binary files /dev/null and b/boards/shields/mikroe_stepper_18_click/doc/stepper_18_click.webp differ diff --git a/boards/shields/mikroe_stepper_18_click/mikroe_stepper_18_click.overlay b/boards/shields/mikroe_stepper_18_click/mikroe_stepper_18_click.overlay new file mode 100644 index 00000000000..69534c7e48e --- /dev/null +++ b/boards/shields/mikroe_stepper_18_click/mikroe_stepper_18_click.overlay @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 Navimatix GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + stepper = &drv8426_mikroe_stepper_18_click; + }; +}; + +&mikrobus_i2c { + status = "okay"; + + mcp4726_mikroe_stepper_18_click: mcp4726@70 { + status = "okay"; + compatible = "microchip,mcp4725"; + reg = < 0x60 >; + + #io-channel-cells = <1>; + }; +}; + +/ { + drv8426_mikroe_stepper_18_click: drv8426 { + status = "okay"; + compatible = "ti,drv84xx"; + + dir-gpios = <&mikrobus_header 0 0>; + step-gpios = <&mikrobus_header 6 0>; + sleep-gpios = <&mikrobus_header 1 GPIO_ACTIVE_LOW>; + en-gpios = <&mikrobus_header 2 0>; + fault-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/boards/shields/mikroe_stepper_18_click/shield.yml b/boards/shields/mikroe_stepper_18_click/shield.yml new file mode 100644 index 00000000000..af0497fdac3 --- /dev/null +++ b/boards/shields/mikroe_stepper_18_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_stepper_18_click + full_name: Stepper 18 Click + vendor: mikroe + supported_features: + - stepper diff --git a/boards/shields/mikroe_stepper_19_click/Kconfig.shield b/boards/shields/mikroe_stepper_19_click/Kconfig.shield new file mode 100644 index 00000000000..75e39aaa93f --- /dev/null +++ b/boards/shields/mikroe_stepper_19_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Navimatix GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_STEPPER_19_CLICK + def_bool $(shields_list_contains,mikroe_stepper_19_click) diff --git a/boards/shields/mikroe_stepper_19_click/doc/index.rst b/boards/shields/mikroe_stepper_19_click/doc/index.rst new file mode 100644 index 00000000000..42fd0d42fa6 --- /dev/null +++ b/boards/shields/mikroe_stepper_19_click/doc/index.rst @@ -0,0 +1,47 @@ +.. _mikroe_stepper_19_click_shield: + +MikroElektronika Stepper 19 Click +################################# + +Overview +******** + +The MikroElektronika `Stepper 19 Click`_ shield has a `TI DRV8424`_ stepper driver accessed via +GPIO and a `NXP PCA9538A`_ GPIO expander accessed via I2C. Some DRV8424 pins are accessed +via the GPIO expander. + +.. figure:: stepper_19_click.webp + :align: center + :alt: MikroElektronika Stepper 19 Click + + MikroElektronika Stepper 19 Click (Credit: MikroElektronika) + +Requirements +************ + +The shield uses a mikroBUS interface. The target board must define +a ``mikrobus_i2c`` and ``mikrobus_header`` node labels +(see :ref:`shields` for more details). + +Programming +*********** + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/stepper/generic/ + :board: + :shield: mikroe_stepper_19_click + :goals: build flash + +References +********** + +.. target-notes:: + +.. _Stepper 19 Click: + https://www.mikroe.com/stepper-19-click + +.. _TI DRV8424: + https://www.ti.com/product/DRV8424 + +.. _NXP PCA9538A: + https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/general-purpose-i-o-gpio/low-voltage-8-bit-ic-bus-i-o-port-with-interrupt-and-reset:PCA9538A diff --git a/boards/shields/mikroe_stepper_19_click/doc/stepper_19_click.webp b/boards/shields/mikroe_stepper_19_click/doc/stepper_19_click.webp new file mode 100644 index 00000000000..337fab7a664 Binary files /dev/null and b/boards/shields/mikroe_stepper_19_click/doc/stepper_19_click.webp differ diff --git a/boards/shields/mikroe_stepper_19_click/mikroe_stepper_19_click.overlay b/boards/shields/mikroe_stepper_19_click/mikroe_stepper_19_click.overlay new file mode 100644 index 00000000000..df5b9a73b0f --- /dev/null +++ b/boards/shields/mikroe_stepper_19_click/mikroe_stepper_19_click.overlay @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2025 Navimatix GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + stepper = &drv8424_mikroe_stepper_19_click; + }; +}; + +&mikrobus_i2c { + status = "okay"; + + pca9538a_mikroe_stepper_19_click: pca9538a@70 { + status = "okay"; + compatible = "nxp,pca9538"; + + reg = <0x70>; + + gpio-controller; + ngpios = <8>; + #gpio-cells = <2>; + + gpio-reserved-ranges = <7 1>; + + gpio-line-names = + "M0", + "M1", + "DEC0", + "DEC1", + "TOFF", + "STP", + "DIR"; + }; +}; + +/ { + drv8424_mikroe_stepper_19_click: drv8424 { + status = "okay"; + compatible = "ti,drv84xx"; + + dir-gpios = <&mikrobus_header 0 0>; + step-gpios = <&mikrobus_header 6 0>; + sleep-gpios = <&mikrobus_header 1 GPIO_ACTIVE_LOW>; + en-gpios = <&mikrobus_header 2 0>; + fault-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; + m0-gpios = <&pca9538a_mikroe_stepper_19_click 0 0>; + m1-gpios = <&pca9538a_mikroe_stepper_19_click 1 0>; + }; +}; diff --git a/boards/shields/mikroe_stepper_19_click/shield.yml b/boards/shields/mikroe_stepper_19_click/shield.yml new file mode 100644 index 00000000000..c55e8d10588 --- /dev/null +++ b/boards/shields/mikroe_stepper_19_click/shield.yml @@ -0,0 +1,6 @@ +shield: + name: mikroe_stepper_19_click + full_name: Stepper 19 Click + vendor: mikroe + supported_features: + - stepper diff --git a/boards/shields/nrf7002eb/doc/index.rst b/boards/shields/nrf7002eb/doc/index.rst index 85079cdefef..637f91ae21b 100644 --- a/boards/shields/nrf7002eb/doc/index.rst +++ b/boards/shields/nrf7002eb/doc/index.rst @@ -36,7 +36,7 @@ below to retrieve those files. .. code-block:: console west update - west blobs fetch hal_nordic + west blobs fetch nrf_wifi Usage ***** diff --git a/boards/shields/nrf7002ek/doc/index.rst b/boards/shields/nrf7002ek/doc/index.rst index 2c55e34c1d8..b79556967a6 100644 --- a/boards/shields/nrf7002ek/doc/index.rst +++ b/boards/shields/nrf7002ek/doc/index.rst @@ -36,7 +36,7 @@ below to retrieve those files. .. code-block:: console west update - west blobs fetch hal_nordic + west blobs fetch nrf_wifi Usage ***** diff --git a/boards/shields/nxp_adtja1101/Kconfig.shield b/boards/shields/nxp_adtja1101/Kconfig.shield new file mode 100644 index 00000000000..82ae3931b4c --- /dev/null +++ b/boards/shields/nxp_adtja1101/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_NXP_ADTJA1101 + def_bool $(shields_list_contains,nxp_adtja1101) diff --git a/boards/shields/nxp_adtja1101/doc/img/adtja1101-rmii.webp b/boards/shields/nxp_adtja1101/doc/img/adtja1101-rmii.webp new file mode 100644 index 00000000000..23ab5895806 Binary files /dev/null and b/boards/shields/nxp_adtja1101/doc/img/adtja1101-rmii.webp differ diff --git a/boards/shields/nxp_adtja1101/doc/index.rst b/boards/shields/nxp_adtja1101/doc/index.rst new file mode 100644 index 00000000000..48174a02aa6 --- /dev/null +++ b/boards/shields/nxp_adtja1101/doc/index.rst @@ -0,0 +1,35 @@ +.. _nxp_adtja1101: + +NXP ADTJA1101-RMII Automotive Ethernet Adapter +############################################## + +Overview +******** + +The ADTJA1101-RMII is an automotive Ethernet adapter card specifically built to +add 100Mbps automotive Ethernet connectivity to the S32K148 Microcontroller and +i.MX8 platforms. + +This shield can be used with the NXP S32K148-Q176 evaluation board by plugging +into the common expansion connector, through which the ADTJA1101-RMII connects +the RMII interfaces of the S32K148 directly to NXP’s 100BASE-T1 Ethernet PHY +TJA1101. + +.. figure:: img/adtja1101-rmii.webp + :align: center + :alt: NXP ADTJA1101-RMII Automotive Ethernet Adapter + +More information about this module can be found at `ADTJA1101-RMII`_. + +Programming +*********** + +Set ``--shield nxp_adtja1101`` when you invoke ``west build``. + +References +********** + +.. target-notes:: + +.. _ADTJA1101-RMII: + https://www.nxp.com/part/ADTJA1101-RMII diff --git a/boards/shields/nxp_adtja1101/nxp_adtja1101.overlay b/boards/shields/nxp_adtja1101/nxp_adtja1101.overlay new file mode 100644 index 00000000000..589efd17c7e --- /dev/null +++ b/boards/shields/nxp_adtja1101/nxp_adtja1101.overlay @@ -0,0 +1,20 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&enet_mac { + status = "okay"; + phy-handle = <&phy>; +}; + +&enet_mdio { + status = "okay"; + + phy: phy@0 { + compatible = "nxp,tja11xx"; + reg = <0>; + status = "okay"; + }; +}; diff --git a/boards/shields/nxp_adtja1101/shield.yml b/boards/shields/nxp_adtja1101/shield.yml new file mode 100644 index 00000000000..d6777ebf464 --- /dev/null +++ b/boards/shields/nxp_adtja1101/shield.yml @@ -0,0 +1,6 @@ +shield: + name: nxp_adtja1101 + full_name: NXP ADTJA1101-RMII Automotive Ethernet Adapter + vendor: nxp + supported_features: + - ethernet diff --git a/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig b/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig index 79692b8f2e2..3efd1552628 100644 --- a/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig +++ b/boards/shields/nxp_m2_wifi_bt/Kconfig.defconfig @@ -16,6 +16,12 @@ if WIFI config WIFI_NXP default y +config WIFI_NM_WPA_SUPPLICANT_11AX + default n + +config WIFI_NM_WPA_SUPPLICANT_11AC + default n + choice NXP_WIFI_PART default NXP_IW416 endchoice @@ -24,6 +30,13 @@ choice NXP_IW416_MODULE default NXP_IW416_MURATA_1XK_M2 endchoice +if WIFI_NM_HOSTAPD_AP + +config WIFI_NM_HOSTAPD_REGULATORY_REGION + default "WW" + +endif # WIFI_NM_HOSTAPD_AP + endif # WIFI endif # SHIELD_NXP_M2_1XK_WIFI_BT @@ -51,11 +64,69 @@ choice NXP_IW61X_MODULE default NXP_IW612_MURATA_2EL_M2 endchoice +if WIFI_NM_HOSTAPD_AP + +config WIFI_NM_HOSTAPD_REGULATORY_REGION + default "WW" + +endif # WIFI_NM_HOSTAPD_AP + endif # WIFI endif # SHIELD_NXP_M2_2EL_WIFI_BT -if (BT_NXP_IW416) || (BT_NXP_NW612) || (NXP_IW416) || (NXP_IW61X) +if SHIELD_NXP_M2_2LL_WIFI_BT + +if BT + +choice BT_NXP_MODULE + default BT_NXP_IW610 +endchoice + +endif # BT + +if WIFI + +config WIFI_NXP + default y + +choice NXP_WIFI_PART + default NXP_IW610 +endchoice + +choice NXP_IW610_MODULE + default NXP_IW610_MURATA_2LL_M2 +endchoice + +if NET_DHCPV4_SERVER + +config NET_DHCPV4_SERVER_ADDR_COUNT + default 32 + +config NET_DHCPV4_SERVER_ICMP_PROBE_TIMEOUT + default 100 + +endif # NET_DHCPV4_SERVER + +if NET_L2_WIFI_MGMT + +config WIFI_MGMT_AP_MAX_NUM_STA + default 8 if NXP_WIFI_SOFTAP_SUPPORT + +endif # NET_L2_WIFI_MGMT + +if WIFI_NM_HOSTAPD_AP + +config WIFI_NM_HOSTAPD_REGULATORY_REGION + default "US" + +endif # WIFI_NM_HOSTAPD_AP + +endif # WIFI + +endif # SHIELD_NXP_M2_2LL_WIFI_BT + +if (BT_NXP_IW416) || (BT_NXP_NW612) || (BT_NXP_IW610) || (NXP_IW416) || (NXP_IW61X) || (NXP_IW610) if BT @@ -68,6 +139,15 @@ config BT_LONG_WQ_STACK_SIZE config MAIN_STACK_SIZE default 2560 +configdefault FPU + default y if CPU_HAS_FPU + +configdefault LIBLC3 + default y if BT_NXP_NW612 && BT_AUDIO && FPU + +configdefault BT_RX_STACK_SIZE + default 4096 if LIBLC3 + if SHELL config SHELL_STACK_SIZE diff --git a/boards/shields/nxp_m2_wifi_bt/Kconfig.shield b/boards/shields/nxp_m2_wifi_bt/Kconfig.shield index d61c97955ef..cba3a53ed5e 100644 --- a/boards/shields/nxp_m2_wifi_bt/Kconfig.shield +++ b/boards/shields/nxp_m2_wifi_bt/Kconfig.shield @@ -6,3 +6,6 @@ config SHIELD_NXP_M2_1XK_WIFI_BT config SHIELD_NXP_M2_2EL_WIFI_BT def_bool $(shields_list_contains,nxp_m2_2el_wifi_bt) + +config SHIELD_NXP_M2_2LL_WIFI_BT + def_bool $(shields_list_contains,nxp_m2_2ll_wifi_bt) diff --git a/boards/shields/nxp_m2_wifi_bt/doc/index.rst b/boards/shields/nxp_m2_wifi_bt/doc/index.rst index 19c3355faf1..fb0db5f797d 100644 --- a/boards/shields/nxp_m2_wifi_bt/doc/index.rst +++ b/boards/shields/nxp_m2_wifi_bt/doc/index.rst @@ -10,22 +10,26 @@ This Zephyr shield is tested with the following M.2 modules and hardware for Wi- - Embedded Artist 1XK module - uses Murata 1XK radio module with NXP IW416 chipset - Embedded Artist 2EL module - uses Murata 2EL radio module with NXP IW612 chipset +- Embedded Artist 2LL module - uses Murata 2LL radio module with NXP IW610 chipset More information about supported chipsets, radio modules and M.2 modules can be found in below links, - `IW612 NXP Chipset `_ - `IW416 NXP Chipset `_ +- `IW610 NXP Chipset `_ - `2EL Murata Radio Module `_ - `1XK Murata Radio Module `_ +- `2LL Murata Radio Module `_ - `1XK Embedded Artist Module `_ - `2EL Embedded Artist Module `_ +- `2LL Embedded Artist Module `_ Requirements ************ To use the shield, below requirements needs to be satisfied. -- M.2 module with BT HCI UART and SDIO Interface with NXP IW416 or IW612 SoC support. +- M.2 module with BT HCI UART and SDIO Interface with NXP IW416 or IW612 or IW610 SoC support. - Host platform shall have compatible M.2 interface slot. - For Coex (Wi-Fi + BT), UART driver that supports UART RTS line control to wakeup BT CPU from sleep. - To use default Bluetooth-Shell app it needs ~490KB flash & ~130KB RAM memory. @@ -34,7 +38,9 @@ To use the shield, below requirements needs to be satisfied. Integration Platform ******************** -This shield works with below host platform, +This shield is validated and tested for use with the host platform listed below. +While the shield can be used with other host platforms, other combinations +are not actively tested or validated. - :zephyr:board:`mimxrt1060_evk` Rev-C. @@ -56,17 +62,70 @@ Below are the supported shields to be used with ``--shield