diff --git a/tests/drivers/flash/common/boards/mx25uw63_low_freq.overlay b/tests/drivers/flash/common/boards/mx25uw63_low_freq.overlay new file mode 100644 index 00000000000..950005eaf5c --- /dev/null +++ b/tests/drivers/flash/common/boards/mx25uw63_low_freq.overlay @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&mx25uw63 { + status = "okay"; + mspi-max-frequency = ; +}; diff --git a/tests/drivers/flash/common/boards/mx25uw63_single_io_4B_addr_sreset.overlay b/tests/drivers/flash/common/boards/mx25uw63_single_io_4B_addr_sreset.overlay new file mode 100644 index 00000000000..587d6854656 --- /dev/null +++ b/tests/drivers/flash/common/boards/mx25uw63_single_io_4B_addr_sreset.overlay @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + + /delete-node/ exmif_default; + /delete-node/ exmif_sleep; + + exmif_default: exmif_default { + group1 { + psels = , + , + , + , + , + , + , + , + , + ; + nordic,drive-mode = ; + }; + }; + + exmif_sleep: exmif_sleep { + group1 { + low-power-enable; + psels = , + , + , + , + , + , + , + , + , + ; + }; + }; + +}; + +&gpio6 { + status = "okay"; +}; + +&exmif { + status = "okay"; + pinctrl-0 = <&exmif_default>; + pinctrl-1 = <&exmif_sleep>; + pinctrl-names = "default", "sleep"; + ce-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; +}; + +&mx25uw63 { + status = "okay"; + mspi-max-frequency = ; + mspi-io-mode = "MSPI_IO_MODE_SINGLE"; + use-4byte-addressing; + initial-soft-reset; +}; diff --git a/tests/drivers/flash/common/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/flash/common/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index 22c24c32f6d..5272bb8fdde 100644 --- a/tests/drivers/flash/common/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/tests/drivers/flash/common/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -4,6 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 */ +/ { + zephyr,user { + test-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio0 { + status = "okay"; +}; + &gpio6 { status = "okay"; zephyr,pm-device-runtime-auto; @@ -16,4 +26,5 @@ &mx25uw63 { status = "okay"; + supply-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; }; diff --git a/tests/drivers/flash/common/src/main.c b/tests/drivers/flash/common/src/main.c index ab0e63bb609..19ee70e407c 100644 --- a/tests/drivers/flash/common/src/main.c +++ b/tests/drivers/flash/common/src/main.c @@ -9,6 +9,7 @@ #include #include #include +#include #if defined(CONFIG_NORDIC_QSPI_NOR) #define TEST_AREA_DEV_NODE DT_INST(0, nordic_qspi_nor) @@ -322,6 +323,72 @@ ZTEST(flash_driver, test_flash_erase) zassert_not_equal(expected[0], erase_value, "These values shall be different"); } +ZTEST(flash_driver, test_flash_erase_different_block_sizes) +{ + if (!IS_ENABLED(CONFIG_SOC_NRF54H20)) { + ztest_test_skip(); + } + + int rc; + + /* There is not enough RAM memory + * to allocate the read buffer + * for the entire erase sector size + */ + uint8_t read_buffer[EXPECTED_SIZE]; + uint32_t offset; + uint32_t erase_block_size_to_expected_size_ratio; + const uint8_t erase_block_size_kB[] = {4, 64}; + const struct flash_parameters *fparams = flash_get_parameters(flash_dev); + + for (int i = 0; i < ARRAY_SIZE(erase_block_size_kB); i++) { + + TC_PRINT("Flash erase with erase size = %ukB\n", erase_block_size_kB[i]); + offset = 0; + + rc = flash_erase(flash_dev, page_info.start_offset, erase_block_size_kB[i] * 1024); + zassert_equal(rc, 0, "Flash memory not properly erased: %d", rc); + + erase_block_size_to_expected_size_ratio = + (erase_block_size_kB[i] * 1024) / EXPECTED_SIZE; + TC_PRINT("Erase block is %u times %uB\n", erase_block_size_to_expected_size_ratio, + EXPECTED_SIZE); + + for (int block_num = 0; block_num < erase_block_size_to_expected_size_ratio; + block_num++) { + rc = flash_read(flash_dev, page_info.start_offset + offset, read_buffer, + EXPECTED_SIZE); + zassert_equal(rc, 0, "Cannot read flash"); + + for (int i = 0; i < EXPECTED_SIZE; i++) { + if (read_buffer[i] != fparams->erase_value) { + zassert_equal(read_buffer[i], fparams->erase_value, + "Erase value != expected erase value, " + "address offset = 0x%x\n", + offset + i); + } + } + offset += EXPECTED_SIZE; + } + } +} + +ZTEST(flash_driver, test_supply_gpios_control) +{ + if (!DT_NODE_HAS_PROP(TEST_AREA_DEV_NODE, supply_gpios)) { + ztest_test_skip(); + } + +#if DT_NODE_HAS_PROP(DT_PATH(zephyr_user), test_gpios) + const struct gpio_dt_spec test_gpio = + GPIO_DT_SPEC_GET(DT_PATH(zephyr_user), test_gpios); + zassert_true(gpio_is_ready_dt(&test_gpio), "Test GPIO is not ready\n"); + zassert_ok(gpio_pin_configure_dt(&test_gpio, GPIO_INPUT | GPIO_PULL_DOWN), + "Failed to configure test pin\n"); + zassert_equal(gpio_pin_get(test_gpio.port, test_gpio.pin), 1, "Supply GPIO is not set\n"); +#endif +} + struct test_cb_data_type { uint32_t page_counter; /* used to count how many pages was iterated */ uint32_t exit_page; /* terminate iteration when this page is reached */ diff --git a/tests/drivers/flash/common/src/periphconf.c b/tests/drivers/flash/common/src/periphconf.c new file mode 100644 index 00000000000..d5cc94bd7c9 --- /dev/null +++ b/tests/drivers/flash/common/src/periphconf.c @@ -0,0 +1,167 @@ +/* Generated by nrf-regtool version 9.2.1 */ +#include + +/* SPU131 feature configuration for 0x5f934000UL ch. 0 */ +UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 0, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f934000UL ch. 1 */ +UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 1, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f934000UL ch. 2 */ +UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 2, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f934000UL ch. 3 */ +UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 3, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f934000UL ch. 4 */ +UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 4, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f934000UL ch. 5 */ +UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 5, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f934000UL ch. 6 */ +UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 6, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f934000UL ch. 7 */ +UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 7, true, NRF_OWNER_APPLICATION); +/* SPU133 feature configuration for GRTC CC4 */ +UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 4, true, NRF_OWNER_APPLICATION); +/* SPU133 feature configuration for GRTC CC5 */ +UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_APPLICATION); +/* SPU133 feature configuration for GRTC CC6 */ +UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.0 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 0, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.2 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 2, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.3 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 3, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.4 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 4, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.5 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 5, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.6 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 6, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.7 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 7, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.8 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 8, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.9 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 9, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.10 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 10, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.11 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 11, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938c00UL, P6.12 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 12, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938000UL, P0.0 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 0, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938000UL, P0.1 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 1, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938000UL, P0.8 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 8, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938000UL, P0.9 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 9, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938000UL, P0.10 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 10, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938000UL, P0.11 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 11, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f939200UL, P9.0 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 0, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f939200UL, P9.1 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 1, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f939200UL, P9.2 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 2, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f939200UL, P9.3 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 3, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f939200UL, P9.4 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 4, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f939200UL, P9.5 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 5, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938400UL, P2.4 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 2, 4, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938400UL, P2.5 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 2, 5, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938400UL, P2.6 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 2, 6, true, NRF_OWNER_APPLICATION); +/* SPU131 feature configuration for 0x5f938400UL, P2.7 */ +UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 2, 7, true, NRF_OWNER_APPLICATION); +/* 0x5f938c00UL - P6.0 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4); +/* 0x5f938c00UL - P6.2 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4); +/* 0x5f938c00UL - P6.3 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4); +/* 0x5f938c00UL - P6.4 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4); +/* 0x5f938c00UL - P6.5 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4); +/* 0x5f938c00UL - P6.6 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4); +/* 0x5f938c00UL - P6.7 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4); +/* 0x5f938c00UL - P6.8 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4); +/* 0x5f938c00UL - P6.9 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4); +/* 0x5f938c00UL - P6.10 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4); +/* 0x5f938c00UL - P6.11 CTRLSEL = 4 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4); +/* 0x5f938c00UL - P6.12 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 12, 0); +/* 0x5f938000UL - P0.0 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 0, 0); +/* 0x5f938000UL - P0.1 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 1, 0); +/* 0x5f938000UL - P0.8 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 8, 0); +/* 0x5f938000UL - P0.9 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 9, 0); +/* 0x5f938000UL - P0.10 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 10, 0); +/* 0x5f938000UL - P0.11 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 11, 0); +/* 0x5f939200UL - P9.0 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 0, 0); +/* 0x5f939200UL - P9.1 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 1, 0); +/* 0x5f939200UL - P9.2 CTRLSEL = 2 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2); +/* 0x5f939200UL - P9.3 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 3, 0); +/* 0x5f939200UL - P9.4 CTRLSEL = 6 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6); +/* 0x5f939200UL - P9.5 CTRLSEL = 6 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6); +/* 0x5f938400UL - P2.4 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938400UL, 4, 0); +/* 0x5f938400UL - P2.5 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938400UL, 5, 0); +/* 0x5f938400UL - P2.6 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938400UL, 6, 0); +/* 0x5f938400UL - P2.7 CTRLSEL = 0 */ +UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938400UL, 7, 0); +/* SPU110 configuration for 0x5f086000UL */ +UICR_SPU_PERIPH_PERM_SET(0x5f080000UL, 6, true, true, NRF_OWNER_APPLICATION); +/* SPU111 configuration for 0x5f095000UL */ +UICR_SPU_PERIPH_PERM_SET(0x5f090000UL, 5, true, false, NRF_OWNER_APPLICATION); +/* SPU120 configuration for 0x5f8c2000UL */ +UICR_SPU_PERIPH_PERM_SET(0x5f8c0000UL, 2, true, false, NRF_OWNER_APPLICATION); +/* SPU121 configuration for 0x5f8d8000UL */ +UICR_SPU_PERIPH_PERM_SET(0x5f8d0000UL, 8, true, true, NRF_OWNER_APPLICATION); +/* SPU132 configuration for 0x5f982000UL */ +UICR_SPU_PERIPH_PERM_SET(0x5f980000UL, 2, true, true, NRF_OWNER_APPLICATION); +/* SPU132 configuration for 0x5f985000UL */ +UICR_SPU_PERIPH_PERM_SET(0x5f980000UL, 5, true, true, NRF_OWNER_APPLICATION); +/* SPU134 configuration for 0x5f9a4000UL */ +UICR_SPU_PERIPH_PERM_SET(0x5f9a0000UL, 4, true, true, NRF_OWNER_APPLICATION); +/* SPU137 configuration for 0x5f9d5000UL */ +UICR_SPU_PERIPH_PERM_SET(0x5f9d0000UL, 5, true, true, NRF_OWNER_APPLICATION); +/* 0x5f086000UL IRQ => APPLICATION */ +UICR_IRQMAP_IRQ_SINK_SET(134, NRF_PROCESSOR_APPLICATION); +/* 0x5f095000UL IRQ => APPLICATION */ +UICR_IRQMAP_IRQ_SINK_SET(149, NRF_PROCESSOR_APPLICATION); +/* 0x5f8d8000UL IRQ => APPLICATION */ +UICR_IRQMAP_IRQ_SINK_SET(216, NRF_PROCESSOR_APPLICATION); +/* 0x5f982000UL IRQ => APPLICATION */ +UICR_IRQMAP_IRQ_SINK_SET(386, NRF_PROCESSOR_APPLICATION); +/* 0x5f985000UL IRQ => APPLICATION */ +UICR_IRQMAP_IRQ_SINK_SET(389, NRF_PROCESSOR_APPLICATION); +/* 0x5f9a4000UL IRQ => APPLICATION */ +UICR_IRQMAP_IRQ_SINK_SET(420, NRF_PROCESSOR_APPLICATION); +/* 0x5f9d5000UL IRQ => APPLICATION */ +UICR_IRQMAP_IRQ_SINK_SET(469, NRF_PROCESSOR_APPLICATION); \ No newline at end of file diff --git a/tests/drivers/flash/common/testcase.yaml b/tests/drivers/flash/common/testcase.yaml index 0a35ec04cd9..b28af1c0746 100644 --- a/tests/drivers/flash/common/testcase.yaml +++ b/tests/drivers/flash/common/testcase.yaml @@ -156,3 +156,13 @@ tests: - nrf54h20dk/nrf54h20/cpuapp extra_args: - EXTRA_DTC_OVERLAY_FILE=boards/mx25uw63_single_io.overlay + drivers.flash.common.mspi_single_io.4B_addr_soft_reset: + platform_allow: + - nrf54h20dk/nrf54h20/cpuapp + extra_args: + - EXTRA_DTC_OVERLAY_FILE=boards/mx25uw63_single_io_4B_addr_sreset.overlay + drivers.flash.common.mspi_low_frequency: + platform_allow: + - nrf54h20dk/nrf54h20/cpuapp + extra_args: + - EXTRA_DTC_OVERLAY_FILE=boards/mx25uw63_low_freq.overlay