From 977eb7fbec00d064817356ebc874180c82e312b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?H=C3=A5kon=20Amundsen?= Date: Fri, 3 Oct 2025 13:08:43 +0200 Subject: [PATCH 01/14] [nrf fromtree] soc: ironside: add min and max values for update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The update will fail if the address is outside of this range. This failure might trigger a bad state where the device is non-trivial to recover. Signed-off-by: Håkon Amundsen (cherry picked from commit 9d5f94f90b05451986f7c37243ae0579e991d734) --- .../nordic/nrf_ironside/update/src/main.c | 3 +++ .../ironside/include/nrf_ironside/update.h | 18 ++++++++++++++++++ soc/nordic/ironside/update.c | 5 +++++ 3 files changed, 26 insertions(+) diff --git a/samples/boards/nordic/nrf_ironside/update/src/main.c b/samples/boards/nordic/nrf_ironside/update/src/main.c index 29d058ca139..ee8823217de 100644 --- a/samples/boards/nordic/nrf_ironside/update/src/main.c +++ b/samples/boards/nordic/nrf_ironside/update/src/main.c @@ -10,6 +10,9 @@ LOG_MODULE_REGISTER(app, LOG_LEVEL_INF); +BUILD_ASSERT(CONFIG_UPDATE_BLOB_ADDRESS >= IRONSIDE_UPDATE_MIN_ADDRESS); +BUILD_ASSERT(CONFIG_UPDATE_BLOB_ADDRESS <= IRONSIDE_UPDATE_MAX_ADDRESS); + int main(void) { int err; diff --git a/soc/nordic/ironside/include/nrf_ironside/update.h b/soc/nordic/ironside/include/nrf_ironside/update.h index b01b5df6dad..6e520e4e680 100644 --- a/soc/nordic/ironside/include/nrf_ironside/update.h +++ b/soc/nordic/ironside/include/nrf_ironside/update.h @@ -18,11 +18,27 @@ #define IRONSIDE_UPDATE_ERROR_NOT_PERMITTED (1) /** Failed to write the update metadata to SICR. */ #define IRONSIDE_UPDATE_ERROR_SICR_WRITE_FAILED (2) +/** Update candidate is placed outside of valid range */ +#define IRONSIDE_UPDATE_ERROR_INVALID_ADDRESS (3) /** * @} */ +/** Size of the update blob */ +#ifdef CONFIG_SOC_SERIES_NRF54HX +#define IRONSIDE_UPDATE_BLOB_SIZE (160 * 1024) +#elif CONFIG_SOC_SERIES_NRF92X +#define IRONSIDE_UPDATE_BLOB_SIZE (160 * 1024) +#else +#error "Missing update blob size" +#endif + +/** Min address used for storing the update candidate */ +#define IRONSIDE_UPDATE_MIN_ADDRESS (0x0e100000) +/** Max address used for storing the update candidate */ +#define IRONSIDE_UPDATE_MAX_ADDRESS (0x0e200000 - IRONSIDE_UPDATE_BLOB_SIZE) + /** Length of the update manifest in bytes */ #define IRONSIDE_UPDATE_MANIFEST_LENGTH (256) /** Length of the update public key in bytes. */ @@ -62,6 +78,8 @@ struct ironside_update_blob { * @param update Pointer to update blob * * @retval 0 on a successful request (although the update itself may still fail). + * @retval -IRONSIDE_UPDATE_ERROR_INVALID_ADDRESS if the address of the update is outside of the + * accepted range. * @retval -IRONSIDE_UPDATE_ERROR_NOT_PERMITTED if missing access to the update candidate. * @retval -IRONSIDE_UPDATE_ERROR_SICR_WRITE_FAILED if writing update parameters to SICR failed. * @retval Positive error status if reported by IronSide call (see error codes in @ref call.h). diff --git a/soc/nordic/ironside/update.c b/soc/nordic/ironside/update.c index a56407a3fa1..fabf6fb0104 100644 --- a/soc/nordic/ironside/update.c +++ b/soc/nordic/ironside/update.c @@ -11,6 +11,11 @@ int ironside_update(const struct ironside_update_blob *update) int err; struct ironside_call_buf *const buf = ironside_call_alloc(); + if ((uintptr_t)update < IRONSIDE_UPDATE_MIN_ADDRESS || + (uintptr_t)update > IRONSIDE_UPDATE_MAX_ADDRESS) { + return -IRONSIDE_UPDATE_ERROR_INVALID_ADDRESS; + } + buf->id = IRONSIDE_CALL_ID_UPDATE_SERVICE_V0; buf->args[IRONSIDE_UPDATE_SERVICE_UPDATE_PTR_IDX] = (uintptr_t)update; From 608118d762430b35147c599dd3de18832aaa3252 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20B=C3=B8e?= Date: Wed, 10 Sep 2025 16:04:38 +0200 Subject: [PATCH 02/14] [nrf fromtree] boards: nrf54h20dk: Add secure storage partitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the default memory map to include a `secure_storage_partition`, which is divided into at most four subpartitions. These will be used to configure UICR.SECURESTORAGE, if enabled. Signed-off-by: Sebastian Bøe (cherry picked from commit d5003d996b266c988757a8a324551e297af5b776) --- .../nrf54h20dk_nrf54h20-memory_map.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index e14426c59fc..eafaf69b398 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -174,5 +174,34 @@ secondary_periphconf_partition: partition@1c0000 { reg = <0x1c0000 DT_SIZE_K(8)>; }; + + /* NB: A gap has been left here for future partitions */ + + /* 0x1fd000 was chosen for secure_storage_partition such that + * there is no more space after secure_storage_partition. + */ + secure_storage_partition: partition@1fd000 { + compatible = "fixed-subpartitions"; + reg = <0x1fd000 DT_SIZE_K(12)>; + ranges = <0x0 0x1fd000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_crypto_partition: partition@0 { + reg = <0x0 DT_SIZE_K(4)>; + }; + + cpurad_crypto_partition: partition@1000 { + reg = <0x1000 DT_SIZE_K(4)>; + }; + + cpuapp_its_partition: partition@2000 { + reg = <0x2000 DT_SIZE_K(2)>; + }; + + cpurad_its_partition: partition@2800 { + reg = <0x2800 DT_SIZE_K(2)>; + }; + }; }; }; From 02ef11fb1a34ad8a426adbbd699dd624be471f0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Mon, 15 Sep 2025 10:58:08 +0200 Subject: [PATCH 03/14] [nrf fromtree] drivers: pinctrl_nrf: Add support for SPIM CSN pin function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Certain SPIM instances in nRF52/53/54L/54H Series provide hardware control of the CSN (chip select) line. Although the standard SPI drivers do not use this feature, it should be possible to configure this line through pinctrl in case some special driver needs this. Signed-off-by: Andrzej Głąbek (cherry picked from commit ca79733388c87664f064e709b50d13afab907411) --- drivers/pinctrl/pinctrl_nrf.c | 14 +++++++++++--- include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h | 2 ++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index 9ea48ee34c4..f32a38b7975 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -46,11 +46,11 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = { #define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line #endif -#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi) || defined(CONFIG_NRFX_SPI) -#define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line -#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim) || defined(CONFIG_NRFX_SPIM) +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim) || defined(CONFIG_NRFX_SPIM) #include #define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line +#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi) || defined(CONFIG_NRFX_SPI) +#define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line #endif #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis) || defined(CONFIG_NRFX_SPIS) @@ -277,6 +277,14 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, dir = NRF_GPIO_PIN_DIR_INPUT; input = NRF_GPIO_PIN_INPUT_CONNECT; break; +#if defined(NRF_SPIM_HAS_HW_CSN) && NRF_SPIM_HAS_HW_CSN + case NRF_FUN_SPIM_CSN: + NRF_PSEL_SPIM(reg, CSN) = psel; + write = 1U; + dir = NRF_GPIO_PIN_DIR_OUTPUT; + input = NRF_GPIO_PIN_INPUT_DISCONNECT; + break; +#endif #endif /* defined(NRF_PSEL_SPIM) */ #if defined(NRF_PSEL_SPIS) case NRF_FUN_SPIS_SCK: diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h index 088cfce648b..342620318f3 100644 --- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h @@ -242,6 +242,8 @@ #define NRF_FUN_TDM_SDOUT 76U /** TDM MCK */ #define NRF_FUN_TDM_MCK 77U +/** SPI master CSN */ +#define NRF_FUN_SPIM_CSN 78U /** @} */ From acac3895a35decd8064184a5bc1fb05d6d40ebfd Mon Sep 17 00:00:00 2001 From: Jonathan Nilsen Date: Thu, 2 Oct 2025 08:22:52 +0200 Subject: [PATCH 04/14] [nrf fromtree] soc: nordic: uicr: fix SPIM CSN CTRLSEL values Fix an incorrect interpretation of the chip select signal for the SPIM instances. If cs-gpios is used then the chip select pin is used as a GPIO, and should have CTRLSEL=0. Only when NRF_FUN_SPIM_CSN is used should CTRLSEL be configured to enable hardware control of the pin. Signed-off-by: Jonathan Nilsen (cherry picked from commit b28b570959c1c578f9079c5b0f10603554701992) --- .../common/uicr/gen_periphconf_entries.py | 27 +++++++++---------- soc/nordic/common/uicr/periphconf/builder.py | 1 + 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/soc/nordic/common/uicr/gen_periphconf_entries.py b/soc/nordic/common/uicr/gen_periphconf_entries.py index 92f5f1d2455..4308df31449 100644 --- a/soc/nordic/common/uicr/gen_periphconf_entries.py +++ b/soc/nordic/common/uicr/gen_periphconf_entries.py @@ -25,7 +25,6 @@ from periphconf.builder import ( Ctrlsel, FixedPPIMap, - GpiosProp, Node, NrfCompChannel, NrfFun, @@ -178,7 +177,7 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables: # SPIM mappings NrfPsel(fun=NrfFun.SPIM_MOSI, port=9, pin=5): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=9, pin=2): Ctrlsel.SERIAL0, - GpiosProp(name="cs-gpios", port=9, pin=3): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=9, pin=3): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=9, pin=4): Ctrlsel.SERIAL0, # SPIS mappings NrfPsel(fun=NrfFun.SPIS_MISO, port=9, pin=5): Ctrlsel.SERIAL0, @@ -202,7 +201,7 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables: # SPIM mappings NrfPsel(fun=NrfFun.SPIM_MOSI, port=9, pin=0): Ctrlsel.CAN_TDM_SERIAL2, NrfPsel(fun=NrfFun.SPIM_MISO, port=9, pin=2): Ctrlsel.CAN_TDM_SERIAL2, - GpiosProp(name="cs-gpios", port=9, pin=3): Ctrlsel.CAN_TDM_SERIAL2, + NrfPsel(fun=NrfFun.SPIM_CSN, port=9, pin=3): Ctrlsel.CAN_TDM_SERIAL2, NrfPsel(fun=NrfFun.SPIM_SCK, port=9, pin=1): Ctrlsel.CAN_TDM_SERIAL2, # SPIS mappings NrfPsel(fun=NrfFun.SPIS_MISO, port=9, pin=0): Ctrlsel.CAN_TDM_SERIAL2, @@ -284,17 +283,17 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables: # SPIM P6 mappings NrfPsel(fun=NrfFun.SPIM_MOSI, port=6, pin=8): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=6, pin=7): Ctrlsel.SERIAL0, - GpiosProp(name="cs-gpios", port=6, pin=5): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=6, pin=5): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=6, pin=1): Ctrlsel.SERIAL0, # SPIM P7 mappings NrfPsel(fun=NrfFun.SPIM_MOSI, port=7, pin=7): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=7, pin=6): Ctrlsel.SERIAL0, - GpiosProp(name="cs-gpios", port=7, pin=5): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=7, pin=5): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=7, pin=3): Ctrlsel.SERIAL0, # SPIM P2 mappings NrfPsel(fun=NrfFun.SPIM_MOSI, port=2, pin=6): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=2, pin=5): Ctrlsel.SERIAL0, - GpiosProp(name="cs-gpios", port=2, pin=7): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=2, pin=7): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=2, pin=3): Ctrlsel.SERIAL0, # UARTÈ P6 mappings NrfPsel(fun=NrfFun.UART_TX, port=6, pin=8): Ctrlsel.SERIAL0, @@ -317,21 +316,21 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables: # SPIM P6 mappings NrfPsel(fun=NrfFun.SPIM_MOSI, port=6, pin=13): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=6, pin=12): Ctrlsel.SERIAL0, - GpiosProp(name="cs-gpios", port=6, pin=10): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=6, pin=10): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=6, pin=2): Ctrlsel.SERIAL0, # SPIM P7 mappings NrfPsel(fun=NrfFun.SPIM_MOSI, port=7, pin=1): Ctrlsel.EXMIF_RADIO_SERIAL1, NrfPsel(fun=NrfFun.SPIS_MISO, port=7, pin=1): Ctrlsel.EXMIF_RADIO_SERIAL1, NrfPsel(fun=NrfFun.SPIM_MISO, port=7, pin=0): Ctrlsel.EXMIF_RADIO_SERIAL1, NrfPsel(fun=NrfFun.SPIS_MOSI, port=7, pin=0): Ctrlsel.EXMIF_RADIO_SERIAL1, - GpiosProp(name="cs-gpios", port=7, pin=4): Ctrlsel.EXMIF_RADIO_SERIAL1, + NrfPsel(fun=NrfFun.SPIM_CSN, port=7, pin=4): Ctrlsel.EXMIF_RADIO_SERIAL1, NrfPsel(fun=NrfFun.SPIS_CSN, port=7, pin=4): Ctrlsel.EXMIF_RADIO_SERIAL1, NrfPsel(fun=NrfFun.SPIM_SCK, port=7, pin=2): Ctrlsel.EXMIF_RADIO_SERIAL1, NrfPsel(fun=NrfFun.SPIS_SCK, port=7, pin=2): Ctrlsel.EXMIF_RADIO_SERIAL1, # SPIM P2 mappings NrfPsel(fun=NrfFun.SPIM_MOSI, port=2, pin=11): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=2, pin=10): Ctrlsel.SERIAL0, - GpiosProp(name="cs-gpios", port=2, pin=8): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=2, pin=8): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=2, pin=2): Ctrlsel.SERIAL0, }, # EXMIF @@ -449,12 +448,12 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables: # SPIM120/UARTE120 0x5F8E_6000: { # SPIM P2 mappings - GpiosProp(name="cs-gpios", port=2, pin=5): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=2, pin=5): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=2, pin=3): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MOSI, port=2, pin=4): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=2, pin=0): Ctrlsel.SERIAL0, # SPIM P6 mappings - GpiosProp(name="cs-gpios", port=6, pin=5): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=6, pin=5): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=6, pin=7): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MOSI, port=6, pin=8): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=6, pin=1): Ctrlsel.SERIAL0, @@ -472,12 +471,12 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables: # SPIM121 0x5F8E_7000: { # P2 - GpiosProp(name="cs-gpios", port=2, pin=6): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=2, pin=6): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=2, pin=8): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MOSI, port=2, pin=9): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=2, pin=1): Ctrlsel.SERIAL0, # P6 - GpiosProp(name="cs-gpios", port=6, pin=10): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=6, pin=10): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=6, pin=12): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MOSI, port=6, pin=13): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=6, pin=2): Ctrlsel.SERIAL0, @@ -492,7 +491,7 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables: # SPIM130/SPIS130/TWIM130/TWIS130/UARTE130 0x5F9A_5000: { # SPIM mappings - GpiosProp(name="cs-gpios", port=9, pin=1): Ctrlsel.SERIAL0, + NrfPsel(fun=NrfFun.SPIM_CSN, port=9, pin=1): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MISO, port=9, pin=2): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_MOSI, port=9, pin=3): Ctrlsel.SERIAL0, NrfPsel(fun=NrfFun.SPIM_SCK, port=9, pin=0): Ctrlsel.SERIAL0, diff --git a/soc/nordic/common/uicr/periphconf/builder.py b/soc/nordic/common/uicr/periphconf/builder.py index 98c2bdfb0a0..1a343dee44a 100644 --- a/soc/nordic/common/uicr/periphconf/builder.py +++ b/soc/nordic/common/uicr/periphconf/builder.py @@ -1017,6 +1017,7 @@ class NrfFun(int, enum.Enum): TDM_SDIN = 75 TDM_SDOUT = 76 TDM_MCK = 77 + SPIM_CSN = 78 # Value used to ignore the function field and only check (port, pin) IGNORE = -1 From 5b325ed4a32350231d3b2e71eb31c5d1b486625d Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Wed, 8 Oct 2025 10:53:35 +0200 Subject: [PATCH 05/14] Revert "[nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration" This reverts commit 915e81a911b3d03834ad11d124449c0f4fa4ccc1. Signed-off-by: Karsten Koenig --- drivers/pinctrl/pinctrl_nrf.c | 32 ----------- .../zephyr/dt-bindings/pinctrl/nrf-pinctrl.h | 56 ------------------- 2 files changed, 88 deletions(-) diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index f32a38b7975..4c916a263e7 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -201,18 +201,6 @@ static void port_pin_clock_set(uint16_t pin_number, bool enable) #endif -#if DT_HAS_COMPAT_STATUS_OKAY(nordic_hpf_mspi_controller) || \ - defined(CONFIG_MSPI_HPF) || \ - DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(nordic_nrf_vpr_coprocessor, pinctrl_0) -#if defined(CONFIG_SOC_SERIES_NRF54LX) -#define NRF_PSEL_SDP_MSPI(psel) \ - nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR); -#elif defined(CONFIG_SOC_SERIES_NRF54HX) -/* On nRF54H, pin routing is controlled by secure domain, via UICR. */ -#define NRF_PSEL_SDP_MSPI(psel) -#endif -#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_hpf_mspi_controller) || ... */ - int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) { @@ -570,26 +558,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, input = NRF_GPIO_PIN_INPUT_CONNECT; break; #endif /* defined(NRF_PSEL_TWIS) */ -#if defined(NRF_PSEL_SDP_MSPI) - case NRF_FUN_SDP_MSPI_CS0: - case NRF_FUN_SDP_MSPI_CS1: - case NRF_FUN_SDP_MSPI_CS2: - case NRF_FUN_SDP_MSPI_CS3: - case NRF_FUN_SDP_MSPI_CS4: - case NRF_FUN_SDP_MSPI_SCK: - case NRF_FUN_SDP_MSPI_DQ0: - case NRF_FUN_SDP_MSPI_DQ1: - case NRF_FUN_SDP_MSPI_DQ2: - case NRF_FUN_SDP_MSPI_DQ3: - case NRF_FUN_SDP_MSPI_DQ4: - case NRF_FUN_SDP_MSPI_DQ5: - case NRF_FUN_SDP_MSPI_DQ6: - case NRF_FUN_SDP_MSPI_DQ7: - NRF_PSEL_SDP_MSPI(psel); - dir = NRF_GPIO_PIN_DIR_OUTPUT; - input = NRF_GPIO_PIN_INPUT_CONNECT; - break; -#endif /* defined(NRF_PSEL_SDP_MSPI) */ default: return -ENOTSUP; } diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h index 342620318f3..42b302193ed 100644 --- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h @@ -172,62 +172,6 @@ #define NRF_FUN_GRTC_CLKOUT_FAST 55U /** GRTC slow clock output */ #define NRF_FUN_GRTC_CLKOUT_32K 56U -/** SDP_MSPI clock pin */ -#define NRF_FUN_SDP_MSPI_SCK 57U -/** SDP_MSPI data pin 0 */ -#define NRF_FUN_SDP_MSPI_DQ0 58U -/** SDP_MSPI data pin 1 */ -#define NRF_FUN_SDP_MSPI_DQ1 59U -/** SDP_MSPI data pin 2 */ -#define NRF_FUN_SDP_MSPI_DQ2 60U -/** SDP_MSPI data pin 3 */ -#define NRF_FUN_SDP_MSPI_DQ3 61U -/** SDP_MSPI data pin 4 */ -#define NRF_FUN_SDP_MSPI_DQ4 62U -/** SDP_MSPI data pin 5 */ -#define NRF_FUN_SDP_MSPI_DQ5 63U -/** SDP_MSPI data pin 6 */ -#define NRF_FUN_SDP_MSPI_DQ6 64U -/** SDP_MSPI data pin 7 */ -#define NRF_FUN_SDP_MSPI_DQ7 65U -/** SDP_MSPI chip select 0 */ -#define NRF_FUN_SDP_MSPI_CS0 66U -/** SDP_MSPI chip select 1 */ -#define NRF_FUN_SDP_MSPI_CS1 67U -/** SDP_MSPI chip select 2 */ -#define NRF_FUN_SDP_MSPI_CS2 68U -/** SDP_MSPI chip select 3 */ -#define NRF_FUN_SDP_MSPI_CS3 69U -/** SDP_MSPI chip select 4 */ -#define NRF_FUN_SDP_MSPI_CS4 70U -/** High-Performance Framework MSPI clock pin */ -#define NRF_FUN_HPF_MSPI_SCK NRF_FUN_SDP_MSPI_SCK -/** High-Performance Framework MSPI data pin 0 */ -#define NRF_FUN_HPF_MSPI_DQ0 NRF_FUN_SDP_MSPI_DQ0 -/** High-Performance Framework MSPI data pin 1 */ -#define NRF_FUN_HPF_MSPI_DQ1 NRF_FUN_SDP_MSPI_DQ1 -/** High-Performance Framework MSPI data pin 2 */ -#define NRF_FUN_HPF_MSPI_DQ2 NRF_FUN_SDP_MSPI_DQ2 -/** High-Performance Framework MSPI data pin 3 */ -#define NRF_FUN_HPF_MSPI_DQ3 NRF_FUN_SDP_MSPI_DQ3 -/** High-Performance Framework MSPI data pin 4 */ -#define NRF_FUN_HPF_MSPI_DQ4 NRF_FUN_SDP_MSPI_DQ4 -/** High-Performance Framework MSPI data pin 5 */ -#define NRF_FUN_HPF_MSPI_DQ5 NRF_FUN_SDP_MSPI_DQ5 -/** High-Performance Framework MSPI data pin 6 */ -#define NRF_FUN_HPF_MSPI_DQ6 NRF_FUN_SDP_MSPI_DQ6 -/** High-Performance Framework MSPI data pin 7 */ -#define NRF_FUN_HPF_MSPI_DQ7 NRF_FUN_SDP_MSPI_DQ7 -/** High-Performance Framework MSPI chip select pin 0 */ -#define NRF_FUN_HPF_MSPI_CS0 NRF_FUN_SDP_MSPI_CS0 -/** High-Performance Framework MSPI chip select pin 1 */ -#define NRF_FUN_HPF_MSPI_CS1 NRF_FUN_SDP_MSPI_CS1 -/** High-Performance Framework MSPI chip select pin 2 */ -#define NRF_FUN_HPF_MSPI_CS2 NRF_FUN_SDP_MSPI_CS2 -/** High-Performance Framework MSPI chip select pin 3 */ -#define NRF_FUN_HPF_MSPI_CS3 NRF_FUN_SDP_MSPI_CS3 -/** High-Performance Framework MSPI chip select pin 4 */ -#define NRF_FUN_HPF_MSPI_CS4 NRF_FUN_SDP_MSPI_CS4 /** TDM SCK in master mode */ #define NRF_FUN_TDM_SCK_M 71U /** TDM SCK in slave mode */ From efab85d11c58e964357c3713a258beffbc78e728 Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Fri, 3 Oct 2025 13:51:17 +0200 Subject: [PATCH 06/14] [nrf fromtree] drivers: debug: Moved nrf_etr from misc Moved the nrf_etr driver from the drive/misc folder into the recently established driver/debug folder where it is a better fit. Moved the associated files such as bindings and headers accordingly as well. Signed-off-by: Karsten Koenig (cherry picked from commit d833556ee55b921a675dd239c3cc2330d3605669) --- doc/services/logging/cs_stm.rst | 4 +- drivers/debug/CMakeLists.txt | 1 + drivers/debug/Kconfig | 1 + .../coresight/Kconfig => debug/Kconfig.nrf} | 40 +++++----- .../nrf_etr.c => debug/debug_nrf_etr.c} | 74 ++++++++++--------- drivers/misc/CMakeLists.txt | 1 - drivers/misc/Kconfig | 1 - drivers/misc/coresight/CMakeLists.txt | 4 - .../{misc => debug}/nordic,nrf-tbm.yaml | 0 .../nrf_etr.h => debug/debug_nrf_etr.h} | 8 +- .../{misc/coresight => debug}/stmesp.h | 6 +- include/zephyr/logging/log_frontend_stmesp.h | 2 +- .../nordic/coresight_stm/pytest/test_stm.py | 2 +- .../nrf54h/Kconfig.defconfig.nrf54h20_cpuapp | 2 +- subsys/logging/frontends/Kconfig | 4 +- .../logging/frontends/log_frontend_stmesp.c | 13 ++-- 16 files changed, 81 insertions(+), 82 deletions(-) rename drivers/{misc/coresight/Kconfig => debug/Kconfig.nrf} (79%) rename drivers/{misc/coresight/nrf_etr.c => debug/debug_nrf_etr.c} (92%) delete mode 100644 drivers/misc/coresight/CMakeLists.txt rename dts/bindings/{misc => debug}/nordic,nrf-tbm.yaml (100%) rename include/zephyr/drivers/{misc/coresight/nrf_etr.h => debug/debug_nrf_etr.h} (52%) rename include/zephyr/drivers/{misc/coresight => debug}/stmesp.h (96%) diff --git a/doc/services/logging/cs_stm.rst b/doc/services/logging/cs_stm.rst index 75a371dfd24..77b097d6516 100644 --- a/doc/services/logging/cs_stm.rst +++ b/doc/services/logging/cs_stm.rst @@ -119,7 +119,7 @@ When using logs, this method has the following advantages: Proxy core is using Nordic specific peripheral (TBM) to get ETR buffer busyness and send data over UART. Nordic specific driver for ETR buffer is located in -:zephyr_file:`drivers/misc/coresight/nrf_etr.c`. +:zephyr_file:`drivers/debug/debug_nrf_etr.c`. Configuration ------------- @@ -175,7 +175,7 @@ in :zephyr_file:`subsys/logging/frontends/log_frontend_stmesp_demux.c`. ``Proxy`` is using Nordic specific peripheral (TBM) to get ETR buffer busyness and read and decode data and send human-readable data over UART. Nordic specific driver for ETR buffer is -located in :zephyr_file:`drivers/misc/coresight/nrf_etr.c`. It is using :ref:`cs_trace_defmt` and +located in :zephyr_file:`drivers/debug/debug_nrf_etr.c`. It is using :ref:`cs_trace_defmt` and :ref:`mipi_stp_decoder` and above-mentioned demultiplexer to decode messages. Logging messages contains read-only format string used in the logging macros thus they cannot be diff --git a/drivers/debug/CMakeLists.txt b/drivers/debug/CMakeLists.txt index 54ca9f71694..8314379f8fa 100644 --- a/drivers/debug/CMakeLists.txt +++ b/drivers/debug/CMakeLists.txt @@ -5,4 +5,5 @@ zephyr_library() # zephyr-keep-sorted-start zephyr_library_sources_ifdef(CONFIG_DEBUG_SILABS_PTI debug_silabs_pti.c) +zephyr_library_sources_ifdef(CONFIG_DEBUG_NRF_ETR debug_nrf_etr.c) # zephyr-keep-sorted-stop diff --git a/drivers/debug/Kconfig b/drivers/debug/Kconfig index 68c23fdf124..b38c5206f3c 100644 --- a/drivers/debug/Kconfig +++ b/drivers/debug/Kconfig @@ -15,6 +15,7 @@ config DEBUG_DRIVER_INIT_PRIORITY Debug drivers initialization priority. # zephyr-keep-sorted-start +source "drivers/debug/Kconfig.nrf" source "drivers/debug/Kconfig.silabs" # zephyr-keep-sorted-stop diff --git a/drivers/misc/coresight/Kconfig b/drivers/debug/Kconfig.nrf similarity index 79% rename from drivers/misc/coresight/Kconfig rename to drivers/debug/Kconfig.nrf index 997d0c23c0a..da2721947e1 100644 --- a/drivers/misc/coresight/Kconfig +++ b/drivers/debug/Kconfig.nrf @@ -3,7 +3,7 @@ DT_COMPAT_NORDIC_NRF_TBM := nordic,nrf-tbm -config NRF_ETR +config DEBUG_NRF_ETR bool "Coresight ETR handler (with Nordic TBM)" depends on $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_TBM)) select NRFX_TBM @@ -14,9 +14,9 @@ config NRF_ETR data). Busyness is tracked using TBM (Trace Buffer Monitor) peripheral which is specific to Nordic Semiconductor SoCs. -if NRF_ETR +if DEBUG_NRF_ETR -config NRF_ETR_DECODE +config DEBUG_NRF_ETR_DECODE bool "Decode ETR content" default y if LOG_FRONTEND_STMESP_FSC select MIPI_STP_DECODER @@ -29,14 +29,14 @@ config NRF_ETR_DECODE In this mode, log messages stored by Coresight STM logging frontends are decoded and printed in the human readable form. -config NRF_ETR_DECODE_DROP_PERIOD +config DEBUG_NRF_ETR_DECODE_DROP_PERIOD int "Period of dropped messages notification" default 5000 help Period (in milliseconds) how often it is checked if any dropped messages have occurred. -config NRF_ETR_DEBUG +config DEBUG_NRF_ETR_DEBUG bool "Debug mode" depends on !LOG_PRINTK select MIPI_STP_DECODER @@ -44,18 +44,18 @@ config NRF_ETR_DEBUG help In debug mode STPv2 decoded data is printed. -config NRF_ETR_STACK_SIZE +config DEBUG_NRF_ETR_STACK_SIZE int "ETR thread stack size" - default 2048 if NRF_ETR_DECODE || NRF_ETR_DEBUG + default 2048 if DEBUG_NRF_ETR_DECODE || DEBUG_NRF_ETR_DEBUG default 1024 -config NRF_ETR_BACKOFF +config DEBUG_NRF_ETR_BACKOFF int "Thread backoff time (ms)" default 10 help Determines how often attempt to dump the data is performed. -config NRF_ETR_FLUSH_TIMEOUT +config DEBUG_NRF_ETR_FLUSH_TIMEOUT int "Backoff time during flushing (ms)" default 100 help @@ -63,10 +63,10 @@ config NRF_ETR_FLUSH_TIMEOUT there is still a pending ETR data. This option specifies how often thread is waking up to check. Given in milliseconds. -config NRF_ETR_SYNC_PERIOD +config DEBUG_NRF_ETR_SYNC_PERIOD int "Period of custom synchronization frame" - default 0 if NRF_ETR_DECODE - default 0 if NRF_ETR_DEBUG + default 0 if DEBUG_NRF_ETR_DECODE + default 0 if DEBUG_NRF_ETR_DEBUG default 16 help To help find the synchronization when decoding the ETR content @@ -74,25 +74,25 @@ config NRF_ETR_SYNC_PERIOD sent on regular intervals. This frame is sent between Coresight formatter frames. Use 0 to disable. -config NRF_ETR_SHELL +config DEBUG_NRF_ETR_SHELL bool "Use shell" select UART_ASYNC_API select UART_ASYNC_RX_HELPER select SHELL_LOG_BACKEND_CUSTOM - depends on NRF_ETR_DECODE + depends on DEBUG_NRF_ETR_DECODE default y if SHELL help Enable shell with Coresight STM logging support. -if NRF_ETR_SHELL +if DEBUG_NRF_ETR_SHELL -config NRF_ETR_SHELL_PROMPT +config DEBUG_NRF_ETR_SHELL_PROMPT string "Displayed prompt name" default "uart:~$ " help Displayed prompt name for UART shell with Coresight STM logging. -config NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE +config DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE int "Size of the RX buffer" default 16 help @@ -101,13 +101,13 @@ config NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE slow and may need to be increased if long messages are pasted directly to the shell prompt. -config NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT +config DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT int "Number of RX buffers" default 4 range 2 64 help Number of RX buffers. -endif # NRF_ETR_SHELL +endif # DEBUG_NRF_ETR_SHELL -endif # NRF_ETR +endif # DEBUG_NRF_ETR diff --git a/drivers/misc/coresight/nrf_etr.c b/drivers/debug/debug_nrf_etr.c similarity index 92% rename from drivers/misc/coresight/nrf_etr.c rename to drivers/debug/debug_nrf_etr.c index bf1aecd6f5b..da425716dbb 100644 --- a/drivers/misc/coresight/nrf_etr.c +++ b/drivers/debug/debug_nrf_etr.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -29,15 +29,15 @@ LOG_MODULE_REGISTER(cs_etr_tbm); #define ETR_BUFFER_NODE DT_NODELABEL(etr_buffer) #define DROP_CHECK_PERIOD \ - COND_CODE_1(CONFIG_NRF_ETR_DECODE, \ - (CONFIG_NRF_ETR_DECODE_DROP_PERIOD), (0)) + COND_CODE_1(CONFIG_DEBUG_NRF_ETR_DECODE, \ + (CONFIG_DEBUG_NRF_ETR_DECODE_DROP_PERIOD), (0)) #define MIN_DATA (2 * CORESIGHT_TRACE_FRAME_SIZE32) /* Since ETR debug is a part of logging infrastructure, logging cannot be used * for debugging. Printk is used (assuming CONFIG_LOG_PRINTK=n) */ -#define DBG(...) IF_ENABLED(CONFIG_NRF_ETR_DEBUG, (printk(__VA_ARGS__))) +#define DBG(...) IF_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG, (printk(__VA_ARGS__))) /** @brief Macro for dumping debug data. * @@ -86,10 +86,10 @@ static const struct device *uart_dev = DEVICE_DT_GET(UART_NODE); static uint32_t frame_buf0[CORESIGHT_TRACE_FRAME_SIZE32] DMM_MEMORY_SECTION(UART_NODE); static uint32_t frame_buf1[CORESIGHT_TRACE_FRAME_SIZE32] DMM_MEMORY_SECTION(UART_NODE); static uint32_t frame_buf_decode[CORESIGHT_TRACE_FRAME_SIZE32]; -static uint32_t *frame_buf = IS_ENABLED(CONFIG_NRF_ETR_DECODE) ? +static uint32_t *frame_buf = IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) ? frame_buf_decode : frame_buf0; -K_KERNEL_STACK_DEFINE(etr_stack, CONFIG_NRF_ETR_STACK_SIZE); +K_KERNEL_STACK_DEFINE(etr_stack, CONFIG_DEBUG_NRF_ETR_STACK_SIZE); static struct k_thread etr_thread; BUILD_ASSERT((DT_REG_SIZE(ETR_BUFFER_NODE) % CONFIG_DCACHE_LINE_SIZE) == 0); @@ -134,9 +134,10 @@ static const char *const hw_evts[] = { "GD0 HS down", /* 31 Global domain high speed 0 down */ }; -#ifdef CONFIG_NRF_ETR_SHELL +#ifdef CONFIG_DEBUG_NRF_ETR_SHELL #define RX_BUF_SIZE \ - (CONFIG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE * CONFIG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT) + (CONFIG_DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_SIZE * \ + CONFIG_DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT) static void etr_timer_handler(struct k_timer *timer); K_TIMER_DEFINE(etr_timer, etr_timer_handler, NULL); @@ -278,7 +279,7 @@ static void message_process(union log_frontend_stmesp_demux_packet packet) */ static void sync_loss(void) { - if (IS_ENABLED(CONFIG_NRF_ETR_DECODE)) { + if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) { mipi_stp_decoder_sync_loss(); log_frontend_stmesp_demux_reset(); oosync_cnt++; @@ -292,7 +293,7 @@ static void sync_loss(void) */ static void on_resync(void) { - if (IS_ENABLED(CONFIG_NRF_ETR_DECODE)) { + if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) { in_sync = true; } } @@ -365,7 +366,7 @@ static void decoder_cb(enum mipi_stp_decoder_ctrl_type type, decoder_cb_debug(type, data, ts, marked); - if (!IS_ENABLED(CONFIG_NRF_ETR_DECODE)) { + if (!IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) { return; } @@ -549,7 +550,7 @@ static void dump_frame(uint8_t *buf) static void process(void) { static const uint32_t *const etr_buf = (uint32_t *)(DT_REG_ADDR(ETR_BUFFER_NODE)); - static uint32_t sync_cnt; + static uint32_t sync_cnt = CONFIG_DEBUG_NRF_ETR_SYNC_PERIOD; uint32_t pending; /* If function is called in panic mode then it may interrupt ongoing @@ -562,7 +563,7 @@ static void process(void) */ while ((pending = pending_data()) >= MIN_DATA) { /* Do not read the data that has already been read but not yet processed. */ - if (sync_cnt || (CONFIG_NRF_ETR_SYNC_PERIOD == 0)) { + if (sync_cnt || (CONFIG_DEBUG_NRF_ETR_SYNC_PERIOD == 0)) { sync_cnt--; sys_cache_data_invd_range((void *)&etr_buf[etr_rd_idx & wsize_mask], CORESIGHT_TRACE_FRAME_SIZE); @@ -572,11 +573,12 @@ static void process(void) rd_idx_inc(); __sync_synchronize(); } else { - sync_cnt = CONFIG_NRF_ETR_SYNC_PERIOD; + sync_cnt = CONFIG_DEBUG_NRF_ETR_SYNC_PERIOD; memset(frame_buf, 0xff, CORESIGHT_TRACE_FRAME_SIZE); } - if (IS_ENABLED(CONFIG_NRF_ETR_DECODE) || IS_ENABLED(CONFIG_NRF_ETR_DEBUG)) { + if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) || + IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG)) { if ((pending >= (wsize_mask - MIN_DATA)) || (pending_data() >= (wsize_mask - MIN_DATA))) { /* If before or after reading the frame it is close to full @@ -586,7 +588,7 @@ static void process(void) } process_frame((uint8_t *)frame_buf, pending); - if (IS_ENABLED(CONFIG_NRF_ETR_DECODE)) { + if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) { process_messages(); } } else { @@ -612,7 +614,7 @@ static int decoder_init(void) } once = true; - if (IS_ENABLED(CONFIG_NRF_ETR_DECODE)) { + if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE)) { static const struct log_frontend_stmesp_demux_config config = { .m_ids = stm_m_id, .m_ids_cnt = ARRAY_SIZE(stm_m_id), @@ -635,12 +637,12 @@ static int decoder_init(void) return 0; } -void nrf_etr_flush(void) +void debug_nrf_etr_flush(void) { int cnt = 4; - if (IS_ENABLED(CONFIG_NRF_ETR_DECODE) || - IS_ENABLED(CONFIG_NRF_ETR_DEBUG)) { + if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) || + IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG)) { (void)decoder_init(); } @@ -658,13 +660,13 @@ void nrf_etr_flush(void) irq_unlock(k); } -#ifndef CONFIG_NRF_ETR_SHELL +#ifndef CONFIG_DEBUG_NRF_ETR_SHELL static void etr_thread_func(void *dummy1, void *dummy2, void *dummy3) { uint64_t checkpoint = 0; - if (IS_ENABLED(CONFIG_NRF_ETR_DECODE) || - IS_ENABLED(CONFIG_NRF_ETR_DEBUG)) { + if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) || + IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG)) { int err; err = decoder_init(); @@ -688,7 +690,7 @@ static void etr_thread_func(void *dummy1, void *dummy2, void *dummy3) } } - k_sleep(K_MSEC(CONFIG_NRF_ETR_BACKOFF)); + k_sleep(K_MSEC(CONFIG_DEBUG_NRF_ETR_BACKOFF)); } } #endif @@ -703,7 +705,7 @@ static void uart_event_handler(const struct device *dev, struct uart_event *evt, case UART_TX_DONE: k_sem_give(&uart_sem); break; -#ifdef CONFIG_NRF_ETR_SHELL +#ifdef CONFIG_DEBUG_NRF_ETR_SHELL case UART_RX_RDY: uart_async_rx_on_rdy(&async_rx, evt->data.rx.buf, evt->data.rx.len); shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, shell_context); @@ -729,7 +731,7 @@ static void uart_event_handler(const struct device *dev, struct uart_event *evt, break; case UART_RX_DISABLED: break; -#endif /* CONFIG_NRF_ETR_SHELL */ +#endif /* CONFIG_DEBUG_NRF_ETR_SHELL */ default: __ASSERT_NO_MSG(0); } @@ -743,7 +745,7 @@ static void tbm_event_handler(nrf_tbm_event_t event) tbm_full = true; } -#ifdef CONFIG_NRF_ETR_SHELL +#ifdef CONFIG_DEBUG_NRF_ETR_SHELL k_poll_signal_raise(&etr_shell.ctx->signals[SHELL_SIGNAL_LOG_MSG], 0); #else k_wakeup(&etr_thread); @@ -767,14 +769,14 @@ int etr_process_init(void) nrfx_isr, nrfx_tbm_irq_handler, 0); irq_enable(DT_IRQN(DT_NODELABEL(tbm))); -#ifdef CONFIG_NRF_ETR_SHELL +#ifdef CONFIG_DEBUG_NRF_ETR_SHELL uint32_t level = CONFIG_LOG_MAX_LEVEL; static const struct shell_backend_config_flags cfg_flags = SHELL_DEFAULT_BACKEND_CONFIG_FLAGS; shell_init(&etr_shell, NULL, cfg_flags, true, level); - k_timer_start(&etr_timer, K_MSEC(CONFIG_NRF_ETR_BACKOFF), K_NO_WAIT); - if (IS_ENABLED(CONFIG_NRF_ETR_DECODE) || IS_ENABLED(CONFIG_NRF_ETR_DEBUG)) { + k_timer_start(&etr_timer, K_MSEC(CONFIG_DEBUG_NRF_ETR_BACKOFF), K_NO_WAIT); + if (IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DECODE) || IS_ENABLED(CONFIG_DEBUG_NRF_ETR_DEBUG)) { err = decoder_init(); if (err < 0) { return err; @@ -791,14 +793,14 @@ int etr_process_init(void) SYS_INIT(etr_process_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); -#ifdef CONFIG_NRF_ETR_SHELL +#ifdef CONFIG_DEBUG_NRF_ETR_SHELL static void etr_timer_handler(struct k_timer *timer) { if (pending_data() >= MIN_DATA) { k_poll_signal_raise(&etr_shell.ctx->signals[SHELL_SIGNAL_LOG_MSG], 0); } else { - k_timer_start(timer, K_MSEC(CONFIG_NRF_ETR_BACKOFF), K_NO_WAIT); + k_timer_start(timer, K_MSEC(CONFIG_DEBUG_NRF_ETR_BACKOFF), K_NO_WAIT); } } @@ -807,7 +809,7 @@ bool z_shell_log_backend_process(const struct shell_log_backend *backend) ARG_UNUSED(backend); process(); - k_timer_start(&etr_timer, K_MSEC(CONFIG_NRF_ETR_BACKOFF), K_NO_WAIT); + k_timer_start(&etr_timer, K_MSEC(CONFIG_DEBUG_NRF_ETR_BACKOFF), K_NO_WAIT); return false; } @@ -901,7 +903,7 @@ static int etr_shell_init(const struct shell_transport *transport, const void *c static const struct uart_async_rx_config async_rx_config = { .buffer = rx_buf, .length = sizeof(rx_buf), - .buf_cnt = CONFIG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT, + .buf_cnt = CONFIG_DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT, }; shell_context = context; @@ -939,6 +941,6 @@ static struct shell_transport transport = { }; static uint8_t shell_out_buffer[CONFIG_SHELL_PRINTF_BUFF_SIZE]; -Z_SHELL_DEFINE(etr_shell, CONFIG_NRF_ETR_SHELL_PROMPT, &transport, shell_out_buffer, NULL, +Z_SHELL_DEFINE(etr_shell, CONFIG_DEBUG_NRF_ETR_SHELL_PROMPT, &transport, shell_out_buffer, NULL, SHELL_FLAG_OLF_CRLF); -#endif /* CONFIG_NRF_ETR_SHELL */ +#endif /* CONFIG_DEBUG_NRF_ETR_SHELL */ diff --git a/drivers/misc/CMakeLists.txt b/drivers/misc/CMakeLists.txt index 437bd124247..8426090ab14 100644 --- a/drivers/misc/CMakeLists.txt +++ b/drivers/misc/CMakeLists.txt @@ -15,5 +15,4 @@ add_subdirectory_ifdef(CONFIG_RENESAS_RX_EXTERNAL_INTERRUPT renesas_rx_external_ add_subdirectory_ifdef(CONFIG_NXP_RTXXX_DSP_CTRL nxp_rtxxx_dsp_ctrl) add_subdirectory_ifdef(CONFIG_STM32N6_AXISRAM stm32n6_axisram) -add_subdirectory(coresight) add_subdirectory(interconn) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6d4d5cfc16f..0a3af14dc2c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -15,7 +15,6 @@ source "drivers/misc/timeaware_gpio/Kconfig" source "drivers/misc/devmux/Kconfig" source "drivers/misc/nordic_vpr_launcher/Kconfig" source "drivers/misc/mcux_flexio/Kconfig" -source "drivers/misc/coresight/Kconfig" source "drivers/misc/interconn/Kconfig" source "drivers/misc/renesas_ra_external_interrupt/Kconfig" source "drivers/misc/renesas_rx_external_interrupt/Kconfig" diff --git a/drivers/misc/coresight/CMakeLists.txt b/drivers/misc/coresight/CMakeLists.txt deleted file mode 100644 index 1ec34ca2f75..00000000000 --- a/drivers/misc/coresight/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_NRF_ETR nrf_etr.c) diff --git a/dts/bindings/misc/nordic,nrf-tbm.yaml b/dts/bindings/debug/nordic,nrf-tbm.yaml similarity index 100% rename from dts/bindings/misc/nordic,nrf-tbm.yaml rename to dts/bindings/debug/nordic,nrf-tbm.yaml diff --git a/include/zephyr/drivers/misc/coresight/nrf_etr.h b/include/zephyr/drivers/debug/debug_nrf_etr.h similarity index 52% rename from include/zephyr/drivers/misc/coresight/nrf_etr.h rename to include/zephyr/drivers/debug/debug_nrf_etr.h index 062afa3b61a..04805a7e2d1 100644 --- a/include/zephyr/drivers/misc/coresight/nrf_etr.h +++ b/include/zephyr/drivers/debug/debug_nrf_etr.h @@ -3,18 +3,18 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_ -#define _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_ +#ifndef _ZEPHYR_DRIVERS_DEBUG_CORESIGHT_NRF_ETR_H_ +#define _ZEPHYR_DRIVERS_DEBUG_CORESIGHT_NRF_ETR_H_ #ifdef __cplusplus extern "C" { #endif /** @brief Flush data from the ETR buffer. */ -void nrf_etr_flush(void); +void debug_nrf_etr_flush(void); #ifdef __cplusplus } #endif -#endif /* _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_ */ +#endif /* _ZEPHYR_DRIVERS_DEBUG_CORESIGHT_NRF_ETR_H_ */ diff --git a/include/zephyr/drivers/misc/coresight/stmesp.h b/include/zephyr/drivers/debug/stmesp.h similarity index 96% rename from include/zephyr/drivers/misc/coresight/stmesp.h rename to include/zephyr/drivers/debug/stmesp.h index ce0f64b52dd..d4b245857eb 100644 --- a/include/zephyr/drivers/misc/coresight/stmesp.h +++ b/include/zephyr/drivers/debug/stmesp.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_ -#define ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_ +#ifndef ZEPHYR_INCLUDE_DRIVERS_DEBUG_CORESIGHT_STMESP_H_ +#define ZEPHYR_INCLUDE_DRIVERS_DEBUG_CORESIGHT_STMESP_H_ #include @@ -190,4 +190,4 @@ static inline int stmesp_get_port(uint32_t idx, STMESP_Type **port) * @} */ -#endif /* ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_ */ +#endif /* ZEPHYR_INCLUDE_DRIVERS_DEBUG_CORESIGHT_STMESP_H_ */ diff --git a/include/zephyr/logging/log_frontend_stmesp.h b/include/zephyr/logging/log_frontend_stmesp.h index 38f33bf62f1..c30972319fa 100644 --- a/include/zephyr/logging/log_frontend_stmesp.h +++ b/include/zephyr/logging/log_frontend_stmesp.h @@ -9,7 +9,7 @@ #include #include #ifdef CONFIG_LOG_FRONTEND_STMESP -#include +#include #endif #ifdef __cplusplus diff --git a/samples/boards/nordic/coresight_stm/pytest/test_stm.py b/samples/boards/nordic/coresight_stm/pytest/test_stm.py index 4af24fbfa3c..6db0b568575 100644 --- a/samples/boards/nordic/coresight_stm/pytest/test_stm.py +++ b/samples/boards/nordic/coresight_stm/pytest/test_stm.py @@ -20,7 +20,7 @@ SB_CONFIG_APP_CPUFLPR_RUN = None # See definition of stm_m_id[] and stm_m_name[] in -# https://github.com/zephyrproject-rtos/zephyr/blob/main/drivers/misc/coresight/nrf_etr.c +# https://github.com/zephyrproject-rtos/zephyr/blob/main/drivers/debug/debug_nrf_etr.c STM_M_ID = { "sec": 33, "app": 34, diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp index 674b5433c14..86149e5bd0e 100644 --- a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp @@ -9,7 +9,7 @@ config NUM_IRQS default 471 config SHELL_BACKEND_SERIAL - default n if NRF_ETR_SHELL + default n if DEBUG_NRF_ETR_SHELL config POWER_DOMAIN default y diff --git a/subsys/logging/frontends/Kconfig b/subsys/logging/frontends/Kconfig index 6e560276357..8bad85c6981 100644 --- a/subsys/logging/frontends/Kconfig +++ b/subsys/logging/frontends/Kconfig @@ -46,7 +46,7 @@ config LOG_FRONTEND_STMESP_DICT config LOG_FRONTEND_STMESP_FSC bool "Send fully self-contained messages" - select LOG_MSG_APPEND_RO_STRING_LOC if !(NRF_ETR || \ + select LOG_MSG_APPEND_RO_STRING_LOC if !(DEBUG_NRF_ETR || \ SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR) config LOG_FRONTEND_STMESP_FLUSH_COUNT @@ -70,7 +70,7 @@ config LOG_FRONTEND_STMESP_DICT_VER config LOG_FRONTEND_STMESP_TURBO_LOG bool "Optimize short_logs" select LOG_CUSTOM_HEADER - default y if (NRF_ETR || SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR) \ + default y if (DEBUG_NRF_ETR || SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR) \ && LOG_FRONTEND_STMESP_FSC help When enabled, then logging messages with 0 and 1 numeric argument are diff --git a/subsys/logging/frontends/log_frontend_stmesp.c b/subsys/logging/frontends/log_frontend_stmesp.c index 0ede3cb4890..7cdd16ffdd3 100644 --- a/subsys/logging/frontends/log_frontend_stmesp.c +++ b/subsys/logging/frontends/log_frontend_stmesp.c @@ -11,8 +11,8 @@ #include #include #include -#ifdef CONFIG_NRF_ETR -#include +#ifdef CONFIG_DEBUG_NRF_ETR +#include #endif /* Only 32 bit platforms supported. */ @@ -574,15 +574,16 @@ void log_frontend_simple_2(const void *source, uint32_t level, const char *fmt, void log_frontend_panic(void) { in_panic = true; -#ifdef CONFIG_NRF_ETR - nrf_etr_flush(); +#ifdef CONFIG_DEBUG_NRF_ETR + debug_nrf_etr_flush(); #endif } void log_frontend_init(void) { -#if defined(CONFIG_LOG_FRONTEND_STPESP_TURBO_SOURCE_PORT_ID) && !defined(CONFIG_NRF_ETR) && \ - !defined(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) +#if defined(CONFIG_LOG_FRONTEND_STPESP_TURBO_SOURCE_PORT_ID) \ + && !defined(CONFIG_DEBUG_NRF_ETR) \ + && !defined(CONFIG_LOG_MSG_APPEND_RO_STRING_LOC) /* Send location of section with constant source data. It is used by the * application core to retrieve source names of log messages coming from * coprocessors (FLPR and PPR). From 8082f49d4d27f767ebdd05b302f6566516e6ca37 Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Wed, 27 Aug 2025 21:38:40 +0200 Subject: [PATCH 07/14] [nrf fromtree] drivers: pinctrl_nrf: Add coresight tpiu pins Pinctrl needs to set the needed drive and direction of the pins. Also this later allows automatically setting the clock bit for the traceclk pin. Signed-off-by: Karsten Koenig (cherry picked from commit 85363f9e53e566e32fc10030f05fa28aa5d1bee4) --- .../nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi | 11 +++++++++++ drivers/pinctrl/pinctrl_nrf.c | 11 +++++++++++ include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h | 12 +++++++++++- soc/nordic/common/uicr/gen_periphconf_entries.py | 8 ++++++++ soc/nordic/common/uicr/periphconf/builder.py | 8 ++++++++ 5 files changed, 49 insertions(+), 1 deletion(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi index f62df87dfe2..0e2ab313df9 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi @@ -138,4 +138,15 @@ low-power-enable; }; }; + + /omit-if-no-ref/ tpiu_default: tpiu_default { + group1 { + psels = , + , + , + , + ; + nordic,drive-mode = ; + }; + }; }; diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index 4c916a263e7..e350e61f0af 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -558,6 +558,17 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, input = NRF_GPIO_PIN_INPUT_CONNECT; break; #endif /* defined(NRF_PSEL_TWIS) */ +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_coresight_nrf) + /* Pin routing is controlled by secure domain, via UICR */ + case NRF_FUN_TPIU_CLOCK: + case NRF_FUN_TPIU_DATA0: + case NRF_FUN_TPIU_DATA1: + case NRF_FUN_TPIU_DATA2: + case NRF_FUN_TPIU_DATA3: + dir = NRF_GPIO_PIN_DIR_OUTPUT; + input = NRF_GPIO_PIN_INPUT_DISCONNECT; + break; +#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_coresight_nrf) */ default: return -ENOTSUP; } diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h index 42b302193ed..92e62a9a6be 100644 --- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h @@ -187,7 +187,17 @@ /** TDM MCK */ #define NRF_FUN_TDM_MCK 77U /** SPI master CSN */ -#define NRF_FUN_SPIM_CSN 78U +#define NRF_FUN_SPIM_CSN 78U +/** TPIU CLOCK */ +#define NRF_FUN_TPIU_CLOCK 79U +/** TPIU DATA0 */ +#define NRF_FUN_TPIU_DATA0 80U +/** TPIU DATA1 */ +#define NRF_FUN_TPIU_DATA1 81U +/** TPIU DATA2 */ +#define NRF_FUN_TPIU_DATA2 82U +/** TPIU DATA3 */ +#define NRF_FUN_TPIU_DATA3 83U /** @} */ diff --git a/soc/nordic/common/uicr/gen_periphconf_entries.py b/soc/nordic/common/uicr/gen_periphconf_entries.py index 4308df31449..d3b79e43f14 100644 --- a/soc/nordic/common/uicr/gen_periphconf_entries.py +++ b/soc/nordic/common/uicr/gen_periphconf_entries.py @@ -425,6 +425,14 @@ def lookup_tables_get(soc: Soc) -> SocLookupTables: NrfPsel(fun=NrfFun.IGNORE, port=2, pin=10): Ctrlsel.CAN, NrfPsel(fun=NrfFun.IGNORE, port=2, pin=11): Ctrlsel.CAN, }, + # Coresight (TPIU) + 0xBF04_0000: { + NrfPsel(fun=NrfFun.TPIU_CLOCK, port=7, pin=3): Ctrlsel.TND, + NrfPsel(fun=NrfFun.TPIU_DATA0, port=7, pin=4): Ctrlsel.TND, + NrfPsel(fun=NrfFun.TPIU_DATA1, port=7, pin=5): Ctrlsel.TND, + NrfPsel(fun=NrfFun.TPIU_DATA2, port=7, pin=6): Ctrlsel.TND, + NrfPsel(fun=NrfFun.TPIU_DATA3, port=7, pin=7): Ctrlsel.TND, + }, } elif soc == Soc.NRF9280: ctrlsel_lookup = { diff --git a/soc/nordic/common/uicr/periphconf/builder.py b/soc/nordic/common/uicr/periphconf/builder.py index 1a343dee44a..b8387fd9a75 100644 --- a/soc/nordic/common/uicr/periphconf/builder.py +++ b/soc/nordic/common/uicr/periphconf/builder.py @@ -41,6 +41,9 @@ "nordic,nrf-temp", "nordic,nrf-vevif-task-tx", "nordic,nrf-vevif-task-rx", + # No retention in TDD so permissions can't be set outside of the TDD service + "nordic,coresight-nrf", + "nordic,nrf-tbm", } # Compatibles of global peripherals that should be assigned to the current core but do not have DMA @@ -1018,6 +1021,11 @@ class NrfFun(int, enum.Enum): TDM_SDOUT = 76 TDM_MCK = 77 SPIM_CSN = 78 + TPIU_CLOCK = 79 + TPIU_DATA0 = 80 + TPIU_DATA1 = 81 + TPIU_DATA2 = 82 + TPIU_DATA3 = 83 # Value used to ignore the function field and only check (port, pin) IGNORE = -1 From ae84f7af1dcdb9af581d0b6b39b5be97317e58d9 Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Wed, 27 Aug 2025 21:41:39 +0200 Subject: [PATCH 08/14] [nrf fromtree] drivers: debub: coresight: Added coresight_nrf Added driver and bindings for the coresight nrf submodule. add integrated it for the nrf54h20. The coresight subsystem is a combination of ARM Coresight peripherals that get configured together to achieve a simplified configuration based on a desired operating mode. This also replaces the previous handling in the nrf54h20 soc.c which was powering the subsystem up but not configuring it. Signed-off-by: Karsten Koenig (cherry picked from commit 6066a427486d847260a43ca0424cf9bc8ad5daec) --- drivers/debug/CMakeLists.txt | 3 +- drivers/debug/Kconfig.nrf | 65 ++++ drivers/debug/coresight_arm.h | 208 +++++++++++++ drivers/debug/debug_coresight_nrf.c | 281 ++++++++++++++++++ drivers/debug/debug_nrf_etr.c | 13 +- dts/bindings/arm/nordic,nrf-tddconf.yaml | 44 --- dts/bindings/debug/nordic,coresight-nrf.yaml | 22 ++ dts/vendor/nordic/nrf54h20.dtsi | 79 ++++- .../zephyr/dt-bindings/misc/nordic-tddconf.h | 15 - .../common/uicr/gen_periphconf_entries.py | 4 + soc/nordic/nrf54h/Kconfig | 11 - soc/nordic/nrf54h/soc.c | 18 -- 12 files changed, 669 insertions(+), 94 deletions(-) create mode 100644 drivers/debug/coresight_arm.h create mode 100644 drivers/debug/debug_coresight_nrf.c delete mode 100644 dts/bindings/arm/nordic,nrf-tddconf.yaml create mode 100644 dts/bindings/debug/nordic,coresight-nrf.yaml delete mode 100644 include/zephyr/dt-bindings/misc/nordic-tddconf.h diff --git a/drivers/debug/CMakeLists.txt b/drivers/debug/CMakeLists.txt index 8314379f8fa..29763be07ec 100644 --- a/drivers/debug/CMakeLists.txt +++ b/drivers/debug/CMakeLists.txt @@ -4,6 +4,7 @@ zephyr_library() # zephyr-keep-sorted-start -zephyr_library_sources_ifdef(CONFIG_DEBUG_SILABS_PTI debug_silabs_pti.c) +zephyr_library_sources_ifdef(CONFIG_DEBUG_CORESIGHT_NRF debug_coresight_nrf.c) zephyr_library_sources_ifdef(CONFIG_DEBUG_NRF_ETR debug_nrf_etr.c) +zephyr_library_sources_ifdef(CONFIG_DEBUG_SILABS_PTI debug_silabs_pti.c) # zephyr-keep-sorted-stop diff --git a/drivers/debug/Kconfig.nrf b/drivers/debug/Kconfig.nrf index da2721947e1..030e9885a06 100644 --- a/drivers/debug/Kconfig.nrf +++ b/drivers/debug/Kconfig.nrf @@ -111,3 +111,68 @@ config DEBUG_NRF_ETR_SHELL_ASYNC_RX_BUFFER_COUNT endif # DEBUG_NRF_ETR_SHELL endif # DEBUG_NRF_ETR + +menuconfig DEBUG_CORESIGHT_NRF + bool "Coresight Trace support" + default y + depends on DT_HAS_NORDIC_CORESIGHT_NRF_ENABLED + select PINCTRL + select NRF_IRONSIDE_TDD_SERVICE + help + Support CoreSight peripherals in Test and Debug Domain for ARM + CoreSight System Trace Macrocell (STM) trace support. + +if DEBUG_CORESIGHT_NRF + +config DEBUG_CORESIGHT_NRF_ATB_TRACE_ID_STM_GLOBAL + def_hex 0x40 + help + Global trace ID used by STM. + +config DEBUG_CORESIGHT_NRF_STM_SYNC_BYTE_COUNT + int "STM: Emit synhronization packet every N bytes" + range 0 4095 + default 512 + +config DEBUG_CORESIGHT_NRF_STM_HWEVENTS + bool "STM: Enable hardware events" + help + Enable the output of hardware events in STM. + +config DEBUG_CORESIGHT_NRF_TPIU_FFCR_TRIG + bool "TPIU: Use flush request trigger" + default y + help + Use CTI channel 1 for triggering flush request in TPIU. + +config DEBUG_CORESIGHT_NRF_TPIU_SYNC_FRAME_COUNT + int "TPIU: Emit synchronisation packet every N frames" + default 8 + +config DEBUG_CORESIGHT_NRF_TPIU_PORTSIZE + int "TPIU: Size of the current TPIU port in bits" + range 1 32 + default 4 + +config DEBUG_CORESIGHT_NRF_ATBFUNNEL_HOLD_TIME + int "ATBFUNNEL: Hold time for the transaction" + range 1 15 + default 4 + help + Number of transactions that are output on the funnel master port from the + same slave. + +config DEBUG_CORESIGHT_NRF_TSGEN_CLK_DIV + int + default 8 + help + Clock division factor for generating trace timestamps. The timestamp + counter should not be slower than 10% of the fastest processor clock + frequency in the system, therefore its clock speed is divided by + eight. + +module = DEBUG_CORESIGHT_NRF +module-str = CoreSight Trace +source "subsys/logging/Kconfig.template.log_config" + +endif # DEBUG_CORESIGHT_NRF diff --git a/drivers/debug/coresight_arm.h b/drivers/debug/coresight_arm.h new file mode 100644 index 00000000000..b0c5da3e92d --- /dev/null +++ b/drivers/debug/coresight_arm.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef CORESIGHT_ARM_H_ +#define CORESIGHT_ARM_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file + * @brief Generic ARM CoreSight Hardware Abstraction Layer + * + * This HAL provides generic register definitions and utility functions for ARM CoreSight + * peripherals. Platform-specific drivers should provide base addresses and use these + * generic definitions for register access. + */ + +/* Common CoreSight unlock key as defined by ARM architecture */ +#define CORESIGHT_UNLOCK_KEY (0xC5ACCE55UL) + +/* CoreSight register offsets */ + +/* Common CoreSight peripheral register offsets (found at the end of all CoreSight peripherals) */ +#define CORESIGHT_CLAIMSET_OFFSET (0xFA0UL) /* Claim Tag Set Register */ +#define CORESIGHT_CLAIMCLR_OFFSET (0xFA4UL) /* Claim Tag Clear Register */ +#define CORESIGHT_LAR_OFFSET (0xFB0UL) /* Lock Access Register */ +#define CORESIGHT_LSR_OFFSET (0xFB4UL) /* Lock Status Register */ + +/* ATB Funnel register offsets */ +#define ATBFUNNEL_CTRLREG_OFFSET (0x000UL) /* Control Register */ + +/* ATB Replicator register offsets */ +#define ATBREPLICATOR_IDFILTER0_OFFSET (0x000UL) /* ID Filter Register 0 */ +#define ATBREPLICATOR_IDFILTER1_OFFSET (0x004UL) /* ID Filter Register 1 */ + +/* ETR (Embedded Trace Router/TMC-ETR) register offsets */ +#define ETR_RSZ_OFFSET (0x004UL) /* RAM Size Register */ +#define ETR_RWP_OFFSET (0x018UL) /* RAM Write Pointer Register */ +#define ETR_CTL_OFFSET (0x020UL) /* Control Register */ +#define ETR_MODE_OFFSET (0x028UL) /* Mode Register */ +#define ETR_DBALO_OFFSET (0x118UL) /* Data Buffer Address Low Register */ +#define ETR_DBAHI_OFFSET (0x11CUL) /* Data Buffer Address High Register */ +#define ETR_FFCR_OFFSET (0x304UL) /* Formatter and Flush Control Register */ + +/* STM (System Trace Macrocell) register offsets */ +#define STM_STMHEER_OFFSET (0xD00UL) /* Hardware Event Enable Register */ +#define STM_STMHEMCR_OFFSET (0xD64UL) /* Hardware Event Master Control Register */ +#define STM_STMSPER_OFFSET (0xE00UL) /* Stimulus Port Enable Register */ +#define STM_STMTCSR_OFFSET (0xE80UL) /* Trace Control and Status Register */ +#define STM_STMTSFREQR_OFFSET (0xE8CUL) /* Timestamp Frequency Register */ +#define STM_STMSYNCR_OFFSET (0xE90UL) /* Synchronization Control Register */ +#define STM_STMAUXCR_OFFSET (0xE94UL) /* Auxiliary Control Register */ + +/* TPIU (Trace Port Interface Unit) register offsets */ +#define TPIU_CSPSR_OFFSET (0x004UL) /* Current Parallel Port Size Register */ +#define TPIU_FFCR_OFFSET (0x304UL) /* Formatter and Flush Control Register */ +#define TPIU_FSCR_OFFSET (0x308UL) /* Formatter Synchronization Counter Register */ + +/* CTI (Cross Trigger Interface) register offsets */ +#define CTI_CTICONTROL_OFFSET (0x000UL) /* CTI Control Register */ +#define CTI_CTIOUTEN0_OFFSET (0x0A0UL) /* CTI Trigger Output Enable Register 0 */ +#define CTI_CTIGATE_OFFSET (0x140UL) /* CTI Channel Gate Enable Register */ + +/* TSGEN (Timestamp Generator) register offsets */ +#define TSGEN_CNTCR_OFFSET (0x000UL) /* Counter Control Register */ +#define TSGEN_CNTFID0_OFFSET (0x020UL) /* Counter Frequency ID Register 0 */ + +/* Lock Status Register (LSR) bit fields */ +#define CORESIGHT_LSR_LOCKED_Pos (1UL) +#define CORESIGHT_LSR_LOCKED_Msk (0x1UL << CORESIGHT_LSR_LOCKED_Pos) +#define CORESIGHT_LSR_PRESENT_Pos (0UL) +#define CORESIGHT_LSR_PRESENT_Msk (0x1UL << CORESIGHT_LSR_PRESENT_Pos) + +/* STM Trace Control and Status Register (STMTCSR) bit fields */ +#define STM_STMTCSR_EN_Pos (0UL) +#define STM_STMTCSR_EN_Msk (0x1UL << STM_STMTCSR_EN_Pos) +#define STM_STMTCSR_TSEN_Pos (1UL) +#define STM_STMTCSR_TSEN_Msk (0x1UL << STM_STMTCSR_TSEN_Pos) +#define STM_STMTCSR_TRACEID_Pos (16UL) +#define STM_STMTCSR_TRACEID_Msk (0x7FUL << STM_STMTCSR_TRACEID_Pos) + +/* STM Hardware Event Master Control Register (STMHEMCR) bit fields */ +#define STM_STMHEMCR_EN_Pos (0UL) +#define STM_STMHEMCR_EN_Msk (0x1UL << STM_STMHEMCR_EN_Pos) + +/* STM Auxiliary Control Register (STMAUXCR) bit fields */ +#define STM_STMAUXCR_FIFOAF_Pos (0UL) +#define STM_STMAUXCR_FIFOAF_Msk (0x1UL << STM_STMAUXCR_FIFOAF_Pos) + +/* CTI Control Register (CTICONTROL) bit fields */ +#define CTI_CTICONTROL_GLBEN_Pos (0UL) +#define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos) + +/* TPIU Formatter and Flush Control Register (FFCR) bit fields */ +#define TPIU_FFCR_ENFCONT_Pos (1UL) +#define TPIU_FFCR_ENFCONT_Msk (0x1UL << TPIU_FFCR_ENFCONT_Pos) +#define TPIU_FFCR_FONFLIN_Pos (4UL) +#define TPIU_FFCR_FONFLIN_Msk (0x1UL << TPIU_FFCR_FONFLIN_Pos) +#define TPIU_FFCR_ENFTC_Pos (0UL) +#define TPIU_FFCR_ENFTC_Msk (0x1UL << TPIU_FFCR_ENFTC_Pos) + +/* ETR Mode Register bit fields */ +#define ETR_MODE_MODE_Pos (0UL) +#define ETR_MODE_MODE_Msk (0x3UL << ETR_MODE_MODE_Pos) +#define ETR_MODE_MODE_CIRCULARBUF (0UL) /* Circular Buffer mode */ +#define ETR_MODE_MODE_SWFIFO1 (1UL) /* Software FIFO mode */ +#define ETR_MODE_MODE_HWFIFO (2UL) /* Hardware FIFO mode */ +#define ETR_MODE_MODE_SWFIFO2 (3UL) /* Software FIFO mode */ + +/* ETR Control Register bit fields */ +#define ETR_CTL_TRACECAPTEN_Pos (0UL) +#define ETR_CTL_TRACECAPTEN_Msk (0x1UL << ETR_CTL_TRACECAPTEN_Pos) + +/* ETR Formatter and Flush Control Register (FFCR) bit fields */ +#define ETR_FFCR_ENFT_Pos (0UL) +#define ETR_FFCR_ENFT_Msk (0x1UL << ETR_FFCR_ENFT_Pos) +#define ETR_FFCR_ENTI_Pos (1UL) +#define ETR_FFCR_ENTI_Msk (0x1UL << ETR_FFCR_ENTI_Pos) + +/* ATB Funnel Control Register bit fields */ +#define ATBFUNNEL_CTRLREG_ENS0_Pos (0UL) +#define ATBFUNNEL_CTRLREG_ENS0_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS0_Pos) +#define ATBFUNNEL_CTRLREG_ENS1_Pos (1UL) +#define ATBFUNNEL_CTRLREG_ENS1_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS1_Pos) +#define ATBFUNNEL_CTRLREG_ENS2_Pos (2UL) +#define ATBFUNNEL_CTRLREG_ENS2_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS2_Pos) +#define ATBFUNNEL_CTRLREG_ENS3_Pos (3UL) +#define ATBFUNNEL_CTRLREG_ENS3_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS3_Pos) +#define ATBFUNNEL_CTRLREG_ENS4_Pos (4UL) +#define ATBFUNNEL_CTRLREG_ENS4_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS4_Pos) +#define ATBFUNNEL_CTRLREG_ENS5_Pos (5UL) +#define ATBFUNNEL_CTRLREG_ENS5_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS5_Pos) +#define ATBFUNNEL_CTRLREG_ENS6_Pos (6UL) +#define ATBFUNNEL_CTRLREG_ENS6_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS6_Pos) +#define ATBFUNNEL_CTRLREG_ENS7_Pos (7UL) +#define ATBFUNNEL_CTRLREG_ENS7_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS7_Pos) +#define ATBFUNNEL_CTRLREG_HT_Pos (8UL) +#define ATBFUNNEL_CTRLREG_HT_Msk (0xFUL << ATBFUNNEL_CTRLREG_HT_Pos) + +/* TSGEN Counter Control Register bit fields */ +#define TSGEN_CNTCR_EN_Pos (0UL) +#define TSGEN_CNTCR_EN_Msk (0x1UL << TSGEN_CNTCR_EN_Pos) + +/** + * @brief Check if a CoreSight peripheral is locked + * + * @param base_addr Base address of CoreSight peripheral + * @return true if peripheral is locked, false otherwise + */ +static inline bool coresight_is_locked(mem_addr_t base_addr) +{ + uint32_t lsr = *(volatile uint32_t *)(base_addr + CORESIGHT_LSR_OFFSET); + + return (lsr & CORESIGHT_LSR_LOCKED_Msk) != 0; +} + +/** + * @brief Unlock a CoreSight peripheral + * + * @param base_addr Base address of CoreSight peripheral + * @retval 0 on success + * @retval -EIO if unlock operation failed + */ +static inline int coresight_unlock(mem_addr_t base_addr) +{ + *(volatile uint32_t *)(base_addr + CORESIGHT_LAR_OFFSET) = CORESIGHT_UNLOCK_KEY; + + if (coresight_is_locked(base_addr)) { + return -EIO; + } + + return 0; +} + +/** + * @brief Lock a CoreSight peripheral + * + * @param base_addr Base address of CoreSight peripheral + * @retval 0 on success + * @retval -EIO if lock operation failed + */ +static inline int coresight_lock(mem_addr_t base_addr) +{ + /* Write any value other than unlock key to Lock Access Register to lock */ + *(volatile uint32_t *)(base_addr + CORESIGHT_LAR_OFFSET) = 0x00000000; + + if (!coresight_is_locked(base_addr)) { + return -EIO; + } + + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* CORESIGHT_ARM_H_ */ diff --git a/drivers/debug/debug_coresight_nrf.c b/drivers/debug/debug_coresight_nrf.c new file mode 100644 index 00000000000..7bc9bab68ee --- /dev/null +++ b/drivers/debug/debug_coresight_nrf.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +#undef ETR_MODE_MODE_CIRCULARBUF + +#include "coresight_arm.h" + +#define DT_DRV_COMPAT nordic_coresight_nrf + +#include +LOG_MODULE_REGISTER(cs_trace, CONFIG_DEBUG_CORESIGHT_NRF_LOG_LEVEL); + +#define CTI_CH_TPIU_FLUSH_REQ_OFFSET (1) + +#define TS_CLOCKRATE \ + (DT_PROP(DT_NODELABEL(hsfll200), clock_frequency) / \ + CONFIG_DEBUG_CORESIGHT_NRF_TSGEN_CLK_DIV) + +#define ATBREPLICATOR_IDFILTER_FORWARD_STM \ + BIT(CONFIG_DEBUG_CORESIGHT_NRF_ATB_TRACE_ID_STM_GLOBAL >> 4) +#define ATBFUNNEL211_STM_ENS_MASK BIT(2) + +enum coresight_nrf_mode { + CORESIGHT_NRF_MODE_UNCONFIGURED, + CORESIGHT_NRF_MODE_STM_TPIU, + CORESIGHT_NRF_MODE_STM_ETR, +}; + +struct coresight_nrf_config { + enum coresight_nrf_mode mode; + const struct pinctrl_dev_config *pcfg; +}; + +static void nrf_tsgen_init(void) +{ + mem_addr_t tsgen = DT_REG_ADDR(DT_NODELABEL(tsgen)); + + coresight_unlock(tsgen); + + sys_write32(TS_CLOCKRATE, tsgen + TSGEN_CNTFID0_OFFSET); + sys_write32(TSGEN_CNTCR_EN_Msk, tsgen + TSGEN_CNTCR_OFFSET); + + coresight_lock(tsgen); + + LOG_INF("CoreSight Host TSGEN initialized with clockrate %u", TS_CLOCKRATE); +} + +static void nrf_cti_for_tpiu_init(void) +{ + mem_addr_t cti210 = DT_REG_ADDR(DT_NODELABEL(cti210)); + + coresight_unlock(cti210); + + /* Connect CTI channel to TPIU formatter flushin */ + sys_write32(BIT(CTI_CH_TPIU_FLUSH_REQ_OFFSET), cti210 + CTI_CTIOUTEN0_OFFSET); + sys_write32(BIT(CTI_CH_TPIU_FLUSH_REQ_OFFSET), cti210 + CTI_CTIGATE_OFFSET); + sys_write32(CTI_CTICONTROL_GLBEN_Msk, cti210 + CTI_CTICONTROL_OFFSET); + + coresight_lock(cti210); + + LOG_INF("CoreSight Host CTI initialized"); +} + +static void nrf_tpiu_init(void) +{ + mem_addr_t tpiu = DT_REG_ADDR(DT_NODELABEL(tpiu)); + + coresight_unlock(tpiu); + + sys_write32(BIT((CONFIG_DEBUG_CORESIGHT_NRF_TPIU_PORTSIZE - 1)), tpiu + TPIU_CSPSR_OFFSET); + + /* Continuous formatting */ + if (IS_ENABLED(CONFIG_DEBUG_CORESIGHT_NRF_TPIU_FFCR_TRIG)) { + sys_write32((TPIU_FFCR_ENFCONT_Msk | TPIU_FFCR_FONFLIN_Msk | TPIU_FFCR_ENFTC_Msk), + tpiu + TPIU_FFCR_OFFSET); + } else { + sys_write32((TPIU_FFCR_ENFCONT_Msk | TPIU_FFCR_ENFTC_Msk), tpiu + TPIU_FFCR_OFFSET); + } + + sys_write32(CONFIG_DEBUG_CORESIGHT_NRF_TPIU_SYNC_FRAME_COUNT, tpiu + TPIU_FSCR_OFFSET); + + coresight_lock(tpiu); + + LOG_INF("CoreSight Host TPIU initialized"); +} + +static void nrf_etr_init(uintptr_t buf, size_t buf_word_len) +{ + mem_addr_t etr = DT_REG_ADDR(DT_NODELABEL(etr)); + + coresight_unlock(etr); + + sys_write32(buf_word_len, etr + ETR_RSZ_OFFSET); + sys_write32(buf, etr + ETR_RWP_OFFSET); + sys_write32(buf, etr + ETR_DBALO_OFFSET); + sys_write32(0UL, etr + ETR_DBAHI_OFFSET); + sys_write32(ETR_FFCR_ENFT_Msk, etr + ETR_FFCR_OFFSET); + sys_write32(ETR_MODE_MODE_CIRCULARBUF, etr + ETR_MODE_OFFSET); + sys_write32(ETR_CTL_TRACECAPTEN_Msk, etr + ETR_CTL_OFFSET); + + coresight_lock(etr); + + LOG_INF("Coresight Host ETR initialized"); +} + +static void nrf_stm_init(void) +{ + mem_addr_t stm = DT_REG_ADDR(DT_NODELABEL(stm)); + + coresight_unlock(stm); + + sys_write32(1, stm + STM_STMAUXCR_OFFSET); + + sys_write32(TS_CLOCKRATE, stm + STM_STMTSFREQR_OFFSET); + + sys_write32((CONFIG_DEBUG_CORESIGHT_NRF_STM_SYNC_BYTE_COUNT & 0xFFF), + stm + STM_STMSYNCR_OFFSET); + + sys_write32(0xFFFFFFFF, stm + STM_STMSPER_OFFSET); + + if (IS_ENABLED(CONFIG_DEBUG_CORESIGHT_NRF_STM_HWEVENTS)) { + sys_write32(0xFFFFFFFF, stm + STM_STMHEER_OFFSET); + sys_write32((1 << STM_STMHEMCR_EN_Pos), stm + STM_STMHEMCR_OFFSET); + } + + sys_write32(((CONFIG_DEBUG_CORESIGHT_NRF_ATB_TRACE_ID_STM_GLOBAL & STM_STMTCSR_TRACEID_Msk) + << STM_STMTCSR_TRACEID_Pos) | + (1 << STM_STMTCSR_EN_Pos) | (1 << STM_STMTCSR_TSEN_Pos), + stm + STM_STMTCSR_OFFSET); + + coresight_lock(stm); + + LOG_INF("CoreSight STM initialized with clockrate %u", TS_CLOCKRATE); +} + +static void nrf_atbfunnel_init(mem_addr_t funnel_addr, uint32_t enable_set_mask) +{ + coresight_unlock(funnel_addr); + + uint32_t ctrlreg_old = sys_read32(funnel_addr + ATBFUNNEL_CTRLREG_OFFSET); + + const uint32_t funnel_hold_time = (((CONFIG_DEBUG_CORESIGHT_NRF_ATBFUNNEL_HOLD_TIME - 1) + << ATBFUNNEL_CTRLREG_HT_Pos) & + ATBFUNNEL_CTRLREG_HT_Msk); + + uint32_t ctrlreg_new = (ctrlreg_old & ~ATBFUNNEL_CTRLREG_HT_Msk) | funnel_hold_time | + (enable_set_mask & 0xFF); + + sys_write32(ctrlreg_new, funnel_addr + ATBFUNNEL_CTRLREG_OFFSET); + + coresight_lock(funnel_addr); +} + +static void nrf_atbreplicator_init(mem_addr_t replicator_addr, uint32_t filter, bool ch0_allow, + bool ch1_allow) +{ + coresight_unlock(replicator_addr); + + uint32_t ch0_current = sys_read32(replicator_addr + ATBREPLICATOR_IDFILTER0_OFFSET); + uint32_t ch1_current = sys_read32(replicator_addr + ATBREPLICATOR_IDFILTER1_OFFSET); + + if (ch0_allow) { + sys_write32(ch0_current & ~filter, + replicator_addr + ATBREPLICATOR_IDFILTER0_OFFSET); + } else { + sys_write32(ch0_current | filter, replicator_addr + ATBREPLICATOR_IDFILTER0_OFFSET); + } + + if (ch1_allow) { + sys_write32(ch1_current & ~filter, + replicator_addr + ATBREPLICATOR_IDFILTER1_OFFSET); + } else { + sys_write32(ch1_current | filter, replicator_addr + ATBREPLICATOR_IDFILTER1_OFFSET); + } + + coresight_lock(replicator_addr); +} + +static int coresight_nrf_init_stm_etr(uintptr_t buf, size_t buf_word_len) +{ + mem_addr_t atbfunnel211 = DT_REG_ADDR(DT_NODELABEL(atbfunnel211)); + mem_addr_t atbreplicator210 = DT_REG_ADDR(DT_NODELABEL(atbreplicator210)); + mem_addr_t atbreplicator213 = DT_REG_ADDR(DT_NODELABEL(atbreplicator213)); + + nrf_atbfunnel_init(atbfunnel211, ATBFUNNEL211_STM_ENS_MASK); + nrf_atbreplicator_init(atbreplicator210, ATBREPLICATOR_IDFILTER_FORWARD_STM, false, true); + nrf_atbreplicator_init(atbreplicator213, ATBREPLICATOR_IDFILTER_FORWARD_STM, false, true); + + nrf_tsgen_init(); + nrf_etr_init(buf, buf_word_len); + nrf_stm_init(); + + return 0; +} + +static int coresight_nrf_init_stm_tpiu(void) +{ + mem_addr_t atbfunnel211 = DT_REG_ADDR(DT_NODELABEL(atbfunnel211)); + mem_addr_t atbreplicator210 = DT_REG_ADDR(DT_NODELABEL(atbreplicator210)); + mem_addr_t atbreplicator213 = DT_REG_ADDR(DT_NODELABEL(atbreplicator213)); + + nrf_atbfunnel_init(atbfunnel211, ATBFUNNEL211_STM_ENS_MASK); + nrf_atbreplicator_init(atbreplicator210, ATBREPLICATOR_IDFILTER_FORWARD_STM, false, true); + nrf_atbreplicator_init(atbreplicator213, ATBREPLICATOR_IDFILTER_FORWARD_STM, true, false); + + nrf_tsgen_init(); + nrf_cti_for_tpiu_init(); + nrf_tpiu_init(); + nrf_stm_init(); + + return 0; +} + +static int coresight_nrf_init(const struct device *dev) +{ + int err; + struct coresight_nrf_config *cfg = (struct coresight_nrf_config *)dev->config; + + if (cfg->pcfg) { + err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (err) { + LOG_ERR("Failed to configure pins (%d)", err); + return err; + } + } + + err = ironside_se_tdd_configure(IRONSIDE_SE_TDD_CONFIG_ON_DEFAULT); + if (err) { + LOG_ERR("Failed to configure TDD (%d)", err); + return err; + } + + switch (cfg->mode) { + case CORESIGHT_NRF_MODE_UNCONFIGURED: { + return 0; + } + case CORESIGHT_NRF_MODE_STM_TPIU: { + return coresight_nrf_init_stm_tpiu(); + } + case CORESIGHT_NRF_MODE_STM_ETR: { + uintptr_t etr_buffer = DT_REG_ADDR(DT_NODELABEL(etr_buffer)); + size_t buf_word_len = DT_REG_SIZE(DT_NODELABEL(etr_buffer)) / sizeof(uint32_t); + + return coresight_nrf_init_stm_etr(etr_buffer, buf_word_len); + } + default: { + LOG_ERR("Unsupported Coresight mode"); + return -ENOTSUP; + } + } + return 0; +} + +#define DEBUG_CORESIGHT_NRF_INIT_PRIORITY UTIL_INC(CONFIG_NRF_IRONSIDE_CALL_INIT_PRIORITY) + +#define CORESIGHT_NRF_INST(inst) \ + COND_CODE_1(DT_INST_PINCTRL_HAS_IDX(inst, 0), \ + (PINCTRL_DT_INST_DEFINE(inst);), ()) \ + \ + static struct coresight_nrf_config coresight_nrf_cfg_##inst = { \ + .mode = _CONCAT(CORESIGHT_NRF_MODE_, \ + DT_STRING_UPPER_TOKEN(DT_DRV_INST(inst), mode)), \ + .pcfg = COND_CODE_1(DT_INST_PINCTRL_HAS_IDX(inst, 0), \ + (PINCTRL_DT_INST_DEV_CONFIG_GET(inst)), \ + (NULL)) }; \ + \ + DEVICE_DT_INST_DEFINE(inst, coresight_nrf_init, NULL, NULL, &coresight_nrf_cfg_##inst, \ + POST_KERNEL, DEBUG_CORESIGHT_NRF_INIT_PRIORITY, NULL); + +DT_INST_FOREACH_STATUS_OKAY(CORESIGHT_NRF_INST) diff --git a/drivers/debug/debug_nrf_etr.c b/drivers/debug/debug_nrf_etr.c index da425716dbb..d536cd4a9f4 100644 --- a/drivers/debug/debug_nrf_etr.c +++ b/drivers/debug/debug_nrf_etr.c @@ -768,6 +768,7 @@ int etr_process_init(void) IRQ_CONNECT(DT_IRQN(DT_NODELABEL(tbm)), DT_IRQ(DT_NODELABEL(tbm), priority), nrfx_isr, nrfx_tbm_irq_handler, 0); irq_enable(DT_IRQN(DT_NODELABEL(tbm))); + nrfx_tbm_start(); #ifdef CONFIG_DEBUG_NRF_ETR_SHELL uint32_t level = CONFIG_LOG_MAX_LEVEL; @@ -791,7 +792,17 @@ int etr_process_init(void) return 0; } -SYS_INIT(etr_process_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +#define NRF_ETR_INIT_PRIORITY UTIL_INC(UTIL_INC(CONFIG_NRF_IRONSIDE_CALL_INIT_PRIORITY)) + +SYS_INIT(etr_process_init, POST_KERNEL, NRF_ETR_INIT_PRIORITY); + +#if defined(CONFIG_NORDIC_VPR_LAUNCHER) && defined(CONFIG_LOG_FRONTEND_STMESP_FSC) +/* TDD/ETR must be up and running before VPR cores are started as they write to + * ETR some vital initial data that cannot be lost. + */ +BUILD_ASSERT(CONFIG_NORDIC_VPR_LAUNCHER_INIT_PRIORITY > NRF_ETR_INIT_PRIORITY); +#endif + #ifdef CONFIG_DEBUG_NRF_ETR_SHELL diff --git a/dts/bindings/arm/nordic,nrf-tddconf.yaml b/dts/bindings/arm/nordic,nrf-tddconf.yaml deleted file mode 100644 index 2273082c12f..00000000000 --- a/dts/bindings/arm/nordic,nrf-tddconf.yaml +++ /dev/null @@ -1,44 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - Nordic TRACE and Debug Domain - - Configuration for the Trace and Debug subsystem - -compatible: "nordic,nrf-tddconf" - -include: base.yaml - -properties: - etbsources: - type: int - description: | - Bitmask of enabled sources for the ETB sink. Valid values can be found in - dt-bindings/misc/nordic-tddconf.h - - tpiusources: - type: int - description: | - Bitmask of enabled sources for the TPIU sink. Valid values can be found in - dt-bindings/misc/nordic-tddconf.h - - etrsources: - type: int - description: | - Bitmask of enabled sources for the ETR sink. Valid values can be found in - dt-bindings/misc/nordic-tddconf.h - - portconfig: - type: int - default: 3 - description: TPIU clock divider - TDD HSFLL / 2^(2 + portconfig) - enum: - - 0 - - 1 - - 2 - - 3 - - etrbuffer: - description: phandle to the memory region used for the ETR buffer - type: phandle diff --git a/dts/bindings/debug/nordic,coresight-nrf.yaml b/dts/bindings/debug/nordic,coresight-nrf.yaml new file mode 100644 index 00000000000..fec4f37ce5a --- /dev/null +++ b/dts/bindings/debug/nordic,coresight-nrf.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic Coresight Subsystem (Trace Port Interface Unit) + +compatible: "nordic,coresight-nrf" + +include: [base.yaml, pinctrl-device.yaml, nordic-clockpin.yaml] + +properties: + reg: + required: true + + mode: + required: true + type: string + enum: + - "unconfigured" + - "stm-tpiu" + - "stm-etr" + description: > + Specifies which mode to configure the Coresight subsystem in. diff --git a/dts/vendor/nordic/nrf54h20.dtsi b/dts/vendor/nordic/nrf54h20.dtsi index 56b807fafd4..62b9c39e3c6 100644 --- a/dts/vendor/nordic/nrf54h20.dtsi +++ b/dts/vendor/nordic/nrf54h20.dtsi @@ -13,7 +13,6 @@ #include #include #include -#include /delete-node/ &sw_pwm; @@ -541,10 +540,82 @@ interrupts = <127 NRF_DEFAULT_IRQ_PRIORITY>; }; - tddconf: tddconf@1000 { - compatible = "nordic,nrf-tddconf"; - reg = <0x1000 0x10>; + hsfll200: clock@4000 { + compatible = "fixed-clock"; + reg = <0x4000 0x1000>; + #clock-cells = <0>; + status = "disabled"; + clock-frequency = ; + }; + + coresight: coresight@40000 { + compatible = "nordic,coresight-nrf"; + reg = <0x40000 0x11000>; status = "disabled"; + nordic,clockpin-enable = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x11000>; + + tsgen: tsgen@1000 { + reg = <0x1000 0x1000>; + }; + + stm: stm@2000 { + reg = <0x2000 0x1000>; + }; + + tpiu: tpiu@3000 { + reg = <0x3000 0x1000>; + }; + + etb: etb@4000 { + reg = <0x4000 0x1000>; + }; + + etr: etr@5000 { + reg = <0x5000 0x1000>; + }; + + cti210: cti@6000 { + reg = <0x6000 0x1000>; + }; + + cti211: cti@7000 { + reg = <0x7000 0x1000>; + }; + + atbreplicator210: atbreplicator@8000 { + reg = <0x8000 0x1000>; + }; + + atbreplicator211: atbreplicator@9000 { + reg = <0x9000 0x1000>; + }; + + atbreplicator212: atbreplicator@A000 { + reg = <0xA000 0x1000>; + }; + + atbreplicator213: atbreplicator@B000 { + reg = <0xB000 0x1000>; + }; + + atbfunnel210: atbfunnel@C000 { + reg = <0xC000 0x1000>; + }; + + atbfunnel211: atbfunnel@D000 { + reg = <0xD000 0x1000>; + }; + + atbfunnel212: atbfunnel@E000 { + reg = <0xE000 0x1000>; + }; + + atbfunnel213: atbfunnel@F000 { + reg = <0xF000 0x1000>; + }; }; }; diff --git a/include/zephyr/dt-bindings/misc/nordic-tddconf.h b/include/zephyr/dt-bindings/misc/nordic-tddconf.h deleted file mode 100644 index 44bc74e491c..00000000000 --- a/include/zephyr/dt-bindings/misc/nordic-tddconf.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_ - -#define NRF_TDDCONF_SOURCE_STMMAINCORE BIT(0) -#define NRF_TDDCONF_SOURCE_ETMMAINCORE BIT(1) -#define NRF_TDDCONF_SOURCE_STMHWEVENTS BIT(2) -#define NRF_TDDCONF_SOURCE_STMPPR BIT(3) -#define NRF_TDDCONF_SOURCE_STMFLPR BIT(4) - -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_ */ diff --git a/soc/nordic/common/uicr/gen_periphconf_entries.py b/soc/nordic/common/uicr/gen_periphconf_entries.py index d3b79e43f14..9a273dab7a5 100644 --- a/soc/nordic/common/uicr/gen_periphconf_entries.py +++ b/soc/nordic/common/uicr/gen_periphconf_entries.py @@ -121,6 +121,10 @@ def main() -> None: for node in dt.label2node["global_peripherals"].children.values(): builder.add_global_peripheral_cfg(node, **get_additional_node_kwargs(node)) + # TDD (Trace and Debug Domain) peripherals - contains coresight/TPIU + for node in dt.label2node["tdd_peripherals"].children.values(): + builder.add_global_peripheral_cfg(node, **get_additional_node_kwargs(node)) + # Add pins referenced by 'gpios' properties on non-peripheral nodes, for example # buttons and leds. We only add SPU configurations for these and not CTRLSEL, # to avoid false CTRLSEL conflicts for things like PWM leds. diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig index a2ef5f1eb18..d4c86932a2c 100644 --- a/soc/nordic/nrf54h/Kconfig +++ b/soc/nordic/nrf54h/Kconfig @@ -66,17 +66,6 @@ config SOC_NRF54H20_CPURAD_COMMON select HAS_PM select HAS_POWEROFF -config SOC_NRF54H20_TDD_ENABLE - bool "Power and configure the trace and debug domain (TDD)" - depends on SOC_NRF54H20_CPUAPP - select NRF_IRONSIDE_TDD_SERVICE - select SOC_LATE_INIT_HOOK - help - This will at application boot time request that the trace and - debug domain (TDD) is powered up and configured. - This allows configuring the coresight peripherals from - the application domain. - config SOC_NRF54H20_CPURAD_ENABLE bool "Boot the nRF54H20 Radio core" default y if NRF_802154_SER_HOST || BT_HCI_HOST diff --git a/soc/nordic/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c index 6692425f674..3d1fdfe5c05 100644 --- a/soc/nordic/nrf54h/soc.c +++ b/soc/nordic/nrf54h/soc.c @@ -23,14 +23,10 @@ #include #include #include -#include #if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE) #include #endif -#if defined(CONFIG_SOC_NRF54H20_TDD_ENABLE) -#include -#endif LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); @@ -195,20 +191,6 @@ void soc_early_init_hook(void) void soc_late_init_hook(void) { -#if defined(CONFIG_SOC_NRF54H20_TDD_ENABLE) - int err_tdd; - - err_tdd = ironside_se_tdd_configure(IRONSIDE_SE_TDD_CONFIG_ON_DEFAULT); - __ASSERT(err_tdd == 0, "err_tdd was %d", err_tdd); - - UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 3, GPIO_PIN_CNF_CTRLSEL_TND); - UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 4, GPIO_PIN_CNF_CTRLSEL_TND); - UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 5, GPIO_PIN_CNF_CTRLSEL_TND); - UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 6, GPIO_PIN_CNF_CTRLSEL_TND); - UICR_GPIO_PIN_CNF_CTRLSEL_SET(NRF_P7, 7, GPIO_PIN_CNF_CTRLSEL_TND); - -#endif - #if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE) int err_cpuconf; From 1fa11a3dda6c6ec06a2dfa2032bec20dcbed2cbc Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Wed, 27 Aug 2025 21:42:37 +0200 Subject: [PATCH 09/14] [nrf fromtree] snippets: nordic-log-stm: Updated for coresight Replaced the old tddconf with the full coresight driver that configures the coresight peripherals locally on the running core. Also fixed minor bug in the corresponding sample where messages were not shown for the radio core. Signed-off-by: Karsten Koenig (cherry picked from commit 02fb6fa1c8df4e1401430f1012f2e3eb37f991bb) --- samples/boards/nordic/coresight_stm/prj.conf | 1 + .../nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay | 7 ++----- .../nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay | 9 --------- snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf | 1 + snippets/nordic/nordic-log-stm-dict/snippet.yml | 3 --- .../nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay | 7 ++----- .../nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay | 9 --------- snippets/nordic/nordic-log-stm/log_stm.conf | 1 + snippets/nordic/nordic-log-stm/snippet.yml | 3 --- 9 files changed, 7 insertions(+), 34 deletions(-) delete mode 100644 snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay delete mode 100644 snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay diff --git a/samples/boards/nordic/coresight_stm/prj.conf b/samples/boards/nordic/coresight_stm/prj.conf index 1e935e973c7..9ee7cf8cc03 100644 --- a/samples/boards/nordic/coresight_stm/prj.conf +++ b/samples/boards/nordic/coresight_stm/prj.conf @@ -1 +1,2 @@ CONFIG_LOG=y +CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y diff --git a/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay index fec54817364..962aa231b7a 100644 --- a/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay +++ b/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpuapp.overlay @@ -7,10 +7,7 @@ status = "okay"; }; -&tddconf { +&coresight { status = "okay"; - etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE | NRF_TDDCONF_SOURCE_STMPPR | - NRF_TDDCONF_SOURCE_STMFLPR)>; - portconfig = <0>; - etrbuffer = <&etr_buffer>; + mode = "stm-etr"; }; diff --git a/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay b/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay deleted file mode 100644 index 5bdeddd3c07..00000000000 --- a/snippets/nordic/nordic-log-stm-dict/boards/nrf54h20_cpurad.overlay +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -&tddconf { - status = "okay"; - etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE)>; -}; diff --git a/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf b/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf index 7384e36b92a..0bd8b46d387 100644 --- a/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf +++ b/snippets/nordic/nordic-log-stm-dict/log_stm_dict.conf @@ -3,3 +3,4 @@ CONFIG_TEST_LOGGING_DEFAULTS=n CONFIG_LOG_FRONTEND=y CONFIG_LOG_FRONTEND_ONLY=y CONFIG_LOG_FRONTEND_STMESP=y +CONFIG_DEBUG_DRIVER=y diff --git a/snippets/nordic/nordic-log-stm-dict/snippet.yml b/snippets/nordic/nordic-log-stm-dict/snippet.yml index 6e4f1c6d23e..a717d39399b 100644 --- a/snippets/nordic/nordic-log-stm-dict/snippet.yml +++ b/snippets/nordic/nordic-log-stm-dict/snippet.yml @@ -5,6 +5,3 @@ boards: /.*/nrf54h20/cpuapp/: append: EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpuapp.overlay - /.*/nrf54h20/cpurad/: - append: - EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpurad.overlay diff --git a/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay index fec54817364..962aa231b7a 100644 --- a/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay +++ b/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpuapp.overlay @@ -7,10 +7,7 @@ status = "okay"; }; -&tddconf { +&coresight { status = "okay"; - etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE | NRF_TDDCONF_SOURCE_STMPPR | - NRF_TDDCONF_SOURCE_STMFLPR)>; - portconfig = <0>; - etrbuffer = <&etr_buffer>; + mode = "stm-etr"; }; diff --git a/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay b/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay deleted file mode 100644 index 5bdeddd3c07..00000000000 --- a/snippets/nordic/nordic-log-stm/boards/nrf54h20_cpurad.overlay +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -&tddconf { - status = "okay"; - etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE)>; -}; diff --git a/snippets/nordic/nordic-log-stm/log_stm.conf b/snippets/nordic/nordic-log-stm/log_stm.conf index 1325c25b505..46550a258cd 100644 --- a/snippets/nordic/nordic-log-stm/log_stm.conf +++ b/snippets/nordic/nordic-log-stm/log_stm.conf @@ -4,3 +4,4 @@ CONFIG_LOG_FRONTEND=y CONFIG_LOG_FRONTEND_ONLY=y CONFIG_LOG_FRONTEND_STMESP=y CONFIG_LOG_FRONTEND_STMESP_FSC=y +CONFIG_DEBUG_DRIVER=y diff --git a/snippets/nordic/nordic-log-stm/snippet.yml b/snippets/nordic/nordic-log-stm/snippet.yml index 0a984a8312c..918379360af 100644 --- a/snippets/nordic/nordic-log-stm/snippet.yml +++ b/snippets/nordic/nordic-log-stm/snippet.yml @@ -5,6 +5,3 @@ boards: /.*/nrf54h20/cpuapp/: append: EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpuapp.overlay - /.*/nrf54h20/cpurad/: - append: - EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpurad.overlay From 02d9cf251a5bc435cc61e9502fd6193243b693b7 Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Wed, 27 Aug 2025 21:50:36 +0200 Subject: [PATCH 10/14] [nrf fromtree] drivers: misc: nordic_vpr_launcher: Init order Make sure the nordic_vpr_launcher gets started after the coresight driver if that is present. Signed-off-by: Karsten Koenig (cherry picked from commit 24353a89387d235d9b507a2a6949dca4cb38b82a) --- drivers/misc/nordic_vpr_launcher/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/nordic_vpr_launcher/Kconfig b/drivers/misc/nordic_vpr_launcher/Kconfig index d00bcc583f9..edd2a9ead75 100644 --- a/drivers/misc/nordic_vpr_launcher/Kconfig +++ b/drivers/misc/nordic_vpr_launcher/Kconfig @@ -18,6 +18,7 @@ source "subsys/logging/Kconfig.template.log_config" config NORDIC_VPR_LAUNCHER_INIT_PRIORITY int "Nordic VPR coprocessor launcher init priority" + default 44 if DT_HAS_NORDIC_CORESIGHT_NRF_ENABLED default 0 help The init priority of the VPR coprocessor launcher. From c5909d60360263a9bec1c190c77f68128b20e413 Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Thu, 28 Aug 2025 18:07:25 +0200 Subject: [PATCH 11/14] [nrf fromtree] snippets: nordic-log-stm-tpiu-dict: Added Added a new convience snippet to redirect logs to STM and then sink them to TPIU where they can be captured by a trace probe. Signed-off-by: Karsten Koenig (cherry picked from commit 0b5bb3c8c48b8cc823edd1c68b54f550978d6f0c) --- samples/boards/nordic/coresight_stm/sample.yaml | 7 +++++++ snippets/nordic/nordic-log-stm-tpiu-dict/README.rst | 11 +++++++++++ .../boards/nrf54h20_cpuapp.overlay | 11 +++++++++++ .../nordic/nordic-log-stm-tpiu-dict/log_stm_dict.conf | 6 ++++++ snippets/nordic/nordic-log-stm-tpiu-dict/snippet.yml | 7 +++++++ 5 files changed, 42 insertions(+) create mode 100644 snippets/nordic/nordic-log-stm-tpiu-dict/README.rst create mode 100644 snippets/nordic/nordic-log-stm-tpiu-dict/boards/nrf54h20_cpuapp.overlay create mode 100644 snippets/nordic/nordic-log-stm-tpiu-dict/log_stm_dict.conf create mode 100644 snippets/nordic/nordic-log-stm-tpiu-dict/snippet.yml diff --git a/samples/boards/nordic/coresight_stm/sample.yaml b/samples/boards/nordic/coresight_stm/sample.yaml index 000241d4d97..9ff835d8ffa 100644 --- a/samples/boards/nordic/coresight_stm/sample.yaml +++ b/samples/boards/nordic/coresight_stm/sample.yaml @@ -22,6 +22,13 @@ tests: - SB_CONFIG_APP_CPUPPR_RUN=y - SB_CONFIG_APP_CPUFLPR_RUN=y + sample.boards.nrf.coresight_stm.tpiu.dict: + required_snippets: + - nordic-log-stm-tpiu-dict + extra_args: + - SB_CONFIG_APP_CPUPPR_RUN=y + - SB_CONFIG_APP_CPUFLPR_RUN=y + sample.boards.nrf.coresight_stm: harness: pytest harness_config: diff --git a/snippets/nordic/nordic-log-stm-tpiu-dict/README.rst b/snippets/nordic/nordic-log-stm-tpiu-dict/README.rst new file mode 100644 index 00000000000..9dbf067671b --- /dev/null +++ b/snippets/nordic/nordic-log-stm-tpiu-dict/README.rst @@ -0,0 +1,11 @@ +.. _nordic-log-stm-tpiu-dict: + +Nordic Dictionary-based STM to TPIU logging snippet (nordic-log-stm-tpiu-dict) +############################################################################## + +Overview +******** + +This snippet allows users to build Zephyr with the dictionary-based logging to +the Coresight STM stimulus ports. Data is written to the TPIU interface and can +be captured with nrfutil trace to translate into a human-readable format. diff --git a/snippets/nordic/nordic-log-stm-tpiu-dict/boards/nrf54h20_cpuapp.overlay b/snippets/nordic/nordic-log-stm-tpiu-dict/boards/nrf54h20_cpuapp.overlay new file mode 100644 index 00000000000..e6f14f46a6a --- /dev/null +++ b/snippets/nordic/nordic-log-stm-tpiu-dict/boards/nrf54h20_cpuapp.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&coresight { + status = "okay"; + mode = "stm-tpiu"; + pinctrl-0 = <&tpiu_default>; + pinctrl-names = "default"; +}; diff --git a/snippets/nordic/nordic-log-stm-tpiu-dict/log_stm_dict.conf b/snippets/nordic/nordic-log-stm-tpiu-dict/log_stm_dict.conf new file mode 100644 index 00000000000..0bd8b46d387 --- /dev/null +++ b/snippets/nordic/nordic-log-stm-tpiu-dict/log_stm_dict.conf @@ -0,0 +1,6 @@ +CONFIG_LOG=y +CONFIG_TEST_LOGGING_DEFAULTS=n +CONFIG_LOG_FRONTEND=y +CONFIG_LOG_FRONTEND_ONLY=y +CONFIG_LOG_FRONTEND_STMESP=y +CONFIG_DEBUG_DRIVER=y diff --git a/snippets/nordic/nordic-log-stm-tpiu-dict/snippet.yml b/snippets/nordic/nordic-log-stm-tpiu-dict/snippet.yml new file mode 100644 index 00000000000..32cd36d377e --- /dev/null +++ b/snippets/nordic/nordic-log-stm-tpiu-dict/snippet.yml @@ -0,0 +1,7 @@ +name: nordic-log-stm-tpiu-dict +append: + EXTRA_CONF_FILE: log_stm_dict.conf +boards: + /.*/nrf54h20/cpuapp/: + append: + EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20_cpuapp.overlay From 667a3388e2601b24d554e6a200ea6b090ff9806f Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Mon, 22 Sep 2025 14:27:36 +0200 Subject: [PATCH 12/14] [nrf fromtree] boards: nordic: nrf54h20dk: ETM in JLinkScript The JLinkScript originally configured more than needed which reduces readability, so stripped it down to the minimum. At the same time improved behavior under reset and added ETM to the radiocore JLinkScript. Signed-off-by: Karsten Koenig (cherry picked from commit a50dc9fb8a894fca284e1f2db1c4d5186f479d5c) --- .../support/nrf54h20_cpuapp.JLinkScript | 139 ++++++++-------- .../support/nrf54h20_cpurad.JLinkScript | 149 +++++++++++++++++- 2 files changed, 210 insertions(+), 78 deletions(-) diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript index 9738ec77f43..d79c9341745 100644 --- a/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript +++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript @@ -1,3 +1,9 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + __constant U32 _CPUCONF_ADDR = 0x52011000; __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C; @@ -5,32 +11,17 @@ __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C; __constant U32 _ATBFUNNEL211_ADDR = 0xBF04D000; __constant U32 _ATBFUNNEL212_ADDR = 0xBF04E000; __constant U32 _ATBFUNNEL_CTRLREG_OFFSET = 0x0; +__constant U32 _ATBFUNNEL_HOLDTIME_MASK = 0x700; __constant U32 _HOLDTIME_4 = 0x300; -__constant U32 _ENS0 = 0x1; -__constant U32 _ENS1 = 0x2; -__constant U32 _ENS2 = 0x4; +__constant U32 _ENS0 = 0x1; // Application Core +__constant U32 _ENS1 = 0x2; // Radio Core // ATBREPLICATOR __constant U32 _ATBREPLICATOR212_ADDR = 0xBF04A000; __constant U32 _ATBREPLICATOR213_ADDR = 0xBF04B000; __constant U32 _ATBREPLICATOR_IDFILTER0_OFFSET = 0x0; __constant U32 _ATBREPLICATOR_IDFILTER1_OFFSET = 0x4; -__constant U32 _ID_NONE = 0xFFFFFFFF; -__constant U32 _ID1x = 0xFFFFFFFD; - -// TSGEN -__constant U32 _TSGEN_ADDR = 0xBF041000; -__constant U32 _TSGEN_CNTCR_OFFSET = 0x0; -__constant U32 _TSGEN_CNTFID0_OFFSET = 0x20; -// Clock rate = TDD Freq. / 8 -__constant U32 _TS_CLOCKRATE = 40000000; - -// CTI -__constant U32 _CTI210_ADDR = 0xBF046000; -__constant U32 _CTICONTROL_OFFSET = 0x0; -__constant U32 _CTIOUTEN_OFFSET = 0xA0; -__constant U32 _CTIGATE_OFFSET = 0x140; -__constant U32 _TPIU_FLUSH_TRIG = 0x2; +__constant U32 _ATBREPLICATOR_IDFILTER_ETM = 0x2; // ETM has 0x10 TRACEID // TPIU __constant U32 _TPIU_ADDR = 0xBF043000; @@ -43,30 +34,10 @@ __constant U32 _ENFTC = 0x1; __constant U32 _TPIU_SYNC_FRAME_COUNT = 0x8; __constant U32 _CURRENTPORTSIZE_4 = 0x8; -// TDDCONF -__constant U32 _TDDCONF_ADDR = 0xBF001000; -__constant U32 _TRACEPORTSPEED_OFFSET = 0x408; -__constant U32 _SPEED80MHZ = 0x0; - // CoreSight general -__constant U32 _CORESIGHT_CLAIMSET_OFFSET = 0xFA0; -__constant U32 _CORESIGHT_CLAIMCLR_OFFSET = 0xFA4; __constant U32 _CORESIGHT_LAR_OFFSET = 0xFB0; __constant U32 _CORESIGHT_UNLOCK_KEY = 0xC5ACCE55; -// GPIO P7 -__constant U32 _P7_ADDR = 0x5F938E00; -__constant U32 _PIN_CNF3_OFFSET = 0x8C; -__constant U32 _PIN_CNF4_OFFSET = 0x90; -__constant U32 _PIN_CNF5_OFFSET = 0x94; -__constant U32 _PIN_CNF6_OFFSET = 0x98; -__constant U32 _PIN_CNF7_OFFSET = 0x9C; -__constant U32 _PIN_CNF_TPIU_CLOCK_VALUE = 0x80000503; -__constant U32 _PIN_CNF_TPIU_DATA_VALUE = 0x00000503; - -// Settings -__constant U32 _DEBUGGER_CLAIM_MASK = 0x2; - // Used to check if we have already set up tracing int _needCoresightSetup = 1; @@ -82,68 +53,59 @@ void _CSLock(U32 addr) JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, 0); } -// Set claim bits in the CoreSight peripheral to indicate to the firmware that it -// has been configured by the host debugger -void _CSClaim(U32 addr) -{ - JLINK_MEM_WriteU32(addr + _CORESIGHT_CLAIMSET_OFFSET, _DEBUGGER_CLAIM_MASK); -} - // Set up CoreSight and other necessary configuration so to enable ETM -> TPIU tracing. int _SetupETMTPIUTrace(void) { + U32 ctrlreg_old; + U32 ctrlreg_new; + U32 idfilter0_old; + U32 idfilter1_old; + U32 idfilter0_new; + U32 idfilter1_new; + // Set up ATB funnels/replicators to route ApplicationDomain ETM to TPIU + _CSUnlock(_ATBFUNNEL212_ADDR); - JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, _HOLDTIME_4 | _ENS0); - _CSClaim(_ATBFUNNEL212_ADDR); + ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET); + ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS0; + JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new); _CSLock(_ATBFUNNEL212_ADDR); _CSUnlock(_ATBREPLICATOR212_ADDR); - JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, _ID_NONE); - JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, _ID1x); - _CSLock(_ATBREPLICATOR212_ADDR); - _CSClaim(_ATBREPLICATOR212_ADDR); + idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET); + idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET); + + idfilter0_new = idfilter0_old | _ATBREPLICATOR_IDFILTER_ETM; // SET for output 0 + idfilter1_new = idfilter1_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 1 + + JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new); + JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new); _CSLock(_ATBREPLICATOR212_ADDR); _CSUnlock(_ATBFUNNEL211_ADDR); - JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, _HOLDTIME_4 | _ENS0); - _CSClaim(_ATBFUNNEL211_ADDR); + ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET); + ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS0; + JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new); _CSLock(_ATBFUNNEL211_ADDR); _CSUnlock(_ATBREPLICATOR213_ADDR); - JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, _ID1x); - JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, _ID_NONE); - _CSClaim(_ATBREPLICATOR213_ADDR); - _CSLock(_ATBREPLICATOR213_ADDR); + idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET); + idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET); - // Configure timestamp generator for the correct clock rate - JLINK_MEM_WriteU32(_TSGEN_ADDR + _TSGEN_CNTFID0_OFFSET, _TS_CLOCKRATE); - JLINK_MEM_WriteU32(_TSGEN_ADDR + _TSGEN_CNTCR_OFFSET, 1); - _CSClaim(_TSGEN_ADDR); + idfilter0_new = idfilter0_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 0 + idfilter1_new = idfilter1_old | _ATBREPLICATOR_IDFILTER_ETM; // SET for output 1 - // Configure CTI1 for TPIU formatter flushing - _CSUnlock(_CTI210_ADDR); - JLINK_MEM_WriteU32(_CTI210_ADDR + _CTIOUTEN_OFFSET, _TPIU_FLUSH_TRIG); - JLINK_MEM_WriteU32(_CTI210_ADDR + _CTIGATE_OFFSET, _TPIU_FLUSH_TRIG); - JLINK_MEM_WriteU32(_CTI210_ADDR + _CTICONTROL_OFFSET, 1); - _CSClaim(_CTI210_ADDR); - _CSLock(_CTI210_ADDR); + JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new); + JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new); + _CSLock(_ATBREPLICATOR213_ADDR); // Configure TPIU for port size 4, continuous formatting _CSUnlock(_TPIU_ADDR); JLINK_MEM_WriteU32(_TPIU_ADDR + _CURRENTPORTSIZE_OFFSET, _CURRENTPORTSIZE_4); JLINK_MEM_WriteU32(_TPIU_ADDR + _FFCR_OFFSET, _ENFCONT | _FONFLIN | _ENFTC); JLINK_MEM_WriteU32(_TPIU_ADDR + _FSCR_OFFSET, _TPIU_SYNC_FRAME_COUNT); - _CSClaim(_TPIU_ADDR); _CSLock(_TPIU_ADDR); - // Configure the trace pins - JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF3_OFFSET, _PIN_CNF_TPIU_CLOCK_VALUE); - JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF4_OFFSET, _PIN_CNF_TPIU_DATA_VALUE); - JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF5_OFFSET, _PIN_CNF_TPIU_DATA_VALUE); - JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF6_OFFSET, _PIN_CNF_TPIU_DATA_VALUE); - JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF7_OFFSET, _PIN_CNF_TPIU_DATA_VALUE); - return 0; } @@ -155,6 +117,19 @@ int ConfigTargetSettings(void) // Adjust trace sample delay to compensate for timing when using 320MHz JLINK_ExecCommand("TraceSampleAdjust TD = 1000"); + JLINK_ExecCommand("CORESIGHT_SetTPIUBaseAddr = 0xBF043000"); + + return 0; +} + +int StartTPIU(void) +{ + /* We sort this ourselves in _SetupETMTPIUTrace, don't let JLink touch it */ + return 0; +} + +int StopTPIU(void) +{ return 0; } @@ -169,6 +144,11 @@ int OnTraceStart(void) return 0; } +int AfterResetTarget(void) +{ + _needCoresightSetup = 1; + return 0; +} int SetupTarget(void) { @@ -179,3 +159,8 @@ int SetupTarget(void) return 0; } + +int InitEMU(void) { + JLINK_ExecCommand("EnableLowPowerHandlingMode"); + return 0; +} diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript index e1861ae8c97..2ff7f6c160e 100644 --- a/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript +++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript @@ -1,11 +1,153 @@ -__constant U32 _CPUCONF_ADDR = 0x53011000; +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +__constant U32 _CPUCONF_ADDR = 0x52011000; __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C; +// ATBFUNNEL +__constant U32 _ATBFUNNEL211_ADDR = 0xBF04D000; +__constant U32 _ATBFUNNEL212_ADDR = 0xBF04E000; +__constant U32 _ATBFUNNEL_CTRLREG_OFFSET = 0x0; +__constant U32 _ATBFUNNEL_HOLDTIME_MASK = 0x700; +__constant U32 _HOLDTIME_4 = 0x300; +__constant U32 _ENS0 = 0x1; // Application Core +__constant U32 _ENS1 = 0x2; // Radio Core + +// ATBREPLICATOR +__constant U32 _ATBREPLICATOR212_ADDR = 0xBF04A000; +__constant U32 _ATBREPLICATOR213_ADDR = 0xBF04B000; +__constant U32 _ATBREPLICATOR_IDFILTER0_OFFSET = 0x0; +__constant U32 _ATBREPLICATOR_IDFILTER1_OFFSET = 0x4; +__constant U32 _ATBREPLICATOR_IDFILTER_ETM = 0x2; // ETM has 0x10 TRACEID + +// TPIU +__constant U32 _TPIU_ADDR = 0xBF043000; +__constant U32 _CURRENTPORTSIZE_OFFSET = 0x4; +__constant U32 _FFCR_OFFSET = 0x304; +__constant U32 _FSCR_OFFSET = 0x308; +__constant U32 _ENFCONT = 0x02; +__constant U32 _FONFLIN = 0x10; +__constant U32 _ENFTC = 0x1; +__constant U32 _TPIU_SYNC_FRAME_COUNT = 0x8; +__constant U32 _CURRENTPORTSIZE_4 = 0x8; + +// CoreSight general +__constant U32 _CORESIGHT_LAR_OFFSET = 0xFB0; +__constant U32 _CORESIGHT_UNLOCK_KEY = 0xC5ACCE55; + +// Used to check if we have already set up tracing +int _needCoresightSetup = 1; + +// Unlock a CoreSight peripheral +void _CSUnlock(U32 addr) +{ + JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, _CORESIGHT_UNLOCK_KEY); +} + +// Lock a CoreSight peripheral +void _CSLock(U32 addr) +{ + JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, 0); +} + +// Set up CoreSight and other necessary configuration so to enable ETM -> TPIU tracing. +int _SetupETMTPIUTrace(void) +{ + U32 ctrlreg_old; + U32 ctrlreg_new; + U32 idfilter0_old; + U32 idfilter1_old; + U32 idfilter0_new; + U32 idfilter1_new; + + // Set up ATB funnels/replicators to route ApplicationDomain ETM to TPIU + + _CSUnlock(_ATBFUNNEL212_ADDR); + ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET); + ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS1; + JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new); + _CSLock(_ATBFUNNEL212_ADDR); + + _CSUnlock(_ATBREPLICATOR212_ADDR); + idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET); + idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET); + + idfilter0_new = idfilter0_old | _ATBREPLICATOR_IDFILTER_ETM; // SET for output 0 + idfilter1_new = idfilter1_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 1 + + JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new); + JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new); + _CSLock(_ATBREPLICATOR212_ADDR); + + _CSUnlock(_ATBFUNNEL211_ADDR); + ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET); + ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS1; + JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new); + _CSLock(_ATBFUNNEL211_ADDR); + + _CSUnlock(_ATBREPLICATOR213_ADDR); + idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET); + idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET); + + idfilter0_new = idfilter0_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 0 + idfilter1_new = idfilter1_old | _ATBREPLICATOR_IDFILTER_ETM; // SET for output 1 + + JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new); + JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new); + _CSLock(_ATBREPLICATOR213_ADDR); + + // Configure TPIU for port size 4, continuous formatting + _CSUnlock(_TPIU_ADDR); + JLINK_MEM_WriteU32(_TPIU_ADDR + _CURRENTPORTSIZE_OFFSET, _CURRENTPORTSIZE_4); + JLINK_MEM_WriteU32(_TPIU_ADDR + _FFCR_OFFSET, _ENFCONT | _FONFLIN | _ENFTC); + JLINK_MEM_WriteU32(_TPIU_ADDR + _FSCR_OFFSET, _TPIU_SYNC_FRAME_COUNT); + _CSLock(_TPIU_ADDR); + + return 0; +} + int ConfigTargetSettings(void) { JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP"); CORESIGHT_IndexAHBAPToUse = 1; + // Adjust trace sample delay to compensate for timing when using 320MHz + JLINK_ExecCommand("TraceSampleAdjust TD = 1000"); + + JLINK_ExecCommand("CORESIGHT_SetTPIUBaseAddr = 0xBF043000"); + + return 0; +} + +int StartTPIU(void) +{ + /* We sort this ourselves in _SetupETMTPIUTrace, don't let JLink touch it */ + return 0; +} + +int StopTPIU(void) +{ + return 0; +} + + +int OnTraceStart(void) +{ + // Set up CoreSight if not already configured + if (_needCoresightSetup) { + _SetupETMTPIUTrace(); + _needCoresightSetup = 0; + } + + return 0; +} + +int AfterResetTarget(void) +{ + _needCoresightSetup = 1; return 0; } @@ -18,3 +160,8 @@ int SetupTarget(void) return 0; } + +int InitEMU(void) { + JLINK_ExecCommand("EnableLowPowerHandlingMode"); + return 0; +} From dac352c0d61a5098fd0e687a986b39f27cd260b6 Mon Sep 17 00:00:00 2001 From: Jakub Zymelka Date: Mon, 25 Nov 2024 14:14:40 +0100 Subject: [PATCH 13/14] [nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Configure SDP MSPI pins to switch their control to VPR core Signed-off-by: Jakub Zymelka Signed-off-by: Andrzej Głąbek Signed-off-by: Magdalena Pastula Signed-off-by: Karsten Koenig (cherry picked from commit a9bcc44f74eed83f28506e8fcd44f0f70c65ea9c) (cherry picked from commit 2e74ea72fa61061c4caf1beb6dda304473838774) (cherry picked from commit 915e81a911b3d03834ad11d124449c0f4fa4ccc1) --- drivers/pinctrl/pinctrl_nrf.c | 32 +++++++++++ .../zephyr/dt-bindings/pinctrl/nrf-pinctrl.h | 56 +++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index e350e61f0af..3d59ba7998b 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -201,6 +201,18 @@ static void port_pin_clock_set(uint16_t pin_number, bool enable) #endif +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_hpf_mspi_controller) || \ + defined(CONFIG_MSPI_HPF) || \ + DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(nordic_nrf_vpr_coprocessor, pinctrl_0) +#if defined(CONFIG_SOC_SERIES_NRF54LX) +#define NRF_PSEL_SDP_MSPI(psel) \ + nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR); +#elif defined(CONFIG_SOC_SERIES_NRF54HX) +/* On nRF54H, pin routing is controlled by secure domain, via UICR. */ +#define NRF_PSEL_SDP_MSPI(psel) +#endif +#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_hpf_mspi_controller) || ... */ + int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) { @@ -569,6 +581,26 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, input = NRF_GPIO_PIN_INPUT_DISCONNECT; break; #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_coresight_nrf) */ +#if defined(NRF_PSEL_SDP_MSPI) + case NRF_FUN_SDP_MSPI_CS0: + case NRF_FUN_SDP_MSPI_CS1: + case NRF_FUN_SDP_MSPI_CS2: + case NRF_FUN_SDP_MSPI_CS3: + case NRF_FUN_SDP_MSPI_CS4: + case NRF_FUN_SDP_MSPI_SCK: + case NRF_FUN_SDP_MSPI_DQ0: + case NRF_FUN_SDP_MSPI_DQ1: + case NRF_FUN_SDP_MSPI_DQ2: + case NRF_FUN_SDP_MSPI_DQ3: + case NRF_FUN_SDP_MSPI_DQ4: + case NRF_FUN_SDP_MSPI_DQ5: + case NRF_FUN_SDP_MSPI_DQ6: + case NRF_FUN_SDP_MSPI_DQ7: + NRF_PSEL_SDP_MSPI(psel); + dir = NRF_GPIO_PIN_DIR_OUTPUT; + input = NRF_GPIO_PIN_INPUT_CONNECT; + break; +#endif /* defined(NRF_PSEL_SDP_MSPI) */ default: return -ENOTSUP; } diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h index 92e62a9a6be..4c7f1d3145d 100644 --- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h @@ -172,6 +172,62 @@ #define NRF_FUN_GRTC_CLKOUT_FAST 55U /** GRTC slow clock output */ #define NRF_FUN_GRTC_CLKOUT_32K 56U +/** SDP_MSPI clock pin */ +#define NRF_FUN_SDP_MSPI_SCK 57U +/** SDP_MSPI data pin 0 */ +#define NRF_FUN_SDP_MSPI_DQ0 58U +/** SDP_MSPI data pin 1 */ +#define NRF_FUN_SDP_MSPI_DQ1 59U +/** SDP_MSPI data pin 2 */ +#define NRF_FUN_SDP_MSPI_DQ2 60U +/** SDP_MSPI data pin 3 */ +#define NRF_FUN_SDP_MSPI_DQ3 61U +/** SDP_MSPI data pin 4 */ +#define NRF_FUN_SDP_MSPI_DQ4 62U +/** SDP_MSPI data pin 5 */ +#define NRF_FUN_SDP_MSPI_DQ5 63U +/** SDP_MSPI data pin 6 */ +#define NRF_FUN_SDP_MSPI_DQ6 64U +/** SDP_MSPI data pin 7 */ +#define NRF_FUN_SDP_MSPI_DQ7 65U +/** SDP_MSPI chip select 0 */ +#define NRF_FUN_SDP_MSPI_CS0 66U +/** SDP_MSPI chip select 1 */ +#define NRF_FUN_SDP_MSPI_CS1 67U +/** SDP_MSPI chip select 2 */ +#define NRF_FUN_SDP_MSPI_CS2 68U +/** SDP_MSPI chip select 3 */ +#define NRF_FUN_SDP_MSPI_CS3 69U +/** SDP_MSPI chip select 4 */ +#define NRF_FUN_SDP_MSPI_CS4 70U +/** High-Performance Framework MSPI clock pin */ +#define NRF_FUN_HPF_MSPI_SCK NRF_FUN_SDP_MSPI_SCK +/** High-Performance Framework MSPI data pin 0 */ +#define NRF_FUN_HPF_MSPI_DQ0 NRF_FUN_SDP_MSPI_DQ0 +/** High-Performance Framework MSPI data pin 1 */ +#define NRF_FUN_HPF_MSPI_DQ1 NRF_FUN_SDP_MSPI_DQ1 +/** High-Performance Framework MSPI data pin 2 */ +#define NRF_FUN_HPF_MSPI_DQ2 NRF_FUN_SDP_MSPI_DQ2 +/** High-Performance Framework MSPI data pin 3 */ +#define NRF_FUN_HPF_MSPI_DQ3 NRF_FUN_SDP_MSPI_DQ3 +/** High-Performance Framework MSPI data pin 4 */ +#define NRF_FUN_HPF_MSPI_DQ4 NRF_FUN_SDP_MSPI_DQ4 +/** High-Performance Framework MSPI data pin 5 */ +#define NRF_FUN_HPF_MSPI_DQ5 NRF_FUN_SDP_MSPI_DQ5 +/** High-Performance Framework MSPI data pin 6 */ +#define NRF_FUN_HPF_MSPI_DQ6 NRF_FUN_SDP_MSPI_DQ6 +/** High-Performance Framework MSPI data pin 7 */ +#define NRF_FUN_HPF_MSPI_DQ7 NRF_FUN_SDP_MSPI_DQ7 +/** High-Performance Framework MSPI chip select pin 0 */ +#define NRF_FUN_HPF_MSPI_CS0 NRF_FUN_SDP_MSPI_CS0 +/** High-Performance Framework MSPI chip select pin 1 */ +#define NRF_FUN_HPF_MSPI_CS1 NRF_FUN_SDP_MSPI_CS1 +/** High-Performance Framework MSPI chip select pin 2 */ +#define NRF_FUN_HPF_MSPI_CS2 NRF_FUN_SDP_MSPI_CS2 +/** High-Performance Framework MSPI chip select pin 3 */ +#define NRF_FUN_HPF_MSPI_CS3 NRF_FUN_SDP_MSPI_CS3 +/** High-Performance Framework MSPI chip select pin 4 */ +#define NRF_FUN_HPF_MSPI_CS4 NRF_FUN_SDP_MSPI_CS4 /** TDM SCK in master mode */ #define NRF_FUN_TDM_SCK_M 71U /** TDM SCK in slave mode */ From acac0ba3e1e94800665157b4002949811493d6bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20G=C5=82=C4=85b?= Date: Wed, 8 Oct 2025 14:33:12 +0200 Subject: [PATCH 14/14] [nrf fromtree] tests: boards: nrf: coresight_stm: Align test to STM driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There were recent changes to nrf54h20dk and STM driver. Align test accordingly: - add Kconfig that boots Radio core, - update expected timing results. Signed-off-by: Sebastian Głąb (cherry picked from commit 3d56c2f8f83b9d2d0072684601bfb11775067198) --- .../nordic/coresight_stm/pytest/test_stm.py | 38 +++++++++---------- tests/boards/nrf/coresight_stm/prj.conf | 1 + 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/samples/boards/nordic/coresight_stm/pytest/test_stm.py b/samples/boards/nordic/coresight_stm/pytest/test_stm.py index 6db0b568575..993df0b55fb 100644 --- a/samples/boards/nordic/coresight_stm/pytest/test_stm.py +++ b/samples/boards/nordic/coresight_stm/pytest/test_stm.py @@ -275,9 +275,9 @@ def test_STM_decoded(dut: DeviceAdapter): app_constraints = STMLimits( # all values in us - log_0_arg=1.8, - log_1_arg=2.1, - log_2_arg=2.0, + log_0_arg=0.6, + log_1_arg=0.6, + log_2_arg=2.1, log_3_arg=2.1, log_str=4.5, tracepoint=0.5, @@ -286,35 +286,35 @@ def test_STM_decoded(dut: DeviceAdapter): ) rad_constraints = STMLimits( # all values in us - log_0_arg=4.6, - log_1_arg=5.0, - log_2_arg=5.2, - log_3_arg=5.6, - log_str=6.3, + log_0_arg=5.6, + log_1_arg=5.8, + log_2_arg=6.1, + log_3_arg=6.4, + log_str=7.1, tracepoint=0.5, tracepoint_d32=0.5, tolerance=0.5, ) ppr_constraints = STMLimits( # all values in us - log_0_arg=25.7, - log_1_arg=27.1, - log_2_arg=27.3, - log_3_arg=30.4, - log_str=65.7, + log_0_arg=2.3, + log_1_arg=2.0, + log_2_arg=26.9, + log_3_arg=27.5, + log_str=68.3, tracepoint=0.55, tracepoint_d32=0.25, tolerance=0.5, ) flpr_constraints = STMLimits( # all values in us - log_0_arg=1.3, - log_1_arg=1.6, - log_2_arg=1.6, - log_3_arg=1.7, + log_0_arg=0.2, + log_1_arg=0.2, + log_2_arg=1.2, + log_3_arg=1.2, log_str=3.0, - tracepoint=0.5, - tracepoint_d32=0.5, + tracepoint=0.25, + tracepoint_d32=0.25, tolerance=0.5, ) diff --git a/tests/boards/nrf/coresight_stm/prj.conf b/tests/boards/nrf/coresight_stm/prj.conf index 1e935e973c7..9ee7cf8cc03 100644 --- a/tests/boards/nrf/coresight_stm/prj.conf +++ b/tests/boards/nrf/coresight_stm/prj.conf @@ -1 +1,2 @@ CONFIG_LOG=y +CONFIG_SOC_NRF54H20_CPURAD_ENABLE=y