diff --git a/.github/SECURITY.md b/.github/SECURITY.md index 3525ac32aad2..f1cac9badb00 100644 --- a/.github/SECURITY.md +++ b/.github/SECURITY.md @@ -12,8 +12,8 @@ At this time, with the latest release of v2.5.0, the supported versions are: - 1.14.2: Current LTS - - v2.4.0: Prior release - - v2.5.0: Current release + - v2.5.0: Prior release + - v2.6.0: Current release ## Reporting process diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 838e92c66546..609292fd66f3 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -3,6 +3,22 @@ name: Compliance on: pull_request jobs: + maintainer_check: + runs-on: ubuntu-latest + name: Check MAINTAINERS file + steps: + - name: Checkout the code + uses: actions/checkout@v2 + with: + ref: ${{ github.event.pull_request.head.sha }} + fetch-depth: 0 + - name: Run Maintainers Script + id: maintainer + env: + BASE_REF: ${{ github.base_ref }} + run: | + python3 ./scripts/get_maintainer.py path CMakeLists.txt + compliance_job: runs-on: ubuntu-latest name: Run compliance checks on patch series (PR) diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index 818876e9ad6a..0156e5f1c8c4 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -22,6 +22,9 @@ jobs: matrix: python-version: [3.6, 3.7, 3.8] os: [ubuntu-latest, macos-latest, windows-latest] + exclude: + - os: macos-latest + python-version: 3.6 steps: - name: checkout uses: actions/checkout@v2 diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index 17ac892b1038..ce1cdbdd9ee8 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -1,9 +1,14 @@ # Copyright (c) 2020 Linaro Limited. # SPDX-License-Identifier: Apache-2.0 -name: Documentation GitHub Workflow +name: Documentation Build on: + schedule: + - cron: '0 */3 * * *' + push: + tags: + - v* pull_request: paths: - 'doc/**' @@ -20,20 +25,18 @@ on: - 'scripts/requirements-doc.txt' env: + # NOTE: west docstrings will be extracted from the version listed here + WEST_VERSION: 0.11.1 # The latest CMake available directly with apt is 3.18, but we need >=3.20 # so we fetch that through pip. CMAKE_VERSION: 3.20.5 jobs: - doc-build: - name: "Documentation Build" + doc-build-html: + name: "Documentation Build (HTML)" runs-on: ubuntu-latest steps: - - name: Update PATH for west - run: | - echo "$HOME/.local/bin" >> $GITHUB_PATH - - name: checkout uses: actions/checkout@v2 @@ -45,27 +48,82 @@ jobs: uses: actions/cache@v1 with: path: ~/.cache/pip - key: ${{ runner.os }}-doc-pip + key: pip-${{ hashFiles('scripts/requirements-doc.txt') }} - name: install-pip run: | sudo pip3 install -U setuptools wheel pip pip3 install -r scripts/requirements-doc.txt - pip3 install west==0.11.0 + pip3 install west==${WEST_VERSION} pip3 install cmake==${CMAKE_VERSION} - name: west setup run: | - west init -l . || true + west init -l . - name: build-docs run: | - SPHINXOPTS="-q -W -j auto" make -C doc html - tar cvf htmldocs.tar --directory=./doc/_build html + if [[ "$GITHUB_REF" =~ "refs/tags/v" ]]; then + DOC_TAG="release" + else + DOC_TAG="development" + fi + + DOC_TAG=${DOC_TAG} SPHINXOPTS="-q -W -j auto" make -C doc html + + - name: compress-docs + run: | + tar cfJ html-output.tar.xz --directory=doc/_build html + + - name: upload-build + uses: actions/upload-artifact@master + with: + name: html-output + path: html-output.tar.xz + + doc-build-pdf: + name: "Documentation Build (PDF)" + runs-on: ubuntu-latest + container: texlive/texlive:latest + + steps: + - name: checkout + uses: actions/checkout@v2 + + - name: install-pkgs + run: | + apt-get update + apt-get install -y python3-pip ninja-build doxygen graphviz librsvg2-bin + + - name: cache-pip + uses: actions/cache@v1 + with: + path: ~/.cache/pip + key: pip-${{ hashFiles('scripts/requirements-doc.txt') }} + + - name: install-pip + run: | + pip3 install -U setuptools wheel pip + pip3 install -r scripts/requirements-doc.txt + pip3 install west==${WEST_VERSION} + pip3 install cmake==${CMAKE_VERSION} + + - name: west setup + run: | + west init -l . + + - name: build-docs + run: | + if [[ "$GITHUB_REF" =~ "refs/tags/v" ]]; then + DOC_TAG="release" + else + DOC_TAG="development" + fi + + DOC_TAG=${DOC_TAG} SPHINXOPTS="-q -j auto" LATEXMKOPTS="-quiet -halt-on-error" make -C doc pdf - name: upload-build uses: actions/upload-artifact@master - continue-on-error: True with: - name: htmldocs.tar - path: htmldocs.tar + name: pdf-output + path: doc/_build/latex/zephyr.pdf diff --git a/.github/workflows/doc-publish.yml b/.github/workflows/doc-publish.yml index b50731889fe0..ca8ee3033c1a 100644 --- a/.github/workflows/doc-publish.yml +++ b/.github/workflows/doc-publish.yml @@ -1,48 +1,35 @@ # Copyright (c) 2020 Linaro Limited. +# Copyright (c) 2021 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -name: Doc build for Release or Daily +name: Publish Documentation -# Either a daily based on schedule/cron or only on tag push on: - schedule: - - cron: '50 1/3 * * *' - push: - paths: - - 'VERSION' + workflow_run: + workflows: ["Documentation Build"] + branches: + - main + - v* tags: - # only publish v* tags, do not care about zephyr-v* which point to the - # same commit - - 'v*' + - v* + types: + - completed jobs: doc-publish: name: Publish Documentation runs-on: ubuntu-latest - if: github.repository == 'zephyrproject-rtos/zephyr' + if: ${{ github.event.workflow_run.conclusion == 'success' }} steps: - - name: Update PATH for west - run: | - echo "$HOME/.local/bin" >> $GITHUB_PATH + - name: Download artifacts + uses: dawidd6/action-download-artifact@v2 + with: + workflow: doc-build.yml - - name: Determine tag - id: tag + - name: Uncompress HTML docs run: | - # We expect to get here either due to a schedule event in which - # case we are doing a daily build of the docs, or because a new - # tag was pushed, in which case we are building docs for a release - if [ ${GITHUB_EVENT_NAME} == "schedule" ]; then - echo ::set-output name=TYPE::daily; - echo ::set-output name=RELEASE::latest; - elif [ ${GITHUB_EVENT_NAME} == "push" ]; then - # If push due to a tag GITHUB_REF will look like refs/tags/TAG-FOO - # chop of 'refs/tags' so RELEASE=TAG-FOO - echo ::set-output name=TYPE::release; - echo ::set-output name=RELEASE::${GITHUB_REF/refs\/tags\//}; - else - exit 1 - fi + tar xf html-output/html-output.tar.xz -C html-output - name: Configure AWS Credentials uses: aws-actions/configure-aws-credentials@v1 @@ -51,59 +38,16 @@ jobs: aws-secret-access-key: ${{ secrets.AWS_SECRET_ACCESS_KEY }} aws-region: us-east-1 - - name: checkout - uses: actions/checkout@v2 - - - name: install-pkgs - run: | - sudo apt-get install -y ninja-build doxygen graphviz - - - name: cache-pip - uses: actions/cache@v1 - with: - path: ~/.cache/pip - key: ${{ runner.os }}-doc-pip - - - name: install-pip - run: | - sudo pip3 install -U setuptools wheel pip - pip3 install -r scripts/requirements-base.txt - pip3 install -r scripts/requirements-doc.txt - - - name: west setup - run: | - west init -l . || true - - - name: build-docs - env: - DOC_TAG: ${{ steps.tag.outputs.TYPE }} - run: | - source zephyr-env.sh - make DOC_TAG=${DOC_TAG} -C doc html - - name: Upload to AWS S3 env: - RELEASE: ${{ steps.tag.outputs.RELEASE }} + HEAD_BRANCH: ${{ github.event.workflow_run.head_branch }} run: | - echo "DOC_RELEASE=[$RELEASE]" - if [ "$RELEASE" == "latest" ]; then - echo "publish latest docs" - aws s3 sync --quiet doc/_build/html s3://docs.zephyrproject.org/latest --delete - echo "success sync of latest docs" + if [ "${HEAD_BRANCH:0:1}" == "v" ]; then + VERSION=${HEAD_BRANCH:1} else - # we want just the version, without the leading 'v' - DOC_RELEASE=${RELEASE:1} - echo "publish release docs: ${DOC_RELEASE}" - aws s3 sync --quiet doc/_build/html s3://docs.zephyrproject.org/${DOC_RELEASE} - echo "success sync of rel docs" - fi - if [ -d doc/_build/doxygen/html ]; then - if [ "$RELEASE" == "latest" ]; then - API_RELEASE=latest - else - API_RELEASE=${RELEASE:1} - fi - echo "publish doxygen to apidoc/${API_RELEASE}" - aws s3 sync --quiet doc/_build/doxygen/html s3://docs.zephyrproject.org/apidoc/${API_RELEASE} --delete - echo "success publish of doxygen" + VERSION="latest" fi + + aws s3 sync --quiet html-output/html s3://docs.zephyrproject.org/${VERSION} --delete + aws s3 sync --quiet html-output/html/doxygen/html s3://docs.zephyrproject.org/apidoc/${VERSION} --delete + aws s3 cp --quiet pdf-output/zephyr.pdf s3://docs.zephyrproject.org/${VERSION}/zephyr.pdf diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml index c8aba40a3bad..59594904ab7a 100644 --- a/.github/workflows/manifest.yml +++ b/.github/workflows/manifest.yml @@ -17,7 +17,7 @@ jobs: fetch-depth: 0 - name: Manifest - uses: zephyrproject-rtos/action-manifest@v1.1.0 + uses: zephyrproject-rtos/action-manifest@2f1ad2908599d4fe747f886f9d733dd7eebae4ef with: github-token: ${{ secrets.GITHUB_TOKEN }} manifest-path: 'west.yml' diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index 608dfe06f505..2bf4eef4388d 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -23,6 +23,9 @@ jobs: matrix: python-version: [3.6, 3.7, 3.8] os: [ubuntu-latest, macos-latest, windows-latest] + exclude: + - os: macos-latest + python-version: 3.6 steps: - name: checkout uses: actions/checkout@v2 diff --git a/CMakeLists.txt b/CMakeLists.txt index 1f0651cf9975..40039c8a4460 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -77,6 +77,8 @@ zephyr_include_directories( ${STDINCLUDE} ) +include(${ZEPHYR_BASE}/cmake/linker_script/${ARCH}/linker.cmake OPTIONAL) + # Don't add non-existing include directories, it creates noise and # warnings in some tooling foreach(optional_include_dir @@ -95,6 +97,11 @@ zephyr_compile_definitions( __ZEPHYR__=1 ) +# Ensure that include/toolchain.h includes toolchain/other.h for all off-tree toolchains +if(TOOLCHAIN_USE_CUSTOM) + zephyr_compile_definitions(__TOOLCHAIN_CUSTOM__) +endif() + # @Intent: Set compiler flags to enable buffer overflow checks in libc functions # @config in CONFIG_NO_OPTIMIZATIONS optional : Optimizations may affect security zephyr_compile_definitions($ ) @@ -230,7 +237,12 @@ zephyr_compile_options($<$:$ # @Intent: Enforce standard integer type correspondance to match Zephyr usage. # (must be after compiler specific flags) -zephyr_compile_options("SHELL: $ ${ZEPHYR_BASE}/include/toolchain/zephyr_stdint.h") +if(NOT CONFIG_ARCH_POSIX) + # `zephyr_stdint.h` is not included for the POSIX (native) arch because it + # compiles with the host toolchain/headers and there can be conflicts if we + # arbitrarily redefine our own type system (see #37718). + zephyr_compile_options("SHELL: $ ${ZEPHYR_BASE}/include/toolchain/zephyr_stdint.h") +endif() # Common toolchain-agnostic assembly flags zephyr_compile_options( @@ -350,6 +362,7 @@ endif() # Declare MPU userspace dependencies before the linker scripts to make # sure the order of dependencies are met if(CONFIG_USERSPACE) + add_custom_target(app_smem) set(APP_SMEM_ALIGNED_DEP app_smem_aligned_linker) set(APP_SMEM_UNALIGNED_DEP app_smem_unaligned_linker) endif() @@ -586,23 +599,12 @@ add_custom_command( add_custom_target(${SYSCALL_LIST_H_TARGET} DEPENDS ${syscall_list_h}) -# This only works for CMake version >=3.15, but as the property is ignored on -# older CMake versions there is no reason to check for version. set_property(TARGET ${SYSCALL_LIST_H_TARGET} APPEND PROPERTY ADDITIONAL_CLEAN_FILES ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscalls ) -# Only works with make. -if(${CMAKE_VERSION} VERSION_LESS 3.15) - set_property(DIRECTORY - APPEND PROPERTY - ADDITIONAL_MAKE_CLEAN_FILES - ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscalls - ) -endif() - add_custom_target(${PARSE_SYSCALLS_TARGET} DEPENDS ${syscalls_json} @@ -715,9 +717,12 @@ foreach(zephyr_lib ${ZEPHYR_LIBS_PROPERTY}) if(NOT source_list AND NOT ${lib_imported} ) - message(WARNING - "No SOURCES given to Zephyr library: ${zephyr_lib}\nExcluding target from build." - ) + get_property(allow_empty TARGET ${zephyr_lib} PROPERTY ALLOW_EMPTY) + if(NOT "${allow_empty}") + message(WARNING + "No SOURCES given to Zephyr library: ${zephyr_lib}\nExcluding target from build." + ) + endif() target_sources(${zephyr_lib} PRIVATE ${ZEPHYR_BASE}/misc/empty_file.c) set_property(TARGET ${zephyr_lib} PROPERTY EXCLUDE_FROM_ALL TRUE) list(REMOVE_ITEM ZEPHYR_LIBS_PROPERTY ${zephyr_lib}) @@ -789,6 +794,7 @@ if(CONFIG_HAS_DTS) --output-source dev_handles.c --kernel $ --zephyr-base ${ZEPHYR_BASE} + --start-symbol "$" DEPENDS ${ZEPHYR_PREBUILT_EXECUTABLE} ) set_property(GLOBAL APPEND PROPERTY GENERATED_KERNEL_SOURCE_FILES dev_handles.c) @@ -980,18 +986,42 @@ toolchain_ld_configure_files() if(CONFIG_USERSPACE) set(APP_SMEM_ALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_aligned.ld") set(APP_SMEM_UNALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_unaligned.ld") + + if(CONFIG_LINKER_USE_PINNED_SECTION) + set(APP_SMEM_PINNED_ALIGNED_LD + "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_aligned.ld") + set(APP_SMEM_PINNED_UNALIGNED_LD + "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_unaligned.ld") + + if(NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + # The libc partition may hold symbols that are required during boot process, + # for example, stack guard (if enabled). So the libc partition must be pinned + # if not sections are in physical memory at boot, as the paging mechanism is + # only initialized post-kernel. + set_property(TARGET app_smem APPEND PROPERTY pinned_partitions "z_libc_partition") + endif() + + get_property(APP_SMEM_PINNED_PARTITION_LIST TARGET app_smem PROPERTY pinned_partitions) + if(APP_SMEM_PINNED_PARTITION_LIST) + list(JOIN APP_SMEM_PINNED_PARTITION_LIST "," APP_SMEM_PINNED_PARTITION_LIST_ARG_CSL) + set(APP_SMEM_PINNED_PARTITION_LIST_ARG "--pinpartitions=${APP_SMEM_PINNED_PARTITION_LIST_ARG_CSL}") + endif() + endif() + set(OBJ_FILE_DIR "${PROJECT_BINARY_DIR}/../") add_custom_target( ${APP_SMEM_ALIGNED_DEP} DEPENDS ${APP_SMEM_ALIGNED_LD} + ${APP_SMEM_PINNED_ALIGNED_LD} ) add_custom_target( ${APP_SMEM_UNALIGNED_DEP} DEPENDS ${APP_SMEM_UNALIGNED_LD} + ${APP_SMEM_PINNED_UNALIGNED_LD} ) if(CONFIG_NEWLIB_LIBC) @@ -1002,11 +1032,13 @@ if(CONFIG_USERSPACE) endif() add_custom_command( - OUTPUT ${APP_SMEM_UNALIGNED_LD} + OUTPUT ${APP_SMEM_UNALIGNED_LD} ${APP_SMEM_PINNED_UNALIGNED_LD} COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/gen_app_partitions.py -d ${OBJ_FILE_DIR} -o ${APP_SMEM_UNALIGNED_LD} + $<$:--pinoutput=${APP_SMEM_PINNED_UNALIGNED_LD}> + ${APP_SMEM_PINNED_PARTITION_LIST_ARG} ${NEWLIB_PART} $ $<$:--verbose> @@ -1024,6 +1056,7 @@ if(CONFIG_USERSPACE) ${CODE_RELOCATION_DEP} ${APP_SMEM_UNALIGNED_DEP} ${APP_SMEM_UNALIGNED_LD} + ${APP_SMEM_PINNED_UNALIGNED_LD} zephyr_generated_headers ) @@ -1056,11 +1089,13 @@ if(CONFIG_USERSPACE) add_dependencies( app_smem_unaligned_prebuilt linker_app_smem_unaligned_script ${OFFSETS_LIB}) add_custom_command( - OUTPUT ${APP_SMEM_ALIGNED_LD} + OUTPUT ${APP_SMEM_ALIGNED_LD} ${APP_SMEM_PINNED_ALIGNED_LD} COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/gen_app_partitions.py -e $ -o ${APP_SMEM_ALIGNED_LD} + $<$:--pinoutput=${APP_SMEM_PINNED_ALIGNED_LD}> + ${APP_SMEM_PINNED_PARTITION_LIST_ARG} ${NEWLIB_PART} $ $<$:--verbose> @@ -1472,8 +1507,8 @@ if(CONFIG_OUTPUT_STAT) COMMAND $ $ $ - $ ${KERNEL_ELF_NAME} - $ ${KERNEL_STAT_NAME} + $${KERNEL_ELF_NAME} + $${KERNEL_STAT_NAME} $ ) list(APPEND @@ -1644,13 +1679,17 @@ if((CMAKE_BUILD_TYPE IN_LIST build_types) AND (NOT NO_BUILD_TYPE_WARNING)) endif() endif() -# @Intent: Set compiler specific flags for standard C includes +# @Intent: Set compiler specific flags for standard C/C++ includes # Done at the very end, so any other system includes which may # be added by Zephyr components were first in list. # Note, the compile flags are moved, but the system include is still present here. zephyr_compile_options($) target_include_directories(zephyr_interface SYSTEM INTERFACE $) +if(NOT CONFIG_LIB_CPLUSPLUS) + zephyr_compile_options($<$:$>) +endif() + # Finally export all build flags from Zephyr add_subdirectory_ifdef( CONFIG_MAKEFILE_EXPORTS diff --git a/CODEOWNERS b/CODEOWNERS index 8725d4b554d2..dbe807c9b7f4 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -38,10 +38,10 @@ /soc/arm/cypress/ @nandojve /soc/arm/bcm*/ @sbranden /soc/arm/infineon_xmc/ @parthitce -/soc/arm/nxp*/ @MaureenHelm @mmahadevan108 @dleach02 +/soc/arm/nxp*/ @mmahadevan108 @dleach02 /soc/arm/nordic_nrf/ @ioannisg -/soc/arm/nuvoton/ @ssekar15 /soc/arm/nuvoton_npcx/ @MulinChao @WealianLiao @ChiHuaL +/soc/arm/nuvoton_numicro/ @ssekar15 /soc/arm/quicklogic_eos_s3/ @kowalewskijan @kgugala /soc/arm/silabs_exx32/efm32pg1b/ @rdmeneze /soc/arm/silabs_exx32/efr32mg21/ @l-alfred @@ -67,7 +67,8 @@ /arch/riscv/ @kgugala @pgielda /soc/posix/ @aescolar @daor-oti /soc/riscv/ @kgugala @pgielda -/soc/riscv/openisa*/ @MaureenHelm +/soc/riscv/openisa*/ @dleach02 +/soc/riscv/riscv-privilege/andes_v5/ @cwshu @Teng-Shih-Wei /soc/x86/ @dcpleung @nashif @jenmwms @aasthagr /arch/xtensa/ @dcpleung @andyross @nashif /soc/xtensa/ @dcpleung @andyross @nashif @@ -93,17 +94,18 @@ /boards/arm/disco_l475_iot1/ @erwango /boards/arm/efm32pg_stk3401a/ @rdmeneze /boards/arm/faze/ @mbittan @simonguinot -/boards/arm/frdm*/ @MaureenHelm @mmahadevan108 @dleach02 -/boards/arm/frdm*/doc/ @MaureenHelm @MeganHansen +/boards/arm/frdm*/ @mmahadevan108 @dleach02 +/boards/arm/frdm*/doc/ @dleach02 @MeganHansen /boards/arm/google_*/ @jackrosenthal -/boards/arm/hexiwear*/ @MaureenHelm @mmahadevan108 @dleach02 -/boards/arm/hexiwear*/doc/ @MaureenHelm @MeganHansen +/boards/arm/hexiwear*/ @mmahadevan108 @dleach02 +/boards/arm/hexiwear*/doc/ @dleach02 @MeganHansen /boards/arm/ip_k66f/ @parthitce @lmajewski -/boards/arm/lpcxpresso*/ @MaureenHelm @mmahadevan108 @dleach02 -/boards/arm/lpcxpresso*/doc/ @MaureenHelm @MeganHansen +/boards/arm/legend/ @mbittan @simonguinot +/boards/arm/lpcxpresso*/ @mmahadevan108 @dleach02 +/boards/arm/lpcxpresso*/doc/ @dleach02 @MeganHansen /boards/arm/mimx8mm_evk/ @Mani-Sadhasivam -/boards/arm/mimxrt*/ @MaureenHelm @mmahadevan108 @dleach02 -/boards/arm/mimxrt*/doc/ @MaureenHelm @MeganHansen +/boards/arm/mimxrt*/ @mmahadevan108 @dleach02 +/boards/arm/mimxrt*/doc/ @dleach02 @MeganHansen /boards/arm/mps2_an385/ @fvincenzo /boards/arm/msp_exp432p401r_launchxl/ @Mani-Sadhasivam /boards/arm/npcx7m6fb_evb/ @MulinChao @WealianLiao @ChiHuaL @@ -141,16 +143,19 @@ /boards/posix/ @aescolar @daor-oti /boards/posix/nrf52_bsim/ @aescolar @wopu-ot /boards/riscv/ @kgugala @pgielda -/boards/riscv/rv32m1_vega/ @MaureenHelm +/boards/riscv/rv32m1_vega/ @dleach02 /boards/riscv/beaglev_starlight_jh7100/ @rajnesh-kanwal +/boards/riscv/adp_xc7k_ae350/ @cwshu @Teng-Shih-Wei /boards/shields/ @erwango /boards/shields/atmel_rf2xx/ @nandojve /boards/shields/esp_8266/ @nandojve /boards/shields/inventek_eswifi/ @nandojve /boards/x86/ @dcpleung @nashif @jenmwms @aasthagr +/boards/x86/acrn/ @enjiamai /boards/xtensa/ @nashif @dcpleung /boards/xtensa/intel_s1000_crb/ @sathishkuttan @dcpleung /boards/xtensa/odroid_go/ @ydamigos +/boards/xtensa/nxp_adsp_imx8/ @iuliana-prodan @dbaluta /boards/sparc/ @martin-aberg /boards/arm64/qemu_cortex_a53/ @carlocaione /boards/arm64/bcm958402m2_a72/ @abhishek-brcm @@ -176,16 +181,19 @@ /drivers/*/*sam4l* @nandojve /drivers/*/*cc13xx_cc26xx* @bwitherspoon /drivers/*/*litex* @mateusz-holenko @kgugala @pgielda -/drivers/*/*mcux* @MaureenHelm @mmahadevan108 @dleach02 +/drivers/*/*mcux* @mmahadevan108 @dleach02 /drivers/*/*stm32* @erwango @ABOSTM @FRASTM /drivers/*/*native_posix* @aescolar @daor-oti /drivers/*/*lpc11u6x* @mbittan @simonguinot /drivers/*/*npcx* @MulinChao @WealianLiao @ChiHuaL +/drivers/*/*andes* @cwshu @Teng-Shih-Wei /drivers/adc/ @anangl /drivers/adc/adc_stm32.c @cybertale +/drivers/audio/*nrfx* @anangl +/drivers/bbram/* @yperess @sjg20 @jackrosenthal /drivers/bluetooth/ @joerchan @jhedberg @Vudentz /drivers/cache/ @carlocaione -/drivers/syscon/ @carlocaione +/drivers/syscon/ @carlocaione @yperess /drivers/can/ @alexanderwachter /drivers/can/*mcp2515* @karstenkoenig /drivers/can/*rcar* @julien-massot @@ -209,7 +217,8 @@ /drivers/edac/ @finikorg /drivers/eeprom/ @henrikbrixandersen /drivers/eeprom/eeprom_stm32.c @KwonTae-young -/drivers/entropy/*rv32m1* @MaureenHelm +/drivers/entropy/*b91* @yurvyn +/drivers/entropy/*rv32m1* @dleach02 /drivers/entropy/*gecko* @chrta /drivers/entropy/*litex* @mateusz-holenko @kgugala @pgielda /drivers/espi/ @albertofloyd @franciscomunoz @scottwcpg @@ -217,16 +226,20 @@ /drivers/ethernet/*stm32* @Nukersson @lochej /drivers/ethernet/*w5500* @parthitce /drivers/ethernet/*xlnx_gem* @ibirnbaum +/drivers/ethernet/phy/ @rlubos @tbursztyka @arvinf +/drivers/mdio/ @rlubos @tbursztyka @arvinf /drivers/flash/ @nashif @nvlsianpu +/drivers/flash/*b91* @yurvyn /drivers/flash/*nrf* @nvlsianpu +/drivers/fpga/ @tgorochowik @kgugala /drivers/gpio/ @mnkp /drivers/gpio/*b91* @yurvyn /drivers/gpio/*lmp90xxx* @henrikbrixandersen /drivers/gpio/*stm32* @erwango /drivers/gpio/*eos_s3* @wtatarski @kowalewskijan @kgugala /drivers/gpio/*rcar* @julien-massot +/drivers/gpio/*esp32* @glaubermaroto /drivers/hwinfo/ @alexanderwachter -/drivers/i2s/i2s_ll_stm32* @avisconti /drivers/i2c/i2c_common.c @sjg20 /drivers/i2c/i2c_emul.c @sjg20 /drivers/i2c/i2c_ite_it8xxx2.c @GTLin08 @@ -238,7 +251,10 @@ /drivers/i2c/i2c_test.c @mbolivar-nordic /drivers/i2c/*rcar* @aaillet /drivers/i2s/*litex* @mateusz-holenko @kgugala @pgielda +/drivers/i2s/i2s_ll_stm32* @avisconti +/drivers/i2s/*nrfx* @anangl /drivers/ieee802154/ @rlubos @tbursztyka +/drivers/ieee802154/*b91* @yurvyn /drivers/ieee802154/ieee802154_rf2xx* @tbursztyka @nandojve /drivers/ieee802154/ieee802154_cc13xx* @bwitherspoon @cfriedt /drivers/interrupt_controller/ @dcpleung @nashif @@ -252,6 +268,7 @@ /drivers/ipm/ipm_nrfx_ipc.c @masz-nordic @ioannisg /drivers/ipm/ipm_nrfx_ipc.h @masz-nordic @ioannisg /drivers/ipm/ipm_stm32_ipcc.c @arnopo +/drivers/ipm/ipm_stm32_hsem.c @cameled /drivers/kscan/ @VenkatKotakonda @franciscomunoz @scottwcpg /drivers/kscan/*xec* @franciscomunoz @scottwcpg /drivers/kscan/*ft5336* @MaureenHelm @@ -262,17 +279,19 @@ /drivers/memc/ @gmarull /drivers/misc/ @tejlmand /drivers/misc/ft8xx/ @hubertmis -/drivers/modem/hl7800.c @rerickson1 -/drivers/modem/Kconfig.hl7800 @rerickson1 +/drivers/modem/hl7800.c @LairdCP/zephyr +/drivers/modem/Kconfig.hl7800 @LairdCP/zephyr /drivers/pcie/ @dcpleung @nashif @jhedberg /drivers/peci/ @albertofloyd @franciscomunoz @scottwcpg /drivers/pinmux/*b91* @yurvyn /drivers/pinmux/*hsdk* @iriszzw /drivers/pinmux/*it8xxx2* @ite +/drivers/pinmux/*esp32* @glaubermaroto /drivers/pm_cpu_ops/ @carlocaione /drivers/ps2/ @franciscomunoz @scottwcpg /drivers/ps2/*xec* @franciscomunoz @scottwcpg /drivers/ps2/*npcx* @MulinChao @WealianLiao @ChiHuaL +/drivers/pwm/*b91* @yurvyn /drivers/pwm/*rv32m1* @henrikbrixandersen /drivers/pwm/*sam0* @nzmichaelh /drivers/pwm/*stm32* @gmarull @@ -303,11 +322,13 @@ /drivers/serial/uart_xlnx_ps.c @wjliang /drivers/serial/uart_xlnx_uartlite.c @henrikbrixandersen /drivers/serial/*xmc4xxx* @parthitce -/drivers/serial/*nuvoton* @ssekar15 +/drivers/serial/*numicro* @ssekar15 /drivers/serial/*apbuart* @martin-aberg /drivers/serial/*rcar* @aaillet /drivers/serial/Kconfig.test @str4t0m /drivers/serial/serial_test.c @str4t0m +/drivers/serial/*esp32c3* @uLipe +/drivers/serial/*esp32s2* @glaubermaroto /drivers/disk/ @jfischer-no /drivers/disk/sdmmc_sdhc.h @JunYangNXP /drivers/disk/sdmmc_spi.c @JunYangNXP @@ -316,6 +337,7 @@ /drivers/net/ @rlubos @tbursztyka /drivers/ptp_clock/ @tbursztyka /drivers/spi/ @tbursztyka +/drivers/spi/*b91* @yurvyn /drivers/spi/spi_rv32m1_lpspi* @karstenkoenig /drivers/timer/apic_timer.c @dcpleung @nashif /drivers/timer/apic_tsc.c @andyross @@ -334,10 +356,12 @@ /drivers/usb/ @jfischer-no /drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain /drivers/video/ @loicpoulain +/drivers/i2c/*b91* @yurvyn /drivers/i2c/i2c_ll_stm32* @ydamigos /drivers/i2c/i2c_rv32m1_lpi2c* @henrikbrixandersen /drivers/i2c/*sam0* @Sizurka /drivers/i2c/i2c_dw* @dcpleung +/drivers/i2c/*tca9546a* @kurddt /drivers/*/*xec* @franciscomunoz @albertofloyd @scottwcpg /drivers/watchdog/*gecko* @oanerer /drivers/watchdog/*sifive* @katsuster @@ -373,7 +397,7 @@ /dts/arm/ti/cc3235* @vanti /dts/arm/nordic/ @ioannisg @carlescufi /dts/arm/nuvoton/ @ssekar15 @MulinChao @WealianLiao @ChiHuaL -/dts/arm/nxp/ @MaureenHelm @mmahadevan108 @dleach02 +/dts/arm/nxp/ @mmahadevan108 @dleach02 /dts/arm/microchip/ @franciscomunoz @albertofloyd @scottwcpg /dts/arm/silabs/efm32_pg_1b.dtsi @rdmeneze /dts/arm/silabs/efm32gg11b* @oanerer @@ -388,9 +412,10 @@ /dts/riscv/ @kgugala @pgielda /dts/riscv/it8xxx2.dtsi @ite /dts/riscv/microsemi-miv.dtsi @galak -/dts/riscv/rv32m1* @MaureenHelm +/dts/riscv/rv32m1* @dleach02 /dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda /dts/riscv/starfive/ @rajnesh-kanwal +/dts/riscv/andes_v5* @cwshu @Teng-Shih-Wei /dts/arm/armv*m.dtsi @galak @ioannisg /dts/arm/armv7-r.dtsi @bbolen @stephanosio /dts/arm/xilinx/ @bbolen @stephanosio @@ -398,24 +423,27 @@ /dts/x86/ @jhedberg /dts/xtensa/xtensa.dtsi @ydamigos /dts/xtensa/intel/ @dcpleung +/dts/xtensa/espressif/ @glaubermaroto +/dts/xtensa/nxp/ @iuliana-prodan @dbaluta /dts/sparc/ @martin-aberg /dts/bindings/ @galak /dts/bindings/can/ @alexanderwachter /dts/bindings/i2c/zephyr*i2c-emul.yaml @sjg20 /dts/bindings/adc/st*stm32-adc.yaml @cybertale -/dts/bindings/modem/*hl7800.yaml @rerickson1 +/dts/bindings/modem/*hl7800.yaml @LairdCP/zephyr /dts/bindings/serial/ns16550.yaml @dcpleung @nashif /dts/bindings/wifi/*esp-at.yaml @mniestroj /dts/bindings/*/*npcx* @MulinChao @WealianLiao @ChiHuaL /dts/bindings/*/*psoc6* @nandojve /dts/bindings/*/nordic* @anangl -/dts/bindings/*/nxp* @MaureenHelm @mmahadevan108 @dleach02 -/dts/bindings/*/openisa* @MaureenHelm +/dts/bindings/*/nxp* @mmahadevan108 @dleach02 +/dts/bindings/*/openisa* @dleach02 /dts/bindings/*/st* @erwango /dts/bindings/sensor/ams* @alexanderwachter /dts/bindings/*/sifive* @mateusz-holenko @kgugala @pgielda /dts/bindings/*/litex* @mateusz-holenko @kgugala @pgielda /dts/bindings/*/vexriscv* @mateusz-holenko @kgugala @pgielda +/dts/bindings/*/andes* @cwshu @Teng-Shih-Wei /dts/bindings/pm_cpu_ops/* @carlocaione /dts/bindings/ethernet/*gem.yaml @ibirnbaum /dts/posix/ @aescolar @vanwinkeljan @daor-oti @@ -436,7 +464,7 @@ /include/drivers/led/ht16k33.h @henrikbrixandersen /include/drivers/interrupt_controller/ @dcpleung @nashif /include/drivers/interrupt_controller/gic.h @stephanosio -/include/drivers/modem/hl7800.h @rerickson1 +/include/drivers/modem/hl7800.h @LairdCP/zephyr /include/drivers/pcie/ @dcpleung /include/drivers/hwinfo.h @alexanderwachter /include/drivers/led.h @Mani-Sadhasivam @@ -523,6 +551,7 @@ /lib/posix/ @pfalcon /subsys/portability/ @nashif /lib/libc/ @nashif +/lib/libc/arcmwdt/ @abrodkin @ruuddw @evgeniy-paltsev /modules/ @nashif /modules/trusted-firmware-m/ @ioannisg @microbuilder /kernel/device.c @andyross @nashif @@ -560,6 +589,7 @@ /samples/subsys/pm/ @nashif @ceolin /samples/tfm_integration/ @ioannisg @microbuilder /samples/userspace/ @dcpleung @nashif +/scripts/release/bug_bash.py @cfriedt /scripts/coccicheck @himanshujha199640 @JuliaLawall /scripts/coccinelle/ @himanshujha199640 @JuliaLawall /scripts/coredump/ @dcpleung diff --git a/Kconfig.zephyr b/Kconfig.zephyr index af84a0197c4b..fd637c1666c9 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -25,6 +25,8 @@ source "$(BOARD_DIR)/Kconfig.defconfig" osource "$(KCONFIG_BINARY_DIR)/Kconfig.soc.defconfig" # This loads Zephyr base SoC root defconfigs osource "soc/$(ARCH)/*/Kconfig.defconfig" +# This loads the toolchain defconfigs +osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig.defconfig" menu "Modules" @@ -130,8 +132,36 @@ config ROM_START_OFFSET alignment requirements on most ARM targets, although some targets may require smaller or larger values. +config LD_LINKER_SCRIPT_SUPPORTED + bool + default y + +choice LINKER_SCRIPT + prompt "Linker script" + default LD_LINKER_TEMPLATE if LD_LINKER_SCRIPT_SUPPORTED + +config LD_LINKER_TEMPLATE + bool "LD template" + depends on LD_LINKER_SCRIPT_SUPPORTED + help + Select this option to use the LD linker script templates. + The templates are pre-processed by the C pre-processor to create the + final LD linker script. + +config CMAKE_LINKER_GENERATOR + bool "CMake generator" + depends on ARM + help + Select this option to use the Zephyr CMake linker script generator. + The linker configuration is written in CMake and the final linker + script will be generated by the toolchain specific linker generator. + For LD based linkers, this will be the ld generator, for ARMClang / + armlink based linkers it will be the scatter generator. + +endchoice + config HAVE_CUSTOM_LINKER_SCRIPT - bool "Custom linker scripts provided" + bool "Custom linker script provided" help Set this option if you have a custom linker script which needed to be define in CUSTOM_LINKER_SCRIPT. @@ -209,6 +239,19 @@ config LINKER_USE_PINNED_SECTION Requires that pinned sections exist in the architecture, SoC, board or custom linker script. +config LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT + bool "Generic sections are present at boot" if DEMAND_PAGING && LINKER_USE_PINNED_SECTION + default y + help + When disabled, the linker sections other than the boot and + pinned sections will be marked as not present in the page + tables. This allows kernel to pull in data pages on demand + as required by current execution context when demand paging + is enabled. There is no need to load all code and data into + memory at once. + + If unsure, say Y. + endmenu # "Linker Sections" endmenu @@ -533,16 +576,43 @@ config MCUBOOT_SIGNATURE_KEY_FILE The existence of bin and hex files depends on CONFIG_BUILD_OUTPUT_BIN and CONFIG_BUILD_OUTPUT_HEX. - This option should contain an absolute path to the same file - as the BOOT_SIGNATURE_KEY_FILE option in your MCUboot - .config. (The MCUboot config option is used for the MCUboot - bootloader image; this option is for your application which - is to be loaded by MCUboot. The MCUboot config option can be - a relative path from the MCUboot repository root; this option's - behavior is undefined for relative paths.) + This option should contain a path to the same file as the + BOOT_SIGNATURE_KEY_FILE option in your MCUboot .config. The path + may be absolute or relative to the west workspace topdir. (The MCUboot + config option is used for the MCUboot bootloader image; this option is + for your application which is to be loaded by MCUboot. The MCUboot + config option can be a relative path from the MCUboot repository + root.) If left empty, you must sign the Zephyr binaries manually. +config MCUBOOT_ENCRYPTION_KEY_FILE + string "Path to the mcuboot encryption key file" + default "" + depends on MCUBOOT_SIGNATURE_KEY_FILE != "" + help + The file contains the public key that is used to encrypt the + ephemeral key that encrypts the image. The corresponding + private key is hard coded in the MCUboot source code and is + used to decrypt the ephemeral key that is embedded in the + image. The file is in PEM format. + + If set to a non-empty value, the build system tries to + sign and encrypt the final binaries using a 'west sign -t imgtool' + command. The binaries are placed in the build directory at + zephyr/zephyr.signed.encrypted.bin and + zephyr/zephyr.signed.encrypted.hex. + + The file names can be customized with CONFIG_KERNEL_BIN_NAME. + The existence of bin and hex files depends on CONFIG_BUILD_OUTPUT_BIN + and CONFIG_BUILD_OUTPUT_HEX. + + This option should either be an absolute path or a path relative to + the west workspace topdir. + Example: './bootloader/mcuboot/enc-rsa2048-pub.pem' + + If left empty, you must encrypt the Zephyr binaries manually. + config MCUBOOT_EXTRA_IMGTOOL_ARGS string "Extra arguments to pass to imgtool" default "" @@ -566,7 +636,7 @@ endif # BOOTLOADER_MCUBOOT config BOOTLOADER_ESP_IDF bool "ESP-IDF bootloader support" - depends on SOC_ESP32 + depends on SOC_ESP32 || SOC_ESP32S2 help This option will trigger the compilation of the ESP-IDF bootloader inside the build folder. diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 915429d7de84..a7416fd9eafa 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -137,11 +137,10 @@ ARM arch: - stephanosio - bbolen files: - - arch/arm/aarch32/ - - arch/arm/common/ - - arch/arm/offsets/ - - include/arch/arm/aarch32 - - include/arch/arm/* + - arch/arm/ + - arch/arm/core/offsets/ + - include/arch/arm/aarch32/ + - include/arch/arm/ - tests/arch/arm/ labels: - "area: ARM" @@ -180,7 +179,7 @@ Bluetooth: - include/bluetooth/ - include/drivers/bluetooth/ - samples/bluetooth/ - - subsys/bluetooth/* + - subsys/bluetooth/ - subsys/bluetooth/common/ - subsys/bluetooth/host/ - subsys/bluetooth/services/ @@ -390,7 +389,7 @@ Display drivers: - include/drivers/display.h - lib/gui/ - subsys/fb/ - - samples/display/ + - samples/subsys/display/ labels: - "area: Display" @@ -403,13 +402,13 @@ Documentation: - utzig - mbolivar-nordic files: - - doc/* - - doc/static/ - - doc/templates/ - - doc/custom-doxygen/ - - doc/scripts/ + - doc/ + - doc/_static/ + - doc/_templates/ + - doc/_doxygen/ + - doc/_scripts/ - README.rst - - Makefile + - doc/Makefile labels: - "area: Documentation" @@ -437,7 +436,7 @@ Documentation: files: - drivers/audio/ - include/audio/ - - samples/audio/ + - samples/subsys/audio/ labels: - "area: Audio" @@ -527,7 +526,6 @@ Documentation: status: orphaned files: - drivers/dma/ - - include/dt-bindings/dma/ - tests/drivers/dma/ labels: - "area: DMA" @@ -552,7 +550,6 @@ Documentation: files: - drivers/entropy/ - include/drivers/entropy.h - - samples/drivers/entropy/ - tests/drivers/entropy/ labels: - "area: Crypto / RNG" @@ -606,7 +603,6 @@ Documentation: - include/drivers/gpio.h - include/dt-bindings/gpio/ - tests/drivers/gpio/ - - samples/drivers/gpio/ labels: - "area: GPIO" @@ -725,12 +721,14 @@ Documentation: - samples/drivers/lora/ - include/lorawan/ - subsys/lorawan/ - - samples/lorawan/ + - samples/subsys/lorawan/ labels: - "area: LoRa" "Drivers: Modem": - status: orphaned + status: maintained + maintainers: + - rerickson1 files: - drivers/modem/ labels: @@ -801,7 +799,7 @@ Documentation: - drivers/pm_cpu_ops/ - include/drivers/pm_cpu_ops/ - include/drivers/pm_cpu_ops.h - - include/arch/arm/arm-smccc.h + - include/arch/arm64/arm-smccc.h labels: - "area: PM CPU ops" @@ -940,8 +938,11 @@ JSON Web Token: status: orphaned collaborators: - mrfuchs + - sir-branch files: - subsys/jwt/ + - include/data/ + - lib/os/json.c labels: - "area: JSON" @@ -952,7 +953,7 @@ Kconfig: - nashif files: - scripts/kconfig/ - - doc/guides/kconfig/ + - doc/guides/build/kconfig/ labels: - "area: Kconfig" description: >- @@ -967,6 +968,7 @@ Kernel: - nashif - ceolin - dcpleung + - peter-mitsis files: - doc/reference/kernel/ - include/kernel*.h @@ -1203,6 +1205,7 @@ RISCV arch: collaborators: - mgielda - katsuster + - henrikbrixandersen files: - arch/riscv/ - boards/riscv/ @@ -1291,22 +1294,42 @@ Synopsys Platforms: labels: - "platform: Synopsys" -Nuvoton Platforms: - status: orphaned +Nuvoton_NPCX Platforms: + status: maintained + maintainers: + - MulinChao + - ChiHuaL + - WealianLiao collaborators: - MulinChao - - sjg20 - - jackrosenthal - ChiHuaL - WealianLiao + - sjg20 + - keith-zephyr + - jackrosenthal + - fabiobaltieri + - yperess files: - - soc/arm/nuvoton/ + - soc/arm/nuvoton_npcx/ - boards/arm/npcx*/ - dts/arm/nuvoton/ - - dts/bindings/*/nuvoton/* - - drivers/*/*_npcx* + - dts/bindings/*/*npcx* + - drivers/*/*_npcx*.c + labels: + - "platform: Nuvoton_NPCX" + +Nuvoton_Numicro Platforms: + status: orphaned + collaborators: + - ssekar15 + files: + - soc/arm/nuvoton_numicro/ + - boards/arm/nuvoton_pfm*/ + - dts/arm/nuvoton/ + - dts/bindings/*/*numicro* + - drivers/*/*_numicro* labels: - - "platform: Nuvoton" + - "platform: Nuvoton_Numicro" SiLabs Platforms: status: orphaned @@ -1324,7 +1347,7 @@ SiLabs Platforms: Intel Platforms (X86): status: maintained maintainers: - - jenmwms + - enjiamai collaborators: - jhedberg - aasthagr @@ -1351,19 +1374,18 @@ Intel Platforms (Xtensa): NXP Platforms: status: maintained maintainers: - - MaureenHelm + - dleach02 collaborators: - mmahadevan108 - - dleach02 files: - boards/arm/mimx*/ - boards/arm/frdm_k*/ - boards/arm/lpcxpress*/ - - boards/arm/twr_* + - boards/arm/twr_*/ - soc/arm/nxp_*/ - drivers/*/*imx* - - drivers/*/*lpc* - - drivers/*/*mcux* + - drivers/*/*lpc*.c + - drivers/*/*mcux*.c - dts/arm/nxp/ - dts/bindings/*/nxp* labels: @@ -1380,7 +1402,7 @@ Microchip Platforms: - boards/arm/mec*/ - dts/arm/microchip/ - soc/arm/microchip_mec/ - - drivers/*/*mchp* + - drivers/*/*mchp*.c labels: - "platform: Microchip" @@ -1390,7 +1412,7 @@ nRF Platforms: - ioannisg files: - boards/arm/*nrf*/ - - drivers/*/*nrfx* + - drivers/*/*nrfx*.c - soc/arm/nordic_nrf/ - samples/boards/nrf/ - dts/arm/nordic/ @@ -1410,7 +1432,8 @@ STM32 Platforms: - boards/arm/stm32*_dk*/ - boards/arm/stm32*_eval/ - drivers/*/*stm32*/ - - drivers/*/*stm32* + - drivers/*/*stm32*.c + - drivers/*/*stm32*.h - drivers/*/*/*stm32* - dts/arm/st/ - dts/bindings/*/*stm32* @@ -1425,12 +1448,18 @@ Espressif Platforms: status: maintained maintainers: - sylvioalves - files: - - drivers/*/*esp32* - - boards/xtensa/esp32/ - - soc/xtensa/esp32/ + - glaubermaroto + - ulipe + files: + - drivers/*/*esp32*.c + - boards/xtensa/esp32*/ + - soc/xtensa/esp32*/ + - boards/riscv/esp32*/ + - soc/riscv/esp32*/ - dts/xtensa/espressif/ + - dts/riscv/espressif/ - dts/bindings/*/*esp32* + - samples/boards/esp32*/ labels: - "platform: ESP32" @@ -1451,9 +1480,9 @@ ITE Platforms: - sjg20 files: - boards/riscv/it8xxx2_evb/ - - drivers/*/*_ite* + - drivers/*/*it8xxx2* - dts/bindings/*/*ite* - - dts/riscv/it8xxx2.dtsi + - dts/riscv/*it8xxx2* - soc/riscv/riscv-ite/ labels: - "platform: ITE" @@ -1489,7 +1518,7 @@ Tracing: - include/tracing/ - subsys/timing/ - samples/subsys/tracing/ - - doc/guides/tracing/ + - doc/guides/debug_tools/tracing/ - tests/subsys/tracing/ labels: - "area: tracing" @@ -1498,8 +1527,6 @@ USB: status: maintained maintainers: - jfischer-no - collaborators: - - mengxianglinx files: - drivers/usb/ - dts/bindings/usb/ @@ -1586,7 +1613,7 @@ x86 arch: - nashif - dcpleung - ceolin - - jenmwms + - enjiamai - aasthagr files: - arch/x86/ diff --git a/README.rst b/README.rst index 5d6292ee71ff..197787ab50d9 100644 --- a/README.rst +++ b/README.rst @@ -39,7 +39,7 @@ and the documentation's `Getting Started Guide`_ to start developing. Community Support ***************** -Community support is provided via mailing lists and Slack; see the Resources +Community support is provided via mailing lists and Discord; see the Resources below for details. .. _project-resources: @@ -64,8 +64,8 @@ Here's a quick summary of resources to help you find your way around: * **Nightly CI Build Status**: https://lists.zephyrproject.org/g/builds The builds@lists.zephyrproject.org mailing list archives the CI (buildkite) nightly build results. -* **Chat**: Zephyr's Slack workspace is https://zephyrproject.slack.com. Use - this `Slack Invite`_ to register. +* **Chat**: Real-time chat happens in Zephyr's Discord Server. Use + this `Discord Invite`_ to register. * **Contributing**: see the `Contribution Guide`_ * **Wiki**: `Zephyr GitHub wiki`_ * **Issues**: https://github.com/zephyrproject-rtos/zephyr/issues @@ -74,7 +74,7 @@ Here's a quick summary of resources to help you find your way around: tracked separately at https://zephyrprojectsec.atlassian.net. * **Zephyr Project Website**: https://zephyrproject.org -.. _Slack Invite: https://tinyurl.com/2vue8666 +.. _Discord Invite: https://chat.zephyrproject.org .. _supported boards: http://docs.zephyrproject.org/latest/boards/index.html .. _Zephyr Documentation: http://docs.zephyrproject.org .. _Introduction to Zephyr: http://docs.zephyrproject.org/latest/introduction/index.html diff --git a/VERSION b/VERSION index 808984a04c51..bff8b1740e87 100644 --- a/VERSION +++ b/VERSION @@ -1,5 +1,5 @@ VERSION_MAJOR = 2 -VERSION_MINOR = 6 -PATCHLEVEL = 99 +VERSION_MINOR = 7 +PATCHLEVEL = 0 VERSION_TWEAK = 0 EXTRAVERSION = diff --git a/arch/Kconfig b/arch/Kconfig index fa0336ed1164..f7e246920171 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -701,6 +701,17 @@ config DEMAND_PAGING_ALLOW_IRQ runs with interrupts disabled for the entire operation. However, ISRs may also page fault. +config DEMAND_PAGING_PAGE_FRAMES_RESERVE + int "Number of page frames reserved for paging" + default 32 if !LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT + default 0 + help + This sets the number of page frames that will be reserved for + paging that do not count towards free memory. This is to + ensure that there are some page frames available for paging + code and data. Otherwise, it would be possible to exhaust + all page frames via anonymous memory mappings. + config DEMAND_PAGING_STATS bool "Gather Demand Paging Statistics" help diff --git a/arch/arc/CMakeLists.txt b/arch/arc/CMakeLists.txt index 66f4848e23d2..3486a7213746 100644 --- a/arch/arc/CMakeLists.txt +++ b/arch/arc/CMakeLists.txt @@ -20,3 +20,7 @@ if(CONFIG_ISA_ARCV2) endif() add_subdirectory(core) + +if(COMPILER STREQUAL arcmwdt) + add_subdirectory(arcmwdt) +endif() diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 1f260ff017dd..5b0dff0959a5 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -330,7 +330,8 @@ config DCACHE_LINE_SIZE config ARC_EXCEPTION_STACK_SIZE int "ARC exception handling stack size" - default 768 + default 768 if !64BIT + default 2048 if 64BIT help Size in bytes of exception handling stack which is at the top of interrupt stack to get smaller memory footprint because exception @@ -353,11 +354,26 @@ endmenu config MAIN_STACK_SIZE default 4096 if 64BIT -config TEST_EXTRA_STACKSIZE +config ISR_STACK_SIZE + default 4096 if 64BIT + +config SYSTEM_WORKQUEUE_STACK_SIZE + default 4096 if 64BIT + +config IDLE_STACK_SIZE default 1024 if 64BIT +config IPM_CONSOLE_STACK_SIZE + default 2048 if 64BIT + +config TEST_EXTRA_STACKSIZE + default 2048 if 64BIT + config CMSIS_THREAD_MAX_STACK_SIZE - default 1024 if 64BIT + default 2048 if 64BIT config CMSIS_V2_THREAD_MAX_STACK_SIZE - default 1024 if 64BIT + default 2048 if 64BIT + +config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE + default 2048 if 64BIT diff --git a/arch/arc/arcmwdt/CMakeLists.txt b/arch/arc/arcmwdt/CMakeLists.txt new file mode 100644 index 000000000000..9fb901c9b73c --- /dev/null +++ b/arch/arc/arcmwdt/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_ARCMWDT_LIBC OR CONFIG_CPLUSPLUS) + zephyr_sources(arcmwdt-dtr-stubs.c) +endif() diff --git a/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c b/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c new file mode 100644 index 000000000000..5520d891ba16 --- /dev/null +++ b/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021 Synopsys. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +__weak void *__dso_handle; + +int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso) +{ + ARG_UNUSED(destructor); + ARG_UNUSED(objptr); + ARG_UNUSED(dso); + return 0; +} + +int atexit(void (*function)(void)) +{ + return 0; +} diff --git a/arch/arc/core/mpu/Kconfig b/arch/arc/core/mpu/Kconfig index 70a98504a4bb..38b9c58542f3 100644 --- a/arch/arc/core/mpu/Kconfig +++ b/arch/arc/core/mpu/Kconfig @@ -5,11 +5,12 @@ config ARC_MPU_VER int "ARC MPU version" - range 2 4 + range 2 6 default 2 help ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes; - For MPU v3 and v4, the minimum region is 32 bytes + For other versions, the minimum region is 32 bytes; v4 has secure features, + v6 supports up to 32 regions. config ARC_CORE_MPU bool "ARC Core MPU functionalities" @@ -31,8 +32,8 @@ config ARC_MPU select SRAM_REGION_PERMISSIONS select ARC_CORE_MPU select THREAD_STACK_INFO - select GEN_PRIV_STACKS if ARC_MPU_VER = 2 - select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if ARC_MPU_VER = 2 + select GEN_PRIV_STACKS if ARC_MPU_VER != 4 + select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if ARC_MPU_VER !=4 select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if ARC_MPU_VER = 4 help Target has ARC MPU (currently only works for EMSK 2.2/2.3 ARCEM7D) diff --git a/arch/arc/core/mpu/arc_mpu.c b/arch/arc/core/mpu/arc_mpu.c index 9fbe49d84a2d..111bc0f6088a 100644 --- a/arch/arc/core/mpu/arc_mpu.c +++ b/arch/arc/core/mpu/arc_mpu.c @@ -52,8 +52,8 @@ static inline uint32_t get_region_attr_by_type(uint32_t type) } } -#if CONFIG_ARC_MPU_VER == 2 -#include "arc_mpu_v2_internal.h" -#elif CONFIG_ARC_MPU_VER == 4 +#if CONFIG_ARC_MPU_VER == 4 #include "arc_mpu_v4_internal.h" +#else +#include "arc_mpu_common_internal.h" #endif diff --git a/arch/arc/core/mpu/arc_mpu_common_internal.h b/arch/arc/core/mpu/arc_mpu_common_internal.h new file mode 100644 index 000000000000..e6e2174a5984 --- /dev/null +++ b/arch/arc/core/mpu/arc_mpu_common_internal.h @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2021 Synopsys. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_COMMON_INTERNAL_H_ +#define ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_COMMON_INTERNAL_H_ + +#if CONFIG_ARC_MPU_VER == 2 || CONFIG_ARC_MPU_VER == 3 +#include "arc_mpu_v2_internal.h" +#elif CONFIG_ARC_MPU_VER == 6 +#include "arc_mpu_v6_internal.h" +#else +#error "Unsupported MPU version" +#endif + +/** + * @brief configure the base address and size for an MPU region + * + * @param type MPU region type + * @param base base address in RAM + * @param size size of the region + */ +static inline int _mpu_configure(uint8_t type, uint32_t base, uint32_t size) +{ + int32_t region_index = get_region_index_by_type(type); + uint32_t region_attr = get_region_attr_by_type(type); + + LOG_DBG("Region info: 0x%x 0x%x", base, size); + + if (region_attr == 0U || region_index < 0) { + return -EINVAL; + } + + /* + * For ARC MPU, MPU regions can be overlapped, smaller + * region index has higher priority. + */ + _region_init(region_index, base, size, region_attr); + + return 0; +} + +/* ARC Core MPU Driver API Implementation for ARC MP */ + +/** + * @brief enable the MPU + */ +void arc_core_mpu_enable(void) +{ + /* Enable MPU */ + z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, + z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) | AUX_MPU_EN_ENABLE); +} + +/** + * @brief disable the MPU + */ +void arc_core_mpu_disable(void) +{ + /* Disable MPU */ + z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, + z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & AUX_MPU_EN_DISABLE); +} + +/** + * @brief configure the thread's MPU regions + * + * @param thread the target thread + */ +void arc_core_mpu_configure_thread(struct k_thread *thread) +{ +#if defined(CONFIG_USERSPACE) + /* configure stack region of user thread */ + if (thread->base.user_options & K_USER) { + LOG_DBG("configure user thread %p's stack", thread); + if (_mpu_configure(THREAD_STACK_USER_REGION, + (uint32_t)thread->stack_info.start, + thread->stack_info.size) < 0) { + LOG_ERR("user thread %p's stack failed", thread); + return; + } + } + + LOG_DBG("configure thread %p's domain", thread); + arc_core_mpu_configure_mem_domain(thread); +#endif +} + + +/** + * @brief configure the default region + * + * @param region_attr region attribute of default region + */ +void arc_core_mpu_default(uint32_t region_attr) +{ + uint32_t val = z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & (~AUX_MPU_RDP_ATTR_MASK); + + region_attr &= AUX_MPU_RDP_ATTR_MASK; + z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, region_attr | val); +} + +/** + * @brief configure the MPU region + * + * @param index MPU region index + * @param base base address + * @param region_attr region attribute + */ +int arc_core_mpu_region(uint32_t index, uint32_t base, uint32_t size, uint32_t region_attr) +{ + if (index >= get_num_regions()) { + return -EINVAL; + } + + region_attr &= AUX_MPU_RDP_ATTR_MASK; + + _region_init(index, base, size, region_attr); + + return 0; +} + +#if defined(CONFIG_USERSPACE) + +/** + * @brief configure MPU regions for the memory partitions of the memory domain + * + * @param thread the thread which has memory domain + */ +void arc_core_mpu_configure_mem_domain(struct k_thread *thread) +{ + int region_index = get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION); + uint32_t num_partitions; + struct k_mem_partition *pparts; + struct k_mem_domain *mem_domain = NULL; + + if (thread) { + mem_domain = thread->mem_domain_info.mem_domain; + } + + if (mem_domain) { + LOG_DBG("configure domain: %p", mem_domain); + num_partitions = mem_domain->num_partitions; + pparts = mem_domain->partitions; + } else { + LOG_DBG("disable domain partition regions"); + num_partitions = 0U; + pparts = NULL; + } + + for (; region_index >= 0; region_index--) { + if (num_partitions) { + LOG_DBG("set region 0x%x 0x%lx 0x%x", + region_index, pparts->start, pparts->size); + _region_init(region_index, pparts->start, pparts->size, pparts->attr); + num_partitions--; + } else { + /* clear the left mpu entries */ + _region_init(region_index, 0, 0, 0); + } + pparts++; + } +} + +/** + * @brief remove MPU regions for the memory partitions of the memory domain + * + * @param mem_domain the target memory domain + */ +void arc_core_mpu_remove_mem_domain(struct k_mem_domain *mem_domain) +{ + ARG_UNUSED(mem_domain); + + int region_index = get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION); + + for (; region_index >= 0; region_index--) { + _region_init(region_index, 0, 0, 0); + } +} + +/** + * @brief reset MPU region for a single memory partition + * + * @param domain the target memory domain + * @param partition_id memory partition id + */ +void arc_core_mpu_remove_mem_partition(struct k_mem_domain *domain, uint32_t part_id) +{ + ARG_UNUSED(domain); + + int region_index = get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION); + + LOG_DBG("disable region 0x%x", region_index + part_id); + /* Disable region */ + _region_init(region_index + part_id, 0, 0, 0); +} + +/** + * @brief get the maximum number of free regions for memory domain partitions + */ +int arc_core_mpu_get_max_domain_partition_regions(void) +{ + return get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION) + 1; +} + +/** + * @brief validate the given buffer is user accessible or not + */ +int arc_core_mpu_buffer_validate(void *addr, size_t size, int write) +{ + /* + * For ARC MPU, smaller region number takes priority. + * we can stop the iteration immediately once we find the + * matched region that grants permission or denies access. + * + */ + for (int r_index = 0; r_index < get_num_regions(); r_index++) { + if (!_is_enabled_region(r_index) || !_is_in_region(r_index, (uint32_t)addr, size)) { + continue; + } + + if (_is_user_accessible_region(r_index, write)) { + return 0; + } else { + return -EPERM; + } + } + + return -EPERM; +} +#endif /* CONFIG_USERSPACE */ + +/* ARC MPU Driver Initial Setup */ +/* + * @brief MPU default initialization and configuration + * + * This function provides the default configuration mechanism for the Memory + * Protection Unit (MPU). + */ +static int arc_mpu_init(const struct device *arg) +{ + ARG_UNUSED(arg); + + uint32_t num_regions = get_num_regions(); + + if (mpu_config.num_regions > num_regions) { + __ASSERT(0, "Request to configure: %u regions (supported: %u)\n", + mpu_config.num_regions, num_regions); + return -EINVAL; + } + + /* Disable MPU */ + arc_core_mpu_disable(); + + /* + * the MPU regions are filled in the reverse order. + * According to ARCv2 ISA, the MPU region with smaller + * index has higher priority. The static background MPU + * regions in mpu_config will be in the bottom. Then + * the special type regions will be above. + */ + int r_index = num_regions - mpu_config.num_regions; + + /* clear all the regions first */ + for (uint32_t i = 0U; i < r_index; i++) { + _region_init(i, 0, 0, 0); + } + + /* configure the static regions */ + for (uint32_t i = 0U; i < mpu_config.num_regions; i++) { + _region_init(r_index, mpu_config.mpu_regions[i].base, + mpu_config.mpu_regions[i].size, mpu_config.mpu_regions[i].attr); + r_index++; + } + + /* default region: no read, write and execute */ + arc_core_mpu_default(0); + + /* Enable MPU */ + arc_core_mpu_enable(); + + return 0; +} + +SYS_INIT(arc_mpu_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); + +#endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_COMMON_INTERNAL_H_ */ diff --git a/arch/arc/core/mpu/arc_mpu_v2_internal.h b/arch/arc/core/mpu/arc_mpu_v2_internal.h index 20f8cea4b143..f59b1e9184ca 100644 --- a/arch/arc/core/mpu/arc_mpu_v2_internal.h +++ b/arch/arc/core/mpu/arc_mpu_v2_internal.h @@ -6,18 +6,44 @@ #ifndef ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V2_INTERNAL_H_ #define ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V2_INTERNAL_H_ -#define AUX_MPU_RDB_VALID_MASK (0x1) -#define AUX_MPU_EN_ENABLE (0x40000000) -#define AUX_MPU_EN_DISABLE (0xBFFFFFFF) +#define AUX_MPU_EN_ENABLE BIT(30) +#define AUX_MPU_EN_DISABLE ~BIT(30) -#define AUX_MPU_RDP_REGION_SIZE(bits) \ - (((bits - 1) & 0x3) | (((bits - 1) & 0x1C) << 7)) +/* + * The size of the region is a 5-bit field, the three MSB bits are + * represented in [11:9] and the two LSB bits are represented in [1:0]. + * Together these fields specify the size of the region in bytes: + * 00000-00011 Reserved + * 0x4 32 0x5 64 0x6 128 0x7 256 + * 0x8 512 0x9 1k 0xA 2K 0xB 4K + * 0xC 8K 0xD 16K 0xE 32K 0xF 64K + * 0x10 128K 0x11 256K 0x12 512K 0x13 1M + * 0x14 2M 0x15 4M 0x16 8M 0x17 16M + * 0x18 32M 0x19 64M 0x1A 128M 0x1B 256M + * 0x1C 512M 0x1D 1G 0x1E 2G 0x1F 4G + * + * Bit ... 12 11 10 9 8 3 2 1 0 + * ------+------------+------+---+-----------+ + * ... | SIZE[11:9] | ATTR | R | SIZE[1:0] | + * ------+------------+------+---+-----------+ + */ +/* arrange size into proper bit field in RDP aux reg*/ +#define AUX_MPU_RDP_REGION_SIZE(size) (((size - 1) & BIT_MASK(2)) | \ + (((size - 1) & (BIT_MASK(3) << 2)) << 7)) +/* recover size from bit fields in RDP aux reg*/ +#define AUX_MPU_RDP_SIZE_SHIFT(rdp) ((rdp & BIT_MASK(2)) | (((rdp >> 9) & BIT_MASK(3)) << 2)) -#define AUX_MPU_RDP_ATTR_MASK (0x1FC) -#define AUX_MPU_RDP_SIZE_MASK (0xE03) +#define AUX_MPU_RDB_VALID_MASK BIT(0) +#define AUX_MPU_RDP_ATTR_MASK (BIT_MASK(6) << 3) +#define AUX_MPU_RDP_SIZE_MASK ((BIT_MASK(3) << 9) | BIT_MASK(2)) /* For MPU version 2, the minimum protection region size is 2048 bytes */ +#if CONFIG_ARC_MPU_VER == 2 #define ARC_FEATURE_MPU_ALIGNMENT_BITS 11 +/* For MPU version 3, the minimum protection region size is 32 bytes */ +#else +#define ARC_FEATURE_MPU_ALIGNMENT_BITS 5 +#endif /** * This internal function initializes a MPU region @@ -34,7 +60,7 @@ static inline void _region_init(uint32_t index, uint32_t region_addr, uint32_t s bits = ARC_FEATURE_MPU_ALIGNMENT_BITS; } - if ((1 << bits) < size) { + if (BIT(bits) < size) { bits++; } @@ -67,8 +93,7 @@ static inline int get_region_index_by_type(uint32_t type) */ switch (type) { case THREAD_STACK_USER_REGION: - return get_num_regions() - mpu_config.num_regions - - THREAD_STACK_REGION; + return get_num_regions() - mpu_config.num_regions - THREAD_STACK_REGION; case THREAD_STACK_REGION: case THREAD_APP_DATA_REGION: case THREAD_DOMAIN_PARTITION_REGION: @@ -105,14 +130,14 @@ static inline bool _is_in_region(uint32_t r_index, uint32_t start, uint32_t size & (~AUX_MPU_RDB_VALID_MASK); r_size_lshift = z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDP0 + r_index * 2U) & AUX_MPU_RDP_SIZE_MASK; - r_size_lshift = (r_size_lshift & 0x3) | ((r_size_lshift >> 7) & 0x1C); + r_size_lshift = AUX_MPU_RDP_SIZE_SHIFT(r_size_lshift); r_addr_end = r_addr_start + (1 << (r_size_lshift + 1)); if (start >= r_addr_start && (start + size) <= r_addr_end) { - return 1; + return true; } - return 0; + return false; } /** @@ -135,296 +160,4 @@ static inline bool _is_user_accessible_region(uint32_t r_index, int write) (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)); } -/** - * @brief configure the base address and size for an MPU region - * - * @param type MPU region type - * @param base base address in RAM - * @param size size of the region - */ -static inline int _mpu_configure(uint8_t type, uint32_t base, uint32_t size) -{ - int32_t region_index = get_region_index_by_type(type); - uint32_t region_attr = get_region_attr_by_type(type); - - LOG_DBG("Region info: 0x%x 0x%x", base, size); - - if (region_attr == 0U || region_index < 0) { - return -EINVAL; - } - - /* - * For ARC MPU v2, MPU regions can be overlapped, smaller - * region index has higher priority. - */ - _region_init(region_index, base, size, region_attr); - - return 0; -} - -/* ARC Core MPU Driver API Implementation for ARC MPUv2 */ - -/** - * @brief enable the MPU - */ -void arc_core_mpu_enable(void) -{ - /* Enable MPU */ - z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, - z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) | AUX_MPU_EN_ENABLE); -} - -/** - * @brief disable the MPU - */ -void arc_core_mpu_disable(void) -{ - /* Disable MPU */ - z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, - z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & AUX_MPU_EN_DISABLE); -} - -/** - * @brief configure the thread's MPU regions - * - * @param thread the target thread - */ -void arc_core_mpu_configure_thread(struct k_thread *thread) -{ -#if defined(CONFIG_USERSPACE) - /* configure stack region of user thread */ - if (thread->base.user_options & K_USER) { - LOG_DBG("configure user thread %p's stack", thread); - if (_mpu_configure(THREAD_STACK_USER_REGION, - (uint32_t)thread->stack_info.start, - thread->stack_info.size) < 0) { - LOG_ERR("user thread %p's stack failed", thread); - return; - } - } - - LOG_DBG("configure thread %p's domain", thread); - arc_core_mpu_configure_mem_domain(thread); -#endif -} - - -/** - * @brief configure the default region - * - * @param region_attr region attribute of default region - */ -void arc_core_mpu_default(uint32_t region_attr) -{ - uint32_t val = z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & - (~AUX_MPU_RDP_ATTR_MASK); - - region_attr &= AUX_MPU_RDP_ATTR_MASK; - - z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, region_attr | val); -} - -/** - * @brief configure the MPU region - * - * @param index MPU region index - * @param base base address - * @param region_attr region attribute - */ -int arc_core_mpu_region(uint32_t index, uint32_t base, uint32_t size, - uint32_t region_attr) -{ - if (index >= get_num_regions()) { - return -EINVAL; - } - - region_attr &= AUX_MPU_RDP_ATTR_MASK; - - _region_init(index, base, size, region_attr); - - return 0; -} - -#if defined(CONFIG_USERSPACE) - -/** - * @brief configure MPU regions for the memory partitions of the memory domain - * - * @param thread the thread which has memory domain - */ -void arc_core_mpu_configure_mem_domain(struct k_thread *thread) -{ - int region_index = - get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION); - uint32_t num_partitions; - struct k_mem_partition *pparts; - struct k_mem_domain *mem_domain = NULL; - - if (thread) { - mem_domain = thread->mem_domain_info.mem_domain; - } - - if (mem_domain) { - LOG_DBG("configure domain: %p", mem_domain); - num_partitions = mem_domain->num_partitions; - pparts = mem_domain->partitions; - } else { - LOG_DBG("disable domain partition regions"); - num_partitions = 0U; - pparts = NULL; - } - - for (; region_index >= 0; region_index--) { - if (num_partitions) { - LOG_DBG("set region 0x%x 0x%lx 0x%x", - region_index, pparts->start, pparts->size); - _region_init(region_index, pparts->start, - pparts->size, pparts->attr); - num_partitions--; - } else { - /* clear the left mpu entries */ - _region_init(region_index, 0, 0, 0); - } - pparts++; - } -} - -/** - * @brief remove MPU regions for the memory partitions of the memory domain - * - * @param mem_domain the target memory domain - */ -void arc_core_mpu_remove_mem_domain(struct k_mem_domain *mem_domain) -{ - ARG_UNUSED(mem_domain); - - int region_index = - get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION); - - for (; region_index >= 0; region_index--) { - _region_init(region_index, 0, 0, 0); - } -} - -/** - * @brief reset MPU region for a single memory partition - * - * @param domain the target memory domain - * @param partition_id memory partition id - */ -void arc_core_mpu_remove_mem_partition(struct k_mem_domain *domain, - uint32_t part_id) -{ - ARG_UNUSED(domain); - - int region_index = - get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION); - - LOG_DBG("disable region 0x%x", region_index + part_id); - /* Disable region */ - _region_init(region_index + part_id, 0, 0, 0); -} - -/** - * @brief get the maximum number of free regions for memory domain partitions - */ -int arc_core_mpu_get_max_domain_partition_regions(void) -{ - return get_region_index_by_type(THREAD_DOMAIN_PARTITION_REGION) + 1; -} - -/** - * @brief validate the given buffer is user accessible or not - */ -int arc_core_mpu_buffer_validate(void *addr, size_t size, int write) -{ - int r_index; - - /* - * For ARC MPU v2, smaller region number takes priority. - * we can stop the iteration immediately once we find the - * matched region that grants permission or denies access. - * - */ - for (r_index = 0; r_index < get_num_regions(); r_index++) { - if (!_is_enabled_region(r_index) || - !_is_in_region(r_index, (uint32_t)addr, size)) { - continue; - } - - if (_is_user_accessible_region(r_index, write)) { - return 0; - } else { - return -EPERM; - } - } - - return -EPERM; -} -#endif /* CONFIG_USERSPACE */ - -/* ARC MPU Driver Initial Setup */ -/* - * @brief MPU default initialization and configuration - * - * This function provides the default configuration mechanism for the Memory - * Protection Unit (MPU). - */ -static int arc_mpu_init(const struct device *arg) -{ - ARG_UNUSED(arg); - - uint32_t num_regions; - uint32_t i; - - num_regions = get_num_regions(); - - /* ARC MPU supports up to 16 Regions */ - if (mpu_config.num_regions > num_regions) { - __ASSERT(0, - "Request to configure: %u regions (supported: %u)\n", - mpu_config.num_regions, num_regions); - return -EINVAL; - } - - /* Disable MPU */ - arc_core_mpu_disable(); - - int r_index; - /* - * the MPU regions are filled in the reverse order. - * According to ARCv2 ISA, the MPU region with smaller - * index has higher priority. The static background MPU - * regions in mpu_config will be in the bottom. Then - * the special type regions will be above. - * - */ - r_index = num_regions - mpu_config.num_regions; - - /* clear all the regions first */ - for (i = 0U; i < r_index; i++) { - _region_init(i, 0, 0, 0); - } - - /* configure the static regions */ - for (i = 0U; i < mpu_config.num_regions; i++) { - _region_init(r_index, - mpu_config.mpu_regions[i].base, - mpu_config.mpu_regions[i].size, - mpu_config.mpu_regions[i].attr); - r_index++; - } - - /* default region: no read, write and execute */ - arc_core_mpu_default(0); - - /* Enable MPU */ - arc_core_mpu_enable(); - - return 0; -} - -SYS_INIT(arc_mpu_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); - #endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V2_INTERNAL_H_ */ diff --git a/arch/arc/core/mpu/arc_mpu_v6_internal.h b/arch/arc/core/mpu/arc_mpu_v6_internal.h new file mode 100644 index 000000000000..1dbd50bdc84a --- /dev/null +++ b/arch/arc/core/mpu/arc_mpu_v6_internal.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2021 Synopsys. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V6_INTERNAL_H_ +#define ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V6_INTERNAL_H_ + +#define AUX_MPU_EN_BANK_MASK BIT(0) +#define AUX_MPU_EN_IC BIT(12) +#define AUX_MPU_EN_DC BIT(13) +#define AUX_MPU_EN_ENABLE BIT(30) +#define AUX_MPU_EN_DISABLE ~BIT(30) + +/* + * The size of the region is a 5-bit field, the three MSB bits are + * represented in [11:9] and the two LSB bits are represented in [1:0]. + * Together these fields specify the size of the region in bytes: + * 00000-00011 Reserved + * 0x4 32 0x5 64 0x6 128 0x7 256 + * 0x8 512 0x9 1k 0xA 2K 0xB 4K + * 0xC 8K 0xD 16K 0xE 32K 0xF 64K + * 0x10 128K 0x11 256K 0x12 512K 0x13 1M + * 0x14 2M 0x15 4M 0x16 8M 0x17 16M + * 0x18 32M 0x19 64M 0x1A 128M 0x1B 256M + * 0x1C 512M 0x1D 1G 0x1E 2G 0x1F 4G + * + * Bit ... 12 11 10 9 8 3 2 1 0 + * ------+------------+------+---+-----------+ + * ... | SIZE[11:9] | ATTR | R | SIZE[1:0] | + * ------+------------+------+---+-----------+ + */ +/* arrange size into proper bit field in RDP aux reg*/ +#define AUX_MPU_RDP_REGION_SIZE(size) (((size - 1) & BIT_MASK(2)) | \ + (((size - 1) & (BIT_MASK(3) << 2)) << 7)) +/* recover size from bit fields in RDP aux reg*/ +#define AUX_MPU_RDP_SIZE_SHIFT(rdp) ((rdp & BIT_MASK(2)) | (((rdp >> 9) & BIT_MASK(3)) << 2)) + +#define AUX_MPU_RDB_VALID_MASK BIT(0) +#define AUX_MPU_RDP_ATTR_MASK (BIT_MASK(6) << 3) +#define AUX_MPU_RDP_SIZE_MASK ((BIT_MASK(3) << 9) | BIT_MASK(2)) +/* Global code cacheability that applies to a region + * 0x0: (Default) Code is cacheable in all levels of the cache hierarchy + * 0x1: Code is not cacheable in any level of the cache hierarchy + */ +#define AUX_MPU_RDB_IC BIT(12) +/* Global data cacheability that applies to a region + * 0x0: (Default) Data is cacheable in all levels of the cache hierarchy + * 0x1: Data is not cacheable in any level of the cache hierarchy + */ +#define AUX_MPU_RDB_DC BIT(13) +/* Define a MPU region as non-volatile + * 0x0: (Default) The memory space for this MPU region is treated as a volatile uncached space. + * 0x1: The memory space for this MPU region is non-volatile + */ +#define AUX_MPU_RDB_NV BIT(14) + +/* For MPU version 6, the minimum protection region size is 32 bytes */ +#define ARC_FEATURE_MPU_ALIGNMENT_BITS 5 +#define ARC_FEATURE_MPU_BANK_SIZE 16 + +/** + * This internal function select a MPU bank + */ +static inline void _bank_select(uint32_t bank) +{ + uint32_t val; + + val = z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & (~AUX_MPU_EN_BANK_MASK); + z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, val | bank); +} +/** + * This internal function initializes a MPU region + */ +static inline void _region_init(uint32_t index, uint32_t region_addr, + uint32_t size, uint32_t region_attr) +{ + uint32_t bank = index / ARC_FEATURE_MPU_BANK_SIZE; + + index = (index % ARC_FEATURE_MPU_BANK_SIZE) * 2U; + + if (size > 0) { + uint8_t bits = find_msb_set(size) - 1; + + if (bits < ARC_FEATURE_MPU_ALIGNMENT_BITS) { + bits = ARC_FEATURE_MPU_ALIGNMENT_BITS; + } + + if (BIT(bits) < size) { + bits++; + } + + /* Clear size bits and IC, DC bits, and set NV bit + * The default value of NV bit is 0 which means the region is volatile and uncached. + * Setting the NV bit here has no effect on mpu v6 but is for the + * forward compatibility to mpu v7. Currently we do not allow to toggle these bits + * until we implement the control of these region properties + * TODO: support uncacheable regions and volatile uncached regions + */ + region_attr &= ~(AUX_MPU_RDP_SIZE_MASK | AUX_MPU_RDB_IC | AUX_MPU_RDB_DC); + region_attr |= AUX_MPU_RDP_REGION_SIZE(bits) | AUX_MPU_RDB_NV; + region_addr |= AUX_MPU_RDB_VALID_MASK; + } else { + region_addr = 0U; + } + + _bank_select(bank); + z_arc_v2_aux_reg_write(_ARC_V2_MPU_RDP0 + index, region_attr); + z_arc_v2_aux_reg_write(_ARC_V2_MPU_RDB0 + index, region_addr); +} + +/** + * This internal function is utilized by the MPU driver to parse the intent + * type (i.e. THREAD_STACK_REGION) and return the correct region index. + */ +static inline int get_region_index_by_type(uint32_t type) +{ + /* + * The new MPU regions are allocated per type after the statically + * configured regions. The type is one-indexed rather than + * zero-indexed. + * + * For ARC MPU v6, the smaller index has higher priority, so the + * index is allocated in reverse order. Static regions start from + * the biggest index, then thread related regions. + * + */ + switch (type) { + case THREAD_STACK_USER_REGION: + return get_num_regions() - mpu_config.num_regions - THREAD_STACK_REGION; + case THREAD_STACK_REGION: + case THREAD_APP_DATA_REGION: + case THREAD_DOMAIN_PARTITION_REGION: + /* + * Start domain partition region from stack guard region + * since stack guard is not supported. + */ + return get_num_regions() - mpu_config.num_regions - type + 1; + default: + __ASSERT(0, "Unsupported type"); + return -EINVAL; + } +} + +/** + * This internal function checks if region is enabled or not + */ +static inline bool _is_enabled_region(uint32_t r_index) +{ + uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; + uint32_t index = (r_index % ARC_FEATURE_MPU_BANK_SIZE) * 2U; + + _bank_select(bank); + return ((z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDB0 + index) + & AUX_MPU_RDB_VALID_MASK) == AUX_MPU_RDB_VALID_MASK); +} + +/** + * This internal function check if the given buffer in in the region + */ +static inline bool _is_in_region(uint32_t r_index, uint32_t start, uint32_t size) +{ + uint32_t r_addr_start; + uint32_t r_addr_end; + uint32_t r_size_lshift; + uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; + uint32_t index = (r_index % ARC_FEATURE_MPU_BANK_SIZE) * 2U; + + _bank_select(bank); + r_addr_start = z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDB0 + index) & (~AUX_MPU_RDB_VALID_MASK); + r_size_lshift = z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDP0 + index) & AUX_MPU_RDP_SIZE_MASK; + r_size_lshift = AUX_MPU_RDP_SIZE_SHIFT(r_size_lshift); + r_addr_end = r_addr_start + (1 << (r_size_lshift + 1)); + + if (start >= r_addr_start && (start + size) <= r_addr_end) { + return true; + } + + return false; +} + +/** + * This internal function check if the region is user accessible or not + */ +static inline bool _is_user_accessible_region(uint32_t r_index, int write) +{ + uint32_t r_ap; + uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; + uint32_t index = (r_index % ARC_FEATURE_MPU_BANK_SIZE) * 2U; + + _bank_select(bank); + r_ap = z_arc_v2_aux_reg_read(_ARC_V2_MPU_RDP0 + index); + + r_ap &= AUX_MPU_RDP_ATTR_MASK; + + if (write) { + return ((r_ap & (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW)) == + (AUX_MPU_ATTR_UW | AUX_MPU_ATTR_KW)); + } + + return ((r_ap & (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)) == + (AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KR)); +} + +#endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V6_INTERNAL_H_ */ diff --git a/arch/arc/core/reset.S b/arch/arc/core/reset.S index e9b7caefeec1..5ce0196d19bf 100644 --- a/arch/arc/core/reset.S +++ b/arch/arc/core/reset.S @@ -159,7 +159,7 @@ _slave_core_wait: ld r1, [arc_cpu_wake_flag] brne r0, r1, _slave_core_wait - ld sp, [arc_cpu_sp] + LDR sp, arc_cpu_sp /* signal master core that slave core runs */ st 0, [arc_cpu_wake_flag] diff --git a/arch/arc/include/swap_macros.h b/arch/arc/include/swap_macros.h index 558e59484480..8ed587e88785 100644 --- a/arch/arc/include/swap_macros.h +++ b/arch/arc/include/swap_macros.h @@ -308,8 +308,11 @@ */ .macro _check_and_inc_int_nest_counter, reg1, reg2 #ifdef CONFIG_SMP + /* get pointer to _cpu_t of this CPU */ _get_cpu_id MACRO_ARG(reg1) - ld.as MACRO_ARG(reg1), [_curr_cpu, MACRO_ARG(reg1)] + ASLR MACRO_ARG(reg1), MACRO_ARG(reg1), ARC_REGSHIFT + LDR MACRO_ARG(reg1), MACRO_ARG(reg1), _curr_cpu + /* _cpu_t.nested is 32 bit despite of platform bittnes */ ld MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET] #else MOVR MACRO_ARG(reg1), _kernel @@ -331,8 +334,11 @@ */ .macro _dec_int_nest_counter, reg1, reg2 #ifdef CONFIG_SMP + /* get pointer to _cpu_t of this CPU */ _get_cpu_id MACRO_ARG(reg1) - ld.as MACRO_ARG(reg1), [_curr_cpu, MACRO_ARG(reg1)] + ASLR MACRO_ARG(reg1), MACRO_ARG(reg1), ARC_REGSHIFT + LDR MACRO_ARG(reg1), MACRO_ARG(reg1), _curr_cpu + /* _cpu_t.nested is 32 bit despite of platform bittnes */ ld MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET] #else MOVR MACRO_ARG(reg1), _kernel @@ -368,7 +374,7 @@ * the result will be in reg (a reg) */ .macro _get_cpu_id, reg - lr MACRO_ARG(reg), [_ARC_V2_IDENTITY] + LRR MACRO_ARG(reg), [_ARC_V2_IDENTITY] xbfu MACRO_ARG(reg), MACRO_ARG(reg), 0xe8 .endm @@ -377,9 +383,12 @@ */ .macro _get_curr_cpu_irq_stack, irq_sp #ifdef CONFIG_SMP + /* get pointer to _cpu_t of this CPU */ _get_cpu_id MACRO_ARG(irq_sp) - ld.as MACRO_ARG(irq_sp), [_curr_cpu, MACRO_ARG(irq_sp)] - ld MACRO_ARG(irq_sp), [MACRO_ARG(irq_sp), ___cpu_t_irq_stack_OFFSET] + ASLR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), ARC_REGSHIFT + LDR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), _curr_cpu + /* get pointer to irq_stack itself */ + LDR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), ___cpu_t_irq_stack_OFFSET #else MOVR MACRO_ARG(irq_sp), _kernel LDR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), _kernel_offset_to_irq_stack @@ -407,7 +416,7 @@ /* save old thread into switch handle which is required by * wait_for_switch */ - st r2, [r2, ___thread_t_switch_handle_OFFSET] + STR r2, r2, ___thread_t_switch_handle_OFFSET #endif .endm diff --git a/arch/arm/core/aarch32/CMakeLists.txt b/arch/arm/core/aarch32/CMakeLists.txt index 80c3e06c4945..5ae7d1d0d07b 100644 --- a/arch/arm/core/aarch32/CMakeLists.txt +++ b/arch/arm/core/aarch32/CMakeLists.txt @@ -3,15 +3,15 @@ zephyr_library() zephyr_library_sources( - swap.c - swap_helper.S - irq_manage.c - thread.c cpu_idle.S fatal.c + irq_manage.c nmi.c nmi_on_reset.S prep_c.c + swap.c + swap_helper.S + thread.c ) zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S) diff --git a/arch/arm/core/aarch32/Kconfig b/arch/arm/core/aarch32/Kconfig index 9e40d1b6ba6e..1fe06790b5ca 100644 --- a/arch/arm/core/aarch32/Kconfig +++ b/arch/arm/core/aarch32/Kconfig @@ -29,7 +29,9 @@ config CPU_CORTEX_R bool select CPU_CORTEX select HAS_CMSIS_CORE + select ARCH_HAS_NESTED_EXCEPTION_DETECTION select HAS_FLASH_LOAD_OFFSET + select ARCH_HAS_USERSPACE if ARM_MPU select ARCH_HAS_EXTRA_EXCEPTION_INFO help This option signifies the use of a CPU of the Cortex-R family. @@ -132,8 +134,8 @@ config RUNTIME_NMI config PLATFORM_SPECIFIC_INIT bool "Enable platform (SOC) specific startup hook" help - The platform specific initialization code (z_platform_init) is executed - at the beginning of the startup code (__start). + The platform specific initialization code (z_arm_platform_init) is + executed at the beginning of the startup code (__start). config FAULT_DUMP int "Fault dump level" @@ -258,6 +260,37 @@ config FP_SOFTABI endchoice +config FP16 + bool "Half-precision floating point support" + default y + help + This option enables the half-precision (16-bit) floating point support + via the `__fp16` (both IEEE and ARM alternative formats) and the + `_Float16` (IEEE format only) types. + +choice + prompt "FP16 format" + default FP16_IEEE + depends on FP16 + +config FP16_IEEE + bool "FP16 IEEE format" + help + This option selects the IEEE 754-2008 format for FP16. This format can + represent normalized values in the range of 2^(-14) to 65504. There are + 11 bits of significand precision, approximately 3 decimal digits. + +config FP16_ALT + bool "FP16 ARM alternative format" + help + This option selects the ARM alternative format for FP16. This + representation is similar to the IEEE 754-2008 format, but does not + support infinites or NaNs. Instead, the range of exponents is extended, + so that this format can represent normalized values in the range of + 2^(-14) to 131008. + +endchoice + rsource "cortex_m/Kconfig" rsource "cortex_a_r/Kconfig" diff --git a/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt b/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt index 504eb1d7b38d..a044a2b20bb8 100644 --- a/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt +++ b/arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt @@ -3,13 +3,15 @@ zephyr_library() zephyr_library_sources( - vector_table.S - reset.S exc.S exc_exit.S fault.c irq_init.c reboot.c + reset.S stacks.c tcm.c + vector_table.S ) + +zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c) diff --git a/arch/arm/core/aarch32/cortex_a_r/exc.S b/arch/arm/core/aarch32/cortex_a_r/exc.S index 7585d857dd5c..b7ec6f46d9e2 100644 --- a/arch/arm/core/aarch32/cortex_a_r/exc.S +++ b/arch/arm/core/aarch32/cortex_a_r/exc.S @@ -156,6 +156,17 @@ SECTION_SUBSEC_FUNC(TEXT, __exc, z_arm_data_abort) exception_entry MODE_ABT bl z_arm_fault_data + + /* + * If z_arm_fault_data returns false, then we recovered from + * the error. It may have updated $pc, so copy $pc back to + * the true esf from the one passed to z_arm_fault_data. + */ + cmp r0, #0 + ldreq r1, [sp, #24] + exception_exit + streq r1, [sp, #24] + b z_arm_exc_exit diff --git a/arch/arm/core/aarch32/cortex_a_r/exc_exit.S b/arch/arm/core/aarch32/cortex_a_r/exc_exit.S index 172b3044bea0..a4e864341fbd 100644 --- a/arch/arm/core/aarch32/cortex_a_r/exc_exit.S +++ b/arch/arm/core/aarch32/cortex_a_r/exc_exit.S @@ -26,6 +26,42 @@ GTEXT(z_arm_int_exit) GTEXT(z_arm_pendsv) GDATA(_kernel) +.macro userspace_exc_exit +#if defined(CONFIG_USERSPACE) + cps #MODE_SVC + sub sp, #8 + push {r0-r1} + + /* + * Copy return state from sys/usr state onto the svc stack. + * We have to put $sp_usr back into $sp since we switched to + * the privileged stack on exception entry. The return state + * is on the privileged stack so it needs to be copied to the + * svc stack since we cannot trust the usr stack. + */ + cps #MODE_SYS + pop {r0-r1} + + cps #MODE_SVC + str r0, [sp, #8] + str r1, [sp, #12] + + /* Only switch the stacks if returning to a user thread */ + and r1, #MODE_MASK + cmp r1, #MODE_USR + bne system_thread_exit\@ + + /* Restore user stack pointer */ + ldr r0, =_kernel + ldr r0, [r0, #_kernel_offset_to_current] + cps #MODE_SYS + ldr sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */ + cps #MODE_SVC +system_thread_exit\@: + pop {r0-r1} +#endif +.endm + /** * @brief Kernel housekeeping when exiting interrupt handler installed directly * in the vector table @@ -98,6 +134,7 @@ __EXIT_INT: */ cps #MODE_SYS pop {r0-r3, r12, lr} + userspace_exc_exit rfeia sp! /** @@ -157,6 +194,7 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit) /* Return to the switched thread */ cps #MODE_SYS pop {r0-r3, r12, lr} + userspace_exc_exit rfeia sp! __EXIT_EXC: diff --git a/arch/arm/core/aarch32/cortex_a_r/fault.c b/arch/arm/core/aarch32/cortex_a_r/fault.c index 007ee2950563..f4a77fe8bed3 100644 --- a/arch/arm/core/aarch32/cortex_a_r/fault.c +++ b/arch/arm/core/aarch32/cortex_a_r/fault.c @@ -7,6 +7,7 @@ #include #include +#include #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -129,6 +130,35 @@ bool z_arm_fault_prefetch(z_arch_esf_t *esf) return true; } +#ifdef CONFIG_USERSPACE +Z_EXC_DECLARE(z_arm_user_string_nlen); + +static const struct z_exc_handle exceptions[] = { + Z_EXC_HANDLE(z_arm_user_string_nlen) +}; + +/* Perform an assessment whether an MPU fault shall be + * treated as recoverable. + * + * @return true if error is recoverable, otherwise return false. + */ +static bool memory_fault_recoverable(z_arch_esf_t *esf) +{ + for (int i = 0; i < ARRAY_SIZE(exceptions); i++) { + /* Mask out instruction mode */ + uint32_t start = (uint32_t)exceptions[i].start & ~0x1U; + uint32_t end = (uint32_t)exceptions[i].end & ~0x1U; + + if (esf->basic.pc >= start && esf->basic.pc < end) { + esf->basic.pc = (uint32_t)(exceptions[i].fixup); + return true; + } + } + + return false; +} +#endif + /** * @brief Data abort fault handler * @@ -143,6 +173,15 @@ bool z_arm_fault_data(z_arch_esf_t *esf) /* Read Data Fault Address Register (DFAR) */ uint32_t dfar = __get_DFAR(); +#if defined(CONFIG_USERSPACE) + if ((fs == FSR_FS_BACKGROUND_FAULT) + || (fs == FSR_FS_PERMISSION_FAULT)) { + if (memory_fault_recoverable(esf)) { + return false; + } + } +#endif + /* Print fault information*/ LOG_ERR("***** DATA ABORT *****"); if (FAULT_DUMP_VERBOSE) { diff --git a/arch/arm/core/aarch32/cortex_a_r/reset.S b/arch/arm/core/aarch32/cortex_a_r/reset.S index ca0c57372e8f..9f5466b3899f 100644 --- a/arch/arm/core/aarch32/cortex_a_r/reset.S +++ b/arch/arm/core/aarch32/cortex_a_r/reset.S @@ -29,7 +29,7 @@ GDATA(z_arm_fiq_stack) GDATA(z_arm_abort_stack) GDATA(z_arm_undef_stack) #if defined(CONFIG_PLATFORM_SPECIFIC_INIT) -GTEXT(z_platform_init) +GTEXT(z_arm_platform_init) #endif /** @@ -177,7 +177,7 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start) #if defined(CONFIG_PLATFORM_SPECIFIC_INIT) /* Execute platform-specific initialisation if applicable */ - bl z_platform_init + bl z_arm_platform_init #endif #if defined(CONFIG_WDOG_INIT) diff --git a/arch/arm/core/aarch32/cortex_a_r/thread.c b/arch/arm/core/aarch32/cortex_a_r/thread.c new file mode 100644 index 000000000000..91c46bbf794b --- /dev/null +++ b/arch/arm/core/aarch32/cortex_a_r/thread.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2021 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +bool z_arm_thread_is_in_user_mode(void) +{ + uint32_t value; + + /* + * For Cortex-R, the mode (lower 5) bits will be 0x10 for user mode. + */ + value = __get_CPSR(); + return ((value & CPSR_M_Msk) == CPSR_M_USR); +} diff --git a/arch/arm/core/aarch32/cortex_m/CMakeLists.txt b/arch/arm/core/aarch32/cortex_m/CMakeLists.txt index f20ffb2d97da..4e3050abd579 100644 --- a/arch/arm/core/aarch32/cortex_m/CMakeLists.txt +++ b/arch/arm/core/aarch32/cortex_m/CMakeLists.txt @@ -3,17 +3,18 @@ zephyr_library() zephyr_library_sources( - vector_table.S - reset.S - fault_s.S - fault.c exc_exit.S + fault.c + fault_s.S fpu.c - scb.c irq_init.c + reset.S + scb.c thread_abort.c + vector_table.S ) +zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c) zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S) diff --git a/arch/arm/core/aarch32/cortex_m/Kconfig b/arch/arm/core/aarch32/cortex_m/Kconfig index 8a501a89f032..fd78960e9dd7 100644 --- a/arch/arm/core/aarch32/cortex_m/Kconfig +++ b/arch/arm/core/aarch32/cortex_m/Kconfig @@ -257,6 +257,22 @@ config ARMV8_M_DSP This option signifies the use of an ARMv8-M processor implementation supporting the DSP Extension. +config ARMV8_1_M_MVEI + bool + depends on ARMV8_1_M_MAINLINE + depends on ARMV8_M_DSP + help + This option signifies the use of an ARMv8.1-M processor implementation + supporting the M-Profile Vector Extension (MVE) integer instruction set. + +config ARMV8_1_M_MVEF + bool + depends on ARMV8_1_M_MVEI + help + This option signifies the use of an ARMv8.1-M processor implementation + supporting the M-Profile Vector Extension (MVE) floating-point + instruction set. + menu "ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 options" depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE diff --git a/arch/arm/core/aarch32/cortex_m/fault.c b/arch/arm/core/aarch32/cortex_m/fault.c index b0f6aaf8d30b..6fa6cef1800f 100644 --- a/arch/arm/core/aarch32/cortex_m/fault.c +++ b/arch/arm/core/aarch32/cortex_m/fault.c @@ -632,6 +632,25 @@ static void debug_monitor(z_arch_esf_t *esf, bool *recoverable) #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ +static inline bool z_arm_is_synchronous_svc(z_arch_esf_t *esf) +{ + uint16_t *ret_addr = (uint16_t *)esf->basic.pc; + /* SVC is a 16-bit instruction. On a synchronous SVC + * escalated to Hard Fault, the return address is the + * next instruction, i.e. after the SVC. + */ +#define _SVC_OPCODE 0xDF00 + + uint16_t fault_insn = *(ret_addr - 1); + + if (((fault_insn & 0xff00) == _SVC_OPCODE) && + ((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) { + return true; + } +#undef _SVC_OPCODE + return false; +} + /** * * @brief Dump hard fault information @@ -655,21 +674,11 @@ static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable) * priority. We handle the case of Kernel OOPS and Stack * Fail here. */ - uint16_t *ret_addr = (uint16_t *)esf->basic.pc; - /* SVC is a 16-bit instruction. On a synchronous SVC - * escalated to Hard Fault, the return address is the - * next instruction, i.e. after the SVC. - */ -#define _SVC_OPCODE 0xDF00 - - uint16_t fault_insn = *(ret_addr - 1); - if (((fault_insn & 0xff00) == _SVC_OPCODE) && - ((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) { + if (z_arm_is_synchronous_svc(esf)) { PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0); reason = esf->basic.r0; } -#undef _SVC_OPCODE *recoverable = memory_fault_recoverable(esf, true); #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) @@ -677,9 +686,14 @@ static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable) if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) { PR_EXC(" Bus fault on vector table read"); + } else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) { + PR_EXC(" Debug event"); } else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) { PR_EXC(" Fault escalation (see below)"); - if (SCB_MMFSR != 0) { + if (z_arm_is_synchronous_svc(esf)) { + PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0); + reason = esf->basic.r0; + } else if (SCB_MMFSR != 0) { reason = mem_manage_fault(esf, 1, recoverable); } else if (SCB_BFSR != 0) { reason = bus_fault(esf, 1, recoverable); @@ -690,10 +704,13 @@ static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable) secure_fault(esf); #endif /* CONFIG_ARM_SECURE_FIRMWARE */ } else { - ; + __ASSERT(0, + "Fault escalation without FSR info"); } } else { - ; + __ASSERT(0, + "HardFault without HFSR info" + " Shall never occur"); } #else #error Unknown ARM architecture diff --git a/arch/arm/core/aarch32/cortex_m/reset.S b/arch/arm/core/aarch32/cortex_m/reset.S index c7ed3c2742cd..25b7ebecca6b 100644 --- a/arch/arm/core/aarch32/cortex_m/reset.S +++ b/arch/arm/core/aarch32/cortex_m/reset.S @@ -22,7 +22,7 @@ GTEXT(z_arm_reset) GTEXT(memset) GDATA(z_interrupt_stacks) #if defined(CONFIG_PLATFORM_SPECIFIC_INIT) -GTEXT(z_platform_init) +GTEXT(z_arm_platform_init) #endif #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT) GTEXT(z_arm_init_arch_hw_at_boot) @@ -79,7 +79,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) #endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */ #if defined(CONFIG_PLATFORM_SPECIFIC_INIT) - bl z_platform_init + bl z_arm_platform_init #endif #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT) diff --git a/arch/arm/core/aarch32/cortex_m/thread.c b/arch/arm/core/aarch32/cortex_m/thread.c new file mode 100644 index 000000000000..3e829a17b7ce --- /dev/null +++ b/arch/arm/core/aarch32/cortex_m/thread.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2021 Lexmark International, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +bool z_arm_thread_is_in_user_mode(void) +{ + uint32_t value; + + /* return mode information */ + value = __get_CONTROL(); + return (value & CONTROL_nPRIV_Msk) != 0; +} diff --git a/arch/arm/core/aarch32/cortex_m/vector_table.S b/arch/arm/core/aarch32/cortex_m/vector_table.S index d54aa68d14fc..d73aabdcb544 100644 --- a/arch/arm/core/aarch32/cortex_m/vector_table.S +++ b/arch/arm/core/aarch32/cortex_m/vector_table.S @@ -22,6 +22,10 @@ #include "vector_table.h" _ASM_FILE_PROLOGUE +/* + * Tell armclang that stack alignment are ensured. + */ +.eabi_attribute Tag_ABI_align_preserved, 1 GDATA(z_main_stack) @@ -73,7 +77,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table) #if defined(CONFIG_MULTITHREADING) .word z_arm_pendsv #else - .word 0 + .word z_arm_exc_spurious #endif #if defined(CONFIG_CPU_CORTEX_M_HAS_SYSTICK) #if defined(CONFIG_SYS_CLOCK_EXISTS) diff --git a/arch/arm/core/aarch32/cortex_m/vector_table.h b/arch/arm/core/aarch32/cortex_m/vector_table.h index 3fbe6593b72b..a78af2444ec0 100644 --- a/arch/arm/core/aarch32/cortex_m/vector_table.h +++ b/arch/arm/core/aarch32/cortex_m/vector_table.h @@ -51,7 +51,9 @@ GTEXT(z_arm_pendsv) GTEXT(z_arm_exc_spurious) GTEXT(z_arm_prep_c) +#if defined(CONFIG_GEN_ISR_TABLES) GTEXT(_isr_wrapper) +#endif /* CONFIG_GEN_ISR_TABLES */ #else /* _ASMLANGUAGE */ diff --git a/arch/arm/core/aarch32/fatal.c b/arch/arm/core/aarch32/fatal.c index 64f884f77b9d..43c840ebb7b1 100644 --- a/arch/arm/core/aarch32/fatal.c +++ b/arch/arm/core/aarch32/fatal.c @@ -13,6 +13,7 @@ */ #include +#include #include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -83,9 +84,9 @@ void z_do_kernel_oops(const z_arch_esf_t *esf) unsigned int reason = esf->basic.r0; #if defined(CONFIG_USERSPACE) - if ((__get_CONTROL() & CONTROL_nPRIV_Msk) == CONTROL_nPRIV_Msk) { + if (z_arm_preempted_thread_in_user_mode(esf)) { /* - * Exception triggered from nPRIV mode. + * Exception triggered from user mode. * * User mode is only allowed to induce oopses and stack check * failures via software-triggered system fatal exceptions. diff --git a/arch/arm/core/aarch32/irq_manage.c b/arch/arm/core/aarch32/irq_manage.c index 1a8305920bfb..be0a3d03ed83 100644 --- a/arch/arm/core/aarch32/irq_manage.c +++ b/arch/arm/core/aarch32/irq_manage.c @@ -291,6 +291,7 @@ void irq_target_state_set_all_non_secure(void) #endif /* CONFIG_ARM_SECURE_FIRMWARE */ #ifdef CONFIG_DYNAMIC_INTERRUPTS +#ifdef CONFIG_GEN_ISR_TABLES int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, void (*routine)(const void *parameter), const void *parameter, uint32_t flags) @@ -299,6 +300,7 @@ int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, z_arm_irq_priority_set(irq, priority, flags); return irq; } +#endif /* CONFIG_GEN_ISR_TABLES */ #ifdef CONFIG_DYNAMIC_DIRECT_INTERRUPTS static inline void z_arm_irq_dynamic_direct_isr_dispatch(void) diff --git a/arch/arm/core/aarch32/isr_wrapper.S b/arch/arm/core/aarch32/isr_wrapper.S index 68bff7391d96..0f60ade2ca36 100644 --- a/arch/arm/core/aarch32/isr_wrapper.S +++ b/arch/arm/core/aarch32/isr_wrapper.S @@ -12,6 +12,10 @@ * Wrapper installed in vector table for handling dynamic interrupts that accept * a parameter. */ +/* + * Tell armclang that stack alignment are ensured. + */ +.eabi_attribute Tag_ABI_align_preserved, 1 #include #include @@ -45,6 +49,35 @@ SECTION_FUNC(TEXT, _isr_wrapper) #if defined(CONFIG_CPU_CORTEX_M) push {r0,lr} /* r0, lr are now the first items on the stack */ #elif defined(CONFIG_CPU_CORTEX_R) + +#if defined(CONFIG_USERSPACE) + /* See comment below about svc stack usage */ + cps #MODE_SVC + push {r0} + + /* Determine if interrupted thread was in user context */ + cps #MODE_IRQ + mrs r0, spsr + and r0, #MODE_MASK + cmp r0, #MODE_USR + bne isr_system_thread + + ldr r0, =_kernel + ldr r0, [r0, #_kernel_offset_to_current] + + /* Save away user stack pointer */ + cps #MODE_SYS + str sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */ + + /* Switch to privileged stack */ + ldr sp, [r0, #_thread_offset_to_priv_stack_end] /* priv stack end */ + +isr_system_thread: + cps #MODE_SVC + pop {r0} + cps #MODE_IRQ +#endif + /* * Save away r0-r3, r12 and lr_irq for the previous context to the * process stack since they are clobbered here. Also, save away lr diff --git a/arch/arm/core/aarch32/mpu/CMakeLists.txt b/arch/arm/core/aarch32/mpu/CMakeLists.txt index 8c7aa7e3c9de..bae30c23bea1 100644 --- a/arch/arm/core/aarch32/mpu/CMakeLists.txt +++ b/arch/arm/core/aarch32/mpu/CMakeLists.txt @@ -5,3 +5,11 @@ zephyr_library() zephyr_library_sources( arm_core_mpu.c) zephyr_library_sources_ifdef(CONFIG_CPU_HAS_ARM_MPU arm_mpu.c) zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_MPU nxp_mpu.c) + +if (CONFIG_CPU_CORTEX_R) +zephyr_library_include_directories(cortex_a_r) +elseif (CONFIG_CPU_CORTEX_M) +zephyr_library_include_directories(cortex_m) +else () +message(FATAL_ERROR "CPU is not Cortex-A/R/M") +endif () diff --git a/arch/arm/core/aarch32/mpu/arm_core_mpu.c b/arch/arm/core/aarch32/mpu/arm_core_mpu.c index 5ad66fe5968c..bc3b8ce8f392 100644 --- a/arch/arm/core/aarch32/mpu/arm_core_mpu.c +++ b/arch/arm/core/aarch32/mpu/arm_core_mpu.c @@ -82,8 +82,8 @@ static const struct z_arm_mpu_partition static_regions[] = { #if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT) { /* Special RAM area for program text */ - .start = (uint32_t)&_ramfunc_ram_start, - .size = (uint32_t)&_ramfunc_ram_size, + .start = (uint32_t)&__ramfunc_start, + .size = (uint32_t)&__ramfunc_size, .attr = K_MEM_PARTITION_P_RX_U_RX, }, #endif /* CONFIG_ARCH_HAS_RAMFUNC_SUPPORT */ @@ -278,7 +278,7 @@ void z_arm_configure_dynamic_mpu_regions(struct k_thread *thread) __ASSERT((uintptr_t)&z_priv_stacks_ram_start <= guard_start, "Guard start: (0x%lx) below privilege stacks boundary: (%p)", - guard_start, &z_priv_stacks_ram_start); + guard_start, z_priv_stacks_ram_start); } else #endif /* CONFIG_USERSPACE */ { diff --git a/arch/arm/core/aarch32/mpu/arm_mpu.c b/arch/arm/core/aarch32/mpu/arm_mpu.c index f8c9d589a29d..30e9098d274e 100644 --- a/arch/arm/core/aarch32/mpu/arm_mpu.c +++ b/arch/arm/core/aarch32/mpu/arm_mpu.c @@ -39,36 +39,12 @@ LOG_MODULE_DECLARE(mpu); */ static uint8_t static_regions_num; -/** - * Get the number of supported MPU regions. - */ -static inline uint8_t get_num_regions(void) -{ -#if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ - defined(CONFIG_CPU_CORTEX_M3) || \ - defined(CONFIG_CPU_CORTEX_M4) - /* Cortex-M0+, Cortex-M3, and Cortex-M4 MCUs may - * have a fixed number of 8 MPU regions. - */ - return 8; -#elif defined(NUM_MPU_REGIONS) - /* Retrieve the number of regions from DTS configuration. */ - return NUM_MPU_REGIONS; -#else - - uint32_t type = MPU->TYPE; - - type = (type & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; - - return (uint8_t)type; -#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */ -} - /* Include architecture-specific internal headers. */ #if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ defined(CONFIG_CPU_CORTEX_M3) || \ defined(CONFIG_CPU_CORTEX_M4) || \ - defined(CONFIG_CPU_CORTEX_M7) + defined(CONFIG_CPU_CORTEX_M7) || \ + defined(CONFIG_CPU_CORTEX_R) #include "arm_mpu_v7_internal.h" #elif defined(CONFIG_CPU_CORTEX_M23) || \ defined(CONFIG_CPU_CORTEX_M33) || \ @@ -109,6 +85,9 @@ static int mpu_configure_region(const uint8_t index, /* Populate internal ARM MPU region configuration structure. */ region_conf.base = new_region->start; +#if defined(CONFIG_CPU_CORTEX_R) + region_conf.size = size_to_mpu_rasr_size(new_region->size); +#endif get_region_attr_from_mpu_partition_info(®ion_conf.attr, &new_region->attr, new_region->start, new_region->size); @@ -158,6 +137,38 @@ static int mpu_configure_regions(const struct z_arm_mpu_partition /* ARM Core MPU Driver API Implementation for ARM MPU */ + +#if defined(CONFIG_CPU_CORTEX_R) +/** + * @brief enable the MPU by setting bit in SCTRL register + */ +void arm_core_mpu_enable(void) +{ + uint32_t val; + + __asm__ volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) ::); + val |= SCTRL_MPU_ENABLE; + /* Make sure that all the registers are set before proceeding */ + __asm__ volatile ("dsb"); + __asm__ volatile ("mcr p15, 0, %0, c1, c0, 0" :: "r" (val) :); + __asm__ volatile ("isb"); +} + +/** + * @brief disable the MPU by clearing bit in SCTRL register + */ +void arm_core_mpu_disable(void) +{ + uint32_t val; + + __asm__ volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) ::); + val &= ~SCTRL_MPU_ENABLE; + /* Force any outstanding transfers to complete before disabling MPU */ + __asm__ volatile ("dsb"); + __asm__ volatile ("mcr p15, 0, %0, c1, c0, 0" :: "r" (val) :); + __asm__ volatile ("isb"); +} +#else /** * @brief enable the MPU */ @@ -184,6 +195,7 @@ void arm_core_mpu_disable(void) /* Disable MPU */ MPU->CTRL = 0; } +#endif #if defined(CONFIG_USERSPACE) /** diff --git a/arch/arm/core/aarch32/mpu/arm_mpu_v7_internal.h b/arch/arm/core/aarch32/mpu/arm_mpu_v7_internal.h index 1d928f9bbecb..543717f731af 100644 --- a/arch/arm/core/aarch32/mpu/arm_mpu_v7_internal.h +++ b/arch/arm/core/aarch32/mpu/arm_mpu_v7_internal.h @@ -10,6 +10,7 @@ #include +#include #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL #include @@ -29,13 +30,26 @@ static void region_init(const uint32_t index, const struct arm_mpu_region *region_conf) { /* Select the region you want to access */ - MPU->RNR = index; + set_region_number(index); + /* Configure the region */ +#if defined(CONFIG_CPU_CORTEX_R) + /* + * Clear size register, which disables the entry. It cannot be + * enabled as we reconfigure it. + */ + set_region_size(0); + + set_region_base_address(region_conf->base & MPU_RBAR_ADDR_Msk); + set_region_attributes(region_conf->attr.rasr); + set_region_size(region_conf->size | MPU_RASR_ENABLE_Msk); +#else MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | index; MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk; LOG_DBG("[%d] 0x%08x 0x%08x", index, region_conf->base, region_conf->attr.rasr); +#endif } /* @brief Partition sanity check @@ -105,7 +119,13 @@ static inline void get_region_attr_from_mpu_partition_info( */ (void) base; +#if defined(CONFIG_CPU_CORTEX_R) + (void) size; + + p_attr->rasr = attr->rasr_attr; +#else p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size); +#endif } #if defined(CONFIG_USERSPACE) @@ -122,115 +142,11 @@ static inline int get_dyn_region_min_index(void) return static_regions_num; } -/** - * This internal function converts the SIZE field value of MPU_RASR - * to the region size (in bytes). - */ -static inline uint32_t mpu_rasr_size_to_size(uint32_t rasr_size) -{ - return 1 << (rasr_size + 1U); -} - -static inline uint32_t mpu_region_get_base(uint32_t index) -{ - MPU->RNR = index; - return MPU->RBAR & MPU_RBAR_ADDR_Msk; -} - -static inline uint32_t mpu_region_get_size(uint32_t index) -{ - MPU->RNR = index; - uint32_t rasr_size = (MPU->RASR & MPU_RASR_SIZE_Msk) >> MPU_RASR_SIZE_Pos; - - return mpu_rasr_size_to_size(rasr_size); -} - -/** - * This internal function checks if region is enabled or not. - * - * Note: - * The caller must provide a valid region number. - */ -static inline int is_enabled_region(uint32_t index) -{ - /* Lock IRQs to ensure RNR value is correct when reading RASR. */ - unsigned int key; - uint32_t rasr; - - key = irq_lock(); - MPU->RNR = index; - rasr = MPU->RASR; - irq_unlock(key); - - return (rasr & MPU_RASR_ENABLE_Msk) ? 1 : 0; -} - /* Only a single bit is set for all user accessible permissions. * In ARMv7-M MPU this is bit AP[1]. */ #define MPU_USER_READ_ACCESSIBLE_Msk (P_RW_U_RO & P_RW_U_RW & P_RO_U_RO & RO) -/** - * This internal function returns the access permissions of an MPU region - * specified by its region index. - * - * Note: - * The caller must provide a valid region number. - */ -static inline uint32_t get_region_ap(uint32_t r_index) -{ - /* Lock IRQs to ensure RNR value is correct when reading RASR. */ - unsigned int key; - uint32_t rasr; - - key = irq_lock(); - MPU->RNR = r_index; - rasr = MPU->RASR; - irq_unlock(key); - - return (rasr & MPU_RASR_AP_Msk) >> MPU_RASR_AP_Pos; -} - -/** - * This internal function checks if the given buffer is in the region. - * - * Note: - * The caller must provide a valid region number. - */ -static inline int is_in_region(uint32_t r_index, uint32_t start, uint32_t size) -{ - uint32_t r_addr_start; - uint32_t r_size_lshift; - uint32_t r_addr_end; - uint32_t end; - - /* Lock IRQs to ensure RNR value is correct when reading RBAR, RASR. */ - unsigned int key; - uint32_t rbar, rasr; - - key = irq_lock(); - MPU->RNR = r_index; - rbar = MPU->RBAR; - rasr = MPU->RASR; - irq_unlock(key); - - r_addr_start = rbar & MPU_RBAR_ADDR_Msk; - r_size_lshift = ((rasr & MPU_RASR_SIZE_Msk) >> - MPU_RASR_SIZE_Pos) + 1U; - r_addr_end = r_addr_start + (1UL << r_size_lshift) - 1UL; - - size = size == 0U ? 0U : size - 1U; - if (u32_add_overflow(start, size, &end)) { - return 0; - } - - if ((start >= r_addr_start) && (end <= r_addr_end)) { - return 1; - } - - return 0; -} - /** * This internal function checks if the region is user accessible or not. * @@ -256,6 +172,9 @@ static inline int is_user_accessible_region(uint32_t r_index, int write) static inline int mpu_buffer_validate(void *addr, size_t size, int write) { int32_t r_index; + int rc = -EPERM; + + int key = arch_irq_lock(); /* Iterate all mpu regions in reversed order */ for (r_index = get_num_regions() - 1U; r_index >= 0; r_index--) { @@ -270,14 +189,15 @@ static inline int mpu_buffer_validate(void *addr, size_t size, int write) * matched region that grants permission or denies access. */ if (is_user_accessible_region(r_index, write)) { - return 0; + rc = 0; } else { - return -EPERM; + rc = -EPERM; } + break; } - return -EPERM; - + arch_irq_unlock(key); + return rc; } #endif /* CONFIG_USERSPACE */ diff --git a/arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h b/arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h index 201486cb8c54..620c1ba699e1 100644 --- a/arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h +++ b/arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h @@ -530,6 +530,23 @@ static int mpu_mark_areas_for_dynamic_regions( return 0; } +/** + * Get the number of supported MPU regions. + */ +static inline uint8_t get_num_regions(void) +{ +#if defined(NUM_MPU_REGIONS) + /* Retrieve the number of regions from DTS configuration. */ + return NUM_MPU_REGIONS; +#else + uint32_t type = MPU->TYPE; + + type = (type & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; + + return (uint8_t)type; +#endif /* NUM_MPU_REGIONS */ +} + /* This internal function programs the dynamic MPU regions. * * It returns the number of MPU region indices configured. diff --git a/arch/arm/core/aarch32/mpu/cortex_a_r/arm_mpu_internal.h b/arch/arm/core/aarch32/mpu/cortex_a_r/arm_mpu_internal.h new file mode 100644 index 000000000000..f9660e5598f9 --- /dev/null +++ b/arch/arm/core/aarch32/mpu/cortex_a_r/arm_mpu_internal.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2019 Lexmark International, Inc. + */ + +#include + +/** + * Get the number of supported MPU regions. + */ +static inline uint8_t get_num_regions(void) +{ +#if defined(NUM_MPU_REGIONS) + /* Retrieve the number of regions from DTS configuration. */ + return NUM_MPU_REGIONS; +#else + uint32_t type; + + __asm__ volatile("mrc p15, 0, %0, c0, c0, 4" : "=r" (type) ::); + + type = (type & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; + + return (uint8_t)type; +#endif /* NUM_MPU_REGIONS */ +} + +static inline uint32_t get_region_attributes(void) +{ + uint32_t attr; + + __asm__ volatile("mrc p15, 0, %0, c6, c1, 4" : "=r" (attr) ::); + return attr; +} + +static inline uint32_t get_region_base_address(void) +{ + uint32_t addr; + + __asm__ volatile("mrc p15, 0, %0, c6, c1, 0" : "=r" (addr) ::); + return addr; +} + +static inline uint32_t get_region_size(void) +{ + uint32_t size; + + __asm__ volatile("mrc p15, 0, %0, c6, c1, 2" : "=r" (size) ::); + return size; +} + +static inline void set_region_attributes(uint32_t attr) +{ + __asm__ volatile("mcr p15, 0, %0, c6, c1, 4" :: "r" (attr) :); +} + +static inline void set_region_base_address(uint32_t addr) +{ + __asm__ volatile("mcr p15, 0, %0, c6, c1, 0" :: "r" (addr) :); +} + +static inline void set_region_number(uint32_t index) +{ + __asm__ volatile("mcr p15, 0, %0, c6, c2, 0" :: "r" (index) :); +} + +static inline uint32_t mpu_region_get_base(uint32_t index) +{ + set_region_number(index); + + return get_region_base_address() & MPU_RBAR_ADDR_Msk; +} + +/** + * This internal function converts the SIZE field value of MPU_RASR + * to the region size (in bytes). + */ +static inline uint32_t mpu_rasr_size_to_size(uint32_t rasr_size) +{ + return 1 << (rasr_size + 1U); +} + +static inline void set_region_size(uint32_t size) +{ + __asm__ volatile("mcr p15, 0, %0, c6, c1, 2" :: "r" (size) :); +} + +static inline void ARM_MPU_ClrRegion(uint32_t rnr) +{ + set_region_number(rnr); + /* clear size field, which contains enable bit */ + set_region_size(0); +} + +/** + * This internal function checks if region is enabled or not. + * + * Note: + * The caller must provide a valid region number. + */ +static inline int is_enabled_region(uint32_t index) +{ + set_region_number(index); + + return (get_region_size() & MPU_RASR_ENABLE_Msk) ? 1 : 0; +} + +/** + * This internal function returns the access permissions of an MPU region + * specified by its region index. + * + * Note: + * The caller must provide a valid region number. + */ +static inline uint32_t get_region_ap(uint32_t r_index) +{ + set_region_number(r_index); + + return (get_region_attributes() & MPU_RASR_AP_Msk) >> MPU_RASR_AP_Pos; +} + +/** + * This internal function checks if the given buffer is in the region. + * + * Note: + * The caller must provide a valid region number. + */ +static inline int is_in_region(uint32_t r_index, uint32_t start, uint32_t size) +{ + uint32_t r_addr_start; + uint32_t r_size_lshift; + uint32_t r_addr_end; + uint32_t end; + + set_region_number(r_index); + + r_addr_start = get_region_base_address() & MPU_RBAR_ADDR_Msk; + + r_size_lshift = ((get_region_size() & MPU_RASR_SIZE_Msk) >> + MPU_RASR_SIZE_Pos) + 1; + + r_addr_end = r_addr_start + (1UL << r_size_lshift) - 1; + + size = size == 0 ? 0 : size - 1; + if (u32_add_overflow(start, size, &end)) { + return 0; + } + + if ((start >= r_addr_start) && (end <= r_addr_end)) { + return 1; + } + + return 0; +} + +static inline uint32_t mpu_region_get_size(uint32_t index) +{ + set_region_number(index); + + uint32_t rasr_size = + (get_region_size() & MPU_RASR_SIZE_Msk) >> MPU_RASR_SIZE_Pos; + + return mpu_rasr_size_to_size(rasr_size); +} diff --git a/arch/arm/core/aarch32/mpu/cortex_m/arm_mpu_internal.h b/arch/arm/core/aarch32/mpu/cortex_m/arm_mpu_internal.h new file mode 100644 index 000000000000..223bdec5ee19 --- /dev/null +++ b/arch/arm/core/aarch32/mpu/cortex_m/arm_mpu_internal.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2019 Lexmark International, Inc. + */ + +#include + +/** + * Get the number of supported MPU regions. + */ +static inline uint8_t get_num_regions(void) +{ +#if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ + defined(CONFIG_CPU_CORTEX_M3) || \ + defined(CONFIG_CPU_CORTEX_M4) + /* Cortex-M0+, Cortex-M3, and Cortex-M4 MCUs may + * have a fixed number of 8 MPU regions. + */ + return 8; +#elif defined(NUM_MPU_REGIONS) + /* Retrieve the number of regions from DTS configuration. */ + return NUM_MPU_REGIONS; +#else + uint32_t type = MPU->TYPE; + + type = (type & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; + + return (uint8_t)type; +#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */ +} + +static inline void set_region_number(uint32_t index) +{ + MPU->RNR = index; +} + +static inline uint32_t mpu_region_get_base(uint32_t index) +{ + MPU->RNR = index; + return MPU->RBAR & MPU_RBAR_ADDR_Msk; +} + +/** + * This internal function converts the SIZE field value of MPU_RASR + * to the region size (in bytes). + */ +static inline uint32_t mpu_rasr_size_to_size(uint32_t rasr_size) +{ + return 1 << (rasr_size + 1U); +} + +/** + * This internal function checks if region is enabled or not. + * + * Note: + * The caller must provide a valid region number. + */ +static inline int is_enabled_region(uint32_t index) +{ + /* Lock IRQs to ensure RNR value is correct when reading RASR. */ + unsigned int key; + uint32_t rasr; + + key = irq_lock(); + MPU->RNR = index; + rasr = MPU->RASR; + irq_unlock(key); + + return (rasr & MPU_RASR_ENABLE_Msk) ? 1 : 0; +} + +/** + * This internal function returns the access permissions of an MPU region + * specified by its region index. + * + * Note: + * The caller must provide a valid region number. + */ +static inline uint32_t get_region_ap(uint32_t r_index) +{ + /* Lock IRQs to ensure RNR value is correct when reading RASR. */ + unsigned int key; + uint32_t rasr; + + key = irq_lock(); + MPU->RNR = r_index; + rasr = MPU->RASR; + irq_unlock(key); + + return (rasr & MPU_RASR_AP_Msk) >> MPU_RASR_AP_Pos; +} + +/** + * This internal function checks if the given buffer is in the region. + * + * Note: + * The caller must provide a valid region number. + */ +static inline int is_in_region(uint32_t r_index, uint32_t start, uint32_t size) +{ + uint32_t r_addr_start; + uint32_t r_size_lshift; + uint32_t r_addr_end; + uint32_t end; + + /* Lock IRQs to ensure RNR value is correct when reading RBAR, RASR. */ + unsigned int key; + uint32_t rbar, rasr; + + key = irq_lock(); + MPU->RNR = r_index; + rbar = MPU->RBAR; + rasr = MPU->RASR; + irq_unlock(key); + + r_addr_start = rbar & MPU_RBAR_ADDR_Msk; + r_size_lshift = ((rasr & MPU_RASR_SIZE_Msk) >> + MPU_RASR_SIZE_Pos) + 1U; + r_addr_end = r_addr_start + (1UL << r_size_lshift) - 1UL; + + size = size == 0U ? 0U : size - 1U; + if (u32_add_overflow(start, size, &end)) { + return 0; + } + + if ((start >= r_addr_start) && (end <= r_addr_end)) { + return 1; + } + + return 0; +} + +static inline uint32_t mpu_region_get_size(uint32_t index) +{ + MPU->RNR = index; + uint32_t rasr_size = + (MPU->RASR & MPU_RASR_SIZE_Msk) >> MPU_RASR_SIZE_Pos; + + return mpu_rasr_size_to_size(rasr_size); +} diff --git a/arch/arm/core/aarch32/swap_helper.S b/arch/arm/core/aarch32/swap_helper.S index 70b009e3442f..67bf266c6fc3 100644 --- a/arch/arm/core/aarch32/swap_helper.S +++ b/arch/arm/core/aarch32/swap_helper.S @@ -20,13 +20,17 @@ #include #include +#if defined(CONFIG_CPU_CORTEX_M) +#include +#endif _ASM_FILE_PROLOGUE GTEXT(z_arm_svc) GTEXT(z_arm_pendsv) GTEXT(z_do_kernel_oops) +#if defined(CONFIG_USERSPACE) GTEXT(z_arm_do_syscall) -GDATA(_k_neg_eagain) +#endif GDATA(_kernel) @@ -100,7 +104,7 @@ SECTION_FUNC(TEXT, z_arm_pendsv) stmia r0, {v1-v8, ip} #ifdef CONFIG_FPU_SHARING /* Assess whether switched-out thread had been using the FP registers. */ - tst lr, #0x10 /* EXC_RETURN & EXC_RETURN.F_Type_Msk */ + tst lr, #_EXC_RETURN_FTYPE_Msk bne out_fp_endif /* FP context active: set FP state and store callee-saved registers. @@ -130,7 +134,7 @@ out_fp_endif: cpsid i #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) movs.n r0, #_EXC_IRQ_DEFAULT_PRIO - msr BASEPRI, r0 + msr BASEPRI_MAX, r0 isb /* Make the effect of disabling interrupts be realized immediately */ #elif defined(CONFIG_ARMV7_R) /* @@ -207,8 +211,7 @@ out_fp_endif: /* Restore previous interrupt disable state (irq_lock key) * (We clear the arch.basepri field after restoring state) */ -#if (defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M0) || \ - defined(CONFIG_CPU_CORTEX_M1)) && _thread_offset_to_basepri > 124 +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && (_thread_offset_to_basepri > 124) /* Doing it this way since the offset to thread->arch.basepri can in * some configurations be larger than the maximum of 124 for ldr/str * immediate offsets. @@ -287,7 +290,7 @@ _thread_irq_disabled: #ifdef CONFIG_FPU_SHARING /* Assess whether switched-in thread had been using the FP registers. */ - tst lr, #0x10 /* EXC_RETURN & EXC_RETURN.F_Type_Msk */ + tst lr, #_EXC_RETURN_FTYPE_Msk beq in_fp_active /* FP context inactive for swapped-in thread: * - reset FPSCR to 0 @@ -309,7 +312,7 @@ in_fp_active: in_fp_endif: /* Clear CONTROL.FPCA that may have been set by FP instructions */ mrs r3, CONTROL - bic r3, #0x4 /* CONTROL.FPCA Msk */ + bic r3, #_CONTROL_FPCA_Msk msr CONTROL, r3 isb #endif @@ -355,6 +358,15 @@ _thread_irq_disabled: cps #MODE_SYS ldm r0, {r4-r11, sp} cps #MODE_SVC + +#if defined (CONFIG_ARM_MPU) + /* r2 contains k_thread */ + mov r0, r2 + /* Re-program dynamic memory map */ + push {r2, lr} + bl z_arm_configure_dynamic_mpu_regions + pop {r2, lr} +#endif #else #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ @@ -408,7 +420,7 @@ SECTION_FUNC(TEXT, z_arm_svc) * MSP or PSP */ #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) - movs r0, #0x4 + movs r0, #_EXC_RETURN_SPSEL_Msk mov r1, lr tst r1, r0 beq _stack_frame_msp @@ -418,7 +430,7 @@ _stack_frame_msp: mrs r0, MSP _stack_frame_endif: #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - tst lr, #0x4 /* did we come from thread mode ? */ + tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */ ite eq /* if zero (equal), came from handler mode */ mrseq r0, MSP /* handler mode, stack frame is on MSP */ mrsne r0, PSP /* thread mode, stack frame is on PSP */ @@ -605,6 +617,29 @@ valid_syscall_id: * @return N/A */ SECTION_FUNC(TEXT, z_arm_svc) +#if defined(CONFIG_USERSPACE) + /* Determine if incoming thread was in user context */ + push {r0} + mrs r0, spsr + and r0, #MODE_MASK + cmp r0, #MODE_USR + bne svc_system_thread + + ldr r0, =_kernel + ldr r0, [r0, #_kernel_offset_to_current] + + /* Save away user stack pointer */ + cps #MODE_SYS + str sp, [r0, #_thread_offset_to_sp_usr] /* sp_usr */ + + /* Switch to privileged stack */ + ldr sp, [r0, #_thread_offset_to_priv_stack_end] /* priv stack end */ + cps #MODE_SVC + +svc_system_thread: + pop {r0} +#endif + /* * Switch to system mode to store r0-r3 to the process stack pointer. * Save r12 and the lr as we could be swapping in another process and @@ -641,17 +676,22 @@ SECTION_FUNC(TEXT, z_arm_svc) beq demux ldr r1, [lr, #-2] - bic r1, #0xff00 + and r1, #0xff /* * grab service call number: * 0: context switch * 1: irq_offload (if configured) * 2: kernel panic or oops (software generated fatal exception) - * Planned implementation of system calls for memory protection will - * expand this case. + * 3: system calls for memory protection */ demux: + +#if defined(CONFIG_USERSPACE) + cmp r1, #_SVC_CALL_SYSTEM_CALL + beq _do_syscall +#endif + cmp r1, #_SVC_CALL_CONTEXT_SWITCH beq _context_switch @@ -672,11 +712,123 @@ _context_switch: b z_arm_int_exit _oops: - push {r0, lr} - blx z_do_kernel_oops - pop {r0, lr} - cpsie i - movs pc, lr + /* + * Pass the exception frame to z_do_kernel_oops. r0 contains the + * exception reason. + */ + cps #MODE_SYS + mov r0, sp + cps #MODE_SVC + bl z_do_kernel_oops + b z_arm_int_exit + +#if defined(CONFIG_USERSPACE) + /* + * System call will setup a jump to the _do_arm_syscall function + * when the SVC returns via the bx lr. + * + * There is some trickery involved here because we have to preserve + * the original PC value so that we can return back to the caller of + * the SVC. + * + * On SVC exception, the USER/SYSTEM stack looks like the following: + * + * sp+0: r0 + * sp+4: r1 + * sp+8: r2 + * sp+12: r3 + * sp+16: r12 + * sp+20: LR_svc (address of opcode just following SVC opcode ) + * + * Registers look like: + * r0 - arg1 + * r1 - arg2 + * r2 - arg3 + * r3 - arg4 + * r4 - arg5 + * r5 - arg6 + * r6 - call_id + * r8 - saved link register + */ +_do_syscall: + /* validate syscall limit, only set priv mode if valid */ + ldr ip, =K_SYSCALL_LIMIT + cmp r6, ip + blo valid_syscall_id + + /* bad syscall id. Set arg0 to bad id and set call_id to SYSCALL_BAD */ + cps #MODE_SYS + str r6, [sp] + cps #MODE_SVC + ldr r6, =K_SYSCALL_BAD + +valid_syscall_id: + push {r0, r1} + ldr r0, =_kernel + ldr r0, [r0, #_kernel_offset_to_current] + ldr r1, [r0, #_thread_offset_to_mode] + bic r1, #1 + /* Store (privileged) mode in thread's mode state variable */ + str r1, [r0, #_thread_offset_to_mode] + dsb + + /* ISB is not strictly necessary here (stack pointer is not being + * touched), but it's recommended to avoid executing pre-fetched + * instructions with the previous privilege. + */ + isb + + /* + * restore r0-r3 from supervisor stack before changing to system mode. + * r0,r1 saved just after valid_syscall_id + * r2,r3 saved just after z_arm_svc + */ + pop {r0-r3} + + add sp,sp,r3 /* un-do stack pointer alignment to double-word boundary */ + + /* Switch to system mode */ + cps #MODE_SYS + + /* + * Restore the nested level. The thread that is doing the system call may + * be put to sleep, as in the case of waiting in k_msgq_get() with + * K_FOREVER, so we don't want the nesting level to be elevated during + * that complete time. + */ + ldr r2, =_kernel + ldr r1, [r2, #_kernel_offset_to_nested] + sub r1, r1, #1 + str r1, [r2, #_kernel_offset_to_nested] + + /* + * restore r0-r3 from stack since we've used them above during demux + */ + ldr r0, [sp, #0] + ldr r1, [sp, #4] + ldr r2, [sp, #8] + ldr r3, [sp, #12] + + /* + * grab return address from USER/SYSTEM stack frame + * (just past the SVC opcode) + */ + ldr r8, [sp, #20] + + /* + * User stack left with: + * + * sp: r0 + * sp+4: r1 + * sp+8: r2 + * sp+12: r3 + * sp+16: r12 + * sp+20: LR_svc (address of opcode just following SVC opcode ) + */ + + /* branch to _arm_do_syscall. We will not return here. */ + b z_arm_do_syscall +#endif GTEXT(z_arm_cortex_r_svc) SECTION_FUNC(TEXT, z_arm_cortex_r_svc) diff --git a/arch/arm/core/aarch32/thread.c b/arch/arm/core/aarch32/thread.c index f6d8bc04d876..8c48389a4b28 100644 --- a/arch/arm/core/aarch32/thread.c +++ b/arch/arm/core/aarch32/thread.c @@ -267,6 +267,11 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ #endif /* CONFIG_MPU_STACK_GUARD */ +#if defined(CONFIG_CPU_CORTEX_R) + _current->arch.priv_stack_end = + _current->arch.priv_stack_start + CONFIG_PRIVILEGED_STACK_SIZE; +#endif + z_arm_userspace_enter(user_entry, p1, p2, p3, (uint32_t)_current->stack_info.start, _current->stack_info.size - @@ -396,7 +401,7 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp #if defined(CONFIG_USERSPACE) if (thread->arch.priv_stack_start) { /* User thread */ - if ((__get_CONTROL() & CONTROL_nPRIV_Msk) == 0U) { + if (z_arm_thread_is_in_user_mode() == false) { /* User thread in privilege mode */ if (IS_MPU_GUARD_VIOLATION( thread->arch.priv_stack_start - guard_len, @@ -509,6 +514,19 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, z_arm_prepare_switch_to_main(); _current = main_thread; + +#if defined(CONFIG_THREAD_LOCAL_STORAGE) && defined(CONFIG_CPU_CORTEX_M) + /* On Cortex-M, TLS uses a global variable as pointer to + * the thread local storage area. So this needs to point + * to the main thread's TLS area before switching to any + * thread for the first time, as the pointer is only set + * during context switching. + */ + extern uintptr_t z_arm_tls_ptr; + + z_arm_tls_ptr = main_thread->tls; +#endif + #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING z_thread_mark_switched_in(); #endif diff --git a/arch/arm/core/aarch32/userspace.S b/arch/arm/core/aarch32/userspace.S index 10c7ec3f1236..c098f9c7e2f0 100644 --- a/arch/arm/core/aarch32/userspace.S +++ b/arch/arm/core/aarch32/userspace.S @@ -14,6 +14,10 @@ #include +#if defined(CONFIG_CPU_CORTEX_R) +#include +#endif + _ASM_FILE_PROLOGUE GTEXT(z_arm_userspace_enter) @@ -59,6 +63,14 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) ldr r0, [r0, #_thread_offset_to_priv_stack_start] /* priv stack ptr */ ldr ip, =CONFIG_PRIVILEGED_STACK_SIZE add r0, r0, ip +#elif defined(CONFIG_CPU_CORTEX_R) + ldr r0, [r0, #_thread_offset_to_priv_stack_start] /* priv stack ptr */ + ldr ip, =CONFIG_PRIVILEGED_STACK_SIZE + add r0, r0, ip + + ldr ip, =_kernel + ldr ip, [ip, #_kernel_offset_to_current] + str r0, [ip, #_thread_offset_to_priv_stack_end] /* priv stack end */ #endif /* store current stack pointer to ip @@ -67,6 +79,9 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) */ mov ip, sp +#if defined(CONFIG_CPU_CORTEX_R) + mov sp, r0 +#else /* set stack to privileged stack * * Note [applies only when CONFIG_BUILTIN_STACK_GUARD is enabled]: @@ -76,6 +91,7 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) * located in memory higher than the default (user) thread stack. */ msr PSP, r0 +#endif #if defined(CONFIG_BUILTIN_STACK_GUARD) /* At this point the privileged stack is not yet protected by PSPLIM. @@ -96,7 +112,8 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) mov r1, ip push {r0,r1} -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) \ + || defined(CONFIG_CPU_CORTEX_R) push {r0,ip} #endif @@ -127,7 +144,8 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) mov ip, r3 push {r0,r3} -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) \ + || defined(CONFIG_CPU_CORTEX_R) pop {r0,ip} /* load up stack info from user stack */ @@ -143,14 +161,15 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) #ifdef CONFIG_INIT_STACKS ldr r1,=0xaaaaaaaa #else - eors.n r1, r1 + eors r1, r1 #endif bl memset #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) pop {r0, r1} mov ip, r1 -#elif (defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)) +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) \ + || defined(CONFIG_CPU_CORTEX_R) pop {r0,ip} #endif @@ -164,10 +183,18 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) pop {r1,r2,r3,r4} mov lr, r4 mov r4, ip -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) \ + || defined(CONFIG_CPU_CORTEX_R) pop {r1,r2,r3,lr} #endif +#if defined(CONFIG_CPU_CORTEX_R) + /* + * set stack to user stack. We are in SYSTEM state, so r13 and r14 are + * shared with USER state + */ + mov sp, r0 +#else #if defined(CONFIG_BUILTIN_STACK_GUARD) /* * Guard the default (user) stack until thread drops privileges. @@ -192,7 +219,7 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) /* Lock PendSV while reprogramming PSP and PSPLIM */ mov r0, #_EXC_PENDSV_PRIO_MASK - msr BASEPRI, r0 + msr BASEPRI_MAX, r0 isb /* Set PSPLIM to guard the thread's user stack. */ @@ -206,6 +233,7 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) /* set stack to user stack */ msr PSP, r0 +#endif #if defined(CONFIG_BUILTIN_STACK_GUARD) /* Restore interrupt lock status */ @@ -216,6 +244,10 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) /* restore r0 */ mov r0, lr +#if defined(CONFIG_CPU_CORTEX_R) + /* change processor mode to unprivileged, with all interrrupts enabled. */ + msr CPSR_c, #MODE_USR +#else /* change processor mode to unprivileged */ #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) push {r0, r1, r2, r3} @@ -244,6 +276,7 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) #endif dsb msr CONTROL, ip +#endif /* ISB is not strictly necessary here (stack pointer is not being * touched), but it's recommended to avoid executing pre-fetched @@ -262,7 +295,8 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter) ldr r0, =z_thread_entry mov ip, r0 pop {r0, r1} -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) \ + || defined(CONFIG_CPU_CORTEX_R) ldr ip, =z_thread_entry #endif bx ip @@ -317,8 +351,7 @@ SECTION_FUNC(TEXT, z_arm_do_syscall) /* Restore user stack and original r0, r1 */ pop {r0, r1} -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) - +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) \ /* setup privileged stack */ ldr ip, =_kernel ldr ip, [ip, #_kernel_offset_to_current] @@ -329,10 +362,18 @@ SECTION_FUNC(TEXT, z_arm_do_syscall) subs ip, #8 str sp, [ip, #0] str lr, [ip, #4] +#elif defined(CONFIG_CPU_CORTEX_R) + /* Store current LR at the beginning of the priv stack */ + push {lr} #endif - /* switch to privileged stack */ +#if !defined(CONFIG_CPU_CORTEX_R) + /* + * switch to privileged stack + * The stack switch happens on exception entry for Cortex-R + */ msr PSP, ip +#endif /* Note (applies when using stack limit checking): * We do not need to lock IRQs after switching PSP to the privileged stack; @@ -404,7 +445,8 @@ dispatch_syscall: /* Restore r0 */ mov r0, ip -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) \ + || defined(CONFIG_CPU_CORTEX_R) ldr ip, =K_SYSCALL_BAD cmp r6, ip bne valid_syscall @@ -412,7 +454,11 @@ dispatch_syscall: /* BAD SYSCALL path */ /* fixup stack frame on the privileged stack, adding ssf */ mov ip, sp +#if defined(CONFIG_CPU_CORTEX_R) + push {r4,r5,ip} +#else push {r4,r5,ip,lr} +#endif b dispatch_syscall valid_syscall: @@ -425,13 +471,37 @@ dispatch_syscall: lsl r6, #2 add ip, r6 ldr ip, [ip] /* load table address */ + +#if defined(CONFIG_CPU_CORTEX_R) + /* + * We can only be in this system call handling code if interrupts were + * enabled. This is because we would only come down this path if we were + * actively running in user state, and user state CANNOT disable external + * interrupts via irq_lock(). We want external interrupts enabled while + * running the system call handler, so we can blindly enable them now, and + * disable them afterwards. + */ + cpsie i +#endif + /* execute function from dispatch table */ blx ip +#if defined(CONFIG_CPU_CORTEX_R) + /* + * for same reasoning as above: we now disable external interrupts. + */ + cpsid i + + /* restore LR */ + ldr lr, [sp,#12] +#else /* restore LR */ ldr lr, [sp,#16] #endif +#endif + #if defined(CONFIG_BUILTIN_STACK_GUARD) /* @@ -456,7 +526,7 @@ dispatch_syscall: /* Lock PendSV while reprogramming PSP and PSPLIM */ mov r3, #_EXC_PENDSV_PRIO_MASK - msr BASEPRI, r3 + msr BASEPRI_MAX, r3 isb /* Set PSPLIM to guard the thread's user stack. */ @@ -475,7 +545,7 @@ dispatch_syscall: /* Restore r0 */ mov r0, ip -#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) \ /* set stack back to unprivileged stack */ ldr ip, [sp,#12] msr PSP, ip @@ -568,7 +638,54 @@ dispatch_syscall: orrs ip, ip, #1 #endif + +#if defined(CONFIG_CPU_CORTEX_R) + /* + * The stack contains (from top) + * spsr lr lr_svc r12 r3 r2 r1 r0 lr sp r5 r4 + * Unwind everything except the return state that will be used for rfeia. + */ + add sp, sp, #(8*4) + ldmia sp!, {r12,lr} + pop {r2, r3} + + cps #MODE_SVC + + /* + * Restore lr_svc stored into the SVC mode stack by the mode entry + * function. This ensures that the return address of the interrupted + * context is preserved in case of interrupt nesting. + */ + pop {lr} + + /* + * Move the return state from the privileged stack to the service + * stack. We need to put the user stack back in $sp, but we cannot + * trust the user stack. Therefore, put the return state on the svc + * stack and return from there. + */ + push {r2, r3} + + /* Restore user stack pointer */ + ldr r1, =_kernel + ldr r1, [r1, #_kernel_offset_to_current] + cps #MODE_SYS + ldr sp, [r1, #_thread_offset_to_sp_usr] /* sp_usr */ + cps #MODE_SVC + + /* Zero out volatile (caller-saved) registers so as to not leak state from + * kernel mode. The C calling convention for the syscall handler will + * restore the others to original values. + */ + mov r1, #0 + mov r2, #0 + mov r3, #0 + + /* return from SVC state to user state. */ + rfeia sp! +#else bx ip +#endif /* @@ -578,7 +695,8 @@ SECTION_FUNC(TEXT, arch_user_string_nlen) push {r0, r1, r2, r4, r5, lr} /* sp+4 is error value, init to -1 */ -#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ + || defined(CONFIG_ARMV7_R) ldr r3, =-1 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) mov.w r3, #-1 @@ -594,6 +712,16 @@ z_arm_user_string_nlen_fault_start: ldrb r5, [r0, r3] z_arm_user_string_nlen_fault_end: +#if defined(CONFIG_CPU_CORTEX_R) + cmp r5, #0 + beq strlen_done + + cmp r3, r1 + beq strlen_done + + adds r3, #1 + b strlen_loop +#else #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) cmp r5, #0 beq strlen_done @@ -605,6 +733,7 @@ z_arm_user_string_nlen_fault_end: adds r3, #1 b.n strlen_loop +#endif strlen_done: /* Move length calculation from r3 to r0 (return value register) */ diff --git a/arch/arm/core/aarch32/vector_table.ld b/arch/arm/core/aarch32/vector_table.ld index e379c4926019..2a4654f858a0 100644 --- a/arch/arm/core/aarch32/vector_table.ld +++ b/arch/arm/core/aarch32/vector_table.ld @@ -12,10 +12,19 @@ * described below. */ +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) +/* VTOR bits 0:7 are reserved (RES0). This requires that the base address + * of the vector table is 64-word aligned. + */ +. = ALIGN( 1 << LOG2CEIL(4 * 64) ); +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) /* VTOR bits 0:6 are reserved (RES0). This requires that the base address * of the vector table is 32-word aligned. */ . = ALIGN( 1 << LOG2CEIL(4 * 32) ); +#else +#error "Unsupported architecture variant" +#endif /* When setting TBLOFF in VTOR we must align the offset to the number of * exception entries in the vector table. The minimum alignment of 32 words diff --git a/arch/arm/core/offsets/offsets_aarch32.c b/arch/arm/core/offsets/offsets_aarch32.c index ff5d61fbcc80..d003f24766f7 100644 --- a/arch/arm/core/offsets/offsets_aarch32.c +++ b/arch/arm/core/offsets/offsets_aarch32.c @@ -40,6 +40,10 @@ GEN_OFFSET_SYM(_thread_arch_t, mode_exc_return); #endif #if defined(CONFIG_USERSPACE) GEN_OFFSET_SYM(_thread_arch_t, priv_stack_start); +#if defined(CONFIG_CPU_CORTEX_R) +GEN_OFFSET_SYM(_thread_arch_t, priv_stack_end); +GEN_OFFSET_SYM(_thread_arch_t, sp_usr); +#endif #endif #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) diff --git a/arch/arm/include/aarch32/cortex_a_r/exc.h b/arch/arm/include/aarch32/cortex_a_r/exc.h index 1bc6fc9f463c..a59fca50479a 100644 --- a/arch/arm/include/aarch32/cortex_a_r/exc.h +++ b/arch/arm/include/aarch32/cortex_a_r/exc.h @@ -38,6 +38,22 @@ static ALWAYS_INLINE bool arch_is_in_isr(void) return (_kernel.cpus[0].nested != 0U); } +static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf) +{ + return (_kernel.cpus[0].nested > 1U) ? (true) : (false); +} + +#if defined(CONFIG_USERSPACE) +/* + * This function is used by privileged code to determine if the thread + * associated with the stack frame is in user mode. + */ +static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const z_arch_esf_t *esf) +{ + return ((esf->basic.xpsr & CPSR_M_Msk) == CPSR_M_USR); +} +#endif + /** * @brief Setup system exceptions * diff --git a/arch/arm/include/aarch32/cortex_m/dwt.h b/arch/arm/include/aarch32/cortex_m/dwt.h index f54fab4a57d2..5d3381e30eed 100644 --- a/arch/arm/include/aarch32/cortex_m/dwt.h +++ b/arch/arm/include/aarch32/cortex_m/dwt.h @@ -163,8 +163,10 @@ static inline void z_arm_dwt_enable_debug_monitor(void) "DebugMonitor targets Non-Secure\n"); #endif - /* Set the DebugMonitor handler priority to the higyhest value. */ - NVIC_SetPriority(DebugMonitor_IRQn, _EXC_FAULT_PRIO); + /* The DebugMonitor handler priority is set already + * to the highest value (_EXC_FAULT_PRIO) during + * system initialization. + */ /* Enable debug monitor exception triggered on debug events */ CoreDebug->DEMCR |= CoreDebug_DEMCR_MON_EN_Msk; diff --git a/arch/arm/include/aarch32/cortex_m/exc.h b/arch/arm/include/aarch32/cortex_m/exc.h index 1f8635be2d32..6e0681c2504d 100644 --- a/arch/arm/include/aarch32/cortex_m/exc.h +++ b/arch/arm/include/aarch32/cortex_m/exc.h @@ -73,6 +73,19 @@ static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf) return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false); } +#if defined(CONFIG_USERSPACE) +/** + * @brief Is the thread in unprivileged mode + * + * @param esf the exception stack frame (unused) + * @return true if the current thread was in unprivileged mode + */ +static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const z_arch_esf_t *esf) +{ + return z_arm_thread_is_in_user_mode(); +} +#endif + /** * @brief Setup system exceptions * @@ -85,6 +98,9 @@ static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf) */ static ALWAYS_INLINE void z_arm_exc_setup(void) { + /* PendSV is set to lowest priority, regardless of it being used. + * This is done as the IRQ is always enabled. + */ NVIC_SetPriority(PendSV_IRQn, _EXC_PENDSV_PRIO); #ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI @@ -98,6 +114,9 @@ static ALWAYS_INLINE void z_arm_exc_setup(void) NVIC_SetPriority(MemoryManagement_IRQn, _EXC_FAULT_PRIO); NVIC_SetPriority(BusFault_IRQn, _EXC_FAULT_PRIO); NVIC_SetPriority(UsageFault_IRQn, _EXC_FAULT_PRIO); +#if defined(CONFIG_CPU_CORTEX_M_HAS_DWT) + NVIC_SetPriority(DebugMonitor_IRQn, _EXC_FAULT_PRIO); +#endif #if defined(CONFIG_ARM_SECURE_FIRMWARE) NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO); #endif /* CONFIG_ARM_SECURE_FIRMWARE */ @@ -129,6 +148,19 @@ static ALWAYS_INLINE void z_arm_exc_setup(void) * SecureHardFault in a PE without the Main Extension. */ #endif /* ARM_SECURE_FIRMWARE && !ARM_SECURE_BUSFAULT_HARDFAULT_NMI */ + +#if defined(CONFIG_CPU_CORTEX_M_HAS_SYSTICK) && \ + !defined(CONFIG_CORTEX_M_SYSTICK) + /* SoC implements SysTick, but the system does not use it + * as driver for system timing. However, the SysTick IRQ is + * always enabled, so we must ensure the interrupt priority + * is set to a level lower than the kernel interrupts (for + * the assert mechanism to work properly) in case the SysTick + * interrupt is accidentally raised. + */ + NVIC_SetPriority(SysTick_IRQn, _EXC_IRQ_DEFAULT_PRIO); +#endif /* CPU_CORTEX_M_HAS_SYSTICK && ! CORTEX_M_SYSTICK */ + } /** diff --git a/arch/arm/include/aarch32/offsets_short_arch.h b/arch/arm/include/aarch32/offsets_short_arch.h index f5b3b619fbed..494852d2a721 100644 --- a/arch/arm/include/aarch32/offsets_short_arch.h +++ b/arch/arm/include/aarch32/offsets_short_arch.h @@ -39,6 +39,14 @@ #ifdef CONFIG_USERSPACE #define _thread_offset_to_priv_stack_start \ (___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_start_OFFSET) + +#if defined(CONFIG_CPU_CORTEX_R) +#define _thread_offset_to_priv_stack_end \ + (___thread_t_arch_OFFSET + ___thread_arch_t_priv_stack_end_OFFSET) + +#define _thread_offset_to_sp_usr \ + (___thread_t_arch_OFFSET + ___thread_arch_t_sp_usr_OFFSET) +#endif #endif #if defined(CONFIG_THREAD_STACK_INFO) diff --git a/arch/arm64/core/mmu.S b/arch/arm64/core/mmu.S index 583f61447d59..e8b70f7f8900 100644 --- a/arch/arm64/core/mmu.S +++ b/arch/arm64/core/mmu.S @@ -24,15 +24,15 @@ SECTION_FUNC(TEXT, z_arm64_set_ttbr0) msr sctlr_el1, x1 isb + /* Switch the TTBR0 */ + msr ttbr0_el1, x0 + isb + /* Invalidate the TLBs */ tlbi vmalle1 dsb sy isb - /* Switch the TTBR0 */ - msr ttbr0_el1, x0 - isb - /* Restore the saved SCTLR_EL1 */ msr sctlr_el1, x2 isb diff --git a/arch/arm64/core/mmu.c b/arch/arm64/core/mmu.c index 67ab97aa4881..d466c7bf4399 100644 --- a/arch/arm64/core/mmu.c +++ b/arch/arm64/core/mmu.c @@ -645,14 +645,14 @@ static const struct arm_mmu_flat_range mmu_zephyr_ranges[] = { /* Mark text segment cacheable,read only and executable */ { .name = "zephyr_code", - .start = _image_text_start, - .end = _image_text_end, + .start = __text_region_start, + .end = __text_region_end, .attrs = MT_NORMAL | MT_P_RX_U_RX | MT_DEFAULT_SECURE_STATE }, /* Mark rodata segment cacheable, read only and execute-never */ { .name = "zephyr_rodata", - .start = _image_rodata_start, - .end = _image_rodata_end, + .start = __rodata_region_start, + .end = __rodata_region_end, .attrs = MT_NORMAL | MT_P_RO_U_RO | MT_DEFAULT_SECURE_STATE }, }; diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index 0acc9c7bcfa3..1f97e585453e 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -237,6 +237,6 @@ static int arm64_smp_init(const struct device *dev) return 0; } -SYS_INIT(arm64_smp_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +SYS_INIT(arm64_smp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif diff --git a/arch/common/CMakeLists.txt b/arch/common/CMakeLists.txt index 3f6e5984c26b..ca0062a317f6 100644 --- a/arch/common/CMakeLists.txt +++ b/arch/common/CMakeLists.txt @@ -24,6 +24,15 @@ zephyr_linker_sources_ifdef(CONFIG_GEN_ISR_TABLES ${ZEPHYR_BASE}/include/linker/intlist.ld ) +if(CONFIG_GEN_ISR_TABLES) + zephyr_linker_section(NAME .intList VMA IDT_LIST LMA IDT_LIST NOINPUT PASS 1) + zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".irq_info" FIRST) + zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".intList") + + zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".irq_info" PASS 2) + zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".intList" PASS 2) +endif() + zephyr_linker_sources_ifdef(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT RAM_SECTIONS ramfunc.ld @@ -38,6 +47,7 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64 OR DEFINED CONFIG_SOC_OPENISA_RV32M1_RISCV32) zephyr_linker_sources(ROM_START SORT_KEY 0x0 rom_start_offset.ld) + # Handled in ld.cmake endif() diff --git a/arch/common/ramfunc.ld b/arch/common/ramfunc.ld index b22579ec8ced..1fe92f55d59c 100644 --- a/arch/common/ramfunc.ld +++ b/arch/common/ramfunc.ld @@ -9,12 +9,12 @@ SECTION_DATA_PROLOGUE(.ramfunc,,) { - MPU_ALIGN(_ramfunc_ram_size); - _ramfunc_ram_start = .; + MPU_ALIGN(__ramfunc_size); + __ramfunc_start = .; *(.ramfunc) *(".ramfunc.*") - MPU_ALIGN(_ramfunc_ram_size); - _ramfunc_ram_end = .; + MPU_ALIGN(__ramfunc_size); + __ramfunc_end = .; } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) -_ramfunc_ram_size = _ramfunc_ram_end - _ramfunc_ram_start; -_ramfunc_rom_start = LOADADDR(.ramfunc); +__ramfunc_size = __ramfunc_end - __ramfunc_start; +__ramfunc_load_start = LOADADDR(.ramfunc); diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ec5a7e4526a0..524ce570415f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -20,6 +20,18 @@ config FLOAT_HARD help This option enables the hard-float calling convention. +config RISCV_GP + bool "Enable RISC-V global pointer relative addressing" + default n + help + Use global pointer relative addressing for small globals declared + anywhere in the executable. It can benefit performance and reduce + the code size. + + Note: To support this feature, RISC-V SoC needs to initialize + global pointer at program start or earlier than any instruction + using GP relative addressing. + menu "RISCV Processor Options" config CORE_E31 @@ -90,12 +102,6 @@ config RISCV_SOC_INTERRUPT_INIT Enable SOC-based interrupt initialization (call soc_interrupt_init, within _IntLibInit when enabled) -config RISCV_SOC_INIT_GP_VALUE - bool "Enable SOC-based global pointer register initialization" - help - Enable SOC-based pointer register initialization - (call __soc_get_gp_initial_value when initializing a thread) - config RISCV_GENERIC_TOOLCHAIN bool "Compile using generic riscv32 toolchain" default y @@ -142,7 +148,7 @@ config MAIN_STACK_SIZE default 4096 if 64BIT config TEST_EXTRA_STACKSIZE - default 1024 if 64BIT + default 1024 config CMSIS_THREAD_MAX_STACK_SIZE default 1024 if 64BIT diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c index 60c621feeb66..a6791d4b8339 100644 --- a/arch/riscv/core/fatal.c +++ b/arch/riscv/core/fatal.c @@ -40,7 +40,7 @@ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason, LOG_ERR(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6); LOG_ERR(" a7: " PR_REG, esf->a7); LOG_ERR(" " NO_REG " tp: " PR_REG, esf->tp); - LOG_ERR(" ra: " PR_REG " gp: " PR_REG, esf->ra, esf->gp); + LOG_ERR(" ra: " PR_REG, esf->ra); LOG_ERR(" mepc: " PR_REG, esf->mepc); LOG_ERR("mstatus: " PR_REG, esf->mstatus); LOG_ERR(""); diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S index eeabab751a1c..edf4b008b41f 100644 --- a/arch/riscv/core/isr.S +++ b/arch/riscv/core/isr.S @@ -122,8 +122,6 @@ RV_OP_STOREREG temp, __z_arch_esf_t_mstatus_OFFSET(to_reg) ;\ RV_OP_LOADREG temp, __z_arch_esf_t_ra_OFFSET(from_reg) ;\ RV_OP_STOREREG temp, __z_arch_esf_t_ra_OFFSET(to_reg) ;\ - RV_OP_LOADREG temp, __z_arch_esf_t_gp_OFFSET(from_reg) ;\ - RV_OP_STOREREG temp, __z_arch_esf_t_gp_OFFSET(to_reg) ;\ RV_OP_LOADREG temp, __z_arch_esf_t_tp_OFFSET(from_reg) ;\ RV_OP_STOREREG temp, __z_arch_esf_t_tp_OFFSET(to_reg) ;\ RV_OP_LOADREG temp, __z_arch_esf_t_t0_OFFSET(from_reg) ;\ @@ -174,12 +172,11 @@ #define STORE_CALLEE_SAVED(reg) \ DO_CALLEE_SAVED(RV_OP_STOREREG, reg) -#define LOAD_CALLER_SAVED(reg) \ +#define LOAD_CALLEE_SAVED(reg) \ DO_CALLEE_SAVED(RV_OP_LOADREG, reg) #define DO_CALLER_SAVED(op) \ op ra, __z_arch_esf_t_ra_OFFSET(sp) ;\ - op gp, __z_arch_esf_t_gp_OFFSET(sp) ;\ op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\ op t0, __z_arch_esf_t_t0_OFFSET(sp) ;\ op t1, __z_arch_esf_t_t1_OFFSET(sp) ;\ @@ -201,7 +198,7 @@ addi sp, sp, -__z_arch_esf_t_SIZEOF ;\ DO_CALLER_SAVED(RV_OP_STOREREG) ; -#define LOAD_CALLEE_SAVED() \ +#define LOAD_CALLER_SAVED() \ DO_CALLER_SAVED(RV_OP_LOADREG) ;\ addi sp, sp, __z_arch_esf_t_SIZEOF ; @@ -814,6 +811,18 @@ skip_fp_move_irq: #endif /* CONFIG_USERSPACE */ reschedule: + /* + * Check if the current thread is the same as the thread on the ready Q. If + * so, do not reschedule. + * Note: + * Sometimes this code is execute back-to-back before the target thread + * has a chance to run. If this happens, the current thread and the + * target thread will be the same. + */ + la t0, _kernel + RV_OP_LOADREG t2, _kernel_offset_to_current(t0) + RV_OP_LOADREG t3, _kernel_offset_to_ready_q_cache(t0) + beq t2, t3, no_reschedule #if CONFIG_INSTRUMENT_THREAD_SWITCHING call z_thread_mark_switched_out @@ -883,7 +892,7 @@ skip_callee_saved_reg: RV_OP_LOADREG sp, _thread_offset_to_sp(t1) /* Restore callee-saved registers of new thread */ - LOAD_CALLER_SAVED(t1) + LOAD_CALLEE_SAVED(t1) #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) /* Determine if we need to restore floating-point registers. */ @@ -967,7 +976,7 @@ skip_load_fp_caller_saved_resched: #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ /* Restore caller-saved registers from thread stack */ - LOAD_CALLEE_SAVED() + LOAD_CALLER_SAVED() /* Call SOC_ERET to exit ISR */ SOC_ERET @@ -1032,7 +1041,7 @@ skip_load_fp_caller_saved: #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ /* Restore caller-saved registers from thread stack */ - LOAD_CALLEE_SAVED() + LOAD_CALLER_SAVED() #ifdef CONFIG_PMP_STACK_GUARD csrrw sp, mscratch, sp diff --git a/arch/riscv/core/offsets/offsets.c b/arch/riscv/core/offsets/offsets.c index 8702d00f1f42..3138bae45e64 100644 --- a/arch/riscv/core/offsets/offsets.c +++ b/arch/riscv/core/offsets/offsets.c @@ -65,7 +65,6 @@ GEN_OFFSET_SYM(_callee_saved_t, fs11); /* esf member offsets */ GEN_OFFSET_SYM(z_arch_esf_t, ra); -GEN_OFFSET_SYM(z_arch_esf_t, gp); GEN_OFFSET_SYM(z_arch_esf_t, tp); GEN_OFFSET_SYM(z_arch_esf_t, t0); GEN_OFFSET_SYM(z_arch_esf_t, t1); diff --git a/arch/riscv/core/pmp/core_pmp.c b/arch/riscv/core/pmp/core_pmp.c index 0ace4a770ede..bc8196b7133a 100644 --- a/arch/riscv/core/pmp/core_pmp.c +++ b/arch/riscv/core/pmp/core_pmp.c @@ -229,11 +229,11 @@ void z_riscv_init_user_accesses(struct k_thread *thread) { unsigned char index; unsigned char *uchar_pmpcfg; - ulong_t rom_start = (ulong_t) _image_rom_start; + ulong_t rom_start = (ulong_t) __rom_region_start; #if defined(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT) - ulong_t rom_size = (ulong_t) _image_rom_size; + ulong_t rom_size = (ulong_t) __rom_region_size; #else /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT */ - ulong_t rom_end = (ulong_t) _image_rom_end; + ulong_t rom_end = (ulong_t) __rom_region_end; #endif /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT */ index = 0U; uchar_pmpcfg = (unsigned char *) thread->arch.u_pmpcfg; diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index cc066f27f909..9ad30a4b223e 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -47,10 +47,6 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, stack_init->a2 = (ulong_t)p2; stack_init->a3 = (ulong_t)p3; -#ifdef CONFIG_RISCV_SOC_INIT_GP_VALUE - stack_init->gp = __soc_get_gp_initial_value(); -#endif - #ifdef CONFIG_THREAD_LOCAL_STORAGE stack_init->tp = (ulong_t)thread->tls; #endif diff --git a/arch/x86/core/ia32.cmake b/arch/x86/core/ia32.cmake index f9a2a7018e3e..48207011b500 100644 --- a/arch/x86/core/ia32.cmake +++ b/arch/x86/core/ia32.cmake @@ -1,7 +1,8 @@ # Copyright (c) 2019 Intel Corp. # SPDX-License-Identifier: Apache-2.0 -if (CMAKE_C_COMPILER_ID STREQUAL "Clang") +if (CMAKE_C_COMPILER_ID STREQUAL "Clang" + OR CMAKE_C_COMPILER_ID STREQUAL "IntelLLVM") # We rely on GAS for assembling, so don't use the integrated assembler zephyr_compile_options($<$:-no-integrated-as>) elseif(CMAKE_C_COMPILER_ID STREQUAL "GNU") diff --git a/arch/x86/core/ia32/crt0.S b/arch/x86/core/ia32/crt0.S index 6a6776e7f216..8f49df8d6050 100644 --- a/arch/x86/core/ia32/crt0.S +++ b/arch/x86/core/ia32/crt0.S @@ -257,7 +257,14 @@ __csSet: #ifdef CONFIG_LINKER_USE_PINNED_SECTION call z_bss_zero_pinned #endif +#ifdef CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT + /* Don't clear BSS if the section is not present + * in memory at boot. Or else it would cause page + * faults. Zeroing BSS will be done later once the + * the paging mechanism has been initialized. + */ call z_bss_zero +#endif /* load 32-bit operand size IDT */ lidt z_x86_idt diff --git a/arch/x86/core/intel64/thread.c b/arch/x86/core/intel64/thread.c index a941022f9fa2..e998b06ac8e2 100644 --- a/arch/x86/core/intel64/thread.c +++ b/arch/x86/core/intel64/thread.c @@ -61,3 +61,15 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, thread->arch.flags = X86_THREAD_FLAG_ALL; thread->switch_handle = thread; } + +int arch_float_disable(struct k_thread *thread) +{ + /* x86-64 always has FP/SSE enabled so cannot be disabled */ + return -ENOTSUP; +} + +int arch_float_enable(struct k_thread *thread, unsigned int options) +{ + /* x86-64 always has FP/SSE enabled so nothing to do here */ + return 0; +} diff --git a/arch/x86/core/memmap.c b/arch/x86/core/memmap.c index b47996c46e4f..4e3882ea16eb 100644 --- a/arch/x86/core/memmap.c +++ b/arch/x86/core/memmap.c @@ -14,7 +14,7 @@ struct x86_memmap_exclusion x86_memmap_exclusions[] = { { "locore", _locore_start, _locore_end }, #endif #ifdef CONFIG_XIP - { "rom", _image_rom_start, _image_rom_end }, + { "rom", __rom_region_start, __rom_region_end }, #endif { "ram", _image_ram_start, _image_ram_end }, #ifdef CONFIG_USERSPACE diff --git a/arch/x86/core/userspace.c b/arch/x86/core/userspace.c index 23342f150bd1..9064e691d28b 100644 --- a/arch/x86/core/userspace.c +++ b/arch/x86/core/userspace.c @@ -106,6 +106,42 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, stack_end -= 8; #endif +#if defined(CONFIG_DEMAND_PAGING) && \ + !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + /* If generic section is not present at boot, + * the thread stack may not be in physical memory. + * Unconditionally page in the stack instead of + * relying on page fault to speed up a little bit + * on starting the thread. + * + * Note that this also needs to page in the reserved + * portion of the stack (which is usually the page just + * before the beginning of stack in + * _current->stack_info.start. + */ + uintptr_t stack_start; + size_t stack_size; + uintptr_t stack_aligned_start; + size_t stack_aligned_size; + + stack_start = POINTER_TO_UINT(_current->stack_obj); + stack_size = Z_THREAD_STACK_SIZE_ADJUST(_current->stack_info.size); + +#if defined(CONFIG_HW_STACK_PROTECTION) + /* With hardware stack protection, the first page of stack + * is a guard page. So need to skip it. + */ + stack_start += CONFIG_MMU_PAGE_SIZE; + stack_size -= CONFIG_MMU_PAGE_SIZE; +#endif + + (void)k_mem_region_align(&stack_aligned_start, &stack_aligned_size, + stack_start, stack_size, + CONFIG_MMU_PAGE_SIZE); + k_mem_page_in(UINT_TO_POINTER(stack_aligned_start), + stack_aligned_size); +#endif + z_x86_userspace_enter(user_entry, p1, p2, p3, stack_end, _current->stack_info.start); CODE_UNREACHABLE; diff --git a/arch/x86/core/x86_mmu.c b/arch/x86/core/x86_mmu.c index 0a9e17ac669e..f54dc01d22a2 100644 --- a/arch/x86/core/x86_mmu.c +++ b/arch/x86/core/x86_mmu.c @@ -1238,7 +1238,7 @@ void z_x86_mmu_init(void) } #if CONFIG_X86_STACK_PROTECTION -__boot_func +__pinned_func void z_x86_set_stack_guard(k_thread_stack_t *stack) { /* Applied to all page tables as this affects supervisor mode. diff --git a/arch/x86/gen_mmu.py b/arch/x86/gen_mmu.py index 6cf33a084e1c..74b46355a4e3 100755 --- a/arch/x86/gen_mmu.py +++ b/arch/x86/gen_mmu.py @@ -22,8 +22,8 @@ vary: - By default, the Present, Write, and Execute Disable bits are set. - - The _image_text region will have Present and User bits set - - The _image_rodata region will have Present, User, and Execute + - The __text_region region will have Present and User bits set + - The __rodata_region region will have Present, User, and Execute Disable bits set - On x86_64, the _locore region will have Present set and the _lorodata region will have Present and Execute Disable set. @@ -667,8 +667,8 @@ def map_extra_regions(pt): one_map = {} one_map['cmdline'] = entry - one_map['phys'] = int(elements[0], 16) - one_map['size']= int(elements[1], 16) + one_map['phys'] = int(elements[0], 0) + one_map['size']= int(elements[1], 0) one_map['large_page'] = False flags = FLAG_P | ENTRY_XD @@ -786,21 +786,34 @@ def main(): is_perm_regions = isdef("CONFIG_SRAM_REGION_PERMISSIONS") + # Are pages in non-boot, non-pinned sections present at boot. + is_generic_section_present = isdef("CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT") + if image_size >= vm_size: error("VM size is too small (have 0x%x need more than 0x%x)" % (vm_size, image_size)) + map_flags = 0 + if is_perm_regions: # Don't allow execution by default for any pages. We'll adjust this # in later calls to pt.set_region_perms() - map_flags = FLAG_P | ENTRY_XD - else: - map_flags = FLAG_P + map_flags = ENTRY_XD pt = pclass(ptables_phys) # Instantiate all the paging structures for the address space pt.reserve(vm_base, vm_size) # Map the zephyr image - pt.map(image_base_phys, image_base, image_size, map_flags | ENTRY_RW) + if is_generic_section_present: + map_flags = map_flags | FLAG_P + pt.map(image_base_phys, image_base, image_size, map_flags | ENTRY_RW) + else: + # When generic linker sections are not present in physical memory, + # the corresponding virtual pages should not be mapped to non-existent + # physical pages. So simply identity map them to create the page table + # entries but without the present bit set. + # Boot and pinned sections (if configured) will be mapped to + # physical memory below. + pt.map(image_base, image_base, image_size, map_flags | ENTRY_RW) if virt_to_phys_offset != 0: # Need to identity map the physical address space @@ -820,18 +833,18 @@ def main(): locore_size = syms["_lodata_end"] - locore_base debug("Base addresses: physical 0x%x size 0x%x" % (locore_base, locore_size)) - pt.map(locore_base, None, locore_size, map_flags | ENTRY_RW) + pt.map(locore_base, None, locore_size, map_flags | FLAG_P | ENTRY_RW) if isdef("CONFIG_XIP"): # Additionally identity-map all ROM as read-only pt.map(syms["CONFIG_FLASH_BASE_ADDRESS"], None, - syms["CONFIG_FLASH_SIZE"] * 1024, map_flags) + syms["CONFIG_FLASH_SIZE"] * 1024, map_flags | FLAG_P) if isdef("CONFIG_LINKER_USE_BOOT_SECTION"): - pt.map_region("lnkr_boot", map_flags | ENTRY_RW, virt_to_phys_offset) + pt.map_region("lnkr_boot", map_flags | FLAG_P | ENTRY_RW, virt_to_phys_offset) if isdef("CONFIG_LINKER_USE_PINNED_SECTION"): - pt.map_region("lnkr_pinned", map_flags | ENTRY_RW, virt_to_phys_offset) + pt.map_region("lnkr_pinned", map_flags | FLAG_P | ENTRY_RW, virt_to_phys_offset) # Process extra mapping requests if args.map: @@ -846,27 +859,32 @@ def main(): # - User mode needs access as we currently do not separate application # text/rodata from kernel text/rodata if isdef("CONFIG_GDBSTUB"): - flags = FLAG_P | ENTRY_US | ENTRY_RW - + flags = ENTRY_US | ENTRY_RW else: - flags = FLAG_P | ENTRY_US + flags = ENTRY_US + + if is_generic_section_present: + flags = flags | FLAG_P - pt.set_region_perms("_image_text", flags) + pt.set_region_perms("__text_region", flags) if isdef("CONFIG_LINKER_USE_BOOT_SECTION"): - pt.set_region_perms("lnkr_boot_text", flags) + pt.set_region_perms("lnkr_boot_text", flags | FLAG_P) if isdef("CONFIG_LINKER_USE_PINNED_SECTION"): - pt.set_region_perms("lnkr_pinned_text", flags) + pt.set_region_perms("lnkr_pinned_text", flags | FLAG_P) + + flags = ENTRY_US | ENTRY_XD + if is_generic_section_present: + flags = flags | FLAG_P - flags = FLAG_P | ENTRY_US | ENTRY_XD - pt.set_region_perms("_image_rodata", flags) + pt.set_region_perms("__rodata_region", flags) if isdef("CONFIG_LINKER_USE_BOOT_SECTION"): - pt.set_region_perms("lnkr_boot_rodata", flags) + pt.set_region_perms("lnkr_boot_rodata", flags | FLAG_P) if isdef("CONFIG_LINKER_USE_PINNED_SECTION"): - pt.set_region_perms("lnkr_pinned_rodata", flags) + pt.set_region_perms("lnkr_pinned_rodata", flags | FLAG_P) if isdef("CONFIG_COVERAGE_GCOV") and isdef("CONFIG_USERSPACE"): # If GCOV is enabled, user mode must be able to write to its diff --git a/arch/x86/ia32.cmake b/arch/x86/ia32.cmake index 6f7182154562..ee2c7a7f01e7 100644 --- a/arch/x86/ia32.cmake +++ b/arch/x86/ia32.cmake @@ -12,7 +12,8 @@ endif() set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_ARCH "i386") set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-i386") -if(CMAKE_C_COMPILER_ID STREQUAL "Clang") +if(CMAKE_C_COMPILER_ID STREQUAL "Clang" + OR CMAKE_C_COMPILER_ID STREQUAL "IntelLLVM") zephyr_compile_options(-Qunused-arguments) zephyr_cc_option( diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index f92b2e298b29..6ae200ac52a6 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -78,4 +78,24 @@ config XTENSA_ENABLE_BACKTRACE help Enable this config option to print backtrace on panic exception +config XTENSA_CPU_IDLE_SPIN + bool "Use busy loop for k_cpu_idle" + help + Use a spin loop instead of WAITI for the CPU idle state. + +config XTENSA_WAITI_BUG + bool "Enable workaround sequence for WAITI bug on LX6" + help + SOF traditionally contains this workaround on its ADSP + platforms which prefixes a WAITI entry with 128 NOP + instructions followed by an ISYNC and EXTW. + +config XTENSA_SMALL_VECTOR_TABLE_ENTRY + bool "Enable workaround for small vector table entries" + help + This option enables a small indirection to bypass the size + constraint of the vector table entry and moved the default + handlers to the end of vector table, renaming them to + _Level\LVL\()VectorHelper. + endmenu diff --git a/arch/xtensa/core/cpu_idle.c b/arch/xtensa/core/cpu_idle.c index 7ce4ca6c3415..648ad1d8abdf 100644 --- a/arch/xtensa/core/cpu_idle.c +++ b/arch/xtensa/core/cpu_idle.c @@ -8,8 +8,36 @@ void arch_cpu_idle(void) { sys_trace_idle(); + + /* Just spin forever with interrupts unmasked, for platforms + * where WAITI can't be used or where its behavior is + * complicated (Intel DSPs will power gate on idle entry under + * some circumstances) + */ + if (IS_ENABLED(CONFIG_XTENSA_CPU_IDLE_SPIN)) { + __asm__ volatile("rsil a0, 0"); + __asm__ volatile("loop_forever: j loop_forever"); + return; + } + + /* Cribbed from SOF: workaround for a bug in some versions of + * the LX6 IP. Preprocessor ugliness avoids the need to + * figure out how to get the compiler to unroll a loop. + */ + if (IS_ENABLED(CONFIG_XTENSA_WAITI_BUG)) { +#define NOP4 __asm__ volatile("nop; nop; nop; nop"); +#define NOP32 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 +#define NOP128() NOP32 NOP32 NOP32 NOP32 + NOP128(); +#undef NOP128 +#undef NOP16 +#undef NOP4 + __asm__ volatile("isync; extw"); + } + __asm__ volatile ("waiti 0"); } + void arch_cpu_atomic_idle(unsigned int key) { sys_trace_idle(); diff --git a/arch/xtensa/core/xtensa-asm2-util.S b/arch/xtensa/core/xtensa-asm2-util.S index d46ea5ee3a75..0646c338672d 100644 --- a/arch/xtensa/core/xtensa-asm2-util.S +++ b/arch/xtensa/core/xtensa-asm2-util.S @@ -248,14 +248,17 @@ xtensa_switch: #ifdef CONFIG_KERNEL_COHERENCE /* Flush the stack. The top of stack was stored for us in - * EXCSAVE3 (FIXME: shouldn't be hardcoded!) by arch_cohere_stacks(). + * EXCSAVE3 (FIXME: shouldn't be hardcoded!) by + * arch_cohere_stacks(). It can be NULL for a dummy thread. */ rsr.EXCSAVE3 a0 + beqz a0, noflush mov a3, a1 flushloop: dhwb a3, 0 addi a3, a3, XCHAL_DCACHE_LINESIZE blt a3, a0, flushloop +noflush: #endif /* Restore the A3 argument we spilled earlier (via the base diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index 061b6a480eb7..b69f951adce1 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -111,7 +111,7 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread, /* Dummy threads appear at system initialization, but don't * have stack_info data and will never be saved. Ignore. */ - if (!osz) { + if (old_thread->base.thread_state & _THREAD_DUMMY) { return; } diff --git a/arch/xtensa/include/xtensa-asm2-s.h b/arch/xtensa/include/xtensa-asm2-s.h index ea7dd1d1de82..a10c4446bacf 100644 --- a/arch/xtensa/include/xtensa-asm2-s.h +++ b/arch/xtensa/include/xtensa-asm2-s.h @@ -356,6 +356,11 @@ _restore_\@: * with a simple jump instruction. */ .macro DEF_EXCINT LVL, ENTRY_SYM, C_HANDLER_SYM +#if defined(CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY) +.pushsection .iram.text, "ax" +.global _Level\LVL\()VectorHelper +_Level\LVL\()VectorHelper : +#else .if \LVL == 1 .pushsection .iram0.text, "ax" .elseif \LVL == XCHAL_DEBUGLEVEL @@ -367,6 +372,7 @@ _restore_\@: .endif .global _Level\LVL\()Vector _Level\LVL\()Vector: +#endif addi a1, a1, -BASE_SAVE_AREA_SIZE s32i a0, a1, BSA_A0_OFF s32i a2, a1, BSA_A2_OFF @@ -418,6 +424,23 @@ _after_imms\LVL: l32r a0, _handle_excint_imm\LVL jx a0 .popsection + +#if defined(CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY) +.if \LVL == 1 +.pushsection .iram0.text, "ax" +.elseif \LVL == XCHAL_DEBUGLEVEL +.pushsection .DebugExceptionVector.text, "ax" +.elseif \LVL == XCHAL_NMILEVEL +.pushsection .NMIExceptionVector.text, "ax" +.else +.pushsection .Level\LVL\()InterruptVector.text, "ax" +.endif +.global _Level\LVL\()Vector +_Level\LVL\()Vector : +j _Level\LVL\()VectorHelper +.popsection +#endif + .endm #endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_S_H */ diff --git a/boards/Kconfig b/boards/Kconfig index 650ea3144c0d..b295e23cad76 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -14,6 +14,13 @@ config QEMU_TARGET Mark all QEMU targets with this variable for checking whether we are running in an emulated environment. +config NET_DRIVERS + bool + default y if QEMU_TARGET && NETWORKING + help + When building for a qemu target then NET_DRIVERS will be default + enabled to allow for easy use of SLIP or PPP + # Note: $BOARD_DIR might be a glob pattern choice @@ -56,6 +63,14 @@ config QEMU_IVSHMEM_PLAIN_MEM_SIZE device in Qemu. Note that it's in mega-bytes, so 1 means 1M for Qemu etc.. +config QEMU_UEFI_BOOT + bool "QEMU uses UEFI to boot up" + default n + depends on BUILD_OUTPUT_EFI && QEMU_TARGET && X86_64 + help + This option indicates that QEMU will use UEFI bootable method + to boot up. + # There might not be any board options, hence the optional source osource "$(BOARD_DIR)/Kconfig" endmenu diff --git a/boards/arc/nsim/board.cmake b/boards/arc/nsim/board.cmake index cbd65a114531..a7e8d1ac4b35 100644 --- a/boards/arc/nsim/board.cmake +++ b/boards/arc/nsim/board.cmake @@ -1,28 +1,19 @@ # SPDX-License-Identifier: Apache-2.0 set(EMU_PLATFORM nsim) -if(NOT CONFIG_SOC_NSIM_HS_SMP) -board_set_flasher_ifnset(arc-nsim) -board_set_debugger_ifnset(arc-nsim) +if(NOT (CONFIG_SOC_NSIM_HS_SMP OR CONFIG_SOC_NSIM_HS6X_SMP)) + board_set_flasher_ifnset(arc-nsim) + board_set_debugger_ifnset(arc-nsim) + + set(NSIM_PROPS "${BOARD}.props") + board_runner_args(arc-nsim "--props=${NSIM_PROPS}") endif() -if(${CONFIG_SOC_NSIM_EM}) -board_runner_args(arc-nsim "--props=nsim_em.props") -board_runner_args(mdb-nsim "--nsim_args=mdb_em.args") -elseif(${CONFIG_SOC_NSIM_EM7D_V22}) -board_runner_args(arc-nsim "--props=nsim_em7d_v22.props") -board_runner_args(mdb-nsim "--nsim_args=mdb_em7d_v22.args") -elseif(${CONFIG_SOC_NSIM_SEM}) -board_runner_args(arc-nsim "--props=nsim_sem.props") -board_runner_args(mdb-nsim "--nsim_args=mdb_sem.args") -elseif(${CONFIG_SOC_NSIM_HS}) -board_runner_args(arc-nsim "--props=nsim_hs.props") -board_runner_args(mdb-nsim "--nsim_args=mdb_hs.args") -elseif(${CONFIG_SOC_NSIM_HS_SMP}) -board_runner_args(mdb-nsim "--cores=${CONFIG_MP_NUM_CPUS}" "--nsim_args=mdb_hs_smp.args") -elseif(${CONFIG_SOC_NSIM_HS6X}) -board_runner_args(arc-nsim "--props=nsim_hs6x.props") -board_runner_args(mdb-nsim "--nsim_args=mdb_hs6x.args") +string(REPLACE "nsim" "mdb" MDB_ARGS "${BOARD}.args") +if((CONFIG_SOC_NSIM_HS_SMP OR CONFIG_SOC_NSIM_HS6X_SMP)) + board_runner_args(mdb-nsim "--cores=${CONFIG_MP_NUM_CPUS}" "--nsim_args=${MDB_ARGS}") +else() + board_runner_args(mdb-nsim "--nsim_args=${MDB_ARGS}") endif() board_finalize_runner_args(arc-nsim) diff --git a/boards/arc/nsim/nsim_hs6x.yaml b/boards/arc/nsim/nsim_hs6x.yaml index 79aeec867b05..9cf8117a7277 100644 --- a/boards/arc/nsim/nsim_hs6x.yaml +++ b/boards/arc/nsim/nsim_hs6x.yaml @@ -5,6 +5,7 @@ simulation: nsim arch: arc toolchain: - cross-compile + - zephyr testing: ignore_tags: - net diff --git a/boards/arc/nsim/nsim_hs6x_smp.dts b/boards/arc/nsim/nsim_hs6x_smp.dts new file mode 100644 index 000000000000..72558defd3dd --- /dev/null +++ b/boards/arc/nsim/nsim_hs6x_smp.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021, Synopsys, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nsim.dtsi" + +/ { + model = "snps,nsim_hs"; + compatible = "snps,nsim_hs"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "snps,arcv3-hs"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "snps,arcv3-hs"; + reg = <1>; + }; + }; +}; diff --git a/boards/arc/nsim/nsim_hs6x_smp.yaml b/boards/arc/nsim/nsim_hs6x_smp.yaml new file mode 100644 index 000000000000..dc405920b73c --- /dev/null +++ b/boards/arc/nsim/nsim_hs6x_smp.yaml @@ -0,0 +1,12 @@ +identifier: nsim_hs6x_smp +name: Multi-core HS6x nSIM simulator +type: mcu +simulation: mdb-nsim +arch: arc +toolchain: + - cross-compile + - zephyr +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/arc/nsim/nsim_hs6x_smp_defconfig b/boards/arc/nsim/nsim_hs6x_smp_defconfig new file mode 100644 index 000000000000..c5fb9326c679 --- /dev/null +++ b/boards/arc/nsim/nsim_hs6x_smp_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ISA_ARCV3=y +CONFIG_SOC_NSIM=y +CONFIG_SOC_NSIM_HS6X_SMP=y +CONFIG_BOARD_NSIM=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_PRINTK=y +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_EXCEPTION_DEBUG=y +CONFIG_SMP=y +CONFIG_MP_NUM_CPUS=2 diff --git a/boards/arc/nsim/nsim_hs_mpuv6.dts b/boards/arc/nsim/nsim_hs_mpuv6.dts new file mode 100644 index 000000000000..c27b2253e8da --- /dev/null +++ b/boards/arc/nsim/nsim_hs_mpuv6.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nsim.dtsi" + +/ { + model = "snps,nsim_hs"; + compatible = "snps,nsim_hs"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "snps,archs"; + reg = <0>; + }; + }; +}; diff --git a/boards/arc/nsim/nsim_hs_mpuv6.yaml b/boards/arc/nsim/nsim_hs_mpuv6.yaml new file mode 100644 index 000000000000..906a3ea1afc7 --- /dev/null +++ b/boards/arc/nsim/nsim_hs_mpuv6.yaml @@ -0,0 +1,13 @@ +identifier: nsim_hs_mpuv6 +name: HS (with MPU v6) nSIM simulator +type: mcu +simulation: nsim +arch: arc +toolchain: + - zephyr + - arcmwdt +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/arc/nsim/nsim_hs_mpuv6_defconfig b/boards/arc/nsim/nsim_hs_mpuv6_defconfig new file mode 100644 index 000000000000..6ad394c2c5a3 --- /dev/null +++ b/boards/arc/nsim/nsim_hs_mpuv6_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_NSIM=y +CONFIG_SOC_NSIM_HS_MPUV6=y +CONFIG_BOARD_NSIM=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_PRINTK=y +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_EXCEPTION_DEBUG=y diff --git a/boards/arc/nsim/support/mdb_hs6x.args b/boards/arc/nsim/support/mdb_hs6x.args index 0b9984a33d9d..267f00d2bd73 100644 --- a/boards/arc/nsim/support/mdb_hs6x.args +++ b/boards/arc/nsim/support/mdb_hs6x.args @@ -10,7 +10,6 @@ -prop=nsim_isa_vec64=1 -dcache=65536,64,2,a -dcache_feature=2 - -dcache_uncached_region -dcache_mem_cycles=2 -icache=65536,64,4,a -icache_feature=2 diff --git a/boards/arc/nsim/support/mdb_hs6x_smp.args b/boards/arc/nsim/support/mdb_hs6x_smp.args new file mode 100644 index 000000000000..cbde485b271b --- /dev/null +++ b/boards/arc/nsim/support/mdb_hs6x_smp.args @@ -0,0 +1,30 @@ + -arc64 + -nogoifmain + -Xatomic + -Xtimer0 + -Xtimer1 + -Xdiv_rem + -Xunaligned + -prop=nsim_isa_addr_size=64 + -prop=nsim_isa_pc_size=64 + -prop=nsim_isa_vec64=1 + -dcache=65536,64,2,a + -dcache_feature=2 + -dcache_mem_cycles=2 + -icache=65536,64,4,a + -icache_feature=2 + -arconnect + -connect_ics=1 + -connect_ics_num_semas=16 + -connect_icm=1 + -connect_icm_sram_size=512 + -connect_icm_sram_prot=none + -connect_pmu=1 + -connect_idu=2 + -connect_idu_cirqnum=64 + -connect_gfrc=1 + -connect_icd=2 + -connect_ici=2 + -noprofile + -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=0,use_connect=1 + -instrs_per_pass=512 diff --git a/boards/arc/nsim/support/mdb_hs_mpuv6.args b/boards/arc/nsim/support/mdb_hs_mpuv6.args new file mode 100644 index 000000000000..a47fdf2718bd --- /dev/null +++ b/boards/arc/nsim/support/mdb_hs_mpuv6.args @@ -0,0 +1,45 @@ + -arcv2hs + -core2 + -arcnum=3 + -rgf_num_banks=2 + -rgf_banked_regs=32 + -rgf_num_wr_ports=2 + -Xatomic + -Xll64 + -Xunaligned + -Xcode_density + -Xdiv_rem=radix4 + -Xswap + -Xbitscan + -Xmpy_option=qmpyh + -mpuv6 + -mpu_regions=32 + -Xshift_assist + -Xbarrel_shifter + -Xfpud_div + -Xfpu_mac + -Xtimer0 + -Xtimer0_level=1 + -Xtimer1 + -Xtimer1_level=0 + -Xrtc + -action_points=8 + -Xstack_check + -interrupts=72 + -interrupt_priorities=2 + -ext_interrupts=70 + -firq + -interrupt_base=0x0 + -dcache=65536,64,2,a + -dcache_feature=2 + -dcache_uncached_region + -dcache_mem_cycles=2 + -icache=65536,64,4,a + -icache_feature=2 + -dccm_size=0x40000 + -dccm_base=0x80000000 + -dccm_mem_cycles=2 + -iccm0_size=0x40000 + -iccm0_base=0x70000000 + -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 + -noprofile diff --git a/boards/arc/nsim/support/nsim_hs_mpuv6.props b/boards/arc/nsim/support/nsim_hs_mpuv6.props new file mode 100644 index 000000000000..62050e83cb4d --- /dev/null +++ b/boards/arc/nsim/support/nsim_hs_mpuv6.props @@ -0,0 +1,48 @@ + nsim_isa_family=av2hs + nsim_isa_core=2 + arcver=0x52 + nsim_isa_rgf_num_banks=2 + nsim_isa_rgf_banked_regs=32 + nsim_isa_rgf_num_regs=32 + nsim_isa_rgf_num_wr_ports=2 + nsim_isa_big_endian=0 + nsim_isa_lpc_size=32 + nsim_isa_pc_size=32 + nsim_isa_addr_size=32 + nsim_isa_atomic_option=1 + nsim_isa_ll64_option=1 + nsim_isa_unaligned_option=1 + nsim_isa_code_density_option=2 + nsim_isa_div_rem_option=2 + nsim_isa_swap_option=1 + nsim_isa_bitscan_option=1 + nsim_isa_mpy_option=9 + nsim_isa_shift_option=3 + mpu_regions=32 + mpu_version=6 + nsim_isa_fpud_div_option=1 + nsim_isa_fpu_mac_option=1 + nsim_isa_enable_timer_0=1 + nsim_isa_timer_0_int_level=1 + nsim_isa_enable_timer_1=1 + nsim_isa_timer_1_int_level=0 + nsim_isa_rtc_option=1 + nsim_isa_num_actionpoints=8 + nsim_isa_stack_checking=1 + nsim_isa_number_of_interrupts=72 + nsim_isa_number_of_levels=2 + nsim_isa_number_of_external_interrupts=70 + nsim_isa_fast_irq=1 + nsim_isa_intvbase_preset=0x0 + dcache=65536,64,2,a + nsim_isa_dc_feature_level=2 + nsim_isa_dc_uncached_region=1 + nsim_isa_dc_mem_cycles=2 + icache=65536,64,4,a + nsim_isa_ic_feature_level=2 + dccm_size=0x40000 + dccm_base=0x80000000 + nsim_isa_dccm_mem_cycles=2 + iccm0_size=0x40000 + iccm0_base=0x70000000 + nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 diff --git a/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args b/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args new file mode 100644 index 000000000000..eff65ee81709 --- /dev/null +++ b/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args @@ -0,0 +1,54 @@ + -arcv2em + -core3 + -rgf_num_banks=1 + -rgf_num_wr_ports=1 + -Xcode_density + -Xdiv_rem=radix2 + -turbo_boost + -Xswap + -Xbitscan + -Xmpy_option=mpyd + -Xshift_assist + -Xbarrel_shifter + -Xdsp2 + -Xdsp_complex + -Xdsp_divsqrt=radix2 + -Xdsp_accshift=limited + -Xtimer0 + -Xtimer0_level=1 + -Xtimer1 + -Xtimer1_level=0 + -Xsec_timer0 + -Xsec_timer0_level=1 + -action_points=2 + -Xstack_check + -smart_stack_entries=8 + -mpuv4 + -mpu_sid + -mpu_regions=16 + -interrupts=22 + -interrupt_priorities=4 + -ext_interrupts=17 + -interrupt_base=0x0 + -sec_interrupt_base=0x0 + -dcache=16384,32,2,a + -dcache_feature=2 + -icache=16384,32,2,a + -icache_feature=2 + -dccm_size=0x80000 + -dccm_base=0x80000000 + -dccm_interleave + -iccm0_size=0x80000 + -iccm0_base=0x00000000 + -esp_encrypt + -Xsec_modes + -iccm0_sec_lvl=NS + -dccm_sec_lvl=NS + -Xpct_counters=8 + -dmac + -dmac_channels=2 + -dmac_registers=0 + -dmac_fifo_depth=2 + -dmac_int_config=single_internal + -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 + -noprofile diff --git a/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props b/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props new file mode 100644 index 000000000000..857168a9ea80 --- /dev/null +++ b/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props @@ -0,0 +1,58 @@ + nsim_isa_family=av2em + nsim_isa_core=3 + arcver=0x43 + nsim_isa_rgf_num_banks=1 + nsim_isa_rgf_num_regs=32 + nsim_isa_rgf_num_wr_ports=1 + nsim_isa_big_endian=0 + nsim_isa_lpc_size=32 + nsim_isa_pc_size=32 + nsim_isa_addr_size=32 + nsim_isa_code_density_option=2 + nsim_isa_div_rem_option=1 + nsim_isa_turbo_boost=1 + nsim_isa_swap_option=1 + nsim_isa_bitscan_option=1 + nsim_isa_mpy_option=8 + nsim_isa_shift_option=3 + nsim_isa_dsp_option=2 + nsim_isa_dsp_complex_option=1 + nsim_isa_dsp_divsqrt_option=1 + nsim_isa_dsp_accshift_option=1 + nsim_isa_enable_timer_0=1 + nsim_isa_timer_0_int_level=1 + nsim_isa_enable_timer_1=1 + nsim_isa_timer_1_int_level=0 + nsim_isa_enable_sec_timer_0=1 + nsim_isa_stimer_0_int_level=1 + nsim_isa_num_actionpoints=2 + nsim_isa_stack_checking=1 + nsim_isa_smart_stack_entries=8 + mpu_sid_option=1 + mpu_regions=16 + mpu_version=4 + nsim_isa_number_of_interrupts=22 + nsim_isa_number_of_levels=4 + nsim_isa_number_of_external_interrupts=17 + nsim_isa_intvbase_preset=0x0 + nsim_isa_intvbase_preset_s=0x0 + dcache=16384,32,2,a + nsim_isa_dc_feature_level=2 + icache=16384,32,2,a + nsim_isa_ic_feature_level=2 + dccm_size=0x80000 + dccm_base=0x80000000 + nsim_isa_dccm_interleave=1 + iccm0_size=0x80000 + iccm0_base=0x00000000 + nsim_isa_has_secure=1 + nsim_isa_sec_modes_option=1 + iccm0_sec_lvl=NS + dccm_sec_lvl=NS + nsim_isa_pct_counters=8 + nsim_isa_dmac_option=1 + nsim_isa_dmac_channels=2 + nsim_isa_dmac_registers=0 + nsim_isa_dmac_fifo_depth=2 + nsim_isa_dmac_int_config=single_internal + nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x.yaml b/boards/arc/qemu_arc/qemu_arc_hs6x.yaml index 181f45cffff6..6c8d0c1102fd 100644 --- a/boards/arc/qemu_arc/qemu_arc_hs6x.yaml +++ b/boards/arc/qemu_arc/qemu_arc_hs6x.yaml @@ -5,7 +5,9 @@ simulation: qemu arch: arc toolchain: - cross-compile + - zephyr testing: + default: true ignore_tags: - net - bluetooth diff --git a/boards/arm/96b_aerocore2/96b_aerocore2.dts b/boards/arm/96b_aerocore2/96b_aerocore2.dts index 356c905e2d67..b5d53dff968f 100644 --- a/boards/arm/96b_aerocore2/96b_aerocore2.dts +++ b/boards/arm/96b_aerocore2/96b_aerocore2.dts @@ -127,7 +127,7 @@ clock-frequency = ; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/96b_carbon/96b_carbon.dts b/boards/arm/96b_carbon/96b_carbon.dts index c8fe3cdafcd8..cd792a49ff28 100644 --- a/boards/arm/96b_carbon/96b_carbon.dts +++ b/boards/arm/96b_carbon/96b_carbon.dts @@ -128,7 +128,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/96b_wistrio/CMakeLists.txt b/boards/arm/96b_wistrio/CMakeLists.txt index 100db5518c64..1333f5929a81 100644 --- a/boards/arm/96b_wistrio/CMakeLists.txt +++ b/boards/arm/96b_wistrio/CMakeLists.txt @@ -1,4 +1,2 @@ -if(CONFIG_PINMUX) zephyr_library() -zephyr_library_sources(pinmux.c) -endif() +zephyr_library_sources(pins.c) diff --git a/boards/arm/96b_wistrio/pinmux.c b/boards/arm/96b_wistrio/pins.c similarity index 59% rename from boards/arm/96b_wistrio/pinmux.c rename to boards/arm/96b_wistrio/pins.c index 13e2d7ee713d..f2c58a7bf743 100644 --- a/boards/arm/96b_wistrio/pinmux.c +++ b/boards/arm/96b_wistrio/pins.c @@ -8,27 +8,13 @@ #include #include #include -#include #include -#include - -static const struct pin_config pinconf[] = { - /* RF_CTX_PA */ - {STM32_PIN_PA4, STM32_PUSHPULL_PULLUP}, - /* RF_CRX_RX */ - {STM32_PIN_PB6, STM32_PUSHPULL_PULLUP}, - /* RF_CBT_HF */ - {STM32_PIN_PB7, STM32_PUSHPULL_PULLUP}, -}; - -static int pinmux_stm32_init(const struct device *port) +static int pins_stm32_init(const struct device *port) { ARG_UNUSED(port); const struct device *gpioa, *gpiob, *gpioh; - stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf)); - gpioa = device_get_binding(DT_LABEL(DT_NODELABEL(gpioa))); if (!gpioa) { return -ENODEV; @@ -44,13 +30,16 @@ static int pinmux_stm32_init(const struct device *port) return -ENODEV; } - gpio_pin_configure(gpioa, 4, GPIO_OUTPUT); + /* RF_CTX_PA */ + gpio_pin_configure(gpioa, 4, GPIO_OUTPUT | GPIO_PULL_UP); gpio_pin_set(gpioa, 4, 1); - gpio_pin_configure(gpiob, 6, GPIO_OUTPUT); + /* RF_CRX_RX */ + gpio_pin_configure(gpiob, 6, GPIO_OUTPUT | GPIO_PULL_UP); gpio_pin_set(gpiob, 6, 1); - gpio_pin_configure(gpiob, 7, GPIO_OUTPUT); + /* RF_CBT_HF */ + gpio_pin_configure(gpiob, 7, GPIO_OUTPUT | GPIO_PULL_UP); gpio_pin_set(gpiob, 7, 0); gpio_pin_configure(gpioh, 1, GPIO_OUTPUT); @@ -60,4 +49,4 @@ static int pinmux_stm32_init(const struct device *port) } /* Need to be initialised after GPIO driver */ -SYS_INIT(pinmux_stm32_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); +SYS_INIT(pins_stm32_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/arm/actinius_icarus/board.c b/boards/arm/actinius_icarus/board.c index 2579469b8ae1..0cd9ef88a7ed 100644 --- a/boards/arm/actinius_icarus/board.c +++ b/boards/arm/actinius_icarus/board.c @@ -40,5 +40,5 @@ static int board_actinius_icarus_init(const struct device *dev) return 0; } -SYS_INIT(board_actinius_icarus_init, POST_KERNEL, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +/* Needs to happen after GPIO driver init */ +SYS_INIT(board_actinius_icarus_init, POST_KERNEL, 99); diff --git a/boards/arm/actinius_icarus_bee/board.c b/boards/arm/actinius_icarus_bee/board.c index 7b191c804661..d59b6170fb11 100644 --- a/boards/arm/actinius_icarus_bee/board.c +++ b/boards/arm/actinius_icarus_bee/board.c @@ -40,5 +40,5 @@ static int board_actinius_icarus_bee_init(const struct device *dev) return 0; } -SYS_INIT(board_actinius_icarus_bee_init, POST_KERNEL, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +/* Needs to happen after GPIO driver init */ +SYS_INIT(board_actinius_icarus_bee_init, POST_KERNEL, 99); diff --git a/boards/arm/actinius_icarus_som/board.c b/boards/arm/actinius_icarus_som/board.c index dc92109a8dbf..a623501071e5 100644 --- a/boards/arm/actinius_icarus_som/board.c +++ b/boards/arm/actinius_icarus_som/board.c @@ -40,5 +40,5 @@ static int board_actinius_icarus_som_init(const struct device *dev) return 0; } -SYS_INIT(board_actinius_icarus_som_init, POST_KERNEL, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +/* Needs to happen after GPIO driver init */ +SYS_INIT(board_actinius_icarus_som_init, POST_KERNEL, 99); diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts b/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts index 0995726d6781..f4733284aa56 100644 --- a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts +++ b/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts @@ -46,6 +46,8 @@ current-speed = <115200>; rxpo = <3>; txpo = <1>; + + pinctrl-0 = <&pa11c_sercom0_pad3 &pa10c_sercom0_pad2>; }; &sercom3 { diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig b/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig index c5e974851e97..dd1a99d61c57 100644 --- a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig +++ b/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig @@ -15,12 +15,8 @@ CONFIG_WATCHDOG=y CONFIG_WDT_SAM0=y CONFIG_SOC_ATMEL_SAMD_XOSC32K=y CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_SPI=y -CONFIG_SPI_SAM0=y CONFIG_PINMUX=y CONFIG_PINMUX_SAM0=y -CONFIG_USB=y -CONFIG_USB_DC_SAM0=y CONFIG_USE_DT_CODE_PARTITION=y CONFIG_I2C=y CONFIG_I2C_SAM0=y diff --git a/boards/arm/adafruit_feather_m0_basic_proto/pinmux.c b/boards/arm/adafruit_feather_m0_basic_proto/pinmux.c index 899a3d445c0d..4a9b4c182f3a 100644 --- a/boards/arm/adafruit_feather_m0_basic_proto/pinmux.c +++ b/boards/arm/adafruit_feather_m0_basic_proto/pinmux.c @@ -11,37 +11,16 @@ static int board_pinmux_init(const struct device *dev) { const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); - - __ASSERT_NO_MSG(device_is_ready(muxa)); - -#if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_spi) && CONFIG_SPI_SAM0) const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); - __ASSERT_NO_MSG(device_is_ready(muxb)); -#endif ARG_UNUSED(dev); -#if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM0 on RX=PA11/pad 3, TX=PA10/pad 2 */ - pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); -#endif - -#if (ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } #if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_spi) && CONFIG_SPI_SAM0) /* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */ @@ -96,4 +75,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig b/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig index f09ae11e4644..f2d04d6cc488 100644 --- a/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig +++ b/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_ADAFRUIT_FEATHER_NRF52840 config BOARD default "adafruit_feather_nrf52840" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.dts b/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.dts index 5844cdadec66..9ac820e466cf 100644 --- a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.dts +++ b/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.dts @@ -150,7 +150,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts b/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts index 054f1a25b9b0..08c644aadbb0 100644 --- a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts +++ b/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts @@ -52,6 +52,8 @@ current-speed = <115200>; rxpo = <1>; txpo = <0>; + + pinctrl-0 = <&pa16d_sercom3_pad1 &pa17d_sercom3_pad0>; }; &sercom1 { @@ -72,7 +74,7 @@ #pwm-cells = <1>; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; diff --git a/boards/arm/adafruit_itsybitsy_m4_express/pinmux.c b/boards/arm/adafruit_itsybitsy_m4_express/pinmux.c index bbb129e374d3..76833e20a62a 100644 --- a/boards/arm/adafruit_itsybitsy_m4_express/pinmux.c +++ b/boards/arm/adafruit_itsybitsy_m4_express/pinmux.c @@ -10,34 +10,17 @@ static int board_pinmux_init(const struct device *dev) { - __unused const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); - __unused const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); - - __ASSERT_NO_MSG(device_is_ready(muxa)); - __ASSERT_NO_MSG(device_is_ready(muxb)); + const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); + const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); ARG_UNUSED(dev); -#if ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) - /* SERCOM3 on RX=PA16/pad 1, TX=PA17/pad 0 */ - pinmux_pin_set(muxa, 16, PINMUX_FUNC_D); - pinmux_pin_set(muxa, 17, PINMUX_FUNC_D); -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } #if ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_spi) && defined(CONFIG_SPI_SAM0) /* SPI SERCOM1 on MISO=PB23/pad 3, MOSI=PA0/pad 0, SCK=PA1/pad 1 */ @@ -81,4 +64,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.dts b/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.dts index ecaf358017e4..334770832dd6 100644 --- a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.dts +++ b/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.dts @@ -52,6 +52,8 @@ current-speed = <115200>; rxpo = <3>; txpo = <1>; + + pinctrl-0 = <&pa7d_sercom0_pad3 &pa6d_sercom0_pad2>; }; &sercom2 { @@ -60,6 +62,8 @@ current-speed = <115200>; rxpo = <1>; txpo = <0>; + + pinctrl-0 = <&pa9d_sercom2_pad1 &pa8d_sercom2_pad0>; }; /* Drives the on-board DotStar LED */ @@ -118,6 +122,6 @@ }; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; diff --git a/boards/arm/adafruit_trinket_m0/pinmux.c b/boards/arm/adafruit_trinket_m0/pinmux.c index d79305c2153a..bd5b82922916 100644 --- a/boards/arm/adafruit_trinket_m0/pinmux.c +++ b/boards/arm/adafruit_trinket_m0/pinmux.c @@ -12,34 +12,11 @@ static int board_pinmux_init(const struct device *dev) { const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); - __ASSERT_NO_MSG(device_is_ready(muxa)); - ARG_UNUSED(dev); -#if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM0 on RX=PA7/pad 3, TX=PA6/pad 2 */ - pinmux_pin_set(muxa, 7, PINMUX_FUNC_D); - pinmux_pin_set(muxa, 6, PINMUX_FUNC_D); -#endif - -#if (ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM2 on RX=PA9/pad 1, TX=PA8/pad 0 */ - pinmux_pin_set(muxa, 9, PINMUX_FUNC_D); - pinmux_pin_set(muxa, 8, PINMUX_FUNC_D); -#endif - -#if (ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } #if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_spi) && CONFIG_SPI_SAM0) /* SPI SERCOM0 on MISO=PA9/pad 1, MOSI=PA6/pad 2, SCK=PA7/pad 3 */ @@ -82,4 +59,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/arduino_nano_33_ble/Kconfig.board b/boards/arm/arduino_nano_33_ble/Kconfig.board index 476a9123da96..ebf4b156c455 100644 --- a/boards/arm/arduino_nano_33_ble/Kconfig.board +++ b/boards/arm/arduino_nano_33_ble/Kconfig.board @@ -9,7 +9,7 @@ config BOARD_ARDUINO_NANO_33_BLE_EN_USB_CONSOLE bool "Sends the console output over the USB port" depends on BOARD_ARDUINO_NANO_33_BLE select SERIAL - select USB + select USB_DEVICE_STACK select CONSOLE select PRINTK select UART_INTERRUPT_DRIVEN diff --git a/boards/arm/arduino_nano_33_ble/Kconfig.defconfig b/boards/arm/arduino_nano_33_ble/Kconfig.defconfig index 937aba0014e1..81b82541ccf4 100644 --- a/boards/arm/arduino_nano_33_ble/Kconfig.defconfig +++ b/boards/arm/arduino_nano_33_ble/Kconfig.defconfig @@ -5,13 +5,6 @@ if BOARD_ARDUINO_NANO_33_BLE config BOARD default "arduino_nano_33_ble" -if USB -config USB_NRFX - default y -config USB_DEVICE_STACK - default y -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts index d11d800eb53c..7e509086d27c 100644 --- a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts +++ b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts @@ -110,7 +110,7 @@ &gpio1 { status = "okay"; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig index ba8eeee9315c..5fbe4ccdfb08 100644 --- a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig +++ b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig @@ -11,7 +11,6 @@ CONFIG_HW_STACK_PROTECTION=y # enable peripherals CONFIG_GPIO=y CONFIG_SERIAL=y -CONFIG_CONSOLE=y # enable sam-ba bootloader on legacy mode CONFIG_BOOTLOADER_BOSSA=y diff --git a/boards/arm/arduino_nano_33_ble/doc/index.rst b/boards/arm/arduino_nano_33_ble/doc/index.rst index 9506ed558f78..431a445b9897 100644 --- a/boards/arm/arduino_nano_33_ble/doc/index.rst +++ b/boards/arm/arduino_nano_33_ble/doc/index.rst @@ -77,7 +77,7 @@ if you link against the :code:`arduino_nano_33_ble_pins` CMake library. For your convience, two Kconfig options are added: -#. :code:`BOARD_ARDUINO_NANO_33_BLE_INIT_SENSORS`: +#. :code:`BOARD_ARDUINO_NANO_33_BLE_INIT_SENSORS`: This configuration option enables the internal I2C sensors. #. :code:`BOARD_ARDUINO_NANO_33_BLE_EN_USB_CONSOLE`: This configuration option enables the USB CDC subsystem and @@ -98,6 +98,7 @@ You can get this variant of bossac with one of two ways: #. Install the board support package within the IDE #. Change your IDE preferences to provide verbose logging #. Build and flash a sample application, and read the logs to figure out where Arduino stored bossac. + #. In most Linux based systems the path is ``$HOME/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac``. Once you have a path to bossac, you can pass it as an argument to west: @@ -105,13 +106,19 @@ Once you have a path to bossac, you can pass it as an argument to west: west flash --bossac="" +For example + +.. code-block:: bash + + west flash --bossac=$HOME/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac + Flashing ======== Attach the board to your computer using the USB cable, and then .. zephyr-app-commands:: - :zephyr-app: samples/blinky + :zephyr-app: samples/basic/blinky :board: arduino_nano_33_ble :goals: build :compact: diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.dts b/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.dts index 62cbec6516d3..ae797b472336 100644 --- a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.dts +++ b/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.dts @@ -83,6 +83,8 @@ rxpo = <1>; txpo = <0>; + pinctrl-0 = <&pa23c_sercom3_pad1 &pa22c_sercom3_pad0>; + nina_prog { compatible = "espressif,esp-at"; label = "NINA_PROG"; @@ -116,6 +118,8 @@ current-speed = <115200>; rxpo = <3>; txpo = <1>; + + pinctrl-0 = <&pb23d_sercom5_pad3 &pb22d_sercom5_pad2>; }; &tcc2 { @@ -155,6 +159,6 @@ }; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; diff --git a/boards/arm/arduino_nano_33_iot/pinmux.c b/boards/arm/arduino_nano_33_iot/pinmux.c index 30100ae67ed7..50160d6ea5df 100644 --- a/boards/arm/arduino_nano_33_iot/pinmux.c +++ b/boards/arm/arduino_nano_33_iot/pinmux.c @@ -13,35 +13,14 @@ static int board_pinmux_init(const struct device *dev) const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); - __ASSERT_NO_MSG(device_is_ready(muxa)); - __ASSERT_NO_MSG(device_is_ready(muxb)); - ARG_UNUSED(dev); -#if defined(CONFIG_UART_SAM0) -#if ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) - /* SERCOM3 on RX=PA23/pad 1, TX=PA22/pad 0 */ - pinmux_pin_set(muxa, 22, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 23, PINMUX_FUNC_C); -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) - /* SERCOM5 on RX=PB23/pad 3, TX=PB22/pad 2 */ - pinmux_pin_set(muxb, 23, PINMUX_FUNC_D); - pinmux_pin_set(muxb, 22, PINMUX_FUNC_D); -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) -#warning Pin mapping may not be configured -#endif -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } #if defined(CONFIG_SPI_SAM0) #if ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_spi) @@ -109,4 +88,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/arduino_zero/arduino_zero.dts b/boards/arm/arduino_zero/arduino_zero.dts index 73832e4ace1a..27d7dc3156b8 100644 --- a/boards/arm/arduino_zero/arduino_zero.dts +++ b/boards/arm/arduino_zero/arduino_zero.dts @@ -61,6 +61,8 @@ current-speed = <115200>; rxpo = <3>; txpo = <1>; + + pinctrl-0 = <&pa11c_sercom0_pad3 &pa10c_sercom0_pad2>; }; &sercom5 { @@ -69,6 +71,8 @@ current-speed = <115200>; rxpo = <3>; txpo = <1>; + + pinctrl-0 = <&pb23d_sercom5_pad3 &pb22d_sercom5_pad2>; }; &sercom4 { @@ -111,6 +115,6 @@ }; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; diff --git a/boards/arm/arduino_zero/pinmux.c b/boards/arm/arduino_zero/pinmux.c index ed84d4f0bca0..3adb042c337b 100644 --- a/boards/arm/arduino_zero/pinmux.c +++ b/boards/arm/arduino_zero/pinmux.c @@ -13,35 +13,14 @@ static int board_pinmux_init(const struct device *dev) const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); - __ASSERT_NO_MSG(device_is_ready(muxa)); - __ASSERT_NO_MSG(device_is_ready(muxb)); - ARG_UNUSED(dev); -#if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM0 on RX=PA11, TX=PA10 */ - pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); -#endif - -#if (ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM5 on RX=PB23, TX=PB22 */ - pinmux_pin_set(muxb, 23, PINMUX_FUNC_D); - pinmux_pin_set(muxb, 22, PINMUX_FUNC_D); -#endif - -#if (ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } #if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_spi) && CONFIG_SPI_SAM0) /* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */ @@ -85,4 +64,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro.dts b/boards/arm/atsamd20_xpro/atsamd20_xpro.dts index 8d9042554f17..b6f1d6e3ac3a 100644 --- a/boards/arm/atsamd20_xpro/atsamd20_xpro.dts +++ b/boards/arm/atsamd20_xpro/atsamd20_xpro.dts @@ -69,6 +69,8 @@ current-speed = <115200>; rxpo = <3>; txpo = <1>; + + pinctrl-0 = <&pa25c_sercom3_pad3 &pa24c_sercom3_pad2>; }; &sercom4 { @@ -77,6 +79,8 @@ current-speed = <115200>; rxpo = <1>; txpo = <0>; + + pinctrl-0 = <&pb9d_sercom4_pad1 &pb8d_sercom4_pad0>; }; &flash0 { diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig b/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig index 26b29a110b84..f9332d42d975 100644 --- a/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig +++ b/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig @@ -16,7 +16,5 @@ CONFIG_WATCHDOG=y CONFIG_WDT_SAM0=y CONFIG_SOC_ATMEL_SAMD_XOSC32K=y CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_SPI=y -CONFIG_SPI_SAM0=y CONFIG_PINMUX=y CONFIG_PINMUX_SAM0=y diff --git a/boards/arm/atsamd20_xpro/pinmux.c b/boards/arm/atsamd20_xpro/pinmux.c index 438719060518..c76a26e555a6 100644 --- a/boards/arm/atsamd20_xpro/pinmux.c +++ b/boards/arm/atsamd20_xpro/pinmux.c @@ -13,32 +13,14 @@ static int board_pinmux_init(const struct device *dev) const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); - __ASSERT_NO_MSG(device_is_ready(muxa)); - __ASSERT_NO_MSG(device_is_ready(muxb)); - ARG_UNUSED(dev); -#if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM3 on RX=PA25, TX=PA24 */ - pinmux_pin_set(muxa, 24, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 25, PINMUX_FUNC_C); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && CONFIG_UART_SAM0) - pinmux_pin_set(muxb, 8, PINMUX_FUNC_D); - pinmux_pin_set(muxb, 9, PINMUX_FUNC_D); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } #if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_spi) && CONFIG_SPI_SAM0) /* SPI SERCOM0 on MISO=PA04, MOSI=PA06, SCK=PA07 */ @@ -86,4 +68,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro.dts b/boards/arm/atsamd21_xpro/atsamd21_xpro.dts index 2e8e38f6135d..414a1a92e236 100644 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro.dts +++ b/boards/arm/atsamd21_xpro/atsamd21_xpro.dts @@ -68,6 +68,8 @@ current-speed = <9600>; rxpo = <3>; txpo = <2>; + + pinctrl-0 = <&pa11c_sercom0_pad3 &pa10c_sercom0_pad2>; }; &sercom1 { @@ -76,6 +78,8 @@ current-speed = <115200>; rxpo = <3>; txpo = <0>; + + pinctrl-0 = <&pa19c_sercom1_pad3 &pa16c_sercom1_pad0>; }; &sercom2 { @@ -92,6 +96,8 @@ current-speed = <115200>; rxpo = <1>; txpo = <0>; + + pinctrl-0 = <&pa23c_sercom3_pad1 &pa22c_sercom3_pad0>; }; &sercom5 { @@ -103,6 +109,6 @@ #size-cells = <0>; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig b/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig index 5692e3901d88..2046a4a01500 100644 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig +++ b/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig @@ -16,7 +16,5 @@ CONFIG_WATCHDOG=y CONFIG_WDT_SAM0=y CONFIG_SOC_ATMEL_SAMD_XOSC32K=y CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_SPI=y -CONFIG_SPI_SAM0=y CONFIG_PINMUX=y CONFIG_PINMUX_SAM0=y diff --git a/boards/arm/atsamd21_xpro/pinmux.c b/boards/arm/atsamd21_xpro/pinmux.c index af33f7105f74..477ae7936d8d 100644 --- a/boards/arm/atsamd21_xpro/pinmux.c +++ b/boards/arm/atsamd21_xpro/pinmux.c @@ -13,35 +13,14 @@ static int board_pinmux_init(const struct device *dev) const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); - __ASSERT_NO_MSG(device_is_ready(muxa)); - __ASSERT_NO_MSG(device_is_ready(muxb)); - ARG_UNUSED(dev); -#if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM0 on RX=PA11, TX=PA10 */ - pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM3 ON RX=PA19, TX=PA16 */ - pinmux_pin_set(muxa, 19, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 16, PINMUX_FUNC_C); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM3 ON RX=PA23, TX=PA22 */ - pinmux_pin_set(muxa, 23, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 22, PINMUX_FUNC_C); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } #if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_spi) && CONFIG_SPI_SAM0) #warning Pin mapping may not be configured @@ -99,4 +78,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/atsame54_xpro/atsame54_xpro.dts b/boards/arm/atsame54_xpro/atsame54_xpro.dts index 73a922f40766..3dafd033c702 100644 --- a/boards/arm/atsame54_xpro/atsame54_xpro.dts +++ b/boards/arm/atsame54_xpro/atsame54_xpro.dts @@ -66,6 +66,8 @@ txpo = <0>; #address-cells = <1>; #size-cells = <0>; + + pinctrl-0 = <&pb25d_sercom2_pad1 &pb24d_sercom2_pad0>; }; &sercom4 { @@ -95,11 +97,22 @@ status = "okay"; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; &gmac { status = "okay"; zephyr,random-mac-address; + + phy: phy { + compatible = "ethernet-phy"; + status = "okay"; + address = <0>; + mdio = <&mdio>; + }; +}; + +&mdio { + status = "okay"; }; diff --git a/boards/arm/atsame54_xpro/atsame54_xpro.yaml b/boards/arm/atsame54_xpro/atsame54_xpro.yaml index 48dcc0263242..68366761647f 100644 --- a/boards/arm/atsame54_xpro/atsame54_xpro.yaml +++ b/boards/arm/atsame54_xpro/atsame54_xpro.yaml @@ -11,6 +11,7 @@ toolchain: - gnuarmemb - xtools supported: + - adc - gpio - pwm - spi diff --git a/boards/arm/atsame54_xpro/pinmux.c b/boards/arm/atsame54_xpro/pinmux.c index 708459313238..4a4a64d23588 100644 --- a/boards/arm/atsame54_xpro/pinmux.c +++ b/boards/arm/atsame54_xpro/pinmux.c @@ -15,46 +15,20 @@ static int board_pinmux_init(const struct device *dev) const struct device *muxc = DEVICE_DT_GET(DT_NODELABEL(pinmux_c)); const struct device *muxd = DEVICE_DT_GET(DT_NODELABEL(pinmux_d)); - __ASSERT_NO_MSG(device_is_ready(muxa)); - __ASSERT_NO_MSG(device_is_ready(muxb)); - __ASSERT_NO_MSG(device_is_ready(muxc)); - __ASSERT_NO_MSG(device_is_ready(muxd)); - ARG_UNUSED(dev); - ARG_UNUSED(muxa); - ARG_UNUSED(muxb); - ARG_UNUSED(muxc); - ARG_UNUSED(muxd); -#if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* NOTE: SERCOM1 UART is used by the UART driver tests */ - /* SERCOM1 ON RX=PC22, TX=PC23 */ - pinmux_pin_set(muxc, 22, PINMUX_FUNC_C); - pinmux_pin_set(muxc, 23, PINMUX_FUNC_C); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM2 ON RX=PB24, TX=PB25 */ - pinmux_pin_set(muxb, 24, PINMUX_FUNC_D); - pinmux_pin_set(muxb, 25, PINMUX_FUNC_D); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(6, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(7, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } + if (!device_is_ready(muxc)) { + return -ENXIO; + } + if (!device_is_ready(muxd)) { + return -ENXIO; + } #if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_spi) && CONFIG_SPI_SAM0) #warning Pin mapping may not be configured @@ -137,4 +111,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro.dts b/boards/arm/atsamr21_xpro/atsamr21_xpro.dts index 26a18c76db34..ea0722da8dac 100644 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro.dts +++ b/boards/arm/atsamr21_xpro/atsamr21_xpro.dts @@ -113,6 +113,8 @@ current-speed = <115200>; rxpo = <1>; txpo = <0>; + + pinctrl-0 = <&pa5d_sercom0_pad1 &pa4d_sercom0_pad0>; }; &sercom1 { @@ -162,7 +164,7 @@ #size-cells = <0>; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml b/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml index c2d0c19bca2a..d0e1cda7bf96 100644 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml +++ b/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml @@ -12,6 +12,7 @@ toolchain: - gnuarmemb - xtools supported: + - adc - gpio - i2c - ieee802154 diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig b/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig index 405c5a4984c7..3ea41fa6e6f7 100644 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig +++ b/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig @@ -19,4 +19,3 @@ CONFIG_SOC_ATMEL_SAMD_XOSC32K=y CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y CONFIG_PINMUX=y CONFIG_PINMUX_SAM0=y -CONFIG_SPI=y diff --git a/boards/arm/atsamr21_xpro/pinmux.c b/boards/arm/atsamr21_xpro/pinmux.c index a66de2e00aa4..75cec73824db 100644 --- a/boards/arm/atsamr21_xpro/pinmux.c +++ b/boards/arm/atsamr21_xpro/pinmux.c @@ -15,37 +15,17 @@ static int board_pinmux_init(const struct device *dev) const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); const struct device *muxc = DEVICE_DT_GET(DT_NODELABEL(pinmux_c)); - __ASSERT_NO_MSG(device_is_ready(muxa)); - __ASSERT_NO_MSG(device_is_ready(muxb)); - __ASSERT_NO_MSG(device_is_ready(muxc)); - ARG_UNUSED(dev); -#if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM0 on RX=PA5, TX=PA4 */ - pinmux_pin_set(muxa, 4, PINMUX_FUNC_D); - pinmux_pin_set(muxa, 5, PINMUX_FUNC_D); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* NOTE: SERCOM3 UART is used by the UART driver tests */ - /* SERCOM3 on RX=PA22, TX=PA23 */ - pinmux_pin_set(muxa, 22, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 23, PINMUX_FUNC_C); -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if (ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && CONFIG_UART_SAM0) - /* SERCOM5 on RX=PA23, TX=PA22 */ - pinmux_pin_set(muxa, 22, PINMUX_FUNC_D); - pinmux_pin_set(muxa, 23, PINMUX_FUNC_D); -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } + if (!device_is_ready(muxc)) { + return -ENXIO; + } #if (ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_spi) && CONFIG_SPI_SAM0) #warning Pin mapping may not be configured @@ -114,4 +94,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/b_u585i_iot02a/Kconfig.board b/boards/arm/b_u585i_iot02a/Kconfig.board new file mode 100644 index 000000000000..2ef452a9fa50 --- /dev/null +++ b/boards/arm/b_u585i_iot02a/Kconfig.board @@ -0,0 +1,8 @@ +# B_U585I_IOT02A discovery kit configuration + +# Copyright (c) 2021 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_U585I_IOT02A + bool "STM32U585I IOT Discovery kit" + depends on SOC_STM32U585XX diff --git a/boards/arm/b_u585i_iot02a/Kconfig.defconfig b/boards/arm/b_u585i_iot02a/Kconfig.defconfig new file mode 100644 index 000000000000..61bfbadbba43 --- /dev/null +++ b/boards/arm/b_u585i_iot02a/Kconfig.defconfig @@ -0,0 +1,11 @@ +# B_U585I_IOT02A discovery kit board configuration + +# Copyright (c) 2021 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_B_U585I_IOT02A + +config BOARD + default "b_u585i_iot02a" + +endif # BOARD_B_U585I_IOT02A diff --git a/boards/arm/b_u585i_iot02a/arduino_r3_connector.dtsi b/boards/arm/b_u585i_iot02a/arduino_r3_connector.dtsi new file mode 100644 index 000000000000..9809f715e3ef --- /dev/null +++ b/boards/arm/b_u585i_iot02a/arduino_r3_connector.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 0 0>, /* A0 */ + <1 0 &gpioc 2 0>, /* A1 */ + <2 0 &gpioc 4 0>, /* A2 */ + <3 0 &gpioc 5 0>, /* A3 */ + <4 0 &gpioa 7 0>, /* A4 */ + <5 0 &gpiob 0 0>, /* A5 */ + <6 0 &gpioc 11 0>, /* D0 */ + <7 0 &gpioc 10 0>, /* D1 */ + <8 0 &gpiod 15 0>, /* D2 */ + <9 0 &gpiob 2 0>, /* D3 */ + <10 0 &gpioe 7 0>, /* D4 */ + <11 0 &gpioe 0 0>, /* D5 */ + <12 0 &gpiob 6 0>, /* D6 */ + <13 0 &gpiof 13 0>, /* D7 */ + <14 0 &gpioc 1 0>, /* D8 */ + <15 0 &gpioa 8 0>, /* D9 */ + <16 0 &gpioe 12 0>, /* D10 */ + <17 0 &gpioe 15 0>, /* D11 */ + <18 0 &gpioe 14 0>, /* D12 */ + <19 0 &gpioe 13 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi b/boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi new file mode 100644 index 000000000000..09e841189630 --- /dev/null +++ b/boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "arduino_r3_connector.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + green_led_1: led_1 { + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + label = "User LD7"; + }; + red_led_1: led_3 { + gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>; + label = "User LD6"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpioc 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_msis { + status = "okay"; + msi-range = <4>; + msi-pll-mode; +}; + +&pll1 { + div-m = <1>; + mul-n = <80>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_msis>; + status = "okay"; +}; + +&rcc { + clocks = <&pll1>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; + apb3-prescaler = <1>; +}; diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts b/boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts new file mode 100644 index 000000000000..5d2fff31f4ff --- /dev/null +++ b/boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "b_u585i_iot02a-common.dtsi" + +/ { + model = "STMicroelectronics B-U585I-IOT02A discovery kit"; + compatible = "st,b-u585i-iot02a"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + led0 = &green_led_1; + led1 = &red_led_1; + sw0 = &user_button; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + current-speed = <115200>; + status = "okay"; +}; diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a.yaml b/boards/arm/b_u585i_iot02a/b_u585i_iot02a.yaml new file mode 100644 index 000000000000..05d3ebf3083e --- /dev/null +++ b/boards/arm/b_u585i_iot02a/b_u585i_iot02a.yaml @@ -0,0 +1,10 @@ +identifier: b_u585i_iot02a +name: ST B_U585I_IOT02A Discovery kit +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 786 +flash: 2048 diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig b/boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig new file mode 100644 index 000000000000..5ad1d1d662d3 --- /dev/null +++ b/boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_STM32U5X=y +CONFIG_SOC_STM32U585XX=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable pinmux +CONFIG_PINMUX=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/b_u585i_iot02a/board.cmake b/boards/arm/b_u585i_iot02a/board.cmake new file mode 100644 index 000000000000..7cb5e5e89ad8 --- /dev/null +++ b/boards/arm/b_u585i_iot02a/board.cmake @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset=hw") +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset=hw") + +board_runner_args(openocd "--tcl-port=6666") +board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") +board_runner_args(openocd "--no-halt") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +# FIXME: openocd runner requires use of STMicro openocd fork. +# Check board documentation for more details. +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg b/boards/arm/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg new file mode 100644 index 000000000000..6fe7baa7faa8 Binary files /dev/null and b/boards/arm/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg differ diff --git a/boards/arm/b_u585i_iot02a/doc/index.rst b/boards/arm/b_u585i_iot02a/doc/index.rst new file mode 100644 index 000000000000..02256bff2b91 --- /dev/null +++ b/boards/arm/b_u585i_iot02a/doc/index.rst @@ -0,0 +1,295 @@ +.. _b_u585i_iot02a_board: + +ST B_U585I_IOT02A Discovery kit +############################### + +Overview +******** + +The B_U585I_IOT02A Discovery kit features an ARM Cortex-M33 based STM32U585AI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the B_U585I_IOT02A Discovery kit: + + +- STM32U585AII6Q microcontroller featuring 2 Mbyte of Flash memory, 786 Kbytes of RAM in UFBGA169 package +- 512-Mbit octal-SPI Flash memory, 64-Mbit octal-SPI PSRAM, 256-Kbit I2C EEPROM +- USB FS, Sink and Source power, 2.5 W power capability +- 802.11 b/g/n compliant Wi-Fi® module from MXCHIP +- Bluetooth Low Energy from STMicroelectronics +- MEMS sensors from STMicroelectronics + + - 2 digital microphones + - Relative humidity and temperature sensor + - 3-axis magnetometer + - 3D accelerometer and 3D gyroscope + - Pressure sensor, 260-1260 hPa absolute digital output barometer + - Time-of-flight and gesture-detection sensor + - Ambient-light sensor + +- 2 push-buttons (user and reset) +- 2 user LEDs + +- Flexible power supply options: + - ST-LINK/V3 + - USB Vbus + - External sources + + +.. image:: img/b-u585i-iot02a.jpg + :width: 426px + :align: center + :height: 33px + :alt: B_U585I_IOT02A Discovery kit + +More information about the board can be found at the `B U585I IOT02A Discovery kit website`_. + +Hardware +******** + +The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) + +- Security and cryptography + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure data storage with hardware unique key (HUK) + - Secure Firmware Update support with TF-M + - 2 AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - Active tampers + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + - Active tampers + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - Internal 48 MHz with clock recovery + +- Power management + + - Embedded regulator (LDO) + - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling + +- RTC with HW calendar and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 17 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5 x 16-bit general purpose + - 4x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- ART accelerator + + - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and + external memories: up to 160 MHz, MPU, 240 DMIPS and DSP + - 4-Kbyte data cache for external memories + +- Memories + + - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles + - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON + - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - 2 Octo-SPI memory interfaces + +- Rich analog peripherals (independent supply) + + - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling + - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 2 12-bit DAC, low-power sample and hold + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- Up to 22 communication interfaces + + - USB Type-C / USB power delivery controller + - USB OTG 2.0 full-speed controller + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) + - 1x FDCAN + - 2x SDMMC interface + - 16- and 4-channel DMA controllers, functional in Stop mode + - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with + sound-activity detection + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + +- Graphic features + + - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation + - 1 digital camera interface + +- Mathematical co-processor + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + + + +More information about STM32U585AI can be found here: + +- `STM32U585 on www.st.com`_ +- `STM32U585 reference manual`_ + + +Supported Features +================== + +The Zephyr b_u585i_iot02a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + + +The default configuration can be found in the defconfig file: + + ``boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig`` + + +Connections and IOs +=================== + +B_U585I_IOT02A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For mode details please refer to `B U585I IOT02A board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- LD1 : PH7 +- LD2 : PH6 +- user button : PC13 + +System Clock +------------ + +B_U585I_IOT02A Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +B_U585I_IOT02A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +B_U585I_IOT02A Discovery kit includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to B_U585I_IOT02A Discovery kit +------------------------------------------------------- + +Connect the B_U585I_IOT02A Discovery kit to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_u585i_iot02a + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +Debugging +========= + +STM32U5 support is not currently supported in openocd. As a temporary workaround, +user can use `STMicroelectronics customized version of OpenOCD`_ to debug the +the B_U585I_IOT02A Discovery kit. +For this you need to fetch this repo, checkout branch "openocd-cubeide-r3" and +build openocd following the instructions provided in the README of the project. +Then, build zephyr project indicating the openocd location in west build command. + +Here is an example for the :ref:`blinky-sample` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: b_u585i_iot02a + :gen-args: -DOPENOCD="/openocd/src/openocd" -DOPENOCD_DEFAULT_PATH="/openocd/tcl/" + :goals: build + +Then, indicate openocd as the chosen runner in flash and debug commands: + + + .. code-block:: console + + $ west flash -r openocd + $ west debug -r openocd + + +.. _B U585I IOT02A Discovery kit website: + https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html + +.. _B U585I IOT02A board User Manual: + https://www.st.com/resource/en/user_manual/um2839-discovery-kit-for-iot-node-with-stm32u5-series-stmicroelectronics.pdf + +.. _STM32U585 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html + +.. _STM32U585 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STMicroelectronics customized version of OpenOCD: + https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/b_u585i_iot02a/support/openocd.cfg b/boards/arm/b_u585i_iot02a/support/openocd.cfg new file mode 100644 index 000000000000..75d859aafa7a --- /dev/null +++ b/boards/arm/b_u585i_iot02a/support/openocd.cfg @@ -0,0 +1,44 @@ +source [find interface/stlink-dap.cfg] + +set WORKAREASIZE 0x8000 + +transport select "dapdirect_swd" + +set CHIPNAME STM32U575ZITxQ +set BOARDNAME B-U585I-IOT02A + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# STlink Debug clock frequency +set CLOCK_FREQ 8000 + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 + +# ACCESS PORT NUMBER +set AP_NUM 0 +# GDB PORT +set GDB_PORT 3333 + +# BCTM CPU variables + +source [find target/stm32u5x.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2.dts b/boards/arm/bbc_microbit_v2/bbc_microbit_v2.dts index 76ca47107eb5..c4f32bccc346 100644 --- a/boards/arm/bbc_microbit_v2/bbc_microbit_v2.dts +++ b/boards/arm/bbc_microbit_v2/bbc_microbit_v2.dts @@ -143,7 +143,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/bl5340_dvk/Kconfig.defconfig b/boards/arm/bl5340_dvk/Kconfig.defconfig index 5a7c3d6b587c..af74b2b350ab 100644 --- a/boards/arm/bl5340_dvk/Kconfig.defconfig +++ b/boards/arm/bl5340_dvk/Kconfig.defconfig @@ -87,15 +87,11 @@ config FLASH_LOAD_SIZE endif # BOARD_BL5340_DVK_CPUAPP_NS -if (BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS) && USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y +# Workaround for not being able to have commas in macro arguments +DT_COMPAT_TI_TCA9538 := ti,tca9538 -endif # (BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS) && USB +config I2C +default $(dt_compat_on_bus,$(DT_COMPAT_TI_TCA9538),i2c) endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts index a8fb213b9fcc..1ce826a09572 100644 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts +++ b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts @@ -21,7 +21,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dts index 9da32ef539f1..c648f6044e7d 100644 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dts +++ b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dts @@ -14,17 +14,66 @@ zephyr,bt-c2h-uart = &uart0; }; + /* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */ + /* Note TCA9538 does not have configurable internal pull ups/ downs */ buttons { compatible = "gpio-keys"; boot_button0: boot_button { gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - label = "Bootloader button S4"; + label = "Bootloader button (S4)"; + }; + + button1: button_1 { + gpios = <&gpio_exp0 0 GPIO_ACTIVE_LOW>; + label = "Push button switch 1 (S1)"; + }; + + button2: button_2 { + gpios = <&gpio_exp0 1 GPIO_ACTIVE_LOW>; + label = "Push button switch 2 (S2)"; + }; + + button3: button_3 { + gpios = <&gpio_exp0 2 GPIO_ACTIVE_LOW>; + label = "Push button switch 3 (S9)"; + }; + + button4: button_4 { + gpios = <&gpio_exp0 3 GPIO_ACTIVE_LOW>; + label = "Push button switch 4 (S10)"; + }; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio_exp0 4 GPIO_ACTIVE_LOW>; + label = "Blue LED 1"; + }; + led2: led_2 { + gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>; + label = "Blue LED 2"; + }; + led3: led_3 { + gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>; + label = "Blue LED 3"; + }; + led4: led_4 { + gpios = <&gpio_exp0 7 GPIO_ACTIVE_LOW>; + label = "Blue LED 4"; }; }; /* These aliases are provided for compatibility with samples */ aliases { - sw0 = &boot_button0; + led0 = &led1; + led1 = &led2; + led2 = &led3; + led3 = &led4; + sw0 = &button1; + sw1 = &button2; + sw2 = &button3; + sw3 = &button4; }; }; @@ -86,6 +135,22 @@ label = "dac0"; #io-channel-cells = <1>; }; + + extrtc0: mcp7940n@6f { + compatible = "microchip,mcp7940n"; + reg = <0x6f>; + label = "mcp7940n"; + }; + + gpio_exp0: tca9538@70 { + compatible = "ti,tca9538"; + reg = <0x70>; + label = "tca9538"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + nint-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; }; &spi2 { diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig index 58de68f03fe3..4084c3750ccf 100644 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig +++ b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig @@ -13,12 +13,18 @@ CONFIG_HW_STACK_PROTECTION=y # Enable TrustZone-M CONFIG_ARM_TRUSTZONE_M=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y # Enable uart driver CONFIG_SERIAL=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y + +# Setup clocks +CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y +CONFIG_SOC_LFXO_CAP_INT_7PF=y +CONFIG_SOC_HFXO_CAP_INTERNAL=y +CONFIG_SOC_HFXO_CAP_INT_VALUE_X2=27 diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts index 2c9fe850d97a..612167fac7be 100644 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts +++ b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts @@ -19,7 +19,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/bl653_dvk/Kconfig.defconfig b/boards/arm/bl653_dvk/Kconfig.defconfig index 4c9b61430e7a..d1c9e1330401 100644 --- a/boards/arm/bl653_dvk/Kconfig.defconfig +++ b/boards/arm/bl653_dvk/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_BL653_DVK config BOARD default "bl653_dvk" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config IEEE802154_NRF5 default y depends on IEEE802154 diff --git a/boards/arm/bl653_dvk/bl653_dvk.dts b/boards/arm/bl653_dvk/bl653_dvk.dts index 753c5be46e8a..490c2e98c4b1 100644 --- a/boards/arm/bl653_dvk/bl653_dvk.dts +++ b/boards/arm/bl653_dvk/bl653_dvk.dts @@ -155,7 +155,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/bl654_dvk/Kconfig.defconfig b/boards/arm/bl654_dvk/Kconfig.defconfig index 12ef2bd1048f..14937622f48d 100644 --- a/boards/arm/bl654_dvk/Kconfig.defconfig +++ b/boards/arm/bl654_dvk/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_BL654_DVK config BOARD default "bl654_dvk" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/bl654_dvk/bl654_dvk.dts b/boards/arm/bl654_dvk/bl654_dvk.dts index 886ead197c01..280c52d3dec4 100644 --- a/boards/arm/bl654_dvk/bl654_dvk.dts +++ b/boards/arm/bl654_dvk/bl654_dvk.dts @@ -182,7 +182,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig b/boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig index bf6bb2f6391b..de461af7c7b0 100644 --- a/boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig +++ b/boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig @@ -7,15 +7,19 @@ CONFIG_BOARD_BL654_SENSOR_BOARD=y # Enable MPU CONFIG_ARM_MPU=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y -# enable uart driver +# Enable uart driver CONFIG_SERIAL=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# additional board options +# Additional board options CONFIG_GPIO_AS_PINRESET=y + +# 32KHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y diff --git a/boards/arm/bl654_usb/Kconfig b/boards/arm/bl654_usb/Kconfig new file mode 100644 index 000000000000..a445fd15f5e8 --- /dev/null +++ b/boards/arm/bl654_usb/Kconfig @@ -0,0 +1,10 @@ +# BL654 USB adapter board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "Enable DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_BL654_USB diff --git a/boards/arm/bl654_usb/Kconfig.board b/boards/arm/bl654_usb/Kconfig.board new file mode 100644 index 000000000000..49f4dc67fad1 --- /dev/null +++ b/boards/arm/bl654_usb/Kconfig.board @@ -0,0 +1,8 @@ +# BL654 USB adapter board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL654_USB + bool "BL654 USB" + depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bl654_usb/Kconfig.defconfig b/boards/arm/bl654_usb/Kconfig.defconfig new file mode 100644 index 000000000000..56125667cbb3 --- /dev/null +++ b/boards/arm/bl654_usb/Kconfig.defconfig @@ -0,0 +1,46 @@ +# BL654 USB adapter board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL654_USB + +config BOARD + default "bl654_usb" + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# so no override is necessary. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on !USE_DT_CODE_PARTITION + +if USB_DEVICE_STACK + +config USB_UART_CONSOLE + default y + +config UART_LINE_CTRL + default y + +endif # USB_DEVICE_STACK + +if IEEE802154 + +config IEEE802154_NRF5 + default y + +endif # IEEE802154 + +config BT_CTLR + default BT + +endif # BOARD_BL654_USB diff --git a/boards/arm/bl654_usb/bl654_usb.dts b/boards/arm/bl654_usb/bl654_usb.dts new file mode 100644 index 000000000000..0f2c1acbb6b5 --- /dev/null +++ b/boards/arm/bl654_usb/bl654_usb.dts @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + model = "Laird Connectivity BL654 USB adapter"; + compatible = "lairdconnect,bl654_usb"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &bl654_cdc_acm_uart; + zephyr,shell-uart = &bl654_cdc_acm_uart; + zephyr,bt-c2h-uart = &bl654_cdc_acm_uart; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Blue LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + led1bluepwm: led_pwm_1 { + pwms = <&pwm0 13>; + label = "PWM LED 1 Blue"; + }; + + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1pwm = &led1bluepwm; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&pwm0 { + status = "okay"; + ch0-pin = <13>; +}; + +&flash0 { + /* + * For more information, see: + * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* MCUboot placed after Nordic MBR. + * The size of this partition ensures that MCUBoot + * can be built with CDC ACM support and w/o optimizations. + */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x000f000>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00005e000>; + }; + slot1_partition: partition@6e000 { + label = "image-1"; + reg = <0x006e000 0x00005e000>; + }; + storage_partition: partition@cc000 { + label = "storage"; + reg = <0x000cc000 0x00008000>; + }; + scratch_partition: partition@d4000 { + label = "image-scratch"; + reg = <0x000d4000 0x0000C000>; + }; + + /* Nordic nRF5 bootloader <0xe0000 0x1c000> + * + * In addition, the last and second last flash pages + * are used by the nRF5 bootloader and MBR to store settings. + */ + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; + + bl654_cdc_acm_uart: bl654_cdc_acm_uart { + compatible = "zephyr,cdc-acm-uart"; + label = "CDC_ACM_0"; + }; +}; diff --git a/boards/arm/bl654_usb/bl654_usb.yaml b/boards/arm/bl654_usb/bl654_usb.yaml new file mode 100644 index 000000000000..436566b935f7 --- /dev/null +++ b/boards/arm/bl654_usb/bl654_usb.yaml @@ -0,0 +1,16 @@ +identifier: bl654_usb +name: BL654_USB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - usb_device + - usb_cdc + - ble + - ieee802154 + - pwm + - watchdog + - counter diff --git a/boards/arm/bl654_usb/bl654_usb_defconfig b/boards/arm/bl654_usb/bl654_usb_defconfig new file mode 100644 index 000000000000..6e326fbaf0a0 --- /dev/null +++ b/boards/arm/bl654_usb/bl654_usb_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_NRF52X=y +CONFIG_SOC_NRF52840_QIAA=y +CONFIG_BOARD_BL654_USB=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y + +# Additional board options +CONFIG_GPIO_AS_PINRESET=y + +# 32KHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y diff --git a/boards/arm/bl654_usb/doc/bl654_usb.rst b/boards/arm/bl654_usb/doc/bl654_usb.rst new file mode 100644 index 000000000000..3a2620340b1e --- /dev/null +++ b/boards/arm/bl654_usb/doc/bl654_usb.rst @@ -0,0 +1,194 @@ +.. _bl654_usb: + +Laird Connectivity BL654 USB (451-00004) +######################################## + +Overview +******** + +The BL654 USB adapter hardware (Laird Connectivity part 451-00004) provides +support for the Laird Connectivity BL654 module powered by a Nordic +Semiconductor nRF52840 ARM Cortex-M4F CPU. + +This USB adapter has the following features: + +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`RTC (nRF RTC System Clock)` + +.. figure:: img/bl654_usb.jpg + :width: 500px + :align: center + :alt: BL654 USB adapter + + BL654 USB Adapter + +.. figure:: img/bl654_usb_pcb.jpg + :width: 500px + :align: center + :alt: 451-00004 Box Contents + + BL654 USB Adapter PCB + +More information about the BL654 USB adapter can be found on the `BL654 USB +Dongle Quick Start Guide`_. There is more information on the BL654 range on +the `BL654 website`_. + +Hardware +******** + +Supported Features +================== + +The BL654 USB board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not supported by the Zephyr kernel. +See `BL654 website`_ +for a complete list of BL654 USB adapter hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (blue) = P0.13 + +Push buttons +------------ + +* RESET = SW1 = nReset + +Serial Port +=========== + +Zephyr console output is available as follows: + +- using the USB connector, which may be used to make the console available on PC as + USB CDC class. + +Programming and Debugging +************************* + +Applications for the ``bl654_usb`` board configuration can be +built in the usual way (see :ref:`build_an_application` for more details). The +``bl654_usb`` board cannot be used for debugging. The compatible BL654_DVK +board can be used for development. Documentation can be found at the `BL654_DVK +Zephyr site`_ and :zephyr_file:`boards/arm/bl654_dvk/doc/bl654_dvk.rst` + +Flashing +======== + +The board supports programming using the built-in bootloader. + +The board is factory-programmed with a Laird Connectivity variation of Nordic's +open bootloader from Nordic's nRF5x SDK. With this option, you'll use +Nordic's `nrfutil`_ program to create firmware packages supported by this +bootloader and flash them to the device. Make sure ``nrfutil`` is installed +before proceeding. These instructions were tested with version 6.1.0. + +#. With the adapter plugged in, reset the board into the bootloader by pressing +the RESET button. + + The push button is in a pin-hole on the logo side of the USB adapter. + + .. image:: img/bl654_usb_reset.jpg + :width: 500px + :align: center + :alt: Location of RESET button + + The blue LED should start a fade pattern, signalling the bootloader is + running. + +#. Compile a Zephyr application; we'll use :ref:`blinky `. + + .. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: bl654_usb + :goals: build + +#. Package the application for the bootloader using ``nrfutil``: + + .. code-block:: console + + nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ + --application build/zephyr/zephyr.hex \ + --application-version 1 blinky.zip + +#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be + something like ``COMx`` on Windows, and something else on macOS. + + .. code-block:: console + + nrfutil dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0 + + When this command exits, observe the blue LED on the board blinking. + + +Testing Bluetooth on the BL654 USB +*********************************** +Many of the Bluetooth examples will work on the BL654 USB. +Try them out: + +* :ref:`ble_peripheral` +* :ref:`bluetooth-eddystone-sample` +* :ref:`bluetooth-ibeacon-sample` + + +Testing the LED on the BL654 USB +************************************************ + +There is a sample that allows you to test that the LED on +the board is working properly with Zephyr: + +* :ref:`blinky-sample` + +You can build and flash the example to make sure Zephyr is running correctly on +your board. The LED definitions can be found in +:zephyr_file:`boards/arm/bl654_usb/bl654_usb.dts`. + + +References +********** + +.. target-notes:: + +.. _BL654 USB Dongle Quick Start Guide: https://www.lairdconnect.com/documentation/user-guide-bl654-usb-nordic-sdk-zephyr +.. _BL654 website: https://connectivity.lairdtech.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl654-series +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _Creating a secure bootloader image: https://www.lairdconnect.com/documentation/application-note-creating-secure-bootloader-image-bl654-usb +.. _nrfutil: https://github.com/NordicSemiconductor/pc-nrfutil +.. _BL654_DVK Zephyr site: https://docs.zephyrproject.org/latest/boards/arm/bl654_dvk/doc/bl654_dvk.html diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb.jpg b/boards/arm/bl654_usb/doc/img/bl654_usb.jpg new file mode 100644 index 000000000000..d05af0ead275 Binary files /dev/null and b/boards/arm/bl654_usb/doc/img/bl654_usb.jpg differ diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb_pcb.jpg b/boards/arm/bl654_usb/doc/img/bl654_usb_pcb.jpg new file mode 100644 index 000000000000..879254326ce5 Binary files /dev/null and b/boards/arm/bl654_usb/doc/img/bl654_usb_pcb.jpg differ diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb_reset.jpg b/boards/arm/bl654_usb/doc/img/bl654_usb_reset.jpg new file mode 100644 index 000000000000..bdcb58d1eea4 Binary files /dev/null and b/boards/arm/bl654_usb/doc/img/bl654_usb_reset.jpg differ diff --git a/boards/arm/bt510/bt510_defconfig b/boards/arm/bt510/bt510_defconfig index f97b87430efd..bdc992253584 100644 --- a/boards/arm/bt510/bt510_defconfig +++ b/boards/arm/bt510/bt510_defconfig @@ -10,13 +10,13 @@ CONFIG_ARM_MPU=y # Enable RTT CONFIG_USE_SEGGER_RTT=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y -# enable uart driver +# Enable uart driver CONFIG_SERIAL=y -# enable accelerometer & temperature sensor +# Enable accelerometer & temperature sensor CONFIG_I2C=y CONFIG_SENSOR=y CONFIG_LIS2DH=y @@ -24,17 +24,17 @@ CONFIG_LIS2DH_TRIGGER_GLOBAL_THREAD=y CONFIG_LIS2DH_OPER_MODE_LOW_POWER=y CONFIG_SI7055=y -# enable magnetoresistive driver +# Enable magnetoresistive driver CONFIG_SM351LT=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_RTT_CONSOLE=y -# additional board options +# Additional board options CONFIG_GPIO_AS_PINRESET=y -# 32kHz clock source +# 32KHz clock source CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_20PPM=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y diff --git a/boards/arm/bt6x0/Kconfig.defconfig b/boards/arm/bt6x0/Kconfig.defconfig index cc5682b747a3..6e9c4544d3c8 100644 --- a/boards/arm/bt6x0/Kconfig.defconfig +++ b/boards/arm/bt6x0/Kconfig.defconfig @@ -15,4 +15,10 @@ config IEEE802154_NRF5 config BT_CTLR default BT +# Workaround for not being able to have commas in macro arguments +DT_COMPAT_TI_TCA9538 := ti,tca9538 + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_TI_TCA9538),i2c) + endif # BOARD_BT6X0 diff --git a/boards/arm/bt6x0/bt6x0.dts b/boards/arm/bt6x0/bt6x0.dts index fdb871f1d695..47c7ec964641 100644 --- a/boards/arm/bt6x0/bt6x0.dts +++ b/boards/arm/bt6x0/bt6x0.dts @@ -141,6 +141,46 @@ label = "Digital Output 2"; gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; }; + + ain1sel: ain_1_current_measurement_selection { + label = "Analogue Input 1 Current/Voltage measurement select"; + gpios = <&gpio_exp0 0 GPIO_ACTIVE_HIGH>; + }; + + ain2sel: ain_2_current_measurement_selection { + label = "Analogue Input 2 Current/Voltage measurement select"; + gpios = <&gpio_exp0 1 GPIO_ACTIVE_HIGH>; + }; + + ain3sel: ain_3_current_measurement_selection { + label = "Analogue Input 3 Current/Voltage measurement select"; + gpios = <&gpio_exp0 2 GPIO_ACTIVE_HIGH>; + }; + + ain4sel: ain_4_current_measurement_selection { + label = "Analogue Input 4 Current/Voltage measurement select"; + gpios = <&gpio_exp0 3 GPIO_ACTIVE_HIGH>; + }; + + aina0: analog_input_selection_0 { + label = "Analogue Input Mux 0"; + gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>; + }; + + aina1: analog_input_selection_1 { + label = "Analogue Input Mux 1"; + gpios = <&gpio_exp0 5 GPIO_ACTIVE_HIGH>; + }; + + aux1: aux_input_1 { + label = "Aux Input 1"; + gpios = <&gpio_exp0 6 GPIO_ACTIVE_HIGH>; + }; + + aux2: aux_input_2 { + label = "Aux Input 2"; + gpios = <&gpio_exp0 7 GPIO_ACTIVE_HIGH>; + }; }; /* These aliases are provided for compatibility with samples */ @@ -206,6 +246,16 @@ status = "okay"; sda-pin = <26>; scl-pin = <27>; + + gpio_exp0: tca9538@70 { + compatible = "ti,tca9538"; + reg = <0x70>; + label = "tca9538"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + nint-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; }; &spi1 { diff --git a/boards/arm/bt6x0/bt6x0_defconfig b/boards/arm/bt6x0/bt6x0_defconfig index f6b801f740a9..a92c3d7986ac 100644 --- a/boards/arm/bt6x0/bt6x0_defconfig +++ b/boards/arm/bt6x0/bt6x0_defconfig @@ -7,23 +7,23 @@ CONFIG_BOARD_BT6X0=y # Enable MPU CONFIG_ARM_MPU=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y CONFIG_NFCT_PINS_AS_GPIOS=y -# enable uart driver +# Enable uart driver CONFIG_SERIAL=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# additional board options +# Additional board options CONFIG_GPIO_AS_PINRESET=y -# 32kHz clock source -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_20PPM=y - # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y + +# 32KHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag.dts b/boards/arm/cc1352r_sensortag/cc1352r_sensortag.dts index b69b8a03484c..5c21d8277b5a 100644 --- a/boards/arm/cc1352r_sensortag/cc1352r_sensortag.dts +++ b/boards/arm/cc1352r_sensortag/cc1352r_sensortag.dts @@ -31,7 +31,7 @@ sw1 = &btn1; sensor0 = &sensor0; sensor1 = &sensor1; - /* TODO: add support for hdc2080 */ + sensor2 = &sensor2; }; chosen { @@ -116,7 +116,12 @@ label = "OPT3001"; }; - /* TODO: add hdc2080 at 0x41 */ + sensor2: sensor@41 { + compatible = "ti,hdc2080"; + reg = <0x41>; + label = "HDC2080"; + int-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; }; &spi0 { diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dts b/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dts index b8696b9476df..b7a4e68a65a2 100644 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dts +++ b/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dts @@ -122,7 +122,8 @@ compatible = "st,lis2dh"; label = "LIS2DH"; reg = <0x18>; - irq-gpios = <&gpio0 29 0>; + irq-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + disconnect-sdo-sa0-pull-up; }; }; @@ -227,7 +228,7 @@ io-channels = <&adc 7>; output-ohms = <100000>; full-ohms = <(100000 + 100000)>; - power-gpios = <&gpio0 25 0>; + power-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; }; }; diff --git a/boards/arm/contextualelectronics_abc/Kconfig.defconfig b/boards/arm/contextualelectronics_abc/Kconfig.defconfig index 5465a207a7d0..da35c9e482ab 100644 --- a/boards/arm/contextualelectronics_abc/Kconfig.defconfig +++ b/boards/arm/contextualelectronics_abc/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_CONTEXTELEC_ABC config BOARD default "nrf52840_ble_cell" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/degu_evk/Kconfig.defconfig b/boards/arm/degu_evk/Kconfig.defconfig index 2895ce1741bf..8728d10f8443 100644 --- a/boards/arm/degu_evk/Kconfig.defconfig +++ b/boards/arm/degu_evk/Kconfig.defconfig @@ -8,13 +8,7 @@ if BOARD_DEGU_EVK config BOARD default "degu_evk" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y +if USB_DEVICE_STACK config USB_DEVICE_PRODUCT default "Degu Evaluation Kit" @@ -28,13 +22,7 @@ config UART_INTERRUPT_DRIVEN config UART_LINE_CTRL default y -config UART_CONSOLE_ON_DEV_NAME - default "CDC_ACM_0" - -config UART_SHELL_ON_DEV_NAME - default "CDC_ACM_0" - -endif # USB +endif # USB_DEVICE_STACK if DISK_DRIVER_FLASH diff --git a/boards/arm/degu_evk/degu_evk.dts b/boards/arm/degu_evk/degu_evk.dts index 992109bae3d8..33c46616d5cd 100644 --- a/boards/arm/degu_evk/degu_evk.dts +++ b/boards/arm/degu_evk/degu_evk.dts @@ -14,6 +14,8 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,console = °u_cdc_acm_uart; + zephyr,shell-uart = °u_cdc_acm_uart; zephyr,code-partition = &slot0_partition; }; @@ -138,7 +140,12 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; + + degu_cdc_acm_uart: degu_cdc_acm_uart { + compatible = "zephyr,cdc-acm-uart"; + label = "CDC_ACM_0"; + }; }; diff --git a/boards/arm/degu_evk/degu_evk_defconfig b/boards/arm/degu_evk/degu_evk_defconfig index 4230d390f9bd..00b41ff6b81e 100644 --- a/boards/arm/degu_evk/degu_evk_defconfig +++ b/boards/arm/degu_evk/degu_evk_defconfig @@ -12,6 +12,9 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y +# enable USB +CONFIG_USB_DEVICE_STACK=y + # additional board options CONFIG_GPIO=y CONFIG_GPIO_AS_PINRESET=y @@ -21,6 +24,3 @@ CONFIG_I2C=y # ADC CONFIG_ADC=y - -# USB -CONFIG_USB=y diff --git a/boards/arm/dragino_nbsn95/Kconfig.board b/boards/arm/dragino_nbsn95/Kconfig.board new file mode 100644 index 000000000000..e308ae652875 --- /dev/null +++ b/boards/arm/dragino_nbsn95/Kconfig.board @@ -0,0 +1,8 @@ +# Dragino NBSN95 NB-IoT Sensor Node board configuration + +# Copyright (c) 2021 Next Big Thing AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DRAGINO_NBSN95 + bool "Dragino NBSN95 Sensor Node" + depends on SOC_STM32L072XX diff --git a/boards/arm/dragino_nbsn95/Kconfig.defconfig b/boards/arm/dragino_nbsn95/Kconfig.defconfig new file mode 100644 index 000000000000..0dbadb732d0e --- /dev/null +++ b/boards/arm/dragino_nbsn95/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Dragino NBSN95 NB-IoT Sensor Node board configuration + +# Copyright (c) 2021 Next Big Thing AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DRAGINO_NBSN95 + +config BOARD + default "dragino_nbsn95" + +endif # BOARD_DRAGINO_NBSN95 diff --git a/boards/arm/dragino_nbsn95/board.cmake b/boards/arm/dragino_nbsn95/board.cmake new file mode 100644 index 000000000000..ef270a0abc87 --- /dev/null +++ b/boards/arm/dragino_nbsn95/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=STM32L072CZ" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/dragino_nbsn95/doc/img/dragino_nbsn95.png b/boards/arm/dragino_nbsn95/doc/img/dragino_nbsn95.png new file mode 100644 index 000000000000..1c5ac11493f2 Binary files /dev/null and b/boards/arm/dragino_nbsn95/doc/img/dragino_nbsn95.png differ diff --git a/boards/arm/dragino_nbsn95/doc/index.rst b/boards/arm/dragino_nbsn95/doc/index.rst new file mode 100644 index 000000000000..989928867532 --- /dev/null +++ b/boards/arm/dragino_nbsn95/doc/index.rst @@ -0,0 +1,195 @@ +.. _dragino_nbsn95_board: + +Dragino NBSN95 NB-IoT Sensor Node +################################# + +Overview +******** + +The Dragino NBSN95 NB-IoT Sensor Node for IoT allows users to develop +applications with NB-IoT connectivity via the Quectel BC95-G. +Dragino NBSN95 enables a wide diversity of applications by exploiting +low-power communication, ARM |reg| Cortex |reg|-M0 core-based +STM32L0 Series features. + +This kit provides: + +- STM32L072CZ MCU +- Quectel BC95-G NB-IoT +- Expansion connectors: + - PMOD +- Li/SOCI2 Unchargable Battery +- GPIOs exposed via screw terminals on the carrier board +- Housing + +.. image:: img/dragino_nbsn95.png + :width: 531px + :align: center + :height: 354px + :alt: Dragino NBSN95 + +More information about the board can be found at the `Dragino NBSN95 website`_. + +Hardware +******** + +The STM32L072CZ SoC provides the following hardware IPs: + +- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz +- Clock Sources: + + - 1 to 32 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal multispeed low-power 65 kHz to 4.2 MHz RC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 2x 16-bit with up to 4 channels + - 2x 16-bit with up to 2 channels + - 1x 16-bit ultra-low-power timer + - 1x SysTick + - 1x RTC + - 2x 16-bit basic for DAC + - 2x watchdogs (independent/window) +- Up to 84 fast I/Os, most 5 V-tolerant. +- Memories + + - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 20 KB of SRAM + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 1.14 MSPS + - 2x 12-bit DAC + - 2x ultra-low-power comparators +- 11x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 6x SPIs (4x SPIs with the Quad SPI) +- 7-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L072CZ can be found here: + + - `STM32L072CZ on www.st.com`_ + - `STM32L0x2 reference manual`_ + +Supported Features +================== + +The Zephyr Dragino NBSN95 Board board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + ``boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig`` + + +Connections and IOs +=================== + +Dragino NBSN95 Board has GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `Dragino NBSN95 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 + +System Clock +------------ + +Dragino NBSN95 System Clock is at 32MHz, + +Serial Port +----------- + +Dragino NBSN95 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``dragino_nbsn95`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Dragino NBSN95 board requires an external debugger. + +Flashing an application to Dragino NBSN95 +----------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the Dragino NBSN95 to a STLinkV2 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_nbsn95 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! dragino_nbsn95 + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_nbsn95 + :maybe-skip-config: + :goals: debug + +.. _Dragino NBSN95 website: + https://www.dragino.com/products/nb-iot/item/163-nbsn95.html + +.. _STM32L072CZ on www.st.com: + http://www.st.com/en/microcontrollers/stm32l072cz.html + +.. _STM32L0x2 reference manual: + http://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95.dts b/boards/arm/dragino_nbsn95/dragino_nbsn95.dts new file mode 100644 index 000000000000..171a4158c392 --- /dev/null +++ b/boards/arm/dragino_nbsn95/dragino_nbsn95.dts @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Next Big Thing AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "Dragino NBSN95 NB-IoT Sensor Node"; + compatible = "vendor,dragino"; + + chosen { + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + green_led: led { + gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + }; + + aliases { + led0 = &green_led; + }; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + div = <2>; + mul = <4>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + current-speed = <115200>; + status = "okay"; +}; diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95.yaml b/boards/arm/dragino_nbsn95/dragino_nbsn95.yaml new file mode 100644 index 000000000000..f614987d58d9 --- /dev/null +++ b/boards/arm/dragino_nbsn95/dragino_nbsn95.yaml @@ -0,0 +1,13 @@ +identifier: dragino_nbsn95 +name: Dragino NBSN95 NB-IoT Sensor Node +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 20 +flash: 192 +testing: + ignore_tags: + - net diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig b/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig new file mode 100644 index 000000000000..8b8cbb939c3e --- /dev/null +++ b/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Zephyr Kernel Configuration +CONFIG_SOC_SERIES_STM32L0X=y + +# Platform Configuration +CONFIG_SOC_STM32L072XX=y +CONFIG_BOARD_DRAGINO_NBSN95=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Pinmux Driver +CONFIG_PINMUX=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/dragino_nbsn95/support/openocd.cfg b/boards/arm/dragino_nbsn95/support/openocd.cfg new file mode 100644 index 000000000000..dcd0568516fd --- /dev/null +++ b/boards/arm/dragino_nbsn95/support/openocd.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 Next Big Thing AG + +source [find interface/stlink.cfg] + +transport select hla_swd + +set WORKAREASIZE 0x2000 + +source [find target/stm32l0_dual_bank.cfg] + +# There is only system reset line and JTAG/SWD command can be issued when SRST +reset_config srst_only + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts b/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts index e116b69bba6d..0a4c577202c6 100644 --- a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts +++ b/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts @@ -15,6 +15,7 @@ aliases { led0 = &led0; led1 = &led1; + pwm-led0 = &pwm_led0; sw0 = &button0; sw1 = &button1; watchdog0 = &wdog0; @@ -53,6 +54,14 @@ label = "User Push Button 1"; }; }; + + pwmleds { + compatible = "pwm-leds"; + status = "okay"; + pwm_led0: pwm_led0 { + pwms = <&pwm0 0 PWM_POLARITY_NORMAL>; + }; + }; }; &cpu0 { @@ -141,6 +150,16 @@ status = "okay"; }; +&timer0 { + status = "okay"; + + pwm0: pwm { + status = "okay"; + pin-location = ; + prescaler = <1024>; + }; +}; + &gpio { location-swo = <0>; status = "okay"; diff --git a/boards/arm/frdm_k22f/frdm_k22f.dts b/boards/arm/frdm_k22f/frdm_k22f.dts index 6327e4c49a4a..65ec0bcaef77 100644 --- a/boards/arm/frdm_k22f/frdm_k22f.dts +++ b/boards/arm/frdm_k22f/frdm_k22f.dts @@ -166,7 +166,7 @@ arduino_spi: &spi0 { pinctrl-0 = <&UART2_RX_PTD2 &UART2_TX_PTD3>; }; -&usbotg { +zephyr_udc0: &usbotg { compatible = "nxp,kinetis-usbd"; status = "okay"; num-bidir-endpoints = <8>; diff --git a/boards/arm/frdm_k64f/frdm_k64f.dts b/boards/arm/frdm_k64f/frdm_k64f.dts index 42799dc27442..f8b143a95ba2 100644 --- a/boards/arm/frdm_k64f/frdm_k64f.dts +++ b/boards/arm/frdm_k64f/frdm_k64f.dts @@ -161,7 +161,7 @@ arduino_spi: &spi0 { pinctrl-0 = <&UART2_RTS_b_PTD0 &UART2_CTS_b_PTD1 &UART2_RX_PTD2 &UART2_TX_PTD3>; }; -&usbotg { +zephyr_udc0: &usbotg { compatible = "nxp,kinetis-usbd"; status = "okay"; num-bidir-endpoints = <8>; diff --git a/boards/arm/frdm_k64f/frdm_k64f.yaml b/boards/arm/frdm_k64f/frdm_k64f.yaml index 3d592953934f..25e4a087b960 100644 --- a/boards/arm/frdm_k64f/frdm_k64f.yaml +++ b/boards/arm/frdm_k64f/frdm_k64f.yaml @@ -2,6 +2,8 @@ identifier: frdm_k64f name: NXP FRDM-K64F type: mcu arch: arm +ram: 256 +flash: 1024 toolchain: - zephyr - gnuarmemb diff --git a/boards/arm/frdm_k82f/frdm_k82f.dts b/boards/arm/frdm_k82f/frdm_k82f.dts index ebc80b608614..1d053230ed3f 100644 --- a/boards/arm/frdm_k82f/frdm_k82f.dts +++ b/boards/arm/frdm_k82f/frdm_k82f.dts @@ -217,7 +217,7 @@ }; }; -&usbotg { +zephyr_udc0: &usbotg { status = "okay"; }; diff --git a/boards/arm/frdm_kl25z/frdm_kl25z.dts b/boards/arm/frdm_kl25z/frdm_kl25z.dts index 1d4f0fbd04b1..79968fb17f65 100644 --- a/boards/arm/frdm_kl25z/frdm_kl25z.dts +++ b/boards/arm/frdm_kl25z/frdm_kl25z.dts @@ -134,7 +134,7 @@ status = "okay"; }; -&usbotg { +zephyr_udc0: &usbotg { compatible = "nxp,kinetis-usbd"; status = "okay"; num-bidir-endpoints = <8>; diff --git a/boards/arm/hexiwear_k64/hexiwear_k64.dts b/boards/arm/hexiwear_k64/hexiwear_k64.dts index 6225ad50929c..3c19da4876fb 100644 --- a/boards/arm/hexiwear_k64/hexiwear_k64.dts +++ b/boards/arm/hexiwear_k64/hexiwear_k64.dts @@ -89,7 +89,7 @@ max30101@57 { status = "disabled"; - compatible = "max,max30101"; + compatible = "maxim,max30101"; reg = <0x57>; label = "MAX30101"; }; diff --git a/boards/arm/ip_k66f/linker.ld b/boards/arm/ip_k66f/linker.ld index b8aa54b678b6..9a620d509b2f 100644 --- a/boards/arm/ip_k66f/linker.ld +++ b/boards/arm/ip_k66f/linker.ld @@ -38,8 +38,8 @@ SECTION_DATA_PROLOGUE(net_if_area,,SUBALIGN(4)) \ KEEP(*(SORT_BY_NAME(._net_if.static.*))); \ _net_if_list_end = .; \ } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) \ -Z_ITERABLE_SECTION_RAM(net_if_dev, 4) \ -Z_ITERABLE_SECTION_RAM(net_l2, 4) \ -Z_ITERABLE_SECTION_RAM(eth_bridge, 4) +ITERABLE_SECTION_RAM(net_if_dev, 4) \ +ITERABLE_SECTION_RAM(net_l2, 4) \ +ITERABLE_SECTION_RAM(eth_bridge, 4) #include diff --git a/boards/arm/legend/Kconfig.board b/boards/arm/legend/Kconfig.board new file mode 100644 index 000000000000..6820a8c0dcd6 --- /dev/null +++ b/boards/arm/legend/Kconfig.board @@ -0,0 +1,8 @@ +# Legend board family configuration + +# Copyright (c) 2021 Seagate Technology +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LEGEND + bool "Legend board" + depends on SOC_STM32F070XB diff --git a/boards/arm/legend/Kconfig.defconfig b/boards/arm/legend/Kconfig.defconfig new file mode 100644 index 000000000000..06c47f232fd8 --- /dev/null +++ b/boards/arm/legend/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Legend board family configuration + +# Copyright (c) 2021, Seagate Technology LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LEGEND + +config BOARD + default "legend" + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_LEGEND diff --git a/boards/arm/legend/board.cmake b/boards/arm/legend/board.cmake new file mode 100644 index 000000000000..f154f6bc8fac --- /dev/null +++ b/boards/arm/legend/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=STM32F070CB" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/legend/doc/img/firecuda_gaming_hard_drive.png b/boards/arm/legend/doc/img/firecuda_gaming_hard_drive.png new file mode 100644 index 000000000000..d307b4233394 Binary files /dev/null and b/boards/arm/legend/doc/img/firecuda_gaming_hard_drive.png differ diff --git a/boards/arm/legend/doc/img/firecuda_gaming_hub.png b/boards/arm/legend/doc/img/firecuda_gaming_hub.png new file mode 100644 index 000000000000..ea56212b05ae Binary files /dev/null and b/boards/arm/legend/doc/img/firecuda_gaming_hub.png differ diff --git a/boards/arm/legend/doc/index.rst b/boards/arm/legend/doc/index.rst new file mode 100644 index 000000000000..55204f7dbc4b --- /dev/null +++ b/boards/arm/legend/doc/index.rst @@ -0,0 +1,141 @@ +.. _legend: + +Legend +###### + +Overview +******** +The Legend board family contains three revisions: 25hdd, 25ssd, and 35. + +The Legend 2.5" HDD board (revision 25hdd) can be found in the Seagate FireCuda +Gaming Hard Drive, Gaming Drive for Xbox and Gaming Drive for PlayStation +devices. A 2.5" drive and two chips are embedded: an ASMedia ASM1153 USB-to-SATA +bridge controller and a STM32F070 MCU. The former is handling the USB to HDD I/Os +while the latter is dedicated to the LED effects. The two chips are connected +together through I2C. + +The Legend 2.5" SSD board (revision 25ssd) is found in the Seagate SSD Gaming +Drive for Xbox. A Realtek RTS5411S USB hub is embedded and connected to a Phison +U17 2.5" SSD, as well as a STM32F070 MCU. + +The Legend 3.5" board (revision 35) can be found in the Seagate FireCuda Gaming +Hub and Gaming Drive Hub for Xbox devices. A Genesys Logic GL3523-S USB hub is +connected to an ASMedia ASM1153 USB-to-SATA bridge controller and a STM32F070 +MCU. The two chips are connected together using I2C. + +On all boards, the Zephyr port is running on the STM32F070 MCU. + +.. image:: img/firecuda_gaming_hard_drive.png + :width: 550px + :align: center + :alt: Seagate FireCuda Gaming Hard Drive + +.. image:: img/firecuda_gaming_hub.png + :width: 550px + :align: center + :alt: Seagate FireCuda Gaming Hub + +Hardware +******** + +- STM32F070cb MCU: + + - ARM Cortex-M0+ + - 16KB SRAM + - 128KB on-chip flash + +- External devices connected to the STM32F070cb MCU: + + - ASMedia ASM1153 USB-to-SATA bridge (I2C master on port 1) (HDD only) + - 6 (hdd) or 4 (ssd) Everlight B1414 LEDs connected on SPI1 MOSI + - 1 white LED (HDD only) + - 64KB external SPI flash connected on SPI2 + +Supported Features +================== + +All the hardware features available on the Legend boards are supported by +Zephyr. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c master/slave controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| SPI flash | on-chip | spi_nor | ++-----------+------------+-------------------------------------+ +| LED strip | on-chip | ws2812 | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ + + +Connections and IOs +=================== + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PB6 | I2C1 | I2C1 SCL (HDD only) | ++---------+-----------------+----------------------------+ +| PB7 | I2C1 | I2C1 SDA (HDD only) | ++---------+-----------------+----------------------------+ +| PA10 | UART | USART0 RX | ++---------+-----------------+----------------------------+ +| PA9 | UART | USART0 TX | ++---------+-----------------+----------------------------+ +| PB0 | PWM | Activity LED (HDD only) | ++---------+-----------------+----------------------------+ +| PB12 | SPI2 | SPI2 Enable | ++---------+-----------------+----------------------------+ +| PB13 | SPI2 | SPI2 Clock | ++---------+-----------------+----------------------------+ +| PB14 | SPI2 | SPI2 MISO | ++---------+-----------------+----------------------------+ +| PB15 | SPI2 | SPI2 MOSI | ++---------+-----------------+----------------------------+ +| PA7 | LED strip | SPI1 MOSI | ++---------+-----------------+----------------------------+ +| PA12 | USB | USB DM (25ssd and 35 only) | ++---------+-----------------+----------------------------+ +| PA13 | USB | USB DP (25ssd and 35 only) | ++---------+-----------------+----------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The STM32F070cb MCU can be flashed by connecting an external debug probe to the +SWD port (on-board 4-pin header). In the default OpenOCD configuration, the +ST Link interface is selected. You may need to replace it with the interface of +your debug probe. + +Once the debug probe is connected to both the Legend board and your host +computer, then you can simply run the ``west flash`` command to write a firmware +image into flash. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `STM32F070 reference manual`_ + +.. _STM32F070 reference manual: + http://www.st.com/resource/en/reference_manual/dm00031936.pdf diff --git a/boards/arm/legend/legend.dts b/boards/arm/legend/legend.dts new file mode 100644 index 000000000000..87d04152ba4e --- /dev/null +++ b/boards/arm/legend/legend.dts @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2021 Seagate Technology LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include + +/ { + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + watchdog0 = &iwdg; + }; + + board_id: brd-id { + compatible = "gpio-keys"; + brd_id0: brd_id_0 { + label = "BRD_ID_0"; + gpios = <&gpioc 13 0>; + }; + brd_id1: brd_id_1 { + label = "BRD_ID_1"; + gpios = <&gpioc 14 0>; + }; + brd_id2: brd_id_2 { + label = "BRD_ID_2"; + gpios = <&gpioc 15 0>; + }; + }; + +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + current-speed = <115200>; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + clock-frequency = ; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; + dmas = <&dma1 3 0x20440>, <&dma1 2 0x20480>; + dma-names = "tx", "rx"; + status = "okay"; + + led_strip_spi: b1414@0 { + compatible = "everlight,b1414", "worldsemi,ws2812-spi"; + label = "B1414"; + + /* SPI */ + reg = <0>; /* ignored, but necessary for SPI bindings */ + spi-max-frequency = ; + + /* B1414 */ + spi-one-frame = ; + spi-zero-frame = ; + color-mapping = , + , + ; + reset-delay = <250>; + }; +}; + +&spi2 { + pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>; + cs-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + spi_nor: spi_nor@0 { + status = "okay"; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <8000000>; + label = "SPI_FLASH_0"; + size = <1048576>; + /* + * Main flash source + * + * Vendor : Puya + * Model : P25Q21H + * Total size : 256 KB + * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors, + * 256 B pages + * Write size : up to 256 B (page size) + * Lifetime : 100K erase/program cycles on each sector/block + */ + jedec-id = [85 40 12]; + /* + * Alternate flash source + * + * Vendor : Fudan + * Model : FM25F01B + * Total size : 128 KB + * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors + * Write size : up to 256 B (page size) + * Lifetime : 100K erase/program cycles on each sector/block + * + * jedec-id = [a1 31 11]; + * + * Model only found in first Jordan (2"5) EVT revision + * + * Vendor : Fudan + * Model : FM25F005 + * Total size : 64 KB + * Erase size : whole chip, 64 and 32 KB blocks, 4 KB sectors + * + * jedec-id = [a1 31 10]; + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + product_info: partition@0 { + label = "product-info"; + reg = <0x00000000 0x1000>; + }; + led_das: partition@10000 { + label = "led-das"; + reg = <0x00001000 0x0000f000>; + }; + }; + }; +}; + +&spi_nor { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&timers3 { + pwm3: pwm { + pinctrl-0 = <&tim3_ch3_pb0>; + /* + * The maximum period needed on Legend devices for activity LED + * hardware blinking is 250ms (i.e. "error" fast blink at 4 Hz). + * + * We can use the following equation to compute the + * corresponding prescaler value: + * + * period_max = counter_size / cycles_per_second + * + * With: + * + * cycles_per_second = 48 MHz / (prescaler + 1) + * counter_size = 2^16 + * period_max = 0.25 + * + * Which gives: + * + * prescaler = 48 MHz * 0.25 / 2^16 + 1 = 182 + * + * So any prescaler value above 182 is good for a 4 Hz hardware + * blinking. In addition the PWM frequency must be as high as + * possible to fool eyes and cameras with steady brightness + * levels. + */ + st,prescaler = <200>; + status = "disabled"; + }; +}; + +&gpiod { + status = "disabled"; +}; + +&gpiof { + status = "disabled"; +}; + +&iwdg { + status = "okay"; +}; diff --git a/boards/arm/legend/legend.yaml b/boards/arm/legend/legend.yaml new file mode 100644 index 000000000000..b8c8d7d7628b --- /dev/null +++ b/boards/arm/legend/legend.yaml @@ -0,0 +1,19 @@ +identifier: legend +name: Legend +type: mcu +arch: arm +ram: 16 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - pwm + - spi +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/arm/legend/legend_25hdd.overlay b/boards/arm/legend/legend_25hdd.overlay new file mode 100644 index 000000000000..9a82a092299e --- /dev/null +++ b/boards/arm/legend/legend_25hdd.overlay @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021 Seagate Technology LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "Seagate Legend 2.5 HDD board"; + compatible = "legend25_hdd", "seagate,legend25_hdd"; + + aliases { + pwm-led0 = &pwm_led0; + led-strip = &led_strip_spi; + }; + + led_pwm: pwmleds { + compatible = "pwm-leds"; + label = "LED PWM"; + + pwm_led0: pwm_led_0 { + label = "Activity LED"; + pwms = <&pwm3 3 255 PWM_POLARITY_NORMAL>; + }; + }; +}; + +&clk_hsi { + status = "okay"; +}; + +&pll { + clocks = <&clk_hsi>; + prediv = <1>; + mul = <6>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +&led_strip_spi { + chain-length = <6>; + status = "okay"; +}; + +&timers3 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; diff --git a/boards/arm/legend/legend_25ssd.overlay b/boards/arm/legend/legend_25ssd.overlay new file mode 100644 index 000000000000..2f0f4d19baf7 --- /dev/null +++ b/boards/arm/legend/legend_25ssd.overlay @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 Seagate Technology LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "Seagate Legend 2.5 SSD board"; + compatible = "legend25_ssd", "seagate,legend25_ssd"; + + aliases { + led-strip = &led_strip_spi; + }; +}; + +&clk_hse { + clock-frequency = ; /* 24MHz external clock */ + status = "okay"; +}; + +&pll { + clocks = <&clk_hse>; + prediv = <1>; + mul = <2>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +&led_strip_spi { + chain-length = <4>; + status = "okay"; +}; + +&usb { + status = "okay"; +}; diff --git a/boards/arm/legend/legend_35.overlay b/boards/arm/legend/legend_35.overlay new file mode 100644 index 000000000000..30ff1299282b --- /dev/null +++ b/boards/arm/legend/legend_35.overlay @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021 Seagate Technology LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "Seagate Legend 3.5 board"; + compatible = "legend35", "seagate,legend35"; + + aliases { + pwm-led0 = &pwm_led0; + led-strip = &led_strip_spi; + }; + + led_pwm: pwmleds { + compatible = "pwm-leds"; + label = "LED PWM"; + + pwm_led0: pwm_led_0 { + label = "Activity LED"; + pwms = <&pwm3 3 255 PWM_POLARITY_NORMAL>; + }; + }; +}; + +&clk_hse { + clock-frequency = ; /* 24MHz external clock */ + status = "okay"; +}; + +&pll { + clocks = <&clk_hse>; + prediv = <1>; + mul = <2>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +&led_strip_spi { + chain-length = <12>; + status = "okay"; +}; + + +&timers3 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&usb { + status = "okay"; +}; diff --git a/boards/arm/legend/legend_defconfig b/boards/arm/legend/legend_defconfig new file mode 100644 index 000000000000..63720f0538f1 --- /dev/null +++ b/boards/arm/legend/legend_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Zephyr Kernel Configuration +CONFIG_SOC_SERIES_STM32F0X=y + +# Platform Configuration +CONFIG_SOC_STM32F070XB=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Pinmux Driver +CONFIG_PINMUX=y + +# GPIO Controller +CONFIG_GPIO=y + +# Clock Control +CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/legend/revision.cmake b/boards/arm/legend/revision.cmake new file mode 100644 index 000000000000..52f6d0878003 --- /dev/null +++ b/boards/arm/legend/revision.cmake @@ -0,0 +1,8 @@ +set(LEGEND_REVISIONS "25hdd" "25ssd" "35") +if (NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "25hdd") +else() + if (NOT BOARD_REVISION IN_LIST LEGEND_REVISIONS) + message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for Legend. Accepted revisions: ${LEGEND_REVISIONS}") + endif() +endif() diff --git a/boards/arm/legend/support/openocd.cfg b/boards/arm/legend/support/openocd.cfg new file mode 100644 index 000000000000..f0d0b22a310b --- /dev/null +++ b/boards/arm/legend/support/openocd.cfg @@ -0,0 +1,12 @@ +source [find board/st_nucleo_f0.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig b/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig index 6333c49bc3e0..8c272dc10052 100644 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig +++ b/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig @@ -7,7 +7,6 @@ CONFIG_SOC_LPC54114_M0=y CONFIG_SOC_SERIES_LPC54XXX=y CONFIG_BOARD_LPCXPRESSO54114_M0=y -CONFIG_CONSOLE=y CONFIG_USE_SEGGER_RTT=y CONFIG_SERIAL=n CONFIG_CORTEX_M_SYSTICK=y diff --git a/boards/arm/lpcxpresso55s28/doc/index.rst b/boards/arm/lpcxpresso55s28/doc/index.rst index ea14959838da..dba912890045 100644 --- a/boards/arm/lpcxpresso55s28/doc/index.rst +++ b/boards/arm/lpcxpresso55s28/doc/index.rst @@ -71,8 +71,6 @@ hardware features: +-----------+------------+-------------------------------------+ | WWDT | on-chip | windowed watchdog timer | +-----------+------------+-------------------------------------+ -| TrustZone | on-chip | Trusted Firmware-M | -+-----------+------------+-------------------------------------+ | ADC | on-chip | adc | +-----------+------------+-------------------------------------+ | CLOCK | on-chip | clock_control | @@ -83,10 +81,6 @@ Other hardware features are not currently enabled. The default configuration file ``boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig`` -Currently available targets for this board are: - -- *lpcxpresso55s28* secure (S) address space - Connections and IOs =================== diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig b/boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig index 04f52495173b..25b4223910a7 100644 --- a/boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig +++ b/boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig @@ -18,10 +18,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_ARM_TRUSTZONE_M=y - CONFIG_RUNTIME_NMI=y CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/lpcxpresso55s69/doc/index.rst b/boards/arm/lpcxpresso55s69/doc/index.rst index 59713ddc9fcc..3888bfb96f85 100644 --- a/boards/arm/lpcxpresso55s69/doc/index.rst +++ b/boards/arm/lpcxpresso55s69/doc/index.rst @@ -80,6 +80,12 @@ features: +-----------+------------+-------------------------------------+ | HWINFO | on-chip | Unique device serial number | +-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ Targets available ================== @@ -139,6 +145,14 @@ functionality of a pin. +---------+-----------------+----------------------------+ | PIO1_24 | USART | USART RX | +---------+-----------------+----------------------------+ +| PIO0_20 | I2S | I2S DATAOUT | ++---------+-----------------+----------------------------+ +| PIO0_19 | I2S | I2S TX WS | ++---------+-----------------+----------------------------+ +| PIO0_21 | I2S | I2S TX SCK | ++---------+-----------------+----------------------------+ +| PIO1_13 | I2S | I2S DATAIN | ++---------+-----------------+----------------------------+ Memory mappings =============== diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts index 3650e148e179..c69df0b62ed4 100644 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts +++ b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts @@ -105,3 +105,49 @@ &mailbox0 { status = "okay"; }; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&ctimer4 { + status = "okay"; +}; + +/* I2S receive channel */ +i2s0: &flexcomm6 { + status = "okay"; + compatible = "nxp,lpc-i2s"; + label = "I2S_0"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 16>; + dma-names = "rx"; +}; + +/* I2S transmit channel */ +i2s1: &flexcomm7 { + status = "okay"; + compatible = "nxp,lpc-i2s"; + label = "I2S_1"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 19>; + dma-names = "tx"; +}; diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml index 782d40245142..520ed04295c1 100644 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml +++ b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml @@ -19,7 +19,10 @@ supported: - arduino_i2c - arduino_serial - arduino_spi + - counter - gpio - i2c + - i2s - spi + - usb_device - watchdog diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts index 82daf1b3ffe7..88d10e332cce 100644 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts +++ b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts @@ -103,3 +103,27 @@ dma-channels = <20>; status = "okay"; }; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&ctimer4 { + status = "okay"; +}; diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml index 97b4f7b19016..b988cc3e01fd 100644 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml +++ b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml @@ -17,6 +17,7 @@ toolchain: supported: - adc - arduino_spi + - counter - dma - gpio - spi diff --git a/boards/arm/lpcxpresso55s69/pinmux.c b/boards/arm/lpcxpresso55s69/pinmux.c index fd471a889de4..10edfb7fc378 100644 --- a/boards/arm/lpcxpresso55s69/pinmux.c +++ b/boards/arm/lpcxpresso55s69/pinmux.c @@ -183,6 +183,70 @@ static int lpcxpresso_55s69_pinmux_init(const struct device *dev) IOCON_PIO_OPENDRAIN_DI); #endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay)) && \ + (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_i2s, okay)) && \ + CONFIG_I2S + CLOCK_EnableClock(kCLOCK_Sysctl); + /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm 7 */ + SYSCTL->SHAREDCTRLSET[0] = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(7) | + SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(7); + +#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES + /* Select Data in from Transmit I2S - Flexcomm 7 */ + SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(7); + /* Enable Transmit I2S - Flexcomm 7 for Shared Data Out */ + SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(1); +#endif + + /* Set Receive I2S - Flexcomm 6 SCK, WS from shared signal set 0 */ + SYSCTL->FCCTRLSEL[6] = SYSCTL_FCCTRLSEL_SCKINSEL(1) | + SYSCTL_FCCTRLSEL_WSINSEL(1); + + /* Set Transmit I2S - Flexcomm 7 SCK, WS from shared signal set 0 */ + SYSCTL->FCCTRLSEL[7] = SYSCTL_FCCTRLSEL_SCKINSEL(1) | + SYSCTL_FCCTRLSEL_WSINSEL(1); + +#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES + /* Select Receive I2S - Flexcomm 6 Data in from shared signal set 0 */ + SYSCTL->FCCTRLSEL[6] |= SYSCTL_FCCTRLSEL_DATAINSEL(1); + /* Select Transmit I2S - Flexcomm 7 Data out to shared signal set 0 */ + SYSCTL->FCCTRLSEL[7] |= SYSCTL_FCCTRLSEL_DATAOUTSEL(1); +#endif + + /* Pin is configured as FC7_TXD_SCL_MISO_WS */ + pinmux_pin_set(port0, 19, IOCON_PIO_FUNC7 | + IOCON_PIO_MODE_PULLUP | + IOCON_PIO_SLEW_FAST | + IOCON_PIO_INV_DI | + IOCON_PIO_DIGITAL_EN | + IOCON_PIO_OPENDRAIN_DI); + + /* Pin is configured as FC7_RXD_SDA_MOSI_DATA */ + pinmux_pin_set(port0, 20, IOCON_PIO_FUNC7 | + IOCON_PIO_MODE_PULLUP | + IOCON_PIO_SLEW_FAST | + IOCON_PIO_INV_DI | + IOCON_PIO_DIGITAL_EN | + IOCON_PIO_OPENDRAIN_DI); + + /* Pin is configured as FC7_SCK */ + pinmux_pin_set(port0, 21, IOCON_PIO_FUNC7 | + IOCON_PIO_MODE_PULLUP | + IOCON_PIO_SLEW_FAST | + IOCON_PIO_INV_DI | + IOCON_PIO_DIGITAL_EN | + IOCON_PIO_OPENDRAIN_DI); + + /* Pin is configured as FC6_RXD_SDA_MOSI_DATA */ + pinmux_pin_set(port1, 13, IOCON_PIO_FUNC2 | + IOCON_PIO_MODE_PULLUP | + IOCON_PIO_SLEW_FAST | + IOCON_PIO_INV_DI | + IOCON_PIO_DIGITAL_EN | + IOCON_PIO_OPENDRAIN_DI); + +#endif + return 0; } diff --git a/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts index a69c026e8cd5..510544a2e551 100644 --- a/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts +++ b/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts @@ -125,7 +125,7 @@ pc_girq = <15>; }; -&timer3 { +&timer5 { status = "okay"; }; diff --git a/boards/arm/mec172xevb_assy6906/Kconfig.defconfig b/boards/arm/mec172xevb_assy6906/Kconfig.defconfig index d55989958178..8b23b520e1f6 100644 --- a/boards/arm/mec172xevb_assy6906/Kconfig.defconfig +++ b/boards/arm/mec172xevb_assy6906/Kconfig.defconfig @@ -6,4 +6,34 @@ if BOARD_MEC172XEVB_ASSY6906 config BOARD default "mec172xevb_assy6906" +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 Hz. +# The driver requires tickless mode and ticks per second to be 32768 for +# accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR +# processor clock divider register. We assume PCR processor clock divider +# is set to 1. Refer to SOC_MEC172X_PROC_CLK_DIV +# + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 96000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # RTOS_TIMER + endif # BOARD_MEC172XEVB_ASSY6906 diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts index 198acaf45d39..fb7c7231a30f 100644 --- a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts +++ b/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts @@ -17,10 +17,36 @@ zephyr,flash = &flash0; zephyr,console = &uart1; }; + + aliases { + led0 = &led4; + led1 = &led3; + i2c0 = &i2c_smb_0; + i2c1 = &i2c_smb_1; + i2c7 = &i2c_smb_2; + }; + + leds { + compatible = "gpio-leds"; + led4: led_0 { + /* GPIO241/CMP_VOUT0/PWM0_ALT on schematic, + * LED4 on silkscreen. + */ + gpios = <&gpio_240_276 1 GPIO_ACTIVE_HIGH>; + label = "LED 4"; + }; + led3: led_1 { + /* GPIO175/CMP_VOUT1/PWM8_ALT on schematic, + * LED5 on silkscreen. + */ + gpios = <&gpio_140_176 29 GPIO_ACTIVE_HIGH>; + label = "LED 5"; + }; + }; }; &cpu0 { - clock-frequency = <96000000>; + status = "okay"; }; /* Initialize ECIA. Does not initialize child devices */ @@ -28,7 +54,7 @@ status = "okay"; }; -&systick { +&rtimer { status = "okay"; }; @@ -40,3 +66,42 @@ status = "okay"; current-speed = <115200>; }; + +&adc0 { + status = "okay"; +}; + +&i2c_smb_0 { + status = "okay"; + label = "I2C0"; + port_sel = <0>; + + pca9555@26 { + compatible = "nxp,pca95xx"; + label = "GPIO_P0"; + + /* Depends on JP53 for device address. + * Pin 1-2 = A0, pin 3-4 = A1, pin 5-6 = A2. + * Address is: 0100b. + * + * Default has pin 1-2 on JP53 connected, + * resulting in device address 0x26. + */ + reg = <0x26>; + + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c_smb_1 { + status = "okay"; + label = "I2C1"; + port_sel = <1>; +}; + +&i2c_smb_2 { + status = "okay"; + label = "I2C7"; + port_sel = <7>; +}; diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.yaml b/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.yaml index fe7bb7e3c265..69e9d64ced33 100644 --- a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.yaml +++ b/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.yaml @@ -16,3 +16,4 @@ flash: 352 supported: - gpio - pinmux + - i2c diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig b/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig index f8c33a22e594..8c03840f5d95 100644 --- a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig +++ b/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig @@ -7,11 +7,13 @@ CONFIG_SOC_MEC172X_NSZ=y CONFIG_SOC_SERIES_MEC172X=y CONFIG_BOARD_MEC172XEVB_ASSY6906=y - -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 +CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y +CONFIG_GPIO=y +CONFIG_PINMUX=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -CONFIG_UART_NS16550=y +CONFIG_ADC=y +CONFIG_I2C=y diff --git a/boards/arm/mec172xevb_assy6906/pinmux.c b/boards/arm/mec172xevb_assy6906/pinmux.c index cfeeedb187a7..49aa3e37420b 100644 --- a/boards/arm/mec172xevb_assy6906/pinmux.c +++ b/boards/arm/mec172xevb_assy6906/pinmux.c @@ -9,9 +9,87 @@ #include #include -#include "soc.h" +#include -/* - * If PINMUX will be used this is where board_pinmux_init should be implemented - * and added to SYS_INIT. - */ +struct pinmux_ports_t { +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_000_036), okay) + const struct device *porta; +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_040_076), okay) + const struct device *portb; +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_100_136), okay) + const struct device *portc; +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_140_176), okay) + const struct device *portd; +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_200_236), okay) + const struct device *porte; +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_240_276), okay) + const struct device *portf; +#endif +}; + +static void brd_init_pinmux_ports(struct pinmux_ports_t *pp) +{ + ARG_UNUSED(pp); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_000_036), okay) + pp->porta = DEVICE_DT_GET(DT_NODELABEL(pinmux_000_036)); + + __ASSERT_NO_MSG(device_is_ready(pp->porta)); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_040_076), okay) + pp->portb = DEVICE_DT_GET(DT_NODELABEL(pinmux_040_076)); + + __ASSERT_NO_MSG(device_is_ready(pp->portb)); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_100_136), okay) + pp->portc = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_136)); + + __ASSERT_NO_MSG(device_is_ready(pp->portc)); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_140_176), okay) + pp->portd = DEVICE_DT_GET(DT_NODELABEL(pinmux_140_176)); + + __ASSERT_NO_MSG(device_is_ready(pp->portd)); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_200_236), okay) + pp->porte = DEVICE_DT_GET(DT_NODELABEL(pinmux_200_236)); + + __ASSERT_NO_MSG(device_is_ready(pp->porte)); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmux_240_276), okay) + pp->portf = DEVICE_DT_GET(DT_NODELABEL(pinmux_240_276)); + + __ASSERT_NO_MSG(device_is_ready(pp->portf)); +#endif +} + +static void brd_cfg_uart(struct pinmux_ports_t *pp) +{ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay) + pinmux_pin_set(pp->portc, MCHP_GPIO_104, MCHP_GPIO_CTRL_MUX_F1); + pinmux_pin_set(pp->portc, MCHP_GPIO_105, MCHP_GPIO_CTRL_MUX_F1); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) + pinmux_pin_set(pp->portd, MCHP_GPIO_170, MCHP_GPIO_CTRL_MUX_F1); + pinmux_pin_set(pp->portd, MCHP_GPIO_171, MCHP_GPIO_CTRL_MUX_F1); +#endif +} + +/* caller passes dev = NULL */ +static int board_pinmux_init(const struct device *dev) +{ + ARG_UNUSED(dev); + struct pinmux_ports_t pp; + + brd_init_pinmux_ports(&pp); + brd_cfg_uart(&pp); + + return 0; +} + +SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig b/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig index 75d80eb012be..3a2bbe8f5d4b 100644 --- a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig +++ b/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig @@ -12,8 +12,4 @@ config SPI_STM32_INTERRUPT default y depends on SPI -config USB_DC_STM32 - default y - depends on USB - endif # BOARD_MIKROE_MINI_M4_FOR_STM32 diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts index f2bc079d04f8..51ca2cd897da 100644 --- a/boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts +++ b/boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts @@ -15,7 +15,6 @@ aliases { led0 = &green_led; sw0 = &user_button; - usbd0 = &usb1; }; chosen { @@ -66,6 +65,6 @@ arduino_serial: &lpuart1 {}; current-speed = <115200>; }; -&usb1 { +zephyr_udc0: &usb1 { status = "okay"; }; diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts index d0090de7316d..e617fd911c54 100644 --- a/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts +++ b/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts @@ -15,7 +15,6 @@ aliases { led0 = &green_led; sw0 = &user_button; - usbd0 = &usb1; }; chosen { @@ -95,6 +94,6 @@ arduino_serial: &lpuart4 {}; current-speed = <115200>; }; -&usb1 { +zephyr_udc0: &usb1 { status = "okay"; }; diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts index 45283a5abddc..91dde0675057 100644 --- a/boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts +++ b/boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts @@ -15,7 +15,6 @@ aliases { led0 = &green_led; sw0 = &user_button; - usbd0 = &usb1; }; chosen { @@ -113,7 +112,7 @@ arduino_serial: &lpuart2 {}; }; }; -&usb1 { +zephyr_udc0: &usb1 { status = "okay"; }; diff --git a/boards/arm/mimxrt1020_evk/pinmux.c b/boards/arm/mimxrt1020_evk/pinmux.c index 4452b9e97faf..84e6e2f17e53 100644 --- a/boards/arm/mimxrt1020_evk/pinmux.c +++ b/boards/arm/mimxrt1020_evk/pinmux.c @@ -244,5 +244,5 @@ static int mimxrt1020_evk_phy_reset(const struct device *dev) SYS_INIT(mimxrt1020_evk_init, PRE_KERNEL_1, 0); #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET -SYS_INIT(mimxrt1020_evk_phy_reset, PRE_KERNEL_2, 0); +SYS_INIT(mimxrt1020_evk_phy_reset, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY); #endif diff --git a/boards/arm/mimxrt1024_evk/Kconfig.defconfig b/boards/arm/mimxrt1024_evk/Kconfig.defconfig index 8bb25ab156a8..98e1d7674693 100644 --- a/boards/arm/mimxrt1024_evk/Kconfig.defconfig +++ b/boards/arm/mimxrt1024_evk/Kconfig.defconfig @@ -12,4 +12,17 @@ choice CODE_LOCATION default CODE_FLEXSPI endchoice +config FLASH_MCUX_FLEXSPI_NOR + default y if FLASH + +config FLASH_MCUX_FLEXSPI_XIP + default y if FLASH + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + endif # BOARD_MIMXRT1024_EVK diff --git a/boards/arm/mimxrt1024_evk/doc/index.rst b/boards/arm/mimxrt1024_evk/doc/index.rst index 30cc6c0b38fc..95f677aeb51f 100644 --- a/boards/arm/mimxrt1024_evk/doc/index.rst +++ b/boards/arm/mimxrt1024_evk/doc/index.rst @@ -79,6 +79,8 @@ features: | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: ``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig`` @@ -101,6 +103,30 @@ The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers. +---------------+-----------------+---------------------------+ | WAKEUP | GPIO | SW4 | +---------------+-----------------+---------------------------+ +| GPIO_AD_B0_04 | ENET_RST | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_08 | ENET_REF_CLK | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | ENET_RX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | ENET_RX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_11 | ENET_RX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_12 | ENET_RX_ER | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | ENET_TX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_14 | ENET_TX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_15 | ENET_TX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_06 | ENET_INT | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_41 | ENET_MDC | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_40 | ENET_MDIO | Ethernet | ++---------------+-----------------+---------------------------+ System Clock ============ diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts index 0b888295d03b..dc69492e0fce 100644 --- a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts @@ -18,7 +18,11 @@ }; chosen { + zephyr,flash-controller = &flexspi; + zephyr,flash = &is25wp032; + zephyr,code-partition = &slot0_partition; zephyr,sram = &sdram0; + zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; @@ -47,6 +51,42 @@ }; }; +&is25wp032 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(1984)>; + }; + + slot1_partition: partition@200000 { + label = "image-1"; + reg = <0x00200000 DT_SIZE_K(1984)>; + }; + + scratch_partition: partition@3f0000 { + label = "image-scratch"; + reg = <0x003f0000 DT_SIZE_K(64)>; + }; + }; +}; + +&enet { + status = "okay"; + ptp { + status = "okay"; + }; +}; + &lpuart1 { status = "okay"; current-speed = <115200>; diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml b/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml index 56c8666c9c45..d3c462792eba 100644 --- a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml +++ b/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml @@ -14,3 +14,5 @@ toolchain: - xtools ram: 32768 flash: 4096 +supported: + - netif:eth diff --git a/boards/arm/mimxrt1024_evk/pinmux.c b/boards/arm/mimxrt1024_evk/pinmux.c index 327981974a6b..0c62b34e2f80 100644 --- a/boards/arm/mimxrt1024_evk/pinmux.c +++ b/boards/arm/mimxrt1024_evk/pinmux.c @@ -8,6 +8,13 @@ #include #include +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET +static gpio_pin_config_t enet_gpio_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0, + .interruptMode = kGPIO_NoIntmode +}; +#endif static int mimxrt1024_evk_init(const struct device *dev) { @@ -43,7 +50,59 @@ static int mimxrt1024_evk_init(const struct device *dev) IOMUXC_SW_PAD_CTL_PAD_DSE(6)); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0xB0A9u); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0xB0A9u); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0xB0E9); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0xB0E9); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0xB0E9); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0xB0E9); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0xB0E9); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0xB0E9); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 0x31); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0xB0E9); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC, 0xB0E9); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0xB829); + + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); + + /* Initialize ENET_INT GPIO */ + GPIO_PinInit(GPIO1, 4, &enet_gpio_config); + GPIO_PinInit(GPIO1, 22, &enet_gpio_config); + + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput(GPIO1, 22, 1); + GPIO_WritePinOutput(GPIO1, 4, 0); +#endif + return 0; } +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET +static int mimxrt1024_evk_phy_reset(const struct device *dev) +{ + /* RESET PHY chip. */ + k_busy_wait(USEC_PER_MSEC * 10U); + GPIO_WritePinOutput(GPIO1, 4, 1); + + return 0; +} +#endif + SYS_INIT(mimxrt1024_evk_init, PRE_KERNEL_1, 0); +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET +SYS_INIT(mimxrt1024_evk_phy_reset, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY); +#endif diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts b/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts index 267a09a07c30..c4a6f5e02af4 100644 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts +++ b/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts @@ -17,7 +17,6 @@ sw0 = &user_button; kscan0 = &touch_controller; watchdog0 = &wdog0; - usbd0 = &usb1; }; chosen { @@ -153,7 +152,7 @@ arduino_serial: &lpuart3 {}; }; }; -&usb1 { +zephyr_udc0: &usb1 { status = "okay"; }; diff --git a/boards/arm/mimxrt1050_evk/pinmux.c b/boards/arm/mimxrt1050_evk/pinmux.c index 903d798a34e1..a013e45912fa 100644 --- a/boards/arm/mimxrt1050_evk/pinmux.c +++ b/boards/arm/mimxrt1050_evk/pinmux.c @@ -331,5 +331,5 @@ static int mimxrt1050_evk_phy_reset(const struct device *dev) SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0); #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET -SYS_INIT(mimxrt1050_evk_phy_reset, PRE_KERNEL_2, 0); +SYS_INIT(mimxrt1050_evk_phy_reset, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY); #endif diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts index e50c44e09ed5..c000c4e4b660 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts +++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts @@ -17,7 +17,6 @@ sw0 = &user_button; kscan0 = &touch_controller; watchdog0 = &wdog0; - usbd0 = &usb1; }; chosen { @@ -173,7 +172,7 @@ arduino_serial: &lpuart3 {}; }; }; -&usb1 { +zephyr_udc0: &usb1 { status = "okay"; }; diff --git a/boards/arm/mimxrt1060_evk/pinmux.c b/boards/arm/mimxrt1060_evk/pinmux.c index 4f113d764fae..ea711d9651bc 100644 --- a/boards/arm/mimxrt1060_evk/pinmux.c +++ b/boards/arm/mimxrt1060_evk/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NXP + * Copyright (c) 2018,2021 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -144,6 +144,21 @@ static int mimxrt1060_evk_init(const struct device *dev) IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + +#if IS_ENABLED(DT_PROP(DT_NODELABEL(lpuart3), hw_flow_control)) + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B, 0U); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); +#endif #endif #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C @@ -313,5 +328,5 @@ static int mimxrt1060_evk_phy_reset(const struct device *dev) SYS_INIT(mimxrt1060_evk_init, PRE_KERNEL_1, 0); #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET -SYS_INIT(mimxrt1060_evk_phy_reset, PRE_KERNEL_2, 0); +SYS_INIT(mimxrt1060_evk_phy_reset, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY); #endif diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts index a644a0fea9da..7595793d0d76 100644 --- a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts @@ -17,7 +17,7 @@ pwm-led0 = &green_pwm_led; sw0 = &user_button; kscan0 = &touch_controller; - usbd0 = &usb1; + watchdog0 = &wdog0; }; chosen { @@ -209,7 +209,7 @@ arduino_serial: &lpuart3 { }; }; -&usb1 { +zephyr_udc0: &usb1 { status = "okay"; }; @@ -234,7 +234,15 @@ arduino_serial: &lpuart3 { cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; }; +&edma0 { + status = "okay"; +}; + &flexcan2 { status = "okay"; bus-speed = <125000>; }; + +&wdog0 { + status = "okay"; +}; diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml b/boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml index 50403b58a24e..4ae7883d5b89 100644 --- a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml +++ b/boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml @@ -19,6 +19,7 @@ supported: - arduino_serial - counter - display + - dma - gpio - i2c - netif:eth @@ -28,3 +29,4 @@ supported: - video - kscan:touch - can + - watchdog diff --git a/boards/arm/mimxrt1064_evk/pinmux.c b/boards/arm/mimxrt1064_evk/pinmux.c index 484a9a9ca699..da74d953ef08 100644 --- a/boards/arm/mimxrt1064_evk/pinmux.c +++ b/boards/arm/mimxrt1064_evk/pinmux.c @@ -351,5 +351,5 @@ static int mimxrt1064_evk_phy_reset(const struct device *dev) SYS_INIT(mimxrt1064_evk_init, PRE_KERNEL_1, 0); #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET -SYS_INIT(mimxrt1064_evk_phy_reset, PRE_KERNEL_2, 0); +SYS_INIT(mimxrt1064_evk_phy_reset, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY); #endif diff --git a/boards/arm/mimxrt1170_evk/pinmux.c b/boards/arm/mimxrt1170_evk/pinmux.c index 329494137302..1a3eeeea608b 100644 --- a/boards/arm/mimxrt1170_evk/pinmux.c +++ b/boards/arm/mimxrt1170_evk/pinmux.c @@ -214,5 +214,5 @@ static int mimxrt1170_evk_phy_reset(const struct device *dev) SYS_INIT(mimxrt1170_evk_init, PRE_KERNEL_1, 0); #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET -SYS_INIT(mimxrt1170_evk_phy_reset, PRE_KERNEL_2, 0); +SYS_INIT(mimxrt1170_evk_phy_reset, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY); #endif diff --git a/boards/arm/mimxrt685_evk/Kconfig.defconfig b/boards/arm/mimxrt685_evk/Kconfig.defconfig index 6b2f51008d0f..13b5e7e5323c 100644 --- a/boards/arm/mimxrt685_evk/Kconfig.defconfig +++ b/boards/arm/mimxrt685_evk/Kconfig.defconfig @@ -38,4 +38,7 @@ config HEAP_MEM_POOL_SIZE endif # DMA_MCUX_LPC +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + endif # BOARD_MIMXRT685_EVK diff --git a/boards/arm/mimxrt685_evk/doc/index.rst b/boards/arm/mimxrt685_evk/doc/index.rst index e2932da3fa20..f94ce8c5a723 100644 --- a/boards/arm/mimxrt685_evk/doc/index.rst +++ b/boards/arm/mimxrt685_evk/doc/index.rst @@ -87,6 +87,18 @@ features: +-----------+------------+-------------------------------------+ | RTC | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CTIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: @@ -159,6 +171,26 @@ functionality of a pin. +---------+-----------------+----------------------------+ | PIO2_23 | FLEXSPI0B_DATA7 | OctalSPI Flash | +---------+-----------------+----------------------------+ +| PIO0_27 | SCT0_OUT7 | PWM | ++---------+-----------------+----------------------------+ +| PIO1_30 | SD0_CLK | SD card | ++---------+-----------------+----------------------------+ +| PIO1_31 | SD0_CMD | SD card | ++---------+-----------------+----------------------------+ +| PIO2_0 | SD0_D0 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_1 | SD0_D1 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_2 | SD0_D2 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_3 | SD0_D3 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_4 | SD0_WR_PRT | SD card | ++---------+-----------------+----------------------------+ +| PIO2_9 | SD0_CD | SD card | ++---------+-----------------+----------------------------+ +| PIO2_10 | SD0_RST | SD card | ++---------+-----------------+----------------------------+ System Clock ============ diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts index d16dcd817260..79e9d23f15b3 100644 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts +++ b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include / { model = "NXP MIMXRT685-EVK board"; @@ -19,6 +20,13 @@ led1 = &blue_led; led2 = &red_led; usart-0 = &flexcomm0; + /* For pwm test suites */ + pwm-0 = &sc_timer; + pwm-led0 = &green_pwm_led; + green-pwm-led = &green_pwm_led; + blue-pwm-led = &blue_pwm_led; + red-pwm-led = &red_pwm_led; + watchdog0 = &wwdt0; }; chosen { @@ -58,6 +66,25 @@ }; }; + pwmleds { + compatible = "pwm-leds"; + green_pwm_led: green_pwm_led { + pwms = <&sc_timer 0 PWM_POLARITY_NORMAL>; + label = "Green PWM LED"; + status = "okay"; + }; + blue_pwm_led: blue_pwm_led { + pwms = <&sc_timer 6 PWM_POLARITY_NORMAL>; + label = "Blue PWM LED"; + status = "okay"; + }; + red_pwm_led: red_pwm_led { + pwms = <&sc_timer 6 PWM_POLARITY_NORMAL>; + label = "Red PWM LED"; + status = "disabled"; + }; + }; + arduino_header: arduino-connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; @@ -226,6 +253,10 @@ i2s1: &flexcomm3 { status = "okay"; }; +&gpio2 { + status = "okay"; +}; + &dma0 { /* * The total number of dma channels available is defined by @@ -239,6 +270,10 @@ i2s1: &flexcomm3 { status = "okay"; }; +&wwdt0 { + status = "okay"; +}; + &user_button_1 { status = "okay"; }; @@ -258,3 +293,42 @@ i2s1: &flexcomm3 { &red_led { status = "okay"; }; + +&sc_timer { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + /* Quick fix for 1.8V SD cards on RT600- disable 1.8V negotiation */ + no-1-8-v; + pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; +}; + +&lpadc0 { + status = "okay"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&ctimer4 { + status = "okay"; +}; diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml index 6629c9bcfb81..605562fcc651 100644 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml +++ b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml @@ -25,4 +25,7 @@ supported: - hwinfo - i2c - i2s + - sdhc - spi + - watchdog + - usb_device diff --git a/boards/arm/mimxrt685_evk/pinmux.c b/boards/arm/mimxrt685_evk/pinmux.c index aeee6923fc59..b45009f30bb9 100644 --- a/boards/arm/mimxrt685_evk/pinmux.c +++ b/boards/arm/mimxrt685_evk/pinmux.c @@ -676,6 +676,378 @@ static int mimxrt685_evk_pinmux_init(const struct device *dev) IOPCTL_PinMuxSet(IOPCTL, 2U, 23U, port2_pin23_config); #endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(sc_timer), nxp_sctimer_pwm, okay) && CONFIG_PWM + /* Pin is configured as SCT0_OUT0 */ + uint32_t port0_pin27_config = ( + IOPCTL_PIO_FUNC3 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT0 PIN27 (coords: B3) is configured as SCT0_OUT7 */ + IOPCTL_PinMuxSet(IOPCTL, 0U, 27U, port0_pin27_config); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(green_pwm_led), okay) + uint32_t port0_pin14_config = ( + IOPCTL_PIO_FUNC3 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT0 PIN14 (coords: B3) is configured as SCT0_OUT0 */ + IOPCTL_PinMuxSet(IOPCTL, 0U, 14U, port0_pin14_config); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(blue_pwm_led), okay) + uint32_t port0_pin26_config = ( + IOPCTL_PIO_FUNC3 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT0 PIN26 (coords: B3) is configured as SCT0_OUT6 */ + IOPCTL_PinMuxSet(IOPCTL, 0U, 26U, port0_pin26_config); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(red_pwm_led), okay) + uint32_t port0_pin31_config = ( + IOPCTL_PIO_FUNC3 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT0 PIN31 (coords: B3) is configured as SCT0_OUT6 */ + IOPCTL_PinMuxSet(IOPCTL, 0U, 31U, port0_pin31_config); +#endif + +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC + uint32_t port1_pin30_config = (/* Pin is configured as SD0_CLK */ + IOPCTL_PIO_FUNC1 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT1 PIN30 (coords: P10) is configured as SD0_CLK */ + IOPCTL_PinMuxSet(IOPCTL, 1U, 30U, port1_pin30_config); + + uint32_t port1_pin31_config = (/* Pin is configured as SD0_CMD */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT1 PIN31 (coords: R9) is configured as SD0_CMD */ + IOPCTL_PinMuxSet(IOPCTL, 1U, 31U, port1_pin31_config); + + uint32_t port2_pin0_config = (/* Pin is configured as SD0_D0 */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN0 (coords: R11) is configured as SD0_D0 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 0U, port2_pin0_config); + + uint32_t port2_pin1_config = (/* Pin is configured as SD0_D1 */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN1 (coords: T11) is configured as SD0_D1 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 1U, port2_pin1_config); + + uint32_t port2_pin10_config = (/* Pin is configured as PIO2_10 */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN10 (coords: T15) is configured as PIO2_10 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 10U, port2_pin10_config); + + uint32_t port2_pin2_config = (/* Pin is configured as SD0_D2 */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN2 (coords: U11) is configured as SD0_D2 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 2U, port2_pin2_config); + + uint32_t port2_pin3_config = (/* Pin is configured as SD0_D3 */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN3 (coords: T12) is configured as SD0_D3 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 3U, port2_pin3_config); + + uint32_t port2_pin4_config = (/* Pin is configured as PIO2_4 */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN4 (coords: T13) is configured as PIO2_4 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 4U, port2_pin4_config); + + uint32_t port2_pin9_config = (/* Pin is configured as SD0_CARD_DET_N */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN9 (coords: R13) is configured as SD0_CARD_DET_N */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpadc0), okay) && CONFIG_ADC + /* + * The current test and sample applications uses a single channel for + * testing so we only need to enable the pin for that single use. + * + * If your application requires more then the mappings are as follows + * for the rt685_evk: + * + * +---------+------+---------+-------+ + * | Port# | ADC |Schematic|Arduino| + * | pin | Chn# | |header | + * +---------+------+---------+-------+ + * | PIO0_5 | CH0A | ADC0_0 | J30.1 | + * +---------+------+---------+-------+ + * | PIO0_6 | CH0B | ADC0_8 | J30.2 | + * +---------+------+---------+-------+ + * | PIO0_12 | CH1A | ADC0_1 | | + * +---------+------+---------+-------+ + * | PIO0_13 | CH1B | ADC0_9 | | + * +---------+------+---------+-------+ + * | PIO0_19 | CH2A | ADC0_2 | J30.3 | + * +---------+------+---------+-------+ + * | PIO0_20 | CH2B | ADC0_10 | J30.4 | + * +---------+------+---------+-------+ + * | PIO0_26 | CH3A | ADC0_3 | | + * +---------+------+---------+-------+ + * | PIO0_27 | CH3B | ADC0_11 | | + * +---------+------+---------+-------+ + * | PIO1_8 | CH4A | ADC0_4 | | + * +---------+------+---------+-------+ + * | PIO1_9 | CH4B | ADC0_12 | | + * +---------+------+---------+-------+ + * | PIO3_23 | CH5A | ADC0_5 | | + * +---------+------+---------+-------+ + * | PIO3_24 | CH5B | ADC0_13 | | + * +---------+------+---------+-------+ + * + * Per the mimxrt6xx reference manual, The channels 0-5 are analong input. + * Optionally, channels 0A through 5A can be paired with channels 0B + * through 5B for differential input on their respective ADC channel. + * + */ + const uint32_t port0_pin5_config = ( + /* Pin is configured as ADC0_0 */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is enabled */ + IOPCTL_PIO_ANAMUX_EN | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT0 PIN5 (coords: F4) is configured as ADC0_0 */ + IOPCTL_PinMuxSet(IOPCTL, 0U, 5U, port0_pin5_config); + + const uint32_t port0_pin6_config = ( + /* Pin is configured as ADC0_8 */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is enabled */ + IOPCTL_PIO_ANAMUX_EN | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT0 PIN6 (coords: E1) is configured as ADC0_8 */ + IOPCTL_PinMuxSet(IOPCTL, 0U, 6U, port0_pin6_config); +#endif + return 0; } diff --git a/boards/arm/mm_feather/CMakeLists.txt b/boards/arm/mm_feather/CMakeLists.txt new file mode 100644 index 000000000000..22e8a9e01d4c --- /dev/null +++ b/boards/arm/mm_feather/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2021 MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(pinmux.c) +zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) +zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmfeather_sdram_ini_dcd.c) diff --git a/boards/arm/mm_feather/Kconfig.board b/boards/arm/mm_feather/Kconfig.board new file mode 100644 index 000000000000..c003514fdab1 --- /dev/null +++ b/boards/arm/mm_feather/Kconfig.board @@ -0,0 +1,10 @@ +# +# Copyright (c) 2021, MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_MM_FEATHER + bool "MM MM-FEATHER" + depends on SOC_SERIES_IMX_RT + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mm_feather/Kconfig.defconfig b/boards/arm/mm_feather/Kconfig.defconfig new file mode 100644 index 000000000000..a0f6910a7dcc --- /dev/null +++ b/boards/arm/mm_feather/Kconfig.defconfig @@ -0,0 +1,18 @@ +# MM-FEATHER board + +# Copyright (c) 2021, MADMACHINE LIMITED +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MM_FEATHER + +config BOARD + default "mm_feather" + +choice CODE_LOCATION + default CODE_FLEXSPI +endchoice + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_MM_FEATHER diff --git a/boards/arm/mm_feather/board.cmake b/boards/arm/mm_feather/board.cmake new file mode 100644 index 000000000000..573baa5ccb0c --- /dev/null +++ b/boards/arm/mm_feather/board.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021, MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_set_debugger_ifnset(pyocd) +board_set_flasher_ifnset(pyocd) + +board_runner_args(pyocd "--target=mimxrt1050_quadspi") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/mm_feather/doc/index.rst b/boards/arm/mm_feather/doc/index.rst new file mode 100644 index 000000000000..ef70ee0a22ca --- /dev/null +++ b/boards/arm/mm_feather/doc/index.rst @@ -0,0 +1,239 @@ +.. _mm_feather: + +MadMachine SwiftIO Feather +########################## + +Overview +******** + +The SwiftIO Feather board, designed by MadMachine is +designed with support for the modern `Swift language +`_. Zephyr provides basic +low-level capabilities for the SwiftIO Feather board. Swift application would +run on top of Zephyr. More information about the board can be found +at: + +- `MadMachine Homepage`_ +- `SwiftIO API Reference`_ + +.. image:: ./mm_feather.jpg + :width: 720px + :align: center + :alt: SwiftIO Feather Board + +Hardware +******** + +- MIMXRT1062DVL6B MCU (Cortex-M7 at 600MHz, 2048KB on-chip memory) + +- Memory + + - 8MB QSPI Flash + - 32MB SDRAM + - TF socket for SD card + +- USB + + - USB-C 2.0 OTG connector + +- Power + + - 5V USB power + - 4.2V DC jack + +- Debug + + - SWD connector + + +- RGB LED + + +Supported Features +================== + +The mm_feather board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | I2S | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ + + + +Connections and IOs +=================== + +Note: +The following SwiftIO Feather pinout diagram is used for Swift programming. +The Swift ID is not the same as the Zephyr driver ID. + ++-----------+---------------+----------+---------------+--------------------------+ +| Name | GPIO | Other peripherals | ++===========+===============+==========+===============+==========+===============+ +| Swift ID | Pin name | Swift ID | Zephyr driver | Swift ID | Zephyr driver | ++-----------+---------------+----------+---------------+----------+---------------+ +| P0 | GPIO_AD_B1_04 | D0 | GPIO1_IO20 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P1 | GPIO_AD_B1_08 | D1 | GPIO1_IO24 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P2 | GPIO_AD_B1_09 | D2 | GPIO1_IO25 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P3 | GPIO_AD_B1_10 | D3 | GPIO1_IO26 | | | ++-----------+---------------+----------+---------------+ UART1 | UART_8 | +| P4 | GPIO_AD_B1_11 | D4 | GPIO1_IO27 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P5 | GPIO_AD_B1_12 | D5 | GPIO1_IO28 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P6 | GPIO_AD_B1_15 | D6 | GPIO1_IO31 | | | ++-----------+---------------+----------+---------------+ | | +| P7 | GPIO_AD_B1_14 | D7 | GPIO1_IO30 | SPI0 | SPI_3 | ++-----------+---------------+----------+---------------+ | | +| P8 | GPIO_AD_B1_13 | D8 | GPIO1_IO29 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P9 | GPIO_AD_B1_03 | D9 | GPIO1_IO19 | | | ++-----------+---------------+----------+---------------+ UART0 | UART_2 | +| P10 | GPIO_AD_B1_02 | D10 | GPIO1_IO18 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P11 | GPIO_AD_B1_05 | D11 | GPIO1_IO21 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P12 | GPIO_AD_B0_14 | D12 | GPIO1_IO14 | | | ++-----------+---------------+----------+---------------+ CAN0 | CAN_3 | +| P13 | GPIO_AD_B0_15 | D13 | GPIO1_IO15 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P14 | GPIO_B0_00 | D14 | GPIO2_IO00 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P15 | GPIO_B1_03 | D15 | GPIO2_IO19 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P16 | GPIO_B1_02 | D16 | GPIO2_IO18 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P17 | GPIO_B1_01 | D17 | GPIO2_IO17 | | | ++-----------+---------------+----------+---------------+ UART2 | UART_4 | +| P18 | GPIO_B1_00 | D18 | GPIO2_IO16 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P19 | GPIO_B1_15 | D19 | GPIO2_IO31 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P20 | GPIO_B1_14 | D20 | GPIO2_IO30 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P21 | GPIO_B0_03 | D21 | GPIO2_IO03 | | | ++-----------+---------------+----------+---------------+ | | +| P22 | GPIO_B0_02 | D22 | GPIO2_IO02 | SPI1 | SPI_4 | ++-----------+---------------+----------+---------------+ | | +| P23 | GPIO_B0_01 | D23 | GPIO2_IO01 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P24 | GPIO_B0_04 | D24 | GPIO2_IO04 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P25 | GPIO_B0_05 | D25 | GPIO2_IO05 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P26 | GPIO_B0_06 | D26 | GPIO2_IO06 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P27 | GPIO_B0_07 | D27 | GPIO2_IO07 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P28 | GPIO_B0_08 | D28 | GPIO2_IO08 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P29 | GPIO_B0_09 | D29 | GPIO2_IO09 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P30 | GPIO_B0_10 | D30 | GPIO2_IO10 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P31 | GPIO_B0_11 | D31 | GPIO2_IO11 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P32 | GPIO_B0_12 | D32 | GPIO2_IO12 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P33 | GPIO_B0_13 | D33 | GPIO2_IO13 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P34 | GPIO_B0_14 | D34 | GPIO2_IO14 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| P35 | GPIO_B0_15 | D35 | GPIO2_IO15 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| | GPIO_AD_B1_07 | | GPIO1_IO23 | | | ++-----------+---------------+----------+---------------+ I2C0 | I2C_3 | +| | GPIO_AD_B1_06 | | GPIO1_IO22 | | | ++-----------+---------------+----------+---------------+----------+---------------+ +| | GPIO_AD_B1_00 | | GPIO1_IO16 | | | ++-----------+---------------+----------+---------------+ I2C1 | I2C_1 | +| | GPIO_AD_B1_00 | | GPIO1_IO17 | | | ++-----------+---------------+----------+---------------+----------+---------------+ + + +Programming and Flash +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Console +===================== + +Connect a USB-to-serial adapter from your PC to corresponding UART pins of SwiftIO Feather. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +Connect a DAPLink debuger from your PC to corresponding SWD pins of SwiftIO Feather. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mm_feather + :goals: flash + +Open a serial terminal, reset the board (press the "reset" button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1-301-gd9c666a5abf8 *** + Hello World! mm_feather + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mm_feather + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1-301-gd9c666a5abf8 *** + Hello World! mm_feather + + +.. _MadMachine Homepage: + https://madmachine.io + +.. _SwiftIO API Reference: + https://swiftioapi.madmachine.io diff --git a/boards/arm/mm_feather/doc/mm_feather.jpg b/boards/arm/mm_feather/doc/mm_feather.jpg new file mode 100644 index 000000000000..43e2ff48eebb Binary files /dev/null and b/boards/arm/mm_feather/doc/mm_feather.jpg differ diff --git a/boards/arm/mm_swiftio/mmswiftio_flexspi_nor_config.c b/boards/arm/mm_feather/flexspi_nor_config.c similarity index 87% rename from boards/arm/mm_swiftio/mmswiftio_flexspi_nor_config.c rename to boards/arm/mm_feather/flexspi_nor_config.c index d7ddba3bd605..647dac001c92 100644 --- a/boards/arm/mm_swiftio/mmswiftio_flexspi_nor_config.c +++ b/boards/arm/mm_feather/flexspi_nor_config.c @@ -6,9 +6,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "mmswiftio_flexspi_nor_config.h" +#include -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER #if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) __attribute__((section(".boot_hdr.conf"))) #elif defined(__ICCARM__) @@ -40,4 +40,4 @@ const struct flexspi_nor_config_t Qspiflash_config = { .blockSize = 256u * 1024u, .isUniformBlockSize = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/mm_feather/mm_feather.dts b/boards/arm/mm_feather/mm_feather.dts new file mode 100644 index 000000000000..60e5c091e2d9 --- /dev/null +++ b/boards/arm/mm_feather/mm_feather.dts @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2021, MADMACHINE LIMITED + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "MM MM-FEATHER board"; + compatible = "nxp,mimxrt1062"; + + aliases { + led0 = &green_led; + led1 = &red_led; + led2 = &blue_led; + }; + + chosen { + zephyr,sram = &sdram0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + }; + + sdram0: memory@80000000 { + /* Micron MT48LC16M16A2B4-6AIT:G */ + device_type = "memory"; + reg = <0x80000000 DT_SIZE_M(32)>; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpio1 9 0>; + label = "RGB R"; + }; + + green_led: led_1 { + gpios = <&gpio1 10 0>; + label = "RGB G"; + }; + + blue_led: led_2 { + gpios = <&gpio1 11 0>; + label = "RGB B"; + }; + }; +}; + + +&flexspi { + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; + is25wp064: is25wp064@0 { + compatible = "nxp,imx-flexspi-nor"; + size = <67108864>; + label = "IS25WP064"; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [9d 70 17]; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart3 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart4 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart8 { + status = "okay"; + current-speed = <115200>; +}; + +&lpi2c1 { + status = "okay"; +}; + +&lpi2c3 { + status = "okay"; +}; + +&lpspi3 { + status = "okay"; + pcs-sck-delay = <2>; + sck-pcs-delay = <2>; + transfer-delay = <2>; +}; + +&lpspi4 { + status = "okay"; + pcs-sck-delay = <2>; + sck-pcs-delay = <2>; + transfer-delay = <2>; +}; + +&flexpwm1_pwm3 { + status = "okay"; +}; + +&flexpwm2_pwm0 { + status = "okay"; +}; + +&flexpwm2_pwm1 { + status = "okay"; +}; + +&flexpwm2_pwm2 { + status = "okay"; +}; + +&flexpwm2_pwm3 { + status = "okay"; +}; + +&flexpwm4_pwm0 { + status = "okay"; +}; + +&flexpwm4_pwm1 { + status = "okay"; +}; + +&flexpwm4_pwm2 { + status = "okay"; +}; + +&flexpwm4_pwm3 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + no-1-8-v; +}; diff --git a/boards/arm/mm_feather/mm_feather.yaml b/boards/arm/mm_feather/mm_feather.yaml new file mode 100644 index 000000000000..2645f42f5bc3 --- /dev/null +++ b/boards/arm/mm_feather/mm_feather.yaml @@ -0,0 +1,25 @@ +# +# Copyright (c) 2021, MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mm_feather +name: MM MM-FEATHER +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32768 +flash: 8192 +supported: + - counter + - sdhc + - gpio + - i2c + - dma + - uart + - pwm + - spi diff --git a/boards/arm/mm_feather/mm_feather_defconfig b/boards/arm/mm_feather/mm_feather_defconfig new file mode 100644 index 000000000000..5090ec4f17da --- /dev/null +++ b/boards/arm/mm_feather/mm_feather_defconfig @@ -0,0 +1,16 @@ +# +# Copyright (c) 2021, MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SOC_MIMXRT1062=y +CONFIG_SOC_SERIES_IMX_RT=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000 +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/mm_feather/mmfeather_sdram_ini_dcd.c b/boards/arm/mm_feather/mmfeather_sdram_ini_dcd.c new file mode 100644 index 000000000000..3bab1761d7c8 --- /dev/null +++ b/boards/arm/mm_feather/mmfeather_sdram_ini_dcd.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2021, MADMACHINE LIMITED + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +const uint8_t dcd_data[] = { + 0xD2, + + 0x04, 0x30, + + 0x41, + + 0xCC, 0x03, 0xAC, 0x04, + + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + + 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, + + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + + 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9, + + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, + + 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, + + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + + 0xCC, 0x00, 0x14, 0x04, + + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + + 0xCC, 0x00, 0x14, 0x04, + + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + + 0xCC, 0x00, 0x1C, 0x04, + + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 +}; + +#else +const uint8_t dcd_data[] = { 0x00 }; +#endif +#endif diff --git a/boards/arm/mm_feather/pinmux.c b/boards/arm/mm_feather/pinmux.c new file mode 100644 index 000000000000..0429035615d1 --- /dev/null +++ b/boards/arm/mm_feather/pinmux.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2021, MADMACHINE LIMITED + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) +static gpio_pin_config_t enet_gpio_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0, + .interruptMode = kGPIO_NoIntmode +}; +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC + +/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + *Speed Field: medium(100MHz) + *Open Drain Enable Field: Open Drain Disabled + *Pull / Keep Enable Field: Pull/Keeper Enabled + *Pull / Keep Select Field: Pull + *Pull Up / Down Config. Field: 47K Ohm Pull Up + *Hyst. Enable Field: Hysteresis Enabled. + */ + +static void mm_feather_usdhc_pinmux( + uint16_t nusdhc, bool init, + uint32_t speed, uint32_t strength) +{ + uint32_t cmd_data = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(1) | + IOMUXC_SW_PAD_CTL_PAD_DSE(strength); + uint32_t clk = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | + IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUS(0) | + IOMUXC_SW_PAD_CTL_PAD_DSE(strength); + + if (nusdhc == 0) { + if (init) { + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, + 0U); + IOMUXC_SetPinMux(/*SD_CD*/ + IOMUXC_GPIO_B1_12_GPIO2_IO28, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, + 0U); + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, + 0x10B0u); + IOMUXC_SetPinConfig(/*SD0_CD_SW*/ + IOMUXC_GPIO_B1_12_GPIO2_IO28, + 0x017089u); + } + + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, + cmd_data); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, + clk); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, + cmd_data); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, + cmd_data); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, + cmd_data); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, + cmd_data); + } +} +#endif + +static int mm_feather_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + CLOCK_EnableClock(kCLOCK_Iomuxc); + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + + + /* LED */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, 0); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_GPIO1_IO11, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL + /* LPUART1 TX/RX */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, + IOMUXC_SW_PAD_CTL_PAD_PUS(3) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, + IOMUXC_SW_PAD_CTL_PAD_PUS(3) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c3), okay) && CONFIG_I2C + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, 1); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, 1); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, + IOMUXC_SW_PAD_CTL_PAD_PUS(3) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, + IOMUXC_SW_PAD_CTL_PAD_PUS(3) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC + mm_feather_usdhc_pinmux(0, true, 2, 1); + imxrt_usdhc_pinmux_cb_register(mm_feather_usdhc_pinmux); +#endif + + return 0; +} + +SYS_INIT(mm_feather_init, PRE_KERNEL_1, 0); diff --git a/boards/arm/mm_swiftio/CMakeLists.txt b/boards/arm/mm_swiftio/CMakeLists.txt index 8552d7fd8899..0fb173ff7322 100644 --- a/boards/arm/mm_swiftio/CMakeLists.txt +++ b/boards/arm/mm_swiftio/CMakeLists.txt @@ -6,5 +6,5 @@ zephyr_library() zephyr_library_sources(pinmux.c) -zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR mmswiftio_flexspi_nor_config.c) +zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmswiftio_sdram_ini_dcd.c) diff --git a/boards/arm/mm_swiftio/flexspi_nor_config.c b/boards/arm/mm_swiftio/flexspi_nor_config.c new file mode 100644 index 000000000000..647dac001c92 --- /dev/null +++ b/boards/arm/mm_swiftio/flexspi_nor_config.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/mps2_an521/mps2_an521.yaml b/boards/arm/mps2_an521/mps2_an521.yaml index ab2008028a27..964258a32d9d 100644 --- a/boards/arm/mps2_an521/mps2_an521.yaml +++ b/boards/arm/mps2_an521/mps2_an521.yaml @@ -2,6 +2,8 @@ identifier: mps2_an521 name: ARM V2M MPS2-AN521 type: mcu arch: arm +ram: 4096 +flash: 4096 simulation: qemu toolchain: - gnuarmemb diff --git a/boards/arm/mps2_an521/mps2_an521_ns.yaml b/boards/arm/mps2_an521/mps2_an521_ns.yaml index 32371c39abfd..f17252b1b6af 100644 --- a/boards/arm/mps2_an521/mps2_an521_ns.yaml +++ b/boards/arm/mps2_an521/mps2_an521_ns.yaml @@ -2,6 +2,8 @@ identifier: mps2_an521_ns name: ARM V2M MPS2-AN521_ns type: mcu arch: arm +ram: 4096 +flash: 4096 simulation: qemu toolchain: - gnuarmemb diff --git a/boards/arm/mps2_an521/mps2_an521_remote.yaml b/boards/arm/mps2_an521/mps2_an521_remote.yaml index a63750a3161f..4fed8621bda6 100644 --- a/boards/arm/mps2_an521/mps2_an521_remote.yaml +++ b/boards/arm/mps2_an521/mps2_an521_remote.yaml @@ -2,6 +2,9 @@ identifier: mps2_an521_remote name: ARM V2M MPS2-AN521_remote type: mcu arch: arm +ram: 4096 +flash: 4096 +simulation: qemu toolchain: - gnuarmemb - zephyr diff --git a/boards/arm/mps3_an547/Kconfig.board b/boards/arm/mps3_an547/Kconfig.board index a628d71b7251..f8e755f12ed5 100644 --- a/boards/arm/mps3_an547/Kconfig.board +++ b/boards/arm/mps3_an547/Kconfig.board @@ -4,3 +4,4 @@ config BOARD_MPS3_AN547 bool "Arm Cortex-M55 (Corstone-300, SSE-300 w/Ethos-U55) on MPS3 (AN547)" depends on SOC_MPS3_AN547 + select QEMU_TARGET diff --git a/boards/arm/mps3_an547/Kconfig.defconfig b/boards/arm/mps3_an547/Kconfig.defconfig index 93571b1472ad..52c7b6bbcaa1 100644 --- a/boards/arm/mps3_an547/Kconfig.defconfig +++ b/boards/arm/mps3_an547/Kconfig.defconfig @@ -6,6 +6,14 @@ if BOARD_MPS3_AN547 config BOARD default "mps3_an547" +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped but QEMU +# will still permit bus access. +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET +endchoice + if GPIO config GPIO_CMSDK_AHB diff --git a/boards/arm/mps3_an547/board.cmake b/boards/arm/mps3_an547/board.cmake index 09519c2daeea..96a375776d32 100644 --- a/boards/arm/mps3_an547/board.cmake +++ b/boards/arm/mps3_an547/board.cmake @@ -10,7 +10,7 @@ # $ west build -b mps3_an547 samples/hello°world -DEMU_PLATFORM=qemu -t run if(NOT DEFINED EMU_PLATFORM) - set(EMU_PLATFORM armfvp) + set(EMU_PLATFORM qemu) endif() if (EMU_PLATFORM STREQUAL "qemu") diff --git a/boards/arm/mps3_an547/doc/index.rst b/boards/arm/mps3_an547/doc/index.rst index cdda585796fb..c1f2a82e7aea 100644 --- a/boards/arm/mps3_an547/doc/index.rst +++ b/boards/arm/mps3_an547/doc/index.rst @@ -209,8 +209,8 @@ at build time via: $ west build -b mps3_an547 samples/hello°world -DEMU_PLATFORM=qemu -t run -Note, however, that the Ethos-U55 FPU is not available in QEMU. If you require -the use of the FPU, please use the default FVP for device emulation. +Note, however, that the Ethos-U55 NPU is not available in QEMU. If you require +the use of the NPU, please use the default FVP for device emulation. .. _Corstone-300 FVP: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps diff --git a/boards/arm/mps3_an547/mps3_an547.yaml b/boards/arm/mps3_an547/mps3_an547.yaml index 72c29aca692b..d5d12b95ab78 100644 --- a/boards/arm/mps3_an547/mps3_an547.yaml +++ b/boards/arm/mps3_an547/mps3_an547.yaml @@ -8,6 +8,7 @@ identifier: mps3_an547 name: Arm MPS3-AN547 type: mcu arch: arm +simulation: qemu toolchain: - gnuarmemb - zephyr diff --git a/boards/arm/mps3_an547/mps3_an547_defconfig b/boards/arm/mps3_an547/mps3_an547_defconfig index eb670f3b9930..838aa4a8d61a 100644 --- a/boards/arm/mps3_an547/mps3_an547_defconfig +++ b/boards/arm/mps3_an547/mps3_an547_defconfig @@ -11,6 +11,7 @@ CONFIG_CORTEX_M_SYSTICK=y CONFIG_RUNTIME_NMI=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_ARM_MPU=y +CONFIG_QEMU_ICOUNT_SHIFT=7 # GPIOs CONFIG_GPIO=y diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts b/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts index 637a59c8880a..159d86aae8d4 100644 --- a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts +++ b/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts @@ -90,6 +90,10 @@ clock-frequency = ; }; +&i2c_ctrl0 { + status = "okay"; +}; + &tach1 { status = "okay"; pinctrl-0 = <&alt3_ta1_sl1>; /* Use TA1_SL1 (PIN40) as input pin */ diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts b/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts index 908e7d1e0cdd..aaa39a2e1ddc 100644 --- a/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts +++ b/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts @@ -103,6 +103,10 @@ clock-frequency = ; }; +&i2c_ctrl0 { + status = "okay"; +}; + &tach1 { status = "okay"; pinctrl-0 = <&alt3_ta1_sl1>; /* Use TA1_SL1 (PIN40) as input pin */ diff --git a/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig b/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig index f5e1b1703199..71cb76615ed5 100644 --- a/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig +++ b/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_NRF21540DK_NRF52840 config BOARD default "nrf21540dk_nrf52840" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts b/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts index 9b611f067a08..28775f8b4e49 100644 --- a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts +++ b/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts @@ -132,7 +132,6 @@ sw2 = &button2; sw3 = &button3; bootloader-led0 = &led0; - usbd0 = &usbd; }; }; @@ -158,14 +157,17 @@ current-speed = <115200>; tx-pin = <6>; rx-pin = <8>; + rx-pull-up; rts-pin = <5>; cts-pin = <7>; + cts-pull-up; }; arduino_serial: &uart1 { status = "okay"; current-speed = <115200>; rx-pin = <33>; + rx-pull-up; tx-pin = <34>; }; @@ -271,7 +273,7 @@ fem_spi: &spi3 { }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig b/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig index b38445803e91..705821fa71d2 100644 --- a/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig +++ b/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_NRF52833DK_NRF52820 config BOARD default "nrf52833dk_nrf52820" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.dts b/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.dts index 0c7033526f9a..03c2474f465e 100644 --- a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.dts +++ b/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.dts @@ -80,7 +80,6 @@ sw2 = &button2; sw3 = &button3; bootloader-led0 = &led0; - usbd0 = &usbd; }; }; @@ -98,8 +97,10 @@ current-speed = <115200>; tx-pin = <6>; rx-pin = <8>; + rx-pull-up; rts-pin = <5>; cts-pin = <7>; + cts-pull-up; }; &i2c0 { @@ -154,7 +155,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig b/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig index b1f86e06e420..6ec17b788646 100644 --- a/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig +++ b/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_NRF52833DK_NRF52833 config BOARD default "nrf52833dk_nrf52833" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts b/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts index b3c66aa551d2..ff91338809f6 100644 --- a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts +++ b/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts @@ -110,7 +110,6 @@ sw2 = &button2; sw3 = &button3; bootloader-led0 = &led0; - usbd0 = &usbd; }; }; @@ -136,14 +135,17 @@ current-speed = <115200>; tx-pin = <6>; rx-pin = <8>; + rx-pull-up; rts-pin = <5>; cts-pin = <7>; + cts-pull-up; }; arduino_serial: &uart1 { status = "okay"; current-speed = <115200>; rx-pin = <33>; + rx-pull-up; tx-pin = <34>; }; @@ -223,7 +225,7 @@ arduino_spi: &spi3 { }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf52840_blip/Kconfig.defconfig b/boards/arm/nrf52840_blip/Kconfig.defconfig index bad6dec42ea6..ab5424a1dd01 100644 --- a/boards/arm/nrf52840_blip/Kconfig.defconfig +++ b/boards/arm/nrf52840_blip/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_NRF52840_BLIP config BOARD default "nrf52840_blip" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/nrf52840_blip/nrf52840_blip.dts b/boards/arm/nrf52840_blip/nrf52840_blip.dts index add674e56b26..f7b7c56fe68a 100644 --- a/boards/arm/nrf52840_blip/nrf52840_blip.dts +++ b/boards/arm/nrf52840_blip/nrf52840_blip.dts @@ -170,7 +170,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf52840_mdk/Kconfig.defconfig b/boards/arm/nrf52840_mdk/Kconfig.defconfig index 4c77821fc518..8c321634996d 100644 --- a/boards/arm/nrf52840_mdk/Kconfig.defconfig +++ b/boards/arm/nrf52840_mdk/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_NRF52840_MDK config BOARD default "nrf52840_mdk" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk.dts b/boards/arm/nrf52840_mdk/nrf52840_mdk.dts index 2f7438a0af06..5487a457f3d3 100644 --- a/boards/arm/nrf52840_mdk/nrf52840_mdk.dts +++ b/boards/arm/nrf52840_mdk/nrf52840_mdk.dts @@ -196,7 +196,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf52840_papyr/Kconfig.defconfig b/boards/arm/nrf52840_papyr/Kconfig.defconfig index f9a421796b13..339d481404b4 100644 --- a/boards/arm/nrf52840_papyr/Kconfig.defconfig +++ b/boards/arm/nrf52840_papyr/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_NRF52840_PAPYR config BOARD default "nrf52840_papyr" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr.dts b/boards/arm/nrf52840_papyr/nrf52840_papyr.dts index 901c1a18a103..033145feb6f8 100644 --- a/boards/arm/nrf52840_papyr/nrf52840_papyr.dts +++ b/boards/arm/nrf52840_papyr/nrf52840_papyr.dts @@ -168,7 +168,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.dts b/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.dts index 36c17ec3523d..0afb486b1695 100644 --- a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.dts +++ b/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.dts @@ -102,8 +102,10 @@ current-speed = <115200>; tx-pin = <6>; rx-pin = <8>; + rx-pull-up; rts-pin = <5>; cts-pin = <7>; + cts-pull-up; }; &i2c0 { diff --git a/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig b/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig index bc06b9074f9e..31850c659375 100644 --- a/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig +++ b/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_NRF52840DK_NRF52840 config BOARD default "nrf52840dk_nrf52840" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts b/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts index b70e5afc0cc1..d991f386756e 100644 --- a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts +++ b/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts @@ -121,7 +121,6 @@ sw2 = &button2; sw3 = &button3; bootloader-led0 = &led0; - usbd0 = &usbd; }; }; @@ -147,14 +146,17 @@ current-speed = <115200>; tx-pin = <6>; rx-pin = <8>; + rx-pull-up; rts-pin = <5>; cts-pin = <7>; + cts-pull-up; }; arduino_serial: &uart1 { status = "okay"; current-speed = <115200>; rx-pin = <33>; + rx-pull-up; tx-pin = <34>; }; @@ -280,7 +282,7 @@ arduino_spi: &spi3 { }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml b/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml index 3d08a71a07ab..874e451eb537 100644 --- a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml +++ b/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml @@ -17,6 +17,7 @@ supported: - counter - gpio - i2c + - i2s - ieee802154 - pwm - spi diff --git a/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig b/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig index c4219d7df4ef..185c4f2f2162 100644 --- a/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig +++ b/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig @@ -24,22 +24,13 @@ config FLASH_LOAD_OFFSET default 0x1000 depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y +if USB_DEVICE_STACK # Enable UART driver, needed for CDC ACM config SERIAL - default USB_CDC_ACM - -config UART_INTERRUPT_DRIVEN - default USB_CDC_ACM + default y -endif # USB +endif # USB_DEVICE_STACK config BT_CTLR default BT diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.dts b/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.dts index e38d208ab2ab..3fe398457a01 100644 --- a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.dts +++ b/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.dts @@ -81,7 +81,6 @@ red-pwm-led = &red_pwm_led; green-pwm-led = &green_pwm_led; blue-pwm-led = &blue_pwm_led; - usbd0 = &usbd; }; }; @@ -107,8 +106,10 @@ current-speed = <115200>; tx-pin = <20>; rx-pin = <24>; + rx-pull-up; rts-pin = <17>; cts-pin = <22>; + cts-pull-up; }; &i2c0 { @@ -164,7 +165,7 @@ */ #include "fstab-stock.dts" -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig b/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig index 37b621689bab..1ceb2a20bce1 100644 --- a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig +++ b/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig @@ -13,9 +13,6 @@ CONFIG_HW_STACK_PROTECTION=y # enable GPIO CONFIG_GPIO=y -# enable console -CONFIG_CONSOLE=y - # additional board options CONFIG_GPIO_AS_PINRESET=y CONFIG_NFCT_PINS_AS_GPIOS=y diff --git a/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig b/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig index 79021436db1e..8d98a2710404 100644 --- a/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig +++ b/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig @@ -76,16 +76,6 @@ config FLASH_LOAD_SIZE endif # BOARD_NRF5340DK_NRF5340_CPUAPP_NS -if (BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS) && USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # (BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS) && USB - endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS config BOARD diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dts b/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dts index 845540a60c37..2312174b9529 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dts +++ b/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dts @@ -144,8 +144,10 @@ current-speed = <115200>; tx-pin = <20>; rx-pin = <22>; + rx-pull-up; rts-pin = <19>; cts-pin = <21>; + cts-pull-up; }; &pwm0 { @@ -198,6 +200,7 @@ arduino_serial: &uart1 { current-speed = <115200>; tx-pin = <33>; rx-pin = <32>; + rx-pull-up; }; arduino_i2c: &i2c1 {}; diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.dts b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.dts index f070b1e4804b..ab9e7d36b214 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.dts +++ b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.dts @@ -19,10 +19,6 @@ zephyr,sram-secure-partition = &sram0_s; zephyr,sram-non-secure-partition = &sram0_ns; }; - - aliases { - usbd0 = &usbd; - }; }; &spi2 { @@ -33,7 +29,7 @@ mosi-pin = <45>; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml index 738f12a81146..6eaded2454fa 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml +++ b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml @@ -11,6 +11,7 @@ flash: 1024 supported: - gpio - i2c + - i2s - pwm - watchdog - usb_cdc diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.dts b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.dts index 8693164008c9..a1c055bc14b8 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.dts +++ b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.dts @@ -17,13 +17,9 @@ zephyr,flash = &flash0; zephyr,code-partition = &slot0_ns_partition; }; - - aliases { - usbd0 = &usbd; - }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.dts b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.dts index b6c594386c2b..90263474dd1a 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.dts +++ b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.dts @@ -122,8 +122,10 @@ current-speed = <115200>; tx-pin = <33>; rx-pin = <32>; + rx-pull-up; rts-pin = <11>; cts-pin = <10>; + cts-pull-up; }; arduino_serial: &uart0{}; diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.dts b/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.dts index 0983e669cc72..9e130cbdaafb 100644 --- a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.dts +++ b/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.dts @@ -156,8 +156,10 @@ status = "okay"; tx-pin = <5>; rx-pin = <3>; + rx-pull-up; rts-pin = <40>; cts-pin = <7>; + cts-pull-up; }; &flash0 { diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dts b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dts index e64288f171b8..7f576284ceca 100644 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dts +++ b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dts @@ -159,8 +159,10 @@ current-speed = <115200>; tx-pin = <29>; rx-pin = <28>; + rx-pull-up; rts-pin = <27>; cts-pin = <26>; + cts-pull-up; }; arduino_serial: &uart1 { @@ -168,8 +170,10 @@ arduino_serial: &uart1 { current-speed = <115200>; tx-pin = <1>; rx-pin = <0>; + rx-pull-up; rts-pin = <14>; cts-pin = <15>; + cts-pull-up; }; &uart2 { diff --git a/boards/arm/nucleo_f091rc/doc/index.rst b/boards/arm/nucleo_f091rc/doc/index.rst index 7db29a93ac7f..438eac6dbdd2 100644 --- a/boards/arm/nucleo_f091rc/doc/index.rst +++ b/boards/arm/nucleo_f091rc/doc/index.rst @@ -102,6 +102,8 @@ The Zephyr nucleo_f091rc board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | DAC | on-chip | DAC controller | +-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported in this Zephyr port. diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc.dts b/boards/arm/nucleo_f091rc/nucleo_f091rc.dts index c7ab6a09e57c..5eeca19c85ba 100644 --- a/boards/arm/nucleo_f091rc/nucleo_f091rc.dts +++ b/boards/arm/nucleo_f091rc/nucleo_f091rc.dts @@ -127,3 +127,7 @@ status = "okay"; pinctrl-0 = <&dac_out1_pa4>; }; + +&dma1 { + status = "okay"; +}; diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml b/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml index 306d7f710f6f..080c1d6273ed 100644 --- a/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml +++ b/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml @@ -20,6 +20,7 @@ supported: - watchdog - adc - dac + - dma testing: ignore_tags: - net diff --git a/boards/arm/nucleo_f103rb/doc/index.rst b/boards/arm/nucleo_f103rb/doc/index.rst index 761e2736be0d..f28c8bd5c743 100644 --- a/boards/arm/nucleo_f103rb/doc/index.rst +++ b/boards/arm/nucleo_f103rb/doc/index.rst @@ -95,6 +95,8 @@ The Zephyr nucleo_f103rb board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | ADC | on-chip | ADC Controller | +-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported in this Zephyr port. diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb.dts b/boards/arm/nucleo_f103rb/nucleo_f103rb.dts index fae4a0e178d8..41462965bbaf 100644 --- a/boards/arm/nucleo_f103rb/nucleo_f103rb.dts +++ b/boards/arm/nucleo_f103rb/nucleo_f103rb.dts @@ -65,6 +65,7 @@ &usart1 { pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; current-speed = <115200>; + status = "okay"; }; &usart2 { @@ -115,6 +116,10 @@ status = "okay"; }; +&dma1 { + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml b/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml index 19ba971ea958..ef7d4302b503 100644 --- a/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml +++ b/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml @@ -17,3 +17,4 @@ supported: - pwm - watchdog - adc + - dma diff --git a/boards/arm/nucleo_f207zg/doc/index.rst b/boards/arm/nucleo_f207zg/doc/index.rst index 9751cbec91f2..e74edf3ed83d 100644 --- a/boards/arm/nucleo_f207zg/doc/index.rst +++ b/boards/arm/nucleo_f207zg/doc/index.rst @@ -104,6 +104,8 @@ The Zephyr nucleo_207zg board configuration supports the following hardware feat +-------------+------------+-------------------------------------+ | RNG | on-chip | Random Number Generator | +-------------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-------------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg.dts b/boards/arm/nucleo_f207zg/nucleo_f207zg.dts index 990e4f332c16..98b9821dc52f 100644 --- a/boards/arm/nucleo_f207zg/nucleo_f207zg.dts +++ b/boards/arm/nucleo_f207zg/nucleo_f207zg.dts @@ -99,7 +99,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; @@ -121,6 +121,10 @@ status = "okay"; }; +&dma2 { + status = "okay"; +}; + &mac { status = "okay"; pinctrl-0 = <ð_mdc_pc1 diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml b/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml index 6efdf1e08262..0856304d8801 100644 --- a/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml +++ b/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml @@ -23,3 +23,4 @@ supported: - backup_sram - pwm - rng + - dma diff --git a/boards/arm/nucleo_f412zg/Kconfig.defconfig b/boards/arm/nucleo_f412zg/Kconfig.defconfig index ffd358de25b7..428368d59279 100644 --- a/boards/arm/nucleo_f412zg/Kconfig.defconfig +++ b/boards/arm/nucleo_f412zg/Kconfig.defconfig @@ -10,9 +10,6 @@ config BOARD if NETWORKING -config USB - default y - config USB_DEVICE_STACK default y diff --git a/boards/arm/nucleo_f412zg/nucleo_f412zg.dts b/boards/arm/nucleo_f412zg/nucleo_f412zg.dts index 7be09a6bac88..51a77b255a36 100644 --- a/boards/arm/nucleo_f412zg/nucleo_f412zg.dts +++ b/boards/arm/nucleo_f412zg/nucleo_f412zg.dts @@ -99,7 +99,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/nucleo_f413zh/Kconfig.defconfig b/boards/arm/nucleo_f413zh/Kconfig.defconfig index b85289b4bbbb..e340a26c99d5 100644 --- a/boards/arm/nucleo_f413zh/Kconfig.defconfig +++ b/boards/arm/nucleo_f413zh/Kconfig.defconfig @@ -10,9 +10,6 @@ config BOARD if NETWORKING -config USB - default y - config USB_DEVICE_STACK default y diff --git a/boards/arm/nucleo_f413zh/nucleo_f413zh.dts b/boards/arm/nucleo_f413zh/nucleo_f413zh.dts index 587343ba72f1..396400896189 100644 --- a/boards/arm/nucleo_f413zh/nucleo_f413zh.dts +++ b/boards/arm/nucleo_f413zh/nucleo_f413zh.dts @@ -99,7 +99,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/nucleo_f429zi/doc/index.rst b/boards/arm/nucleo_f429zi/doc/index.rst index b5b9e9a161be..59a65ae9457e 100644 --- a/boards/arm/nucleo_f429zi/doc/index.rst +++ b/boards/arm/nucleo_f429zi/doc/index.rst @@ -109,6 +109,8 @@ The Zephyr nucleo_f429zi board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | DAC | on-chip | DAC Controller | +-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi.dts b/boards/arm/nucleo_f429zi/nucleo_f429zi.dts index e2a80e2d26c0..7ded78741d98 100644 --- a/boards/arm/nucleo_f429zi/nucleo_f429zi.dts +++ b/boards/arm/nucleo_f429zi/nucleo_f429zi.dts @@ -110,7 +110,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; @@ -137,6 +137,10 @@ status = "okay"; }; +&dma2 { + status = "okay"; +}; + &mac { status = "okay"; pinctrl-0 = <ð_mdc_pc1 diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi.yaml b/boards/arm/nucleo_f429zi/nucleo_f429zi.yaml index 338344ed6065..fd27edb6e845 100644 --- a/boards/arm/nucleo_f429zi/nucleo_f429zi.yaml +++ b/boards/arm/nucleo_f429zi/nucleo_f429zi.yaml @@ -22,3 +22,4 @@ supported: - watchdog - adc - dac + - dma diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg.dts b/boards/arm/nucleo_f746zg/nucleo_f746zg.dts index 376fa97d8314..474f7fcf3b6d 100644 --- a/boards/arm/nucleo_f746zg/nucleo_f746zg.dts +++ b/boards/arm/nucleo_f746zg/nucleo_f746zg.dts @@ -102,7 +102,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/nucleo_f756zg/nucleo_f756zg.dts b/boards/arm/nucleo_f756zg/nucleo_f756zg.dts index 672e354645b2..c6065c969e31 100644 --- a/boards/arm/nucleo_f756zg/nucleo_f756zg.dts +++ b/boards/arm/nucleo_f756zg/nucleo_f756zg.dts @@ -102,7 +102,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/nucleo_f767zi/nucleo_f767zi.dts b/boards/arm/nucleo_f767zi/nucleo_f767zi.dts index 2849224cc0da..8a0f5177b6fd 100644 --- a/boards/arm/nucleo_f767zi/nucleo_f767zi.dts +++ b/boards/arm/nucleo_f767zi/nucleo_f767zi.dts @@ -105,7 +105,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/nucleo_g071rb/board.cmake b/boards/arm/nucleo_g071rb/board.cmake index f54b2457490c..5c1981c81f64 100644 --- a/boards/arm/nucleo_g071rb/board.cmake +++ b/boards/arm/nucleo_g071rb/board.cmake @@ -5,7 +5,7 @@ board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") board_runner_args(jlink "--device=STM32G071RB" "--speed=4000") board_runner_args(stm32cubeprogrammer "--port=swd" "--reset=hw") -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) diff --git a/boards/arm/nucleo_g071rb/doc/index.rst b/boards/arm/nucleo_g071rb/doc/index.rst index 6c4b1c8baf94..186ff58b2c1c 100644 --- a/boards/arm/nucleo_g071rb/doc/index.rst +++ b/boards/arm/nucleo_g071rb/doc/index.rst @@ -154,27 +154,7 @@ flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -Nucleo G071RB board includes an ST-LINK/V2-1 embedded debug tool interface. - -This interface is not yet supported by the openocd version included in the Zephyr SDK. - -Instead, support can be enabled on pyocd by adding "pack" support with -the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g071rb - -Note: -To manually enable the openocd interface, You can still update, compile and install -a 'local' openocd from the official openocd repo http://openocd.zylin.com . -Then run the following openocd command where the '/usr/local/bin/openocd'is your path -for the freshly installed openocd, given by "$ which openocd" : - -.. code-block:: console - - $ west flash --openocd /usr/local/bin/openocd +Nucleo G071RB board includes an ST-LINK/V3 embedded debug tool interface. Flashing an application to Nucleo G071RB ---------------------------------------- diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb.dts b/boards/arm/nucleo_g071rb/nucleo_g071rb.dts index f1c4a914a742..8169ffabcafc 100644 --- a/boards/arm/nucleo_g071rb/nucleo_g071rb.dts +++ b/boards/arm/nucleo_g071rb/nucleo_g071rb.dts @@ -21,6 +21,21 @@ zephyr,flash = &flash0; }; + power-states { + stop0: state0 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <1>; + min-residency-us = <20>; + }; + stop1: state1 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <2>; + min-residency-us = <100>; + }; + }; + leds { compatible = "gpio-leds"; green_led_1: led_4 { @@ -140,3 +155,11 @@ }; }; }; + +&cpu0 { + cpu-power-states = <&stop0 &stop1>; +}; + +&lptim1 { + status = "okay"; +}; diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb.yaml b/boards/arm/nucleo_g071rb/nucleo_g071rb.yaml index a3e8f96062f4..991b4484fb14 100644 --- a/boards/arm/nucleo_g071rb/nucleo_g071rb.yaml +++ b/boards/arm/nucleo_g071rb/nucleo_g071rb.yaml @@ -22,3 +22,4 @@ supported: - adc - dac - dma + - lptim diff --git a/boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts b/boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts index fb9c0fe550ef..071bfbe75ed8 100644 --- a/boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts +++ b/boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts @@ -22,6 +22,21 @@ zephyr,code-partition = &slot0_partition; }; + power-states { + stop0: state0 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <1>; + min-residency-us = <20>; + }; + stop1: state1 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <2>; + min-residency-us = <100>; + }; + }; + leds { compatible = "gpio-leds"; green_led_1: led_4 { @@ -65,6 +80,11 @@ apb1-prescaler = <1>; }; +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>; current-speed = <115200>; @@ -90,7 +110,16 @@ pwm3: pwm { status = "okay"; st,prescaler = <10000>; - pinctrl-0 = <&tim3_ch1_pa6>; + pinctrl-0 = <&tim3_ch1_pb4>; + }; +}; + +&timers15 { + status = "okay"; + pwm15: pwm { + status = "okay"; + st,prescaler = <10000>; + pinctrl-0 = <&tim15_ch1_pb14>; }; }; @@ -113,8 +142,8 @@ }; &spi2 { - pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13 - &spi2_miso_pb14 &spi2_mosi_pb15>; + pinctrl-0 = <&spi2_nss_pd0 &spi2_sck_pd1 + &spi2_miso_pd3 &spi2_mosi_pd4>; status = "okay"; }; @@ -154,3 +183,11 @@ }; }; }; + +&cpu0 { + cpu-power-states = <&stop0 &stop1>; +}; + +&lptim1 { + status = "okay"; +}; diff --git a/boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml b/boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml index 1038e1a43d2d..d7dab13c4e60 100644 --- a/boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml +++ b/boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml @@ -18,3 +18,5 @@ supported: - spi - nvs - dma + - usb_device + - lptim diff --git a/boards/arm/nucleo_g474re/board.cmake b/boards/arm/nucleo_g474re/board.cmake index 3331330e265d..fb3697071afd 100644 --- a/boards/arm/nucleo_g474re/board.cmake +++ b/boards/arm/nucleo_g474re/board.cmake @@ -4,5 +4,5 @@ # to allow board re-flashing (see PR #23230) board_runner_args(pyocd "--target=stm32g474rbtx") -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/nucleo_g474re/doc/index.rst b/boards/arm/nucleo_g474re/doc/index.rst index 6a46cf250529..ff5a745c4125 100644 --- a/boards/arm/nucleo_g474re/doc/index.rst +++ b/boards/arm/nucleo_g474re/doc/index.rst @@ -197,26 +197,6 @@ Flashing Nucleo G474RE board includes an ST-LINK/V3E embedded debug tool interface. -This interface is not yet supported by the openocd version included in the Zephyr SDK. - -Instead, support can be enabled on pyocd by adding "pack" support with -the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g474re - -Note: -To manually enable the openocd interface, You can still update, compile and install -a 'local' openocd from the official openocd repo http://openocd.zylin.com . -Then run the following openocd command where the '/usr/local/bin/openocd'is your path -for the freshly installed openocd, given by "$ which openocd" : - -.. code-block:: console - - $ west flash --openocd /usr/local/bin/openocd - Flashing an application to Nucleo G474RE ---------------------------------------- diff --git a/boards/arm/nucleo_g474re/nucleo_g474re.dts b/boards/arm/nucleo_g474re/nucleo_g474re.dts index 576f5c2ecf70..0ad600a7f58b 100644 --- a/boards/arm/nucleo_g474re/nucleo_g474re.dts +++ b/boards/arm/nucleo_g474re/nucleo_g474re.dts @@ -116,7 +116,16 @@ pwm2: pwm { status = "okay"; - pinctrl-0 = <&tim2_ch1_pa5>; + pinctrl-0 = <&tim2_ch3_pb10>; + }; +}; + +&timers3 { + status = "okay"; + pwm3: pwm { + status = "okay"; + st,prescaler = <10000>; + pinctrl-0 = <&tim3_ch1_pb4>; }; }; diff --git a/boards/arm/nucleo_h723zg/doc/index.rst b/boards/arm/nucleo_h723zg/doc/index.rst index 8770037c9aa0..3df5540abffc 100644 --- a/boards/arm/nucleo_h723zg/doc/index.rst +++ b/boards/arm/nucleo_h723zg/doc/index.rst @@ -92,27 +92,29 @@ Supported Features The Zephyr nucleo_h723zg board configuration supports the following hardware features: -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -147,6 +149,12 @@ Serial Port Nucleo H723ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is assigned to UART3. Default settings are 115200 8N1. +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB52`` jumper on the back side of the board. + Programming and Debugging ************************* diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg.dts b/boards/arm/nucleo_h723zg/nucleo_h723zg.dts index 70b358be72e9..116a34d529cc 100644 --- a/boards/arm/nucleo_h723zg/nucleo_h723zg.dts +++ b/boards/arm/nucleo_h723zg/nucleo_h723zg.dts @@ -95,6 +95,12 @@ status = "okay"; }; +&usart2 { + pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>; + current-speed = <115200>; + status = "okay"; +}; + &rtc { status = "okay"; }; @@ -105,6 +111,10 @@ clock-frequency = ; }; +&backup_sram { + status = "okay"; +}; + &timers12 { status = "okay"; diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg.yaml b/boards/arm/nucleo_h723zg/nucleo_h723zg.yaml index 0d380ddc2b99..0539a8926fb6 100644 --- a/boards/arm/nucleo_h723zg/nucleo_h723zg.yaml +++ b/boards/arm/nucleo_h723zg/nucleo_h723zg.yaml @@ -17,3 +17,4 @@ supported: - i2c - pwm - netif:eth + - backup_sram diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi.dts b/boards/arm/nucleo_h743zi/nucleo_h743zi.dts index a86c5b56170c..372e121bae99 100644 --- a/boards/arm/nucleo_h743zi/nucleo_h743zi.dts +++ b/boards/arm/nucleo_h743zi/nucleo_h743zi.dts @@ -91,7 +91,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi.dts b/boards/arm/nucleo_h753zi/nucleo_h753zi.dts index 55b1b4626f69..484466320a69 100644 --- a/boards/arm/nucleo_h753zi/nucleo_h753zi.dts +++ b/boards/arm/nucleo_h753zi/nucleo_h753zi.dts @@ -91,7 +91,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/nucleo_l073rz/Kconfig.defconfig b/boards/arm/nucleo_l073rz/Kconfig.defconfig index 6a73209134a8..b165c4ae0021 100644 --- a/boards/arm/nucleo_l073rz/Kconfig.defconfig +++ b/boards/arm/nucleo_l073rz/Kconfig.defconfig @@ -12,4 +12,10 @@ config SPI_STM32_INTERRUPT default y depends on SPI +# FIXME: LSE not working as LPTIM clock source. Use LSI instead. +choice STM32_LPTIM_CLOCK + default STM32_LPTIM_CLOCK_LSI + depends on STM32_LPTIM_TIMER +endchoice + endif # BOARD_NUCLEO_L073RZ diff --git a/boards/arm/nucleo_l152re/doc/index.rst b/boards/arm/nucleo_l152re/doc/index.rst index e8dbf6ef1e28..a73ae28d9a32 100644 --- a/boards/arm/nucleo_l152re/doc/index.rst +++ b/boards/arm/nucleo_l152re/doc/index.rst @@ -98,6 +98,8 @@ The Zephyr nucleo_l152re board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | PWM | on-chip | PWM | +-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported in this Zephyr port. diff --git a/boards/arm/nucleo_l152re/nucleo_l152re.dts b/boards/arm/nucleo_l152re/nucleo_l152re.dts index 2d86e8c6dc29..16829e34a249 100644 --- a/boards/arm/nucleo_l152re/nucleo_l152re.dts +++ b/boards/arm/nucleo_l152re/nucleo_l152re.dts @@ -117,3 +117,7 @@ pinctrl-0 = <&tim3_ch1_pa6>; }; }; + +&dma1 { + status = "okay"; +}; diff --git a/boards/arm/nucleo_l152re/nucleo_l152re.yaml b/boards/arm/nucleo_l152re/nucleo_l152re.yaml index 3845a5b7f6fa..9ddaaf94d1d4 100644 --- a/boards/arm/nucleo_l152re/nucleo_l152re.yaml +++ b/boards/arm/nucleo_l152re/nucleo_l152re.yaml @@ -19,3 +19,4 @@ supported: - adc - dac - pwm + - dma diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg.dts b/boards/arm/nucleo_l476rg/nucleo_l476rg.dts index 2c5e1a13dd82..f57619020443 100644 --- a/boards/arm/nucleo_l476rg/nucleo_l476rg.dts +++ b/boards/arm/nucleo_l476rg/nucleo_l476rg.dts @@ -140,7 +140,17 @@ pwm2: pwm { status = "okay"; - pinctrl-0 = <&tim2_ch1_pa0>; + pinctrl-0 = <&tim2_ch3_pb10>; + }; +}; + +&timers3 { + status = "okay"; + + pwm3: pwm { + status = "okay"; + st,prescaler = <10000>; + pinctrl-0 = <&tim3_ch1_pb4>; }; }; diff --git a/boards/arm/nucleo_l4r5zi/Kconfig.defconfig b/boards/arm/nucleo_l4r5zi/Kconfig.defconfig index 7bcfc4f82be0..5b3db7604cbd 100644 --- a/boards/arm/nucleo_l4r5zi/Kconfig.defconfig +++ b/boards/arm/nucleo_l4r5zi/Kconfig.defconfig @@ -14,9 +14,6 @@ config SPI_STM32_INTERRUPT if NETWORKING -config USB - default y - config USB_DEVICE_STACK default y diff --git a/boards/arm/nucleo_l552ze_q/CMakeLists.txt b/boards/arm/nucleo_l552ze_q/CMakeLists.txt index 3f061ca42c86..dd0b75d97594 100644 --- a/boards/arm/nucleo_l552ze_q/CMakeLists.txt +++ b/boards/arm/nucleo_l552ze_q/CMakeLists.txt @@ -7,7 +7,7 @@ elseif(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "gnuarmemb") endif() if (CONFIG_BUILD_WITH_TFM) - set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands #Execute post build script postbuild.sh COMMAND ${CMAKE_BINARY_DIR}/tfm/postbuild.sh ${COMPILER_FULL_PATH} ) diff --git a/boards/arm/nucleo_u575zi_q/CMakeLists.txt b/boards/arm/nucleo_u575zi_q/CMakeLists.txt new file mode 100644 index 000000000000..5522a882264e --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "zephyr") + set(COMPILER_FULL_PATH ${ZEPHYR_SDK_INSTALL_DIR}/arm-zephyr-eabi/bin/arm-zephyr-eabi-gcc) +elseif(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "gnuarmemb") + set(COMPILER_FULL_PATH ${GNUARMEMB_TOOLCHAIN_PATH}/bin/arm-none-eabi-gcc) +endif() diff --git a/boards/arm/nucleo_u575zi_q/Kconfig.board b/boards/arm/nucleo_u575zi_q/Kconfig.board new file mode 100644 index 000000000000..1f08c09447e4 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/Kconfig.board @@ -0,0 +1,8 @@ +# STM32U575ZI Q Nucleo board configuration + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_U575ZI_Q + bool "Nucleo U575ZI Q Development Board" + depends on SOC_STM32U575XX diff --git a/boards/arm/nucleo_u575zi_q/Kconfig.defconfig b/boards/arm/nucleo_u575zi_q/Kconfig.defconfig new file mode 100644 index 000000000000..901d86a25515 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/Kconfig.defconfig @@ -0,0 +1,11 @@ +# STM32U575ZI Q Nucleo board configuration + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_U575ZI_Q + +config BOARD + default "nucleo_u575zi_q" + +endif # BOARD_NUCLEO_U575ZI_Q diff --git a/boards/arm/nucleo_u575zi_q/arduino_r3_connector.dtsi b/boards/arm/nucleo_u575zi_q/arduino_r3_connector.dtsi new file mode 100644 index 000000000000..b199c65989b0 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/arduino_r3_connector.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 3 0>, /* A0 */ + <1 0 &gpioa 2 0>, /* A1 */ + <2 0 &gpioc 3 0>, /* A2 */ + <3 0 &gpiob 0 0>, /* A3 */ + <4 0 &gpioc 1 0>, /* A4 */ + <5 0 &gpioc 0 0>, /* A5 */ + <6 0 &gpiog 8 0>, /* D0 */ + <7 0 &gpiog 7 0>, /* D1 */ + <8 0 &gpiof 15 0>, /* D2 */ + <9 0 &gpioe 13 0>, /* D3 */ + <10 0 &gpiof 14 0>, /* D4 */ + <11 0 &gpioe 11 0>, /* D5 */ + <12 0 &gpioe 9 0>, /* D6 */ + <13 0 &gpiof 13 0>, /* D7 */ + <14 0 &gpiof 12 0>, /* D8 */ + <15 0 &gpiod 15 0>, /* D9 */ + <16 0 &gpiod 14 0>, /* D10 */ + <17 0 &gpioa 7 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; diff --git a/boards/arm/nucleo_u575zi_q/board.cmake b/boards/arm/nucleo_u575zi_q/board.cmake new file mode 100644 index 000000000000..13bb91f44316 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/board.cmake @@ -0,0 +1,11 @@ +board_runner_args(stm32cubeprogrammer "--erase" "--port=swd" "--reset=hw") +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset=hw") + +board_runner_args(openocd "--tcl-port=6666") +board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable") +board_runner_args(openocd "--no-halt") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +# FIXME: openocd runner requires use of STMicro openocd fork. +# Check board documentation for more details. +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/nucleo_u575zi_q/doc/nucleou575zi_q.rst b/boards/arm/nucleo_u575zi_q/doc/nucleou575zi_q.rst new file mode 100644 index 000000000000..1141a2a31962 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/doc/nucleou575zi_q.rst @@ -0,0 +1,277 @@ +.. _nucleo_u575zi_q_board: + +ST Nucleo U575ZI Q +################## + +Overview +******** + +The Nucleo U575ZI Q board, featuring an ARM Cortex-M33 based STM32U575ZI MCU, +provides an affordable and flexible way for users to try out new concepts and +build prototypes by choosing from the various combinations of performance and +power consumption features. Here are some highlights of the Nucleo U575ZI Q +board: + + +- STM32U575ZI microcontroller in LQFP144 package +- Internal SMPS to generate V core logic supply +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V3E debugger/programmer +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - ST-Link V3E + +- Three users LEDs +- Two push-buttons: USER and RESET +- USB Type-C |trade| Sink device FS + +Hardware +******** + +The STM32U575xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) + +- Security + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure Firmware Update support with TF-M + - HASH hardware accelerator + - Active tampers + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - Internal 48 MHz with clock recovery + +- Power management + + - Embedded regulator (LDO) + - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling + +- RTC with HW calendar and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 17 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5 x 16-bit general purpose + - 4x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- ART accelerator + + - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and + external memories: up to 160 MHz, MPU, 240 DMIPS and DSP + - 4-Kbyte data cache for external memories + +- Memories + + - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles + - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON + - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - 2 Octo-SPI memory interfaces + +- Rich analog peripherals (independent supply) + + - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling + - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 2 12-bit DAC, low-power sample and hold + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- Up to 22 communication interfaces + + - USB Type-C / USB power delivery controller + - USB OTG 2.0 full-speed controller + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) + - 1x FDCAN + - 2x SDMMC interface + - 16- and 4-channel DMA controllers, functional in Stop mode + - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with + sound-activity detection + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + +- Graphic features + + - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation + - 1 digital camera interface + +- Mathematical co-processor + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + +More information about STM32U575ZI can be found here: + +- `STM32U575ZI on www.st.com`_ +- `STM32U575 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_u575zi_q board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +``boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig`` + + +Connections and IOs +=================== + +Nucleo U575ZI Q Board has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For mode details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- USER_PB : PC13 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PG2 + +System Clock +------------ + +Nucleo U575ZI Q System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +160MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +Nucleo U575ZI Q board has 6 U(S)ARTs. The Zephyr console output is assigned to +USART1. Default settings are 115200 8N1. + + +Programming +*********** + +Applications for the ``nucleo_u575zi_q`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + + +Flashing an application to Nucleo U575ZI Q +------------------------------------------ + +Connect the Nucleo U575ZI Q to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_u575zi_q + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +STM32U5 support is not currently supported in openocd. As a temporary workaround, +user can use `STMicroelectronics customized version of OpenOCD`_ to debug the +the Nucleo U575ZI Q. +For this you need to fetch this repo, checkout branch "openocd-cubeide-r3" and +build openocd following the instructions provided in the README of the project. +Then, build zephyr project indicating the openocd location in west build command. + +Here is an example for the :ref:`blinky-sample` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_u575zi_q + :gen-args: -DOPENOCD="/openocd/src/openocd" -DOPENOCD_DEFAULT_PATH="/openocd/tcl/" + :goals: build + +Then, indicate openocd as the chosen runner in flash and debug commands: + + + .. code-block:: console + + $ west flash -r openocd + $ west debug -r openocd + + +.. _STM32 Nucleo-144 board User Manual: + http://www.st.com/resource/en/user_manual/dm00615305.pdf + +.. _STM32U575ZI on www.st.com: + http://www.st.com/en/microcontrollers/stm32u575zi.html + +.. _STM32U575 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STMicroelectronics customized version of OpenOCD: + https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi b/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi new file mode 100644 index 000000000000..16d564cdda4a --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "arduino_r3_connector.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + green_led_1: led_1 { + gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + blue_led_1: led_2 { + gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + red_led_1: led_3 { + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + label = "User LD3"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_msis { + status = "okay"; + msi-range = <4>; + msi-pll-mode; +}; + +&pll1 { + div-m = <1>; + mul-n = <80>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_msis>; + status = "okay"; +}; + +&rcc { + clocks = <&pll1>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; + apb3-prescaler = <1>; +}; diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.dts b/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.dts new file mode 100644 index 000000000000..3557bd2c4e44 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "nucleo_u575zi_q-common.dtsi" + +/ { + model = "STMicroelectronics STM32U575ZI-NUCLEO-Q board"; + compatible = "st,stm32u575zi-nucleo-q"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + led0 = &blue_led_1; + sw0 = &user_button; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + current-speed = <115200>; + status = "okay"; +}; diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.yaml b/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.yaml new file mode 100644 index 000000000000..061f696ca9a1 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.yaml @@ -0,0 +1,11 @@ +identifier: nucleo_u575zi_q +name: ST Nucleo U575ZI Q +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio +ram: 786 +flash: 2048 diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig b/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig new file mode 100644 index 000000000000..b5656b326af5 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_STM32U5X=y +CONFIG_SOC_STM32U575XX=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable pinmux +CONFIG_PINMUX=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable clock +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/nucleo_u575zi_q/support/openocd.cfg b/boards/arm/nucleo_u575zi_q/support/openocd.cfg new file mode 100644 index 000000000000..2cac8fc0af62 --- /dev/null +++ b/boards/arm/nucleo_u575zi_q/support/openocd.cfg @@ -0,0 +1,44 @@ +source [find interface/stlink-dap.cfg] + +set WORKAREASIZE 0x8000 + +transport select "dapdirect_swd" + +set CHIPNAME STM32U575ZITxQ +set BOARDNAME NUCLEO-U575ZI-Q + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# STlink Debug clock frequency +set CLOCK_FREQ 8000 + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 + +# ACCESS PORT NUMBER +set AP_NUM 0 +# GDB PORT +set GDB_PORT 3333 + +# BCTM CPU variables + +source [find target/stm32u5x.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts index a0acad10fa65..b8122d6c1754 100644 --- a/boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts +++ b/boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts @@ -133,11 +133,21 @@ status = "okay"; }; +&timers1 { + status = "okay"; + + pwm1: pwm { + status = "okay"; + st,prescaler = <10000>; + pinctrl-0 = <&tim1_ch1_pa8>; + }; +}; + &timers2 { status = "okay"; pwm2: pwm { status = "okay"; - pinctrl-0 = <&tim2_ch1_pa0>; + pinctrl-0 = <&tim2_ch1_pa15>; }; }; @@ -160,7 +170,7 @@ status = "okay"; }; -&usb { +zephyr_udc0: &usb { status = "okay"; pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; }; @@ -179,9 +189,9 @@ #address-cells = <1>; #size-cells = <1>; - /* Set all partitions with first 812K of flash */ - /* last 212K are reseved for M0 usage */ - /* Configure partitions to make use of the whole 812K */ + /* Set all partitions with first 808K of flash */ + /* last 216K are reseved for M0 usage */ + /* Configure partitions to make use of the whole 808K */ boot_partition: partition@0 { label = "mcuboot"; @@ -201,7 +211,7 @@ }; storage_partition: partition@c8000 { label = "storage"; - reg = <0x000c8000 0x3000>; + reg = <0x000c8000 0x2000>; }; }; diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig b/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig index 7efb83ea74d5..c88bca11190d 100644 --- a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig +++ b/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=192000000 # enable uart driver CONFIG_SERIAL=y -CONFIG_UART_NUVOTON=y +CONFIG_UART_NUMICRO=y # console CONFIG_CONSOLE=y diff --git a/boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts b/boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts index 9ad72d3e135f..d69a679b0b6b 100644 --- a/boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts +++ b/boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts @@ -96,7 +96,7 @@ usb_otg1: &usbotg_fs { status = "disabled"; }; -usb_otg2: &usbotg_hs { +zephyr_udc0: &usbotg_hs { pinctrl-0 = <&usb_otg_hs_dm_pb14 &usb_otg_hs_dp_pb15>; status = "okay"; }; diff --git a/boards/arm/olimexino_stm32/Kconfig.board b/boards/arm/olimexino_stm32/Kconfig.board index c26c4417d65d..163bba9fe43b 100644 --- a/boards/arm/olimexino_stm32/Kconfig.board +++ b/boards/arm/olimexino_stm32/Kconfig.board @@ -6,4 +6,4 @@ config BOARD_OLIMEXINO_STM32 bool "OLIMEXINO-STM32 Development Board" depends on SOC_STM32F103XB - select USB_DC_STM32_DISCONN_ENABLE if USB + select USB_DC_STM32_DISCONN_ENABLE if USB_DEVICE_DRIVER diff --git a/boards/arm/olimexino_stm32/olimexino_stm32.dts b/boards/arm/olimexino_stm32/olimexino_stm32.dts index 087cc1633d25..c06d22cb1404 100644 --- a/boards/arm/olimexino_stm32/olimexino_stm32.dts +++ b/boards/arm/olimexino_stm32/olimexino_stm32.dts @@ -119,7 +119,7 @@ uext_serial: &usart1 {}; }; }; -&usb { +zephyr_udc0: &usb { status = "okay"; disconnect-gpios = <&gpioc 12 GPIO_ACTIVE_LOW>; pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; diff --git a/boards/arm/particle_argon/Kconfig.defconfig b/boards/arm/particle_argon/Kconfig.defconfig index 58be02e64555..df988c09cd80 100644 --- a/boards/arm/particle_argon/Kconfig.defconfig +++ b/boards/arm/particle_argon/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_PARTICLE_ARGON config BOARD default "particle_argon" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/particle_argon/dts/mesh_feather.dtsi b/boards/arm/particle_argon/dts/mesh_feather.dtsi index 4ab1ee7c6c76..eca68bd40aac 100644 --- a/boards/arm/particle_argon/dts/mesh_feather.dtsi +++ b/boards/arm/particle_argon/dts/mesh_feather.dtsi @@ -225,7 +225,7 @@ feather_serial: &uart0 { /* feather UART1 */ /* optional mesh_feather_uart1_rtscts.dtsi */ }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/particle_boron/Kconfig.defconfig b/boards/arm/particle_boron/Kconfig.defconfig index e386f02a122b..9352289086c6 100644 --- a/boards/arm/particle_boron/Kconfig.defconfig +++ b/boards/arm/particle_boron/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_PARTICLE_BORON config BOARD default "particle_boron" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/particle_boron/dts/mesh_feather.dtsi b/boards/arm/particle_boron/dts/mesh_feather.dtsi index 4ab1ee7c6c76..eca68bd40aac 100644 --- a/boards/arm/particle_boron/dts/mesh_feather.dtsi +++ b/boards/arm/particle_boron/dts/mesh_feather.dtsi @@ -225,7 +225,7 @@ feather_serial: &uart0 { /* feather UART1 */ /* optional mesh_feather_uart1_rtscts.dtsi */ }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/particle_boron/particle_boron.dts b/boards/arm/particle_boron/particle_boron.dts index ceb94b33da78..3c0bd0ae1b54 100644 --- a/boards/arm/particle_boron/particle_boron.dts +++ b/boards/arm/particle_boron/particle_boron.dts @@ -43,7 +43,7 @@ hw-flow-control; sara_r4 { - compatible = "ublox,sara-r4"; + compatible = "u-blox,sara-r4"; label = "ublox-sara-r4"; status = "okay"; diff --git a/boards/arm/particle_xenon/Kconfig.defconfig b/boards/arm/particle_xenon/Kconfig.defconfig index 760b5d06e60d..858a1230726d 100644 --- a/boards/arm/particle_xenon/Kconfig.defconfig +++ b/boards/arm/particle_xenon/Kconfig.defconfig @@ -9,16 +9,6 @@ if BOARD_PARTICLE_XENON config BOARD default "particle_xenon" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/particle_xenon/dts/mesh_feather.dtsi b/boards/arm/particle_xenon/dts/mesh_feather.dtsi index 4ab1ee7c6c76..eca68bd40aac 100644 --- a/boards/arm/particle_xenon/dts/mesh_feather.dtsi +++ b/boards/arm/particle_xenon/dts/mesh_feather.dtsi @@ -225,7 +225,7 @@ feather_serial: &uart0 { /* feather UART1 */ /* optional mesh_feather_uart1_rtscts.dtsi */ }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0.dts b/boards/arm/pinetime_devkit0/pinetime_devkit0.dts index e69df67df636..f2088a4df097 100644 --- a/boards/arm/pinetime_devkit0/pinetime_devkit0.dts +++ b/boards/arm/pinetime_devkit0/pinetime_devkit0.dts @@ -100,14 +100,14 @@ /* TianYiHeXin HRS3300 PPG Hear Rate Sensor (800KHz) */ hrs3300: hrs3300@44 { - compatible = "tian-yi-he-xin,hrs3300"; + compatible = "tian-yi-he-xin-hrs3300"; reg = <0x44>; label = "HRS3300"; }; /* Hynitron CST816S Capacitive Touch Controller (400KHz) */ cst816s: cst816s@15 { - compatible = "hynitron,cst816s"; + compatible = "hynitron-cst816s"; reg = <0x15>; label = "CST816S"; irq-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; @@ -126,7 +126,7 @@ /* Macronix MX25L CMOS Flash Memory */ mx25l: mx25l@0 { - compatible = "macronix,cmos-mx25l"; + compatible = "mxicy,cmos-mx25l"; reg = <0>; spi-max-frequency = <8000000>; /* 8MHz */ label = "CMOS MX25L"; diff --git a/boards/arm/pinnacle_100_dvk/Kconfig.defconfig b/boards/arm/pinnacle_100_dvk/Kconfig.defconfig index 90d1ee2af708..a560f49a579a 100644 --- a/boards/arm/pinnacle_100_dvk/Kconfig.defconfig +++ b/boards/arm/pinnacle_100_dvk/Kconfig.defconfig @@ -11,16 +11,6 @@ config BOARD config MODEM_HL7800 default NETWORKING -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config IEEE802154_NRF5 default y depends on IEEE802154 diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts b/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts index 1a596279e30d..883f2bff1ab1 100644 --- a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts +++ b/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts @@ -116,7 +116,6 @@ mdm-wake-gpios = <&gpio1 13 0>; mdm-pwr-on-gpios = <&gpio1 2 0>; mdm-fast-shutd-gpios = <&gpio1 14 0>; - mdm-uart-dtr-gpios = <&gpio0 24 0>; mdm-vgpio-gpios = <&gpio1 11 0>; mdm-uart-dsr-gpios = <&gpio0 25 0>; mdm-uart-cts-gpios = <&gpio0 15 0>; @@ -236,7 +235,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig b/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig index c23640113295..b10a6046eda6 100644 --- a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig +++ b/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig @@ -1,4 +1,4 @@ -# Copyright (c) 2020 Laird Connectivity +# Copyright (c) 2020-2021 Laird Connectivity # SPDX-License-Identifier: Apache-2.0 @@ -12,15 +12,19 @@ CONFIG_ARM_MPU=y # Enable RTT CONFIG_USE_SEGGER_RTT=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y -# enable uart driver +# Enable uart driver CONFIG_SERIAL=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# additional board options +# Additional board options CONFIG_GPIO_AS_PINRESET=y + +# 32KHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y diff --git a/boards/arm/qemu_cortex_r5/Kconfig.defconfig b/boards/arm/qemu_cortex_r5/Kconfig.defconfig index 3071e8d4f475..9cac36e1ee6b 100644 --- a/boards/arm/qemu_cortex_r5/Kconfig.defconfig +++ b/boards/arm/qemu_cortex_r5/Kconfig.defconfig @@ -9,4 +9,11 @@ config BUILD_OUTPUT_BIN config BOARD default "qemu_cortex_r5" +if USERSPACE + +config COMPILER_ISA_THUMB2 + default n + +endif + endif # BOARD_QEMU_CORTEX_R5 diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig b/boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig index 2d02b2c9254f..e40aebce522b 100644 --- a/boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig +++ b/boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig @@ -17,3 +17,4 @@ CONFIG_UART_CONSOLE=y CONFIG_UART_XLNX_PS=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_ARM_MPU=y diff --git a/boards/arm/quick_feather/quick_feather.dts b/boards/arm/quick_feather/quick_feather.dts index 63b93160e29f..caf26e039c92 100644 --- a/boards/arm/quick_feather/quick_feather.dts +++ b/boards/arm/quick_feather/quick_feather.dts @@ -50,6 +50,10 @@ label = "User Push Button 0"; }; }; + + fpga { + status = "okay"; + }; }; &cpu0 { diff --git a/boards/arm/rak4631_nrf52840/Kconfig.defconfig b/boards/arm/rak4631_nrf52840/Kconfig.defconfig index 46d127f30016..10a6070f95b6 100644 --- a/boards/arm/rak4631_nrf52840/Kconfig.defconfig +++ b/boards/arm/rak4631_nrf52840/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_RAK4631_NRF52840 config BOARD default "rak4631_nrf52840" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840.dts b/boards/arm/rak4631_nrf52840/rak4631_nrf52840.dts index 2f36faa351a4..3fd8144d8bd7 100644 --- a/boards/arm/rak4631_nrf52840/rak4631_nrf52840.dts +++ b/boards/arm/rak4631_nrf52840/rak4631_nrf52840.dts @@ -160,7 +160,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/rak5010_nrf52840/Kconfig.defconfig b/boards/arm/rak5010_nrf52840/Kconfig.defconfig index e42682979f10..502e1d8b7f69 100644 --- a/boards/arm/rak5010_nrf52840/Kconfig.defconfig +++ b/boards/arm/rak5010_nrf52840/Kconfig.defconfig @@ -11,16 +11,6 @@ config BOARD config MODEM_QUECTEL_BG9X default y -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840.dts b/boards/arm/rak5010_nrf52840/rak5010_nrf52840.dts index 005583b88f04..084529e291d7 100644 --- a/boards/arm/rak5010_nrf52840/rak5010_nrf52840.dts +++ b/boards/arm/rak5010_nrf52840/rak5010_nrf52840.dts @@ -74,7 +74,6 @@ }; &uart1 { - compatible = "nordic,nrf-uart"; current-speed = <115200>; status = "okay"; tx-pin = <33>; @@ -170,7 +169,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/rcar_h3ulcb/board.cmake b/boards/arm/rcar_h3ulcb/board.cmake index 9881313609aa..b106c562c540 100644 --- a/boards/arm/rcar_h3ulcb/board.cmake +++ b/boards/arm/rcar_h3ulcb/board.cmake @@ -1 +1,3 @@ # SPDX-License-Identifier: Apache-2.0 +board_runner_args(openocd "--use-elf") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst b/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst index ed496be13a74..95114c799164 100644 --- a/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst +++ b/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst @@ -17,7 +17,7 @@ It is possible to order 2 different types of H3 Starter Kit Boards, one with Eth :height: 288px :alt: R-Car starter kit -.. Note:: The H3ULCB board can be plugged on a Renesas Kingfisher Infotainment daughter board through COM Express connector in order to physically access more I/O. CAUTION : In this case, power supply is managed by the daughter board. +.. note:: The H3ULCB board can be plugged on a Renesas Kingfisher Infotainment daughter board through COM Express connector in order to physically access more I/O. CAUTION: In this case, power supply is managed by the daughter board. More information about the board can be found at `Renesas R-Car Starter Kit website`_. @@ -32,9 +32,9 @@ Hardware capabilities for the H3ULCB for can be found on the `eLinux H3SK page`_ :height: 280px :alt: R-Car starter kit features -.. Note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. +.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. -More information about the SoC that equips the board can be found here : +More information about the SoC that equips the board can be found here: - `Renesas R-Car H3 chip`_ @@ -53,6 +53,14 @@ Here is the current supported features when running Zephyr Project on the R-Car | GPIO | gpio | | +-----------+------------------------------+--------------------------------+ | UART | uart | serial port-polling | ++ + + + +| | FT232RQ / CP2102 | serial port-interrupt | ++-----------+------------------------------+--------------------------------+ +| CAN | can | normal mode | ++ + + + +| | TCAN332GDCNT | loopback mode | ++-----------+------------------------------+--------------------------------+ +| I2C | i2c | interrupt driven | +-----------+------------------------------+--------------------------------+ It's also currently possible to write on the ram console. @@ -62,37 +70,37 @@ More features will be supported soon. Connections and IOs =================== -H3ULCB Board : ------------------- +H3ULCB Board +------------ -Here are official IOs figures from eLinux for H3ULCB board : +Here are official IOs figures from eLinux for H3ULCB board: `H3SK top view`_ `H3SK bottom view`_ -Kingfisher Infotainment daughter board : ----------------------------------------- +Kingfisher Infotainment daughter board +-------------------------------------- When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. -Here are official IOs figures from eLinux for Kingfisher Infotainment board : +Here are official IOs figures from eLinux for Kingfisher Infotainment board: `Kingfisher top view`_ `Kingfisher bottom view`_ -GPIO : ------- +GPIO +---- By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software contollable LED 'LED5' can be used as output. -UART : ------- +UART +---- H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. -Here is information about these serial ports : +Here is information about these serial ports: +--------------------+-------------------+--------------------+-----------+--------------------------------------+ | Physical Interface | Physical Location | Software Interface | Converter | Further Information | @@ -104,9 +112,9 @@ Here is information about these serial ports : | CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | +--------------------+-------------------+--------------------+-----------+--------------------------------------+ -.. Note:: The Zephyr console output is assigned to SCIF1 (commonly used on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default. +.. note:: The Zephyr console output is assigned to SCIF1 (commonly used on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default. -Here is CN04 UART interface pinout (depending on your Kingfisher board version) : +Here is CN04 UART interface pinout (depending on your Kingfisher board version): +--------+----------+----------+ | Signal | Pin KF03 | Pin KF04 | @@ -122,60 +130,110 @@ Here is CN04 UART interface pinout (depending on your Kingfisher board version) | GND | 9 | 6 | +--------+----------+----------+ +CAN +--- + +H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. + ++--------------------+--------------------+--------------+ +| Physical Interface | Software Interface | Transceiver | ++====================+====================+==============+ +| CN17 | CAN0 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ +| CN18 | CAN1 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ + +.. note:: Interfaces are set to 125 kbit/s by default. + +The following table lists CAN physical interfaces pinout: + ++-----+--------+ +| Pin | Signal | ++=====+========+ +| 1 | CANH | ++-----+--------+ +| 2 | CANL | ++-----+--------+ +| 3 | GND | ++-----+--------+ + +I2C +--- + +H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. + +I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. + +Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. + Programming and Debugging ************************* -The Cortex®-R7 of rcar_h3ulcb board needs to be started by the Cortex®-A cores. Cortex®-A cores are responsible to load the Cortex®-R7 binary application into the RAM, and get the Cortex®-R7 out of reset. The Cortex®-A can currently perform these steps at bootloader level. +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. + +.. note:: + See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. -Building +Configuring a Console +===================== + +Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing ======== +First of all, open your serial terminal. + Applications for the ``rcar_h3ulcb_cr7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: rcar_h3ulcb_cr7 - :goals: build - -Debugging -========= -You can debug an application using OpenOCD and GDB. The Solution proposed below is using a OpenOCD custom version that support R-Car ULCB boards Cortex®-R7. + :goals: flash -Get Renesas ready OpenOCD version ---------------------------------- +You should see the following message in the terminal: -.. code-block:: bash +.. code-block:: console - git clone --branch renesas https://github.com/iotbzh/openocd.git - cd openocd - ./bootstrap - ./configure - make - sudo make install + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb_cr7 -Start OpenOCD -------------- - -.. code-block:: bash - - cd openocd - sudo openocd -f tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg -f tcl/board/renesas_h3ulcb.cfg +Debugging +========= -In a new terminal session +First of all, open your serial terminal. -.. code-block:: bash +Here is an example for the :ref:`hello_world` application. - telnet 127.0.0.1 4444 - r8a77950.r7 arp_examine +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb_cr7 + :goals: debug -Start Debugging ---------------- +You will then get access to a GDB session for debug. -In a new terminal session +By continuing the app, you should see the following message in the terminal: -.. code-block:: bash +.. code-block:: console - {ZEPHYR_SDK}/arm-zephyr-eabi/bin/arm-zephyr-eabi-gdb {APP_BUILD_DIR}/zephyr/zephyr.elf + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb_cr7 References ********** @@ -208,3 +266,6 @@ References .. _Kingfisher bottom view: https://elinux.org/images/0/06/Kfisher_bot_specs.png + +.. _Install a toolchain: + https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml index e9da1501faf8..61f8cbc3ac2a 100644 --- a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml +++ b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml @@ -5,4 +5,12 @@ arch: arm toolchain: - zephyr - gnuarmemb -ram: 768 +supported: + - i2c + - can + - gpio + - clock_control + - uart +testing: + ignore_tags: + - isotp diff --git a/boards/arm/rcar_h3ulcb/support/openocd.cfg b/boards/arm/rcar_h3ulcb/support/openocd.cfg new file mode 100644 index 000000000000..0395cb3efebf --- /dev/null +++ b/boards/arm/rcar_h3ulcb/support/openocd.cfg @@ -0,0 +1,88 @@ +# Renesas R-Car Gen3 H3ULCB Cortex-R7 Board Config + +source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg] +source [find target/renesas_rcar_reset_common.cfg] +set _CHIPNAME r8a77951 +set DAP_TAPID 0x5ba00477 +set CA57_0_DBGBASE 0x80410000 +set CA57_0_CTIBASE 0x80420000 +set CR7_DBGBASE 0x80910000 +set CR7_CTIBASE 0x80918000 + +adapter srst delay 1000 +adapter speed 20000 +global $_CHIPNAME +transport select jtag + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $DAP_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +cti create $_CHIPNAME.r7.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CR7_CTIBASE +target create $_CHIPNAME.r7 cortex_r4 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CR7_DBGBASE -defer-examine + +$_CHIPNAME.r7 configure -rtos auto + +cti create $_CHIPNAME.a57.0.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CA57_0_CTIBASE +target create $_CHIPNAME.a57.0 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CA57_0_DBGBASE -cti $_CHIPNAME.a57.0.cti + +proc reset_cr7 { assert } { + global _CHIPNAME + if { $assert == 1 } { + # Software Reset Register 2 Bit(22) Arm Realtime core + $_CHIPNAME.a57.0 mww 0xe61500b0 0x00400000 + } else { + # Software Reset Clearing Register 2 Bit(22) Arm Realtime core + $_CHIPNAME.a57.0 mww 0xe6150948 0x00400000 + } +} + +# This function make use of A5x processor to: +# - Power on the CR7 (PWRONCR7) +# - Set the boot address (CR7BAR) +# - Halt the processor +# - Deassert the CR7 reset +proc start_cr7 { args } { + global _CHIPNAME + + targets $_CHIPNAME.a57.0 + $_CHIPNAME.a57.0 arp_halt + + # CR7BAR RBAR [31:18] BAREN bit(4) + $_CHIPNAME.a57.0 mww 0xe6160070 0x40040010 + + # PWRONCR7 + $_CHIPNAME.a57.0 mww 0xe618024c 1 + # Wait until power is on. Also possible to + # poll PWRSR7 and CR7PSTR register. + sleep 100 + + $_CHIPNAME.r7 arp_examine + catch { $_CHIPNAME.r7 arp_halt } + reset_cr7 0 + + # resume a5x processor or cmt timer will not run + resume + # set CR7 processor as default target for future commands + targets $_CHIPNAME.r7 +} + +$_CHIPNAME.r7 configure -event reset-end { + global _CHIPNAME + targets $_CHIPNAME.a57.0 + # Resume the A57 processor and gives + # enough time to A57 bootloaders to set-up dram + # clocks, power management, security groups + resume + sleep 500 + $_CHIPNAME.a57.0 arp_halt + $_CHIPNAME.a57.0 arp_poll + start_cr7 +} + +$_CHIPNAME.a57.0 configure -event examine-end { + start_cr7 +} + +$_CHIPNAME.r7 configure -event gdb-attach { + reset halt +} diff --git a/boards/arm/reel_board/Kconfig.defconfig b/boards/arm/reel_board/Kconfig.defconfig index b6a3fec81271..e04c41dff3cd 100644 --- a/boards/arm/reel_board/Kconfig.defconfig +++ b/boards/arm/reel_board/Kconfig.defconfig @@ -12,16 +12,6 @@ config BOARD config I2C default y -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default y depends on BT diff --git a/boards/arm/reel_board/dts/reel_board.dtsi b/boards/arm/reel_board/dts/reel_board.dtsi index 691fe8c418d6..053aff93b072 100644 --- a/boards/arm/reel_board/dts/reel_board.dtsi +++ b/boards/arm/reel_board/dts/reel_board.dtsi @@ -202,7 +202,7 @@ arduino_spi: &spi3 { }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/sam4e_xpro/sam4e_xpro.dts b/boards/arm/sam4e_xpro/sam4e_xpro.dts index 6c071fd5ee13..a14d6f51411d 100644 --- a/boards/arm/sam4e_xpro/sam4e_xpro.dts +++ b/boards/arm/sam4e_xpro/sam4e_xpro.dts @@ -148,6 +148,17 @@ &gmac { status = "okay"; zephyr,random-mac-address; + + phy: phy { + compatible = "ethernet-phy"; + status = "okay"; + address = <0>; + mdio = <&mdio>; + }; +}; + +&mdio { + status = "okay"; }; &wdt { diff --git a/boards/arm/sam4l_ek/sam4l_ek.dts b/boards/arm/sam4l_ek/sam4l_ek.dts index 66cd06478293..4479e975420d 100644 --- a/boards/arm/sam4l_ek/sam4l_ek.dts +++ b/boards/arm/sam4l_ek/sam4l_ek.dts @@ -83,3 +83,7 @@ hs-master-code = <0>; }; + +zephyr_udc0: &usbc { + status = "okay"; +}; diff --git a/boards/arm/sam4l_ek/sam4l_ek.yaml b/boards/arm/sam4l_ek/sam4l_ek.yaml index eec21aa7c2f2..2a8ecf8c0e1f 100644 --- a/boards/arm/sam4l_ek/sam4l_ek.yaml +++ b/boards/arm/sam4l_ek/sam4l_ek.yaml @@ -13,3 +13,4 @@ supported: - i2c - spi - usart + - usb_device diff --git a/boards/arm/sam4l_ek/sam4l_ek_defconfig b/boards/arm/sam4l_ek/sam4l_ek_defconfig index 11e6258fed0e..9de0da21b86d 100644 --- a/boards/arm/sam4l_ek/sam4l_ek_defconfig +++ b/boards/arm/sam4l_ek/sam4l_ek_defconfig @@ -9,7 +9,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_BOARD_SAM4L_EK=y CONFIG_WATCHDOG=n -CONFIG_SPI=y CONFIG_GPIO=y # Enable HW stack protection diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi b/boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi index 6296dff9067d..d5f0c10d49ae 100644 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi +++ b/boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi @@ -57,6 +57,10 @@ status = "okay"; }; +&dacc { + status = "okay"; +}; + &twihs0 { status = "okay"; }; @@ -79,12 +83,23 @@ status = "okay"; }; -&usbhs { +zephyr_udc0: &usbhs { status = "okay"; }; &gmac { status = "okay"; + + phy: phy { + compatible = "ethernet-phy"; + status = "okay"; + address = <0>; + mdio = <&mdio>; + }; +}; + +&mdio { + status = "okay"; }; &pwm0 { diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml b/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml index b35d1b7e597b..a0ccd506e2ba 100644 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml +++ b/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml @@ -2,6 +2,8 @@ identifier: sam_e70_xplained name: SAM E70 Xplained type: mcu arch: arm +ram: 384 +flash: 2048 toolchain: - zephyr - gnuarmemb diff --git a/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml b/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml index f43391b65155..ee8d96a417cd 100644 --- a/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml +++ b/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml @@ -2,6 +2,8 @@ identifier: sam_e70b_xplained name: SAM E70 Xplained (Revision B) type: mcu arch: arm +ram: 384 +flash: 2048 toolchain: - zephyr - gnuarmemb diff --git a/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi b/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi index b329f84d50ba..d1cc35a7df8d 100644 --- a/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi +++ b/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi @@ -156,6 +156,10 @@ status = "okay"; }; +&dacc { + status = "okay"; +}; + &twihs0 { status = "okay"; }; @@ -193,12 +197,23 @@ status = "okay"; }; -&usbhs { +zephyr_udc0: &usbhs { status = "okay"; }; &gmac { status = "okay"; + + phy: phy { + compatible = "ethernet-phy"; + status = "okay"; + address = <0>; + mdio = <&mdio>; + }; +}; + +&mdio { + status = "okay"; }; &pwm0 { diff --git a/boards/arm/seeeduino_xiao/pinmux.c b/boards/arm/seeeduino_xiao/pinmux.c index 8b745fc9ee02..fe5dd14b9b80 100644 --- a/boards/arm/seeeduino_xiao/pinmux.c +++ b/boards/arm/seeeduino_xiao/pinmux.c @@ -10,35 +10,17 @@ static int board_pinmux_init(const struct device *dev) { - __unused const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); - __unused const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); - - __ASSERT_NO_MSG(device_is_ready(muxa)); - __ASSERT_NO_MSG(device_is_ready(muxb)); + const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); + const struct device *muxb = DEVICE_DT_GET(DT_NODELABEL(pinmux_b)); ARG_UNUSED(dev); -#if ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) - /* SERCOM4 on RX=PB9/pad 1, TX=PB8/pad 0 */ - pinmux_pin_set(muxb, 9, PINMUX_FUNC_D); - pinmux_pin_set(muxb, 8, PINMUX_FUNC_D); -#endif - -#if ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(1, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(3, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(5, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) -#warning Pin mapping may not be configured -#endif + if (!device_is_ready(muxa)) { + return -ENXIO; + } + if (!device_is_ready(muxb)) { + return -ENXIO; + } #if ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_i2c) && defined(CONFIG_I2C_SAM0) /* SERCOM2 on SDA=PA08, SCL=PA09 */ @@ -94,4 +76,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao.dts b/boards/arm/seeeduino_xiao/seeeduino_xiao.dts index 4db295ba3063..d694a2ac52e0 100644 --- a/boards/arm/seeeduino_xiao/seeeduino_xiao.dts +++ b/boards/arm/seeeduino_xiao/seeeduino_xiao.dts @@ -53,6 +53,8 @@ current-speed = <115200>; rxpo = <1>; txpo = <0>; + + pinctrl-0 = <&pb9d_sercom4_pad1 &pb8d_sercom4_pad0>; }; &sercom0 { @@ -72,7 +74,7 @@ #size-cells = <0>; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; diff --git a/boards/arm/sensortile_box/sensortile_box.dts b/boards/arm/sensortile_box/sensortile_box.dts index 0ea17c50d551..ae8c92c907d9 100644 --- a/boards/arm/sensortile_box/sensortile_box.dts +++ b/boards/arm/sensortile_box/sensortile_box.dts @@ -164,7 +164,7 @@ }; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/serpente/pinmux.c b/boards/arm/serpente/pinmux.c index f40e3ffa924f..e60c1111d12c 100644 --- a/boards/arm/serpente/pinmux.c +++ b/boards/arm/serpente/pinmux.c @@ -12,17 +12,18 @@ static int board_pinmux_init(const struct device *dev) { const struct device *muxa = DEVICE_DT_GET(DT_NODELABEL(pinmux_a)); - __ASSERT_NO_MSG(device_is_ready(muxa)); - ARG_UNUSED(dev); + if (!device_is_ready(muxa)) { + return -ENXIO; + } + /* sercom 3 is always spi - it is the onboard flash */ /* SPI SERCOM3 on MISO=PA18, MOSI=PA16, SCK=PA17, CS=PA15*/ pinmux_pin_set(muxa, 18, PINMUX_FUNC_D); pinmux_pin_set(muxa, 16, PINMUX_FUNC_D); pinmux_pin_set(muxa, 17, PINMUX_FUNC_D); - #if ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_spi) && defined(CONFIG_SPI_SAM0) /* SPI SERCOM0 on MISO=PA6, MOSI=PA4, SCK=PA5 */ pinmux_pin_set(muxa, 6, PINMUX_FUNC_D); @@ -30,24 +31,12 @@ static int board_pinmux_init(const struct device *dev) pinmux_pin_set(muxa, 5, PINMUX_FUNC_D); #endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(0, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) - /* SERCOM0 on RX=PA5, TX=PA4 */ - pinmux_pin_set(muxa, 5, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 4, PINMUX_FUNC_C); -#endif - #if ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_i2c) && defined(CONFIG_I2C_SAM0) /* SERCOM2 on SDA=PA08, SCL=PA09 */ pinmux_pin_set(muxa, 4, PINMUX_FUNC_D); pinmux_pin_set(muxa, 5, PINMUX_FUNC_D); #endif -#if ATMEL_SAM0_DT_SERCOM_CHECK(2, atmel_sam0_uart) && defined(CONFIG_UART_SAM0) - /* SERCOM0 on RX=PA9, TX=PA8 */ - pinmux_pin_set(muxa, 9, PINMUX_FUNC_C); - pinmux_pin_set(muxa, 8, PINMUX_FUNC_C); -#endif - #ifdef CONFIG_USB_DC_SAM0 /* USB DP on PA25, USB DM on PA24 */ pinmux_pin_set(muxa, 25, PINMUX_FUNC_G); @@ -64,4 +53,4 @@ static int board_pinmux_init(const struct device *dev) return 0; } -SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY); +SYS_INIT(board_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/arm/serpente/serpente.dts b/boards/arm/serpente/serpente.dts index 7d454ce026e0..d0aa5fcda0e4 100644 --- a/boards/arm/serpente/serpente.dts +++ b/boards/arm/serpente/serpente.dts @@ -82,6 +82,8 @@ current-speed = <115200>; rxpo = <1>; txpo = <0>; + + pinctrl-0 = <&pa9d_sercom2_pad1 &pa8d_sercom2_pad0>; }; &sercom3 { @@ -93,7 +95,7 @@ #size-cells = <0>; }; -&usb0 { +zephyr_udc0: &usb0 { status = "okay"; }; diff --git a/boards/arm/serpente/serpente_defconfig b/boards/arm/serpente/serpente_defconfig index 5400ebc314b8..312fdca43119 100644 --- a/boards/arm/serpente/serpente_defconfig +++ b/boards/arm/serpente/serpente_defconfig @@ -7,10 +7,8 @@ CONFIG_CORTEX_M_SYSTICK=y CONFIG_CONSOLE=y CONFIG_GPIO=y CONFIG_PINMUX=y -CONFIG_SPI=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_USB=y CONFIG_BOOTLOADER_BOSSA=y CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32f103_mini/doc/index.rst b/boards/arm/stm32f103_mini/doc/index.rst index f337bac1b9ec..af5a1de1a10f 100644 --- a/boards/arm/stm32f103_mini/doc/index.rst +++ b/boards/arm/stm32f103_mini/doc/index.rst @@ -75,6 +75,8 @@ The Zephyr stm32f103_mini board configuration supports the following hardware fe +-----------+------------+-------------------------------------+ | SPI | on-chip | spi | +-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported in this Zephyr port. @@ -100,14 +102,20 @@ Board connectors: Default Zephyr Peripheral Mapping: ---------------------------------- -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- UART_1 TX/RX: PA9/PA10 +- UART_2 TX/RX: PA2/PA3 (ST-Link Virtual COM Port) +- SPI1 NSS/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 +- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 - I2C1 SDA/SCL: PB9/PB8 - PWM1_CH1: PA8 -- USER_PB : PC13 -- LD1 : PA5 +- USER_PB: PC13 +- LD1: PA5 +- USB_DC DM/DP: PA11/PA12 + +System Clock +------------ + +The on-board 8MHz crystal is used to produce a 72MHz system clock with PLL. Programming and Debugging ************************* diff --git a/boards/arm/stm32f103_mini/stm32f103_mini.dts b/boards/arm/stm32f103_mini/stm32f103_mini.dts index 40a225e357f5..368682d1d9e0 100644 --- a/boards/arm/stm32f103_mini/stm32f103_mini.dts +++ b/boards/arm/stm32f103_mini/stm32f103_mini.dts @@ -32,19 +32,20 @@ }; }; -&clk_hsi { +&clk_hse { + clock-frequency = ; status = "okay"; }; &pll { mul = <9>; - clocks = <&clk_hsi>; + clocks = <&clk_hse>; status = "okay"; }; &rcc { clocks = <&pll>; - clock-frequency = ; + clock-frequency = ; ahb-prescaler = <1>; apb1-prescaler = <2>; apb2-prescaler = <1>; @@ -98,6 +99,11 @@ }; }; +&usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + status = "okay"; +}; + &adc1 { pinctrl-0 = <&adc1_in0_pa0>; status = "okay"; diff --git a/boards/arm/stm32f3_disco/doc/index.rst b/boards/arm/stm32f3_disco/doc/index.rst index a7bbbc63ec52..68b74d9012b8 100644 --- a/boards/arm/stm32f3_disco/doc/index.rst +++ b/boards/arm/stm32f3_disco/doc/index.rst @@ -107,6 +107,8 @@ features: +-----------+------------+-------------------------------------+ | DAC | on-chip | dac | +-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. diff --git a/boards/arm/stm32f3_disco/stm32f3_disco.dts b/boards/arm/stm32f3_disco/stm32f3_disco.dts index 2b8800a1c728..512bf8a06b02 100644 --- a/boards/arm/stm32f3_disco/stm32f3_disco.dts +++ b/boards/arm/stm32f3_disco/stm32f3_disco.dts @@ -142,7 +142,7 @@ status = "okay"; }; -&usb { +zephyr_udc0: &usb { pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; status = "okay"; }; @@ -194,3 +194,7 @@ /* dac output pins(pa4,pa5,pa6) might conflict with spi1 pins */ pinctrl-0 = <&dac_out1_pa4>; }; + +&dma1 { + status = "okay"; +}; diff --git a/boards/arm/stm32f3_disco/stm32f3_disco.yaml b/boards/arm/stm32f3_disco/stm32f3_disco.yaml index 51e7594d8420..ef5b77054cc5 100644 --- a/boards/arm/stm32f3_disco/stm32f3_disco.yaml +++ b/boards/arm/stm32f3_disco/stm32f3_disco.yaml @@ -20,3 +20,4 @@ supported: - pwm - adc - dac + - dma diff --git a/boards/arm/stm32f412g_disco/doc/index.rst b/boards/arm/stm32f412g_disco/doc/index.rst index 1c40175cd3ac..ef92f71846c0 100644 --- a/boards/arm/stm32f412g_disco/doc/index.rst +++ b/boards/arm/stm32f412g_disco/doc/index.rst @@ -95,6 +95,12 @@ The Zephyr stm32f412g_disco board configuration supports the following hardware +-----------+------------+-------------------------------------+ | GPIO | on-chip | gpio | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. diff --git a/boards/arm/stm32f412g_disco/stm32f412g_disco.dts b/boards/arm/stm32f412g_disco/stm32f412g_disco.dts index bb05fa0967cb..94b9c552e7e8 100644 --- a/boards/arm/stm32f412g_disco/stm32f412g_disco.dts +++ b/boards/arm/stm32f412g_disco/stm32f412g_disco.dts @@ -123,3 +123,20 @@ &rtc { status = "okay"; }; + +&quadspi { + pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pg6 + &quadspi_bk1_io0_pf8 &quadspi_bk1_io1_pf9 + &quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6>; + + status = "okay"; + + n25q128a1: qspi-nor-flash@0 { + compatible = "st,stm32-qspi-nor"; + label = "N25Q128A1"; + reg = <0>; + qspi-max-frequency = <72000000>; + size = ; + status = "okay"; + }; +}; diff --git a/boards/arm/stm32f469i_disco/stm32f469i_disco.dts b/boards/arm/stm32f469i_disco/stm32f469i_disco.dts index f79832dee4eb..5d78a8cd1a68 100644 --- a/boards/arm/stm32f469i_disco/stm32f469i_disco.dts +++ b/boards/arm/stm32f469i_disco/stm32f469i_disco.dts @@ -103,7 +103,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/stm32f723e_disco/stm32f723e_disco.dts b/boards/arm/stm32f723e_disco/stm32f723e_disco.dts index 595873e77b58..d93265a16fe1 100644 --- a/boards/arm/stm32f723e_disco/stm32f723e_disco.dts +++ b/boards/arm/stm32f723e_disco/stm32f723e_disco.dts @@ -106,7 +106,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts b/boards/arm/stm32f746g_disco/stm32f746g_disco.dts index 76daf4cb6c11..eeb16f7b6507 100644 --- a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts +++ b/boards/arm/stm32f746g_disco/stm32f746g_disco.dts @@ -104,7 +104,7 @@ status = "okay"; }; -&usbotg_fs { +zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "okay"; }; diff --git a/boards/arm/stm32h747i_disco/Kconfig.defconfig b/boards/arm/stm32h747i_disco/Kconfig.defconfig index 6afd0f51dcef..c8fa55a2e37d 100644 --- a/boards/arm/stm32h747i_disco/Kconfig.defconfig +++ b/boards/arm/stm32h747i_disco/Kconfig.defconfig @@ -19,4 +19,7 @@ config NET_L2_ETHERNET endif # NETWORKING +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + endif # BOARD_STM32H747I_DISCO_M7 diff --git a/boards/arm/stm32h747i_disco/doc/index.rst b/boards/arm/stm32h747i_disco/doc/index.rst index 1e09c3951ed1..5aace0211fc2 100644 --- a/boards/arm/stm32h747i_disco/doc/index.rst +++ b/boards/arm/stm32h747i_disco/doc/index.rst @@ -73,6 +73,10 @@ The current Zephyr stm32h747i_disco board configuration supports the following h +-----------+------------+-------------------------------------+ | SPI | on-chip | spi | +-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ (*) From UM2411 Rev 4: With the default setting, the Ethernet feature is not working because of @@ -99,6 +103,7 @@ Default Zephyr Peripheral Mapping: - UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) - UART_8 TX/RX : PJ8/PJ9 (Arduino Serial) - SPI_5 NSS/SCK/MISO/MOSI : PK1/PK0/PJ11/PJ10 (Arduino SPI) +- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 - LD1 : PI12 - LD2 : PI13 - LD3 : PI14 diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts index ded5b8d95254..4fc50f4ce194 100644 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts +++ b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts @@ -161,4 +161,12 @@ }; }; +&sdmmc1 { + status = "okay"; + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; +}; + arduino_spi: &spi5 {}; diff --git a/boards/arm/stm32l562e_dk/CMakeLists.txt b/boards/arm/stm32l562e_dk/CMakeLists.txt index 009a6cab30ba..60198611eca5 100644 --- a/boards/arm/stm32l562e_dk/CMakeLists.txt +++ b/boards/arm/stm32l562e_dk/CMakeLists.txt @@ -7,7 +7,7 @@ elseif(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "gnuarmemb") endif() if(CONFIG_BUILD_WITH_TFM) - set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands #Execute post build script postbuild.sh COMMAND ${CMAKE_BINARY_DIR}/tfm/postbuild.sh ${COMPILER_FULL_PATH} ) diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk.dts b/boards/arm/stm32l562e_dk/stm32l562e_dk.dts index 9d312e4cf7a4..8bb987504f47 100644 --- a/boards/arm/stm32l562e_dk/stm32l562e_dk.dts +++ b/boards/arm/stm32l562e_dk/stm32l562e_dk.dts @@ -52,3 +52,17 @@ &aes { status = "okay"; }; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 2KB at the end of 512KB flash is set for storage */ + storage_partition: partition@7f800 { + label = "storage"; + reg = <0x0007f800 0x00000800>; + }; + }; +}; diff --git a/boards/arm/teensy4/CMakeLists.txt b/boards/arm/teensy4/CMakeLists.txt index f82582a53423..bb7336d6c16e 100644 --- a/boards/arm/teensy4/CMakeLists.txt +++ b/boards/arm/teensy4/CMakeLists.txt @@ -10,5 +10,5 @@ if(CONFIG_PINMUX) zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) endif() -zephyr_library_sources(teensy4_flexspi_nor_config.c) +zephyr_library_sources(flexspi_nor_config.c) zephyr_library_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA teensy4_sdram_ini_dcd.c) diff --git a/boards/arm/teensy4/teensy4_flexspi_nor_config.c b/boards/arm/teensy4/flexspi_nor_config.c similarity index 87% rename from boards/arm/teensy4/teensy4_flexspi_nor_config.c rename to boards/arm/teensy4/flexspi_nor_config.c index ad752e23e2f9..6420e446bd9f 100644 --- a/boards/arm/teensy4/teensy4_flexspi_nor_config.c +++ b/boards/arm/teensy4/flexspi_nor_config.c @@ -7,9 +7,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "teensy4_flexspi_nor_config.h" +#include -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER #if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) __attribute__((section(".boot_hdr.conf"))) #elif defined(__ICCARM__) @@ -41,4 +41,4 @@ const struct flexspi_nor_config_t Qspiflash_config = { .blockSize = 256u * 1024u, .isUniformBlockSize = false, }; -#endif /* XIP_BOOT_HEADER_ENABLE */ +#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/teensy4/teensy40.dts b/boards/arm/teensy4/teensy40.dts index 5a0c1ad43622..e8a190ea4dbe 100644 --- a/boards/arm/teensy4/teensy40.dts +++ b/boards/arm/teensy4/teensy40.dts @@ -47,7 +47,7 @@ }; }; -&usb1 { +zephyr_udc0: &usb1 { status = "okay"; }; diff --git a/boards/arm/teensy4/teensy4_flexspi_nor_config.h b/boards/arm/teensy4/teensy4_flexspi_nor_config.h deleted file mode 100644 index b8a2872b4818..000000000000 --- a/boards/arm/teensy4/teensy4_flexspi_nor_config.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * Copyright (c) 2021, Bernhard Kraemer - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __TEENSY4_FLEXSPI_NOR_CONFIG__ -#define __TEENSY4_FLEXSPI_NOR_CONFIG__ - -#include -#include "fsl_common.h" - -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) -#define FLEXSPI_CFG_BLK_SIZE (512) - -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ - FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -enum { - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_133MHz = 7, - kFlexSpiSerialClk_166MHz = 8, - kFlexSpiSerialClk_200MHz = 9, -}; - -enum { - kFlexSpiClk_SDR, - kFlexSpiClk_DDR, }; - -enum { - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -}; - - -enum { kFlexSpiMiscOffset_DiffClkEnable = 0, - kFlexSpiMiscOffset_Ck2Enable = 1, - kFlexSpiMiscOffset_ParallelEnable = 2, - kFlexSpiMiscOffset_WordAddressableEnable = 3, - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, - kFlexSpiMiscOffset_DdrModeEnable = 6, }; - - -enum { kFlexSpiDeviceType_SerialNOR = 1, - kFlexSpiDeviceType_SerialNAND = 2, - kFlexSpiDeviceType_SerialRAM = 3, - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, }; - - -enum { kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, }; - - -struct flexspi_lut_seq_t { - uint8_t seqNum; - uint8_t seqId; - uint16_t reserved; -}; - - -enum { kDeviceConfigCmdType_Generic, - kDeviceConfigCmdType_QuadEnable, - kDeviceConfigCmdType_Spi2Xpi, - kDeviceConfigCmdType_Xpi2Spi, - kDeviceConfigCmdType_Spi2NoCmd, - kDeviceConfigCmdType_Reset, }; - - -struct flexspi_mem_config_t { - uint32_t tag; - uint32_t version; - uint32_t reserved0; - uint8_t readSampleClkSrc; - uint8_t csHoldTime; - uint8_t csSetupTime; - uint8_t columnAddressWidth; - - uint8_t deviceModeCfgEnable; - uint8_t deviceModeType; - - uint16_t waitTimeCfgCommands; - - struct flexspi_lut_seq_t deviceModeSeq; - - uint32_t deviceModeArg; - uint8_t configCmdEnable; - uint8_t configModeType[3]; - struct flexspi_lut_seq_t configCmdSeqs[3]; - uint32_t reserved1; - uint32_t configCmdArgs[3]; - uint32_t reserved2; - uint32_t controllerMiscOption; - - uint8_t deviceType; - uint8_t sflashPadType; - uint8_t serialClkFreq; - - uint8_t lutCustomSeqEnable; - - uint32_t reserved3[2]; - uint32_t sflashA1Size; - uint32_t sflashA2Size; - uint32_t sflashB1Size; - uint32_t sflashB2Size; - uint32_t csPadSettingOverride; - uint32_t sclkPadSettingOverride; - uint32_t dataPadSettingOverride; - uint32_t dqsPadSettingOverride; - uint32_t timeoutInMs; - uint32_t commandInterval; - uint16_t dataValidTime[2]; - uint16_t busyOffset; - uint16_t busyBitPolarity; - - uint32_t lookupTable[64]; - struct flexspi_lut_seq_t lutCustomSeq[12]; - uint32_t reserved4[4]; -}; - - -#define NOR_CMD_INDEX_READ CMD_INDEX_READ -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE -#define NOR_CMD_INDEX_ERASESECTOR 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE -#define NOR_CMD_INDEX_CHIPERASE 5 -#define NOR_CMD_INDEX_DUMMY 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ \ - CMD_LUT_SEQ_IDX_READ -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ - 5 -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ - 8 -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ - 11 -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ - 13 -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 - - -struct flexspi_nor_config_t { - struct flexspi_mem_config_t memConfig; - uint32_t pageSize; - uint32_t sectorSize; - uint8_t ipcmdSerialClkFreq; - uint8_t isUniformBlockSize; - uint8_t reserved0[2]; - uint8_t serialNorType; - uint8_t needExitNoCmdMode; - uint8_t halfClkForNonReadCmd; - uint8_t needRestoreNoCmdMode; - uint32_t blockSize; - uint32_t reserve2[11]; -}; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __TEENSY4_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/arm/thingy53_nrf5340/Kconfig.defconfig b/boards/arm/thingy53_nrf5340/Kconfig.defconfig index 0d65c75599eb..c5ae7da4c3bb 100644 --- a/boards/arm/thingy53_nrf5340/Kconfig.defconfig +++ b/boards/arm/thingy53_nrf5340/Kconfig.defconfig @@ -68,14 +68,8 @@ config HEAP_MEM_POOL_SIZE config BT_HAS_HCI_VS default BT -config USB_NRFX - default USB - -config USB_DEVICE_STACK - default USB - config USB_NRFX_ATTACHED_EVENT_DELAY - default 700 if USB + default 700 if USB_DEVICE_DRIVER config I2C default y diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.dts b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.dts index c9e3dc1fddb5..eabf1ba81c5b 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.dts +++ b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.dts @@ -19,13 +19,9 @@ zephyr,sram-secure-partition = &sram0_s; zephyr,sram-non-secure-partition = &sram0_ns; }; - - aliases { - usbd0 = &usbd; - }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.dts b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.dts index 9ebf3efa6a56..8e0377672a43 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.dts +++ b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.dts @@ -17,13 +17,9 @@ zephyr,flash = &flash0; zephyr,code-partition = &slot0_ns_partition; }; - - aliases { - usbd0 = &usbd; - }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig index aa0fb99d0a2f..33dc6fbdeddd 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig +++ b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig @@ -12,6 +12,3 @@ CONFIG_HW_STACK_PROTECTION=y # Enable GPIO CONFIG_GPIO=y - -# Enable console -CONFIG_CONSOLE=y diff --git a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig index ec0cf76eaf7a..f3113a62b3a6 100644 --- a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig +++ b/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_UBX_BMD340EVAL_NRF52840 config BOARD default "ubx_bmd340eval_nrf52840" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts b/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts index 8ff9514087dc..61a734627c55 100644 --- a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts +++ b/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts @@ -287,7 +287,7 @@ arduino_spi: &spi3 { }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig index 9362471fe1e4..e66bae50d865 100644 --- a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig +++ b/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig @@ -9,16 +9,6 @@ if BOARD_UBX_BMD345EVAL_NRF52840 config BOARD default "ubx_bmd345eval_nrf52840" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.dts b/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.dts index 22bc4b180016..21b73dd43dc4 100644 --- a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.dts +++ b/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.dts @@ -282,7 +282,7 @@ arduino_spi: &spi3 { }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig index 4eca2799be4c..e13411085e10 100644 --- a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig +++ b/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_UBX_BMD380EVAL_NRF52840 config BOARD default "ubx_bmd380eval_nrf52840" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config IEEE802154_NRF5 default y depends on IEEE802154 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.dts b/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.dts index dc388c726c50..2c46aea40fe9 100644 --- a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.dts +++ b/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.dts @@ -228,7 +228,7 @@ }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig b/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig index f7ea1e8c5093..0e2c4e94efc7 100644 --- a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig +++ b/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_UBX_EVKNINAB3_NRF52840 config BOARD default "ubx_evkninab3_nrf52840" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config IEEE802154_NRF5 default y depends on IEEE802154 diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.dts b/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.dts index bfbd3b0e1c7a..f17d1629ba44 100644 --- a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.dts +++ b/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.dts @@ -221,7 +221,7 @@ arduino_i2c: &i2c0 { }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig b/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig index 863190d087fd..0e6ffbcfc5a2 100644 --- a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig +++ b/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig @@ -8,16 +8,6 @@ if BOARD_UBX_EVKNINAB4_NRF52833 config BOARD default "ubx_evkninab4_nrf52833" -if USB - -config USB_NRFX - default y - -config USB_DEVICE_STACK - default y - -endif # USB - config BT_CTLR default BT diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts b/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts index a17dc3c95375..4cbe1c5fbe89 100644 --- a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts +++ b/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts @@ -224,7 +224,7 @@ arduino_spi: &spi2 { }; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; diff --git a/boards/arm/usb_kw24d512/usb_kw24d512.dts b/boards/arm/usb_kw24d512/usb_kw24d512.dts index 11a0f0e0c95b..78779fbd113a 100644 --- a/boards/arm/usb_kw24d512/usb_kw24d512.dts +++ b/boards/arm/usb_kw24d512/usb_kw24d512.dts @@ -62,7 +62,7 @@ pinctrl-0 = <&UART0_RX_PTA1 &UART0_TX_PTA2>; }; -&usbd { +zephyr_udc0: &usbd { compatible = "nxp,kinetis-usbd"; status = "okay"; num-bidir-endpoints = <8>; diff --git a/boards/arm/waveshare_open103z/waveshare_open103z.dts b/boards/arm/waveshare_open103z/waveshare_open103z.dts index 38cb2e3f0f94..234d25e810e9 100644 --- a/boards/arm/waveshare_open103z/waveshare_open103z.dts +++ b/boards/arm/waveshare_open103z/waveshare_open103z.dts @@ -147,7 +147,7 @@ phase-seg2 = <6>; }; -&usb { +zephyr_udc0: &usb { /* * make sure CAN and USB are not enabled at the same time * because they share interrupts 19, 20 (stm32f103Xb.dtsi) diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/doc/index.rst b/boards/arm64/fvp_base_revc_2xaemv8a/doc/index.rst index 7fff1e993cb2..ef3df9a7001d 100644 --- a/boards/arm64/fvp_base_revc_2xaemv8a/doc/index.rst +++ b/boards/arm64/fvp_base_revc_2xaemv8a/doc/index.rst @@ -71,6 +71,29 @@ To run with FVP, ARMFVP_BIN_PATH must be set before running: e.g. export ARMFVP_BIN_PATH= +Running Zephyr at EL1NS +*********************** + +In order to run Zephyr as EL1NS with ``CONFIG_ARMV8_A_NS``, you'll need a proper +Trusted Firmware loaded in the FVP model. + +The ARM TF-A for FVP can be used to run Zephyr as preloaded BL33 payload. + +Checkout and Build the TF-A: + +.. code-block:: console + + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git --depth 1 + cd trusted-firmware-a/ + make PLAT=fvp PRELOADED_BL33_BASE="0x88000000" all fip + +then export the ``ARMFVP_BL1_FILE` and ``ARMFVP_FIP_FILE`` environment variables: + +.. code-block:: console + + export ARMFVP_BL1_FILE= + export ARMFVP_FIP_FILE= + Debugging ========= diff --git a/boards/common/openocd-nrf5.board.cmake b/boards/common/openocd-nrf5.board.cmake index 8f6f4137ccb1..90ab5d32a4cf 100644 --- a/boards/common/openocd-nrf5.board.cmake +++ b/boards/common/openocd-nrf5.board.cmake @@ -27,7 +27,6 @@ set(pre_init_cmds "source [find interface/${OPENOCD_NRF5_INTERFACE}.cfg]" "transport select swd" "source [find target/${OPENOCD_NRF5_SUBFAMILY}.cfg]" - "$_TARGETNAME configure -rtos auto" ) foreach(cmd ${pre_init_cmds}) diff --git a/boards/nios2/altera_max10/doc/index.rst b/boards/nios2/altera_max10/doc/index.rst index 1c2915d9300c..f96710075f56 100644 --- a/boards/nios2/altera_max10/doc/index.rst +++ b/boards/nios2/altera_max10/doc/index.rst @@ -122,13 +122,15 @@ minicom with flow control disabled, 115200-8N1 settings. JTAG UART --------- -You can also have it send its console output to the JTAG UART. Set these in your -project configuration: +You can also have it send its console output to the JTAG UART. +Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: -.. code-block:: console +.. code-block:: devicetree - CONFIG_UART_ALTERA_JTAG=y - CONFIG_UART_CONSOLE_ON_DEV_NAME="jtag_uart0" + &jtag_uart { + status = "okay"; + current-speed = <115200>; + }; To view these messages on your local workstation, run the terminal application in the SDK: diff --git a/boards/nios2/qemu_nios2/qemu_nios2_defconfig b/boards/nios2/qemu_nios2/qemu_nios2_defconfig index aaf51a4811a5..c60fd0a2e71d 100644 --- a/boards/nios2/qemu_nios2/qemu_nios2_defconfig +++ b/boards/nios2/qemu_nios2/qemu_nios2_defconfig @@ -6,7 +6,6 @@ CONFIG_HAS_ALTERA_HAL=y CONFIG_CONSOLE=y CONFIG_PRINTK=y CONFIG_SERIAL=y -CONFIG_UART_ALTERA_JTAG=y CONFIG_UART_NS16550=y CONFIG_UART_CONSOLE=y CONFIG_INCLUDE_RESET_VECTOR=n diff --git a/boards/posix/native_posix/Kconfig.defconfig b/boards/posix/native_posix/Kconfig.defconfig index a226c26d6031..ba2304886c2d 100644 --- a/boards/posix/native_posix/Kconfig.defconfig +++ b/boards/posix/native_posix/Kconfig.defconfig @@ -75,10 +75,20 @@ config FLASH_SIMULATOR config USB_NATIVE_POSIX default y - depends on USB + depends on USB_DEVICE_DRIVER config EEPROM_SIMULATOR default y depends on EEPROM +if I2C + +config EMUL + default y + +config I2C_EMUL + default y + +endif # I2C + endif # BOARD_NATIVE_POSIX diff --git a/boards/posix/native_posix/native_posix.dts b/boards/posix/native_posix/native_posix.dts index 5e52d3cbca16..b444a12e8cc0 100644 --- a/boards/posix/native_posix/native_posix.dts +++ b/boards/posix/native_posix/native_posix.dts @@ -171,4 +171,9 @@ gpio-controller; #gpio-cells = <2>; }; + + zephyr_udc0: udc0 { + compatible = "zephyr,native-posix-udc"; + label = "USBD"; + }; }; diff --git a/boards/posix/native_posix/native_posix.yaml b/boards/posix/native_posix/native_posix.yaml index 8d8a1655324f..35751988690c 100644 --- a/boards/posix/native_posix/native_posix.yaml +++ b/boards/posix/native_posix/native_posix.yaml @@ -2,8 +2,10 @@ identifier: native_posix name: Native 32-bit POSIX port type: native arch: posix +ram: 65536 +flash: 65536 toolchain: - - zephyr + - host - llvm supported: - eeprom diff --git a/boards/posix/native_posix/native_posix_64.yaml b/boards/posix/native_posix/native_posix_64.yaml index ee063a9952d4..2f3794be347d 100644 --- a/boards/posix/native_posix/native_posix_64.yaml +++ b/boards/posix/native_posix/native_posix_64.yaml @@ -2,8 +2,10 @@ identifier: native_posix_64 name: Native 64-bit POSIX port type: native arch: posix +ram: 65536 +flash: 65536 toolchain: - - zephyr + - host - llvm supported: - eeprom diff --git a/boards/riscv/adp_xc7k_ae350/Kconfig.board b/boards/riscv/adp_xc7k_ae350/Kconfig.board new file mode 100644 index 000000000000..085eb9696a8c --- /dev/null +++ b/boards/riscv/adp_xc7k_ae350/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADP_XC7K_AE350 + bool "Andes ADP-XC7K AE350 Platform" + depends on SOC_RISCV_ANDES_AE350 diff --git a/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig b/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig new file mode 100644 index 000000000000..7438c2eae72e --- /dev/null +++ b/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "adp_xc7k_ae350" if BOARD_ADP_XC7K_AE350 diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.dts b/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.dts new file mode 100644 index 000000000000..4fee6978d929 --- /dev/null +++ b/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.dts @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2021 Andes Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "Andes ADP-XC7K AE350"; + compatible = "andestech,adp_xc7k_ae350"; + + aliases { + gpio-0 = &gpio0; + led0 = &seg7_led1_g; + led1 = &seg7_led2_g; + sw0 = &user_button1; + }; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &dram; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + seg7_led1_a: led_1 { + label = "7SEG LED1 A"; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + seg7_led1_b: led_2 { + label = "7SEG LED1 B"; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + seg7_led1_c: led_3 { + label = "7SEG LED1 C"; + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + seg7_led1_d: led_4 { + label = "7SEG LED1 D"; + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + }; + seg7_led1_e: led_5 { + label = "7SEG LED1 E"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + seg7_led1_f: led_6 { + label = "7SEG LED1 F"; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + seg7_led1_g: led_7 { + label = "7SEG LED1 G"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + seg7_led1_dp: led_8 { + label = "7SEG LED1 DP"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + seg7_led2_a: led_9 { + label = "7SEG LED2 A"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + seg7_led2_b: led_10 { + label = "7SEG LED2 B"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + seg7_led2_c: led_11 { + label = "7SEG LED2 C"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + seg7_led2_d: led_12 { + label = "7SEG LED2 D"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + seg7_led2_e: led_13 { + label = "7SEG LED2 E"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + seg7_led2_f: led_14 { + label = "7SEG LED2 F"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + seg7_led2_g: led_15 { + label = "7SEG LED2 G"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + seg7_led2_dp: led_16 { + label = "7SEG LED2 DP"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + user_button2: button_2 { + label = "User SW2"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + user_button3: button_3 { + label = "User SW3"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + user_button4: button_4 { + label = "User SW4"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + user_button5: button_5 { + label = "User SW5"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + }; + user_button6: button_6 { + label = "User SW6"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; + user_button7: button_7 { + label = "User SW7"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart1 { + status = "okay"; + clock-frequency = <19660800>; + current-speed = <115200>; +}; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + flash0: flash@0 { + compatible = "jedec,spi-nor"; + label = "JEDEC SPI-NOR"; + reg = <0>; + size = <16777216>; + spi-max-frequency = <1000000>; + jedec-id = [c2 25 35]; + status = "okay"; + }; +}; diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml b/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml new file mode 100644 index 000000000000..93be22abf7ca --- /dev/null +++ b/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml @@ -0,0 +1,13 @@ +identifier: adp_xc7k_ae350 +name: Andes ADP-XC7K AE350 +type: mcu +arch: riscv32 +toolchain: + - zephyr + - cross-compile +ram: 512 +supported: + - gpio +testing: + ignore_tags: + - bluetooth diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig b/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig new file mode 100644 index 000000000000..f7010d29e140 --- /dev/null +++ b/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig @@ -0,0 +1,43 @@ +CONFIG_SOC_SERIES_RISCV_ANDES_V5=y +CONFIG_SOC_RISCV_ANDES_AE350=y +CONFIG_BOARD_ADP_XC7K_AE350=y +CONFIG_XIP=n +CONFIG_PLIC=y +CONFIG_RISCV_MACHINE_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_BOOT_BANNER=y + +# Serial driver options +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y + +# GPIO driver options +CONFIG_GPIO=y +CONFIG_GPIO_ANDES_ATCGPIO100=y + +# RV64 options +#CONFIG_RV64I_CPU=y + +# FPU (single precision) options +#CONFIG_FPU=y +#CONFIG_FPU_SHARING=y +#CONFIG_FLOAT_HARD=y +#CONFIG_SINGLE_PRECISION_FPU=y + +# FPU (double precision) options +#CONFIG_FPU=y +#CONFIG_FPU_SHARING=y +#CONFIG_FLOAT_HARD=y +#CONFIG_DOUBLE_PRECISION_FPU=y + +# HW DSP options +#CONFIG_SOC_ANDES_V5_HWDSP=y + +# Cache options +CONFIG_CACHE_ENABLE=y + +# Nocache memory options +#CONFIG_SOC_ANDES_V5_PMA=y +#CONFIG_NOCACHE_MEMORY=y diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k160.png b/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k160.png new file mode 100644 index 000000000000..38ca5294f099 Binary files /dev/null and b/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k160.png differ diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k410.png b/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k410.png new file mode 100644 index 000000000000..592bce499536 Binary files /dev/null and b/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k410.png differ diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/connect_aice.png b/boards/riscv/adp_xc7k_ae350/doc/img/connect_aice.png new file mode 100644 index 000000000000..353b6aaa6733 Binary files /dev/null and b/boards/riscv/adp_xc7k_ae350/doc/img/connect_aice.png differ diff --git a/boards/riscv/adp_xc7k_ae350/doc/index.rst b/boards/riscv/adp_xc7k_ae350/doc/index.rst new file mode 100644 index 000000000000..e8a202cd5fd7 --- /dev/null +++ b/boards/riscv/adp_xc7k_ae350/doc/index.rst @@ -0,0 +1,318 @@ +.. _adp_xc7k_ae350: + +Andes ADP-XC7K AE350 +#################### + +Overview +******** + +ADP-XC7K AE350 board is for AndeShape AE350 platform on ADP-XC7K series +FPGA-based development boards. + +ADP-XC7K series are FPGA-based development and prototyping boards for evaluation of +variety of AndesCore processors and AndeShape SoC platform IPs. +AE350 is a RISC-V platform which can integrate AndesCore CPUs with a collection +of fundamental peripheral IPs. + +1st figure shows the green PCB is ADP-XC7K160 and 2nd figure shows the red PCB is ADP-XC7K410. + +.. image:: img/adp_xc7k160.png + :width: 600px + :align: center + :alt: ADP-XC7K160 + +.. image:: img/adp_xc7k410.png + :width: 600px + :align: center + :alt: ADP-XC7K410 + +More information can be found on `ADP-XC7K160/410`_ and `AndeShape AE350`_ websites. + +Hardware +******** + +The ADP-XC7K AE350 platform integrates 1 ~ 4 cores 32/64-bit 60MHz RISC-V CPUs, DSP, +1GB RAM, Cache, SPI flash memory, ethernet controller and other peripherals. + +The ADP-XC7K AE350 platform provides following hardware components: + +- 1 ~ 4 cores 32/64-bit 60MHz AndeStar v5 RISC-V CPUs +- 1GB on-board SDRAM +- 2MB SPI flash memory (1MB can be used for XIP) +- UART +- I2C +- SPI +- GPIO +- PWM +- DMA +- 10/100 Ethernet RJ45 port +- LCD module connector +- 16KB I2C EEPROM +- SD memory card slot +- MIC-in, Line-in, and Line-out with AC97 audio codec + +Supported Features +================== + +The ``adp_xc7k_ae350`` board configuration supports the following hardware features: + ++----------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++================+============+======================+ +| PLIC | on-chip | interrupt_controller | ++----------------+------------+----------------------+ +| RISC-V Machine | on-chip | timer | +| Timer | | | ++----------------+------------+----------------------+ +| GPIO | on-chip | gpio | ++----------------+------------+----------------------+ +| UART | on-chip | serial | ++----------------+------------+----------------------+ + +Other hardware features are not supported yet. + +Connections and IOs +=================== + +The ADP-XC7K AE350 platform has 1 GPIO controller. It providing 32 bits of IO. +It is responsible for pin input/output, pull-up, etc. + +Mapping from GPIO controller to the ADP-XC7K board pins: + ++--------------------+--------------------+ +| GPIO controller | Usage / Board pins | ++====================+====================+ +| **Push Buttons** | | ++--------------------+--------------------+ +| GPIO.0 | SW1 | ++--------------------+--------------------+ +| GPIO.1 | SW2 | ++--------------------+--------------------+ +| GPIO.2 | SW3 | ++--------------------+--------------------+ +| GPIO.3 | SW4 | ++--------------------+--------------------+ +| GPIO.4 | SW5 | ++--------------------+--------------------+ +| GPIO.5 | SW6 | ++--------------------+--------------------+ +| GPIO.6 | SW7 | ++--------------------+--------------------+ +| **7-Segment LED1** | | ++--------------------+--------------------+ +| GPIO.16 | 7SEG1.A | ++--------------------+--------------------+ +| GPIO.17 | 7SEG1.B | ++--------------------+--------------------+ +| GPIO.18 | 7SEG1.C | ++--------------------+--------------------+ +| GPIO.19 | 7SEG1.D | ++--------------------+--------------------+ +| GPIO.20 | 7SEG1.E | ++--------------------+--------------------+ +| GPIO.21 | 7SEG1.F | ++--------------------+--------------------+ +| GPIO.22 | 7SEG1.G | ++--------------------+--------------------+ +| GPIO.23 | 7SEG1.DP | ++--------------------+--------------------+ +| **7-Segment LED2** | | ++--------------------+--------------------+ +| GPIO.24 | 7SEG2.A | ++--------------------+--------------------+ +| GPIO.25 | 7SEG2.B | ++--------------------+--------------------+ +| GPIO.26 | 7SEG2.C | ++--------------------+--------------------+ +| GPIO.27 | 7SEG2.D | ++--------------------+--------------------+ +| GPIO.28 | 7SEG2.E | ++--------------------+--------------------+ +| GPIO.29 | 7SEG2.F | ++--------------------+--------------------+ +| GPIO.30 | 7SEG2.G | ++--------------------+--------------------+ +| GPIO.31 | 7SEG2.DP | ++--------------------+--------------------+ +| **GPIO pins** | | ++--------------------+--------------------+ +| GPIO.7 | IDE_CON1.4 | ++--------------------+--------------------+ +| GPIO.8 | IDE_CON1.6 | ++--------------------+--------------------+ +| GPIO.9 | IDE_CON1.8 | ++--------------------+--------------------+ +| GPIO.10 | IDE_CON1.10 | ++--------------------+--------------------+ +| GPIO.11 | IDE_CON1.11 | ++--------------------+--------------------+ +| GPIO.12 | IDE_CON1.12 | ++--------------------+--------------------+ +| GPIO.13 | IDE_CON1.13 | ++--------------------+--------------------+ +| GPIO.14 | IDE_CON1.14 | ++--------------------+--------------------+ +| GPIO.15 | IDE_CON1.15 | ++--------------------+--------------------+ + +Other peripheral mapping are listed below: + ++-------------+---------------------------------+ +| Peripherals | Usage / Board pins | ++=============+=================================+ +| SPI_1 | internal connected to SPI Flash | ++-------------+---------------------------------+ +| SPI_2_CS | IDE_CON1.37 | ++-------------+---------------------------------+ +| SPI_2_MOSI | IDE_CON1.36 | ++-------------+---------------------------------+ +| SPI_2_MISO | IDE_CON1.38 | ++-------------+---------------------------------+ +| SPI_2_SCLK | IDE_CON1.35 | ++-------------+---------------------------------+ +| I2C_SDA | J27.1 | ++-------------+---------------------------------+ +| I2C_SCL | J27.2 | ++-------------+---------------------------------+ + +System Clock +------------ + +The ADP-XC7K AE350 platform has 60MHz core clock. + +Serial Port +----------- + +The ADP-XC7K AE350 platform has 2 UARTs. +The Zephyr console output is by default assigned to UART2 and the default +settings are 115200 8N1. + +Programming and debugging +************************* + +For debugging zephyr applications or burning them into a flash, you will need to +connect Andes ICE from host computer to ADP-XC7K board and execute the +Andes ICE management software, ICEman, on this host computer. + +Connecting Andes ICE (AICE) +=========================== + +AICE is used for flashing and debugging the board. Please connect AICE to both +ADP-XC7K board and the host computer as shown in the figure. + +.. image:: img/connect_aice.png + :width: 600px + :align: center + :alt: Connect AICE + +More information can be found on `AICE-MINI+`_, `AICE-MICRO`_ website + +Building +======== + +You can build applications in the usual way. Here is an example for +the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :board: adp_xc7k_ae350 + :goals: build + +Flashing +======== + +Before flashing, you have to download ICEman (``ice.zip``) from the +`Andes Development Kit`_. +If you want to use XIP mode (``CONFIG_XIP=y``), you also need to download +the flash burner (``flash.zip``). + +At first, you should run ICEman when flashing and debugging program. + +.. code-block:: console + + # Enable execute file permission of ICEman + chmod a+x ./ICEman + + # Running the ICEman server + sudo ./ICEman -Z v5 + +.. note:: + + To run ICEman commands as a normal user, you will need to install the + :file:`70-ndsusb-v1.rules` udev rules file (usually by placing it in + :file:`/etc/udev/rules.d`, then unplugging and plugging the + AICE adapter in again via USB.). + +If ``CONFIG_XIP=n``, you can load the program (``zephyr.elf``) into RAM directly +and execute it. + +.. code-block:: console + + # Check the ICEman server is running + # Load the program into RAM and execute it + riscv64-zephyr-elf-gdb zephyr/zephyr.elf + (gdb) target remote :1111 + (gdb) monitor reset halt + (gdb) load + (gdb) quit + +If ``CONFIG_XIP=y``, you need to burn the program (``zephyr.bin``) into flash memory +and execute it. + +.. code-block:: console + + # Check the ICEman server is running + # Burn the program into flash and execute it + /bin/target_burn_frontend \ + -P 4444 --unlock --verify --image=zephyr/zephyr.bin \ + --algorithm-bin=/target_bin/target_SPI_v5_[32|64].bin + + # Note: + # 1. Assume the flash burner is downloaded to directory + # 2. For algorithm-bin file, use target_SPI_v5_32.bin in RV32 platform and + # use target_SPI_v5_64.bin in RV64 platform + +Open a serial terminal with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +you should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.4.0 ***** + Hello World! adp_xc7k_ae350 + +Debugging +========= + +.. code-block:: console + + # Check the ICEman server is running + # Load and debug program + ./riscv64-zephyr-elf-gdb zephyr/zephyr.elf + (gdb) target remote :1111 + (gdb) monitor reset halt + (gdb) load + +If ``CONFIG_XIP=y``, please follow the flashing section to burn the program into +flash memory first. +Then, you can use GDB to debug program by above commands but do NOT execute ``load`` +command since the program has been placed in the flash memory. + +References +********** + +.. target-notes:: + +.. _ADP-XC7K160/410: http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/ + +.. _AndeShape AE350: http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/ + +.. _AICE-MINI+: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-mini-plus/ + +.. _AICE-MICRO: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-micro/ + +.. _Andes Development Kit: https://github.com/andestech/Andes-Development-Kit/releases diff --git a/boards/riscv/esp32c3_devkitm/CMakeLists.txt b/boards/riscv/esp32c3_devkitm/CMakeLists.txt index 4b2a5fa8abe5..da1e041373dc 100644 --- a/boards/riscv/esp32c3_devkitm/CMakeLists.txt +++ b/boards/riscv/esp32c3_devkitm/CMakeLists.txt @@ -20,6 +20,10 @@ if(CONFIG_BOOTLOADER_ESP_IDF) -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} -DSDKCONFIG_DEFAULTS=${ESP_IDF_PATH}/zephyr/esp32c3/sdkconfig.defaults -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} BUILD_COMMAND ${CMAKE_COMMAND} --build . INSTALL_COMMAND "" # This particular build system has no install command diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.defconfig b/boards/riscv/esp32c3_devkitm/Kconfig.defconfig index 4978542f4bd1..3276547dbac0 100644 --- a/boards/riscv/esp32c3_devkitm/Kconfig.defconfig +++ b/boards/riscv/esp32c3_devkitm/Kconfig.defconfig @@ -6,3 +6,14 @@ config BOARD default "esp32c3" depends on BOARD_ESP32C3_DEVKITM + +if BT + +config HEAP_MEM_POOL_SIZE + default 16384 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 +endchoice + +endif # BT diff --git a/boards/riscv/esp32c3_devkitm/doc/index.rst b/boards/riscv/esp32c3_devkitm/doc/index.rst index 4cee3fcc4809..f32dbcbeb6ca 100644 --- a/boards/riscv/esp32c3_devkitm/doc/index.rst +++ b/boards/riscv/esp32c3_devkitm/doc/index.rst @@ -52,7 +52,6 @@ On Linux and macOS: export ZEPHYR_TOOLCHAIN_VARIANT="espressif" export ESPRESSIF_TOOLCHAIN_PATH="${HOME}/.espressif/tools/riscv32-esp-elf/1.24.0.123_64eb9ff-8.4.0/riscv32-esp-elf" - export PATH=$PATH:$ESPRESSIF_TOOLCHAIN_PATH/bin On Windows: @@ -109,7 +108,9 @@ specific options for the ESP32C3 board, as listed here: --esp-idf-path ESP_IDF_PATH path to ESP-IDF --esp-device ESP_DEVICE - serial port to flash, default /dev/ttyUSB0 + serial port to flash, default $ESPTOOL_PORT if defined. + If not, esptool will loop over available serial ports until + it finds ESP32 device to flash. --esp-baud-rate ESP_BAUD_RATE serial baud rate, default 921600 --esp-flash-size ESP_FLASH_SIZE diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts index d78b261086b5..c58fa003ce39 100644 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts @@ -14,5 +14,12 @@ chosen { zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; }; }; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig index b98871af4b2d..f2361455ae0e 100644 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig +++ b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig @@ -1,10 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 - CONFIG_BOARD_ESP32C3_DEVKITM=y CONFIG_SOC_ESP32C3=y CONFIG_MAIN_STACK_SIZE=2048 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_ROM_ESP32C3=y CONFIG_XIP=n diff --git a/boards/riscv/hifive_unleashed/Kconfig.board b/boards/riscv/hifive_unleashed/Kconfig.board new file mode 100644 index 000000000000..4766e0ea7929 --- /dev/null +++ b/boards/riscv/hifive_unleashed/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE_UNLEASHED + bool "HiFive Unleashed target" + depends on SOC_RISCV_SIFIVE_FU540 diff --git a/boards/riscv/hifive_unleashed/Kconfig.defconfig b/boards/riscv/hifive_unleashed/Kconfig.defconfig new file mode 100644 index 000000000000..249abdb7c99b --- /dev/null +++ b/boards/riscv/hifive_unleashed/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HIFIVE_UNLEASHED + +config BOARD + default "hifive_unleashed" + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config SPI_SIFIVE + default y + depends on SPI + +config UART_SIFIVE + default y + depends on SERIAL + +endif diff --git a/boards/riscv/hifive_unleashed/board.cmake b/boards/riscv/hifive_unleashed/board.cmake new file mode 100644 index 000000000000..6142f4f1126b --- /dev/null +++ b/boards/riscv/hifive_unleashed/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(OPENOCD_USE_LOAD_IMAGE NO) + +board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_hifive_unleashed.cfg") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/riscv/hifive_unleashed/doc/index.rst b/boards/riscv/hifive_unleashed/doc/index.rst new file mode 100644 index 000000000000..b6fe5bb71dc8 --- /dev/null +++ b/boards/riscv/hifive_unleashed/doc/index.rst @@ -0,0 +1,44 @@ +.. _hifive_unleashed: + +SiFive HiFive Unleashed +####################### + +Overview +******** + +The HiFive Unleashed is a development board with a SiFive FU540-C000 +multi-core 64bit RISC-V SoC. + +Programming and debugging +************************* + +Building +======== + +Applications for the ``hifive_unleashed`` board configuration can be built as +usual (see :ref:`build_an_application`) using the corresponding board name: + +.. zephyr-app-commands:: + :board: hifive_unleashed + :goals: build + +Flashing +======== + +Current version has not yet supported flashing binary to onboard Flash ROM. + +This board has USB-JTAG interface and this can be used with OpenOCD. +Load applications on DDR and run as follows: + +.. code-block:: console + + openocd -c 'bindto 0.0.0.0' \ + -f boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg + riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf + (gdb) target remote :3333 + (gdb) c + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed.dts b/boards/riscv/hifive_unleashed/hifive_unleashed.dts new file mode 100644 index 000000000000..1742d08a9222 --- /dev/null +++ b/boards/riscv/hifive_unleashed/hifive_unleashed.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2021 Katsuhiro Suzuki + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram0; + }; + + ram0: ram0@80000000 { + compatible = "memory"; + reg = <0x80000000 0xf0000000>; + reg-names = "mem"; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <500000000>; +}; + +&spi0 { + status = "okay"; + clock-frequency = <500000000>; + + reg = <0x10040000 0x1000 0x20000000 0x2000000>; + flash0: flash@0 { + compatible = "issi,is25wp256d", "jedec,spi-nor"; + size = <33554432>; + label = "FLASH0"; + jedec-id = [96 60 18]; + reg = <0>; + spi-max-frequency = <133000000>; + }; +}; + +&spi1 { + status = "okay"; + clock-frequency = <500000000>; +}; + +&spi2 { + status = "okay"; + clock-frequency = <500000000>; +}; diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed.yaml b/boards/riscv/hifive_unleashed/hifive_unleashed.yaml new file mode 100644 index 000000000000..4e7b31467e41 --- /dev/null +++ b/boards/riscv/hifive_unleashed/hifive_unleashed.yaml @@ -0,0 +1,13 @@ +identifier: hifive_unleashed +name: SiFive HiFive Unleashed +type: mcu +arch: riscv64 +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth +supported: + - spi diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig b/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig new file mode 100644 index 000000000000..259dbf0df0a9 --- /dev/null +++ b/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig @@ -0,0 +1,15 @@ +CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM=y +CONFIG_SOC_RISCV_SIFIVE_FU540=y +CONFIG_BOARD_HIFIVE_UNLEASHED=y +CONFIG_RISCV_MACHINE_TIMER=y +CONFIG_PLIC=y +CONFIG_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_SPI=y +CONFIG_SPI_SIFIVE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_BOOT_BANNER=y +CONFIG_XIP=n diff --git a/boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg b/boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg new file mode 100644 index 000000000000..1620f6cbd39c --- /dev/null +++ b/boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg @@ -0,0 +1,22 @@ +adapter speed 10000 + +adapter driver ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread +target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1 +target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2 +target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3 +target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4 +target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4 +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 + +flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000 diff --git a/boards/riscv/hifive_unmatched/Kconfig.board b/boards/riscv/hifive_unmatched/Kconfig.board new file mode 100644 index 000000000000..cf6ac1c83920 --- /dev/null +++ b/boards/riscv/hifive_unmatched/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE_UNMATCHED + bool "HiFive Unmatched target" + depends on SOC_RISCV_SIFIVE_FU740 diff --git a/boards/riscv/hifive_unmatched/Kconfig.defconfig b/boards/riscv/hifive_unmatched/Kconfig.defconfig new file mode 100644 index 000000000000..5cb952bfad42 --- /dev/null +++ b/boards/riscv/hifive_unmatched/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HIFIVE_UNMATCHED + +config BOARD + default "hifive_unmatched" + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config SPI_SIFIVE + default y + depends on SPI + +config UART_SIFIVE + default y + depends on SERIAL + +endif diff --git a/boards/riscv/hifive_unmatched/board.cmake b/boards/riscv/hifive_unmatched/board.cmake new file mode 100644 index 000000000000..c985f2d7bcaf --- /dev/null +++ b/boards/riscv/hifive_unmatched/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(OPENOCD_USE_LOAD_IMAGE NO) + +board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_hifive_unmatched.cfg") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/riscv/hifive_unmatched/doc/index.rst b/boards/riscv/hifive_unmatched/doc/index.rst new file mode 100644 index 000000000000..3cc41d2d06f2 --- /dev/null +++ b/boards/riscv/hifive_unmatched/doc/index.rst @@ -0,0 +1,44 @@ +.. _hifive_unmatched: + +SiFive HiFive Unmatched +####################### + +Overview +******** + +The HiFive Unmatched is a development board with a SiFive FU740-C000 +multi-core 64bit RISC-V SoC. + +Programming and debugging +************************* + +Building +======== + +Applications for the ``hifive_unmatched`` board configuration can be built as +usual (see :ref:`build_an_application`) using the corresponding board name: + +.. zephyr-app-commands:: + :board: hifive_unmatched + :goals: build + +Flashing +======== + +Current version has not yet supported flashing binary to onboard Flash ROM. + +This board has USB-JTAG interface and this can be used with OpenOCD. +Load applications on DDR and run as follows: + +.. code-block:: console + + openocd -c 'bindto 0.0.0.0' \ + -f boards/riscv/hifive_unmatched/support/openocd_hifive_unmatched.cfg + riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf + (gdb) target remote :3333 + (gdb) c + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched.dts b/boards/riscv/hifive_unmatched/hifive_unmatched.dts new file mode 100644 index 000000000000..5226704400b9 --- /dev/null +++ b/boards/riscv/hifive_unmatched/hifive_unmatched.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2021 Katsuhiro Suzuki + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &l2lim; + }; + + ram0: ram0@80000000 { + compatible = "memory"; + reg = <0x80000000 0xf0000000>; + reg-names = "mem"; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <125125000>; +}; + +&spi0 { + status = "okay"; + clock-frequency = <125125000>; + + reg = <0x10040000 0x1000 0x20000000 0x2000000>; + flash0: flash@0 { + compatible = "issi,is25wp256d", "jedec,spi-nor"; + size = <33554432>; + label = "FLASH0"; + jedec-id = [96 60 18]; + reg = <0>; + spi-max-frequency = <133000000>; + }; +}; + +&spi1 { + status = "okay"; + clock-frequency = <125125000>; +}; + +&spi2 { + status = "okay"; + clock-frequency = <125125000>; +}; diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched.yaml b/boards/riscv/hifive_unmatched/hifive_unmatched.yaml new file mode 100644 index 000000000000..d0543af145c6 --- /dev/null +++ b/boards/riscv/hifive_unmatched/hifive_unmatched.yaml @@ -0,0 +1,13 @@ +identifier: hifive_unmatched +name: SiFive HiFive Unmatched +type: mcu +arch: riscv64 +toolchain: + - zephyr +ram: 3840 +testing: + ignore_tags: + - net + - bluetooth +supported: + - spi diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig b/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig new file mode 100644 index 000000000000..96e2215fc69a --- /dev/null +++ b/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig @@ -0,0 +1,15 @@ +CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM=y +CONFIG_SOC_RISCV_SIFIVE_FU740=y +CONFIG_BOARD_HIFIVE_UNMATCHED=y +CONFIG_RISCV_MACHINE_TIMER=y +CONFIG_PLIC=y +CONFIG_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_SPI=y +CONFIG_SPI_SIFIVE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_BOOT_BANNER=y +CONFIG_XIP=n diff --git a/boards/riscv/hifive_unmatched/support/openocd_hifive_unleashed.cfg b/boards/riscv/hifive_unmatched/support/openocd_hifive_unleashed.cfg new file mode 100644 index 000000000000..1620f6cbd39c --- /dev/null +++ b/boards/riscv/hifive_unmatched/support/openocd_hifive_unleashed.cfg @@ -0,0 +1,22 @@ +adapter speed 10000 + +adapter driver ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread +target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1 +target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2 +target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3 +target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4 +target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4 +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 + +flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000 diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv.yaml b/boards/riscv/m2gl025_miv/m2gl025_miv.yaml index ff4194889964..00e67f645059 100644 --- a/boards/riscv/m2gl025_miv/m2gl025_miv.yaml +++ b/boards/riscv/m2gl025_miv/m2gl025_miv.yaml @@ -7,6 +7,7 @@ toolchain: ram: 64 simulation: renode testing: + default: true ignore_tags: - net - bluetooth diff --git a/boards/riscv/tlsr9518adk80d/Kconfig.defconfig b/boards/riscv/tlsr9518adk80d/Kconfig.defconfig index 2b3208b03d1a..d651133bfe43 100644 --- a/boards/riscv/tlsr9518adk80d/Kconfig.defconfig +++ b/boards/riscv/tlsr9518adk80d/Kconfig.defconfig @@ -18,4 +18,25 @@ config UART_TELINK_B91 config PINMUX_TELINK_B91 default y if PINMUX +config PWM_TELINK_B91 + default y if PWM + +config ENTROPY_TELINK_B91_TRNG + default y if ENTROPY_GENERATOR + +config SOC_FLASH_TELINK_B91 + default y if FLASH + +config SPI_TELINK_B91 + default y if SPI + +config IEEE802154_TELINK_B91 + default y if IEEE802154 + +config NET_CONFIG_IEEE802154_DEV_NAME + default "IEEE802154_b91" + +config I2C_TELINK_B91 + default y if I2C + endif diff --git a/boards/riscv/tlsr9518adk80d/doc/index.rst b/boards/riscv/tlsr9518adk80d/doc/index.rst index 8f54ed0df5be..56173009e5fa 100644 --- a/boards/riscv/tlsr9518adk80d/doc/index.rst +++ b/boards/riscv/tlsr9518adk80d/doc/index.rst @@ -1,4 +1,4 @@ -.. _tlst9518adk80d: +.. _tlsr9518adk80d: Telink TLSR9518ADK80D ##################### @@ -63,6 +63,18 @@ The Zephyr TLSR9518ADK80D board configuration supports the following hardware fe +----------------+------------+------------------------------+ | UART | on-chip | serial | +----------------+------------+------------------------------+ +| PWM | on-chip | pwm | ++----------------+------------+------------------------------+ +| TRNG | on-chip | entopy | ++----------------+------------+------------------------------+ +| FLASH (MSPI) | on-chip | flash | ++----------------+------------+------------------------------+ +| RADIO | on-chip | ieee802154, OpenThread | ++----------------+------------+------------------------------+ +| SPI (Master) | on-chip | spi | ++----------------+------------+------------------------------+ +| I2C (Master) | on-chip | i2c | ++----------------+------------+------------------------------+ The following example projects are supported: @@ -71,12 +83,19 @@ The following example projects are supported: - samples/philosophers - samples/basic/threads - samples/basic/blinky +- samples/basic/blinky_pwm +- samples/basic/fade_led - samples/basic/button +- samples/subsys/nvs - samples/subsys/console/echo - samples/subsys/console/getchar - samples/subsys/console/getline - samples/subsys/shell/shell_module - samples/subsys/cpp/cpp_synchronization +- samples/drivers/flash_shell +- samples/net/sockets/echo_client (OpenThread and IEEE802154) +- samples/net/sockets/echo_server (OpenThread and IEEE802154) +- samples/net/openthread/coprocessor .. note:: To support "button" example project PC3-KEY3 (J20-19, J20-20) jumper needs to be removed and KEY3 (J20-19) should be connected to VDD3_DCDC (J51-13) externally. @@ -89,8 +108,10 @@ Limitations ----------- - Maximum 3 GPIO pins could be configured to generate interrupts simultaneously. All pins must be related to different ports and use different IRQ numbers. -- DMA mode is not supported by Serial Port. +- DMA mode is not supported by I2C, SPI and Serial Port. - UART hardware flow control is not implemented. +- SPI Slave mode is not implemented. +- I2C Slave mode is not implemented. Default configuration and IOs ============================= @@ -128,14 +149,17 @@ currently enabled (PORT_B for LEDs control and PORT_C for buttons) in the board Peripheral's pins on the SoC are mapped to the following GPIO pins in the ``boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts`` file: -- UART0 RX: PB2, TX: PB3 -- UART1 RX: PC6, TX: PC7 +- UART0 TX: PB2, RX: PB3 +- UART1 TX: PC6, RX: PC7 +- PWM Channel 0: PB4 +- PSPI CS0: PC4, CLK: PC5, MISO: PC6, MOSI: PC7 +- HSPI CS0: PA1, CLK: PA2, MISO: PA3, MOSI: PA4 +- I2C SCL: PE1, SDA: PE3 Serial Port ----------- -The TLSR9518A SoC has 2 UARTs. The Zephyr console output is assigned -to UART0 in the ``boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig`` file. +The TLSR9518A SoC has 2 UARTs. The Zephyr console output is assigned to UART0. The default settings are 115200 8N1. Programming and debugging @@ -153,6 +177,7 @@ the "hello_world" application. west build -b tlsr9518adk80d samples/hello_world To use `Telink RISC-V Linux Toolchain`_, ``ZEPHYR_TOOLCHAIN_VARIANT`` and ``CROSS_COMPILE`` variables need to be set. +In addition ``CONFIG_FPU=y`` must be selected in ``boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig`` file. .. code-block:: console diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts b/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts index 82bee5e59e0d..61af1413562a 100644 --- a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts +++ b/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts @@ -16,6 +16,8 @@ led0 = &led_blue; led1 = &led_green; sw0 = &key_1; + pwm-led0 = &pwm_led_blue; + pwm-0 = &pwm0; }; leds { @@ -42,6 +44,15 @@ }; }; + pwm_leds { + compatible = "pwm-leds"; + + pwm_led_blue: pwm_led_0 { + pwms = <&pwm0 0 0>; + label = "PWM LED Blue"; + }; + }; + keys { compatible = "gpio-keys"; key_1: button_1 { @@ -56,6 +67,7 @@ zephyr,sram = &ram_dlm; zephyr,flash = &flash; zephyr,flash-controller = &flash_mspi; + zephyr,entropy = &trng0; }; }; @@ -95,6 +107,38 @@ pinctrl-0 = <&uart0_tx_pb2 &uart0_rx_pb3>; }; +&trng0 { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&pwm0 { + status = "okay"; + clock-frequency = <93750>; + pinctrl-0 = <&pwm_ch0_pb4>; +}; + +&pspi { + status = "okay"; + cs0-pin = "PSPI_CSN_PC4"; + pinctrl-0 = <&pspi_clk_pc5 &pspi_miso_io1_pc6 &pspi_mosi_io0_pc7>; +}; + +&hspi { + status = "okay"; + cs0-pin = "HSPI_CSN_PA1"; + pinctrl-0 = <&hspi_clk_pa2 &hspi_miso_io1_pa3 &hspi_mosi_io0_pa4>; +}; + +&i2c { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c_scl_pe1 &i2c_sda_pe3>; +}; + &flash_mspi { partitions { compatible = "fixed-partitions"; @@ -119,7 +163,10 @@ }; storage_partition: partition@f0000 { label = "storage"; - reg = <0x000f0000 0x00010000>; + reg = <0x000f0000 0x00008000>; + /* region 0x000f8000 .. 0x000FFFFF + * is reserved for factory calibration + */ }; }; }; diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.yaml b/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.yaml index e661002a9ef4..e358e1a4de8c 100644 --- a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.yaml +++ b/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.yaml @@ -9,3 +9,8 @@ ram: 128 flash: 1024 supported: - gpio + - i2c + - ieee802154 + - pwm + - spi + - netif:openthread diff --git a/boards/shields/sparkfun_sara_r4/sparkfun_sara_r4.overlay b/boards/shields/sparkfun_sara_r4/sparkfun_sara_r4.overlay index fa70bce754d5..436dc7acf83f 100644 --- a/boards/shields/sparkfun_sara_r4/sparkfun_sara_r4.overlay +++ b/boards/shields/sparkfun_sara_r4/sparkfun_sara_r4.overlay @@ -9,7 +9,7 @@ status = "okay"; sara_r4 { - compatible = "ublox,sara-r4"; + compatible = "u-blox,sara-r4"; label = "ublox-sara-r4"; mdm-power-gpios = <&arduino_header 11 0>; /* D5 */ mdm-reset-gpios = <&arduino_header 12 0>; /* D6 */ diff --git a/boards/x86/acrn/acrn_ehl_crb.dts b/boards/x86/acrn/acrn_ehl_crb.dts index 81044b6b501a..cc2b9e511691 100644 --- a/boards/x86/acrn/acrn_ehl_crb.dts +++ b/boards/x86/acrn/acrn_ehl_crb.dts @@ -5,11 +5,3 @@ */ #include "acrn.dts" - -/ { - ibecc: ibecc { - compatible = "intel,ibecc"; - label = "ibecc"; - status = "okay"; - }; -}; diff --git a/boards/x86/acrn/acrn_ehl_crb_defconfig b/boards/x86/acrn/acrn_ehl_crb_defconfig index e8dd4d57df3d..8dc457385ab4 100644 --- a/boards/x86/acrn/acrn_ehl_crb_defconfig +++ b/boards/x86/acrn/acrn_ehl_crb_defconfig @@ -16,4 +16,5 @@ CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n CONFIG_KERNEL_VM_SIZE=0x1000000 CONFIG_BUILD_NO_GAP_FILL=y CONFIG_APIC_TSC_DEADLINE_TIMER=y +CONFIG_APIC_TIMER_IRQ_PRIORITY=1 CONFIG_SMP=y diff --git a/boards/x86/acrn/doc/ACRN-Hybrid.png b/boards/x86/acrn/doc/ACRN-Hybrid.png new file mode 100644 index 000000000000..9eb466d636c2 Binary files /dev/null and b/boards/x86/acrn/doc/ACRN-Hybrid.png differ diff --git a/boards/x86/acrn/doc/index.rst b/boards/x86/acrn/doc/index.rst index 1c73f8da0a8b..63968d9a0c24 100644 --- a/boards/x86/acrn/doc/index.rst +++ b/boards/x86/acrn/doc/index.rst @@ -5,6 +5,28 @@ Zephyr's is capable of running as a guest under the x86 ACRN hypervisor (see https://projectacrn.org/). The process for getting this to work is somewhat involved, however. +ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so- +called "pre-launched" mode. This means Zephyr will access the ACRN +hypervisor directly without involving the SOS VM. This is the most +practical user scenario in the real world because Zephyr's real-time +and safety capability can be assured without influence from other +VMs. The following figure from ACRN's official documentation shows +how a hybrid scenario works: + +.. figure:: ACRN-Hybrid.png + :align: center + :alt: ACRN Hybrid User Scenario + :figclass: align-center + :width: 80% + + ACRN Hybrid User Scenario + +In this tutorial, we will show you how to build a minimal running instance of Zephyr +and ACRN hypervisor to demonstrate that it works successfully. To learn more about +other features of ACRN, such as building and using the SOS VM or other guest VMs, +please refer to the Getting Started Guide for ACRN: +https://projectacrn.github.io/latest/tutorials/using_hybrid_mode_on_nuc.html + Build your Zephyr App ********************* @@ -15,6 +37,10 @@ normally would, selecting an appropriate board: west build -b acrn_ehl_crb samples/hello_world +In this tutorial, we will use the Intel Elkhart Lake Reference Board +(`EHL`_ CRB) since it is one of the suggested platform for this +type of scenario. Use ``acrn_ehl_crb`` as the target board parameter. + Note the kconfig output in ``build/zephyr/.config``, you will need to reference that to configure ACRN later. @@ -31,6 +57,9 @@ First you need the source code, clone from: git clone https://github.com/projectacrn/acrn-hypervisor +We suggest that you use versions v2.5.1 or later of the ACRN hypervisor +as they have better support for SMP in Zephyr. + Like Zephyr, ACRN favors build-time configuration management instead of runtime probing or control. Unlike Zephyr, ACRN has single large configuration files instead of small easily-merged configuration @@ -102,10 +131,51 @@ many CPUs in the ```` tag. For example: .. code-block:: xml - - 0 - 1 - + + SAFETY_VM + ACRN PRE-LAUNCHED VM0 + + 0 + + + 0 + 1 + + ... + + 0 + 0 + + ... + + +To use SMP, we have to change the pcpu_id of VM0 to 0 and 1. +This configures ACRN to run Zephyr on CPU0 and CPU1. The ACRN hypervisor +and Zephyr application will not boot successfully without this change. +If you plan to run Zephyr with one CPU only, you can skip it. + +Since Zephyr is using CPU0 and CPU1, we also have to change +VM1's configuration so it runs on CPU2 and CPU3. If your ACRN set up has +additional VMs, you should change their configurations as well. + + .. code-block:: xml + + + SOS_VM + ACRN SOS VM + + 0 + + + 2 + 3 + + + 0 + 0 + + ... + Note that these indexes are physical CPUs on the host. When configuring multiple guests, you probably don't want to overlap these @@ -228,3 +298,6 @@ command: ----- Entering VM 0 Shell ----- *** Booting Zephyr OS build v2.6.0-rc1-324-g1a03783861ad *** Hello World! acrn + + +.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/x86/ehl_crb/doc/index.rst b/boards/x86/ehl_crb/doc/index.rst index d59214fee508..5a41cba3d457 100644 --- a/boards/x86/ehl_crb/doc/index.rst +++ b/boards/x86/ehl_crb/doc/index.rst @@ -36,38 +36,6 @@ Use the following procedures for booting an image on a EHL CRB board. :local: :backlinks: top -Creating a GRUB2 Boot Loader Image from a Linux Host -==================================================== - -If you are having problems running an application using the preinstalled -copy of GRUB, follow these steps to test on supported boards using a custom GRUB. - -#. Install the requirements to build GRUB on your host machine. - - On Ubuntu, type: - - .. code-block:: console - - $ sudo apt-get install bison autoconf libopts25-dev flex automake \ - pkg-config gettext autopoint - - On Fedora, type: - - .. code-block:: console - - $ sudo dnf install gnu-efi bison m4 autoconf help2man flex \ - automake texinfo gettext-devel - -#. Clone and build the GRUB repository using the script in Zephyr tree, type: - - .. code-block:: console - - $ cd $ZEPHYR_BASE - $ ./boards/x86/common/scripts/build_grub.sh x86_64 - -#. Find the binary at - :file:`$ZEPHYR_BASE/boards/x86/common/scripts/grub/bin/grub_x86_64.efi`. - Build Zephyr application ======================== @@ -81,9 +49,8 @@ Build Zephyr application .. note:: - A stripped project image file named :file:`zephyr.strip` is automatically - created in the build directory after the application is built. This image - has removed debug information from the :file:`zephyr.elf` file. + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. Preparing the Boot Device ========================= @@ -111,33 +78,12 @@ an Elkhart Lake CRB board. the USB flash drive. Or else you may erase other storage devices on your system, and will render the system unusable afterwards. -#. Create the following directories - - :file:`efi` - - :file:`efi/boot` - - :file:`kernel` - -#. Copy the kernel file :file:`zephyr/zephyr.strip` to the :file:`$USB/kernel` folder. - -#. Copy your built version of GRUB to :file:`$USB/efi/boot/bootx64.efi` - -#. Create :file:`$USB/efi/boot/grub.cfg` containing the following: - - .. code-block:: console - - set default=0 - set timeout=10 - - menuentry "Zephyr Kernel" { - multiboot /kernel/zephyr.strip - } +#. Copy the Zephyr EFI image file :file:`zephyr/zephyr.efi` to the USB drive. Booting the Elkhart Lake CRB Board ================================== -Boot the Elkhart Lake CRB board from the boot device using GRUB2 via USB flash drive. +Boot the Elkhart Lake CRB board to the EFI shell with USB flash drive connected. #. Insert the prepared boot device (USB flash drive) into the Elkhart Lake CRB board. @@ -158,23 +104,13 @@ Boot the Elkhart Lake CRB board from the boot device using GRUB2 via USB flash d Press or to enter setup. #. From the menu that appears, select the menu entry that describes - that particular type of USB flash drive. - - GRUB2 starts and a menu shows entries for the items you added - to the file :file:`grub.cfg`. - -#. Select the image you want to boot and press :guilabel:`Enter`. - - When the boot process completes, you have finished booting the - Zephyr application image. + that particular EFI shell. - .. note:: - You can safely ignore this message if it appears: - - .. code-block:: console +#. From the EFI shell select Zephyr EFI image to boot. - WARNING: no console will be available to OS + .. code-block:: console + Shell> fs0:zephyr.efi Booting the Elkhart Lake CRB Board over network =============================================== @@ -187,9 +123,6 @@ Build Zephyr image Prepare Linux host ------------------ -#. Follow `Creating a GRUB2 Boot Loader Image from a Linux Host`_ steps - to create grub binary. - #. Install DHCP, TFTP servers. For example ``dnsmasq`` .. code-block:: console @@ -211,49 +144,16 @@ Prepare Linux host # tftp enable-tftp tftp-root=/srv/tftp - dhcp-boot=grub_x86_64.efi - - ``grub_x86_64.efi`` is a grub binary created above. - -#. Create the following directories inside TFTP root :file:`/srv/tftp` + dhcp-boot=zephyr.efi - .. code-block:: console - - $ sudo mkdir -p /srv/tftp/EFI/BOOT - $ sudo mkdir -p /srv/tftp/kernel + ``zephyr.efi`` is a Zephyr EFI binary created above. -#. Copy the Zephyr image :file:`zephyr/zephyr.strip` to the - :file:`/srv/tftp/kernel` folder. +#. Copy the Zephyr EFI image :file:`zephyr/zephyr.efi` to the + :file:`/srv/tftp` folder. .. code-block:: console - $ sudo cp zephyr/zephyr.strip /srv/tftp/kernel - -#. Copy your built version of GRUB to :file:`/srv/tftp/grub_x86_64.efi` - -#. Create :file:`/srv/tftp/EFI/BOOT/grub.cfg` containing the following: - - .. code-block:: console - - set default=0 - set timeout=10 - - menuentry "Zephyr Kernel" { - multiboot /kernel/zephyr.strip - } - -#. TFTP root should be looking like: - - .. code-block:: console - - $ tree /srv/tftp - /srv/tftp - ├── EFI - │   └── BOOT - │   └── grub.cfg - ├── grub_x86_64.efi - └── kernel - └── zephyr.strip + $ cp zephyr/zephyr.efi /srv/tftp/ #. Restart ``dnsmasq`` service: @@ -264,17 +164,24 @@ Prepare Linux host Prepare Elkhart Lake CRB board for network boot ----------------------------------------------- -#. Enable PXE network from BIOS settings. +#. Enable boot from PXE. Go to EFI shell and make sure that the first boot + option is ``UEFI PXEv4``. .. code-block:: console - Advanced -> Network Stack Configuration -> Enable Network Stack -> Enable Ipv4 PXE Support + Shell> bcfg boot dump + Option: 00. Variable: Boot0007 + Desc - UEFI PXEv4 (MAC:6805CABC1997) + DevPath - PciRoot(0x0)/Pci(0x1C,0x0)/Pci(0x0,0x0)/MAC(6805CABC1997,0x0)/IPv4(0.0.0.0) + Optional- Y + ... -#. Make network boot as the first boot option. +#. If UEFI PXEv4 is not the first boot option use ``bcfg boot mv`` command to + change boot order .. code-block:: console - Boot -> Boot Option #1 : [Network] + Shell> bcfg boot mv 7 0 Booting Elkhart Lake CRB ------------------------ @@ -299,9 +206,7 @@ Booting Elkhart Lake CRB .. code-block:: console $ journalctl -f -u dnsmasq - dnsmasq-tftp[5386]: sent /srv/tftp/grub_x86_64.efi to 10.1.1.28 - dnsmasq-tftp[5386]: sent /srv/tftp/EFI/BOOT/grub.cfg to 10.1.1.28 - dnsmasq-tftp[5386]: sent /srv/tftp/kernel/zephyr.strip to 10.1.1.28 + dnsmasq-tftp[5386]: sent /srv/tftp/zephyr.efi to 10.1.1.28 #. When the boot process completes, you have finished booting the Zephyr application image. diff --git a/boards/x86/qemu_x86/Kconfig.board b/boards/x86/qemu_x86/Kconfig.board index 2c3739b3397d..739f18c1eec8 100644 --- a/boards/x86/qemu_x86/Kconfig.board +++ b/boards/x86/qemu_x86/Kconfig.board @@ -20,3 +20,9 @@ config BOARD_QEMU_X86_LAKEMONT select QEMU_TARGET select CPU_HAS_FPU select HAS_COVERAGE_SUPPORT + +config BOARD_QEMU_X86_TINY + bool "QEMU x86 (tiny memory)" + depends on SOC_IA32 + select QEMU_TARGET + select CPU_HAS_FPU diff --git a/boards/x86/qemu_x86/Kconfig.defconfig b/boards/x86/qemu_x86/Kconfig.defconfig index 56abe634b3e1..7b0b8f709794 100644 --- a/boards/x86/qemu_x86/Kconfig.defconfig +++ b/boards/x86/qemu_x86/Kconfig.defconfig @@ -24,6 +24,12 @@ config MULTIBOOT_INFO config MULTIBOOT_MEMMAP default y if MULTIBOOT +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + endif # BOARD_QEMU_X86 if BOARD_QEMU_X86_64 @@ -55,4 +61,51 @@ config X86_PC_COMPATIBLE # QEMU presents a PC-compatible machine default y +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + endif # BOARD_QEMU_X86_LAKEMONT + +if BOARD_QEMU_X86_TINY + +config BUILD_OUTPUT_BIN + default n + +config BOARD + default "qemu_x86_tiny" + +config KERNEL_VM_SIZE + default 0x400000 + +config MULTIBOOT + # This is needed for QEMU to load the ELF image + default y + +config X86_PC_COMPATIBLE + # QEMU presents a PC-compatible machine + default y + +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + +config HAVE_CUSTOM_LINKER_SCRIPT + default y + +config CUSTOM_LINKER_SCRIPT + default "${ZEPHYR_BASE}/boards/x86/qemu_x86/qemu_x86_tiny.ld" + +config X86_EXTRA_PAGE_TABLE_PAGES + # This is needed for gen_mmu.py to map the flash into memory + default 2 if DEMAND_PAGING && !LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT + +config DEMAND_PAGING_PAGE_FRAMES_RESERVE + # Need to accommodate the heap for newlib in libc-hook.c + default 6 if NEWLIB_LIBC + +endif # BOARD_QEMU_X86_TINY diff --git a/boards/x86/qemu_x86/board.cmake b/boards/x86/qemu_x86/board.cmake index ca0bf054fc41..48ffdeb906e4 100644 --- a/boards/x86/qemu_x86/board.cmake +++ b/boards/x86/qemu_x86/board.cmake @@ -22,6 +22,10 @@ endif() if(CONFIG_XIP) # Extra 4MB to emulate flash area math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024 + 4") +elseif(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING + AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + # Flash is at 4MB-8MB, so need this to be large enough + math(EXPR QEMU_MEMORY_SIZE_MB "8") else() math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024") endif() @@ -69,3 +73,11 @@ endif() # board_set_debugger_ifnset(qemu) # debugserver: QEMU_EXTRA_FLAGS += -s -S # debugserver: qemu + +if(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING + AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + # This is to map the flash so it is accessible. + math(EXPR QEMU_FLASH_SIZE_KB "${CONFIG_FLASH_SIZE} * 1024") + set(X86_EXTRA_GEN_MMU_ARGUMENTS + --map ${CONFIG_FLASH_BASE_ADDRESS},${QEMU_FLASH_SIZE_KB},W) +endif() diff --git a/boards/x86/qemu_x86/doc/index.rst b/boards/x86/qemu_x86/doc/index.rst index f85efa8b630a..99a55cded955 100644 --- a/boards/x86/qemu_x86/doc/index.rst +++ b/boards/x86/qemu_x86/doc/index.rst @@ -113,6 +113,53 @@ QEMU, and display the following console output: Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. +For qemu_x86_64 platform, it also supports to use UEFI bootable method +to run Zephyr applications and kernel tests, but you need to set up +some environemnt configurations as follows: + +* Please install uefi-run in your system environment according to this + reference link https://github.com/Richard-W/uefi-run. + +* Please install OVMF in your system environment according to this + reference link https://github.com/tianocore/tianocore.github.io/wiki/OVMF. + +* Set system environment variable OVMF_FD_PATH, + for example: export OVMF_FD_PATH=/usr/share/edk2.git/ovmf-x64/OVMF_CODE-pure-efi.fd + +For example, with the test "sample.basic.helloworld.uefi": + +.. code-block:: console + + export OVMF_FD_PATH=/usr/share/edk2.git/ovmf-x64/OVMF_CODE-pure-efi.fd + west build -b qemu_x86_64 -p auto samples/hello_world/ -DCONF_FILE=prj_uefi.conf + west build -t run + +This will build an image with the hello_world sample app, boot it on +qemu_x86_64 using UEFI, and display the following console output: + +.. code-block:: console + + UEFI Interactive Shell v2.2 + EDK II + UEFI v2.70 (EDK II, 0x00010000) + Mapping table + FS0: Alias(s):F0a:;BLK0: + PciRoot(0x0)/Pci(0x1,0x1)/Ata(0x0) + BLK1: Alias(s): + PciRoot(0x0)/Pci(0x1,0x1)/Ata(0x0) + Press ESC in 1 seconds to skip startup.nsh or any other key to continue. + Starting UEFI application... + *** Zephyr EFI Loader *** + Zeroing 524544 bytes of memory at 0x105000 + Copying 32768 data bytes to 0x1000 from image offset + Copying 20480 data bytes to 0x100000 from image offset 32768 + Copying 540416 data bytes to 0x185100 from image offset 53248 + Jumping to Entry Point: 0x112b (48 31 c0 48 31 d2 48) + *** Booting Zephyr OS build zephyr-v2.6.0-1472-g61810ec36d28 *** + Hello World! qemu_x86_64 + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + Debugging ========= diff --git a/boards/x86/qemu_x86/qemu_x86_defconfig b/boards/x86/qemu_x86/qemu_x86_defconfig index 9db929558b7d..8f485f6c3123 100644 --- a/boards/x86/qemu_x86/qemu_x86_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_defconfig @@ -16,4 +16,3 @@ CONFIG_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT_SHIFT=5 diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig b/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig index 423798f2b08c..49baaf127644 100644 --- a/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig @@ -16,4 +16,3 @@ CONFIG_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT_SHIFT=5 diff --git a/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig b/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig index 6443b51b8f19..cf03a83ae432 100644 --- a/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig @@ -16,5 +16,4 @@ CONFIG_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT_SHIFT=5 CONFIG_X86_KPTI=n diff --git a/boards/x86/qemu_x86/qemu_x86_nommu_defconfig b/boards/x86/qemu_x86/qemu_x86_nommu_defconfig index ed3b7d4f5866..d4bfd61f1db2 100644 --- a/boards/x86/qemu_x86/qemu_x86_nommu_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_nommu_defconfig @@ -12,4 +12,3 @@ CONFIG_UART_CONSOLE=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_DEBUG_INFO=y -CONFIG_QEMU_ICOUNT_SHIFT=5 diff --git a/boards/x86/qemu_x86/qemu_x86_nopae_defconfig b/boards/x86/qemu_x86/qemu_x86_nopae_defconfig index 60dc38b6ea1d..2cea3ba3ba8b 100644 --- a/boards/x86/qemu_x86/qemu_x86_nopae_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_nopae_defconfig @@ -16,5 +16,4 @@ CONFIG_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT_SHIFT=5 CONFIG_X86_PAE=n diff --git a/boards/x86/qemu_x86/qemu_x86_tiny.ld b/boards/x86/qemu_x86/qemu_x86_tiny.ld new file mode 100644 index 000000000000..1e0a74a7aee7 --- /dev/null +++ b/boards/x86/qemu_x86/qemu_x86_tiny.ld @@ -0,0 +1,774 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright (c) 2021 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + + +/* Bounds of physical RAM from DTS */ +#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) +#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) + +/* Bounds of flash from DTS */ +#define FLASH_ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) +#define FLASH_ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) + +/* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily + * the same as its physical location, although an identity mapping for RAM + * is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS. + */ +#ifdef Z_VM_KERNEL + +#define KERNEL_BASE_ADDR \ + (CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET) + +#define KERNEL_RAM_SIZE \ + (CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET) + +#define PHYS_RAM_AVAIL \ + (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET) + +#else + +#define KERNEL_BASE_ADDR (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET) +#define KERNEL_RAM_SIZE (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET) + +#endif + +/* "kernel RAM" for linker VMA allocations starts at the offset */ + +/* Physical RAM location where the kernel image is loaded */ +#define PHYS_LOAD_ADDR (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET) + +#ifdef CONFIG_USERSPACE +#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN_PERM +#define APP_SHARED_ALIGN MMU_PAGE_ALIGN_PERM +#endif + +MEMORY + { +#if defined(Z_VM_KERNEL) + ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL +#endif + RAM (wx) : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE + +#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + FLASH (rw) : ORIGIN = FLASH_ROM_ADDR, LENGTH = FLASH_ROM_SIZE +#endif + + /* + * On 32-bit x86, fake memory area for build-time IDT generation data. + * + * It doesn't matter where this region goes as it is stripped from the + * final ELF image. The address doesn't even have to be valid on the + * target. However, it shouldn't overlap any other regions. + */ + + IDT_LIST : ORIGIN = 0xFFFF1000, LENGTH = 2K + } + +#if defined(Z_VM_KERNEL) + #define ROMABLE_REGION ROM + #define RAMABLE_REGION RAM +#else + #define ROMABLE_REGION RAM + #define RAMABLE_REGION RAM +#endif + +#ifdef CONFIG_MMU + #define MMU_PAGE_ALIGN . = ALIGN(CONFIG_MMU_PAGE_SIZE); +#else + #define MMU_PAGE_ALIGN +#endif + +#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + +#undef SECTION_PROLOGUE +#define SECTION_PROLOGUE(name, options, align) \ + name options : ALIGN_WITH_INPUT align + +#undef SECTION_DATA_PROLOGUE +#define SECTION_DATA_PROLOGUE(name, options, align) \ + name options : ALIGN_WITH_INPUT align + +#undef GROUP_ROM_LINK_IN +#define GROUP_ROM_LINK_IN(vregion, lregion) > vregion AT > lregion + +#undef GROUP_DATA_LINK_IN +#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion + +#undef GROUP_NOLOAD_LINK_IN +#define GROUP_NOLOAD_LINK_IN(vregion, lregion) > vregion AT > lregion + +#endif + +/* Used to align areas with separate memory permission characteristics + * so that the page permissions can be set in the MMU. Without this, + * the kernel is just one blob with the same RWX permissions on all RAM + */ +#ifdef CONFIG_SRAM_REGION_PERMISSIONS + #define MMU_PAGE_ALIGN_PERM MMU_PAGE_ALIGN +#else + #define MMU_PAGE_ALIGN_PERM +#endif + +/* For all source files under arch/x86/. */ +#define LIB_ARCH_X86_IN_SECT(lsect) \ + *libarch__x86__core.a.a:(.##lsect) \ + *libarch__x86__core.a:(.##lsect##.*) + +#ifdef CONFIG_MINIMAL_LIBC +/* For all source files under lib/libc/minimal/. + * These files includes, for example, math and string functions. + */ +#define LIB_C_IN_SECT(lsect) \ + *liblib__libc__minimal.a:(.##lsect) \ + *liblib__libc__minimal.a:(.##lsect##.*) + +#endif /* CONFIG_MINIMAL_LIBC */ + +#ifdef CONFIG_NEWLIB_LIBC +/* For Newlib libc-hook.c. */ +#define LIB_C_IN_SECT(lsect) \ + *liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect) \ + *liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect##.*) + +#endif /* CONFIG_NEWLIB_LIBC */ + +/* + * For drivers that are usually used (e.g. serial) + */ +#define LIB_DRIVERS_IN_SECT(lsect) \ + *libdrivers__serial.a:(.##lsect) \ + *libdrivers__serial.a:(.##lsect##.*) \ + *hpet.c.obj(.##lsect) \ + *hpet.c.obj(.##lsect##.*) \ + *intc_ioapic.c.obj(.##lsect) \ + *intc_ioapic.c.obj(.##lsect##.*) \ + *intc_loapic.c.obj(.##lsect) \ + *intc_loapic.c.obj(.##lsect##.*) \ + *intc_system_apic.c.obj(.##lsect) \ + *intc_system_apic.c.obj(.##lsect##.*) \ + *rand32_timer.c.obj(.##lsect) \ + *rand32_timer.c.obj(.##lsect##.*) \ + *uart_console.c.obj(.##lsect) \ + *uart_console.c.obj(.##lsect##.*) + +/* For all source files under kernel/. and kernel related files */ +#define LIB_KERNEL_IN_SECT(lsect) \ + *libkernel.a:(.##lsect) \ + *libkernel.a:(.##lsect##.*) \ + *libsubsys__demand_paging__*.a:(.##lsect) \ + *libsubsys__demand_paging__*.a:(.##lsect##.*) + +/* For particular file packaged in libzephyr.a. */ +#define LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, objfile) \ + *libzephyr.a:objfile.c.obj(.##lsect) \ + *libzephyr.a:objfile.c.obj(.##lsect##.*) + +/* For source files under lib/os/ with commonly used functions. */ +#define LIB_ZEPHYR_IN_SECT(lsect) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, assert) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, bitarray) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_complete) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_nano) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, configs) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap-validate) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, mutex) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, notify) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, printk) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sem) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, stdout_console) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sys_clock_init) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, rb) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, thread_entry) \ + LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, work_q) + +/* + * Catch all for all internal/external kernel functions + * as they are usually defined as "static inline" where + * they are attached to the source which uses them. + * Hence the need to specify them here so they can be pinned. + */ +#define ZEPHYR_KERNEL_FUNCS_IN_SECT \ + *(.text.atomic_*) \ + *(.text.k_*) \ + *(.text.sys_*_bit) \ + *(.text.sys_bitfield_*) \ + *(.text.sys_clock_hw_cycles_per_sec) \ + *(.text.sys_cache_*) \ + *(.text.sys_dcache_*) \ + *(.text.sys_icache_*) \ + *(.text.sys_mutex_*) \ + *(.text.sys_notify_*) \ + *(.text.sys_dlist_*) \ + *(.text.sys_slist_*) \ + *(.text.sys_sflist_*) \ + *(.text.sys_sfnode_*) \ + *(.text.sys_io_*) \ + *(.text.sys_in*) \ + *(.text.sys_out*) \ + *(.text.sys_read*) \ + *(.text.sys_write*) \ + *(.text.sys_get_be*) \ + *(.text.sys_get_le*) \ + *(.text.sys_put_be*) \ + *(.text.sys_put_le*) \ + *(.text.sys_mem_swap) \ + *(.text.sys_memcpy_swap) \ + *(.text.z_*) + +epoint = Z_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY); +ENTRY(epoint) + +/* SECTIONS definitions */ +SECTIONS + { + +#include + + /DISCARD/ : + { + *(.plt) + } + + /DISCARD/ : + { + *(.iplt) + } + +#ifdef CONFIG_LINKER_USE_BOOT_SECTION + + SECTION_PROLOGUE(boot.text,,) + { +#include + + MMU_PAGE_ALIGN + lnkr_boot_start = .; + z_mapped_start = .; + + lnkr_boot_text_start = .; + + KEEP(*(.boot_text.__start)) + *(.boot_text) + *(.boot_text.*) + + *(.text.k_mem_paging_backing_store_init) + *(.text.k_mem_paging_eviction_init) + + MMU_PAGE_ALIGN_PERM + + lnkr_boot_text_end = .; + } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(boot.rodata,,) + { + MMU_PAGE_ALIGN_PERM + + lnkr_boot_rodata_start = .; + + *(.boot_rodata) + *(.boot_rodata.*) + + MMU_PAGE_ALIGN_PERM + + lnkr_boot_rodata_end = .; + } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(boot.data,,) + { + MMU_PAGE_ALIGN_PERM + + . = ALIGN(4); + + lnkr_boot_data_start = .; + + *(.boot_data) + *(.boot_data.*) + + lnkr_boot_data_end = .; + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(boot.bss, (NOLOAD),) + { + . = ALIGN(4); + + lnkr_boot_bss_start = .; + + *(.boot_bss) + *(.boot_bss.*) + + lnkr_boot_bss_end = .; + } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(boot.noinit, (NOLOAD),) + { + . = ALIGN(4); + + lnkr_boot_noinit_start = .; + + *(.boot_noinit) + *(.boot_noinit.*) + + lnkr_boot_noinit_end = .; + + MMU_PAGE_ALIGN + + lnkr_boot_end = .; + } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + lnkr_boot_text_size = lnkr_boot_text_end - lnkr_boot_text_start; + lnkr_boot_rodata_size = lnkr_boot_rodata_end - lnkr_boot_rodata_start; + lnkr_boot_data_size = lnkr_boot_data_end - lnkr_boot_data_start; + lnkr_boot_bss_size = lnkr_boot_bss_end - lnkr_boot_bss_start; + lnkr_boot_noinit_size = lnkr_boot_noinit_end - lnkr_boot_noinit_start; + +#endif /* CONFIG_LINKER_USE_BOOT_SECTION */ + +#ifdef CONFIG_LINKER_USE_PINNED_SECTION + + SECTION_PROLOGUE(pinned.text,,) + { +#ifndef CONFIG_LINKER_USE_BOOT_SECTION +#include +#endif + + MMU_PAGE_ALIGN + + lnkr_pinned_start = .; + +#ifndef CONFIG_LINKER_USE_BOOT_SECTION + z_mapped_start = .; +#endif + + lnkr_pinned_text_start = .; + + LIB_KERNEL_IN_SECT(text) + LIB_ARCH_X86_IN_SECT(text) + *(.text._OffsetAbsSyms) + + *(.pinned_text) + *(.pinned_text.*) + + LIB_ZEPHYR_IN_SECT(text) + LIB_C_IN_SECT(text) + LIB_DRIVERS_IN_SECT(text) + + *_divdi3.o(.text) + *_udivdi3.o(.text) + *_udivmoddi4.o(.text) + *_umoddi3.o(.text) + *_popcountsi2.o(.text) + + *(.gnu.linkonce.t.exc_*) + + *(.text.*.constprop) + *(.text.*.constprop.*) + +#ifdef CONFIG_NEWLIB_LIBC + *libc.a:(.text) + *libc.a:(.text.*) +#endif /* CONFIG_NEWLIB_LIBC */ + + ZEPHYR_KERNEL_FUNCS_IN_SECT + +#include + + MMU_PAGE_ALIGN_PERM + + lnkr_pinned_text_end = .; + } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + MMU_PAGE_ALIGN_PERM + + lnkr_pinned_rodata_start = .; + +#include +#include + + SECTION_PROLOGUE(pinned.rodata,,) + { +#include + + LIB_KERNEL_IN_SECT(rodata) + LIB_ARCH_X86_IN_SECT(rodata) + + *(.pinned_rodata) + *(.pinned_rodata.*) + + LIB_ZEPHYR_IN_SECT(rodata) + LIB_C_IN_SECT(rodata) + LIB_DRIVERS_IN_SECT(rodata) + + /* Static strings */ + *(.rodata.str*.*) + *(.rodata.*.str*.*) + +#ifdef CONFIG_NEWLIB_LIBC + *libc.a:(.rodata) + *libc.a:(.rodata.*) +#endif /* CONFIG_NEWLIB_LIBC */ + +#include + +#include + + MMU_PAGE_ALIGN_PERM + + lnkr_pinned_rodata_end = .; + } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(pinned.data,,) + { + MMU_PAGE_ALIGN_PERM + + lnkr_pinned_data_start = .; + + . = ALIGN(4); + +#include +#include + + LIB_KERNEL_IN_SECT(data) + LIB_ARCH_X86_IN_SECT(data) + + *(.pinned_data) + *(.pinned_data.*) + + LIB_ZEPHYR_IN_SECT(data) + LIB_C_IN_SECT(data) + LIB_DRIVERS_IN_SECT(data) + + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +#include +#include +#include + + lnkr_pinned_data_end = .; + + SECTION_PROLOGUE(pinned.bss, (NOLOAD),) + { + . = ALIGN(4); + + lnkr_pinned_bss_start = .; + + LIB_KERNEL_IN_SECT(bss) + LIB_ARCH_X86_IN_SECT(bss) + + *(.pinned_bss) + *(.pinned_bss.*) + + LIB_ZEPHYR_IN_SECT(bss) + LIB_C_IN_SECT(bss) + LIB_DRIVERS_IN_SECT(bss) + + lnkr_pinned_bss_end = .; + } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +#ifdef CONFIG_USERSPACE + /* PINNED APP SHARED MEMORY REGION */ +#include + + _app_smem_pinned_size = _app_smem_pinned_end - _app_smem_pinned_start; + _app_smem_pinned_num_words = _app_smem_pinned_size >> 2; +#endif /* CONFIG_USERSPACE */ + + SECTION_PROLOGUE(pinned.noinit, (NOLOAD),) + { + . = ALIGN(4); + + lnkr_pinned_noinit_start = .; + + LIB_KERNEL_IN_SECT(noinit) + LIB_ARCH_X86_IN_SECT(noinit) + + *(.pinned_noinit) + *(.pinned_noinit.*) + + LIB_ZEPHYR_IN_SECT(noinit) + LIB_C_IN_SECT(noinit) + LIB_DRIVERS_IN_SECT(noinit) + +#ifdef CONFIG_ZTEST + /* For tests/kernel/mem_slab/ tests */ + *(.noinit.*.k_mem_slab_buf_*) + + /* For tests/kernel/mem_heap tests */ + *(.noinit.*.kheap_buf_*) + + /* Pin ztest_thread_stack. + * This must be done or else double fault + * may arise: testing exceptions while + * page fault for the ztest stack. + */ + *libsubsys__testsuite__ztest.a:(.noinit.*) +#endif + + lnkr_pinned_noinit_end = .; + + MMU_PAGE_ALIGN + + lnkr_pinned_end = .; + + } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + lnkr_pinned_text_size = lnkr_pinned_text_end - lnkr_pinned_text_start; + lnkr_pinned_rodata_size = lnkr_pinned_rodata_end - lnkr_pinned_rodata_start; + lnkr_pinned_data_size = lnkr_pinned_data_end - lnkr_pinned_data_start; + lnkr_pinned_bss_size = lnkr_pinned_bss_end - lnkr_pinned_bss_start; + lnkr_pinned_noinit_size = lnkr_pinned_noinit_end - lnkr_pinned_noinit_start; + +#endif /* CONFIG_LINKER_USE_PINNED_SECTION */ + +#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) +/* From now on, put symbols into FLASH */ +#undef ROMABLE_REGION +#define ROMABLE_REGION FLASH + + /* This is to align the following sections in flash + * to their corresponding virtual addresses. + * In other words, the offset from start of flash + * for these sections would be the same from start of + * their virtual addresses. This provides a simple and + * direct mapping from backing store. + */ + flash_load_offset : + { + . = FLASH_ROM_ADDR + (lnkr_pinned_end - KERNEL_BASE_ADDR); + } > FLASH AT > FLASH + +#endif + + GROUP_START(ROMABLE_REGION) + + . = ALIGN(8); + + SECTION_PROLOGUE(_TEXT_SECTION_NAME,,) + { + __text_region_start = .; + +#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \ + !defined(CONFIG_LINKER_USE_PINNED_SECTION) + z_mapped_start = .; +#endif + +#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \ + !defined(CONFIG_LINKER_USE_PINNED_SECTION) +/* Located in generated directory. This file is populated by calling + * zephyr_linker_sources(ROM_START ...). This typically contains the vector + * table and debug information. + */ +#include +#endif + + /* Needs KEEP() as ENTRY() is given a physical address */ + KEEP(*(.text.__start)) + *(.text) + *(".text.*") + *(.gnu.linkonce.t.*) + *(.init) + *(.fini) + *(.eini) + +#ifndef CONFIG_LINKER_USE_PINNED_SECTION +#include +#endif + + MMU_PAGE_ALIGN_PERM + } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + __text_region_end = .; + __text_region_size = __text_region_end - __text_region_start; + __rodata_region_start = .; + +#ifndef CONFIG_LINKER_USE_PINNED_SECTION +#include +#include +#endif + + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + { + *(.rodata) + *(".rodata.*") + *(.gnu.linkonce.r.*) + +#ifndef CONFIG_DYNAMIC_INTERRUPTS +#ifndef CONFIG_LINKER_USE_PINNED_SECTION +#include +#endif /* !CONFIG_LINKER_USE_PINNED_SECTION */ +#endif /* CONFIG_DYNAMIC_INTERRUPTS */ + +#ifndef CONFIG_LINKER_USE_PINNED_SECTION +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + +#include +#endif + } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + +#include + + MMU_PAGE_ALIGN_PERM + /* ROM ends here, position counter will now be in RAM areas */ + __rodata_region_end = .; + __rodata_region_size = __rodata_region_end - __rodata_region_start; + GROUP_END(ROMABLE_REGION) + /* + * Needed for dynamic linking which we do not have, do discard + */ + /DISCARD/ : { + *(.got.plt) + *(.igot.plt) + *(.got) + *(.igot) + } + /* RAMABLE_REGION */ + GROUP_START(RAMABLE_REGION) + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + +#ifdef CONFIG_USERSPACE + /* APP SHARED MEMORY REGION */ +#include + + _image_ram_start = _app_smem_start; + _app_smem_size = _app_smem_end - _app_smem_start; + _app_smem_num_words = _app_smem_size >> 2; + _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME); +#endif /* CONFIG_USERSPACE */ + + SECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),) + { + MMU_PAGE_ALIGN_PERM +#if !defined(CONFIG_USERSPACE) + _image_ram_start = .; +#endif + /* + * For performance, BSS section is forced to be both 4 byte aligned and + * a multiple of 4 bytes. + */ + . = ALIGN(4); + __kernel_ram_start = .; + __bss_start = .; + + *(.bss) + *(".bss.*") + *(COMMON) + *(".kernel_bss.*") + + /* + * As memory is cleared in words only, it is simpler to ensure the BSS + * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes. + */ + . = ALIGN(4); + __bss_end = .; + } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + __bss_num_words = (__bss_end - __bss_start) >> 2; + +#include + + MMU_PAGE_ALIGN_PERM + + SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) + { + + __data_ram_start = .; + + *(.data) + *(".data.*") + *(".kernel.*") + +#ifdef CONFIG_DYNAMIC_INTERRUPTS +#ifndef CONFIG_LINKER_USE_PINNED_SECTION +#include +#endif /* !CONFIG_LINKER_USE_PINNED_SECTION */ +#endif /* CONFIG_DYNAMIC_INTERRUPTS */ + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + +#ifndef CONFIG_LINKER_USE_PINNED_SECTION +#include +#endif /* !CONFIG_LINKER_USE_PINNED_SECTION */ + + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + __data_rom_start = LOADADDR(_DATA_SECTION_NAME); + +#include + +#ifndef CONFIG_LINKER_USE_PINNED_SECTION +#include +#include + +/* Must be last in RAM */ +#include +#endif /* !CONFIG_LINKER_USE_PINNED_SECTION */ + + MMU_PAGE_ALIGN + __data_ram_end = .; + + /* All unused memory also owned by the kernel for heaps */ + __kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE; + __kernel_ram_size = __kernel_ram_end - __kernel_ram_start; + + _image_ram_end = .; + _image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start; + + z_mapped_end = .; + z_mapped_size = z_mapped_end - z_mapped_start; + _end = .; /* end of image */ + + GROUP_END(RAMABLE_REGION) + +#ifndef LINKER_ZEPHYR_FINAL + /* static interrupts */ + SECTION_PROLOGUE(intList,,) + { + KEEP(*(.spurIsr)) + KEEP(*(.spurNoErrIsr)) + KEEP(*(.intList)) + KEEP(*(.gnu.linkonce.intList.*)) + } > IDT_LIST +#else + /DISCARD/ : + { + KEEP(*(.spurIsr)) + KEEP(*(.spurNoErrIsr)) + KEEP(*(.intList)) + KEEP(*(.gnu.linkonce.intList.*)) + } +#endif + + + +/* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ +#include + +#include + + /DISCARD/ : { *(.note.GNU-stack) } + + } diff --git a/boards/x86/qemu_x86/qemu_x86_tiny_defconfig b/boards/x86/qemu_x86/qemu_x86_tiny_defconfig index 5ff1480301d1..c4280c304d26 100644 --- a/boards/x86/qemu_x86/qemu_x86_tiny_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_tiny_defconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y +CONFIG_BOARD_QEMU_X86_TINY=y CONFIG_HPET_TIMER=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y @@ -16,14 +16,19 @@ CONFIG_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT_SHIFT=5 CONFIG_X86_PAE=n CONFIG_X86_COMMON_PAGE_TABLE=y CONFIG_X86_KPTI=n + CONFIG_KERNEL_VM_SIZE=0x400000 -CONFIG_KERNEL_VM_BASE=0x0 +CONFIG_KERNEL_VM_BASE=0x40000000 CONFIG_KERNEL_VM_OFFSET=0x100000 CONFIG_SRAM_OFFSET=0 + CONFIG_DEMAND_PAGING=y -CONFIG_BACKING_STORE_RAM=y +CONFIG_BACKING_STORE_QEMU_X86_TINY_FLASH=y + +CONFIG_LINKER_USE_BOOT_SECTION=y +CONFIG_LINKER_USE_PINNED_SECTION=y +CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT=n diff --git a/boards/x86/qemu_x86/qemu_x86_virt_defconfig b/boards/x86/qemu_x86/qemu_x86_virt_defconfig index 9ca4c8cec46e..755c65908c46 100644 --- a/boards/x86/qemu_x86/qemu_x86_virt_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_virt_defconfig @@ -16,7 +16,6 @@ CONFIG_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT_SHIFT=5 CONFIG_SRAM_OFFSET=0x100000 CONFIG_KERNEL_VM_SIZE=0x400000 diff --git a/boards/x86/qemu_x86/qemu_x86_xip_defconfig b/boards/x86/qemu_x86/qemu_x86_xip_defconfig index 4f47b5c63901..929126713e34 100644 --- a/boards/x86/qemu_x86/qemu_x86_xip_defconfig +++ b/boards/x86/qemu_x86/qemu_x86_xip_defconfig @@ -15,5 +15,4 @@ CONFIG_DEBUG_INFO=y CONFIG_SCHED_SCALABLE=y CONFIG_WAITQ_SCALABLE=y CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT_SHIFT=5 CONFIG_XIP=y diff --git a/boards/x86/up_squared/doc/index.rst b/boards/x86/up_squared/doc/index.rst index 2aa781ed2e9b..2f9d8a126814 100644 --- a/boards/x86/up_squared/doc/index.rst +++ b/boards/x86/up_squared/doc/index.rst @@ -61,38 +61,6 @@ Use the following procedures for booting an image on a UP Squared board. :local: :backlinks: top -Creating a GRUB2 Boot Loader Image from a Linux Host -==================================================== - -If you are having problems running an application using the preinstalled -copy of GRUB, follow these steps to test on supported boards using a custom GRUB. - -#. Install the requirements to build GRUB on your host machine. - - On Ubuntu, type: - - .. code-block:: console - - $ sudo apt-get install bison autoconf libopts25-dev flex automake \ - pkg-config gettext autopoint - - On Fedora, type: - - .. code-block:: console - - $ sudo dnf install gnu-efi bison m4 autoconf help2man flex \ - automake texinfo gettext-devel - -#. Clone and build the GRUB repository using the script in Zephyr tree, type: - - .. code-block:: console - - $ cd $ZEPHYR_BASE - $ ./boards/x86/common/scripts/build_grub.sh x86_64 - -#. Find the binary at - :file:`$ZEPHYR_BASE/boards/x86/common/scripts/grub/bin/grub_x86_64.efi`. - Build Zephyr application ======================== @@ -106,9 +74,8 @@ Build Zephyr application .. note:: - A stripped project image file named :file:`zephyr.strip` is automatically - created in the build directory after the application is built. This image - has removed debug information from the :file:`zephyr.elf` file. + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. Preparing the Boot Device ========================= @@ -140,33 +107,12 @@ a UP Squared board. the USB flash drive. Or else you may erase other storage devices on your system, and will render the system unusable afterwards. -#. Create the following directories - - :file:`efi` - - :file:`efi/boot` - - :file:`kernel` - -#. Copy the kernel file :file:`zephyr/zephyr.strip` to the :file:`$USB/kernel` folder. - -#. Copy your built version of GRUB to :file:`$USB/efi/boot/bootx64.efi` - -#. Create :file:`$USB/efi/boot/grub.cfg` containing the following: - - .. code-block:: console - - set default=0 - set timeout=10 - - menuentry "Zephyr Kernel" { - multiboot /kernel/zephyr.strip - } +#. Copy the Zephyr EFI image file :file:`zephyr/zephyr.efi` to the USB drive. Booting the UP Squared Board ============================ -Boot the UP Squared board from the boot device using GRUB2 via USB flash drive. +Boot the UP Squared board to the EFI shell with USB flash drive connected. #. Insert the prepared boot device (USB flash drive) into the UP Squared board. @@ -187,15 +133,13 @@ Boot the UP Squared board from the boot device using GRUB2 via USB flash drive. Press or to enter setup. #. From the menu that appears, select the menu entry that describes - that particular type of USB flash drive. + that particular EFI shell. - GRUB2 starts and a menu shows entries for the items you added - to the file :file:`grub.cfg`. +#. From the EFI shell select Zephyr EFI image to boot. -#. Select the image you want to boot and press :guilabel:`Enter`. + .. code-block:: console - When the boot process completes, you have finished booting the - Zephyr application image. + Shell> fs0:zephyr.efi .. note:: You can safely ignore this message if it appears: @@ -216,9 +160,6 @@ Build Zephyr image Prepare Linux host ------------------ -#. Follow `Creating a GRUB2 Boot Loader Image from a Linux Host`_ steps - to create grub binary. - #. Install DHCP, TFTP servers. For example ``dnsmasq`` .. code-block:: console @@ -240,36 +181,17 @@ Prepare Linux host # tftp enable-tftp tftp-root=/srv/tftp - dhcp-boot=grub_x86_64.efi + dhcp-boot=zephyr.efi - ``grub_x86_64.efi`` is a grub binary created above. + ``zephyr.efi`` is a Zephyr EFI binary created above. -#. Create the following directories inside TFTP root :file:`/srv/tftp` +#. Copy the Zephyr EFI image :file:`zephyr/zephyr.efi` to the + :file:`/srv/tftp` folder. .. code-block:: console - $ sudo mkdir -p /srv/tftp/EFI/BOOT - $ sudo mkdir -p /srv/tftp/kernel - -#. Copy the Zephyr image :file:`zephyr/zephyr.strip` to the - :file:`/srv/tftp/kernel` folder. - - .. code-block:: console - - $ sudo cp zephyr/zephyr.strip /srv/tftp/kernel - -#. Copy your built version of GRUB to :file:`/srv/tftp/grub_x86_64.efi` - -#. Create :file:`/srv/tftp/EFI/BOOT/grub.cfg` containing the following: - - .. code-block:: console - - set default=0 - set timeout=10 + $ sudo cp zephyr/zephyr.efi /srv/tftp - menuentry "Zephyr Kernel" { - multiboot /kernel/zephyr.strip - } #. TFTP root should be looking like: @@ -277,12 +199,7 @@ Prepare Linux host $ tree /srv/tftp /srv/tftp - ├── EFI - │   └── BOOT - │   └── grub.cfg - ├── grub_x86_64.efi - └── kernel - └── zephyr.strip + └── zephyr.efi #. Restart ``dnsmasq`` service: @@ -329,9 +246,7 @@ Booting UP Squared .. code-block:: console $ journalctl -f -u dnsmasq - dnsmasq-tftp[5386]: sent /srv/tftp/grub_x86_64.efi to 10.1.1.28 - dnsmasq-tftp[5386]: sent /srv/tftp/EFI/BOOT/grub.cfg to 10.1.1.28 - dnsmasq-tftp[5386]: sent /srv/tftp/kernel/zephyr.strip to 10.1.1.28 + dnsmasq-tftp[5386]: sent /srv/tftp/zephyr.efi to 10.1.1.28 #. When the boot process completes, you have finished booting the Zephyr application image. diff --git a/boards/xtensa/esp32/CMakeLists.txt b/boards/xtensa/esp32/CMakeLists.txt index bc72a5cdeb3d..7425e27fd275 100644 --- a/boards/xtensa/esp32/CMakeLists.txt +++ b/boards/xtensa/esp32/CMakeLists.txt @@ -19,6 +19,10 @@ if(CONFIG_BOOTLOADER_ESP_IDF) -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_BOARD} -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} BUILD_COMMAND ${CMAKE_COMMAND} --build . INSTALL_COMMAND "" # This particular build system has no install command diff --git a/boards/xtensa/esp32/Kconfig.defconfig b/boards/xtensa/esp32/Kconfig.defconfig index 7711584fb8b8..1c9cf9283d42 100644 --- a/boards/xtensa/esp32/Kconfig.defconfig +++ b/boards/xtensa/esp32/Kconfig.defconfig @@ -10,13 +10,6 @@ config BOARD config ENTROPY_ESP32_RNG default y if ENTROPY_GENERATOR -if LOG - -config LOG_DETECT_MISSED_STRDUP - default n - -endif - if BT config HEAP_MEM_POOL_SIZE diff --git a/boards/xtensa/esp32/doc/index.rst b/boards/xtensa/esp32/doc/index.rst index 119edb246d45..87bbfa34bbb1 100644 --- a/boards/xtensa/esp32/doc/index.rst +++ b/boards/xtensa/esp32/doc/index.rst @@ -84,7 +84,6 @@ On Linux and macOS: export ZEPHYR_TOOLCHAIN_VARIANT="espressif" export ESPRESSIF_TOOLCHAIN_PATH="${HOME}/.espressif/tools/xtensa-esp32-elf/esp-2020r3-8.4.0/xtensa-esp32-elf" - export PATH=$PATH:$ESPRESSIF_TOOLCHAIN_PATH/bin On Windows: @@ -143,7 +142,9 @@ specific options for the ESP32 board, as listed here: --esp-idf-path ESP_IDF_PATH path to ESP-IDF --esp-device ESP_DEVICE - serial port to flash, default /dev/ttyUSB0 + serial port to flash, default $ESPTOOL_PORT if defined. + If not, esptool will loop over available serial ports until + it finds ESP32 device to flash. --esp-baud-rate ESP_BAUD_RATE serial baud rate, default 921600 --esp-flash-size ESP_FLASH_SIZE diff --git a/boards/xtensa/esp32/esp32_defconfig b/boards/xtensa/esp32/esp32_defconfig index 41046fc6aa64..c9dedd181880 100644 --- a/boards/xtensa/esp32/esp32_defconfig +++ b/boards/xtensa/esp32/esp32_defconfig @@ -32,4 +32,3 @@ CONFIG_I2C_1=y CONFIG_CLOCK_CONTROL=y CONFIG_BOOTLOADER_ESP_IDF=y -CONFIG_MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE=n diff --git a/boards/xtensa/esp32s2_saola/CMakeLists.txt b/boards/xtensa/esp32s2_saola/CMakeLists.txt new file mode 100644 index 000000000000..1044915b66a4 --- /dev/null +++ b/boards/xtensa/esp32s2_saola/CMakeLists.txt @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + python ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x1000 --flash-size 4MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND python ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-boot-address=0x1000") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + + board_finalize_runner_args(esp32 "--esp-app-address=0x10000") + +endif() diff --git a/boards/xtensa/esp32s2_saola/Kconfig.board b/boards/xtensa/esp32s2_saola/Kconfig.board new file mode 100644 index 000000000000..5accd94308af --- /dev/null +++ b/boards/xtensa/esp32s2_saola/Kconfig.board @@ -0,0 +1,8 @@ +# ESP32S2 saola board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S2_SAOLA + bool "ESP32S2 Saola Board" + depends on SOC_ESP32S2 diff --git a/boards/xtensa/esp32s2_saola/Kconfig.defconfig b/boards/xtensa/esp32s2_saola/Kconfig.defconfig new file mode 100644 index 000000000000..595bd03aa2f6 --- /dev/null +++ b/boards/xtensa/esp32s2_saola/Kconfig.defconfig @@ -0,0 +1,8 @@ +# ESP32S2 Saola board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "esp32s2_saola" + depends on BOARD_ESP32S2_SAOLA diff --git a/boards/xtensa/esp32s2_saola/board.cmake b/boards/xtensa/esp32s2_saola/board.cmake new file mode 100644 index 000000000000..71735daa671e --- /dev/null +++ b/boards/xtensa/esp32s2_saola/board.cmake @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) diff --git a/boards/xtensa/esp32s2_saola/doc/index.rst b/boards/xtensa/esp32s2_saola/doc/index.rst new file mode 100644 index 000000000000..000df2878b6c --- /dev/null +++ b/boards/xtensa/esp32s2_saola/doc/index.rst @@ -0,0 +1,141 @@ +.. _esp32s2_saola: + +ESP32-S2 +######## + +Overview +******** + +ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be secure and +cost-effective, with a high performance and a rich set of IO capabilities. [1]_ + +The features include the following: + +- RSA-3072-based secure boot +- AES-XTS-256-based flash encryption +- Protected private key and device secrets from software access +- Cryptographic accelerators for enhanced performance +- Protection against physical fault injection attacks +- Various peripherals: + + - 43x programmable GPIOs + - 14x configurable capacitive touch GPIOs + - USB OTG + - LCD interface + - camera interface + - SPI + - I2S + - UART + - ADC + - DAC + +System requirements +******************* + +Build Environment Setup +======================= + +Some variables must be exported into the environment prior to building this port. +Find more information at :ref:`env_vars` on how to keep this settings saved in you environment. + +.. note:: + + In case of manual toolchain installation, set :file:`ESPRESSIF_TOOLCHAIN_PATH` accordingly. + Otherwise, set toolchain path as below. If necessary. + +On Linux and macOS: + +.. code-block:: console + + export ZEPHYR_TOOLCHAIN_VARIANT="espressif" + export ESPRESSIF_TOOLCHAIN_PATH="${HOME}/.espressif/tools/xtensa-esp32s2-elf/esp-2020r3-8.4.0/xtensa-esp32s2-elf" + +On Windows: + +.. code-block:: console + + # on CMD: + set ESPRESSIF_TOOLCHAIN_PATH=%USERPROFILE%\.espressif\tools\xtensa-esp32s2-elf\esp-2020r3-8.4.0\xtensa-esp32s2-elf + set ZEPHYR_TOOLCHAIN_VARIANT=espressif + set PATH=%PATH%;%ESPRESSIF_TOOLCHAIN_PATH%\bin + + # on PowerShell + $env:ESPRESSIF_TOOLCHAIN_PATH="$env:USERPROFILE\.espressif\tools\xtensa-esp32s2-elf\esp-2020r3-8.4.0\xtensa-esp32s2-elf" + $env:ZEPHYR_TOOLCHAIN_VARIANT="espressif" + $env:Path += "$env:ESPRESSIF_TOOLCHAIN_PATH\bin" + +Finally, retrieve required submodules to build this port. This might take a while for the first time: + +.. code-block:: console + + west espressif update + +.. note:: + + It is recommended running the command above after :file:`west update` so that submodules also get updated. + +Flashing +======== + +The usual ``flash`` target will work with the ``esp32s2_saola`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: flash + +Refer to :ref:`build_an_application` and :ref:`application_run` for +more details. + +It's impossible to determine which serial port the ESP32-S2 board is +connected to, as it uses a generic RS232-USB converter. The default of +``/dev/ttyUSB0`` is provided as that's often the assigned name on a Linux +machine without any other such converters. + +The baud rate of 921600bps is recommended. If experiencing issues when +flashing, try halving the value a few times (460800, 230400, 115200, +etc). + +All flashing options are now handled by the :ref:`west` tool, including flashing +with custom options such as a different serial port. The ``west`` tool supports +specific options for the ESP32-S2 board, as listed here: + + --esp-idf-path ESP_IDF_PATH + path to ESP-IDF + --esp-device ESP_DEVICE + serial port to flash, default $ESPTOOL_PORT if defined. + If not, esptool will loop over available serial ports until + it finds ESP32 device to flash. + --esp-baud-rate ESP_BAUD_RATE + serial baud rate, default 921600 + --esp-flash-size ESP_FLASH_SIZE + flash size, default "detect" + --esp-flash-freq ESP_FLASH_FREQ + flash frequency, default "40m" + --esp-flash-mode ESP_FLASH_MODE + flash mode, default "dio" + --esp-tool ESP_TOOL if given, complete path to espidf. default is to + search for it in [ESP_IDF_PATH]/components/esptool_py/ + esptool/esptool.py + --esp-flash-bootloader ESP_FLASH_BOOTLOADER + Bootloader image to flash + --esp-flash-partition_table ESP_FLASH_PARTITION_TABLE + Partition table to flash + +For example, to flash to ``/dev/ttyUSB2``, use the following command after +having build the application in the ``build`` directory: + + +.. code-block:: console + + west flash -d build/ --skip-rebuild --esp-device /dev/ttyUSB2 + + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-s2 +.. _`ESP32S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf +.. _`ESP32S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola.dts b/boards/xtensa/esp32s2_saola/esp32s2_saola.dts new file mode 100644 index 000000000000..f5dc69c5afc9 --- /dev/null +++ b/boards/xtensa/esp32s2_saola/esp32s2_saola.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "esp32s2_saola"; + compatible = "espressif,esp32s2"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola.yaml b/boards/xtensa/esp32s2_saola/esp32s2_saola.yaml new file mode 100644 index 000000000000..f7581cfdb29f --- /dev/null +++ b/boards/xtensa/esp32s2_saola/esp32s2_saola.yaml @@ -0,0 +1,6 @@ +identifier: esp32s2_saola +name: ESP32-S2 +type: mcu +arch: xtensa +toolchain: + - espressif diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig new file mode 100644 index 000000000000..f841cd5ff572 --- /dev/null +++ b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XTENSA_RESET_VECTOR=n + +CONFIG_BOARD_ESP32S2_SAOLA=y +CONFIG_SOC_ESP32S2=y +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_ROM_ESP32S2=y + +CONFIG_XTENSA_USE_CORE_CRT1=n + +CONFIG_PINMUX=y +CONFIG_PINMUX_ESP32=y + +CONFIG_GPIO=y +CONFIG_GPIO_ESP32=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BOOTLOADER_ESP_IDF=y diff --git a/boards/xtensa/intel_adsp_cavs15/tools/adsplog.py b/boards/xtensa/intel_adsp_cavs15/tools/adsplog.py index c5efb4cc050b..a7446ad269fd 100755 --- a/boards/xtensa/intel_adsp_cavs15/tools/adsplog.py +++ b/boards/xtensa/intel_adsp_cavs15/tools/adsplog.py @@ -42,6 +42,8 @@ mem = None sys_devices = "/sys/bus/pci/devices" +reset_logged = False + for dev_addr in os.listdir(sys_devices): class_file = sys_devices + "/" + dev_addr + "/class" pciclass = open(class_file).read() @@ -93,6 +95,7 @@ def read_slot(slot, mem): return (sid, msg.decode(encoding="utf-8", errors="ignore")) def read_hist(start_slot): + global reset_logged id0, msg = read_slot(start_slot, mem) # An invalid slot zero means no data has ever been placed in the @@ -101,11 +104,15 @@ def read_hist(start_slot): # been observed to hang the flash process (which I think can only # be a hardware bug). if start_slot == 0 and id0 < 0: - sys.stdout.write("===\n=== [ADSP Device Reset]\n===\n") - sys.stdout.flush() - time.sleep(1) + if not reset_logged: + sys.stdout.write("===\n=== [ADSP Device Reset?]\n===\n") + sys.stdout.flush() + reset_logged = True + time.sleep(0.1) return (0, 0, "") + reset_logged = False + # Start at zero and read forward to get the last data in the # buffer. We are always guaranteed that slot zero will contain # valid data if any slot contains valid data. diff --git a/boards/xtensa/intel_adsp_cavs15/tools/cavs-fw.py b/boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v15.py similarity index 94% rename from boards/xtensa/intel_adsp_cavs15/tools/cavs-fw.py rename to boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v15.py index f36deb755fca..56080ebff5c4 100755 --- a/boards/xtensa/intel_adsp_cavs15/tools/cavs-fw.py +++ b/boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v15.py @@ -1,7 +1,6 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: Apache-2.0 # Copyright(c) 2021 Intel Corporation. All rights reserved. - import ctypes import mmap import os @@ -30,6 +29,10 @@ def main(): with open(FW_FILE, "rb") as f: fw_bytes = f.read() + (magic, sz) = struct.unpack("4sI", fw_bytes[0:8]) + if magic == b'XMan': + fw_bytes = fw_bytes[sz:len(fw_bytes)] + (hda, sd, dsp) = map_regs() # Device register mappings # Turn on HDA "global processing enable" first, which actually @@ -59,7 +62,7 @@ def main(): # sleep seems to be needed; if we're banging on the memory window # during initial boot (before/while the window control registers # are configured?) the DSP hardware will hang fairly reliably. - time.sleep(0.01) + time.sleep(0.1) while (dsp.SRAM_FW_STATUS >> 24) != 5: pass # Send the DSP an IPC message to tell the device how to boot @@ -121,6 +124,16 @@ def map_regs(): pcidir = os.path.dirname(p) break + # Disengage runtime power management so the kernel doesn't put it to sleep + with open(pcidir + b"/power/control", "w") as ctrl: + ctrl.write("on") + + # Make sure PCI memory space access and busmastering are enabled. + # Also disable interrupts so as not to confuse the kernel. + with open(pcidir + b"/config", "wb+") as cfg: + cfg.seek(4) + cfg.write(b'\x06\x04') + hdamem = bar_map(pcidir, 0) # Standard HD Audio Registers diff --git a/boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v25.py b/boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v25.py new file mode 100755 index 000000000000..64a510168f90 --- /dev/null +++ b/boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v25.py @@ -0,0 +1,348 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: Apache-2.0 +# Copyright(c) 2021 Intel Corporation. All rights reserved. +import ctypes +import mmap +import os +import struct +import subprocess +import sys +import time +import logging + +# Intel Audio DSP firmware loader. No dependencies on anything +# outside this file beyond Python3 builtins. Pass a signed rimage +# file as the single argument. + +logging.basicConfig() +log = logging.getLogger("cavs-fw") +log.setLevel(logging.INFO) + +FW_FILE = sys.argv[1] + +PAGESZ = 4096 +HUGEPAGESZ = 2 * 1024 * 1024 +HUGEPAGE_FILE = "/dev/hugepages/cavs-fw-dma.tmp" + +HDA_PPCTL__GPROCEN = 1 << 30 +HDA_SD_CTL__TRAFFIC_PRIO = 1 << 18 +HDA_SD_CTL__START = 1 << 1 + +def main(): + if os.system("lsmod | grep -q snd_sof_pci") == 0: + log.warning("The Linux snd-sof-pci kernel module is loaded. While this") + log.warning(" loader will normally work in such circumstances, things") + log.warning(" will get confused if the system tries to touch the hardware") + log.warning(" simultaneously. Operation is most reliable if it is") + log.warning(" unloaded first.") + + # Make sure hugetlbfs is mounted (not there on chromeos) + os.system("mount | grep -q hugetlbfs ||" + + " (mkdir -p /dev/hugepages; " + + " mount -t hugetlbfs hugetlbfs /dev/hugepages)") + + with open(FW_FILE, "rb") as f: + fw_bytes = f.read() + + (magic, sz) = struct.unpack("4sI", fw_bytes[0:8]) + if magic == b'XMan': + log.info(f"Trimming {sz} bytes of extended manifest") + fw_bytes = fw_bytes[sz:len(fw_bytes)] + + (hda, sd, dsp) = map_regs() # Device register mappings + + # Reset the HDA device + log.info("Reset HDA device") + hda.GCTL = 0 + while hda.GCTL & 1: pass + hda.GCTL = 1 + while not hda.GCTL & 1: pass + + # Turn on HDA "global processing enable" first. As documented, + # this enables the audio DSP (vs. hardware HDA emulation). But it + # actually means "enable access to the ADSP registers in PCI BAR 4" (!) + log.info("Enable HDA global processing") + hda.PPCTL |= HDA_PPCTL__GPROCEN + + # Turn off the DSP CPUs (each byte of ADSPCS is a bitmask for each + # of 1-8 DSP cores: lowest byte controls "stall", the second byte + # engages "reset", the third controls power, and the highest byte + # is the output state for "powered" to be read after a state + # change. Set stall and reset, and turn off power for everything: + log.info(f"Powering down, ADSPCS = 0x{dsp.ADSPCS:x}") + dsp.ADSPCS = 0xffff + while dsp.ADSPCS & 0xff000000: pass + log.info(f"Powered down, ADSPCS = 0x{dsp.ADSPCS:x}") + + # Configure our DMA stream to transfer the firmware image + log.info(f"Configuring DMA output stream {hda_ostream_id}...") + (buf_list_addr, num_bufs) = setup_dma_mem(fw_bytes) + + # Reset stream + sd.CTL = 1 + while (sd.CTL & 1) == 0: pass + sd.CTL = 0 + while (sd.CTL & 1) == 1: pass + + sd.CTL = (1 << 20) # Set stream ID to anything non-zero + sd.BDPU = (buf_list_addr >> 32) & 0xffffffff + sd.BDPL = buf_list_addr & 0xffffffff + sd.CBL = len(fw_bytes) + sd.LVI = num_bufs - 1 + + # Enable "processing" on the output stream (send DMA to the DSP + # and not the audio output hardware) + hda.PPCTL |= (HDA_PPCTL__GPROCEN | (1 << hda_ostream_id)) + + # SPIB ("Software Position In Buffer") is an Intel HDA extension + # that puts a transfer boundary into the stream beyond which the + # other side will not read. The ROM wants to poll on a "buffer + # full" bit on the other side that only works with this enabled. + hda.SPBFCTL |= (1 << hda_ostream_id) + hda.SD_SPIB = len(fw_bytes) + + # Power up all the cores on the DSP and wait for CPU0 to show that + # it has power. Leave stall and reset high for now + log.info(f"Powering up DSP core #0, ADSPCS = 0x{dsp.ADSPCS:x}") + dsp.ADSPCS = 0x01ffff + while (dsp.ADSPCS & 0x01000000) == 0: pass + log.info(f"Powered up {ncores(dsp)} cores, ADSPCS = 0x{dsp.ADSPCS:x}") + + # Send the DSP an IPC message to tell the device how to boot + # ("PURGE_FW" means "load new code") and which DMA channel to use. + # The high bit is the "BUSY" signal bit that latches a device + # interrupt. + # + # Note: with cAVS 1.8+ the ROM receives the stream argument as an index + # within the array of output streams (and we always use the first + # one by construction). But with 1.5 it's the HDA index, and + # depends on the number of input streams on the device. + stream_idx = hda_ostream_id if cavs15 else 0 + ipcval = ( (1 << 31) # BUSY bit + | (0x01 << 24) # type = PURGE_FW + | (1 << 14) # purge_fw = 1 + | (stream_idx << 9)) # dma_id + log.info(f"Sending PURGW_FW IPC, HIPCR = 0x{ipcval:x}") + dsp.HIPCI = ipcval + + # Now start CPU #0 by dropping stall and reset + log.info(f"Starting {ncores(dsp)} cores, ADSPCS = 0x{dsp.ADSPCS:x}") + dsp.ADSPCS = 0x01fffe # Out of reset + time.sleep(0.1) + dsp.ADSPCS = 0x01fefe # Un-stall + log.info(f"Started {ncores(dsp)} cores, ADSPCS = 0x{dsp.ADSPCS:x}") + + # Experimentation shows that these steps aren't actually required, + # the ROM just charges ahead and initializes itself correctly even + # if we don't wait for it. Do them anyway for better visibility, + # when requested. Potentially remove later once this code is + # mature. + if log.level <= logging.INFO: + # Wait for the ROM to boot and signal it's ready. NOTE: This + # short sleep seems to be needed; if we're banging on the + # memory window during initial boot (before/while the window + # control registers are configured?) the DSP hardware will + # hang fairly reliably. + time.sleep(0.1) + log.info(f"Waiting for ROM init, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}") + while (dsp.SRAM_FW_STATUS >> 24) != 5: pass + log.info(f"ROM ready, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}") + + # Newer devices have an ACK bit we can check + if not cavs15: + log.info(f"Awaiting IPC acknowledgment, HIPCA 0x{dsp.HIPCA:x}") + while not dsp.HIPCA & (1 << 31): pass + dsp.HIPCA |= ~(1 << 31) + + # Wait for it to signal ROM_INIT_DONE + log.info(f"Awaiting ROM init... FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}") + while (dsp.SRAM_FW_STATUS & 0x00ffffff) != 1: pass + + # It's ready, uncork the stream + log.info(f"Starting DMA, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}") + sd.CTL |= HDA_SD_CTL__START + + # The ROM sets a FW_ENTERED value of 5 into the bottom 28 bit + # "state" field of FW_STATUS on entry to the app. (Pedantry: this + # is actually ephemeral and racy, because Zephyr is free to write + # its own data once the app launches and we might miss it. + # There's no standard "alive" signaling from the OS, which is + # really what we want to wait for. So give it one second and move + # on). + log.info(f"Waiting for load, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}") + for _ in range(100): + alive = dsp.SRAM_FW_STATUS & ((1 << 28) - 1) == 5 + if alive: break + time.sleep(0.01) + if alive: + log.info("ROM reports firmware was entered") + else: + log.warning(f"Load failed? FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}") + + # Turn DMA off and reset the stream. If this doesn't happen the + # hardware continues streaming out of our now-stale page and has + # been observed to glitch the next boot. + sd.CTL = 1 + + time.sleep(1) + + log.info(f"ADSPCS = 0x{dsp.ADSPCS:x}") + log.info(f"Load complete, {ncores(dsp)} cores active") + +# Count of active/running cores +def ncores(dsp): + return bin(dsp.ADSPCS >> 24).count("1") + +def map_regs(): + # List cribbed from kernel SOF driver. Not all tested! + for id in ["119a", "5a98", "1a98", "3198", "9dc8", + "a348", "34C8", "38c8", "4dc8", "02c8", + "06c8", "a3f0", "a0c8", "4b55", "4b58"]: + p = runx(f"grep -il PCI_ID=8086:{id} /sys/bus/pci/devices/*/uevent") + if p: + pcidir = os.path.dirname(p) + break + + # Detect hardware version, this matters in a few spots + global cavs15 + cavs15 = id in [ "5a98", "1a98", "3198" ] + log.info(f"Detected cAVS {'1.5' if cavs15 else '1.8+'} hardware") + + # Disengage runtime power management so the kernel doesn't put it to sleep + with open(pcidir + b"/power/control", "w") as ctrl: + ctrl.write("on") + + # Make sure PCI memory space access and busmastering are enabled. + # Also disable interrupts so as not to confuse the kernel. + with open(pcidir + b"/config", "wb+") as cfg: + cfg.seek(4) + cfg.write(b'\x06\x04') + + time.sleep(0.1) + + hdamem = bar_map(pcidir, 0) + + # Standard HD Audio Registers + hda = Regs(hdamem) + hda.GCAP = 0x0000 + hda.GCTL = 0x0008 + hda.SPBFCTL = 0x0704 + hda.PPCTL = 0x0804 + + # Find the ID of the first output stream + global hda_ostream_id + hda_ostream_id = (hda.GCAP >> 8) & 0x0f # number of input streams + log.info(f"Selected output stream {hda_ostream_id} (GCAP = 0x{hda.GCAP:x})") + hda.SD_SPIB = 0x0708 + (8 * hda_ostream_id) + + hda.freeze() + + # Standard HD Audio Stream Descriptor + sd = Regs(hdamem + 0x0080 + (hda_ostream_id * 0x20)) + sd.CTL = 0x00 + sd.LPIB = 0x04 + sd.CBL = 0x08 + sd.LVI = 0x0c + sd.FMT = 0x12 + sd.BDPL = 0x18 + sd.BDPU = 0x1c + sd.freeze() + + # Intel Audio DSP Registers + dsp = Regs(bar_map(pcidir, 4)) + dsp.ADSPCS = 0x00004 + if cavs15: + dsp.HIPCI = 0x00048 # original name of the register... + else: + dsp.HIPCI = 0x000d0 # ...now named "HIPCR" per 1.8+ docs + dsp.HIPCA = 0x000d4 + dsp.SRAM_FW_STATUS = 0x80000 # Start of first SRAM window + dsp.freeze() + + return (hda, sd, dsp) + +def setup_dma_mem(fw_bytes): + (mem, phys_addr) = map_phys_mem() + mem[0:len(fw_bytes)] = fw_bytes + + log.info("Mapped 2M huge page at 0x%x to contain %d bytes of firmware" + % (phys_addr, len(fw_bytes))) + + # HDA requires at least two buffers be defined, but we don't care + # about boundaries because it's all a contiguous region. Place a + # vestigial 128-byte (minimum size and alignment) buffer after the + # main one, and put the 4-entry BDL list into the final 128 bytes + # of the page. + buf0_len = HUGEPAGESZ - 2 * 128 + buf1_len = 128 + bdl_off = buf0_len + buf1_len + mem[bdl_off:bdl_off + 32] = struct.pack(" /proc/sys/vm/nr_hugepages") + + hugef = open(HUGEPAGE_FILE, "w+") + hugef.truncate(HUGEPAGESZ) + mem = mmap.mmap(hugef.fileno(), HUGEPAGESZ) + global_mmaps.append(mem) + os.unlink(HUGEPAGE_FILE) + + # Find the local process address of the mapping, then use that to + # extract the physical address from the kernel's pagemap + # interface. The physical page frame number occupies the bottom + # bits of the entry. + mem[0] = 0 # Fault the page in so it has an address! + vaddr = ctypes.addressof(ctypes.c_int.from_buffer(mem)) + vpagenum = vaddr >> 12 + pagemap = open("/proc/self/pagemap", "rb") + pagemap.seek(vpagenum * 8) + pent = pagemap.read(8) + paddr = (struct.unpack("Q", pent)[0] & ((1 << 54) - 1)) * PAGESZ + pagemap.close() + + return (mem, paddr) + +# Maps a PCI BAR and returns the in-process address +def bar_map(pcidir, barnum): + f = open(pcidir.decode() + "/resource" + str(barnum), "r+") + mm = mmap.mmap(f.fileno(), os.fstat(f.fileno()).st_size) + global_mmaps.append(mm) + return ctypes.addressof(ctypes.c_int.from_buffer(mm)) + +# Syntactic sugar to make register block definition & use look nice. +# Instantiate from a base address, assign offsets to (uint32) named +# registers as fields, call freeze(), then the field acts as a direct +# alias for the register! +class Regs: + def __init__(self, base_addr): + vars(self)["base_addr"] = base_addr + vars(self)["ptrs"] = {} + vars(self)["frozen"] = False + def freeze(self): + vars(self)["frozen"] = True + def __setattr__(self, name, val): + if not self.frozen and name not in self.ptrs: + addr = self.base_addr + val + self.ptrs[name] = ctypes.c_uint32.from_address(addr) + else: + self.ptrs[name].value = val + def __getattr__(self, name): + return self.ptrs[name].value + +def runx(cmd): + return subprocess.Popen(["sh", "-c", cmd], + stdout=subprocess.PIPE).stdout.read() + +if __name__ == "__main__": + main() diff --git a/boards/xtensa/intel_adsp_cavs25/doc/index.rst b/boards/xtensa/intel_adsp_cavs25/doc/index.rst new file mode 100644 index 000000000000..95301c7315e5 --- /dev/null +++ b/boards/xtensa/intel_adsp_cavs25/doc/index.rst @@ -0,0 +1,409 @@ +Zephyr Audio DSP Development on Chromebooks +########################################### + +The Audio DSP on Intel Chromebooks is configured to use the SOF +"Community" key for firmware signing, and can therefore accept +arbitrary user-developed firmware like Zephyr applications (of which +SOF is one), including the Zephyr samples and test suite. + +Initial TGL Chromebook Setup +**************************** + +(These instructions were written specifically to the Asus Flip CX5 +device code named "delbin". But they should be reasonably applicable +to any recent Intel device.) + +Power the device on and connect it to a wireless network. It will +likely want to download a firmware update (mine did). Let this finish +first, to ensure you have two working OS images. + +Enable Developer Mode +===================== + +Power the device off (menu in lower right, or hold the power button +on the side) + +Hold Esc + Refresh (the arrow-in-a-circle "reload" key above "3") and +hit the power key to enter recovery mode. Note: the touchscreen and +pad don't work in recovery mode, use the arrow keys to navigate. + +Select "Advanced Options", then "Enable Developer Mode" and confirm +that you really mean it. Select "Boot from Internal Storage" at the +bootloader screen. You will see this screen every time the machine +boots now, telling you that the boot is unverified. + +Wait while the device does the required data wipe. My device takes +about 15 minutes to completely write the stateful partition. On +reboot, select "Boot from Internal Storage" again and set it up +(again) with Google account. + +Make a Recovery Drive +===================== + +You will at some point wreck your device and need a recovery stick. +Install the Chromebook Recovery Utility from the Google Web Store and +make one. + +You can actually do this on any machine (and any OS) with Chrome +installed, but it's easiest on the Chromebook because it knows its +device ID (for example "DELBIN-XHVI D4B-H4D-G4G-Q9A-A9P" for the Asus +Tiger Lake board). Note that recovery, when it happens, will not +affect developer mode or firmware settings but it **will wipe out the +root filesystem and /usr/local customizations you have made**. So +plan on a strategy that can tolerate data loss on the device you're +messing with! + +Make the root filesystem writable +================================= + +For security, ChromeOS signs and cryptographically verifies (using +Linux's dm-verity feature) all access to the read-only root +filesystem. Mucking with the rootfs (for example, to install modules +for a custom kernel) requires that the dm-verity layer be turned off: + +First open a terminal with Ctrl-Alt-T. Then at the "crosh> " prompt +issue the "shell" command to get a shell running as the "chronos" +user. Finally (in developer mode) a simple "sudo su -" will get you a +root prompt. + +.. code-block:: console + + crosh> shell + chronos@localhost / $ sudo su - + localhost ~ # + +Now you need to turn of signature verification in the bootloader +(because obviously we'll be breaking whatever signature existed). +Note that signature verification is something done by the ROM +bootloader, not the OS, and this setting is a (developer-mode-only) +directive to that code: + +.. code-block:: console + + cros# crossystem dev_boot_signed_only=0 + +(*Note: for clarity, commands in this document entered at the ChromeOS +core shell will be prefixed with a hostname of cros.*) + +Next you disable the validation step: + +.. code-block:: console + + cros# /usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification + +**THIS COMMAND WILL FAIL**, give you an error that you are changing +the setting for the entire running system, and suggest an alternative +"--paritions X" argument to use that modifies only the currently used +partition. Run that modified command, then reboot. + +After rebooting, you will notice that your chromebook boots with the +raw storage device (e.g. /dev/nvme0n1p5) mounted as root and not the +"dm-0" verity device, and that the rootfs is read-write. + +Note: What this command actually does is modify the command line of +the installed kernel image (it saves a backup in +/mnt/stateful_partition/cros_sign_backups) so that it specifies +"root=" and not "root=dm-0". It does seem to leave the other +verity configuration in place though, it just doesn't try to mount the +resulting (now-invalid!) partition. + +Metanote: The astute will note that we're probably going to throw this +kernel out, and that we could probably have just editted the command +line of the new kernel instead of flashing and rebooting into this +modified one. But that's too many balls to juggle at once for me. + +Enable ChromeOS SSH +=================== + +Once you are booted with a writable partition, you can turn on the +built-in ssh server with: + +.. code-block:: console + + cros# /usr/libexec/debugd/helpers/dev_features_ssh + +By default neither the "chronos" user nor root accounts have +passwords, so unless you want to type a ssh key in by hand, you +probably want to set a password for the first login (before you run +ssh-copy-id, of course): + +.. code-block:: console + + cros# passwd + +Now ssh into the chromebook and add your key to +``.ssh/authorized_keys`` as you do for any Linux system. + +Install Crouton +*************** + +The Zephyr integration tools require a proper Linux environment and +won't run on ChromeOS's minimal distro. So we need to install a Linux +personality. **DO NOT** bother installing the "Linux Development +Environment" (Crostini) from the ChromeOS Developer settings. This +personality runs inside a VM, where our tools need access to the real +kernel running on the real hardware. Instead install Crouton +(https://github.com/dnschneid/crouton), which is a community +chroot-based personality that preserves access to the real hardware +sysfs and /dev filesystem. These instructions install the "cli-extra" +package list, there are X11-enabled ones available too if you prefer +to work on the device screen directly. See the project page, etc... + +At a root shell, grab the installer and run it (note: /usr/local is +the only writable filesystem without noexec, you must place the binary +there for it to run!): + +.. code-block:: console + + cros# mkdir -p /usr/local/bin + cros# curl -L https://github.com/dnschneid/crouton/raw/master/installer/crouton \ + > /usr/local/bin/crouton + cros# chmod 755 /usr/local/bin/crouton + cros# crouton -r focal -t cli-extra + +Start the Crouton chroot environment: + +.. code-block:: console + + cros# startcli + +Now you are typing commands into the Ubuntu environment. Enable +inbound ssh on Crouton, but on a port other than 22 (which is used for +the native ChromeOS ssh server). I'm using 222 here (which is easy to +remember, and not a registered port in /etc/services): + +.. code-block:: console + + crouton# apt install iptables openssh-server + crouton# echo "Port 222" >> /etc/ssh/sshd_config + crouton# mkdir /run/sshd + crouton# iptables -I INPUT -p tcp --dport 222 -j ACCEPT + crouton# /usr/sbin/sshd + +(*As above: note that we have introduced a hostname of "crouton" to +refer to the separate Linux personality.*) + +NOTE: the mkdir, iptables and sshd commands need to be run every time +the chroot is restarted. You can put them in /etc/rc.local for +convenience. Crouton doesn't run systemd (because it can't -- it +doesn't own the system!) so Ubuntu services like openssh-server don't +know how to start themselves. + +Building and Installing a Custom Kernel +*************************************** + +On your build host, grab a copy of the ChromeOS kernel tree. The +shipping device is using a 5.4 kernel, but the 5.10 tree works for me +and seems to have been backporting upstream drivers such that its main +hardware is all quite recent (5-6 weeks behind mainline or so). We +place it in the home directory here for simplicity: + +.. code-block:: console + + dev$ cd $HOME + dev$ git clone https://chromium.googlesource.com/chromiumos/third_party/kernel + dev$ cd kernel + dev$ git checkout chromeos-5.10 + +(*Once again, we are typing into a different shell. We introduce the +hostname "dev" here to represent the development machine on which you +are building kernels and Zephyr apps. It is possible to do this on the +chromebook directly, but not advisable. Remember the discussion above +about requiring a drive wipe on system recovery!*) + +Note: you probably have an existing Linux tree somewhere already. If +you do it's much faster to add this as a remote there and just fetch +the deltas -- ChromeOS tracks upstream closely. + +Now you need a .config file. The Chromebook kernel ships with the +"configs" module built which exposes this in the running kernel. You +just have to load the module and read the file. + +.. code-block:: console + + dev$ cd /path/to/kernel + dev$ ssh root@cros modprobe configs + dev$ ssh root@cros zcat /proc/config.gz > .config + +You will need to set some custom configuration variables differently +from ChromeOS defaults (you can edit .config directly, or use +menuconfig, etc...): + ++ ``CONFIG_HUGETLBFS=y`` - The Zephyr loader tool requires this ++ ``CONFIG_EXTRA_FIRMWARE_DIR=n`` - This refers to a build directory + in Google's build environment that we will not have. ++ ``CONFIG_SECURITY_LOADPIN=n`` - Pins modules such that they will + only load from one filesystem. Annoying restriction for custom + kernels. ++ ``CONFIG_MODVERSIONS=n`` - Allow modules to be built and installed + from modified "dirty" build trees. + +Now build your kernel just as you would any other: + +.. code-block:: console + + dev$ make olddefconfig # Or otherwise update .config + dev$ make bzImage modules # Probably want -j for parallel build + +The modules you can copy directly to the (now writable) rootfs on the +device. Note that this filesystem has very limited space (it's +intended to be read only), so the INSTALL_MOD_STRIP=1 is absolutely +required, and you may find you need to regularly prune modules from +older kernels to make space: + +.. code-block:: console + + dev$ make INSTALL_MOD_PATH=mods INSTALL_MOD_STRIP=1 modules_install + dev$ (cd mods/lib/modules; tar cf - .) | ssh root@cros '(cd /lib/modules; tar xfv -)' + +Pack and Install ChromeOS Kernel Image +====================================== + +The kernel bzImage file itself needs to be signed and packaged into a +ChromeOS vboot package and written directly to the kernel partition. +Thankfully the tools to do this are shipped in Debian/Ubuntu +repositories already: + +.. code-block:: console + + $ sudo apt install vboot-utils vboot-kernel-utils + +Find the current kernel partition on the device. You can get this by +comparing the "kernel_guid" command line parameter (passed by the +bootloader) with the partition table of the boot drive, for example: + +.. code-block:: console + + dev$ KPART=`ssh root@cros 'fdisk -l -o UUID,Device /dev/nvme0n1 | \ + grep -i $(sed "s/.*kern_guid=//" /proc/cmdline \ + | sed "s/ .*//") \ + | sed "s/.* //"'` + dev$ echo $KPART + /dev/nvme0n1p4 + +Extract the command line from that image into a local file: + +.. code-block:: console + + dev$ ssh root@cros vbutil_kernel --verify /dev/$KPART | tail -1 > cmdline.txt + +Now you can pack a new kernel image using the vboot tooling. Most of +these arguments are boilerplate and always the same. The keys are +there because the boot requires a valid signature, even though as +configured it won't use it. Note the cannot-actually-be-empty dummy +file passed as a "bootloader", which is a holdover from previous ROM +variants which needed an EFI stub. + +.. code-block:: console + + dev$ echo dummy > dummy.efi + dev$ vbutil_kernel --pack kernel.img --config cmdline.txt \ + --vmlinuz arch/x86_64/boot/bzImage \ + --keyblock /usr/share/vboot/devkeys/kernel.keyblock \ + --signprivate /usr/share/vboot/devkeys/kernel_data_key.vbprivk \ + --version 1 --bootloader dummy.efi --arch x86_64 + +You can verify this image if you like with "vbutil_kernel --verify". + +Now just copy up the file and write it to the partition on the device: + +.. code-block:: console + + $ scp kernel.img root@cros:/tmp + $ ssh root@cros dd if=/tmp/kernel.img of=/dev/nvme0n1p4 + +Now reboot, and if all goes well you will find yourself running in +your new kernel. + +Wifi Firmware Fixup +=================== + +On the Tiger Lake Chromebook, the /lib/firmware tree is a bit stale +relative to the current 5.10 kernel. The iwlwifi driver requests a +firmware file that doesn't exist, leading to a device with no network. +It's a simple problem, but a catastrophic drawback if uncorrected. It +seems to be sufficient just to link the older version to the new name. +(It would probably be better to copy the proper version from +/lib/firmware from a recent kernel.org checkout.): + +.. code-block:: console + + cros# cd /lib/firmware + cros# ln -s iwlwifi-QuZ-a0-hr-b0-62.ucode iwlwifi-QuZ-a0-hr-b0-64.ucode + +Build and Run a Zephyr Application +********************************** + +Finally, with your new kernel booted, you are ready to run Zephyr +code. + +Build rimage Signing Tool +========================= + +First download and build a copy of the Sound Open Firmware "rimage" +tool (these instructions put it in your home directory for clarity, +but anywhere is acceptable): + +.. code-block:: console + + dev$ cd $HOME + dev$ git clone https://github.com/thesofproject/rimage + dev$ cd rimage/ + dev$ git submodule init + dev$ git submodule update + dev$ cmake . + dev$ make + +Copy Integration Scripting to Chromebook +======================================== + +There are two python scripts needed on the device, to be run inside +the Crouton environment installed above. Copy them: + +.. code-block:: console + + dev$ scp boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v25.py root@crouton: + dev$ scp boards/xtensa/intel_adsp_cavs15/tools/adsplog.py root@crouton: + +Build and Sign Zephyr App +========================= + +Zephyr applications build conventionally for this platform, and are +signed with "west flash" with just a few extra arguments. Note that +the key in use for the Tiger Lake DSP is the "3k" key from SOF, not +the original that is used with older hardware. The output artifact is +a "zephyr.ri" file to be copied to the device. + +.. code-block:: console + + dev$ west build -b intel_adsp_cavs25 samples/hello_world + dev$ west sign --tool-data=~/rimage/config -t ~/rimage/rimage -- \ + -k $ZEPHYR_BASE/../modules/audio/sof/keys/otc_private_key_3k.pem + dev$ scp build/zephyr/zephyr.ri root@crouton: + +Run it! +======= + +The loader script takes the signed rimage file as its argument. Once +it reports success, the application begins running immediately and its +console output (in the SOF shared memory trace buffer) can be read by +the logging script. + +.. code-block:: console + + crouton# ./cavs-fw-v25.py zephyr.ri + crouton# ./adsplog.py + Hello World! intel_adsp_cavs25 + +Misc References +*************** + +Upstream documentation from which these instructions were drawn: + +This page has the best reference for the boot process: + +http://www.chromium.org/chromium-os/chromiumos-design-docs/disk-format + +This is great too, with an eye toward booting things other than ChromeOS: + +https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices/custom-firmware diff --git a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig index 016222caa41a..57bd49754938 100644 --- a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig +++ b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig @@ -49,7 +49,8 @@ config ROM_START_OFFSET default 0x100 depends on BOOTLOADER_MCUBOOT -if USB +if USB_DEVICE_STACK + config USB_DW default y @@ -64,9 +65,6 @@ config USB_REQUEST_BUFFER_SIZE default 4096 depends on USB_DFU_CLASS -config USB_DEVICE_STACK - default y - config USB_DEVICE_VID default "0x8087" @@ -79,7 +77,7 @@ config USB_DEVICE_MANUFACTURER config USB_DEVICE_PRODUCT default "Sue Creek (S1000) ASIC" -endif # USB +endif # USB_DEVICE_STACK if SERIAL diff --git a/boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts b/boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts index b647be2f20c4..f84fdee0c385 100644 --- a/boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts +++ b/boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts @@ -107,6 +107,6 @@ }; }; -&usb { +zephyr_udc0: &usb { status = "okay"; }; diff --git a/boards/xtensa/nxp_adsp_imx8/Kconfig.board b/boards/xtensa/nxp_adsp_imx8/Kconfig.board new file mode 100644 index 000000000000..e24c0a453169 --- /dev/null +++ b/boards/xtensa/nxp_adsp_imx8/Kconfig.board @@ -0,0 +1,7 @@ +# Xtensa board configuration + +# Copyright (c) 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NXP_ADSP_IMX8 + bool "NXP ADSP i.MX8" diff --git a/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig new file mode 100644 index 000000000000..225826cebbc7 --- /dev/null +++ b/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2021 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NXP_ADSP_IMX8 + +config BOARD + default "nxp_adsp_imx8" + +config DUMMY_DMA + default y + depends on DMA + +config IMX_EDMA + default y + depends on DMA + + +endif # BOARD_NXP_ADSP_IMX8 diff --git a/boards/xtensa/nxp_adsp_imx8/board.cmake b/boards/xtensa/nxp_adsp_imx8/board.cmake new file mode 100644 index 000000000000..6b01bab2aeea --- /dev/null +++ b/boards/xtensa/nxp_adsp_imx8/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(misc-flasher) +board_finalize_runner_args(misc-flasher) diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts new file mode 100644 index 000000000000..51d3162134af --- /dev/null +++ b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "nxp_adsp_imx8"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + }; +}; diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml new file mode 100644 index 000000000000..f5cfc11cc756 --- /dev/null +++ b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml @@ -0,0 +1,10 @@ +identifier: nxp_adsp_imx8 +name: i.MX8 DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel + - sof diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig new file mode 100644 index 000000000000..e51e01c51fcb --- /dev/null +++ b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=3072 + +CONFIG_SOC_SERIES_NXP_IMX8=y +CONFIG_BOARD_NXP_ADSP_IMX8=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_XTENSA_RESET_VECTOR=y + +CONFIG_XTENSA_USE_CORE_CRT1=y + +CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y + +CONFIG_MULTI_LEVEL_INTERRUPTS=n +CONFIG_2ND_LEVEL_INTERRUPTS=n + +CONFIG_BOOTLOADER_SRAM_SIZE=192 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_CLEANUP_INTERMEDIATE_FILES=y diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa.dts b/boards/xtensa/qemu_xtensa/qemu_xtensa.dts index 83d3572e48e2..4fa67abf2eca 100644 --- a/boards/xtensa/qemu_xtensa/qemu_xtensa.dts +++ b/boards/xtensa/qemu_xtensa/qemu_xtensa.dts @@ -10,7 +10,7 @@ / { model = "qemu_xtensa"; - compatible = "xtensa,sample-controller"; + compatible = "cdns,xtensa-sample-controller"; chosen { zephyr,sram = &sram0; diff --git a/boards/xtensa/xt-sim/xt-sim.dts b/boards/xtensa/xt-sim/xt-sim.dts index e3658565f71b..459cf81daa4d 100644 --- a/boards/xtensa/xt-sim/xt-sim.dts +++ b/boards/xtensa/xt-sim/xt-sim.dts @@ -9,7 +9,7 @@ / { model = "xt-sim"; - compatible = "xtensa,sample-controller"; + compatible = "cdns,xtensa-sample-controller"; chosen { zephyr,sram = &sram0; diff --git a/cmake/app/boilerplate.cmake b/cmake/app/boilerplate.cmake index 7a466c21aa82..96d3fcbf1f8a 100644 --- a/cmake/app/boilerplate.cmake +++ b/cmake/app/boilerplate.cmake @@ -31,11 +31,6 @@ cmake_minimum_required(VERSION 3.20.0) # CMP0002: "Logical target names must be globally unique" cmake_policy(SET CMP0002 NEW) -# Use the old CMake behaviour until the build scripts have been ported -# to the new behaviour. -# CMP0079: "target_link_libraries() allows use with targets in other directories" -cmake_policy(SET CMP0079 OLD) - # Use the old CMake behaviour until we are updating the CMake 3.20 as minimum # required. This ensure that CMake >=3.20 will be consistent with older CMakes. # CMP0116: Ninja generators transform DEPFILE s from add_custom_command(). @@ -470,10 +465,6 @@ elseif(CACHED_CONF_FILE) elseif(DEFINED ENV{CONF_FILE}) set(CONF_FILE $ENV{CONF_FILE}) -elseif(COMMAND set_conf_file) - message(WARNING "'set_conf_file' is deprecated, it will be removed in a future release.") - set_conf_file() - elseif(EXISTS ${APPLICATION_CONFIG_DIR}/prj_${BOARD}.conf) set(CONF_FILE ${APPLICATION_CONFIG_DIR}/prj_${BOARD}.conf) @@ -502,10 +493,7 @@ zephyr_boilerplate_watch(CONF_FILE) if(DTC_OVERLAY_FILE) # DTC_OVERLAY_FILE has either been specified on the cmake CLI or is already - # in the CMakeCache.txt. This has precedence over the environment - # variable DTC_OVERLAY_FILE -elseif(DEFINED ENV{DTC_OVERLAY_FILE}) - set(DTC_OVERLAY_FILE $ENV{DTC_OVERLAY_FILE}) + # in the CMakeCache.txt. elseif(APP_BOARD_DTS) set(DTC_OVERLAY_FILE ${APP_BOARD_DTS}) elseif(EXISTS ${APPLICATION_CONFIG_DIR}/${BOARD}.overlay) @@ -595,6 +583,11 @@ endif() include(${ZEPHYR_BASE}/cmake/target_toolchain.cmake) project(Zephyr-Kernel VERSION ${PROJECT_VERSION}) + +# Add .S file extension suffix into CMAKE_ASM_SOURCE_FILE_EXTENSIONS, +# because clang from OneApi can't recongnize them as asm files on +# windows now. +list(APPEND CMAKE_ASM_SOURCE_FILE_EXTENSIONS "S") enable_language(C CXX ASM) # The setup / configuration of the toolchain itself and the configuration of # supported compilation flags are now split, as this allows to use the toolchain diff --git a/cmake/bintools/armclang/elfconvert_command.cmake b/cmake/bintools/armclang/elfconvert_command.cmake new file mode 100644 index 000000000000..6a5549b96fce --- /dev/null +++ b/cmake/bintools/armclang/elfconvert_command.cmake @@ -0,0 +1,54 @@ +# For armclang the elfconvert command is made into a script. +# Reason for that is because not a single command covers all use cases, +# and it must therefore be possible to call individual commands, depending +# on the arguments used. +cmake_minimum_required(VERSION 3.13) + +# Handle stripping +if (STRIP_DEBUG OR STRIP_ALL) + set(obj_copy_target_output "--elf") + if(STRIP_ALL) + set(obj_copy_strip "--strip=all") + elseif(STRIP_DEBUG) + set(obj_copy_strip "--strip=debug") + endif() +endif() + +# Unknown support of --srec-len in arm-ds + +# Handle Input and Output target types +if(DEFINED OUTTARGET) + if(${OUTTARGET} STREQUAL "srec") + set(obj_copy_target_output "--m32") + elseif(${OUTTARGET} STREQUAL "ihex") + set(obj_copy_target_output "--i32combined") + elseif(${OUTTARGET} STREQUAL "binary") + set(obj_copy_target_output "--bincombined") + if(GAP_FILL) + set(obj_copy_gap_fill "--bincombined_padding=1,${GAP_FILL}") + endif() + endif() +endif() + +if(DEFINED ONLY_SECTION AND "${OUTTARGET}" STREQUAL "binary") + set(obj_copy_target_output "--bin") + set(outfile_dir .dir) + string(REGEX REPLACE "^[\.]" "" only_section_clean "${ONLY_SECTION}") +endif() + +# Note: fromelf is a little special regarding bin output, as each section gets +# its own file. This means that when only a specific section is required +# then that section must be moved to correct location. +execute_process( + COMMAND ${FROMELF} + ${obj_copy_strip} + ${obj_copy_gap_fill} ${obj_copy_target_output} + --output ${OUTFILE}${outfile_dir} ${INFILE} +) + +if(DEFINED ONLY_SECTION AND "${OUTTARGET}" STREQUAL "binary") + execute_process( + COMMAND ${CMAKE_COMMAND} -E copy + ${OUTFILE}${outfile_dir}/${only_section_clean} ${OUTFILE} + ) +endif() diff --git a/cmake/bintools/armclang/target.cmake b/cmake/bintools/armclang/target.cmake new file mode 100644 index 000000000000..529028f73672 --- /dev/null +++ b/cmake/bintools/armclang/target.cmake @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Configures binary tools as mwdt binutils + +find_program(CMAKE_FROMELF fromelf PATH ${TOOLCHAIN_HOME}/bin NO_DEFAULT_PATH) +find_program(CMAKE_AS armasm PATH ${TOOLCHAIN_HOME}/bin NO_DEFAULT_PATH) +find_program(CMAKE_AR armar PATH ${TOOLCHAIN_HOME}/bin NO_DEFAULT_PATH) + +SET(CMAKE_CXX_ARCHIVE_CREATE " -rq ") +SET(CMAKE_C_ARCHIVE_CREATE " -rq ") +SET(CMAKE_CXX_ARCHIVE_FINISH " -sq ") +SET(CMAKE_C_ARCHIVE_FINISH " -sq ") + +find_program(CMAKE_GDB ${CROSS_COMPILE}mdb PATH ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) + +include(${CMAKE_CURRENT_LIST_DIR}/target_bintools.cmake) diff --git a/cmake/bintools/armclang/target_bintools.cmake b/cmake/bintools/armclang/target_bintools.cmake new file mode 100644 index 000000000000..677d702c636e --- /dev/null +++ b/cmake/bintools/armclang/target_bintools.cmake @@ -0,0 +1,71 @@ +# List of format the tool supports for converting, for example, +# GNU tools uses objectcopyy, which supports the following: ihex, srec, binary +set_property(TARGET bintools PROPERTY elfconvert_formats ihex binary) + +# armclang toolchain does not support all options in a single command +# Therefore a CMake script is used, so that multiple commands can be executed +# successively. +set_property(TARGET bintools PROPERTY elfconvert_command ${CMAKE_COMMAND}) + +set_property(TARGET bintools PROPERTY elfconvert_flag + -DFROMELF=${CMAKE_FROMELF} +) + +set_property(TARGET bintools PROPERTY elfconvert_flag_final + -P ${CMAKE_CURRENT_LIST_DIR}/elfconvert_command.cmake) + +set_property(TARGET bintools PROPERTY elfconvert_flag_strip_all "-DSTRIP_ALL=True") +set_property(TARGET bintools PROPERTY elfconvert_flag_strip_debug "-DSTRIP_DEBUG=True") + +set_property(TARGET bintools PROPERTY elfconvert_flag_intarget "-DINTARGET=") +set_property(TARGET bintools PROPERTY elfconvert_flag_outtarget "-DOUTTARGET=") + +set_property(TARGET bintools PROPERTY elfconvert_flag_section_remove "-DREMOVE_SECTION=") +set_property(TARGET bintools PROPERTY elfconvert_flag_section_only "-DONLY_SECTION=") + +# mwdt doesn't handle rename, consider adjusting abstraction. +set_property(TARGET bintools PROPERTY elfconvert_flag_section_rename "-DRENAME_SECTION=") + +set_property(TARGET bintools PROPERTY elfconvert_flag_gapfill "-DGAP_FILL=") +set_property(TARGET bintools PROPERTY elfconvert_flag_srec_len "-DSREC_LEN=") + +set_property(TARGET bintools PROPERTY elfconvert_flag_infile "-DINFILE=") +set_property(TARGET bintools PROPERTY elfconvert_flag_outfile "-DOUTFILE=") + +# +# - disassembly : Name of command for disassembly of files +# In this implementation `fromelf` is used +# disassembly_flag : --disassemble +# disassembly_flag_final : empty +# disassembly_flag_inline_source : --interleave=source +# disassembly_flag_all : empty, fromelf does not differentiate on this. +# disassembly_flag_infile : empty, fromelf doesn't take arguments for filenames +# disassembly_flag_outfile : --output + +set_property(TARGET bintools PROPERTY disassembly_command ${CMAKE_FROMELF}) +set_property(TARGET bintools PROPERTY disassembly_flag --disassemble) +set_property(TARGET bintools PROPERTY disassembly_flag_final "") +set_property(TARGET bintools PROPERTY disassembly_flag_inline_source --interleave=source) +set_property(TARGET bintools PROPERTY disassembly_flag_all "") + +set_property(TARGET bintools PROPERTY disassembly_flag_infile "") +set_property(TARGET bintools PROPERTY disassembly_flag_outfile "--output=" ) + +# +# - readelf : Name of command for reading elf files. +# In this implementation `fromelf` is used +# readelf_flag : empty +# readelf_flag_final : empty +# readelf_flag_headers : --text +# readelf_flag_infile : empty, fromelf doesn't take arguments for filenames +# readelf_flag_outfile : --output + +# This is using fromelf from arm-ds / Keil. +set_property(TARGET bintools PROPERTY readelf_command ${CMAKE_FROMELF}) + +set_property(TARGET bintools PROPERTY readelf_flag "") +set_property(TARGET bintools PROPERTY readelf_flag_final "") +set_property(TARGET bintools PROPERTY readelf_flag_headers --text) + +set_property(TARGET bintools PROPERTY readelf_flag_infile "") +set_property(TARGET bintools PROPERTY readelf_flag_outfile "--output=") diff --git a/cmake/bintools/gnu/target.cmake b/cmake/bintools/gnu/target.cmake index 65b63c507ea8..bef546c82c4a 100644 --- a/cmake/bintools/gnu/target.cmake +++ b/cmake/bintools/gnu/target.cmake @@ -12,6 +12,23 @@ find_program(CMAKE_NM ${CROSS_COMPILE}nm PATHS ${TOOLCHAIN_HOME} NO_DE find_program(CMAKE_STRIP ${CROSS_COMPILE}strip PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) find_program(CMAKE_GDB ${CROSS_COMPILE}gdb PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) + +if(CMAKE_GDB) + execute_process( + COMMAND ${CMAKE_GDB} --configuration + OUTPUT_VARIABLE GDB_PY_NO_PY + OUTPUT_STRIP_TRAILING_WHITESPACE + RESULTS_VARIABLE GDB_CFG_ERR + ) + if (${GDB_CFG_ERR}) + # Failed to execute GDB, likely because of Python deps + find_program(CMAKE_GDB_NO_PY ${CROSS_COMPILE}gdb-no-py PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) + if (CMAKE_GDB_NO_PY) + set(CMAKE_GDB ${CMAKE_GDB_NO_PY} CACHE FILEPATH "Path to a program." FORCE) + endif() + endif() +endif() + find_program(CMAKE_GDB gdb-multiarch PATHS ${TOOLCHAIN_HOME} ) # Include bin tool properties diff --git a/cmake/bintools/oneApi/target.cmake b/cmake/bintools/oneApi/target.cmake index 3abe5e813e03..4b69900f0686 100644 --- a/cmake/bintools/oneApi/target.cmake +++ b/cmake/bintools/oneApi/target.cmake @@ -7,7 +7,10 @@ endif() find_program(CMAKE_AR llvm-ar ${find_program_clang_args} ) find_program(CMAKE_NM llvm-nm ${find_program_clang_args} ) -find_program(CMAKE_OBJDUMP llvm-objdump ${find_program_clang_args} ) +# In OneApi installation directory on Windows, there is no llvm-objdump +# binary, so would better use objdump from system environment both +# on Linux and Windows. +find_program(CMAKE_OBJDUMP objdump ${find_program_binutils_args}) find_program(CMAKE_RANLIB llvm-ranlib ${find_program_clang_args} ) find_program(CMAKE_OBJCOPY llvm-objcopy ${find_program_binutils_args}) find_program(CMAKE_READELF readelf ${find_program_binutils_args}) diff --git a/cmake/compiler/arcmwdt/compiler_flags.cmake b/cmake/compiler/arcmwdt/compiler_flags.cmake index 8d736ba203f2..00e2233bff33 100644 --- a/cmake/compiler/arcmwdt/compiler_flags.cmake +++ b/cmake/compiler/arcmwdt/compiler_flags.cmake @@ -115,20 +115,19 @@ set_compiler_property(PROPERTY warning_error_misra_sane -Werror=vla) set_compiler_property(PROPERTY cstd -std=) -if (NOT CONFIG_NEWLIB_LIBC AND - NOT CONFIG_NATIVE_APPLICATION) +if (NOT CONFIG_ARCMWDT_LIBC) set_compiler_property(PROPERTY nostdinc -Hno_default_include -Hnoarcexlib) - set_compiler_property(APPEND PROPERTY nostdinc_include ${NOSTDINC}) endif() +set_compiler_property(APPEND PROPERTY nostdinc_include ${NOSTDINC}) # C++ std options set_property(TARGET compiler-cpp PROPERTY dialect_cpp98 "-std=c++98") set_property(TARGET compiler-cpp PROPERTY dialect_cpp11 "-std=c++11") +set_property(TARGET compiler-cpp PROPERTY dialect_cpp14 "-std=c++14") +set_property(TARGET compiler-cpp PROPERTY dialect_cpp17 "-std=c++17") -#no support of C++14, C++17, C++2a, C++20, C++2b -set_property(TARGET compiler-cpp PROPERTY dialect_cpp14 "") -set_property(TARGET compiler-cpp PROPERTY dialect_cpp17 "") +#no support of C++2a, C++20, C++2b set_property(TARGET compiler-cpp PROPERTY dialect_cpp2a "") set_property(TARGET compiler-cpp PROPERTY dialect_cpp20 "") set_property(TARGET compiler-cpp PROPERTY dialect_cpp2b "") @@ -173,7 +172,7 @@ set_compiler_property(PROPERTY security_canaries -fstack-protector-all) set_compiler_property(PROPERTY security_fortify "") # Required C++ flags when using mwdt -set_property(TARGET compiler-cpp PROPERTY required "") +set_property(TARGET compiler-cpp PROPERTY required "-Hcplus" "-Hoff=Stackcheck_alloca") # Compiler flag for turning off thread-safe initialization of local statics set_property(TARGET compiler-cpp PROPERTY no_threadsafe_statics "-fno-threadsafe-statics") diff --git a/cmake/compiler/arcmwdt/generic.cmake b/cmake/compiler/arcmwdt/generic.cmake index ceda135f257b..d062c962684a 100644 --- a/cmake/compiler/arcmwdt/generic.cmake +++ b/cmake/compiler/arcmwdt/generic.cmake @@ -19,6 +19,8 @@ if(NOT CMAKE_DTS_PREPROCESSOR) endif() find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}ccac PATH ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) +find_program(CMAKE_LLVM_COV ${CROSS_COMPILE}llvm-cov PATH ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) +set(CMAKE_GCOV "${CMAKE_LLVM_COV} gcov") if(CMAKE_C_COMPILER STREQUAL CMAKE_C_COMPILER-NOTFOUND) message(FATAL_ERROR "Zephyr was unable to find the Metaware compiler") diff --git a/cmake/compiler/arcmwdt/target.cmake b/cmake/compiler/arcmwdt/target.cmake index 8c6def51e16d..9bed7a511945 100644 --- a/cmake/compiler/arcmwdt/target.cmake +++ b/cmake/compiler/arcmwdt/target.cmake @@ -26,6 +26,10 @@ set(NOSTDINC "") list(APPEND NOSTDINC ${TOOLCHAIN_HOME}/arc/inc) +if(CONFIG_ARCMWDT_LIBC AND CONFIG_LIB_CPLUSPLUS) + list(APPEND NOSTDINC ${TOOLCHAIN_HOME}/arc/lib/src/c++/inc) +endif() + # For CMake to be able to test if a compiler flag is supported by the # toolchain we need to give CMake the necessary flags to compile and # link a dummy C file. @@ -39,3 +43,11 @@ endforeach() # common compile options, no copyright msg, little-endian, no small data, # no MWDT stack checking list(APPEND TOOLCHAIN_C_FLAGS -Hnocopyr -HL -Hnosdata -Hoff=Stackcheck_alloca) + +# The MWDT compiler can replace some code with call to builtin functions. +# We can't rely on these functions presence if we don't use MWDT libc. +# NOTE: the option name '-fno-builtin' is misleading a bit - we still can +# manually call __builtin_** functions even if we specify it. +if(NOT CONFIG_ARCMWDT_LIBC) + list(APPEND TOOLCHAIN_C_FLAGS -fno-builtin) +endif() diff --git a/cmake/compiler/armclang/compiler_flags.cmake b/cmake/compiler/armclang/compiler_flags.cmake new file mode 100644 index 000000000000..3d0f713da4f4 --- /dev/null +++ b/cmake/compiler/armclang/compiler_flags.cmake @@ -0,0 +1,9 @@ +# First step is to inherit all properties from gcc, as clang is compatible with most flags. +include(${ZEPHYR_BASE}/cmake/compiler/clang/compiler_flags.cmake) + +# Required ASM flags when using armclang, this should be handled by CMake, but +# fails because of: https://gitlab.kitware.com/cmake/cmake/-/issues/19963 +set_property(TARGET asm APPEND PROPERTY required "--target=${triple}") + +# Only the ARM Compiler C library is currently supported. +set_compiler_property(PROPERTY nostdinc) diff --git a/cmake/compiler/armclang/generic.cmake b/cmake/compiler/armclang/generic.cmake new file mode 100644 index 000000000000..44d34ddcdbe5 --- /dev/null +++ b/cmake/compiler/armclang/generic.cmake @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Configures CMake for using ccac + +find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}armclang PATH ${TOOLCHAIN_HOME}/bin NO_DEFAULT_PATH) + +set(triple arm-arm-none-eabi) + +set(CMAKE_DTS_PREPROCESSOR + ${CMAKE_C_COMPILER} + "--target=${triple}" + # -march=armv6-m is added to silence the warnings: + # 'armv4t' and 'arm7tdmi' is unsupported. + # We only do preprocessing so the actual arch is not important. + "-march=armv6-m" +) + +set(CMAKE_C_COMPILER_TARGET ${triple}) +set(CMAKE_ASM_COMPILER_TARGET ${triple}) +set(CMAKE_CXX_COMPILER_TARGET ${triple}) + +if(CMAKE_C_COMPILER STREQUAL CMAKE_C_COMPILER-NOTFOUND) + message(FATAL_ERROR "Zephyr was unable to find the armclang compiler") +endif() + +execute_process( + COMMAND ${CMAKE_C_COMPILER} --version + RESULT_VARIABLE ret + OUTPUT_QUIET + ERROR_QUIET + ) + +if(ret) + message(FATAL_ERROR "Executing the below command failed. " + "Are permissions set correctly? '${CMAKE_C_COMPILER} --version' " + "And is the license setup correctly ?" + ) +endif() diff --git a/cmake/compiler/armclang/target.cmake b/cmake/compiler/armclang/target.cmake new file mode 100644 index 000000000000..c84089fa1ae7 --- /dev/null +++ b/cmake/compiler/armclang/target.cmake @@ -0,0 +1,77 @@ +# find the compilers for C, CPP, assembly +find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}armclang PATH ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) +find_program(CMAKE_CXX_COMPILER ${CROSS_COMPILE}armclang PATH ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) +find_program(CMAKE_ASM_COMPILER ${CROSS_COMPILE}armclang PATH ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) + +# The CMAKE_REQUIRED_FLAGS variable is used by check_c_compiler_flag() +# (and other commands which end up calling check_c_source_compiles()) +# to add additional compiler flags used during checking. These flags +# are unused during "real" builds of Zephyr source files linked into +# the final executable. +# +include(${ZEPHYR_BASE}/cmake/gcc-m-cpu.cmake) +set(CMAKE_SYSTEM_PROCESSOR ${GCC_M_CPU}) + +list(APPEND TOOLCHAIN_C_FLAGS + -fshort-enums + ) + +if(CONFIG_ARM64) + list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_M_CPU}) + + list(APPEND TOOLCHAIN_C_FLAGS -mabi=lp64) + list(APPEND TOOLCHAIN_LD_FLAGS -mabi=lp64) +else() + list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_M_CPU}) + + if(CONFIG_COMPILER_ISA_THUMB2) + list(APPEND TOOLCHAIN_C_FLAGS -mthumb) + endif() + + list(APPEND TOOLCHAIN_C_FLAGS -mabi=aapcs) + + # Defines a mapping from GCC_M_CPU to FPU + + if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION) + set(PRECISION_TOKEN) + else() + set(PRECISION_TOKEN sp-) + endif() + + set(FPU_FOR_cortex-m4 fpv4-${PRECISION_TOKEN}d16) + set(FPU_FOR_cortex-m7 fpv5-${PRECISION_TOKEN}d16) + set(FPU_FOR_cortex-m33 fpv5-${PRECISION_TOKEN}d16) + + if(CONFIG_FPU) + list(APPEND TOOLCHAIN_C_FLAGS -mfpu=${FPU_FOR_${GCC_M_CPU}}) + if (CONFIG_FP_SOFTABI) + list(APPEND TOOLCHAIN_C_FLAGS -mfloat-abi=softfp) + elseif(CONFIG_FP_HARDABI) + list(APPEND TOOLCHAIN_C_FLAGS -mfloat-abi=hard) + endif() + endif() +endif() + +foreach(file_name include/stddef.h) + execute_process( + COMMAND ${CMAKE_C_COMPILER} --print-file-name=${file_name} + OUTPUT_VARIABLE _OUTPUT + ) + get_filename_component(_OUTPUT "${_OUTPUT}" DIRECTORY) + string(REGEX REPLACE "\n" "" _OUTPUT ${_OUTPUT}) + + list(APPEND NOSTDINC ${_OUTPUT}) +endforeach() + +foreach(isystem_include_dir ${NOSTDINC}) + list(APPEND isystem_include_flags -isystem ${isystem_include_dir}) +endforeach() + +set(CMAKE_REQUIRED_FLAGS ${isystem_include_flags}) +string(REPLACE ";" " " CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS}") + +if(CONFIG_ARMCLANG_STD_LIBC) + # Zephyr requires AEABI portability to ensure correct functioning of the C + # library, for example error numbers, errno.h. + list(APPEND TOOLCHAIN_C_FLAGS -D_AEABI_PORTABILITY_LEVEL=1) +endif() diff --git a/cmake/compiler/clang/generic.cmake b/cmake/compiler/clang/generic.cmake index 7033a9581229..869a788e2449 100644 --- a/cmake/compiler/clang/generic.cmake +++ b/cmake/compiler/clang/generic.cmake @@ -5,4 +5,6 @@ if(DEFINED TOOLCHAIN_HOME) endif() find_program(CMAKE_C_COMPILER clang ${find_program_clang_args}) +find_program(CMAKE_LLVM_COV llvm-cov ${find_program_clang_args}) +set(CMAKE_GCOV "${CMAKE_LLVM_COV} gcov") diff --git a/cmake/compiler/clang/target.cmake b/cmake/compiler/clang/target.cmake index c8488fc3ca76..fe98499b2f8b 100644 --- a/cmake/compiler/clang/target.cmake +++ b/cmake/compiler/clang/target.cmake @@ -69,7 +69,7 @@ if(NOT "${ARCH}" STREQUAL "posix") list(APPEND TOOLCHAIN_LIBS gcc) endif() - set(CMAKE_REQUIRED_FLAGS -nostartfiles -nostdlib ${isystem_include_flags}) + list(APPEND CMAKE_REQUIRED_FLAGS -nostartfiles -nostdlib ${isystem_include_flags}) string(REPLACE ";" " " CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS}") endif() diff --git a/cmake/compiler/compiler_flags_template.cmake b/cmake/compiler/compiler_flags_template.cmake index 9d609a7acdb5..4900a7594653 100644 --- a/cmake/compiler/compiler_flags_template.cmake +++ b/cmake/compiler/compiler_flags_template.cmake @@ -50,6 +50,9 @@ set_compiler_property(PROPERTY cstd) set_compiler_property(PROPERTY nostdinc) set_compiler_property(PROPERTY nostdinc_include) +# Compiler flags for disabling C++ standard include. +set_compiler_property(TARGET compiler-cpp PROPERTY nostdincxx) + # Required C++ flags when compiling C++ code set_property(TARGET compiler-cpp PROPERTY required) diff --git a/cmake/compiler/gcc/compiler_flags.cmake b/cmake/compiler/gcc/compiler_flags.cmake index 4e8883992dee..a2f3020b8a14 100644 --- a/cmake/compiler/gcc/compiler_flags.cmake +++ b/cmake/compiler/gcc/compiler_flags.cmake @@ -120,6 +120,8 @@ if (NOT CONFIG_NEWLIB_LIBC AND set_compiler_property(APPEND PROPERTY nostdinc_include ${NOSTDINC}) endif() +set_compiler_property(TARGET compiler-cpp PROPERTY nostdincxx "-nostdinc++") + # Required C++ flags when using gcc set_property(TARGET compiler-cpp PROPERTY required "-fcheck-new") diff --git a/cmake/compiler/gcc/generic.cmake b/cmake/compiler/gcc/generic.cmake index 57b32f633b04..ca96eb93809c 100644 --- a/cmake/compiler/gcc/generic.cmake +++ b/cmake/compiler/gcc/generic.cmake @@ -3,6 +3,7 @@ set_ifndef(CC gcc) find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}${CC} PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) +find_program(CMAKE_GCOV ${CROSS_COMPILE}gcov PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) if(CMAKE_C_COMPILER STREQUAL CMAKE_C_COMPILER-NOTFOUND) message(FATAL_ERROR "Zephyr was unable to find the toolchain. Is the environment misconfigured? diff --git a/cmake/compiler/gcc/target_arm.cmake b/cmake/compiler/gcc/target_arm.cmake index 1b362f5872d3..36b0513458af 100644 --- a/cmake/compiler/gcc/target_arm.cmake +++ b/cmake/compiler/gcc/target_arm.cmake @@ -18,10 +18,14 @@ else() set(PRECISION_TOKEN sp-) endif() -set(FPU_FOR_cortex-m4 fpv4-${PRECISION_TOKEN}d16) -set(FPU_FOR_cortex-m7 fpv5-${PRECISION_TOKEN}d16) -set(FPU_FOR_cortex-m33 fpv5-${PRECISION_TOKEN}d16) -set(FPU_FOR_cortex-m33+nodsp fpv5-${PRECISION_TOKEN}d16) +set(FPU_FOR_cortex-m4 fpv4-${PRECISION_TOKEN}d16) +set(FPU_FOR_cortex-m7 fpv5-${PRECISION_TOKEN}d16) +set(FPU_FOR_cortex-m33 fpv5-${PRECISION_TOKEN}d16) +set(FPU_FOR_cortex-m33+nodsp fpv5-${PRECISION_TOKEN}d16) +set(FPU_FOR_cortex-m55 auto) +set(FPU_FOR_cortex-m55+nomve.fp auto) +set(FPU_FOR_cortex-m55+nomve auto) +set(FPU_FOR_cortex-m55+nodsp auto) if(CONFIG_FPU) list(APPEND TOOLCHAIN_C_FLAGS -mfpu=${FPU_FOR_${GCC_M_CPU}}) @@ -34,3 +38,13 @@ if(CONFIG_FPU) list(APPEND TOOLCHAIN_LD_FLAGS -mfloat-abi=hard) endif() endif() + +if(CONFIG_FP16) + if (CONFIG_FP16_IEEE) + list(APPEND TOOLCHAIN_C_FLAGS -mfp16-format=ieee) + list(APPEND TOOLCHAIN_LD_FLAGS -mfp16-format=ieee) + elseif(CONFIG_FP16_ALT) + list(APPEND TOOLCHAIN_C_FLAGS -mfp16-format=alternative) + list(APPEND TOOLCHAIN_LD_FLAGS -mfp16-format=alternative) + endif() +endif() diff --git a/cmake/compiler/host-gcc/generic.cmake b/cmake/compiler/host-gcc/generic.cmake index 3f889564ca9f..e7fbf17c7308 100644 --- a/cmake/compiler/host-gcc/generic.cmake +++ b/cmake/compiler/host-gcc/generic.cmake @@ -3,3 +3,4 @@ # Configures CMake for using GCC find_program(CMAKE_C_COMPILER gcc) +find_program(CMAKE_GCOV gcov) diff --git a/cmake/compiler/xcc/compiler_flags.cmake b/cmake/compiler/xcc/compiler_flags.cmake index b089f3c7b932..a6205bbf546b 100644 --- a/cmake/compiler/xcc/compiler_flags.cmake +++ b/cmake/compiler/xcc/compiler_flags.cmake @@ -4,4 +4,10 @@ if(CC STREQUAL "clang") include(${ZEPHYR_BASE}/cmake/compiler/clang/compiler_flags.cmake) else() include(${ZEPHYR_BASE}/cmake/compiler/gcc/compiler_flags.cmake) + + # XCC is based on GCC 4.2 which has a somewhat pedantic take on the + # fact that linkage semantics differed between C99 and GNU at the + # time. Suppress the warning, it's the best we can do given that + # it's a legacy compiler. + set_compiler_property(APPEND PROPERTY warning_base "-fgnu89-inline") endif() diff --git a/cmake/compiler/xcc/generic.cmake b/cmake/compiler/xcc/generic.cmake index 57b32f633b04..ca96eb93809c 100644 --- a/cmake/compiler/xcc/generic.cmake +++ b/cmake/compiler/xcc/generic.cmake @@ -3,6 +3,7 @@ set_ifndef(CC gcc) find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}${CC} PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) +find_program(CMAKE_GCOV ${CROSS_COMPILE}gcov PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH) if(CMAKE_C_COMPILER STREQUAL CMAKE_C_COMPILER-NOTFOUND) message(FATAL_ERROR "Zephyr was unable to find the toolchain. Is the environment misconfigured? diff --git a/cmake/dts.cmake b/cmake/dts.cmake index 83c89f8fe1d8..673ce6f85172 100644 --- a/cmake/dts.cmake +++ b/cmake/dts.cmake @@ -23,6 +23,9 @@ set(EDT_PICKLE ${PROJECT_BINARY_DIR}/edt.pickle) set(DEVICETREE_UNFIXED_H ${PROJECT_BINARY_DIR}/include/generated/devicetree_unfixed.h) set(DEVICE_EXTERN_H ${PROJECT_BINARY_DIR}/include/generated/device_extern.h) set(DTS_POST_CPP ${PROJECT_BINARY_DIR}/${BOARD}.dts.pre.tmp) +# The location of a list of known vendor prefixes. +# This is relative to each element of DTS_ROOT. +set(VENDOR_PREFIXES dts/bindings/vendor-prefixes.txt) # Devicetree in CMake. set(DTS_CMAKE_SCRIPT ${ZEPHYR_BASE}/scripts/dts/gen_dts_cmake.py) @@ -92,6 +95,7 @@ if(SUPPORTS_DTS) endforeach() unset(DTS_ROOT_SYSTEM_INCLUDE_DIRS) + unset(DTS_ROOT_BINDINGS) foreach(dts_root ${DTS_ROOT}) foreach(dts_root_path include @@ -107,17 +111,19 @@ if(SUPPORTS_DTS) ) endif() endforeach() - endforeach() - unset(DTS_ROOT_BINDINGS) - foreach(dts_root ${DTS_ROOT}) - set(full_path ${dts_root}/dts/bindings) - if(EXISTS ${full_path}) + set(bindings_path ${dts_root}/dts/bindings) + if(EXISTS ${bindings_path}) list(APPEND DTS_ROOT_BINDINGS - ${full_path} + ${bindings_path} ) endif() + + set(vendor_prefixes ${dts_root}/${VENDOR_PREFIXES}) + if(EXISTS ${vendor_prefixes}) + list(APPEND EXTRA_GEN_DEFINES_ARGS --vendor-prefixes ${vendor_prefixes}) + endif() endforeach() # Cache the location of the root bindings so they can be used by diff --git a/cmake/emu/armfvp.cmake b/cmake/emu/armfvp.cmake index afebd8ea3ff9..8db5db81ab99 100644 --- a/cmake/emu/armfvp.cmake +++ b/cmake/emu/armfvp.cmake @@ -10,11 +10,36 @@ find_program( NAMES ${ARMFVP_BIN_NAME} ) +if(CONFIG_ARMV8_A_NS) + foreach(filetype BL1 FIP) + if ((NOT DEFINED ARMFVP_${filetype}_FILE) AND (EXISTS "$ENV{ARMFVP_${filetype}_FILE}")) + set(ARMFVP_${filetype}_FILE "$ENV{ARMFVP_${filetype}_FILE}" CACHE FILEPATH + "ARM FVP ${filetype} File specified in environment" + ) + endif() + + if(NOT EXISTS "${ARMFVP_${filetype}_FILE}") + string(TOLOWER ${filetype} filename) + message(FATAL_ERROR "Please specify ARMFVP_${filetype}_FILE in environment " + "or with -DARMFVP_${filetype}_FILE=") + endif() + endforeach() + + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} + -C bp.secureflashloader.fname=${ARMFVP_BL1_FILE} + -C bp.flashloader0.fname=${ARMFVP_FIP_FILE} + --data cluster0.cpu0="${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_BIN_NAME}"@0x88000000 + ) +else() + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} + -a ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) +endif() + add_custom_target(run COMMAND ${ARMFVP} ${ARMFVP_FLAGS} - -a ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} DEPENDS ${ARMFVP} ${logical_target_for_zephyr_elf} WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} COMMENT "FVP: ${ARMFVP}" diff --git a/cmake/emu/nsim.cmake b/cmake/emu/nsim.cmake index 9126627481bf..c64c5cff8a9a 100644 --- a/cmake/emu/nsim.cmake +++ b/cmake/emu/nsim.cmake @@ -1,44 +1,54 @@ # SPDX-License-Identifier: Apache-2.0 -if(${CONFIG_SOC_NSIM_HS_SMP}) +if("${BOARD_DEBUG_RUNNER}" STREQUAL "mdb-nsim" OR "${BOARD_FLASH_RUNNER}" STREQUAL "mdb-nsim") # mdb is required to run nsim multicore targets find_program( MDB mdb ) +set(MDB_BASIC_OPTIONS -nooptions -nogoifmain -toggle=include_local_symbols=1) -if(${CONFIG_SOC_NSIM_HS_SMP}) - set(MDB_ARGS mdb_hs_smp.args) +# remove previous .sc.project folder which has temporary settings for MDB. +set(MDB_OPTIONS ${CMAKE_COMMAND} -E rm -rf ${APPLICATION_BINARY_DIR}/.sc.project) +if(CONFIG_MP_NUM_CPUS GREATER 1) + set(MULTIFILES ${MDB} -multifiles=) + foreach(val RANGE ${CONFIG_MP_NUM_CPUS}) + if(val LESS CONFIG_MP_NUM_CPUS) + MATH(EXPR PSET_NUM "${CONFIG_MP_NUM_CPUS}-${val}") + MATH(EXPR CORE_NUM "${CONFIG_MP_NUM_CPUS}-${val}-1") + if(PSET_NUM GREATER 0) + list(APPEND MDB_OPTIONS &&) + endif() + list(APPEND MDB_OPTIONS ${MDB} -pset=${PSET_NUM} -psetname=core${CORE_NUM}) + if(PSET_NUM GREATER 1) + list(APPEND MDB_OPTIONS -prop=download=2) + set(MULTIFILES ${MULTIFILES}core${CORE_NUM},) + else() + set(MULTIFILES ${MULTIFILES}core${CORE_NUM}) + endif() + list(APPEND MDB_OPTIONS ${MDB_BASIC_OPTIONS} -nsim @${BOARD_DIR}/support/${MDB_ARGS} ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}) + endif() + endforeach() + list(APPEND MDB_OPTIONS && NSIM_MULTICORE=1 ${MULTIFILES} -run -cl) +else() + list(APPEND MDB_OPTIONS && ${MDB} ${MDB_BASIC_OPTIONS} -nsim @${BOARD_DIR}/support/${MDB_ARGS} -run -cl) endif() +string(REPLACE ";" " " MDB_COMMAND "${MDB_OPTIONS}") add_custom_target(run COMMAND - ${MDB} -pset=1 -psetname=core0 -prop=ident=0x00000050 -cmpd=soc - @${BOARD_DIR}/support/${MDB_ARGS} ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} && - ${MDB} -pset=2 -psetname=core1 -prop=download=2 -prop=ident=0x00000150 -cmpd=soc - @${BOARD_DIR}/support/${MDB_ARGS} ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} && - NSIM_MULTICORE=1 ${MDB} -multifiles=core0,core1 -cmpd=soc -run -cl + ${MDB_OPTIONS} + ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} DEPENDS ${logical_target_for_zephyr_elf} WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} + COMMENT "MDB COMMAND: ${MDB_COMMAND} ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}" USES_TERMINAL - ) +) else() find_program( NSIM nsimdrv ) -if(${CONFIG_SOC_NSIM_EM}) - set(NSIM_PROPS nsim_em.props) -elseif(${CONFIG_SOC_NSIM_EM7D_V22}) - set(NSIM_PROPS nsim_em7d_v22.props) -elseif(${CONFIG_SOC_NSIM_SEM}) - set(NSIM_PROPS nsim_sem.props) -elseif(${CONFIG_SOC_NSIM_HS}) - set(NSIM_PROPS nsim_hs.props) -elseif(${CONFIG_SOC_NSIM_HS6X}) - set(NSIM_PROPS nsim_hs6x.props) -endif() - add_custom_target(run COMMAND ${NSIM} @@ -47,6 +57,7 @@ add_custom_target(run ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} DEPENDS ${logical_target_for_zephyr_elf} WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} + COMMENT "nSIM COMMAND: ${NSIM} -propsfile ${BOARD_DIR}/support/${NSIM_PROPS} ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}" USES_TERMINAL ) diff --git a/cmake/emu/qemu.cmake b/cmake/emu/qemu.cmake index 87f5fa6a38d4..af38a2840e57 100644 --- a/cmake/emu/qemu.cmake +++ b/cmake/emu/qemu.cmake @@ -23,6 +23,19 @@ find_program( ) endif() +# We need to set up uefi-run and OVMF environment +# for testing UEFI method on qemu platforms +if(CONFIG_QEMU_UEFI_BOOT) + find_program(UEFI NAMES uefi-run REQUIRED) + if(DEFINED ENV{OVMF_FD_PATH}) + set(OVMF_FD_PATH $ENV{OVMF_FD_PATH}) + else() + message(FATAL_ERROR "Couldn't find an valid OVMF_FD_PATH.") + endif() + list(APPEND UEFI -b ${OVMF_FD_PATH} -q ${QEMU}) + set(QEMU ${UEFI}) +endif() + set(qemu_targets run debugserver @@ -242,7 +255,7 @@ elseif(QEMU_NET_STACK) endif() endif(QEMU_PIPE_STACK) -if(CONFIG_X86_64) +if(CONFIG_X86_64 AND NOT CONFIG_QEMU_UEFI_BOOT) # QEMU doesn't like 64-bit ELF files. Since we don't use any >4GB # addresses, converting it to 32-bit is safe enough for emulation. add_custom_target(qemu_image_target @@ -327,7 +340,10 @@ list(APPEND MORE_FLAGS_FOR_debugserver -s -S) # file to pass to qemu (and a "qemu_kernel_target" target to generate # it), or set QEMU_KERNEL_OPTION if they want to replace the "-kernel # ..." option entirely. -if(DEFINED QEMU_KERNEL_FILE) +if(CONFIG_QEMU_UEFI_BOOT) + set(QEMU_UEFI_OPTION ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.efi) + list(APPEND QEMU_UEFI_OPTION --) +elseif(DEFINED QEMU_KERNEL_FILE) set(QEMU_KERNEL_OPTION "-kernel;${QEMU_KERNEL_FILE}") elseif(NOT DEFINED QEMU_KERNEL_OPTION) set(QEMU_KERNEL_OPTION "-kernel;$") @@ -341,6 +357,7 @@ foreach(target ${qemu_targets}) ${PRE_QEMU_COMMANDS_FOR_${target}} COMMAND ${QEMU} + ${QEMU_UEFI_OPTION} ${QEMU_FLAGS_${ARCH}} ${QEMU_FLAGS} ${QEMU_EXTRA_FLAGS} diff --git a/cmake/extensions.cmake b/cmake/extensions.cmake index ea9c0f26a687..f864b8f286e6 100644 --- a/cmake/extensions.cmake +++ b/cmake/extensions.cmake @@ -21,6 +21,8 @@ # 3.5. File system management # 4. Devicetree extensions # 4.1 dt_* +# 5. Zephyr linker functions +# 5.1. zephyr_linker* ######################################################## # 1. Zephyr-aware extensions @@ -563,6 +565,30 @@ function(zephyr_library_app_memory partition) "-l" $ "${partition}") endfunction() +# Configure a Zephyr library specific property. +# +# Usage: +# zephyr_library_property( ) +# +# Current Zephyr library specific properties that are supported: +# ALLOW_EMPTY : Allow a Zephyr library to be empty. +# An empty Zephyr library will generate a CMake +# configure time warning unless `ALLOW_EMPTY` is TRUE. +function(zephyr_library_property) + set(single_args "ALLOW_EMPTY") + cmake_parse_arguments(LIB_PROP "" "${single_args}" "" ${ARGN}) + + if(LIB_PROP_UNPARSED_ARGUMENTS) + message(FATAL_ERROR "zephyr_library_property(${ARGV0} ...) given unknown arguments: ${FILE_UNPARSED_ARGUMENTS}") + endif() + + foreach(arg ${single_args}) + if(DEFINED LIB_PROP_${arg}) + set_property(TARGET ${ZEPHYR_CURRENT_LIBRARY} PROPERTY ${arg} ${LIB_PROP_${arg}}) + endif() + endforeach() +endfunction() + # 1.2.1 zephyr_interface_library_* # # A Zephyr interface library is a thin wrapper over a CMake INTERFACE @@ -788,8 +814,11 @@ function(board_finalize_runner_args runner) # Default arguments from the common runner file come first. ${ARGN} # Arguments explicitly given with board_runner_args() come - # last, so they take precedence. + # next, so they take precedence over the common runner file. ${explicit} + # Arguments given via the CMake cache come last of all. Users + # can provide variables in this way from the CMake command line. + ${BOARD_RUNNER_ARGS_${runner_id}} ) # Add the finalized runner to the global property list. @@ -1096,16 +1125,17 @@ endfunction(zephyr_check_compiler_flag_hardcoded) # Preprocessor directives work inside . Relative paths are resolved # relative to the calling file, like zephyr_sources(). # is one of -# NOINIT Inside the noinit output section. -# RWDATA Inside the data output section. -# RODATA Inside the rodata output section. -# ROM_START Inside the first output section of the image. This option is -# currently only available on ARM Cortex-M, ARM Cortex-R, -# x86, ARC, openisa_rv32m1, and RISC-V. -# Note: On RISC-V the rom_start section will be after vector section. -# RAM_SECTIONS Inside the RAMABLE_REGION GROUP. -# SECTIONS Near the end of the file. Don't use this when linking into -# RAMABLE_REGION, use RAM_SECTIONS instead. +# NOINIT Inside the noinit output section. +# RWDATA Inside the data output section. +# RODATA Inside the rodata output section. +# ROM_START Inside the first output section of the image. This option is +# currently only available on ARM Cortex-M, ARM Cortex-R, +# x86, ARC, openisa_rv32m1, and RISC-V. +# Note: On RISC-V the rom_start section will be after vector section. +# RAM_SECTIONS Inside the RAMABLE_REGION GROUP, not initialized. +# DATA_SECTIONS Inside the RAMABLE_REGION GROUP, initialized. +# SECTIONS Near the end of the file. Don't use this when linking into +# RAMABLE_REGION, use RAM_SECTIONS instead. # is an optional key to sort by inside of each location. The key must # be alphanumeric, and the keys are sorted alphabetically. If no key is # given, the key 'default' is used. Keys are case-sensitive. @@ -1120,8 +1150,8 @@ endfunction(zephyr_check_compiler_flag_hardcoded) # _mysection_end = .; # _mysection_size = ABSOLUTE(_mysection_end - _mysection_start); # -# When placing into SECTIONS or RAM_SECTIONS, the files must instead define -# their own output sections to achieve the same thing: +# When placing into SECTIONS, RAM_SECTIONS or DATA_SECTIONS, the files must +# instead define their own output sections to achieve the same thing: # SECTION_PROLOGUE(.mysection,,) # { # _mysection_start = .; @@ -1139,19 +1169,21 @@ endfunction(zephyr_check_compiler_flag_hardcoded) function(zephyr_linker_sources location) # Set up the paths to the destination files. These files are #included inside # the global linker.ld. - set(snippet_base "${__build_dir}/include/generated") - set(sections_path "${snippet_base}/snippets-sections.ld") - set(ram_sections_path "${snippet_base}/snippets-ram-sections.ld") - set(rom_start_path "${snippet_base}/snippets-rom-start.ld") - set(noinit_path "${snippet_base}/snippets-noinit.ld") - set(rwdata_path "${snippet_base}/snippets-rwdata.ld") - set(rodata_path "${snippet_base}/snippets-rodata.ld") + set(snippet_base "${__build_dir}/include/generated") + set(sections_path "${snippet_base}/snippets-sections.ld") + set(ram_sections_path "${snippet_base}/snippets-ram-sections.ld") + set(data_sections_path "${snippet_base}/snippets-data-sections.ld") + set(rom_start_path "${snippet_base}/snippets-rom-start.ld") + set(noinit_path "${snippet_base}/snippets-noinit.ld") + set(rwdata_path "${snippet_base}/snippets-rwdata.ld") + set(rodata_path "${snippet_base}/snippets-rodata.ld") # Clear destination files if this is the first time the function is called. get_property(cleared GLOBAL PROPERTY snippet_files_cleared) if (NOT DEFINED cleared) file(WRITE ${sections_path} "") file(WRITE ${ram_sections_path} "") + file(WRITE ${data_sections_path} "") file(WRITE ${rom_start_path} "") file(WRITE ${noinit_path} "") file(WRITE ${rwdata_path} "") @@ -1164,6 +1196,8 @@ function(zephyr_linker_sources location) set(snippet_path "${sections_path}") elseif("${location}" STREQUAL "RAM_SECTIONS") set(snippet_path "${ram_sections_path}") + elseif("${location}" STREQUAL "DATA_SECTIONS") + set(snippet_path "${data_sections_path}") elseif("${location}" STREQUAL "ROM_START") set(snippet_path "${rom_start_path}") elseif("${location}" STREQUAL "NOINIT") @@ -1243,6 +1277,38 @@ function(check_dtc_flag flag ok) endif() endfunction() +# Function to round number to next power of two. +# +# Usage: +# pow2round() +# +# Example: +# set(test 2) +# pow2round(test) +# # test is still 2 +# +# set(test 5) +# pow2round(test) +# # test is now 8 +# +# Arguments: +# n = Variable containing the number to round +function(pow2round n) + math(EXPR x "${${n}} & (${${n}} - 1)") + if(${x} EQUAL 0) + return() + endif() + + math(EXPR ${n} "${${n}} | (${${n}} >> 1)") + math(EXPR ${n} "${${n}} | (${${n}} >> 2)") + math(EXPR ${n} "${${n}} | (${${n}} >> 4)") + math(EXPR ${n} "${${n}} | (${${n}} >> 8)") + math(EXPR ${n} "${${n}} | (${${n}} >> 16)") + math(EXPR ${n} "${${n}} | (${${n}} >> 32)") + math(EXPR ${n} "${${n}} + 1") + set(${n} ${${n}} PARENT_SCOPE) +endfunction() + # Function to create a build string based on BOARD, BOARD_REVISION, and BUILD # type. # @@ -1448,24 +1514,12 @@ function(zephyr_library_sources_ifdef feature_toggle source) endif() endfunction() -function(zephyr_library_sources_ifndef feature_toggle source) - if(NOT ${feature_toggle}) - zephyr_library_sources(${source} ${ARGN}) - endif() -endfunction() - function(zephyr_sources_ifdef feature_toggle) if(${${feature_toggle}}) zephyr_sources(${ARGN}) endif() endfunction() -function(zephyr_sources_ifndef feature_toggle) - if(NOT ${feature_toggle}) - zephyr_sources(${ARGN}) - endif() -endfunction() - function(zephyr_cc_option_ifdef feature_toggle) if(${${feature_toggle}}) zephyr_cc_option(${ARGN}) @@ -1508,6 +1562,12 @@ function(zephyr_library_compile_definitions_ifdef feature_toggle item) endif() endfunction() +function(zephyr_library_include_directories_ifdef feature_toggle) + if(${${feature_toggle}}) + zephyr_library_include_directories(${ARGN}) + endif() +endfunction() + function(zephyr_library_compile_options_ifdef feature_toggle item) if(${${feature_toggle}}) zephyr_library_compile_options(${item} ${ARGN}) @@ -1546,24 +1606,144 @@ function(set_ifndef variable value) endif() endfunction() +function(add_subdirectory_ifndef feature_toggle source_dir) + if(NOT ${feature_toggle}) + add_subdirectory(${source_dir} ${ARGN}) + endif() +endfunction() + +function(target_sources_ifndef feature_toggle target scope item) + if(NOT ${feature_toggle}) + target_sources(${target} ${scope} ${item} ${ARGN}) + endif() +endfunction() + +function(target_compile_definitions_ifndef feature_toggle target scope item) + if(NOT ${feature_toggle}) + target_compile_definitions(${target} ${scope} ${item} ${ARGN}) + endif() +endfunction() + +function(target_include_directories_ifndef feature_toggle target scope item) + if(NOT ${feature_toggle}) + target_include_directories(${target} ${scope} ${item} ${ARGN}) + endif() +endfunction() + +function(target_link_libraries_ifndef feature_toggle target item) + if(NOT ${feature_toggle}) + target_link_libraries(${target} ${item} ${ARGN}) + endif() +endfunction() + +function(add_compile_option_ifndef feature_toggle option) + if(NOT ${feature_toggle}) + add_compile_options(${option}) + endif() +endfunction() + +function(target_compile_option_ifndef feature_toggle target scope option) + if(NOT ${feature_toggle}) + target_compile_options(${target} ${scope} ${option}) + endif() +endfunction() + function(target_cc_option_ifndef feature_toggle target scope option) if(NOT ${feature_toggle}) target_cc_option(${target} ${scope} ${option}) endif() endfunction() +function(zephyr_library_sources_ifndef feature_toggle source) + if(NOT ${feature_toggle}) + zephyr_library_sources(${source} ${ARGN}) + endif() +endfunction() + +function(zephyr_sources_ifndef feature_toggle) + if(NOT ${feature_toggle}) + zephyr_sources(${ARGN}) + endif() +endfunction() + function(zephyr_cc_option_ifndef feature_toggle) if(NOT ${feature_toggle}) zephyr_cc_option(${ARGN}) endif() endfunction() +function(zephyr_ld_option_ifndef feature_toggle) + if(NOT ${feature_toggle}) + zephyr_ld_options(${ARGN}) + endif() +endfunction() + +function(zephyr_link_libraries_ifndef feature_toggle) + if(NOT ${feature_toggle}) + zephyr_link_libraries(${ARGN}) + endif() +endfunction() + function(zephyr_compile_options_ifndef feature_toggle) if(NOT ${feature_toggle}) zephyr_compile_options(${ARGN}) endif() endfunction() +function(zephyr_compile_definitions_ifndef feature_toggle) + if(NOT ${feature_toggle}) + zephyr_compile_definitions(${ARGN}) + endif() +endfunction() + +function(zephyr_include_directories_ifndef feature_toggle) + if(NOT ${feature_toggle}) + zephyr_include_directories(${ARGN}) + endif() +endfunction() + +function(zephyr_library_compile_definitions_ifndef feature_toggle item) + if(NOT ${feature_toggle}) + zephyr_library_compile_definitions(${item} ${ARGN}) + endif() +endfunction() + +function(zephyr_library_include_directories_ifndef feature_toggle) + if(NOT ${feature_toggle}) + zephyr_library_include_directories(${ARGN}) + endif() +endfunction() + +function(zephyr_library_compile_options_ifndef feature_toggle item) + if(NOT ${feature_toggle}) + zephyr_library_compile_options(${item} ${ARGN}) + endif() +endfunction() + +function(zephyr_link_interface_ifndef feature_toggle interface) + if(NOT ${feature_toggle}) + target_link_libraries(${interface} INTERFACE zephyr_interface) + endif() +endfunction() + +function(zephyr_library_link_libraries_ifndef feature_toggle item) + if(NOT ${feature_toggle}) + zephyr_library_link_libraries(${item}) + endif() +endfunction() + +function(zephyr_linker_sources_ifndef feature_toggle) + if(NOT ${feature_toggle}) + zephyr_linker_sources(${ARGN}) + endif() +endfunction() + +macro(list_append_ifndef feature_toggle list) + if(NOT ${feature_toggle}) + list(APPEND ${list} ${ARGN}) + endif() +endmacro() + # 3.3. *_option Compiler-compatibility checks # # Utility functions for silently omitting compiler flags when the @@ -1676,30 +1856,35 @@ endfunction() # The argument 'include_files' is an output parameter with the result # of parsing the include files. function(toolchain_parse_make_rule input_file include_files) - file(READ ${input_file} input) + file(STRINGS ${input_file} input) # The file is formatted like this: # empty_file.o: misc/empty_file.c \ # nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts \ # nrf52840_qiaa.dtsi - # Get rid of the backslashes - string(REPLACE "\\" ";" input_as_list ${input}) + # The dep file will contain `\` for line continuation. + # This results in `\;` which is then treated a the char `;` instead of + # the element separator, so let's get the pure `;` back. + string(REPLACE "\;" ";" input_as_list ${input}) # Pop the first line and treat it specially - list(GET input_as_list 0 first_input_line) + list(POP_FRONT input_as_list first_input_line) string(FIND ${first_input_line} ": " index) math(EXPR j "${index} + 2") string(SUBSTRING ${first_input_line} ${j} -1 first_include_file) - list(REMOVE_AT input_as_list 0) - list(APPEND result ${first_include_file}) + # Remove whitespace before and after filename and convert to CMake path. + string(STRIP "${first_include_file}" first_include_file) + file(TO_CMAKE_PATH "${first_include_file}" first_include_file) + set(result "${first_include_file}") - # Add the other lines - list(APPEND result ${input_as_list}) - - # Strip away the newlines and whitespaces - list(TRANSFORM result STRIP) + # Remove whitespace before and after filename and convert to CMake path. + foreach(file ${input_as_list}) + string(STRIP "${file}" file) + file(TO_CMAKE_PATH "${file}" file) + list(APPEND result "${file}") + endforeach() set(${include_files} ${result} PARENT_SCOPE) endfunction() @@ -2657,12 +2842,12 @@ function(dt_reg_size var) cmake_parse_arguments(DT_REG "" "${req_single_args};${single_args}" "" ${ARGN}) if(${ARGV0} IN_LIST req_single_args) - message(FATAL_ERROR "dt_reg_addr(${ARGV0} ...) missing return parameter.") + message(FATAL_ERROR "dt_reg_size(${ARGV0} ...) missing return parameter.") endif() foreach(arg ${req_single_args}) if(NOT DEFINED DT_REG_${arg}) - message(FATAL_ERROR "dt_reg_addr(${ARGV0} ...) " + message(FATAL_ERROR "dt_reg_size(${ARGV0} ...) " "missing required argument: ${arg}" ) endif() @@ -2785,3 +2970,698 @@ function(dt_chosen var) set(${var} ${${var}} PARENT_SCOPE) endif() endfunction() + +######################################################## +# 5. Zephyr linker function +######################################################## +# 5.1. zephyr_linker* +# +# The following methods are for defining linker structure using CMake functions. +# +# This allows Zephyr developers to define linker sections and their content and +# have this configuration rendered into an appropriate linker script based on +# the toolchain in use. +# For example: +# ld linker scripts with GNU ld +# ARM scatter files with ARM linker. +# +# Example usage: +# zephyr_linker_section( +# NAME my_data +# VMA RAM +# LMA FLASH +# ) +# +# and to configure special input sections for the section +# zephyr_linker_section_configure( +# SECTION my_data +# INPUT "my_custom_data" +# KEEP +# ) + + +# Usage: +# zephyr_linker([FORMAT ] +# [ENTRY ] +# ) +# +# Zephyr linker general settings. +# This function specifies general settings for the linker script to be generated. +# +# FORMAT : The output format of the linked executable. +# ENTRY : The code entry symbol. +# +function(zephyr_linker) + set(single_args "ENTRY;FORMAT") + cmake_parse_arguments(LINKER "" "${single_args}" "" ${ARGN}) + + if(LINKER_UNPARSED_ARGUMENTS) + message(FATAL_ERROR "zephyr_linker(${ARGV0} ...) given unknown " + "arguments: ${LINKER_UNPARSED_ARGUMENTS}" + ) + endif() + + if(DEFINED LINKER_FORMAT) + get_property(format_defined TARGET linker PROPERTY FORMAT SET) + if(format_defined) + message(FATAL_ERROR "zephyr_linker(FORMAT ...) already configured.") + else() + set_property(TARGET linker PROPERTY FORMAT ${LINKER_FORMAT}) + endif() + endif() + + if(DEFINED LINKER_ENTRY) + get_property(entry_defined TARGET linker PROPERTY ENTRY SET) + if(entry_defined) + message(FATAL_ERROR "zephyr_linker(ENTRY ...) already configured.") + else() + set_property(TARGET linker PROPERTY ENTRY ${LINKER_ENTRY}) + endif() + endif() +endfunction() + +# Usage: +# zephyr_linker_memory(NAME START
SIZE FLAGS ) +# +# Zephyr linker memory. +# This function specifies a memory region for the platform in use. +# +# Note: +# This function should generally be called with values obtained from +# devicetree or Kconfig. +# +# NAME : Name of the memory region, for example FLASH. +# START
: Start address of the memory region. +# Start address can be given as decimal or hex value. +# SIZE : Size of the memory region. +# Size can be given as decimal value, hex value, or decimal with postfix k or m. +# All the following are valid values: +# 1048576, 0x10000, 1024k, 1024K, 1m, and 1M. +# FLAGS : Flags describing properties of the memory region. +# Currently supported: +# r: Read-only region +# w: Read-write region +# x: Executable region +# The flags r and x, or w and x may be combined like: rx, wx. +function(zephyr_linker_memory) + set(single_args "FLAGS;NAME;SIZE;START") + cmake_parse_arguments(MEMORY "" "${single_args}" "" ${ARGN}) + + if(MEMORY_UNPARSED_ARGUMENTS) + message(FATAL_ERROR "zephyr_linker_memory(${ARGV0} ...) given unknown " + "arguments: ${MEMORY_UNPARSED_ARGUMENTS}" + ) + endif() + + foreach(arg ${single_args}) + if(NOT DEFINED MEMORY_${arg}) + message(FATAL_ERROR "zephyr_linker_memory(${ARGV0} ...) missing required " + "argument: ${arg}" + ) + endif() + endforeach() + + set(MEMORY) + zephyr_linker_arg_val_list(MEMORY "${single_args}") + + string(REPLACE ";" "\;" MEMORY "${MEMORY}") + set_property(TARGET linker + APPEND PROPERTY MEMORY_REGIONS "{${MEMORY}}" + ) +endfunction() + +# Usage: +# zephyr_linker_memory_ifdef( NAME START
SIZE FLAGS ) +# +# Will create memory region if is enabled. +# +# : Setting to check for True value before invoking +# zephyr_linker_memory() +# +# See zephyr_linker_memory() description for other supported arguments. +# +macro(zephyr_linker_memory_ifdef feature_toggle) + if(${${feature_toggle}}) + zephyr_linker_memory(${ARGN}) + endif() +endmacro() + +# Usage: +# zephyr_linker_dts_memory(NAME PATH FLAGS ) +# zephyr_linker_dts_memory(NAME NODELABEL FLAGS ) +# zephyr_linker_dts_memory(NAME CHOSEN FLAGS ) +# +# Zephyr linker devicetree memory. +# This function specifies a memory region for the platform in use based on its +# devicetree configuration. +# +# The memory will only be defined if the devicetree node or a devicetree node +# matching the nodelabel exists and has status okay. +# +# Only one of PATH, NODELABEL, and CHOSEN parameters may be given. +# +# NAME : Name of the memory region, for example FLASH. +# PATH : Devicetree node identifier. +# NODELABEL