RISCV32: Add DWARF regno definitions

Ast-x64 · Ast-x64 · commit d93beb825920 · 2022-06-17T01:33:30.000+08:00
diff --git a/src/rt/dwarfeh.d b/src/rt/dwarfeh.d
@@ -78,6 +78,11 @@ else version (RISCV64)
     enum eh_exception_regno = 10;
     enum eh_selector_regno = 11;
 }
+else version (RISCV32)
+{
+    enum eh_exception_regno = 10;
+    enum eh_selector_regno = 11;
+}
 else
 {
     static assert(0, "Unknown EH register numbers for this architecture");

Original file line number	Diff line number	Diff line change
`@@ -78,6 +78,11 @@ else version (RISCV64)`
`78`	`78`	`enum eh_exception_regno = 10;`
`79`	`79`	`enum eh_selector_regno = 11;`
`80`	`80`	`}`
	`81`	`+else version (RISCV32)`
	`82`	`+{`
	`83`	`+ enum eh_exception_regno = 10;`
	`84`	`+ enum eh_selector_regno = 11;`
	`85`	`+}`
`81`	`86`	`else`
`82`	`87`	`{`
`83`	`88`	`static assert(0, "Unknown EH register numbers for this architecture");`