Merge branch 'master' into c40_flash_hal_nxp_1

Author: sumitbatra-nxp

mcux/README

@@ -246,3 +246,6 @@ Patch List:
      This patch was merged after PR https://github.com/zephyrproject-rtos/hal_nxp/pull/618/commits was created.
      Also since the additions about C40 Flash geometry in S32K344_features.h and defining local Flash Aliases in
      S32K344_glue_mcux.h, are for S32K344 SoC so they are not present in the mcusdk-core repo.
+  - mcux-sdk-ng: drivers: xspi: cache64: Fix cache management issue.
+   - PR: https://github.com/zephyrproject-rtos/hal_nxp/pull/597
+   - This patch is in hal_nxp but is not in mcux-sdk-ng 25.09.00.

mcux/mcux-sdk-ng/drivers/xspi/fsl_xspi.c

@@ -3054,7 +3054,7 @@ void XSPI_Cache64_InvalidateCacheByRange(uint32_t address, size_t size)
 {
     if (size > 0UL)
     {
-        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size - 0x01U);
+        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size);
         uint32_t pccReg  = 0;
         /* Align address to cache line size. */
         uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)FSL_FEATURE_CACHE64_LINESIZE_BYTE - 1U));
@@ -3070,7 +3070,7 @@ void XSPI_Cache64_InvalidateCacheByRange(uint32_t address, size_t size)
             return;
         }
         base    = s_xspi_cache64ctrlBases[instance];
-        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance] + phyMemSize[instance] - 0x01U);
+        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance] + phyMemSize[instance]);
         endAddr = endAddr > endLim ? endLim : endAddr;
 
         /* Set the invalidate by line command and use the physical address. */
@@ -3120,7 +3120,7 @@ void XSPI_Cache64_CleanCacheByRange(uint32_t address, size_t size)
 {
     if (size > 0UL)
     {
-        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size - 0x01U);
+        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size);
         uint32_t pccReg  = 0;
         /* Align address to cache line size. */
         uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)FSL_FEATURE_CACHE64_LINESIZE_BYTE - 1U));
@@ -3136,7 +3136,7 @@ void XSPI_Cache64_CleanCacheByRange(uint32_t address, size_t size)
             return;
         }
         base    = s_xspi_cache64ctrlBases[instance];
-        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance] + phyMemSize[instance] - 0x01U);
+        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance] + phyMemSize[instance]);
         endAddr = endAddr > endLim ? endLim : endAddr;
 
         /* Set the push by line command. */
@@ -3188,7 +3188,7 @@ void XSPI_Cache64_CleanInvalidateByRange(uint32_t address, size_t size)
 {
     if (size > 0UL)
     {
-        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size - 0x01U);
+        uint32_t endAddr = MSDK_REG_SECURE_ADDR(address + size);
         uint32_t pccReg  = 0;
         /* Align address to cache line size. */
         uint32_t startAddr = MSDK_REG_SECURE_ADDR(address & ~((uint32_t)FSL_FEATURE_CACHE64_LINESIZE_BYTE - 1U));
@@ -3204,7 +3204,7 @@ void XSPI_Cache64_CleanInvalidateByRange(uint32_t address, size_t size)
             return;
         }
         base    = s_xspi_cache64ctrlBases[instance];
-        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance] + phyMemSize[instance] - 0x01U);
+        endLim  = MSDK_REG_SECURE_ADDR(phyMemBase[instance] + phyMemSize[instance]);
         endAddr = endAddr > endLim ? endLim : endAddr;
 
         /* Set the push by line command. */

mcux/mcux-sdk-ng/middleware/usb/device/usb_device_ehci.c

@@ -363,16 +363,22 @@ _Pragma("diag_suppress=Pm120")
 
 #elif defined(__GNUC__)
 
+#if defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
+#define CS "//"
+#else
+#define CS "@"
+#endif
+
 #define USB_WEAK_VAR                 __attribute__((weak))
 #define USB_WEAK_FUN                 __attribute__((weak))
 #define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
 #define USB_LINK_DMA_INIT_DATA(sec)  __attribute__((section(#sec)))
-#define USB_LINK_USB_GLOBAL          __attribute__((section("m_usb_global, \"aw\", %nobits @")))
-#define USB_LINK_USB_BDT             __attribute__((section("m_usb_bdt, \"aw\", %nobits @")))
+#define USB_LINK_USB_GLOBAL          __attribute__((section("m_usb_global, \"aw\", %nobits " CS)))
+#define USB_LINK_USB_BDT             __attribute__((section("m_usb_bdt, \"aw\", %nobits " CS)))
 #define USB_LINK_USB_GLOBAL_BSS
 #define USB_LINK_USB_BDT_BSS
-#define USB_LINK_DMA_NONINIT_DATA      __attribute__((section("CacheLineData, \"aw\", %nobits @")))
-#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @")))
+#define USB_LINK_DMA_NONINIT_DATA      __attribute__((section("CacheLineData, \"aw\", %nobits " CS)))
+#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits " CS)))
 
 #elif (defined(__DSC__) && defined(__CW__))
 #define MAX(a, b)                    (((a) > (b)) ? (a) : (b))

mcux/mcux-sdk-ng/middleware/usb/include/usb_misc.h

@@ -53738,6 +53738,9 @@ typedef struct {
  * @{
  */
 
+/** TPM - Size of Registers Arrays */
+#define TPM_CONTROLS_COUNT                        4u
+
 /** TPM - Register Layout Typedef */
 typedef struct {
   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */