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Refactor module structure
1 parent a97ff5e commit dcbe39e

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14 files changed

+29
-33
lines changed

14 files changed

+29
-33
lines changed

src/bin/mlog.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,11 @@ use std::{error::Error, time::Instant};
33
use clap::Parser;
44
use clap_stdin::FileOrStdin;
55
use mindustry_rs::{
6-
logic::vm::{
6+
types::{Object, ProcessorConfig, ProcessorLinkConfig},
7+
vm::{
78
Building, BuildingData, HYPER_PROCESSOR, LOGIC_PROCESSOR, LogicVMBuilder, MEMORY_BANK,
89
MEMORY_CELL, MESSAGE, MICRO_PROCESSOR, WORLD_PROCESSOR,
910
},
10-
types::{Object, ProcessorConfig, ProcessorLinkConfig},
1111
};
1212
use strum_macros::EnumString;
1313
use widestring::U16String;

src/bin/mlogv32.rs

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,12 @@ use cursive::views::{
1818
};
1919
use indicatif::ProgressIterator;
2020
use itertools::Itertools;
21-
use mindustry_rs::logic::vm::{LObject, LVar};
2221
use mindustry_rs::{
23-
logic::vm::{
24-
Building, BuildingData, LValue, LogicVM, LogicVMBuilder, MEMORY_BANK, MESSAGE,
25-
MICRO_PROCESSOR, SWITCH, WORLD_PROCESSOR,
26-
},
2722
types::{Object, PackedPoint2, ProcessorConfig, schematics::Schematic},
23+
vm::{
24+
Building, BuildingData, LObject, LValue, LVar, LogicVM, LogicVMBuilder, MEMORY_BANK,
25+
MESSAGE, MICRO_PROCESSOR, SWITCH, WORLD_PROCESSOR,
26+
},
2827
};
2928
use serde::Deserialize;
3029
use widestring::{U16String, u16str};

src/lib.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ extern crate alloc;
55
#[cfg(feature = "std")]
66
extern crate std;
77

8-
pub mod logic;
8+
pub mod parser;
99
pub mod types;
1010
mod utils;
11+
pub mod vm;
File renamed without changes.

src/logic/mod.rs renamed to src/parser/mod.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
pub mod ast;
22
#[cfg(feature = "std")]
33
mod grammar_util;
4-
pub mod vm;
54

65
#[cfg(feature = "std")]
76
lalrpop_util::lalrpop_mod!(
@@ -21,9 +20,10 @@ use core::error::Error;
2120
use std::{boxed::Box, string::ToString};
2221

2322
#[cfg(feature = "std")]
24-
use crate::types::{PackedPoint2, content};
25-
#[cfg(feature = "std")]
26-
use vm::{Building, LogicVMBuilder, ProcessorBuilder};
23+
use crate::{
24+
types::{PackedPoint2, content},
25+
vm::{Building, LogicVMBuilder, ProcessorBuilder},
26+
};
2727

2828
#[cfg(feature = "std")]
2929
pub fn parse_and_serialize_ast(
Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -17,19 +17,17 @@ use super::{
1717
variables::{Content, LValue, LVar, RAD_DEG},
1818
};
1919
use crate::{
20-
logic::{
21-
ast::{self, ConditionOp, LogicOp, TileLayer},
22-
vm::{
23-
LObject,
24-
variables::{F64_DEG_RAD, F64_RAD_DEG, LString},
25-
},
26-
},
20+
parser::ast::{self, ConditionOp, LogicOp, TileLayer},
2721
types::{
2822
ContentType, LAccess, PackedPoint2, Team,
2923
colors::{self, f32_to_double_bits, f64_from_double_bits},
3024
content,
3125
},
3226
utils::{RapidHashMap, u16format},
27+
vm::{
28+
LObject,
29+
variables::{F64_DEG_RAD, F64_RAD_DEG, LString},
30+
},
3331
};
3432

3533
const MAX_IPT: i32 = 1000;
Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -274,11 +274,9 @@ mod tests {
274274
use widestring::u16str;
275275

276276
use crate::{
277-
logic::{
278-
ast,
279-
vm::{Building, BuildingData, LObject, LVar, processor::ProcessorBuilder},
280-
},
277+
parser::ast,
281278
types::{PackedPoint2, content},
279+
vm::{Building, BuildingData, LObject, LVar, processor::ProcessorBuilder},
282280
};
283281

284282
use super::LogicVMBuilder;
@@ -377,18 +375,18 @@ mod tests {
377375
use widestring::{U16Str, U16String, u16str};
378376

379377
use crate::{
380-
logic::vm::{
378+
types::{
379+
ContentID, ContentType, Object, PackedPoint2, ProcessorConfig, ProcessorLinkConfig,
380+
Team, colors::COLORS, content,
381+
},
382+
utils::u16format,
383+
vm::{
381384
buildings::{
382385
HYPER_PROCESSOR, MEMORY_BANK, MEMORY_CELL, MESSAGE, MICRO_PROCESSOR, SWITCH,
383386
WORLD_CELL,
384387
},
385388
variables::{Content, LValue, LVar},
386389
},
387-
types::{
388-
ContentID, ContentType, Object, PackedPoint2, ProcessorConfig, ProcessorLinkConfig,
389-
Team, colors::COLORS, content,
390-
},
391-
utils::u16format,
392390
};
393391

394392
use super::{
@@ -868,7 +866,7 @@ mod tests {
868866

869867
#[test]
870868
fn test_link_max_range() {
871-
let data = include_bytes!("../../../tests/logic/vm/test_link_max_range.msch");
869+
let data = include_bytes!("../../tests/vm/test_link_max_range.msch");
872870
let schematic = Schematic::read(&mut Cursor::new(data)).unwrap();
873871
let mut vm = LogicVM::from_schematic(&schematic).unwrap();
874872

@@ -1469,7 +1467,7 @@ mod tests {
14691467
.join("\n");
14701468
let code = format!("setrate 1000\n{code}\nstop");
14711469

1472-
let data = include_bytes!("../../../tests/logic/vm/test_sensor_schematic.msch");
1470+
let data = include_bytes!("../../tests/vm/test_sensor_schematic.msch");
14731471
let mut schematic = Schematic::read(&mut Cursor::new(data)).unwrap();
14741472

14751473
// replace main processor code

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