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Begin implementing supervisor mode
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‎README.md‎

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -92,20 +92,24 @@ Additionally, the machine trap vector CSR `mtvec` is initialized to `0xfffffff0`
9292

9393
## ISA
9494

95-
`RV32IMAZicntr_Zicsr_Zifencei_Zihintpause`
95+
`RV32IMAZicntr_Zicsr_Zifencei_Zihintpause_Svade`
9696

97-
Supported privilege levels: M, U
97+
Supported privilege levels: M, S, U
98+
99+
Supported address translation schemes: Bare, Sv32
98100

99101
| Extension | Version |
100102
| ----------- | ------- |
101103
| M-mode | 1.13 |
104+
| S-mode | 1.13 |
102105
| I | 2.1 |
103106
| M | 2.0 |
104107
| A | 2.1 |
105108
| Zicntr | 2.0 |
106109
| Zicsr | 2.0 |
107110
| Zifencei\* | 2.0 |
108111
| Zihintpause | 2.0 |
112+
| Svade | 1.0 |
109113
| Xmlogsys | N/A |
110114

111115
\* Zifencei is currently just a stub - the instruction cache is already updated on every write to memory.
@@ -138,13 +142,27 @@ CSR values are stored either in a RAM processor (CSRS) or in a variable in the C
138142
| `time[h]` | CPU | Frequency: ms. Traps in U-mode. |
139143
| `instret[h]` | CPU | Traps in U-mode. |
140144
| `hpmcounter*[h]` | CSRS | Not implemented. |
145+
| `sstatus` | CPU | Subset of `mstatus`. |
146+
| `sie` | CPU | Subset of `mie`. |
147+
| `stvec` | CSRS | Bits 1:0 read-only zero. |
148+
| `scounteren` | CSRS | Read-only zero. |
149+
| `senvcfg` | CSRS | Bits 31:1 read-only zero. |
150+
| `sscratch` | CSRS | |
151+
| `sepc` | CSRS | Bits 1:0 read-only zero. |
152+
| `scause` | CSRS | |
153+
| `stval` | CSRS | |
154+
| `sip` | CPU | Subset of `mip`. |
155+
| `satp` | CPU | |
141156
| `mvendorid` | CSRS | Read-only zero. |
142157
| `marchid` | CSRS | Read-only zero. |
143158
| `mimpid` | CSRS | Read-only zero. |
144159
| `mhartid` | CSRS | Read-only zero. |
145160
| `mstatus` | CPU | |
146161
| `mstatush` | CSRS | Read-only zero. |
147162
| `misa` | CSRS | Read-only. |
163+
| `medeleg` | CSRS | Read-only zero. |
164+
| `medelegh` | CSRS | Read-only zero. |
165+
| `mideleg` | CSRS | Read-only zero. |
148166
| `mie` | CPU | |
149167
| `mtvec` | CSRS | Bits 1:0 read-only zero. |
150168
| `mcounteren` | CSRS | Read-only zero. |
@@ -153,6 +171,10 @@ CSR values are stored either in a RAM processor (CSRS) or in a variable in the C
153171
| `mcause` | CSRS | Stored in CSRS because the CPU often speculatively sets the corresponding CPU variable. |
154172
| `mtval` | CSRS | Same reasoning as `mcause`. |
155173
| `mip` | CPU | |
174+
| `menvcfg` | CSRS | Bits 31:1 read-only zero. |
175+
| `menvcfgh` | CSRS | Read-only zero. |
176+
| `pmpcfg*` | CSRS | Read-only zero. |
177+
| `pmpaddr*` | CSRS | Read-only zero. |
156178
| `mcycle[h]` | CSRS | See `cycle[h]`. |
157179
| `minstret[h]` | CPU | See `instret[h]`. |
158180
| `mhpmcounter*[h]` | CSRS | See `hpmcounter*[h]`. |

‎python/src/mlogv32/preprocessor/filters.py‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,25 @@ def memory_size(size: int):
7979
"timeh": 0xC81,
8080
"instreth": 0xC82,
8181
**{f"hpmcounter{i}h": 0xC80 + i for i in range(3, 32)},
82+
# supervisor
83+
"sstatus": 0x100,
84+
"sie": 0x104,
85+
"stvec": 0x105,
86+
"scounteren": 0x106,
87+
"senvcfg": 0x10A,
88+
"scountinhibit": 0x120,
89+
"sscratch": 0x140,
90+
"sepc": 0x141,
91+
"scause": 0x142,
92+
"stval": 0x143,
93+
"sip": 0x144,
94+
"scountovf": 0xDA0,
95+
"satp": 0x180,
96+
"scontext": 0x5A8,
97+
"sstateen0": 0x10C,
98+
"sstateen1": 0x10D,
99+
"sstateen2": 0x10E,
100+
"sstateen3": 0x10F,
82101
# machine
83102
"mvendorid": 0xF11,
84103
"marchid": 0xF12,

‎riscof/mlogv32/mlogv32_isa.yaml‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# https://riscv-config.readthedocs.io/en/stable/yaml-specs.html
22
hart_ids: [0]
33
hart0:
4-
ISA: RV32IMAUZicsr_Zifencei
4+
ISA: RV32IMASUZicsr_Zifencei
55
physical_addr_sz: 32
66
User_Spec_Version: '2.3'
77
Privilege_Spec_Version: '1.11'
@@ -13,15 +13,16 @@ hart0:
1313
mtval_update: 0b11111011
1414
misa:
1515
# X bit is disabled because riscv-config doesn't seem to like it
16-
reset-val: 0b01000000000100000001000100000001
16+
# ZYXWVUTSRQPONMLKJIHGFEDCBA
17+
reset-val: 0b01000000000101000001000100000001
1718
rv32:
1819
accessible: true
1920
extensions:
2021
implemented: true
2122
type:
2223
warl:
2324
legal:
24-
- extensions[25:0] in [0b00000100000001000100000001]
25+
- extensions[25:0] in [0b00000101000001000100000001]
2526
wr_illegal:
2627
- unchanged
2728
cycle:

‎riscof/mlogv32/riscof_mlogv32.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,7 @@ def runTests(self, testlist: dict[str, Any]):
129129
"riscv-arch-test/riscv-test-suite/"
130130
)
131131

132-
logger.info(f"Building test: {test_display_name}")
132+
logger.info(f"Building test: {test_display_name}")
133133

134134
# for each testname we get all its fields (as described by the testlist format)
135135
testentry = testlist[testname]
@@ -228,7 +228,7 @@ def runTests(self, testlist: dict[str, Any]):
228228
f"{begin_signature=:#x} {end_signature=:#x} {signature_length=}"
229229
)
230230

231-
logger.info(f"Running test: {test_display_name}")
231+
logger.info(f"Running test: {test_display_name}")
232232

233233
processor.stop()
234234
processor.flash(binary_file_host)

‎src/cpu/controller.mlog.jinja‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,9 @@ end_slow_init:
135135

136136
# set mcause to 0, since we don't distinguish different reset conditions
137137
# use null so the debugger can tell if it's a reset or a misaligned instruction
138+
# also set scause (unspecified)
138139
write null {{CSRS}} "{{ 'mcause'|csr }}"
140+
write null {{CSRS}} "{{ 'scause'|csr }}"
139141

140142
# clear LR/SC reservation set
141143
set reservation_set null
@@ -157,14 +159,18 @@ end_slow_init:
157159
set csr_mie 0
158160
set interrupt_flags 0b00
159161

160-
# reset mtvec to implementation-defined value to help catch bugs
162+
# reset mtvec and stvec to implementation-defined value to help catch bugs
161163
write {{SYSCON}} {{CSRS}} "{{ 'mtvec'|csr }}"
164+
write {{SYSCON}} {{CSRS}} "{{ 'stvec'|csr }}"
165+
166+
# clear satp
167+
set csr_satp 0
162168

163169
# misa
164170
# XLEN=32 --
165171
# 0 ----
166172
# ISA ZYXWVUTSRQPONMLKJIHGFEDCBA
167-
write 0b01000000100100000001000100000001 {{CSRS}} "{{ 'misa'|csr }}"
173+
write 0b01000000100101000001000100000001 {{CSRS}} "{{ 'misa'|csr }}"
168174

169175
# mlogv32 only has one hart, so mhartid is required to be zero
170176
write 0 {{CSRS}} "{{ 'mhartid'|csr }}"
@@ -179,8 +185,9 @@ end_slow_init:
179185
write 0 {{CSRS}} "{{ 'mscratch'|csr }}"
180186
write 0 {{CSRS}} "{{ 'mtval'|csr }}"
181187

182-
# clear critical section if set
183-
set controller_critical_section null
188+
write 0 {{CSRS}} "{{ 'sepc'|csr }}"
189+
write 0 {{CSRS}} "{{ 'sscratch'|csr }}"
190+
write 0 {{CSRS}} "{{ 'stval'|csr }}"
184191

185192
# align to tick
186193
wait 1e-5
@@ -214,11 +221,9 @@ end_breakpoint:
214221

215222
# check which CSR we're currently updating, if any
216223

217-
# update time
224+
# update mtime
218225
# TODO: handle mtimeh/mcycleh overflow
219226

220-
jump skip_mtime_update equal controller_critical_section "mtime"
221-
222227
op sub delta_ms @time last_mtime_update
223228

224229
op add csr_mtime csr_mtime delta_ms
@@ -232,15 +237,12 @@ end_breakpoint:
232237
write csr_mtime prev_proc "csr_mtime"
233238
write csr_mtimeh prev_proc "csr_mtimeh"
234239

235-
skip_mtime_update:
236240
set last_mtime_update @time
237241

238-
# update cycle
239-
# we define the rate of increase of cycle as "@ipt * ticks"
242+
# update mcycle
243+
# we define the rate of increase of mcycle as "@ipt * ticks"
240244
# this should be a decent estimation of the number of mlog instructions executed
241245

242-
jump skip_mcycle_update equal controller_critical_section "mcycle"
243-
244246
read csr_mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
245247
read csr_mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
246248

@@ -257,10 +259,7 @@ skip_mtime_update:
257259

258260
write csr_mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
259261
write csr_mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
260-
write csr_mcycle {{CSRS}} "{{ 'cycle'|csr }}"
261-
write csr_mcycleh {{CSRS}} "{{ 'cycleh'|csr }}"
262262

263-
skip_mcycle_update:
264263
set last_mcycle_update @tick
265264

266265
# tell the next worker to poll and fire interrupts
@@ -362,5 +361,6 @@ set _ csr_minstreth
362361
set _ csr_mstatus
363362
set _ csr_mip
364363
set _ csr_mie
364+
set _ csr_satp
365365
set _ interrupt_flags
366366
# {% endraw %}

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