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Use Jinja preprocessor to remove some constant variables from the code
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+283
-86
lines changed

11 files changed

+283
-86
lines changed

.gitignore

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*.hex
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/build/
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/out/
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/src/main.mlog
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node_modules/
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.vscode/settings.json

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{
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"files.associations": {
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"*.s": "riscv"
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"*.s": "riscv",
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"*.mlog.jinja": "mlog"
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},
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"[markdown]": {
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"editor.formatOnSave": true,

nodemon.json

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{
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"watch": ["src", "python"],
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"ext": "jinja,py",
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"exec": "python -m mlogv32.preprocessor src/main.mlog.jinja -o src/main.mlog"
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}

pyproject.toml

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@@ -7,6 +7,7 @@ name = "mlogv32"
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version = "0.1.0"
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requires-python = ">=3.12"
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dependencies = [
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"jinja2>=3.1.6",
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"pydantic>=2.11.5",
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"pymsch>=0.0.11",
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"pyperclip>=1.9.0",
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"""Fairly simple mlog preprocessor script."""
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from .app import app
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app()
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from pathlib import Path
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from typing import Annotated
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from jinja2 import Environment, FileSystemLoader, StrictUndefined
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from typer import Option, Typer
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from . import filters
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app = Typer()
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@app.command()
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def main(
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path: Path,
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output: Annotated[Path | None, Option("-o", "--output")] = None,
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):
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path = path.resolve()
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env = Environment(
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loader=FileSystemLoader(path.parent),
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line_statement_prefix="#%",
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line_comment_prefix="#%#",
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autoescape=False,
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lstrip_blocks=True,
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trim_blocks=True,
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undefined=StrictUndefined,
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)
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env.filters |= { # pyright: ignore[reportAttributeAccessIssue]
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"ram_variable": filters.ram_variable,
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"quote": filters.quote,
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"csr": filters.csr,
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}
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template = env.get_template(path.name)
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result = template.render()
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if output:
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output.parent.mkdir(parents=True, exist_ok=True)
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output.write_text(result, "utf-8")
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else:
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print(result)
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if __name__ == "__main__":
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app()
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import functools
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from typing import Any, Callable
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from jinja2.runtime import Context
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from mlogv32.scripts.ram_proc import VariableFormat
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# from hexdoc.jinja.filters
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def make_jinja_exceptions_suck_a_bit_less[**P, R](f: Callable[P, R]) -> Callable[P, R]:
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@functools.wraps(f)
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def wrapper(*args: P.args, **kwargs: P.kwargs):
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try:
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return f(*args, **kwargs)
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except Exception as e:
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args_ = list(args)
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if args_ and isinstance(args_[0], Context):
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args_ = args_[1:]
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e.add_note(f"args: {args_}")
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e.add_note(f"kwargs: {kwargs}")
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raise
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return wrapper
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@make_jinja_exceptions_suck_a_bit_less
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def ram_variable(index: int):
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return VariableFormat.minimized.get_variable(index)
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@make_jinja_exceptions_suck_a_bit_less
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def csr(name: str | int):
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match name:
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case str():
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if name not in CSRS:
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raise KeyError(f"Invalid CSR: {name}")
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return ram_variable(CSRS[name])
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case int():
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return ram_variable(name)
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@make_jinja_exceptions_suck_a_bit_less
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def quote(value: Any):
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return f'"{value}"'
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CSRS: dict[str, int] = {
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# unprivileged
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"cycle": 0xC00,
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"time": 0xC01,
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"instret": 0xC02,
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**{f"hpmcounter{i}": 0xC00 + i for i in range(3, 32)},
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"cycleh": 0xC80,
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"timeh": 0xC81,
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"instreth": 0xC82,
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**{f"hpmcounter{i}h": 0xC80 + i for i in range(3, 32)},
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# supervisor
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"sstatus": 0x100,
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"sie": 0x104,
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"stvec": 0x105,
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"scounteren": 0x106,
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"senvcfg": 0x10A,
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"scountinhibit": 0x120,
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"sscratch": 0x140,
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"sepc": 0x141,
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"scause": 0x142,
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"stval": 0x143,
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"sip": 0x144,
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"scountovf": 0xDA0,
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"satp": 0x180,
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"scontext": 0x5A8,
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"sstateen0": 0x10C,
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"sstateen1": 0x10D,
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"sstateen2": 0x10E,
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"sstateen3": 0x10F,
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# machine
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"mvendorid": 0xF11,
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"marchid": 0xF12,
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"mimpid": 0xF13,
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"mhartid": 0xF14,
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"mconfigptr": 0xF15,
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"mstatus": 0x300,
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"misa": 0x301,
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"medeleg": 0x302,
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"mideleg": 0x303,
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"mie": 0x304,
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"mtvec": 0x305,
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"mcounteren": 0x306,
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"mstatush": 0x310,
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"medelegh": 0x312,
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"mscratch": 0x340,
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"mepc": 0x341,
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"mcause": 0x342,
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"mtval": 0x343,
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"mip": 0x344,
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"mtinst": 0x34A,
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"mtval2": 0x34B,
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"menvcfg": 0x30A,
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"menvcfgh": 0x31A,
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"mseccfg": 0x747,
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"mseccfgh": 0x757,
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**{f"pmpcfg{i}": 0x3A0 + i for i in range(0, 16)},
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**{f"pmpaddr{i}": 0x3B0 + i for i in range(0, 64)},
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"mstateen0": 0x30C,
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"mstateen1": 0x30D,
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"mstateen2": 0x30E,
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"mstateen3": 0x30F,
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"mstateen0h": 0x31C,
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"mstateen1h": 0x31D,
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"mstateen2h": 0x31E,
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"mstateen3h": 0x31F,
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}

src/main.constants.jinja

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{#- preprocessor constants for main.mlog.jinja -#}
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{#- linked buildings -#}
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{% set REGISTERS = 'cell1' %}
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{% set CSRS = 'processor17' %}
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{% set INCR = 'processor18' %}
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{% set CONFIG = 'processor19' %}
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{% set ERROR_OUTPUT = 'message1' %}
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{% set RESET_SWITCH = 'switch1' %}
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{% set PAUSE_SWITCH = 'switch2' %}
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{% set SINGLE_STEP_SWITCH = 'switch3' %}
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{% set KBCONV_DATA = 'cell2' %}
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{% set DISPLAY = 'display1' %}
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{% block contents %}{% endblock %}

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