|
| 1 | +import functools |
| 2 | +from typing import Any, Callable |
| 3 | + |
| 4 | +from jinja2.runtime import Context |
| 5 | + |
| 6 | +from mlogv32.scripts.ram_proc import VariableFormat |
| 7 | + |
| 8 | + |
| 9 | +# from hexdoc.jinja.filters |
| 10 | +def make_jinja_exceptions_suck_a_bit_less[**P, R](f: Callable[P, R]) -> Callable[P, R]: |
| 11 | + @functools.wraps(f) |
| 12 | + def wrapper(*args: P.args, **kwargs: P.kwargs): |
| 13 | + try: |
| 14 | + return f(*args, **kwargs) |
| 15 | + except Exception as e: |
| 16 | + args_ = list(args) |
| 17 | + if args_ and isinstance(args_[0], Context): |
| 18 | + args_ = args_[1:] |
| 19 | + |
| 20 | + e.add_note(f"args: {args_}") |
| 21 | + e.add_note(f"kwargs: {kwargs}") |
| 22 | + raise |
| 23 | + |
| 24 | + return wrapper |
| 25 | + |
| 26 | + |
| 27 | +@make_jinja_exceptions_suck_a_bit_less |
| 28 | +def ram_variable(index: int): |
| 29 | + return VariableFormat.minimized.get_variable(index) |
| 30 | + |
| 31 | + |
| 32 | +@make_jinja_exceptions_suck_a_bit_less |
| 33 | +def csr(name: str | int): |
| 34 | + match name: |
| 35 | + case str(): |
| 36 | + if name not in CSRS: |
| 37 | + raise KeyError(f"Invalid CSR: {name}") |
| 38 | + return ram_variable(CSRS[name]) |
| 39 | + case int(): |
| 40 | + return ram_variable(name) |
| 41 | + |
| 42 | + |
| 43 | +@make_jinja_exceptions_suck_a_bit_less |
| 44 | +def quote(value: Any): |
| 45 | + return f'"{value}"' |
| 46 | + |
| 47 | + |
| 48 | +CSRS: dict[str, int] = { |
| 49 | + # unprivileged |
| 50 | + "cycle": 0xC00, |
| 51 | + "time": 0xC01, |
| 52 | + "instret": 0xC02, |
| 53 | + **{f"hpmcounter{i}": 0xC00 + i for i in range(3, 32)}, |
| 54 | + "cycleh": 0xC80, |
| 55 | + "timeh": 0xC81, |
| 56 | + "instreth": 0xC82, |
| 57 | + **{f"hpmcounter{i}h": 0xC80 + i for i in range(3, 32)}, |
| 58 | + # supervisor |
| 59 | + "sstatus": 0x100, |
| 60 | + "sie": 0x104, |
| 61 | + "stvec": 0x105, |
| 62 | + "scounteren": 0x106, |
| 63 | + "senvcfg": 0x10A, |
| 64 | + "scountinhibit": 0x120, |
| 65 | + "sscratch": 0x140, |
| 66 | + "sepc": 0x141, |
| 67 | + "scause": 0x142, |
| 68 | + "stval": 0x143, |
| 69 | + "sip": 0x144, |
| 70 | + "scountovf": 0xDA0, |
| 71 | + "satp": 0x180, |
| 72 | + "scontext": 0x5A8, |
| 73 | + "sstateen0": 0x10C, |
| 74 | + "sstateen1": 0x10D, |
| 75 | + "sstateen2": 0x10E, |
| 76 | + "sstateen3": 0x10F, |
| 77 | + # machine |
| 78 | + "mvendorid": 0xF11, |
| 79 | + "marchid": 0xF12, |
| 80 | + "mimpid": 0xF13, |
| 81 | + "mhartid": 0xF14, |
| 82 | + "mconfigptr": 0xF15, |
| 83 | + "mstatus": 0x300, |
| 84 | + "misa": 0x301, |
| 85 | + "medeleg": 0x302, |
| 86 | + "mideleg": 0x303, |
| 87 | + "mie": 0x304, |
| 88 | + "mtvec": 0x305, |
| 89 | + "mcounteren": 0x306, |
| 90 | + "mstatush": 0x310, |
| 91 | + "medelegh": 0x312, |
| 92 | + "mscratch": 0x340, |
| 93 | + "mepc": 0x341, |
| 94 | + "mcause": 0x342, |
| 95 | + "mtval": 0x343, |
| 96 | + "mip": 0x344, |
| 97 | + "mtinst": 0x34A, |
| 98 | + "mtval2": 0x34B, |
| 99 | + "menvcfg": 0x30A, |
| 100 | + "menvcfgh": 0x31A, |
| 101 | + "mseccfg": 0x747, |
| 102 | + "mseccfgh": 0x757, |
| 103 | + **{f"pmpcfg{i}": 0x3A0 + i for i in range(0, 16)}, |
| 104 | + **{f"pmpaddr{i}": 0x3B0 + i for i in range(0, 64)}, |
| 105 | + "mstateen0": 0x30C, |
| 106 | + "mstateen1": 0x30D, |
| 107 | + "mstateen2": 0x30E, |
| 108 | + "mstateen3": 0x30F, |
| 109 | + "mstateen0h": 0x31C, |
| 110 | + "mstateen1h": 0x31D, |
| 111 | + "mstateen2h": 0x31E, |
| 112 | + "mstateen3h": 0x31F, |
| 113 | +} |
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