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Commit 21f495a

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Clarify mcause 0 message
1 parent 5728e3e commit 21f495a

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2 files changed

+10
-5
lines changed

2 files changed

+10
-5
lines changed

src/debugger.mlog.jinja

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -755,18 +755,18 @@ format_uart__rx_fifo_size__no_overrun:
755755
set @counter ret
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format_mcause:
758-
jump format_null strictEqual n null
758+
jump format_mcause__reset strictEqual n null
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jump format_mcause__interrupt greaterThanEq n 0x80000000
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jump format_hex greaterThan n 19
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op mul jump n 2
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op add @counter @counter jump
763-
format "instr addr align"; set @counter ret
763+
format "instr misalign"; set @counter ret
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format "instr access fault"; set @counter ret
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format "illegal instr"; set @counter ret
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format "breakpoint"; set @counter ret
767-
format "load addr align"; set @counter ret
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format "load misalign"; set @counter ret
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format "load access fault"; set @counter ret
769-
format "store/AMO addr align"; set @counter ret
769+
format "store/AMO misalign"; set @counter ret
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format "store/AMO access fault"; set @counter ret
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format "ecall from U-mode"; set @counter ret
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format "ecall from S-mode"; set @counter ret
@@ -781,6 +781,10 @@ format_mcause:
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format "software check"; set @counter ret
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format "hardware check"; set @counter ret
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784+
format_mcause__reset:
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format "reset"
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set @counter ret
787+
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format_mcause__interrupt:
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op and n2 n 0x7fffffff
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op mod rem n2 2

src/main.mlog.jinja

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,8 @@ reset:
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set icache_var null
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# set mcause to 0, since we don't distinguish different reset conditions
62-
write 0 {{CSRS}} "{{ 'mcause'|csr }}"
62+
# use null so the debugger can tell if it's a reset or a misaligned instruction
63+
write null {{CSRS}} "{{ 'mcause'|csr }}"
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# clear LR/SC reservation set
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set reservation_set null

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