Increment cycle at start of each worker instead of based on @tick and @ipt

Author: object-Object

README.md

@@ -144,6 +144,14 @@ The `mlogsys.icache` M-mode instruction uses register _rs1_ as the number of byt
 
 CSR values are stored either in a RAM processor (CSRS), in a variable in the CPU, or as an implicit read-only zero value, depending on the CSR. See [cpu.yaml](src/cpu/cpu.yaml) for the full list of implemented CSRs. Attempts to access a CSR that is not in this list will raise an illegal instruction exception.
 
+### `cycle`
+
+The `[m]cycle[h]` counter is incremented at the start of each worker's tick, just before it jumps back into code execution. The period should be something like `number of workers * 1/60 seconds`, but it will vary based on FPS.
+
+### `time`
+
+The `[m]time[h]` counter is based on the `@time` value in Mindustry. It has a period of 1 ms, and is incremented once per tick by the controller based on the time delta since the previous tick.
+
 ## riscv-arch-test
 
 mlogv32 currently passes all compliance tests for the `RV32IMASUZicsr_Zifencei` ISA.

python/src/mlogv32/preprocessor/parser/mlog.py

@@ -176,11 +176,13 @@ def check_unsaved_variables(ast: Iterable[ASTNode]):
             case Directive(name="end_fetch"):
                 state = "check"
                 continue
-            case Directive(name="push_saved", args=[var]):
-                saved_variables.add(var)
+            case Directive(name="push_saved", args=args):
+                for var in args:
+                    saved_variables.add(var)
                 continue
-            case Directive(name="pop_saved", args=[var]):
-                saved_variables.remove(var)
+            case Directive(name="pop_saved", args=args):
+                for var in args:
+                    saved_variables.remove(var)
                 continue
             case _:
                 continue

src/cpu/controller.mlog.jinja

@@ -247,9 +247,8 @@ end_slow_init:
     # align to tick
     wait 1e-5
 
-    # set mtime/mcycle reference points
+    # set mtime reference point
     set last_mtime_update @time
-    set last_mcycle_update @tick
 
     # start the workers
     set prev_proc @this
@@ -282,7 +281,7 @@ end_breakpoint:
     # check which CSR we're currently updating, if any
 
     # update mtime
-    # TODO: handle mtimeh/mcycleh overflow
+    # TODO: handle mtimeh overflow
 
     op sub delta_ms @time last_mtime_update
 
@@ -299,29 +298,6 @@ end_breakpoint:
 
     set last_mtime_update @time
 
-    # update mcycle
-    # we define the rate of increase of mcycle as "@ipt * ticks"
-    # this should be a decent estimation of the number of mlog instructions executed
-
-    read csr_mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
-    read csr_mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
-
-    op sub delta_cycles @tick last_mcycle_update
-    op mul delta_cycles delta_cycles @ipt
-
-    op add csr_mcycle csr_mcycle delta_cycles
-    op floor csr_mcycle csr_mcycle
-
-    op shr overflow csr_mcycle 32
-    op add csr_mcycleh csr_mcycleh overflow
-
-    op mod csr_mcycle csr_mcycle 0x100000000
-
-    write csr_mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
-    write csr_mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
-
-    set last_mcycle_update @tick
-
     # tell the next worker to poll and fire interrupts
     op or csr_mip csr_mip 0b11000000000000000000000000000000
     write csr_mip prev_proc "csr_mip"
@@ -360,9 +336,8 @@ breakpoint__end_loop:
     set state "running"
     write state prev_proc "state"
 
-    # pause timers while at a breakpoint
+    # pause timer while at a breakpoint
     set last_mtime_update @time
-    set last_mcycle_update @tick
 
     jump end_breakpoint always
 
@@ -439,8 +414,6 @@ set _ csr_mtimecmp
 set _ csr_mtimecmph
 set _ csr_stimecmp
 set _ csr_stimecmph
-set _ csr_mcycle
-set _ csr_mcycleh
 set _ csr_minstret
 set _ csr_mstatus
 set _ csr_mip

src/cpu/worker.mlog.jinja

@@ -94,7 +94,7 @@
 
 #% set labels.next_tick = 14
 
-#% set labels.end_instruction_with_rd_and_poll_interrupts = 147
+#% set labels.end_instruction_with_rd_and_poll_interrupts = 155
 #% set labels.end_instruction_with_rd_and_fire_interrupts = _labels_vals|last + 1
 #% set labels.end_instruction_with_rd                     = _labels_vals|last + 1
 #% set labels.end_instruction                             = _labels_vals|last + 2
@@ -140,16 +140,34 @@ reset:
     # tell the next worker to fetch the hart state from us
     write @this {{CONTROLLER}} "prev_proc"
 
+    # these variables don't need to be saved because this should only ever run at the start of a tick
+
+#directive push_saved __mcycle __mcycleh
+    # increment mcycle
+    read __mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
+    op add __mcycle __mcycle 1
+    jump reset__no_overflow lessThan __mcycle 0x100000000
+
+    # overflow mcycle into mcycleh
+    # TODO: handle mcycleh overflow
+    set __mcycle 0
+    read __mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
+    op add __mcycleh __mcycleh 1
+    write __mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
+
+reset__no_overflow:
+    write __mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
+#directive pop_saved __mcycle __mcycleh
+
     # if we just started executing, don't restore @counter
     jump poll_interrupts equal prev_proc {{CONTROLLER}}
 
+#directive push_saved __counter
     # otherwise, jump to whatever instruction the previous worker would have executed next
-    # _counter doesn't need to be saved because this should only ever run at the start of a tick
-#directive push_saved _counter
-    read _counter prev_proc "@counter"
+    read __counter prev_proc "@counter"
     write {{labels.next_tick}} prev_proc "@counter"
-    set @counter _counter
-#directive pop_saved _counter
+    set @counter __counter
+#directive pop_saved __counter
 
 # check if software-manipulable interrupts should become pending
 # this runs at the start of the first worker each tick, and at the start of the next worker if certain CSRs/MMRs are modified
@@ -296,7 +314,7 @@ main__read_icache:
     op and rs2_id rs2_id 0b11111
 
     # read rs1 and rs2
-    # this wastes 1 cycle for I-type and 2 cycles for U-type and J-type, but it saves a huge amount of space
+    # this wastes 1 instruction for I-type and 2 for U-type and J-type, but it saves a huge amount of space
     read rs1 {{REGISTERS}} rs1_id
     read rs2 {{REGISTERS}} rs2_id