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Refactor CSR instructions, use rd instead of result, add next_pc
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‎README.md‎

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@@ -176,6 +176,36 @@ Returns 1 if the id was successfully looked up, or 0 if the lookup returned null
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Only alignment `topLeft` is supported.
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## CSRs
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CSR values are stored either in a RAM processor (CSRS) or in a variable in the CPU, depending on the CSR. Following is a table of CSRs, their storage location, and any relevant notes (eg. supported fields).
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| CSR | Location | Notes |
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| ----------------- | -------- | --------------------------------------------------------------------------------------- |
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| `cycle[h]` | CPU | Frequency: ticks \* ipt. Traps in U-mode. |
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| `time[h]` | CPU | Frequency: ms. Traps in U-mode. |
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| `instret[h]` | CPU | Traps in U-mode. |
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| `hpmcounter*[h]` | CSRS | Not implemented. |
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| `mvendorid` | CSRS | Read-only zero. |
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| `marchid` | CSRS | Read-only zero. |
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| `mimpid` | CSRS | Read-only zero. |
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| `mhartid` | CSRS | Read-only zero. |
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| `mstatus` | CPU | |
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| `mstatush` | CSRS | Read-only zero. |
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| `misa` | CSRS | Read-only. |
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| `mie` | CPU | |
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| `mtvec` | CSRS | Bits 1:0 read-only zero. |
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| `mcounteren` | CSRS | Read-only zero. |
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| `mscratch` | CSRS | |
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| `mepc` | CSRS | Bits 1:0 read-only zero. |
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| `mcause` | CSRS | Stored in CSRS because the CPU often speculatively sets the corresponding CPU variable. |
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| `mtval` | CSRS | Same reasoning as `mcause`. |
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| `mip` | CPU | |
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| `mcycle[h]` | CPU | See `cycle[h]`. |
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| `minstret[h]` | CPU | See `instret[h]`. |
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| `mhpmcounter*[h]` | CSRS | See `hpmcounter*[h]`. |
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| `mcountinhibit` | CSRS | Not implemented. |
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## riscv-arch-test
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mlogv32 currently passes all compliance tests for the `RV32IMAUZicsr_Zifencei` ISA.

‎src/debugger.mlog.jinja‎

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@@ -155,30 +155,30 @@ loop:
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read x30_t5 REGISTERS 30
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read x31_t6 REGISTERS 31
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read cycle CSRS "{{ 'cycle'|csr }}"
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read cycleh CSRS "{{ 'cycleh'|csr }}"
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op shl cycleh cycleh 32
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op add cycle cycle cycleh
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read mcycle CPU "csr_mcycle"
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read mcycleh CPU "csr_mcycleh"
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op shl mcycleh mcycleh 32
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op add mcycle mcycle mcycleh
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read time CSRS "{{ 'time'|csr }}"
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read timeh CSRS "{{ 'timeh'|csr }}"
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op shl timeh timeh 32
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op add time time timeh
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read mtime CPU "csr_mtime"
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read mtimeh CPU "csr_mtimeh"
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op shl mtimeh mtimeh 32
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op add mtime mtime mtimeh
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read mtimecmp CPU "mtimecmp"
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read mtimecmph CPU "mtimecmph"
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read mtimecmp CPU "csr_mtimecmp"
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read mtimecmph CPU "csr_mtimecmph"
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op shl mtimecmph mtimecmph 32
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op add mtimecmp mtimecmp mtimecmph
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read instret CSRS "{{ 'instret'|csr }}"
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read instreth CSRS "{{ 'instreth'|csr }}"
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op shl instreth instreth 32
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op add instret instret instreth
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read minstret CPU "csr_minstret"
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read minstreth CPU "csr_minstreth"
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op shl minstreth minstreth 32
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op add minstret minstret minstreth
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read mstatus CSRS "{{ 'mstatus'|csr }}"
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read mstatus CPU "csr_mstatus"
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read mtvec CSRS "{{ 'mtvec'|csr }}"
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read mip CSRS "{{ 'mip'|csr }}"
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read mie CSRS "{{ 'mie'|csr }}"
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read mip CPU "csr_mip"
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read mie CPU "csr_mie"
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read mscratch CSRS "{{ 'mscratch'|csr }}"
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read mepc CSRS "{{ 'mepc'|csr }}"
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read mcause CSRS "{{ 'mcause'|csr }}"
@@ -367,14 +367,14 @@ loop__no_mark_icache:
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print "mtimecmp = {0}\n"
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format mtimecmp
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print "time = {0}\n"
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format time
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print "mtime = {0}\n"
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format mtime
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print "cycle = {0}\n"
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format cycle
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print "mcycle = {0}\n"
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format mcycle
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print "instret = {0}\n\n"
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format instret
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print "minstret = {0}\n\n"
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format minstret
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#{{'\n'}} {{ print(0, 17) }}
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‎src/init.mlog.jinja‎

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@@ -89,42 +89,37 @@ init_incr:
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# ISA ZYXWVUTSRQPONMLKJIHGFEDCBA
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write 0b01000000100100000001000100000001 CSRS "{{ 'misa'|csr }}"
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# mstatush
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# WPRI -------------------------- ----
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# MBE -
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# SBE -
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write 0b00000000000000000000000000000000 CSRS "{{ 'mstatush'|csr }}"
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# mlogv32 only has one hart, so mhartid is required to be zero
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write 0 CSRS "{{ 'mhartid'|csr }}"
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# unimplemented fields
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# unimplemented CSRs
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write 0 CSRS "{{ 'mvendorid'|csr }}"
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write 0 CSRS "{{ 'marchid'|csr }}"
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write 0 CSRS "{{ 'mimpid'|csr }}"
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# default values for writable CSRs
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write 0 CSRS "{{ 'mepc'|csr }}"
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write 0 CSRS "{{ 'mscratch'|csr }}"
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write 0 CSRS "{{ 'mie'|csr }}"
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write 0 CSRS "{{ 'mcause'|csr }}"
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write 0 CSRS "{{ 'mtval'|csr }}"
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# init UARTs
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write 0 UART0 {{UART_RX_RPTR}}
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write 0 UART0 {{UART_RX_WPTR}}
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write 0 UART0 {{UART_TX_RPTR}}
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write 0 UART0 {{UART_TX_WPTR}}
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write 0 UART1 {{UART_RX_RPTR}}
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write 0 UART1 {{UART_RX_WPTR}}
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write 0 UART1 {{UART_TX_RPTR}}
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write 0 UART1 {{UART_TX_WPTR}}
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write 0 UART2 {{UART_RX_RPTR}}
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write 0 UART2 {{UART_RX_WPTR}}
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write 0 UART2 {{UART_TX_RPTR}}
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write 0 UART2 {{UART_TX_WPTR}}
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write 0 UART3 {{UART_RX_RPTR}}
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write 0 UART3 {{UART_RX_WPTR}}
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write 0 UART3 {{UART_TX_RPTR}}
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write 0 UART3 {{UART_TX_WPTR}}
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write 0 UART0 {{UART_RX_READ}}
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write 0 UART0 {{UART_RX_WRITE}}
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write 0 UART0 {{UART_TX_READ}}
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write 0 UART0 {{UART_TX_WRITE}}
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write 0 UART1 {{UART_RX_READ}}
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write 0 UART1 {{UART_RX_WRITE}}
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write 0 UART1 {{UART_TX_READ}}
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write 0 UART1 {{UART_TX_WRITE}}
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write 0 UART2 {{UART_RX_READ}}
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write 0 UART2 {{UART_RX_WRITE}}
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write 0 UART2 {{UART_TX_READ}}
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write 0 UART2 {{UART_TX_WRITE}}
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write 0 UART3 {{UART_RX_READ}}
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write 0 UART3 {{UART_RX_WRITE}}
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write 0 UART3 {{UART_TX_READ}}
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write 0 UART3 {{UART_TX_WRITE}}
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setrate 1
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stop
@@ -150,8 +145,8 @@ set {{LOOKUP_PROC_SIZE}} null
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set {{ROM_PROC_BYTES}} null
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set {{RAM_PROC_BYTES}} null
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set {{RAM_PROC_VARS}} null
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set {{UART_RX_RPTR}} null
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set {{UART_RX_WPTR}} null
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set {{UART_TX_RPTR}} null
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set {{UART_TX_WPTR}} null
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set {{UART_RX_READ}} null
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set {{UART_RX_WRITE}} null
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set {{UART_TX_READ}} null
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set {{UART_TX_WRITE}} null
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# {% endraw %}

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