Tentatively implement Sv32 address translation (untested)

Author: object-Object

Makefile

@@ -15,6 +15,7 @@ rust: $(RUST_PROGRAMS)
 
 .PHONY: mlog
 mlog: $(MLOG_PROGRAMS) mlog-configs
+	poe build -s 16
 
 .PHONY: coremark
 coremark:

README.md

@@ -124,9 +124,9 @@ This non-standard extension adds instructions to control the mlogv32 processor's
 
 The MLOG instructions are encoded with an I-type instruction format using the _custom-0_ opcode. The zero-extended immediate is used as a minor opcode (funct12) for implementation reasons.
 
-The MLOGSYS instruction is used for simple system controls, currently only including icache initialization.
+The MLOGSYS instruction is used for simple system controls.
 
-The `mlogsys.icache` instruction uses register _rs1_ as the number of bytes to decode. This can be generated by using a linker script to find the end address of the `.text` section and load it using `li`. The actual number of bytes decoded will be the smallest of _rs1_, the size of the icache, and the size of ROM.
+The `mlogsys.icache` M-mode instruction uses register _rs1_ as the number of bytes to decode. This can be generated by using a linker script to find the end address of the `.text` section and load it using `li`. The actual number of bytes decoded will be the smallest of _rs1_, the size of the icache, and the size of ROM.
 
 | funct12 | rs1    | name                  |
 | ------- | ------ | --------------------- |

pyproject.toml

@@ -86,7 +86,7 @@ exclude = [
     "**/__pycache__",
 ]
 
-typeCheckingMode = "basic"
+typeCheckingMode = "standard"
 
 strictDictionaryInference = true
 strictListInference = true

python/src/mlogv32/preprocessor/app.py

@@ -21,7 +21,13 @@
 )
 from .filters import FILTERS
 from .models import BuildConfig
-from .parser import check_unsaved_variables, iter_labels, parse_mlog
+from .parser import (
+    AssertCounterError,
+    Statement,
+    check_unsaved_variables,
+    iter_labels,
+    parse_mlog,
+)
 
 app = Typer(
     pretty_exceptions_show_locals=False,
@@ -135,8 +141,20 @@ def build(
     print(f"Local variable count: {i}")
 
     worker_ast = parse_mlog(worker_code)
+
     check_unsaved_variables(worker_ast)
-    worker_labels = dict(iter_labels(worker_ast))
+    print(
+        f"""\
+Code size:
+  Instructions: {len(list(n for n in worker_ast if isinstance(n, Statement)))} / 1000
+  Bytes: {len(worker_code.encode())} / {1024 * 100}"""
+    )
+
+    try:
+        worker_labels = dict(iter_labels(worker_ast))
+    except AssertCounterError as e:
+        e.add_note(f"{worker_output}:{e.token.line}")
+        raise
 
     controller_output = get_template_output_path(config.templates.controller)
     controller_code = render_template(

python/src/mlogv32/preprocessor/filters.py

@@ -2,6 +2,7 @@
 from typing import Any, Callable
 
 from jinja2.runtime import Context
+from jinja2.utils import Namespace
 
 from mlogv32.scripts.ram_proc import VariableFormat
 
@@ -69,6 +70,14 @@ def memory_size(size: int):
     return hex(size)
 
 
+@make_jinja_exceptions_suck_a_bit_less
+@register_filter
+def namespace_dict(namespace: Namespace):
+    # cursed
+    attrs: dict[str, Any] = namespace._Namespace__attrs
+    return attrs
+
+
 CSRS: dict[str, int] = {
     # unprivileged
     "cycle": 0xC00,

python/src/mlogv32/preprocessor/models.py

@@ -6,7 +6,7 @@
 from typing import Annotated
 
 import yaml
-from pydantic import AfterValidator, BaseModel
+from pydantic import AfterValidator, BaseModel, Field, field_validator
 
 _relative_path_root_var = ContextVar[Path]("_relative_path_root_var")
 
@@ -41,6 +41,31 @@ class Schematics(BaseModel):
 
     class Instruction(BaseModel):
         label: str
+        count: int = Field(default=1, ge=1)
+        up_to: int | None = None
+
+    @field_validator("instructions", mode="after")
+    @classmethod
+    def _resolve_instructions(cls, instructions: list[Instruction]):
+        result = list[BuildConfig.Instruction]()
+        address = 0
+
+        for i, value in enumerate(instructions):
+            if value.up_to is not None:
+                value = value.model_copy()
+                assert value.up_to is not None
+
+                if value.up_to < address:
+                    raise ValueError(
+                        f"Instruction {i} is at address {address}, but up_to is {value.up_to}: {value}"
+                    )
+
+                value.count = value.up_to - address + 1
+
+            result.append(value)
+            address += value.count
+
+        return result
 
     @classmethod
     def load(cls, path: str | Path):

python/src/mlogv32/preprocessor/parser/__init__.py

@@ -1,9 +1,19 @@
 __all__ = [
+    "AssertCounterError",
+    "Directive",
     "Label",
     "Statement",
     "check_unsaved_variables",
     "iter_labels",
     "parse_mlog",
 ]
 
-from .mlog import Label, Statement, check_unsaved_variables, iter_labels, parse_mlog
+from .mlog import (
+    AssertCounterError,
+    Directive,
+    Label,
+    Statement,
+    check_unsaved_variables,
+    iter_labels,
+    parse_mlog,
+)

python/src/mlogv32/preprocessor/parser/mlog.lark

@@ -6,7 +6,7 @@ start: (line? _NEWLINE)*
 
 statement: TOKEN (TOKEN | LABEL | STRING)*
 
-directive: _DIRECTIVE TOKEN+
+directive: _DIRECTIVE /assert_counter|(begin|end)_fetch|(push|pop)_saved/ TOKEN*
 
 STRING.2: /"[^\n]*"/
 

python/src/mlogv32/preprocessor/parser/mlog.py

@@ -17,19 +17,19 @@ def v_args[T](
 
 @dataclass
 class Label:
-    name: str
+    name: Token
 
 
 @dataclass
 class Statement:
-    name: str
-    args: list[str]
+    name: Token
+    args: list[Token]
 
 
 @dataclass
 class Directive:
-    name: str
-    args: list[str]
+    name: Token
+    args: list[Token]
 
 
 type ASTNode = Label | Statement | Directive
@@ -41,18 +41,15 @@ class MlogTransformer(Transformer[Token, list[ASTNode]]):
     def start(self, *children: ASTNode):
         return list(children)
 
-    def label(self, name: str):
-        return Label(name[:-1])
+    def label(self, name: Token):
+        return Label(name.update(value=name[:-1]))
 
-    def statement(self, name: str, *args: str):
+    def statement(self, name: Token, *args: Token):
         return Statement(name, list(args))
 
-    def directive(self, name: str, *args: str):
+    def directive(self, name: Token, *args: Token):
         return Directive(name, list(args))
 
-    def TOKEN(self, token: Token):
-        return str(token)
-
 
 GRAMMAR = (resources.files() / "mlog.lark").read_text("utf-8")
 
@@ -68,18 +65,25 @@ def parse_mlog(text: str):
     return MlogTransformer().transform(tree)
 
 
+class AssertCounterError(AssertionError):
+    def __init__(self, message: str, token: Token, *args: object) -> None:
+        super().__init__(message, *args)
+        self.token = token
+
+
 def iter_labels(ast: Iterable[ASTNode]) -> Iterator[tuple[str, int]]:
-    line_num = 0
+    counter = 0
     for node in ast:
         match node:
             case Label(name=name):
-                yield (name, line_num)
+                yield (name, counter)
             case Statement():
-                line_num += 1
-            case Directive(name="assert_line", args=[n]):
-                assert line_num == int(n), (
-                    f"Expected next line to be {n}, but got {line_num}"
-                )
+                counter += 1
+            case Directive(name="assert_counter", args=[n]):
+                if counter != int(n):
+                    raise AssertCounterError(
+                        f"Expected @counter to be {n}, but got {counter}", node.name
+                    )
             case Directive():
                 pass
 

riscof/mlogv32/env/reloc.ld

@@ -2,8 +2,8 @@ OUTPUT_ARCH( "riscv" )
 ENTRY(rvtest_entry_point)
 
 MEMORY {
-    ROM (rx)  : ORIGIN = 0x00000000, LENGTH = 0x480000
-    RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 0x480000
+    ROM (rx)  : ORIGIN = 0x00000000, LENGTH = 18M
+    RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 18M
 }
 
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