Finish implementing accumulator tracking

Author: object-Object

README.md

@@ -125,6 +125,8 @@ The MLOGSYS instruction is used for simple system controls, including `printchar
 
 The `mlogsys.icache` instruction uses register _rs1_ as the number of bytes to decode. This can be generated by using a linker script to find the end address of the `.text` section and load it using `li`. The actual number of bytes decoded will be the smallest of _rs1_, the size of the icache, and the size of ROM.
 
+FIXME: `printflush` and `drawflush` are broken with subframe :(
+
 | funct12 | rs1     | name                  |
 | ------- | ------- | --------------------- |
 | 0       | length  | Initialize ROM icache |

coremark/mlogv32/ee_printf.c

@@ -660,22 +660,43 @@ ee_vsprintf(char *buf, const char *fmt, va_list args)
     return str - buf;
 }
 
-static unsigned int print_x = 7;
-static unsigned int print_y = 508;
+typedef struct {
+    unsigned char rhr_thr[4];
+    unsigned char ier[4];
+    unsigned char isr_fcr[4];
+    unsigned char lcr[4];
+    unsigned char mcr[4];
+    unsigned char lsr[4];
+    unsigned char msr[4];
+    unsigned char spr[4];
+} uart_mmio_t;
+
+#define UART0_BASE ((volatile uart_mmio_t*)(0xf0000010))
+
+#define UART_FIFO_CAPACITY 253
+
+static unsigned int uart0_fifo_size = 0;
 
 void
 uart_send_char(char c)
 {
-    MLOGSYS_printchar(c);
+    volatile uart_mmio_t* uart0 = UART0_BASE;
+
+    if (uart0_fifo_size >= UART_FIFO_CAPACITY) {
+        while ((uart0->lsr[0] & 0b1100000) != 0b1100000) {}
+        uart0_fifo_size = 0;
+    }
+
+    uart0->rhr_thr[0] = c;
+    uart0_fifo_size += 1;
 }
 
 void init_printf() {
-    print_x = 7;
-    print_y = 508;
-    MLOGDRAW_reset();
-    MLOGDRAW_clear(0, 0, 0);
-    MLOGDRAW_color(255, 255, 255, 255);
-    MLOGSYS_drawflush();
+    volatile uart_mmio_t* uart0 = UART0_BASE;
+    uart0->isr_fcr[0] = 0b00000111;
+    while (uart0->lsr[0] & 0b1) {
+        uart0->isr_fcr[0] = 0b00000111;
+    }
 }
 
 int
@@ -685,33 +706,16 @@ ee_printf(const char *fmt, ...)
     va_list args;
     int     n = 0;
 
-    int old_print_x = print_x;
-    int old_print_y = print_y;
-
     va_start(args, fmt);
     ee_vsprintf(buf, fmt, args);
     va_end(args);
     p = buf;
     while (*p)
     {
-        if (*p == '\n') {
-            print_x = 7;
-            print_y -= 13;
-        } else {
-            print_x += 7;
-            if (print_x > 504) {
-                uart_send_char('\n');
-                print_x = 7;
-                print_y -= 13;
-            }
-        }
         uart_send_char(*p);
         n++;
         p++;
     }
 
-    MLOGDRAW_print(old_print_x, old_print_y);
-    MLOGSYS_drawflush();
-
     return n;
 }

mod/src/main/kotlin/gay/object/mlogv32/ProcessorAccess.kt

@@ -40,9 +40,13 @@ class ProcessorAccess(
     uartFifoModulo: Int,
     uart0: MemoryBuild,
     uart1: MemoryBuild,
+    uart2: MemoryBuild,
+    uart3: MemoryBuild,
 ) {
     val uart0 = UartAccess(uart0, uartFifoModulo - 1)
     val uart1 = UartAccess(uart1, uartFifoModulo - 1)
+    val uart2 = UartAccess(uart2, uartFifoModulo - 1)
+    val uart3 = UartAccess(uart3, uartFifoModulo - 1)
 
     val romEnd = ROM_START + romSize.toUInt()
     val ramEnd = RAM_START + ramSize.toUInt()
@@ -261,6 +265,8 @@ class ProcessorAccess(
                 uartFifoModulo = positiveIntVar(build, "UART_FIFO_MODULO") ?: return null,
                 uart0 = buildVar<MemoryBuild>(build, "bank1") ?: return null,
                 uart1 = buildVar<MemoryBuild>(build, "bank2") ?: return null,
+                uart2 = buildVar<MemoryBuild>(build, "bank3") ?: return null,
+                uart3 = buildVar<MemoryBuild>(build, "bank4") ?: return null,
             )
         }
 
@@ -383,6 +389,8 @@ data class WaitRequest(
 enum class UartDevice {
     uart0,
     uart1,
+    uart2,
+    uart3,
 }
 
 @Serializable
@@ -396,6 +404,8 @@ data class SerialRequest(
         val uart = when (device) {
             UartDevice.uart0 -> processor.uart0
             UartDevice.uart1 -> processor.uart1
+            UartDevice.uart2 -> processor.uart2
+            UartDevice.uart3 -> processor.uart3
         }
         while (true) {
             if (rx.isClosedForRead || tx.isClosedForWrite) {
@@ -476,9 +486,9 @@ data object StatusRequest : Request() {
             mepc = processor.getCSR(0x341),
             mcause = processor.getCSR(0x342),
             mtval = processor.getCSR(0x343),
-            mstatus = processor.getCSR(0x300),
-            mip = processor.getCSR(0x344),
-            mie = processor.getCSR(0x304),
+            mstatus = processor.build.executor.optionalVar("csr_mstatus")?.numu() ?: 0u,
+            mip = processor.build.executor.optionalVar("csr_mip")?.numu() ?: 0u,
+            mie = processor.build.executor.optionalVar("csr_mie")?.numu() ?: 0u,
         )
     }
 }

python/src/mlogv32/preprocessor/app.py

@@ -123,37 +123,34 @@ def build(
         for y in lenrange(0, 16):
             schem.add_block(simple_block(BEContent.TILE_LOGIC_DISPLAY, x, y))
 
-    display_link = ProcessorLink(0, 0, "display1")
+    display_link = ProcessorLink(0, 0, "")
 
     schem.add_schem(lookups_schem, 0, 16)
-    lookup_links = [
-        ProcessorLink(x=i % 4, y=16 + i // 4, name=f"processor{i + 1}")
-        for i in range(16)
-    ]
+    lookup_links = [ProcessorLink(x=i % 4, y=16 + i // 4, name="") for i in range(16)]
 
     add_label(schem, 4, 19, right="UART0, UART2", down="LABELS")
     schem.add_block(simple_block(Content.WORLD_CELL, 4, 18))
     schem.add_block(simple_block(Content.WORLD_CELL, 4, 17))
     add_label(schem, 4, 16, up="COSTS", right="UART1, UART3")
 
-    labels_link = ProcessorLink(4, 18, "cell1")
-    costs_link = ProcessorLink(4, 17, "cell2")
+    labels_link = ProcessorLink(4, 18, "")
+    costs_link = ProcessorLink(4, 17, "")
 
     uart_links = list[ProcessorLink]()
     for x in lenrange(5, 4, 2):
         for y in lenrange(18, -4, -2):
             schem.add_block(simple_block(Content.MEMORY_BANK, x, y))
-            uart_links.append(ProcessorLink(x, y, f"bank{len(uart_links) + 1}"))
+            uart_links.append(ProcessorLink(x, y, ""))
 
     schem.add_block(simple_block(Content.MEMORY_CELL, 9, 19))
     schem.add_schem(ram_schem, 9, 18)
     schem.add_schem(ram_schem, 9, 17)
     schem.add_block(Block(Content.MICRO_PROCESSOR, 9, 16, ProcessorConfig("", []), 0))
 
-    registers_link = ProcessorLink(9, 19, "cell3")
-    csrs_link = ProcessorLink(9, 18, "processor17")
-    incr_link = ProcessorLink(9, 17, "processor18")
-    config_link = ProcessorLink(9, 16, "processor19")
+    registers_link = ProcessorLink(9, 19, "")
+    csrs_link = ProcessorLink(9, 18, "")
+    incr_link = ProcessorLink(9, 17, "")
+    config_link = ProcessorLink(9, 16, "")
 
     add_with_label(
         schem,
@@ -180,10 +177,10 @@ def build(
         right="SINGLE_STEP_SWITCH",
     )
 
-    error_output_link = ProcessorLink(11, 19, "message1")
-    power_switch_link = ProcessorLink(11, 18, "switch2")
-    pause_switch_link = ProcessorLink(11, 17, "switch3")
-    single_step_switch_link = ProcessorLink(11, 16, "switch1")
+    error_output_link = ProcessorLink(11, 19, "")
+    power_switch_link = ProcessorLink(11, 18, "")
+    pause_switch_link = ProcessorLink(11, 17, "")
+    single_step_switch_link = ProcessorLink(11, 16, "")
 
     # hack
     if cpu_only:
@@ -199,15 +196,16 @@ def build(
                 links=relative_links(
                     *lookup_links,
                     *uart_links,
+                    registers_link,
                     labels_link,
                     costs_link,
                     csrs_link,
                     incr_link,
                     config_link,
                     error_output_link,
-                    single_step_switch_link,
                     power_switch_link,
                     pause_switch_link,
+                    single_step_switch_link,
                     display_link,
                     x=16,
                     y=0,
@@ -217,7 +215,7 @@ def build(
         )
     )
 
-    controller_link = ProcessorLink(16, 0, "processor20")
+    controller_link = ProcessorLink(16, 0, "")
 
     for x in lenrange(16, width):
         for y in lenrange(0, height):
@@ -235,9 +233,9 @@ def build(
                         links=relative_links(
                             *lookup_links,
                             *uart_links,
+                            registers_link,
                             labels_link,
                             costs_link,
-                            registers_link,
                             csrs_link,
                             incr_link,
                             config_link,
@@ -253,8 +251,6 @@ def build(
                 )
             )
 
-    schem.set_tag("name", "mlogv32")
-
     if output:
         schem.write_file(str(output))
     else:

python/src/mlogv32/preprocessor/models.py

@@ -3,10 +3,10 @@
 from contextlib import contextmanager
 from contextvars import ContextVar
 from pathlib import Path
-from typing import Annotated
+from typing import Annotated, Any
 
 import yaml
-from pydantic import AfterValidator, BaseModel, Field
+from pydantic import AfterValidator, BaseModel, Field, field_validator
 
 _relative_path_root_var = ContextVar[Path]("_relative_path_root_var")
 
@@ -42,6 +42,13 @@ class Instruction(BaseModel):
         label: str
         cost: int = Field(ge=0)
 
+        @field_validator("cost", mode="before")
+        @classmethod
+        def _resolve_cost_math(cls, value: Any):
+            if isinstance(value, str):
+                return eval(value)  # CURSED
+            return value
+
     @classmethod
     def load(cls, path: str | Path):
         path = Path(path).resolve()

riscof/mlogv32/riscof_mlogv32.py

@@ -123,6 +123,8 @@ def runTests(self, testlist: dict[str, Any]):
             # we will iterate over each entry in the testlist. Each entry node will be refered to by the
             # variable testname.
             for testname in testlist:
+                logger.info(f"Building test: {testname}")
+
                 # for each testname we get all its fields (as described by the testlist format)
                 testentry = testlist[testname]
 
@@ -219,7 +221,7 @@ def runTests(self, testlist: dict[str, Any]):
                     f"{begin_signature=:#x} {end_signature=:#x} {signature_length=}"
                 )
 
-                logger.info(f"Starting test: {testname}")
+                logger.info(f"Running test: {testname}")
 
                 processor.stop()
                 processor.flash(binary_file_host)

src/config/configs.yaml

@@ -7,8 +7,8 @@ defaults:
 
 configs:
   riscv-arch-test:
-    MEMORY_X_OFFSET: -11
-    MEMORY_Y_OFFSET: -26
+    MEMORY_X_OFFSET: -9
+    MEMORY_Y_OFFSET: -40
     MEMORY_WIDTH: 32
     ROM_ROWS: 9
     RAM_ROWS: 9