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Add trap test
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Makefile

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@@ -46,7 +46,7 @@ build/%.out: build/%.o
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riscv32-unknown-elf-ld --script=rust/mlogv32/link.x -o build/$*.out build/$*.o
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build/%.o: asm/%.s | build
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riscv32-unknown-elf-gcc --compile -o build/$*.o asm/$*.s
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riscv32-unknown-elf-gcc --compile -march=rv32ima_zicsr -o build/$*.o asm/$*.s
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src/%.mlog: src/%.mlog.jinja
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python -m mlogv32.preprocessor -o src/$*.mlog src/$*.mlog.jinja

asm/trap.s

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@@ -0,0 +1,14 @@
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.global _start
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_start:
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la t0, trap
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csrw mtvec, t0
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ecall
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.insn i CUSTOM_0, 0, zero, zero, 0 # halt
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trap:
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csrr t0, mepc
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addi t0, t0, 4
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csrw mepc, t0
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mret

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