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Change mtime frequency from 1 ms to 1 μs
1 parent 1d0a019 commit 5d195ef

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-7
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7 files changed

+8
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README.md

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@@ -43,7 +43,7 @@ Addresses `0xf0000000` - `0xffffffff` are reserved for system purposes such as M
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### Machine Timers
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The `mtime` and `mtimecmp` registers are mapped to `0xf0000000` and `0xf0000008` respectively, and have a period of 1 ms. The timer registers are not accessible to privilege modes lower than M-mode.
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The `mtime` and `mtimecmp` registers are mapped to `0xf0000000` and `0xf0000008` respectively, and have a period of 1 μs. The timer registers are not accessible to privilege modes lower than M-mode.
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### UART
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@@ -151,7 +151,7 @@ The `[m]cycle[h]` counter is incremented at the start of each worker's tick, jus
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### `time`
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The `[m]time[h]` counter is based on the `@time` value in Mindustry. It has a period of 1 ms, and is incremented once per tick by the controller based on the time delta since the previous tick.
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The `[m]time[h]` counter is based on the `@time` value in Mindustry. It has a period of 1 μs, and is incremented once per tick by the controller based on the time delta since the previous tick.
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## riscv-arch-test
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coremark/mlogv32/core_portme.c

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@@ -57,7 +57,7 @@ barebones_clock()
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does not occur. If there are issues with the return value overflowing,
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increase this value.
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*/
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#define CLOCKS_PER_SEC 1000
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#define CLOCKS_PER_SEC 1000000
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#define GETMYTIME(_t) (*_t = barebones_clock())
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#define MYTIMEDIFF(fin, ini) ((fin) - (ini))
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#define TIMER_RES_DIVIDER 1
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linux/buildroot/board/mlogv32/dts/mlogv32.dts

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@@ -41,7 +41,7 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000>;
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timebase-frequency = <1000000>;
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cpu@0 {
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device_type = "cpu";

linux/buildroot/opensbi/platform/mlogv32/platform.c

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@@ -19,7 +19,7 @@
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#include <sbi_utils/serial/xlnx_uartlite.h>
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#include <sbi_utils/timer/aclint_mtimer.h>
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#define MLOGV32_MTIME_FREQ 1000
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#define MLOGV32_MTIME_FREQ 1000000
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#define MLOGV32_MTIME_ADDR 0xf0000000
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#define MLOGV32_MTIME_SIZE 0x8
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#define MLOGV32_MTIMECMP_ADDR 0xf0000008

rust/examples/timer/src/main.rs

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@@ -25,7 +25,7 @@ fn main() -> ! {
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let mut timer = TIMER.borrow_ref_mut(cs);
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timer.write_mtime(0);
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timer.write_mtimecmp(1000);
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timer.write_mtimecmp(1_000_000);
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});
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unsafe {
@@ -43,7 +43,7 @@ fn machine_timer() {
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critical_section::with(|cs| {
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let mut timer = TIMER.borrow_ref_mut(cs);
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let mtime = timer.read_mtime();
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timer.write_mtimecmp(mtime + 1000);
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timer.write_mtimecmp(mtime + 1_000_000);
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let mut uart0 = UART0.borrow_ref_mut(cs);
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let uart0 = uart0.as_mut().unwrap();

src/cpu/controller.mlog.jinja

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@@ -297,6 +297,7 @@ end_breakpoint:
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# TODO: handle mtimeh overflow
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op sub delta_ms @time last_mtime_update
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op mul delta_ms delta_ms 1000 # ms -> μs
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op add csr_mtime csr_mtime delta_ms
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op floor csr_mtime csr_mtime

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