Skip to content

Commit 66c2422

Browse files
committed
Remove old init/main files
1 parent 4bfc1b9 commit 66c2422

File tree

4 files changed

+1
-2413
lines changed

4 files changed

+1
-2413
lines changed

README.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ Instructions are cached in the following format, utilizing the full 54 bits of `
1616
| ----------------- | ----- | ----- | ----- | ---- |
1717
| op_id (-64 to 63) | rs2 | rs1 | rd | imm |
1818

19-
The main CPU code is generated from `src/main.mlog.jinja` using a custom Jinja-based preprocessor (`python/src/mlogv32/preprocessor`).
19+
The CPU is implemented using a variable-size build-order-independent subframe architecture. There is one controller processor (`src/cpu/controller.mlog.jinja`) and an arbitrary number of worker processors (`src/cpu/worker.mlog.jinja`). Schematics are generated using a custom preprocessor (`python/src/mlogv32/preprocessor`) based on Jinja and pymsch.
2020

2121
## Memory
2222

src/init.mlog.jinja

Lines changed: 0 additions & 152 deletions
This file was deleted.

src/main.constants.jinja

Lines changed: 0 additions & 38 deletions
This file was deleted.

0 commit comments

Comments
 (0)