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Physical memory consists of three sections. Two are directly accessible by code: ROM (rx) and RAM (rwx). The third section is an instruction cache which is 4x less dense than main memory.
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Physical memory consists of three sections. Two are directly accessible by code: ROM (rx) and RAM (rwx). The third section is an instruction cache, which sits directly after RAM and uses the same processor layout to store partially decoded instructions.
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For maximum performance, the instruction cache for ROM can be initialized at boot using the MLOGSYS instruction. It is also updated whenever an instruction writes to RAM that is covered by the icache. If executing from memory not covered by the icache, the processor manually fetches and decodes the instruction from main memory.
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Instructions are cached in the following format, utilizing the full 54 bits of `double` precision ([53 mantissa](https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Global_Objects/Number/MAX_SAFE_INTEGER), 1 sign).
Copy file name to clipboardExpand all lines: src/config/base.mlog.jinja
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set ROM_SIZE {{# '%#0x'|format(ROM_ROWS * MEMORY_WIDTH * 16384) }} # ROM size in bytes (rx)
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set RAM_SIZE {{# '%#0x'|format(RAM_ROWS * MEMORY_WIDTH * 16384) }} # RAM size in bytes (rwx)
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set ICACHE_SIZE {{# '%#0x'|format(ICACHE_ROWS * MEMORY_WIDTH * 4096) }} # icache size in variables, or bytes of memory it can represent; 4x less dense than ROM/RAM
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set ICACHE_SIZE {{# '%#0x'|format(ICACHE_ROWS * MEMORY_WIDTH * 16384) }} # icache size in bytes
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set UART_FIFO_CAPACITY {{#UART_FIFO_CAPACITY}} # UART TX/RX FIFO capacity in bytes (max 253)
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