Skip to content

Commit 857572f

Browse files
committed
Add support for generating ROM without using mlogv32-utils
1 parent 7590fbb commit 857572f

File tree

2 files changed

+56
-5
lines changed

2 files changed

+56
-5
lines changed

python/src/mlogv32/preprocessor/app.py

Lines changed: 29 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,10 @@
1010
from pymsch import Block, Content, ProcessorConfig, ProcessorLink, Schematic
1111
from typer import Option, Typer
1212

13-
from mlogv32.utils.msch import BEContent
13+
from mlogv32.utils.msch import (
14+
BEContent,
15+
ProcessorConfigUTF8,
16+
)
1417

1518
from .extensions import (
1619
CommentStatement,
@@ -96,6 +99,7 @@ def build(
9699
height: Annotated[int, Option("-h", "--height")] = 16,
97100
size: Annotated[int | None, Option("-s", "--size")] = None,
98101
output: Annotated[Path | None, Option("-o", "--output")] = None,
102+
bin_path: Annotated[Path | None, Option("--bin")] = None,
99103
include_all: Annotated[bool, Option("--all")] = False,
100104
include_cpu: Annotated[bool, Option("--cpu")] = False,
101105
include_peripherals: Annotated[bool, Option("--peripherals")] = False,
@@ -257,8 +261,6 @@ def _render_template(
257261

258262
display_code, _, _ = _render_template(config.templates.display)
259263

260-
rom_code = 'set v ""; stop'
261-
262264
# load schematics
263265

264266
lookups_schem = Schematic.read_file(str(config.schematics.lookups))
@@ -479,6 +481,15 @@ def add_with_label(block: Block, **labels: Unpack[Labels]):
479481

480482
# memory
481483
if include_memory:
484+
i = 0
485+
if bin_path:
486+
data = bin_path.read_bytes()
487+
if len(data) % 4 != 0:
488+
print("[WARNING] Bin is not aligned to 4 bytes, appending zeros.")
489+
data += bytes([0, 0, 0, 0])[: len(data) % 4]
490+
else:
491+
data = bytes()
492+
482493
base_y = config_link.y + config_args["MEMORY_Y_OFFSET"]
483494
for y in lenrange(
484495
0,
@@ -491,18 +502,32 @@ def add_with_label(block: Block, **labels: Unpack[Labels]):
491502
config_args["MEMORY_WIDTH"],
492503
):
493504
if y < config_args["ROM_ROWS"]:
505+
if i < len(data):
506+
payload = "".join(chr(174 + c) for c in data[i : i + 16384])
507+
i += 16384
508+
else:
509+
payload = ""
510+
494511
schem.add_block(
495512
Block(
496513
block=Content.MICRO_PROCESSOR,
497514
x=x,
498515
y=base_y + y,
499-
config=ProcessorConfig(rom_code, []),
516+
config=ProcessorConfigUTF8(
517+
code=f'set v "{payload}"; stop',
518+
links=[],
519+
).compress(),
500520
rotation=0,
501521
)
502522
)
503523
else:
504524
schem.add_schem(ram_schem, x, base_y + y)
505525

526+
if i < len(data):
527+
print(
528+
f"[WARNING] Bin is too large to fit into the generated ROM ({len(data) - i} bytes overflowed)."
529+
)
530+
506531
# debugger
507532

508533
if include_debugger:

python/src/mlogv32/utils/msch.py

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,33 @@
1+
import zlib
12
from enum import Enum
3+
from typing import override
24

3-
from pymsch import ContentBlock
5+
from pymsch import (
6+
ContentBlock,
7+
ProcessorConfig,
8+
_ByteBuffer, # pyright: ignore[reportPrivateUsage]
9+
)
410

511

612
class BEContent(Enum):
713
TILE_LOGIC_DISPLAY = ContentBlock(415, 1)
14+
15+
16+
class ProcessorConfigUTF8(ProcessorConfig):
17+
@override
18+
def compress(self):
19+
buffer = _ByteBuffer()
20+
21+
buffer.writeByte(1)
22+
23+
code = self.code.encode("utf-8")
24+
buffer.writeInt(len(code))
25+
buffer.data.extend(code)
26+
27+
buffer.writeInt(len(self.links))
28+
for link in self.links:
29+
buffer.writeUTF(link.name)
30+
buffer.writeShort(link.x)
31+
buffer.writeShort(link.y)
32+
33+
return bytearray(zlib.compress(buffer.data))

0 commit comments

Comments
 (0)