Add bitmask field to CSR label lookup

Author: object-Object

python/src/mlogv32/preprocessor/filters.py

@@ -85,6 +85,14 @@ def hex_filter(n: int):
     return hex(n)
 
 
+@make_jinja_exceptions_suck_a_bit_less
+@register_filter("bin")
+def bin_filter(n: int, bits: int | None = None):
+    if bits:
+        return f"{n:#0{bits + 2}b}"
+    return bin(n)
+
+
 @make_jinja_exceptions_suck_a_bit_less
 @register_filter()
 def namespace_dict(namespace: Namespace):

python/src/mlogv32/preprocessor/models.py

@@ -59,6 +59,7 @@ class Instruction(BaseModel):
     class CSR(BaseModel):
         read: CSRLocation
         write: CSRLocation | None = None
+        mask: int = Field(default=0xFFFF_FFFF, ge=0, le=0xFFFF_FFFF)
         args: Iterable[Any] | None = None
 
     @field_validator("instructions", mode="after")

src/cpu/controller.mlog.jinja

@@ -139,10 +139,11 @@ init_labels__loop{{ns.loop}}:
 #% for name, csr in csrs.items()
 #% set read_label = 'csr_read_' ~ csr.read
 #% set write_label = 'csr_write_' ~ csr.write if csr.write is not none else 'ILLEGAL_OP'
-#% set value = labels[read_label] * 1000 + labels[write_label]
+#% set value = csr.mask * 1_000_000 + labels[write_label] * 1000 + labels[read_label]
     # {{ name }}
     # read: {{ read_label }} ({{ labels[read_label] }})
     # write: {{ write_label }} ({{ labels[write_label] }})
+    # mask: {{ csr.mask|bin(32) }}
     write {{value}} {{CSR_LABELS}} "{{ name|csr }}"
 #% endfor
 

src/cpu/cpu.yaml

@@ -193,12 +193,23 @@ csrs:
   sstatus:
     read: LABEL
     write: LABEL
+    # MXR               -
+    # SUM                -
+    # SPP                          -
+    # SPIE                            -
+    # SIE                                 -
+    mask: 0b00000000000011000000000100100010
   sie:
     read: LABEL
     write: LABEL
+    # SEIE                        -
+    # STIE                            -
+    # SSIE                                -
+    mask: 0b00000000000000000000001000100010
   stvec:
     read: csrs
-    write: csrs_align_4B
+    write: csrs
+    mask: &align_4B 0xfffffffc
   scounteren:
     read: csrs
     write: csrs
@@ -225,7 +236,8 @@ csrs:
     write: csrs
   sepc:
     read: csrs
-    write: csrs_align_4B
+    write: csrs
+    mask: *align_4B
   scause:
     read: csrs
     write: csrs
@@ -235,6 +247,8 @@ csrs:
   sip:
     read: LABEL
     write: LABEL
+    # SSIP                                -
+    mask: 0b00000000000000000000000000000010
 
   # protection and translation
   satp:
@@ -259,21 +273,37 @@ csrs:
   mstatus:
     read: LABEL
     write: LABEL
+    # state  -              ----  --
+    # WPRI    --------                  - - -
+    # UBE                             -
+    mask:  0b00000000011111100001100110101010
   misa:
     read: csrs
     write: readonly
   medeleg:
     read: csrs
-    write: LABEL
+    write: csrs
+    # custom    --------
+    # reserved          ----  -- -   -
+    # M-call                        -
+    mask:     0b00000000000011001011001111111111
   mideleg:
     read: csrs
-    write: LABEL
+    write: csrs
+    # MEI                       -
+    # SEI                         -
+    # MTI                           -
+    # STI                             -
+    # MSI                               -
+    # SSI                                 -
+    mask: 0b00000000000000000000101010101010
   mie:
     read: LABEL
     write: LABEL
   mtvec:
     read: csrs
-    write: csrs_align_4B
+    write: csrs
+    mask: *align_4B
   mcounteren:
     read: csrs
     write: csrs
@@ -290,7 +320,8 @@ csrs:
     write: csrs
   mepc:
     read: csrs
-    write: csrs_align_4B
+    write: csrs
+    mask: *align_4B
   mcause:
     read: csrs
     write: csrs
@@ -300,6 +331,9 @@ csrs:
   mip:
     read: LABEL
     write: LABEL
+    # SEIP                        -
+    # SSIP                                -
+    mask: 0b00000000000000000000001000000010
 
   # configuration
   menvcfg: