Relocate all Sv32 tests to RAM

Author: object-Object

riscof/config.ini

@@ -11,7 +11,7 @@ pspec=./mlogv32/mlogv32_platform.yaml
 target_run=1
 jobs=8
 skip_tests=
-reloc_tests=/Zifencei/src/Fencei.S,/pmp32/
+reloc_tests=/Zifencei/src/Fencei.S,/pmp32/,/vm_sv32/
 # change these when running the tests on another computer (FIXME: hack)
 host_repo_path=/Users/object/Git/mlogv32
 riscof_repo_path=/workspaces/mlogv32

riscof/mlogv32/env/reloc.ld

@@ -3,7 +3,7 @@ ENTRY(rvtest_entry_point)
 
 MEMORY {
     ROM (rx)  : ORIGIN = 0x00000000, LENGTH = 18M
-    RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 18M
+    RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 21M
 }
 
 SECTIONS

riscof/mlogv32/env/xip.ld

@@ -3,7 +3,7 @@ ENTRY(rvtest_entry_point)
 
 MEMORY {
     ROM (rx)  : ORIGIN = 0x00000000, LENGTH = 18M
-    RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 18M
+    RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 21M
 }
 
 __stext = 0;

riscof/mlogv32/riscof_mlogv32.py

@@ -83,7 +83,7 @@ def initialise(self, suite: str, workdir: str, env: str):
         # runTests function
         self.compile_cmd = (
             "riscv{xlen}-unknown-elf-gcc -march={isa} \
- -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g\
+ -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles\
  -D 'MLOGV32_TEST_NAME=\"{test_name}\"'\
  -T "
             + self.pluginpath
@@ -239,7 +239,8 @@ def get_compile_command(self, testlist: dict[str, Any], testname: str):
             for cmd in [
                 compile_cmd,
                 objcopy_cmd,
-                objdump_cmd,
+                # comment out objdump command to make the tests run faster
+                "#" + objdump_cmd,
             ]
         )
 

riscof/sail_cSim/riscof_sail_cSim.py

@@ -125,7 +125,7 @@ def runTests(self, testList, cgf_file=None, header_file=None):
 
             elf = "ref.elf"
 
-            execute = "@cd " + testentry["work_dir"] + ";"
+            execute = ""
 
             cmd = (
                 self.compile_cmd.format(testentry["isa"].lower(), self.xlen)
@@ -137,7 +137,8 @@ def runTests(self, testList, cgf_file=None, header_file=None):
             compile_cmd = cmd + " -D" + " -D".join(testentry["macros"])
             execute += compile_cmd + ";"
 
-            execute += self.objdump_cmd.format(elf, self.xlen, "ref.dump")
+            # comment out objdump command to make the tests run faster
+            execute += "#" + self.objdump_cmd.format(elf, self.xlen, "ref.dump")
             sig_file = os.path.join(test_dir, self.name[:-1] + ".signature")
             log_file = os.path.join(test_dir, test_name + ".log")
 
@@ -179,8 +180,11 @@ def runTests(self, testList, cgf_file=None, header_file=None):
             execute += coverage_cmd
 
             make.add_target(
-                " \\\n&& ".join(
-                    re.sub(r" +", " ", cmd.strip())
+                "\n\n".join(
+                    "@cd "
+                    + testentry["work_dir"]
+                    + "; "
+                    + re.sub(r" +", " ", cmd.strip())
                     for cmd in execute.split(";")
                     if cmd.strip()
                 )

src/config/configs.yaml

@@ -7,10 +7,10 @@ defaults:
 configs:
   riscv-arch-test:
     MEMORY_X_OFFSET: -9
-    MEMORY_Y_OFFSET: -54
+    MEMORY_Y_OFFSET: -57
     MEMORY_WIDTH: 64
     ROM_ROWS: 18
-    RAM_ROWS: 18
+    RAM_ROWS: 21
     ICACHE_ROWS: 2
 
   micro: