@@ -273,7 +273,7 @@ done_pause_step:
273273 jump SLLI always
274274 jump SRLI always
275275 jump SRAI always
276- jump illegal_instruction always # null + 64 would jump here
276+ jump ILLEGAL_INSTRUCTION always # null + 64 would jump here
277277 jump MLOGSYS always
278278 jump MLOGDRAW always
279279
@@ -332,7 +332,7 @@ default_mtvec_handler:
332332 printflush {{ERROR_OUTPUT}}
333333 jump halt always
334334
335- illegal_instruction :
335+ ILLEGAL_INSTRUCTION :
336336 set mcause 2
337337 # TODO: return faulting instruction bits?
338338 # continue into trap_without_mtval
@@ -1734,7 +1734,7 @@ PRIV:
17341734 jump EBREAK equal imm 1
17351735 jump MRET equal imm 0b001100000010
17361736 jump end_instruction equal imm 0b000100000101 # WFI (no-op, ignore TW bit)
1737- jump illegal_instruction always
1737+ jump ILLEGAL_INSTRUCTION always
17381738
17391739ECALL:
17401740 # 0b1000 (8) = ecall from U-mode
@@ -1748,7 +1748,7 @@ EBREAK:
17481748 jump trap always
17491749
17501750MRET:
1751- jump illegal_instruction lessThan privilege_mode 0b11
1751+ jump ILLEGAL_INSTRUCTION lessThan privilege_mode 0b11
17521752
17531753 # set mstatus.MIE to mstatus.MPIE, set mstatus.MPIE to 1, set privilege_mode to mstatus.MPP, and set mstatus.MPP to U
17541754 op and mstatus.mie csr_mstatus 0b10000000
@@ -1839,15 +1839,15 @@ modify_csr:
18391839 # csr[9:8] encodes the lowest privilege level that can access the CSR
18401840 op shr csr_11_8 imm 8
18411841 op and required_privilege csr_11_8 0b1100000000
1842- jump illegal_instruction lessThan privilege_mode required_privilege
1842+ jump ILLEGAL_INSTRUCTION lessThan privilege_mode required_privilege
18431843
18441844 # disable all supervisor and hypervisor CSRs
1845- jump illegal_instruction equal required_privilege 0b01
1846- jump illegal_instruction equal required_privilege 0b10
1845+ jump ILLEGAL_INSTRUCTION equal required_privilege 0b01
1846+ jump ILLEGAL_INSTRUCTION equal required_privilege 0b10
18471847
18481848 # 0x7b0-0x7bf are only visible to debug mode
18491849 op shr csr_11_4 imm 4
1850- jump illegal_instruction equal csr_11_4 0x7b
1850+ jump ILLEGAL_INSTRUCTION equal csr_11_4 0x7b
18511851
18521852 # read
18531853
@@ -1878,7 +1878,7 @@ modify_csr__conditional_write:
18781878 jump end_instruction_with_rd equal rs1_id 0
18791879
18801880modify_csr__always_write:
1881- jump illegal_instruction equal readonly true
1881+ jump ILLEGAL_INSTRUCTION equal readonly true
18821882
18831883 set @counter modify_csr_write
18841884 # -----------------
@@ -1922,7 +1922,7 @@ modify_csr__read__not_machine:
19221922 jump modify_csr__read__not_timer notEqual tmp 0
19231923
19241924 # mcounteren is hardwired zero, so now that we know it's a timer, trap if we're not in M-mode
1925- jump illegal_instruction lessThan privilege_mode 0b11
1925+ jump ILLEGAL_INSTRUCTION lessThan privilege_mode 0b11
19261926
19271927 jump modify_csr__mcycle equal csr_7_0 0x00
19281928 jump modify_csr__time equal imm 0xc01 # mtime doesn't exist
@@ -2066,7 +2066,7 @@ modify_csr__minstreth:
20662066
20672067MLOGSYS:
20682068 # I-type: rs1, imm=funct12, rd_id
2069- jump illegal_instruction greaterThan imm 3
2069+ jump ILLEGAL_INSTRUCTION greaterThan imm 3
20702070
20712071 # TODO: we could save an instruction if we used B-type instead of I-type
20722072 op mul jump imm 2
@@ -2108,7 +2108,7 @@ MLOGSYS__init_icache__loop:
21082108
21092109MLOGDRAW:
21102110 # I-type: rs1, imm=funct12, rd_id
2111- jump illegal_instruction greaterThan imm 15
2111+ jump ILLEGAL_INSTRUCTION greaterThan imm 15
21122112
21132113 read a1 {{REGISTERS}} 11
21142114 read a2 {{REGISTERS}} 12
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