Move mcycle entirely into controller

Author: object-Object

src/cpu/controller.mlog.jinja

@@ -154,10 +154,10 @@ end_slow_init:
     set csr_mtimeh 0
     set csr_mtimecmp 0
     set csr_mtimecmph 0
-    set csr_mcycle 0
-    set csr_mcycleh 0
     set csr_minstret 0
     set csr_minstreth 0
+    write 0 {{CSRS}} "{{ 'mcycle'|csr }}"
+    write 0 {{CSRS}} "{{ 'mcycleh'|csr }}"
 
     # clear pending/enabled interrupts
     set csr_mip 0
@@ -217,8 +217,6 @@ next_tick:
     read csr_mtimeh prev_proc "csr_mtimeh"
     read csr_mtimecmp prev_proc "csr_mtimecmp"
     read csr_mtimecmph prev_proc "csr_mtimecmph"
-    read csr_mcycle prev_proc "csr_mcycle"
-    read csr_mcycleh prev_proc "csr_mcycleh"
     read csr_minstret prev_proc "csr_minstret"
     read csr_minstreth prev_proc "csr_minstreth"
     read csr_mstatus prev_proc "csr_mstatus"
@@ -265,6 +263,9 @@ end_pause:
     # we define the rate of increase of cycle as "@ipt * ticks"
     # this should be a decent estimation of the number of mlog instructions executed
 
+    read csr_mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
+    read csr_mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
+
     op sub delta_cycles @tick last_cycle_update
     op mul delta_cycles delta_cycles @ipt
 
@@ -276,6 +277,11 @@ end_pause:
 
     op mod csr_mcycle csr_mcycle 0x100000000
 
+    write csr_mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
+    write csr_mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
+    write csr_mcycle {{CSRS}} "{{ 'cycle'|csr }}"
+    write csr_mcycleh {{CSRS}} "{{ 'cycleh'|csr }}"
+
     set last_time_update @time
     set last_cycle_update @tick
 

src/cpu/worker.mlog.jinja

@@ -94,8 +94,6 @@ next_tick_no_check_overrun:
     read csr_mtimeh prev_proc "csr_mtimeh"
     read csr_mtimecmp prev_proc "csr_mtimecmp"
     read csr_mtimecmph prev_proc "csr_mtimecmph"
-    read csr_mcycle prev_proc "csr_mcycle"
-    read csr_mcycleh prev_proc "csr_mcycleh"
     read csr_minstret prev_proc "csr_minstret"
     read csr_minstreth prev_proc "csr_minstreth"
     read csr_mstatus prev_proc "csr_mstatus"
@@ -113,7 +111,7 @@ next_tick_no_check_overrun:
     jump reset notEqual state "running"
 
     set current_tick @tick
-    op sub accumulator @ipt 32
+    op sub accumulator @ipt 30
     jump main notEqual interrupts_pending true
 
 check_interrupts:
@@ -1981,11 +1979,11 @@ modify_csr__read__not_machine:
     # mcounteren is hardwired zero, so now that we know it's a timer, trap if we're not in M-mode
     jump ILLEGAL_OP lessThan privilege_mode 0b11
 
-    jump modify_csr__mcycle equal csr_7_0 0x00
+    jump modify_csr__read__not_timer equal csr_7_0 0x00 # mcycle
     jump modify_csr__time equal imm 0xc01 # mtime doesn't exist
     jump modify_csr__minstret equal csr_7_0 0x02
 
-    jump modify_csr__mcycleh equal csr_7_0 0x80
+    jump modify_csr__read__not_timer equal csr_7_0 0x80 # mcycleh
     jump modify_csr__timeh equal imm 0xc81
     jump modify_csr__minstreth equal csr_7_0 0x82
 
@@ -2080,24 +2078,6 @@ modify_csr__mie:
 
     jump end_instruction_with_rd_and_interrupts always
 
-modify_csr__mcycle:
-    set rd csr_mcycle
-
-    op add modify_csr_write @counter 1
-    set @counter modify_csr_op
-
-    set csr_mcycle new_value
-    jump end_instruction_with_rd_and_interrupts always
-
-modify_csr__mcycleh:
-    set rd csr_mcycleh
-
-    op add modify_csr_write @counter 1
-    set @counter modify_csr_op
-
-    set csr_mcycleh new_value
-    jump end_instruction_with_rd_and_interrupts always
-
 modify_csr__minstret:
     set rd csr_minstret