Rewrite memory system, move RAM to 0x80000000, fall back to slow instruction fetch/decode if not in icache range

Author: object-Object

README.md

@@ -6,13 +6,19 @@ RISC-V processor in Mindustry logic. Requires Mindustry build 149+.
 
 ## Architecture
 
-Memory consists of three sections. Two are directly accessible by code: ROM (rx) and RAM (rw). The third section is an instruction cache, which takes up 4x as much space as the executable portion of memory. The instruction cache is updated at reset and whenever an instruction writes to RAM.
+Physical memory consists of three sections. Two are directly accessible by code: ROM (rx) and RAM (rwx). The third section is an instruction cache which is 4x less dense than main memory. The instruction cache is updated at reset, and whenever an instruction writes to RAM that is covered by the icache. If executing from memory not covered by the icache, the processor manually fetches and decodes the instruction from main memory.
 
-Code begins executing at address `0x4`. Address `0x0` must contain the size of the `.text` section (ie. `__etext`) to tell the processor how much data to decode from ROM; alternatively, it can be `0` to decode the entire ROM.
+Code begins executing at address `0x4`. Address `0x0` must contain the size of the `.text` section (ie. `__etext`) to tell the processor how much data to decode from ROM. If this value is `0`, no ROM data will be decoded.
 
 The main CPU code is generated from `src/main.mlog.jinja` using a custom Jinja-based preprocessor (`python/src/mlogv32/preprocessor`).
 
-### MMIO
+## Memory
+
+| Address      | Value |
+| ------------ | ----- |
+| `0x00000000` | ROM   |
+| `0x80000000` | RAM   |
+| `0xf0000000` | MMIO  |
 
 Addresses `0xf0000000` - `0xffffffff` are reserved for MMIO.
 

coremark/mlogv32/core_portme.mak

@@ -43,7 +43,7 @@ SEPARATE_COMPILE=1
 # You must also define below how to create an object file, and how to link.
 OBJOUT 	= -o
 LFLAGS 	= -T$(PORT_DIR)/../../rust/mlogv32/link.x
-ASFLAGS = --compile
+ASFLAGS = --compile -march=$(RISCV_ARCH)
 OFLAG 	= -o
 COUT 	= -c
 

coremark/mlogv32/entry.s

@@ -2,6 +2,17 @@
 
 .global _start
 _start:
+    # reset mtime/mcycle/minstret
+    li t0, 0xf0000000 # mtime
+    sw zero, 4(t0)
+    sw zero, 0(t0)
+
+    csrw mcycleh, zero
+    csrw mcycle, zero
+
+    csrw minstreth, zero
+    csrw minstret, zero
+
     la t1, _stack_start
     andi sp, t1, -16
     add s0, sp, zero

mod/src/main/kotlin/gay/object/mlogv32/Mlogv32UtilsMod.kt

@@ -65,14 +65,14 @@ class Mlogv32UtilsMod : Mod() {
             file.parent().mkdirs()
 
             val startAddress = if (args.size >= 4) {
-                val result = args[3].toIntOrNull()
+                val result = args[3].toUIntOrNull()
                 if (result == null) {
                     Log.err("Failed to parse start address.")
                     return@register
                 }
                 result
             } else {
-                processor.ramStart
+                ProcessorAccess.RAM_START
             }
 
             val bytes = if (args.size >= 5) {
@@ -83,7 +83,7 @@ class Mlogv32UtilsMod : Mod() {
                 }
                 result
             } else {
-                processor.ramEnd - startAddress
+                (processor.ramEnd - startAddress).toInt()
             }
 
             try {

mod/src/main/kotlin/gay/object/mlogv32/ProcessorAccess.kt

@@ -25,33 +25,30 @@ class ProcessorAccess(
     val memoryX: Int,
     val memoryY: Int,
     val memoryWidth: Int,
-    val romByteOffset: Int,
-    val romProcSize: Int,
-    val romStart: Int,
-    val romEnd: Int,
-    val ramProcSize: Int,
-    val ramStart: Int,
-    val ramEnd: Int,
-    val resetSwitch: SwitchBuild,
+    val romSize: Int,
+    val ramSize: Int,
     val errorOutput: MessageBuild,
+    val resetSwitch: SwitchBuild,
 ) {
-    val romSize = romEnd - romStart
-    val ramSize = ramEnd - ramStart
+    val romEnd = ROM_START + romSize.toUInt()
+    val ramEnd = RAM_START + ramSize.toUInt()
+
+    val ramStartProc = (romEnd / ROM_PROC_BYTES.toUInt()).toInt()
 
     fun flashRom(file: Fi): Int {
         val data = file.readBytes()
         require(data.size.mod(4) == 0) { "Data length must be a multiple of 4 bytes." }
         require(data.size <= romSize) { "Data is too large to fit into the processor's ROM." }
 
-        var address = romStart
+        var address = ROM_START
         val bytes = mutableListOf<Byte>()
         for (byte in data) {
             bytes.add(byte)
 
-            if (bytes.size == romProcSize) {
+            if (bytes.size == ROM_PROC_BYTES) {
                 flashRomProc(address, bytes)
                 bytes.clear()
-                address += romProcSize
+                address += ROM_PROC_BYTES.toUInt()
             }
         }
 
@@ -64,11 +61,11 @@ class ProcessorAccess(
     }
 
     fun dumpRam(file: Fi): Int {
-        dumpRam(file, ramStart, ramSize)
+        dumpRam(file, RAM_START, ramSize)
         return ramSize
     }
 
-    fun dumpRam(file: Fi, startAddress: Int, bytes: Int) {
+    fun dumpRam(file: Fi, startAddress: UInt, bytes: Int) {
         require(bytes > 0) { "Bytes must be positive." }
         require(bytes <= ramSize) { "Bytes must not be greater than the RAM size." }
         require(bytes.mod(4) == 0) { "Bytes must be aligned to 4 bytes." }
@@ -119,25 +116,24 @@ class ProcessorAccess(
         ProcessorAccess.stopServer()
     }
 
-    private fun ramWordsSequence(startAddress: Int = 0) = sequence {
-        require(startAddress in ramStart..<ramEnd) { "Start address must be within RAM." }
-        require(startAddress.mod(4) == 0) { "Start address must be aligned to 4 bytes." }
+    private fun ramWordsSequence(startAddress: UInt) = sequence {
+        require(startAddress in RAM_START..<ramEnd) { "Start address must be within RAM." }
+        require(startAddress.mod(4u) == 0u) { "Start address must be aligned to 4 bytes." }
 
         var address = startAddress
         while (address < ramEnd) {
-            val proc = getRamProc(address) ?: break
-            val startIndex = (address / 4).mod(ramProcSize) + 1
-            for (i in startIndex..ramProcSize) {
-                yield(proc.executor.vars[i]!! to address)
-                address += 4
+            val (proc, startIndex) = getRamProc(address) ?: break
+            for (i in startIndex..<RAM_PROC_VARS) {
+                yield(proc.executor.vars[i + 1]!! to address)
+                address += 4u
             }
         }
     }
 
-    private fun getRomProc(address: Int): LogicBuild? {
-        if (address !in romStart..<romEnd) return null
+    private fun getRomProc(address: UInt): LogicBuild? {
+        if (address !in ROM_START..<romEnd) return null
 
-        val index = address / romProcSize
+        val index = (address / ROM_PROC_BYTES.toUInt()).toInt()
         val x = memoryX + index.mod(memoryWidth)
         val y = memoryY + index / memoryWidth
 
@@ -148,11 +144,11 @@ class ProcessorAccess(
         return proc
     }
 
-    private fun flashRomProc(address: Int, data: Iterable<Byte>) {
+    private fun flashRomProc(address: UInt, data: Iterable<Byte>) {
         val code = buildString {
             append("set v \"")
             for (byte in data) {
-                val char = (byte.toInt() and 0xff) + romByteOffset
+                val char = (byte.toInt() and 0xff) + ROM_BYTE_OFFSET
                 append(char.toChar())
             }
             append("\"\nstop")
@@ -164,22 +160,25 @@ class ProcessorAccess(
         proc.updateCode(code)
     }
 
-    private fun getRamProc(address: Int): LogicBuild? {
-        if (address !in ramStart..<ramEnd) return null
+    private fun getRamProc(address: UInt): Pair<LogicBuild, Int>? {
+        if (address !in RAM_START..<ramEnd) return null
+
+        val ramAddress = address - RAM_START
+        val ramVariable = (ramAddress / 4u).toInt()
 
         // each ROM and RAM proc currently holds the same amount of data, so this doesn't matter too much
-        val index = address / 4 / ramProcSize
+        val index = ramStartProc + ramVariable / RAM_PROC_VARS
         val x = memoryX + index.mod(memoryWidth)
         val y = memoryY + index / memoryWidth
 
         val proc = Vars.world.build(x, y) as? LogicBuild ?: return null
 
         if (
-            proc.executor.vars.size != ramProcSize + 1
+            proc.executor.vars.size != RAM_PROC_VARS + 1
             || proc.executor.vars[1].name != "!!"
         ) return null
 
-        return proc
+        return proc to ramVariable.mod(RAM_PROC_VARS)
     }
 
     private suspend fun runServer(serverSocket: ServerSocket) {
@@ -212,6 +211,13 @@ class ProcessorAccess(
     }
 
     companion object {
+        const val ROM_BYTE_OFFSET = 174
+        const val ROM_PROC_BYTES = 16384
+        const val RAM_PROC_VARS = 4096
+
+        const val ROM_START = 0x00000000u
+        const val RAM_START = 0x80000000u
+
         private var serverThread: Thread? = null
         private var serverJob: Job? = null
         private var serverBuildId: Int? = null
@@ -222,15 +228,10 @@ class ProcessorAccess(
                 memoryX = nonZeroIntVar(build, "MEMORY_X") ?: return null,
                 memoryY = nonZeroIntVar(build, "MEMORY_Y") ?: return null,
                 memoryWidth = positiveIntVar(build, "MEMORY_WIDTH") ?: return null,
-                romByteOffset = nonNegativeIntVar(build, "ROM_BYTE_OFFSET") ?: return null,
-                romProcSize = positiveIntVar(build, "ROM_PROC_SIZE") ?: return null,
-                romStart = nonNegativeIntVar(build, "ROM_START") ?: return null,
-                romEnd = nonNegativeIntVar(build, "ROM_END") ?: return null,
-                ramProcSize = positiveIntVar(build, "RAM_PROC_SIZE") ?: return null,
-                ramStart = nonNegativeIntVar(build, "RAM_START") ?: return null,
-                ramEnd = nonNegativeIntVar(build, "RAM_END") ?: return null,
-                resetSwitch = buildVar<SwitchBuild>(build, "RESET_SWITCH") ?: return null,
-                errorOutput = buildVar<MessageBuild>(build, "ERROR_OUTPUT") ?: return null,
+                romSize = positiveIntVar(build, "ROM_SIZE") ?: return null,
+                ramSize = positiveIntVar(build, "RAM_SIZE") ?: return null,
+                errorOutput = buildVar<MessageBuild>(build, "message1") ?: return null,
+                resetSwitch = buildVar<SwitchBuild>(build, "switch1") ?: return null,
             )
         }
 
@@ -250,18 +251,18 @@ private fun nonZeroIntVar(build: LogicBuild, name: String): Int? =
         ?.numi()
         ?.takeIf { it != 0 }
 
-private fun nonNegativeIntVar(build: LogicBuild, name: String): Int? =
-    build.executor.optionalVar(name)
-        ?.takeIf { !it.isobj }
-        ?.numi()
-        ?.takeIf { it >= 0 }
-
 private fun positiveIntVar(build: LogicBuild, name: String): Int? =
     nonZeroIntVar(build, name)
         ?.takeIf { it > 0 }
 
 private inline fun <reified T : Building> buildVar(build: LogicBuild, name: String): T? =
-    build.executor.optionalVar(name)?.obj() as? T
+    (build.executor.optionalVar(name)?.obj() ?: linkedBuild(build, name)) as? T
+
+// why
+private fun linkedBuild(build: LogicBuild, name: String) =
+    build.links
+        .firstOrNull { it.active && it.valid && it.name == name }
+        ?.let { Vars.world.build(it.x, it.y) }
 
 @Serializable
 sealed class Request {
@@ -296,15 +297,15 @@ data class FlashRequest(val path: String) : Request() {
 @SerialName("dump")
 data class DumpRequest(
     val path: String,
-    val address: Int?,
+    val address: UInt?,
     val bytes: Int?,
 ) : Request() {
     override suspend fun handle(processor: ProcessorAccess) = runOnMainThread {
         val file = Core.files.absolute(path)
         file.parent().mkdirs()
 
-        val address = address ?: processor.ramStart
-        val bytes = bytes ?: (processor.ramEnd - address)
+        val address = address ?: ProcessorAccess.RAM_START
+        val bytes = bytes ?: (processor.ramEnd - address).toInt()
 
         processor.dumpRam(file, address, bytes)
         SuccessResponse("Successfully dumped $bytes bytes from RAM to $file.")

riscof/mlogv32/env/link.ld

@@ -2,8 +2,9 @@ OUTPUT_ARCH( "riscv" )
 ENTRY(rvtest_entry_point)
 
 MEMORY {
-    ROM (rx) : ORIGIN = 0, LENGTH = 0x200000
-    RAM (rw) : ORIGIN = 0x200000, LENGTH = 0x200000
+    ROM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x200000
+    RAM  (rwx) : ORIGIN = 0x80000000, LENGTH = 0x200000
+    MMIO (rw)  : ORIGIN = 0xf0000000, LENGTH = 16
 }
 
 SECTIONS

rust/mlogv32/link.x

@@ -12,16 +12,17 @@ MEMORY {
     0x3000000 = 128*24 * 4096*4
     0x1000000 = 128*8 * 4096*4
     */
-    rom (rx) : ORIGIN = 0, LENGTH = 0x200000
-    ram (rw) : ORIGIN = 0x200000, LENGTH = 0x200000
+    ROM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x200000
+    RAM  (rwx) : ORIGIN = 0x80000000, LENGTH = 0x200000
+    MMIO (rw)  : ORIGIN = 0xf0000000, LENGTH = 16
 }
 
-REGION_ALIAS("REGION_TEXT",   rom);
-REGION_ALIAS("REGION_RODATA", rom);
-REGION_ALIAS("REGION_DATA",   ram);
-REGION_ALIAS("REGION_BSS",    ram);
-REGION_ALIAS("REGION_HEAP",   ram);
-REGION_ALIAS("REGION_STACK",  ram);
+REGION_ALIAS("REGION_TEXT",   ROM);
+REGION_ALIAS("REGION_RODATA", ROM);
+REGION_ALIAS("REGION_DATA",   RAM);
+REGION_ALIAS("REGION_BSS",    RAM);
+REGION_ALIAS("REGION_HEAP",   RAM);
+REGION_ALIAS("REGION_STACK",  RAM);
 
 PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
 PROVIDE(_stack_size = 4K);

src/config.mlog

@@ -1,8 +1,16 @@
     # per-world config options
-    set IPT 500000
-    set MEMORY_X_OFFSET -3  # x offset from cpu of bottom left memory proc
-    set MEMORY_Y_OFFSET -130  # y offset from cpu of bottom left memory proc
-    set MEMORY_WIDTH 128  # physical width of the memory procs
-    set ROM_SIZE 0x1000000  # total rom size in bytes (rx); also total decoded size in variables
-    set RAM_SIZE 0x3000000  # total ram size in bytes (rw)
+    set TARGET_IPT 500000
+
+    set MEMORY_X_OFFSET -11  # x offset from this proc to bottom left memory proc
+    set MEMORY_Y_OFFSET -26  # y offset from this proc to bottom left memory proc
+    set MEMORY_WIDTH 32  # physical width of the memory procs
+
+    set ROM_SIZE    0x200000  # ROM size in bytes (rx)
+    set RAM_SIZE    0x200000  # RAM size in bytes (rwx)
+    set ICACHE_SIZE 0x200000  # icache size in variables, or bytes of memory it can represent; 4x less dense than ROM/RAM
+
+    # computed values
+    op add MEMORY_X @thisx MEMORY_X_OFFSET
+    op add MEMORY_Y @thisy MEMORY_Y_OFFSET
+
     stop